drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42
  43 /* Template header */
  44 struct qlc_83xx_reset_hdr {
  45 #if defined(__LITTLE_ENDIAN)
  46         u16     version;
  47         u16     signature;
  48         u16     size;
  49         u16     entries;
  50         u16     hdr_size;
  51         u16     checksum;
  52         u16     init_offset;
  53         u16     start_offset;
  54 #elif defined(__BIG_ENDIAN)
  55         u16     signature;
  56         u16     version;
  57         u16     entries;
  58         u16     size;
  59         u16     checksum;
  60         u16     hdr_size;
  61         u16     start_offset;
  62         u16     init_offset;
  63 #endif
  64 } __packed;
  65
  66 /* Command entry header. */
  67 struct qlc_83xx_entry_hdr {
  68 #if defined(__LITTLE_ENDIAN)
  69         u16     cmd;
  70         u16     size;
  71         u16     count;
  72         u16     delay;
  73 #elif defined(__BIG_ENDIAN)
  74         u16     size;
  75         u16     cmd;
  76         u16     delay;
  77         u16     count;
  78 #endif
  79 } __packed;
  80
  81 /* Generic poll command */
  82 struct qlc_83xx_poll {
  83         u32     mask;
  84         u32     status;
  85 } __packed;
  86
  87 /* Read modify write command */
  88 struct qlc_83xx_rmw {
  89         u32     mask;
  90         u32     xor_value;
  91         u32     or_value;
  92 #if defined(__LITTLE_ENDIAN)
  93         u8      shl;
  94         u8      shr;
  95         u8      index_a;
  96         u8      rsvd;
  97 #elif defined(__BIG_ENDIAN)
  98         u8      rsvd;
  99         u8      index_a;
 100         u8      shr;
 101         u8      shl;
 102 #endif
 103 } __packed;
 104
 105 /* Generic command with 2 DWORD */
 106 struct qlc_83xx_entry {
 107         u32 arg1;
 108         u32 arg2;
 109 } __packed;
 110
 111 /* Generic command with 4 DWORD */
 112 struct qlc_83xx_quad_entry {
 113         u32 dr_addr;
 114         u32 dr_value;
 115         u32 ar_addr;
 116         u32 ar_value;
 117 } __packed;
 118 static const char *const qlc_83xx_idc_states[] = {
 119         "Unknown",
 120         "Cold",
 121         "Init",
 122         "Ready",
 123         "Need Reset",
 124         "Need Quiesce",
 125         "Failed",
 126         "Quiesce"
 127 };
 128
 129 static int
 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 131 {
 132         u32 val;
 133
 134         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 135         if ((val & 0xFFFF))
 136                 return 1;
 137         else
 138                 return 0;
 139 }
 140
 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 142 {
 143         u32 cur, prev;
 144         cur = adapter->ahw->idc.curr_state;
 145         prev = adapter->ahw->idc.prev_state;
 146
 147         dev_info(&adapter->pdev->dev,
 148                  "current state  = %s,  prev state = %s\n",
 149                  adapter->ahw->idc.name[cur],
 150                  adapter->ahw->idc.name[prev]);
 151 }
 152
 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 154                                             u8 mode, int lock)
 155 {
 156         u32 val;
 157         int seconds;
 158
 159         if (lock) {
 160                 if (qlcnic_83xx_lock_driver(adapter))
 161                         return -EBUSY;
 162         }
 163
 164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 165         val |= (adapter->portnum & 0xf);
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * qlcnic_83xx_idc_detach_driver
 390  *
 391  * @adapter: adapter structure
 392  * Detach net interface, stop TX and cleanup resources before the HW reset.
 393  * Returns: None
 394  *
 395  **/
 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 397 {
 398         int i;
 399         struct net_device *netdev = adapter->netdev;
 400
 401         netif_device_detach(netdev);
 402         qlcnic_83xx_detach_mailbox_work(adapter);
 403
 404         /* Disable mailbox interrupt */
 405         qlcnic_83xx_disable_mbx_intr(adapter);
 406         qlcnic_down(adapter, netdev);
 407         for (i = 0; i < adapter->ahw->num_msix; i++) {
 408                 adapter->ahw->intr_tbl[i].id = i;
 409                 adapter->ahw->intr_tbl[i].enabled = 0;
 410                 adapter->ahw->intr_tbl[i].src = 0;
 411         }
 412
 413         if (qlcnic_sriov_pf_check(adapter))
 414                 qlcnic_sriov_pf_reset(adapter);
 415 }
 416
 417 /**
 418  * qlcnic_83xx_idc_attach_driver
 419  *
 420  * @adapter: adapter structure
 421  *
 422  * Re-attach and re-enable net interface
 423  * Returns: None
 424  *
 425  **/
 426 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 427 {
 428         struct net_device *netdev = adapter->netdev;
 429
 430         if (netif_running(netdev)) {
 431                 if (qlcnic_up(adapter, netdev))
 432                         goto done;
 433                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 434         }
 435 done:
 436         netif_device_attach(netdev);
 437 }
 438
 439 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 440                                               int lock)
 441 {
 442         if (lock) {
 443                 if (qlcnic_83xx_lock_driver(adapter))
 444                         return -EBUSY;
 445         }
 446
 447         qlcnic_83xx_idc_clear_registers(adapter, 0);
 448         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 449         if (lock)
 450                 qlcnic_83xx_unlock_driver(adapter);
 451
 452         qlcnic_83xx_idc_log_state_history(adapter);
 453         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 454
 455         return 0;
 456 }
 457
 458 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 459                                             int lock)
 460 {
 461         if (lock) {
 462                 if (qlcnic_83xx_lock_driver(adapter))
 463                         return -EBUSY;
 464         }
 465
 466         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 467
 468         if (lock)
 469                 qlcnic_83xx_unlock_driver(adapter);
 470
 471         return 0;
 472 }
 473
 474 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 475                                               int lock)
 476 {
 477         if (lock) {
 478                 if (qlcnic_83xx_lock_driver(adapter))
 479                         return -EBUSY;
 480         }
 481
 482         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 483                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 484
 485         if (lock)
 486                 qlcnic_83xx_unlock_driver(adapter);
 487
 488         return 0;
 489 }
 490
 491 static int
 492 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 493 {
 494         if (lock) {
 495                 if (qlcnic_83xx_lock_driver(adapter))
 496                         return -EBUSY;
 497         }
 498
 499         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 500                QLC_83XX_IDC_DEV_NEED_RESET);
 501
 502         if (lock)
 503                 qlcnic_83xx_unlock_driver(adapter);
 504
 505         return 0;
 506 }
 507
 508 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 509                                              int lock)
 510 {
 511         if (lock) {
 512                 if (qlcnic_83xx_lock_driver(adapter))
 513                         return -EBUSY;
 514         }
 515
 516         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 517         if (lock)
 518                 qlcnic_83xx_unlock_driver(adapter);
 519
 520         return 0;
 521 }
 522
 523 /**
 524  * qlcnic_83xx_idc_find_reset_owner_id
 525  *
 526  * @adapter: adapter structure
 527  *
 528  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 529  * Within the same class, function with lowest PCI ID assumes ownership
 530  *
 531  * Returns: reset owner id or failure indication (-EIO)
 532  *
 533  **/
 534 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 535 {
 536         u32 reg, reg1, reg2, i, j, owner, class;
 537
 538         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 539         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 540         owner = QLCNIC_TYPE_NIC;
 541         i = 0;
 542         j = 0;
 543         reg = reg1;
 544
 545         do {
 546                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 547                 if (class == owner)
 548                         break;
 549                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 550                         reg = reg2;
 551                         j = 0;
 552                 } else {
 553                         j++;
 554                 }
 555
 556                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 557                         if (owner == QLCNIC_TYPE_NIC)
 558                                 owner = QLCNIC_TYPE_ISCSI;
 559                         else if (owner == QLCNIC_TYPE_ISCSI)
 560                                 owner = QLCNIC_TYPE_FCOE;
 561                         else if (owner == QLCNIC_TYPE_FCOE)
 562                                 return -EIO;
 563                         reg = reg1;
 564                         j = 0;
 565                         i = 0;
 566                 }
 567         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 568
 569         return i;
 570 }
 571
 572 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 573 {
 574         int ret = 0;
 575
 576         ret = qlcnic_83xx_restart_hw(adapter);
 577
 578         if (ret) {
 579                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 580         } else {
 581                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 582                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 583         }
 584
 585         return ret;
 586 }
 587
 588 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 589 {
 590         u32 status;
 591
 592         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 593
 594         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 595                 dev_err(&adapter->pdev->dev,
 596                         "peg halt status1=0x%x\n", status);
 597                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 598                         dev_err(&adapter->pdev->dev,
 599                                 "On board active cooling fan failed. "
 600                                 "Device has been halted.\n");
 601                         dev_err(&adapter->pdev->dev,
 602                                 "Replace the adapter.\n");
 603                         return -EIO;
 604                 }
 605         }
 606
 607         return 0;
 608 }
 609
 610 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 611 {
 612         int err;
 613
 614         qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
 615         qlcnic_83xx_enable_mbx_interrupt(adapter);
 616
 617         /* register for NIC IDC AEN Events */
 618         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 619
 620         err = qlcnic_sriov_pf_reinit(adapter);
 621         if (err)
 622                 return err;
 623
 624         qlcnic_83xx_enable_mbx_interrupt(adapter);
 625
 626         if (qlcnic_83xx_configure_opmode(adapter)) {
 627                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 628                 return -EIO;
 629         }
 630
 631         if (adapter->nic_ops->init_driver(adapter)) {
 632                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 633                 return -EIO;
 634         }
 635
 636         if (adapter->portnum == 0)
 637                 qlcnic_set_drv_version(adapter);
 638
 639         qlcnic_dcb_get_info(adapter);
 640         qlcnic_83xx_idc_attach_driver(adapter);
 641
 642         return 0;
 643 }
 644
 645 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 646 {
 647         struct qlcnic_hardware_context *ahw = adapter->ahw;
 648
 649         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 650         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 651         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 652
 653         ahw->idc.quiesce_req = 0;
 654         ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 655         ahw->idc.err_code = 0;
 656         ahw->idc.collect_dump = 0;
 657         ahw->reset_context = 0;
 658         adapter->tx_timeo_cnt = 0;
 659         ahw->idc.delay_reset = 0;
 660
 661         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 662 }
 663
 664 /**
 665  * qlcnic_83xx_idc_ready_state_entry
 666  *
 667  * @adapter: adapter structure
 668  *
 669  * Perform ready state initialization, this routine will get invoked only
 670  * once from READY state.
 671  *
 672  * Returns: Error code or Success(0)
 673  *
 674  **/
 675 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 676 {
 677         struct qlcnic_hardware_context *ahw = adapter->ahw;
 678
 679         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 680                 qlcnic_83xx_idc_update_idc_params(adapter);
 681                 /* Re-attach the device if required */
 682                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 683                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 684                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 685                                 return -EIO;
 686                 }
 687         }
 688
 689         return 0;
 690 }
 691
 692 /**
 693  * qlcnic_83xx_idc_vnic_pf_entry
 694  *
 695  * @adapter: adapter structure
 696  *
 697  * Ensure vNIC mode privileged function starts only after vNIC mode is
 698  * enabled by management function.
 699  * If vNIC mode is ready, start initialization.
 700  *
 701  * Returns: -EIO or 0
 702  *
 703  **/
 704 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 705 {
 706         u32 state;
 707         struct qlcnic_hardware_context *ahw = adapter->ahw;
 708
 709         /* Privileged function waits till mgmt function enables VNIC mode */
 710         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 711         if (state != QLCNIC_DEV_NPAR_OPER) {
 712                 if (!ahw->idc.vnic_wait_limit--) {
 713                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 714                         return -EIO;
 715                 }
 716                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 717                 return -EIO;
 718
 719         } else {
 720                 /* Perform one time initialization from ready state */
 721                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 722                         qlcnic_83xx_idc_update_idc_params(adapter);
 723
 724                         /* If the previous state is UNKNOWN, device will be
 725                            already attached properly by Init routine*/
 726                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 727                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 728                                         return -EIO;
 729                         }
 730                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 731                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 732                 }
 733         }
 734
 735         return 0;
 736 }
 737
 738 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 739 {
 740         adapter->ahw->idc.err_code = -EIO;
 741         dev_err(&adapter->pdev->dev,
 742                 "%s: Device in unknown state\n", __func__);
 743         return 0;
 744 }
 745
 746 /**
 747  * qlcnic_83xx_idc_cold_state
 748  *
 749  * @adapter: adapter structure
 750  *
 751  * If HW is up and running device will enter READY state.
 752  * If firmware image from host needs to be loaded, device is
 753  * forced to start with the file firmware image.
 754  *
 755  * Returns: Error code or Success(0)
 756  *
 757  **/
 758 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 759 {
 760         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 761         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 762
 763         if (qlcnic_load_fw_file) {
 764                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 765         } else {
 766                 if (qlcnic_83xx_check_hw_status(adapter)) {
 767                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 768                         return -EIO;
 769                 } else {
 770                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 771                 }
 772         }
 773         return 0;
 774 }
 775
 776 /**
 777  * qlcnic_83xx_idc_init_state
 778  *
 779  * @adapter: adapter structure
 780  *
 781  * Reset owner will restart the device from this state.
 782  * Device will enter failed state if it remains
 783  * in this state for more than DEV_INIT time limit.
 784  *
 785  * Returns: Error code or Success(0)
 786  *
 787  **/
 788 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 789 {
 790         int timeout, ret = 0;
 791         u32 owner;
 792
 793         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 794         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 795                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 796                 if (adapter->ahw->pci_func == owner)
 797                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 798         } else {
 799                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 800         }
 801
 802         return ret;
 803 }
 804
 805 /**
 806  * qlcnic_83xx_idc_ready_state
 807  *
 808  * @adapter: adapter structure
 809  *
 810  * Perform IDC protocol specicifed actions after monitoring device state and
 811  * events.
 812  *
 813  * Returns: Error code or Success(0)
 814  *
 815  **/
 816 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 817 {
 818         struct qlcnic_hardware_context *ahw = adapter->ahw;
 819         struct qlcnic_mailbox *mbx = ahw->mailbox;
 820         int ret = 0;
 821         u32 val;
 822
 823         /* Perform NIC configuration based ready state entry actions */
 824         if (ahw->idc.state_entry(adapter))
 825                 return -EIO;
 826
 827         if (qlcnic_check_temp(adapter)) {
 828                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 829                         qlcnic_83xx_idc_check_fan_failure(adapter);
 830                         dev_err(&adapter->pdev->dev,
 831                                 "Error: device temperature %d above limits\n",
 832                                 adapter->ahw->temp);
 833                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 834                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 835                         qlcnic_83xx_idc_detach_driver(adapter);
 836                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 837                         return -EIO;
 838                 }
 839         }
 840
 841         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 842         ret = qlcnic_83xx_check_heartbeat(adapter);
 843         if (ret) {
 844                 adapter->flags |= QLCNIC_FW_HANG;
 845                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 846                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 847                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 848                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 849                 }
 850                 return -EIO;
 851         }
 852
 853         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 854                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 855
 856                 /* Move to need reset state and prepare for reset */
 857                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 858                 return ret;
 859         }
 860
 861         /* Check for soft reset request */
 862         if (ahw->reset_context &&
 863             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 864                 adapter->ahw->reset_context = 0;
 865                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 866                 return ret;
 867         }
 868
 869         /* Move to need quiesce state if requested */
 870         if (adapter->ahw->idc.quiesce_req) {
 871                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 872                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 873                 return ret;
 874         }
 875
 876         return ret;
 877 }
 878
 879 /**
 880  * qlcnic_83xx_idc_need_reset_state
 881  *
 882  * @adapter: adapter structure
 883  *
 884  * Device will remain in this state until:
 885  *      Reset request ACK's are recieved from all the functions
 886  *      Wait time exceeds max time limit
 887  *
 888  * Returns: Error code or Success(0)
 889  *
 890  **/
 891 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 892 {
 893         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 894         int ret = 0;
 895
 896         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 897                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 898                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 899                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 900                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 901                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 902
 903                 if (qlcnic_check_diag_status(adapter)) {
 904                         dev_info(&adapter->pdev->dev,
 905                                  "%s: Wait for diag completion\n", __func__);
 906                         adapter->ahw->idc.delay_reset = 1;
 907                         return 0;
 908                 } else {
 909                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 910                         qlcnic_83xx_idc_detach_driver(adapter);
 911                 }
 912         }
 913
 914         if (qlcnic_check_diag_status(adapter)) {
 915                 dev_info(&adapter->pdev->dev,
 916                          "%s: Wait for diag completion\n", __func__);
 917                 return  -1;
 918         } else {
 919                 if (adapter->ahw->idc.delay_reset) {
 920                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 921                         qlcnic_83xx_idc_detach_driver(adapter);
 922                         adapter->ahw->idc.delay_reset = 0;
 923                 }
 924
 925                 /* Check for ACK from other functions */
 926                 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 927                 if (ret) {
 928                         dev_info(&adapter->pdev->dev,
 929                                  "%s: Waiting for reset ACK\n", __func__);
 930                         return -1;
 931                 }
 932         }
 933
 934         /* Transit to INIT state and restart the HW */
 935         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 936
 937         return ret;
 938 }
 939
 940 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 941 {
 942         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 943         return 0;
 944 }
 945
 946 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 947 {
 948         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 949         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 950         adapter->ahw->idc.err_code = -EIO;
 951
 952         return 0;
 953 }
 954
 955 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 956 {
 957         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 958         return 0;
 959 }
 960
 961 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 962                                                 u32 state)
 963 {
 964         u32 cur, prev, next;
 965
 966         cur = adapter->ahw->idc.curr_state;
 967         prev = adapter->ahw->idc.prev_state;
 968         next = state;
 969
 970         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 971             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 972                 dev_err(&adapter->pdev->dev,
 973                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 974                         __func__, cur, prev, state);
 975                 return 1;
 976         }
 977
 978         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 979             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 980                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 981                     (next != QLC_83XX_IDC_DEV_READY)) {
 982                         dev_err(&adapter->pdev->dev,
 983                                 "%s: failed, cur %d prev %d next %d\n",
 984                                 __func__, cur, prev, next);
 985                         return 1;
 986                 }
 987         }
 988
 989         if (next == QLC_83XX_IDC_DEV_INIT) {
 990                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 991                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 992                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 993                         dev_err(&adapter->pdev->dev,
 994                                 "%s: failed, cur %d prev %d next %d\n",
 995                                 __func__, cur, prev, next);
 996                         return 1;
 997                 }
 998         }
 999
1000         return 0;
1001 }
1002
1003 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1004 {
1005         if (adapter->fhash.fnum)
1006                 qlcnic_prune_lb_filters(adapter);
1007 }
1008
1009 /**
1010  * qlcnic_83xx_idc_poll_dev_state
1011  *
1012  * @work: kernel work queue structure used to schedule the function
1013  *
1014  * Poll device state periodically and perform state specific
1015  * actions defined by Inter Driver Communication (IDC) protocol.
1016  *
1017  * Returns: None
1018  *
1019  **/
1020 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1021 {
1022         struct qlcnic_adapter *adapter;
1023         u32 state;
1024
1025         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1026         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1027
1028         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1029                 qlcnic_83xx_idc_log_state_history(adapter);
1030                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1031         } else {
1032                 adapter->ahw->idc.curr_state = state;
1033         }
1034
1035         switch (adapter->ahw->idc.curr_state) {
1036         case QLC_83XX_IDC_DEV_READY:
1037                 qlcnic_83xx_idc_ready_state(adapter);
1038                 break;
1039         case QLC_83XX_IDC_DEV_NEED_RESET:
1040                 qlcnic_83xx_idc_need_reset_state(adapter);
1041                 break;
1042         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1043                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1044                 break;
1045         case QLC_83XX_IDC_DEV_FAILED:
1046                 qlcnic_83xx_idc_failed_state(adapter);
1047                 return;
1048         case QLC_83XX_IDC_DEV_INIT:
1049                 qlcnic_83xx_idc_init_state(adapter);
1050                 break;
1051         case QLC_83XX_IDC_DEV_QUISCENT:
1052                 qlcnic_83xx_idc_quiesce_state(adapter);
1053                 break;
1054         default:
1055                 qlcnic_83xx_idc_unknown_state(adapter);
1056                 return;
1057         }
1058         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1059         qlcnic_83xx_periodic_tasks(adapter);
1060
1061         /* Re-schedule the function */
1062         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1063                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1064                                      adapter->ahw->idc.delay);
1065 }
1066
1067 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1068 {
1069         u32 idc_params, val;
1070
1071         if (qlcnic_83xx_lockless_flash_read32(adapter,
1072                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1073                                               (u8 *)&idc_params, 1)) {
1074                 dev_info(&adapter->pdev->dev,
1075                          "%s:failed to get IDC params from flash\n", __func__);
1076                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1077                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1078         } else {
1079                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1080                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1081         }
1082
1083         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1084         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1085         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1086         adapter->ahw->idc.err_code = 0;
1087         adapter->ahw->idc.collect_dump = 0;
1088         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1089
1090         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1091         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1092
1093         /* Check if reset recovery is disabled */
1094         if (!qlcnic_auto_fw_reset) {
1095                 /* Propagate do not reset request to other functions */
1096                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1097                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1098                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1099         }
1100 }
1101
1102 static int
1103 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1104 {
1105         u32 state, val;
1106
1107         if (qlcnic_83xx_lock_driver(adapter))
1108                 return -EIO;
1109
1110         /* Clear driver lock register */
1111         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1112         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1113                 qlcnic_83xx_unlock_driver(adapter);
1114                 return -EIO;
1115         }
1116
1117         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1118         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1119                 qlcnic_83xx_unlock_driver(adapter);
1120                 return -EIO;
1121         }
1122
1123         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1124                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1125                        QLC_83XX_IDC_DEV_COLD);
1126                 state = QLC_83XX_IDC_DEV_COLD;
1127         }
1128
1129         adapter->ahw->idc.curr_state = state;
1130         /* First to load function should cold boot the device */
1131         if (state == QLC_83XX_IDC_DEV_COLD)
1132                 qlcnic_83xx_idc_cold_state_handler(adapter);
1133
1134         /* Check if reset recovery is enabled */
1135         if (qlcnic_auto_fw_reset) {
1136                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1137                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1138                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1139         }
1140
1141         qlcnic_83xx_unlock_driver(adapter);
1142
1143         return 0;
1144 }
1145
1146 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1147 {
1148         int ret = -EIO;
1149
1150         qlcnic_83xx_setup_idc_parameters(adapter);
1151
1152         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1153                 return ret;
1154
1155         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1156                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1157                         return -EIO;
1158         } else {
1159                 if (qlcnic_83xx_idc_check_major_version(adapter))
1160                         return -EIO;
1161         }
1162
1163         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1164
1165         return 0;
1166 }
1167
1168 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1169 {
1170         int id;
1171         u32 val;
1172
1173         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1174                 usleep_range(10000, 11000);
1175
1176         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1177         id = id & 0xFF;
1178
1179         if (id == adapter->portnum) {
1180                 dev_err(&adapter->pdev->dev,
1181                         "%s: wait for lock recovery.. %d\n", __func__, id);
1182                 msleep(20);
1183                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1184                 id = id & 0xFF;
1185         }
1186
1187         /* Clear driver presence bit */
1188         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1189         val = val & ~(1 << adapter->portnum);
1190         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1191         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1192         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1193
1194         cancel_delayed_work_sync(&adapter->fw_work);
1195 }
1196
1197 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1198 {
1199         u32 val;
1200
1201         if (qlcnic_sriov_vf_check(adapter))
1202                 return;
1203
1204         if (qlcnic_83xx_lock_driver(adapter)) {
1205                 dev_err(&adapter->pdev->dev,
1206                         "%s:failed, please retry\n", __func__);
1207                 return;
1208         }
1209
1210         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1211         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1212             !qlcnic_auto_fw_reset) {
1213                 dev_err(&adapter->pdev->dev,
1214                         "%s:failed, device in non reset mode\n", __func__);
1215                 qlcnic_83xx_unlock_driver(adapter);
1216                 return;
1217         }
1218
1219         if (key == QLCNIC_FORCE_FW_RESET) {
1220                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1221                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1222                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1223         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1224                 adapter->ahw->idc.collect_dump = 1;
1225         }
1226
1227         qlcnic_83xx_unlock_driver(adapter);
1228         return;
1229 }
1230
1231 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1232 {
1233         u8 *p_cache;
1234         u32 src, size;
1235         u64 dest;
1236         int ret = -EIO;
1237
1238         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1239         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1240         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1241
1242         /* alignment check */
1243         if (size & 0xF)
1244                 size = (size + 16) & ~0xF;
1245
1246         p_cache = kzalloc(size, GFP_KERNEL);
1247         if (p_cache == NULL)
1248                 return -ENOMEM;
1249
1250         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1251                                                 size / sizeof(u32));
1252         if (ret) {
1253                 kfree(p_cache);
1254                 return ret;
1255         }
1256         /* 16 byte write to MS memory */
1257         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1258                                           size / 16);
1259         if (ret) {
1260                 kfree(p_cache);
1261                 return ret;
1262         }
1263         kfree(p_cache);
1264
1265         return ret;
1266 }
1267
1268 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1269 {
1270         u32 dest, *p_cache;
1271         u64 addr;
1272         u8 data[16];
1273         size_t size;
1274         int i, ret = -EIO;
1275
1276         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1277         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1278         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1279         addr = (u64)dest;
1280
1281         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1282                                           (u32 *)p_cache, size / 16);
1283         if (ret) {
1284                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1285                 release_firmware(adapter->ahw->fw_info.fw);
1286                 adapter->ahw->fw_info.fw = NULL;
1287                 return -EIO;
1288         }
1289
1290         /* alignment check */
1291         if (adapter->ahw->fw_info.fw->size & 0xF) {
1292                 addr = dest + size;
1293                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1294                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1295                 for (; i < 16; i++)
1296                         data[i] = 0;
1297                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1298                                                   (u32 *)data, 1);
1299                 if (ret) {
1300                         dev_err(&adapter->pdev->dev,
1301                                 "MS memory write failed\n");
1302                         release_firmware(adapter->ahw->fw_info.fw);
1303                         adapter->ahw->fw_info.fw = NULL;
1304                         return -EIO;
1305                 }
1306         }
1307         release_firmware(adapter->ahw->fw_info.fw);
1308         adapter->ahw->fw_info.fw = NULL;
1309
1310         return 0;
1311 }
1312
1313 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1314 {
1315         int i, j;
1316         u32 val = 0, val1 = 0, reg = 0;
1317         int err = 0;
1318
1319         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG, &err);
1320         if (err == -EIO)
1321                 return;
1322         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1323
1324         for (j = 0; j < 2; j++) {
1325                 if (j == 0) {
1326                         dev_info(&adapter->pdev->dev,
1327                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1328                         reg = QLC_83XX_PORT0_THRESHOLD;
1329                 } else if (j == 1) {
1330                         dev_info(&adapter->pdev->dev,
1331                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1332                         reg = QLC_83XX_PORT1_THRESHOLD;
1333                 }
1334                 for (i = 0; i < 8; i++) {
1335                         val = QLCRD32(adapter, reg + (i * 0x4), &err);
1336                         if (err == -EIO)
1337                                 return;
1338                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1339                 }
1340                 dev_info(&adapter->pdev->dev, "\n");
1341         }
1342
1343         for (j = 0; j < 2; j++) {
1344                 if (j == 0) {
1345                         dev_info(&adapter->pdev->dev,
1346                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1347                         reg = QLC_83XX_PORT0_TC_MC_REG;
1348                 } else if (j == 1) {
1349                         dev_info(&adapter->pdev->dev,
1350                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1351                         reg = QLC_83XX_PORT1_TC_MC_REG;
1352                 }
1353                 for (i = 0; i < 4; i++) {
1354                         val = QLCRD32(adapter, reg + (i * 0x4), &err);
1355                         if (err == -EIO)
1356                                 return;
1357                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1358                 }
1359                 dev_info(&adapter->pdev->dev, "\n");
1360         }
1361
1362         for (j = 0; j < 2; j++) {
1363                 if (j == 0) {
1364                         dev_info(&adapter->pdev->dev,
1365                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1366                         reg = QLC_83XX_PORT0_TC_STATS;
1367                 } else if (j == 1) {
1368                         dev_info(&adapter->pdev->dev,
1369                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1370                         reg = QLC_83XX_PORT1_TC_STATS;
1371                 }
1372                 for (i = 7; i >= 0; i--) {
1373                         val = QLCRD32(adapter, reg, &err);
1374                         if (err == -EIO)
1375                                 return;
1376                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1377                         QLCWR32(adapter, reg, (val | (i << 29)));
1378                         val = QLCRD32(adapter, reg, &err);
1379                         if (err == -EIO)
1380                                 return;
1381                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1382                 }
1383                 dev_info(&adapter->pdev->dev, "\n");
1384         }
1385
1386         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, &err);
1387         if (err == -EIO)
1388                 return;
1389         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, &err);
1390         if (err == -EIO)
1391                 return;
1392         dev_info(&adapter->pdev->dev,
1393                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1394                  val, val1);
1395 }
1396
1397
1398 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1399 {
1400         u32 reg = 0, i, j;
1401
1402         if (qlcnic_83xx_lock_driver(adapter)) {
1403                 dev_err(&adapter->pdev->dev,
1404                         "%s:failed to acquire driver lock\n", __func__);
1405                 return;
1406         }
1407
1408         qlcnic_83xx_dump_pause_control_regs(adapter);
1409         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1410
1411         for (j = 0; j < 2; j++) {
1412                 if (j == 0)
1413                         reg = QLC_83XX_PORT0_THRESHOLD;
1414                 else if (j == 1)
1415                         reg = QLC_83XX_PORT1_THRESHOLD;
1416
1417                 for (i = 0; i < 8; i++)
1418                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1419         }
1420
1421         for (j = 0; j < 2; j++) {
1422                 if (j == 0)
1423                         reg = QLC_83XX_PORT0_TC_MC_REG;
1424                 else if (j == 1)
1425                         reg = QLC_83XX_PORT1_TC_MC_REG;
1426
1427                 for (i = 0; i < 4; i++)
1428                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1429         }
1430
1431         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1432         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1433         dev_info(&adapter->pdev->dev,
1434                  "Disabled pause frames successfully on all ports\n");
1435         qlcnic_83xx_unlock_driver(adapter);
1436 }
1437
1438 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1439 {
1440         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1441         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1442         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1443         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1444         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1445         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1446         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1447         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1448         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1449 }
1450
1451 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1452 {
1453         u32 heartbeat, peg_status;
1454         int retries, ret = -EIO, err = 0;
1455
1456         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1457         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1458                                                QLCNIC_PEG_ALIVE_COUNTER);
1459
1460         do {
1461                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1462                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1463                                                 QLCNIC_PEG_ALIVE_COUNTER);
1464                 if (heartbeat != p_dev->heartbeat) {
1465                         ret = QLCNIC_RCODE_SUCCESS;
1466                         break;
1467                 }
1468         } while (--retries);
1469
1470         if (ret) {
1471                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1472                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1473                 qlcnic_83xx_disable_pause_frames(p_dev);
1474                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1475                                                  QLCNIC_PEG_HALT_STATUS1);
1476                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1477                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1478                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1479                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1480                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1481                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1482                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0, &err),
1483                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1, &err),
1484                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2, &err),
1485                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3, &err),
1486                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4, &err));
1487
1488                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1489                         dev_err(&p_dev->pdev->dev,
1490                                 "Device is being reset err code 0x00006700.\n");
1491         }
1492
1493         return ret;
1494 }
1495
1496 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1497 {
1498         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1499         u32 val;
1500
1501         do {
1502                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1503                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1504                         return 0;
1505                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1506         } while (--retries);
1507
1508         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1509         return -EIO;
1510 }
1511
1512 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1513 {
1514         int err;
1515
1516         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1517         if (err)
1518                 return err;
1519
1520         err = qlcnic_83xx_check_heartbeat(p_dev);
1521         if (err)
1522                 return err;
1523
1524         return err;
1525 }
1526
1527 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1528                                 int duration, u32 mask, u32 status)
1529 {
1530         int timeout_error, err = 0;
1531         u32 value;
1532         u8 retries;
1533
1534         value = QLCRD32(p_dev, addr, &err);
1535         if (err == -EIO)
1536                 return err;
1537         retries = duration / 10;
1538
1539         do {
1540                 if ((value & mask) != status) {
1541                         timeout_error = 1;
1542                         msleep(duration / 10);
1543                         value = QLCRD32(p_dev, addr, &err);
1544                         if (err == -EIO)
1545                                 return err;
1546                 } else {
1547                         timeout_error = 0;
1548                         break;
1549                 }
1550         } while (retries--);
1551
1552         if (timeout_error) {
1553                 p_dev->ahw->reset.seq_error++;
1554                 dev_err(&p_dev->pdev->dev,
1555                         "%s: Timeout Err, entry_num = %d\n",
1556                         __func__, p_dev->ahw->reset.seq_index);
1557                 dev_err(&p_dev->pdev->dev,
1558                         "0x%08x 0x%08x 0x%08x\n",
1559                         value, mask, status);
1560         }
1561
1562         return timeout_error;
1563 }
1564
1565 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1566 {
1567         u32 sum = 0;
1568         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1569         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1570
1571         while (count-- > 0)
1572                 sum += *buff++;
1573
1574         while (sum >> 16)
1575                 sum = (sum & 0xFFFF) + (sum >> 16);
1576
1577         if (~sum) {
1578                 return 0;
1579         } else {
1580                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1581                 return -1;
1582         }
1583 }
1584
1585 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1586 {
1587         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1588         u32 addr, count, prev_ver, curr_ver;
1589         u8 *p_buff;
1590
1591         if (ahw->reset.buff != NULL) {
1592                 prev_ver = p_dev->fw_version;
1593                 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1594                 if (curr_ver > prev_ver)
1595                         kfree(ahw->reset.buff);
1596                 else
1597                         return 0;
1598         }
1599
1600         ahw->reset.seq_error = 0;
1601         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1602         if (p_dev->ahw->reset.buff == NULL)
1603                 return -ENOMEM;
1604
1605         p_buff = p_dev->ahw->reset.buff;
1606         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1607         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1608
1609         /* Copy template header from flash */
1610         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1611                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1612                 return -EIO;
1613         }
1614         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1615         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1616         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1617         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1618
1619         /* Copy rest of the template */
1620         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1621                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1622                 return -EIO;
1623         }
1624
1625         if (qlcnic_83xx_reset_template_checksum(p_dev))
1626                 return -EIO;
1627         /* Get Stop, Start and Init command offsets */
1628         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1629         ahw->reset.start_offset = ahw->reset.buff +
1630                                   ahw->reset.hdr->start_offset;
1631         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1632         return 0;
1633 }
1634
1635 /* Read Write HW register command */
1636 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1637                                            u32 raddr, u32 waddr)
1638 {
1639         int err = 0;
1640         u32 value;
1641
1642         value = QLCRD32(p_dev, raddr, &err);
1643         if (err == -EIO)
1644                 return;
1645         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1646 }
1647
1648 /* Read Modify Write HW register command */
1649 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1650                                     u32 raddr, u32 waddr,
1651                                     struct qlc_83xx_rmw *p_rmw_hdr)
1652 {
1653         int err = 0;
1654         u32 value;
1655
1656         if (p_rmw_hdr->index_a) {
1657                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1658         } else {
1659                 value = QLCRD32(p_dev, raddr, &err);
1660                 if (err == -EIO)
1661                         return;
1662         }
1663
1664         value &= p_rmw_hdr->mask;
1665         value <<= p_rmw_hdr->shl;
1666         value >>= p_rmw_hdr->shr;
1667         value |= p_rmw_hdr->or_value;
1668         value ^= p_rmw_hdr->xor_value;
1669         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1670 }
1671
1672 /* Write HW register command */
1673 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1674                                    struct qlc_83xx_entry_hdr *p_hdr)
1675 {
1676         int i;
1677         struct qlc_83xx_entry *entry;
1678
1679         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1680                                           sizeof(struct qlc_83xx_entry_hdr));
1681
1682         for (i = 0; i < p_hdr->count; i++, entry++) {
1683                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1684                                              entry->arg2);
1685                 if (p_hdr->delay)
1686                         udelay((u32)(p_hdr->delay));
1687         }
1688 }
1689
1690 /* Read and Write instruction */
1691 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1692                                         struct qlc_83xx_entry_hdr *p_hdr)
1693 {
1694         int i;
1695         struct qlc_83xx_entry *entry;
1696
1697         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1698                                           sizeof(struct qlc_83xx_entry_hdr));
1699
1700         for (i = 0; i < p_hdr->count; i++, entry++) {
1701                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1702                                                entry->arg2);
1703                 if (p_hdr->delay)
1704                         udelay((u32)(p_hdr->delay));
1705         }
1706 }
1707
1708 /* Poll HW register command */
1709 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1710                                   struct qlc_83xx_entry_hdr *p_hdr)
1711 {
1712         long delay;
1713         struct qlc_83xx_entry *entry;
1714         struct qlc_83xx_poll *poll;
1715         int i, err = 0;
1716         unsigned long arg1, arg2;
1717
1718         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1719                                         sizeof(struct qlc_83xx_entry_hdr));
1720
1721         entry = (struct qlc_83xx_entry *)((char *)poll +
1722                                           sizeof(struct qlc_83xx_poll));
1723         delay = (long)p_hdr->delay;
1724
1725         if (!delay) {
1726                 for (i = 0; i < p_hdr->count; i++, entry++)
1727                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1728                                              delay, poll->mask,
1729                                              poll->status);
1730         } else {
1731                 for (i = 0; i < p_hdr->count; i++, entry++) {
1732                         arg1 = entry->arg1;
1733                         arg2 = entry->arg2;
1734                         if (delay) {
1735                                 if (qlcnic_83xx_poll_reg(p_dev,
1736                                                          arg1, delay,
1737                                                          poll->mask,
1738                                                          poll->status)){
1739                                         QLCRD32(p_dev, arg1, &err);
1740                                         if (err == -EIO)
1741                                                 return;
1742                                         QLCRD32(p_dev, arg2, &err);
1743                                         if (err == -EIO)
1744                                                 return;
1745                                 }
1746                         }
1747                 }
1748         }
1749 }
1750
1751 /* Poll and write HW register command */
1752 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1753                                         struct qlc_83xx_entry_hdr *p_hdr)
1754 {
1755         int i;
1756         long delay;
1757         struct qlc_83xx_quad_entry *entry;
1758         struct qlc_83xx_poll *poll;
1759
1760         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1761                                         sizeof(struct qlc_83xx_entry_hdr));
1762         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1763                                                sizeof(struct qlc_83xx_poll));
1764         delay = (long)p_hdr->delay;
1765
1766         for (i = 0; i < p_hdr->count; i++, entry++) {
1767                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1768                                              entry->dr_value);
1769                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1770                                              entry->ar_value);
1771                 if (delay)
1772                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1773                                              poll->mask, poll->status);
1774         }
1775 }
1776
1777 /* Read Modify Write register command */
1778 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1779                                           struct qlc_83xx_entry_hdr *p_hdr)
1780 {
1781         int i;
1782         struct qlc_83xx_entry *entry;
1783         struct qlc_83xx_rmw *rmw_hdr;
1784
1785         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1786                                           sizeof(struct qlc_83xx_entry_hdr));
1787
1788         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1789                                           sizeof(struct qlc_83xx_rmw));
1790
1791         for (i = 0; i < p_hdr->count; i++, entry++) {
1792                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1793                                         entry->arg2, rmw_hdr);
1794                 if (p_hdr->delay)
1795                         udelay((u32)(p_hdr->delay));
1796         }
1797 }
1798
1799 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1800 {
1801         if (p_hdr->delay)
1802                 mdelay((u32)((long)p_hdr->delay));
1803 }
1804
1805 /* Read and poll register command */
1806 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1807                                        struct qlc_83xx_entry_hdr *p_hdr)
1808 {
1809         long delay;
1810         int index, i, j, err;
1811         struct qlc_83xx_quad_entry *entry;
1812         struct qlc_83xx_poll *poll;
1813         unsigned long addr;
1814
1815         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1816                                         sizeof(struct qlc_83xx_entry_hdr));
1817
1818         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1819                                                sizeof(struct qlc_83xx_poll));
1820         delay = (long)p_hdr->delay;
1821
1822         for (i = 0; i < p_hdr->count; i++, entry++) {
1823                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1824                                              entry->ar_value);
1825                 if (delay) {
1826                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1827                                                   poll->mask, poll->status)){
1828                                 index = p_dev->ahw->reset.array_index;
1829                                 addr = entry->dr_addr;
1830                                 j = QLCRD32(p_dev, addr, &err);
1831                                 if (err == -EIO)
1832                                         return;
1833
1834                                 p_dev->ahw->reset.array[index++] = j;
1835
1836                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1837                                         p_dev->ahw->reset.array_index = 1;
1838                         }
1839                 }
1840         }
1841 }
1842
1843 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1844 {
1845         p_dev->ahw->reset.seq_end = 1;
1846 }
1847
1848 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1849 {
1850         p_dev->ahw->reset.template_end = 1;
1851         if (p_dev->ahw->reset.seq_error == 0)
1852                 dev_err(&p_dev->pdev->dev,
1853                         "HW restart process completed successfully.\n");
1854         else
1855                 dev_err(&p_dev->pdev->dev,
1856                         "HW restart completed with timeout errors.\n");
1857 }
1858
1859 /**
1860 * qlcnic_83xx_exec_template_cmd
1861 *
1862 * @p_dev: adapter structure
1863 * @p_buff: Poiter to instruction template
1864 *
1865 * Template provides instructions to stop, restart and initalize firmware.
1866 * These instructions are abstracted as a series of read, write and
1867 * poll operations on hardware registers. Register information and operation
1868 * specifics are not exposed to the driver. Driver reads the template from
1869 * flash and executes the instructions located at pre-defined offsets.
1870 *
1871 * Returns: None
1872 * */
1873 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1874                                           char *p_buff)
1875 {
1876         int index, entries;
1877         struct qlc_83xx_entry_hdr *p_hdr;
1878         char *entry = p_buff;
1879
1880         p_dev->ahw->reset.seq_end = 0;
1881         p_dev->ahw->reset.template_end = 0;
1882         entries = p_dev->ahw->reset.hdr->entries;
1883         index = p_dev->ahw->reset.seq_index;
1884
1885         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1886                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1887
1888                 switch (p_hdr->cmd) {
1889                 case QLC_83XX_OPCODE_NOP:
1890                         break;
1891                 case QLC_83XX_OPCODE_WRITE_LIST:
1892                         qlcnic_83xx_write_list(p_dev, p_hdr);
1893                         break;
1894                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1895                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1896                         break;
1897                 case QLC_83XX_OPCODE_POLL_LIST:
1898                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1899                         break;
1900                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1901                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1902                         break;
1903                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1904                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1905                         break;
1906                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1907                         qlcnic_83xx_pause(p_hdr);
1908                         break;
1909                 case QLC_83XX_OPCODE_SEQ_END:
1910                         qlcnic_83xx_seq_end(p_dev);
1911                         break;
1912                 case QLC_83XX_OPCODE_TMPL_END:
1913                         qlcnic_83xx_template_end(p_dev);
1914                         break;
1915                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1916                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1917                         break;
1918                 default:
1919                         dev_err(&p_dev->pdev->dev,
1920                                 "%s: Unknown opcode 0x%04x in template %d\n",
1921                                 __func__, p_hdr->cmd, index);
1922                         break;
1923                 }
1924                 entry += p_hdr->size;
1925         }
1926         p_dev->ahw->reset.seq_index = index;
1927 }
1928
1929 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1930 {
1931         p_dev->ahw->reset.seq_index = 0;
1932
1933         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1934         if (p_dev->ahw->reset.seq_end != 1)
1935                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1936 }
1937
1938 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1939 {
1940         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1941         if (p_dev->ahw->reset.template_end != 1)
1942                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1943 }
1944
1945 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1946 {
1947         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1948         if (p_dev->ahw->reset.seq_end != 1)
1949                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1950 }
1951
1952 static void qlcnic_83xx_get_fw_file_name(struct qlcnic_adapter *adapter,
1953                                          char *file_name)
1954 {
1955         struct pci_dev *pdev = adapter->pdev;
1956
1957         memset(file_name, 0, QLC_FW_FILE_NAME_LEN);
1958
1959         switch (pdev->device) {
1960         case PCI_DEVICE_ID_QLOGIC_QLE834X:
1961                 strncpy(file_name, QLC_83XX_FW_FILE_NAME,
1962                         QLC_FW_FILE_NAME_LEN);
1963                 break;
1964         case PCI_DEVICE_ID_QLOGIC_QLE844X:
1965                 strncpy(file_name, QLC_84XX_FW_FILE_NAME,
1966                         QLC_FW_FILE_NAME_LEN);
1967                 break;
1968         default:
1969                 dev_err(&pdev->dev, "%s: Invalid device id\n",
1970                         __func__);
1971         }
1972 }
1973
1974 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1975 {
1976         char fw_file_name[QLC_FW_FILE_NAME_LEN];
1977         int err = -EIO;
1978
1979         qlcnic_83xx_get_fw_file_name(adapter, fw_file_name);
1980         if (request_firmware(&adapter->ahw->fw_info.fw, fw_file_name,
1981                              &(adapter->pdev->dev))) {
1982                 dev_err(&adapter->pdev->dev,
1983                         "No file FW image, loading flash FW image.\n");
1984                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1985                                     QLC_83XX_BOOT_FROM_FLASH);
1986         } else {
1987                 if (qlcnic_83xx_copy_fw_file(adapter))
1988                         return err;
1989                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1990                                     QLC_83XX_BOOT_FROM_FILE);
1991         }
1992
1993         return 0;
1994 }
1995
1996 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1997 {
1998         u32 val;
1999         int err = -EIO;
2000
2001         qlcnic_83xx_stop_hw(adapter);
2002
2003         /* Collect FW register dump if required */
2004         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
2005         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
2006                 qlcnic_dump_fw(adapter);
2007         qlcnic_83xx_init_hw(adapter);
2008
2009         if (qlcnic_83xx_copy_bootloader(adapter))
2010                 return err;
2011         /* Boot either flash image or firmware image from host file system */
2012         if (qlcnic_load_fw_file) {
2013                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
2014                         return err;
2015         } else {
2016                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
2017                                     QLC_83XX_BOOT_FROM_FLASH);
2018         }
2019
2020         qlcnic_83xx_start_hw(adapter);
2021         if (qlcnic_83xx_check_hw_status(adapter))
2022                 return -EIO;
2023
2024         return 0;
2025 }
2026
2027 /**
2028 * qlcnic_83xx_config_default_opmode
2029 *
2030 * @adapter: adapter structure
2031 *
2032 * Configure default driver operating mode
2033 *
2034 * Returns: Error code or Success(0)
2035 * */
2036 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
2037 {
2038         u32 op_mode;
2039         struct qlcnic_hardware_context *ahw = adapter->ahw;
2040
2041         qlcnic_get_func_no(adapter);
2042         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
2043
2044         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
2045                 op_mode = QLC_83XX_DEFAULT_OPMODE;
2046
2047         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
2048                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
2049                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
2050         } else {
2051                 return -EIO;
2052         }
2053
2054         return 0;
2055 }
2056
2057 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2058 {
2059         int err;
2060         struct qlcnic_info nic_info;
2061         struct qlcnic_hardware_context *ahw = adapter->ahw;
2062
2063         memset(&nic_info, 0, sizeof(struct qlcnic_info));
2064         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2065         if (err)
2066                 return -EIO;
2067
2068         ahw->physical_port = (u8) nic_info.phys_port;
2069         ahw->switch_mode = nic_info.switch_mode;
2070         ahw->max_tx_ques = nic_info.max_tx_ques;
2071         ahw->max_rx_ques = nic_info.max_rx_ques;
2072         ahw->capabilities = nic_info.capabilities;
2073         ahw->max_mac_filters = nic_info.max_mac_filters;
2074         ahw->max_mtu = nic_info.max_mtu;
2075
2076         /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2077          * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2078          * exclusive. So in case of sriov capable device load driver in
2079          * default mode
2080          */
2081         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2082                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2083                 return ahw->nic_mode;
2084         }
2085
2086         if (ahw->capabilities & BIT_23)
2087                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2088         else
2089                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2090
2091         return ahw->nic_mode;
2092 }
2093
2094 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2095 {
2096         int ret;
2097
2098         ret = qlcnic_83xx_get_nic_configuration(adapter);
2099         if (ret == -EIO)
2100                 return -EIO;
2101
2102         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2103                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2104                         return -EIO;
2105         } else if (ret == QLC_83XX_DEFAULT_MODE) {
2106                 if (qlcnic_83xx_config_default_opmode(adapter))
2107                         return -EIO;
2108         }
2109
2110         return 0;
2111 }
2112
2113 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2114 {
2115         struct qlcnic_hardware_context *ahw = adapter->ahw;
2116
2117         if (ahw->port_type == QLCNIC_XGBE) {
2118                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2119                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2120                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2121                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2122
2123         } else if (ahw->port_type == QLCNIC_GBE) {
2124                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2125                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2126                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2127                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2128         }
2129         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2130         adapter->max_rds_rings = MAX_RDS_RINGS;
2131 }
2132
2133 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2134 {
2135         int err = -EIO;
2136
2137         qlcnic_83xx_get_minidump_template(adapter);
2138         if (qlcnic_83xx_get_port_info(adapter))
2139                 return err;
2140
2141         qlcnic_83xx_config_buff_descriptors(adapter);
2142         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2143         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2144
2145         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2146                  adapter->ahw->fw_hal_version);
2147
2148         return 0;
2149 }
2150
2151 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2152 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2153 {
2154         struct qlcnic_cmd_args cmd;
2155         u32 presence_mask, audit_mask;
2156         int status;
2157
2158         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2159         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2160
2161         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2162                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2163                                                QLCNIC_CMD_STOP_NIC_FUNC);
2164                 if (status)
2165                         return;
2166
2167                 cmd.req.arg[1] = BIT_31;
2168                 status = qlcnic_issue_cmd(adapter, &cmd);
2169                 if (status)
2170                         dev_err(&adapter->pdev->dev,
2171                                 "Failed to clean up the function resources\n");
2172                 qlcnic_free_mbx_args(&cmd);
2173         }
2174 }
2175
2176 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2177 {
2178         struct qlcnic_hardware_context *ahw = adapter->ahw;
2179         int err = 0;
2180
2181         ahw->msix_supported = !!qlcnic_use_msi_x;
2182         err = qlcnic_83xx_init_mailbox_work(adapter);
2183         if (err)
2184                 goto exit;
2185
2186         if (qlcnic_sriov_vf_check(adapter)) {
2187                 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2188                 if (err)
2189                         goto detach_mbx;
2190                 else
2191                         return err;
2192         }
2193
2194         err = qlcnic_83xx_check_hw_status(adapter);
2195         if (err)
2196                 goto detach_mbx;
2197
2198         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2199                 qlcnic_83xx_read_flash_mfg_id(adapter);
2200
2201         err = qlcnic_83xx_idc_init(adapter);
2202         if (err)
2203                 goto detach_mbx;
2204
2205         err = qlcnic_setup_intr(adapter, 0, 0);
2206         if (err) {
2207                 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2208                 goto disable_intr;
2209         }
2210
2211         err = qlcnic_83xx_setup_mbx_intr(adapter);
2212         if (err)
2213                 goto disable_mbx_intr;
2214
2215         qlcnic_83xx_clear_function_resources(adapter);
2216
2217         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2218
2219         /* register for NIC IDC AEN Events */
2220         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2221
2222         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2223         err = qlcnic_83xx_configure_opmode(adapter);
2224         if (err)
2225                 goto disable_mbx_intr;
2226
2227         /* Perform operating mode specific initialization */
2228         err = adapter->nic_ops->init_driver(adapter);
2229         if (err)
2230                 goto disable_mbx_intr;
2231
2232         if (adapter->dcb && qlcnic_dcb_attach(adapter))
2233                 qlcnic_clear_dcb_ops(adapter);
2234
2235         /* Periodically monitor device status */
2236         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2237         return 0;
2238
2239 disable_mbx_intr:
2240         qlcnic_83xx_free_mbx_intr(adapter);
2241
2242 disable_intr:
2243         qlcnic_teardown_intr(adapter);
2244
2245 detach_mbx:
2246         qlcnic_83xx_detach_mailbox_work(adapter);
2247         qlcnic_83xx_free_mailbox(ahw->mailbox);
2248 exit:
2249         return err;
2250 }
2251
2252 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *adapter)
2253 {
2254         struct qlcnic_hardware_context *ahw = adapter->ahw;
2255         struct qlc_83xx_idc *idc = &ahw->idc;
2256
2257         clear_bit(QLC_83XX_MBX_READY, &idc->status);
2258         cancel_delayed_work_sync(&adapter->fw_work);
2259
2260         if (ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
2261                 qlcnic_83xx_disable_vnic_mode(adapter, 1);
2262
2263         qlcnic_83xx_idc_detach_driver(adapter);
2264         qlcnic_83xx_register_nic_idc_func(adapter, 0);
2265
2266         cancel_delayed_work_sync(&adapter->idc_aen_work);
2267 }
2268
2269 int qlcnic_83xx_aer_reset(struct qlcnic_adapter *adapter)
2270 {
2271         struct qlcnic_hardware_context *ahw = adapter->ahw;
2272         struct qlc_83xx_idc *idc = &ahw->idc;
2273         int ret = 0;
2274         u32 owner;
2275
2276         /* Mark the previous IDC state as NEED_RESET so
2277          * that state_entry() will perform the reattachment
2278          * and bringup the device
2279          */
2280         idc->prev_state = QLC_83XX_IDC_DEV_NEED_RESET;
2281         owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2282         if (ahw->pci_func == owner) {
2283                 ret = qlcnic_83xx_restart_hw(adapter);
2284                 if (ret < 0)
2285                         return ret;
2286                 qlcnic_83xx_idc_clear_registers(adapter, 0);
2287         }
2288
2289         ret = idc->state_entry(adapter);
2290         return ret;
2291 }
2292
2293 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *adapter)
2294 {
2295         struct qlcnic_hardware_context *ahw = adapter->ahw;
2296         struct qlc_83xx_idc *idc = &ahw->idc;
2297         u32 owner;
2298
2299         idc->prev_state = QLC_83XX_IDC_DEV_READY;
2300         owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
2301         if (ahw->pci_func == owner)
2302                 qlcnic_83xx_idc_enter_ready_state(adapter, 0);
2303
2304         qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state, 0);
2305 }