drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 332         { PCI_VENDOR_ID_DLINK,                  0x4300,
 333                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 334         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 338         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 339                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 340         { 0x0001,                               0x8168,
 341                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 342         {0,},
 343 };
 344
 345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 346
 347 static int rx_buf_sz = 16383;
 348 static int use_dac;
 349 static struct {
 350         u32 msg_enable;
 351 } debug = { -1 };
 352
 353 enum rtl_registers {
 354         MAC0            = 0,    /* Ethernet hardware address. */
 355         MAC4            = 4,
 356         MAR0            = 8,    /* Multicast filter. */
 357         CounterAddrLow          = 0x10,
 358         CounterAddrHigh         = 0x14,
 359         TxDescStartAddrLow      = 0x20,
 360         TxDescStartAddrHigh     = 0x24,
 361         TxHDescStartAddrLow     = 0x28,
 362         TxHDescStartAddrHigh    = 0x2c,
 363         FLASH           = 0x30,
 364         ERSR            = 0x36,
 365         ChipCmd         = 0x37,
 366         TxPoll          = 0x38,
 367         IntrMask        = 0x3c,
 368         IntrStatus      = 0x3e,
 369
 370         TxConfig        = 0x40,
 371 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 372 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 373
 374         RxConfig        = 0x44,
 375 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 376 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 377 #define RXCFG_FIFO_SHIFT                13
 378                                         /* No threshold before first PCI xfer */
 379 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 380 #define RX_EARLY_OFF                    (1 << 11)
 381 #define RXCFG_DMA_SHIFT                 8
 382                                         /* Unlimited maximum PCI burst. */
 383 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 384
 385         RxMissed        = 0x4c,
 386         Cfg9346         = 0x50,
 387         Config0         = 0x51,
 388         Config1         = 0x52,
 389         Config2         = 0x53,
 390 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 391
 392         Config3         = 0x54,
 393         Config4         = 0x55,
 394         Config5         = 0x56,
 395         MultiIntr       = 0x5c,
 396         PHYAR           = 0x60,
 397         PHYstatus       = 0x6c,
 398         RxMaxSize       = 0xda,
 399         CPlusCmd        = 0xe0,
 400         IntrMitigate    = 0xe2,
 401         RxDescAddrLow   = 0xe4,
 402         RxDescAddrHigh  = 0xe8,
 403         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 404
 405 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 406
 407         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 408
 409 #define TxPacketMax     (8064 >> 7)
 410 #define EarlySize       0x27
 411
 412         FuncEvent       = 0xf0,
 413         FuncEventMask   = 0xf4,
 414         FuncPresetState = 0xf8,
 415         IBCR0           = 0xf8,
 416         IBCR2           = 0xf9,
 417         IBIMR0          = 0xfa,
 418         IBISR0          = 0xfb,
 419         FuncForceEvent  = 0xfc,
 420 };
 421
 422 enum rtl8110_registers {
 423         TBICSR                  = 0x64,
 424         TBI_ANAR                = 0x68,
 425         TBI_LPAR                = 0x6a,
 426 };
 427
 428 enum rtl8168_8101_registers {
 429         CSIDR                   = 0x64,
 430         CSIAR                   = 0x68,
 431 #define CSIAR_FLAG                      0x80000000
 432 #define CSIAR_WRITE_CMD                 0x80000000
 433 #define CSIAR_BYTE_ENABLE               0x0f
 434 #define CSIAR_BYTE_ENABLE_SHIFT         12
 435 #define CSIAR_ADDR_MASK                 0x0fff
 436 #define CSIAR_FUNC_CARD                 0x00000000
 437 #define CSIAR_FUNC_SDIO                 0x00010000
 438 #define CSIAR_FUNC_NIC                  0x00020000
 439 #define CSIAR_FUNC_NIC2                 0x00010000
 440         PMCH                    = 0x6f,
 441         EPHYAR                  = 0x80,
 442 #define EPHYAR_FLAG                     0x80000000
 443 #define EPHYAR_WRITE_CMD                0x80000000
 444 #define EPHYAR_REG_MASK                 0x1f
 445 #define EPHYAR_REG_SHIFT                16
 446 #define EPHYAR_DATA_MASK                0xffff
 447         DLLPR                   = 0xd0,
 448 #define PFM_EN                          (1 << 6)
 449 #define TX_10M_PS_EN                    (1 << 7)
 450         DBG_REG                 = 0xd1,
 451 #define FIX_NAK_1                       (1 << 4)
 452 #define FIX_NAK_2                       (1 << 3)
 453         TWSI                    = 0xd2,
 454         MCU                     = 0xd3,
 455 #define NOW_IS_OOB                      (1 << 7)
 456 #define TX_EMPTY                        (1 << 5)
 457 #define RX_EMPTY                        (1 << 4)
 458 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 459 #define EN_NDP                          (1 << 3)
 460 #define EN_OOB_RESET                    (1 << 2)
 461 #define LINK_LIST_RDY                   (1 << 1)
 462         EFUSEAR                 = 0xdc,
 463 #define EFUSEAR_FLAG                    0x80000000
 464 #define EFUSEAR_WRITE_CMD               0x80000000
 465 #define EFUSEAR_READ_CMD                0x00000000
 466 #define EFUSEAR_REG_MASK                0x03ff
 467 #define EFUSEAR_REG_SHIFT               8
 468 #define EFUSEAR_DATA_MASK               0xff
 469         MISC_1                  = 0xf2,
 470 #define PFM_D3COLD_EN                   (1 << 6)
 471 };
 472
 473 enum rtl8168_registers {
 474         LED_FREQ                = 0x1a,
 475         EEE_LED                 = 0x1b,
 476         ERIDR                   = 0x70,
 477         ERIAR                   = 0x74,
 478 #define ERIAR_FLAG                      0x80000000
 479 #define ERIAR_WRITE_CMD                 0x80000000
 480 #define ERIAR_READ_CMD                  0x00000000
 481 #define ERIAR_ADDR_BYTE_ALIGN           4
 482 #define ERIAR_TYPE_SHIFT                16
 483 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 484 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 485 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 486 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 487 #define ERIAR_MASK_SHIFT                12
 488 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 489 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 490 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 491 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 492 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 493         EPHY_RXER_NUM           = 0x7c,
 494         OCPDR                   = 0xb0, /* OCP GPHY access */
 495 #define OCPDR_WRITE_CMD                 0x80000000
 496 #define OCPDR_READ_CMD                  0x00000000
 497 #define OCPDR_REG_MASK                  0x7f
 498 #define OCPDR_GPHY_REG_SHIFT            16
 499 #define OCPDR_DATA_MASK                 0xffff
 500         OCPAR                   = 0xb4,
 501 #define OCPAR_FLAG                      0x80000000
 502 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 503 #define OCPAR_GPHY_READ_CMD             0x0000f060
 504         GPHY_OCP                = 0xb8,
 505         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 506         MISC                    = 0xf0, /* 8168e only. */
 507 #define TXPLA_RST                       (1 << 29)
 508 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 509 #define PWM_EN                          (1 << 22)
 510 #define RXDV_GATED_EN                   (1 << 19)
 511 #define EARLY_TALLY_EN                  (1 << 16)
 512 };
 513
 514 enum rtl_register_content {
 515         /* InterruptStatusBits */
 516         SYSErr          = 0x8000,
 517         PCSTimeout      = 0x4000,
 518         SWInt           = 0x0100,
 519         TxDescUnavail   = 0x0080,
 520         RxFIFOOver      = 0x0040,
 521         LinkChg         = 0x0020,
 522         RxOverflow      = 0x0010,
 523         TxErr           = 0x0008,
 524         TxOK            = 0x0004,
 525         RxErr           = 0x0002,
 526         RxOK            = 0x0001,
 527
 528         /* RxStatusDesc */
 529         RxBOVF  = (1 << 24),
 530         RxFOVF  = (1 << 23),
 531         RxRWT   = (1 << 22),
 532         RxRES   = (1 << 21),
 533         RxRUNT  = (1 << 20),
 534         RxCRC   = (1 << 19),
 535
 536         /* ChipCmdBits */
 537         StopReq         = 0x80,
 538         CmdReset        = 0x10,
 539         CmdRxEnb        = 0x08,
 540         CmdTxEnb        = 0x04,
 541         RxBufEmpty      = 0x01,
 542
 543         /* TXPoll register p.5 */
 544         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 545         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 546         FSWInt          = 0x01,         /* Forced software interrupt */
 547
 548         /* Cfg9346Bits */
 549         Cfg9346_Lock    = 0x00,
 550         Cfg9346_Unlock  = 0xc0,
 551
 552         /* rx_mode_bits */
 553         AcceptErr       = 0x20,
 554         AcceptRunt      = 0x10,
 555         AcceptBroadcast = 0x08,
 556         AcceptMulticast = 0x04,
 557         AcceptMyPhys    = 0x02,
 558         AcceptAllPhys   = 0x01,
 559 #define RX_CONFIG_ACCEPT_MASK           0x3f
 560
 561         /* TxConfigBits */
 562         TxInterFrameGapShift = 24,
 563         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 564
 565         /* Config1 register p.24 */
 566         LEDS1           = (1 << 7),
 567         LEDS0           = (1 << 6),
 568         Speed_down      = (1 << 4),
 569         MEMMAP          = (1 << 3),
 570         IOMAP           = (1 << 2),
 571         VPD             = (1 << 1),
 572         PMEnable        = (1 << 0),     /* Power Management Enable */
 573
 574         /* Config2 register p. 25 */
 575         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 576         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 577         PCI_Clock_66MHz = 0x01,
 578         PCI_Clock_33MHz = 0x00,
 579
 580         /* Config3 register p.25 */
 581         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 582         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 583         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 584         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 585         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 586
 587         /* Config4 register */
 588         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 589
 590         /* Config5 register p.27 */
 591         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 592         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 593         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 594         Spi_en          = (1 << 3),
 595         LanWake         = (1 << 1),     /* LanWake enable/disable */
 596         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 597         ASPM_en         = (1 << 0),     /* ASPM enable */
 598
 599         /* TBICSR p.28 */
 600         TBIReset        = 0x80000000,
 601         TBILoopback     = 0x40000000,
 602         TBINwEnable     = 0x20000000,
 603         TBINwRestart    = 0x10000000,
 604         TBILinkOk       = 0x02000000,
 605         TBINwComplete   = 0x01000000,
 606
 607         /* CPlusCmd p.31 */
 608         EnableBist      = (1 << 15),    // 8168 8101
 609         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 610         Normal_mode     = (1 << 13),    // unused
 611         Force_half_dup  = (1 << 12),    // 8168 8101
 612         Force_rxflow_en = (1 << 11),    // 8168 8101
 613         Force_txflow_en = (1 << 10),    // 8168 8101
 614         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 615         ASF             = (1 << 8),     // 8168 8101
 616         PktCntrDisable  = (1 << 7),     // 8168 8101
 617         Mac_dbgo_sel    = 0x001c,       // 8168
 618         RxVlan          = (1 << 6),
 619         RxChkSum        = (1 << 5),
 620         PCIDAC          = (1 << 4),
 621         PCIMulRW        = (1 << 3),
 622         INTT_0          = 0x0000,       // 8168
 623         INTT_1          = 0x0001,       // 8168
 624         INTT_2          = 0x0002,       // 8168
 625         INTT_3          = 0x0003,       // 8168
 626
 627         /* rtl8169_PHYstatus */
 628         TBI_Enable      = 0x80,
 629         TxFlowCtrl      = 0x40,
 630         RxFlowCtrl      = 0x20,
 631         _1000bpsF       = 0x10,
 632         _100bps         = 0x08,
 633         _10bps          = 0x04,
 634         LinkStatus      = 0x02,
 635         FullDup         = 0x01,
 636
 637         /* _TBICSRBit */
 638         TBILinkOK       = 0x02000000,
 639
 640         /* DumpCounterCommand */
 641         CounterDump     = 0x8,
 642
 643         /* magic enable v2 */
 644         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 645 };
 646
 647 enum rtl_desc_bit {
 648         /* First doubleword. */
 649         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 650         RingEnd         = (1 << 30), /* End of descriptor ring */
 651         FirstFrag       = (1 << 29), /* First segment of a packet */
 652         LastFrag        = (1 << 28), /* Final segment of a packet */
 653 };
 654
 655 /* Generic case. */
 656 enum rtl_tx_desc_bit {
 657         /* First doubleword. */
 658         TD_LSO          = (1 << 27),            /* Large Send Offload */
 659 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 660
 661         /* Second doubleword. */
 662         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 663 };
 664
 665 /* 8169, 8168b and 810x except 8102e. */
 666 enum rtl_tx_desc_bit_0 {
 667         /* First doubleword. */
 668 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 669         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 670         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 671         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 672 };
 673
 674 /* 8102e, 8168c and beyond. */
 675 enum rtl_tx_desc_bit_1 {
 676         /* First doubleword. */
 677         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 678         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 679 #define GTTCPHO_SHIFT                   18
 680 #define GTTCPHO_MAX                     0x7fU
 681
 682         /* Second doubleword. */
 683 #define TCPHO_SHIFT                     18
 684 #define TCPHO_MAX                       0x3ffU
 685 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 686         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 687         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 688         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 689         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 690 };
 691
 692 enum rtl_rx_desc_bit {
 693         /* Rx private */
 694         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 695         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 696
 697 #define RxProtoUDP      (PID1)
 698 #define RxProtoTCP      (PID0)
 699 #define RxProtoIP       (PID1 | PID0)
 700 #define RxProtoMask     RxProtoIP
 701
 702         IPFail          = (1 << 16), /* IP checksum failed */
 703         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 704         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 705         RxVlanTag       = (1 << 16), /* VLAN tag available */
 706 };
 707
 708 #define RsvdMask        0x3fffc000
 709
 710 struct TxDesc {
 711         __le32 opts1;
 712         __le32 opts2;
 713         __le64 addr;
 714 };
 715
 716 struct RxDesc {
 717         __le32 opts1;
 718         __le32 opts2;
 719         __le64 addr;
 720 };
 721
 722 struct ring_info {
 723         struct sk_buff  *skb;
 724         u32             len;
 725         u8              __pad[sizeof(void *) - sizeof(u32)];
 726 };
 727
 728 enum features {
 729         RTL_FEATURE_WOL         = (1 << 0),
 730         RTL_FEATURE_MSI         = (1 << 1),
 731         RTL_FEATURE_GMII        = (1 << 2),
 732 };
 733
 734 struct rtl8169_counters {
 735         __le64  tx_packets;
 736         __le64  rx_packets;
 737         __le64  tx_errors;
 738         __le32  rx_errors;
 739         __le16  rx_missed;
 740         __le16  align_errors;
 741         __le32  tx_one_collision;
 742         __le32  tx_multi_collision;
 743         __le64  rx_unicast;
 744         __le64  rx_broadcast;
 745         __le32  rx_multicast;
 746         __le16  tx_aborted;
 747         __le16  tx_underun;
 748 };
 749
 750 enum rtl_flag {
 751         RTL_FLAG_TASK_ENABLED,
 752         RTL_FLAG_TASK_SLOW_PENDING,
 753         RTL_FLAG_TASK_RESET_PENDING,
 754         RTL_FLAG_TASK_PHY_PENDING,
 755         RTL_FLAG_MAX
 756 };
 757
 758 struct rtl8169_stats {
 759         u64                     packets;
 760         u64                     bytes;
 761         struct u64_stats_sync   syncp;
 762 };
 763
 764 struct rtl8169_private {
 765         void __iomem *mmio_addr;        /* memory map physical address */
 766         struct pci_dev *pci_dev;
 767         struct net_device *dev;
 768         struct napi_struct napi;
 769         u32 msg_enable;
 770         u16 txd_version;
 771         u16 mac_version;
 772         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 773         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 774         u32 dirty_tx;
 775         struct rtl8169_stats rx_stats;
 776         struct rtl8169_stats tx_stats;
 777         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 778         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 779         dma_addr_t TxPhyAddr;
 780         dma_addr_t RxPhyAddr;
 781         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 782         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 783         struct timer_list timer;
 784         u16 cp_cmd;
 785
 786         u16 event_slow;
 787
 788         struct mdio_ops {
 789                 void (*write)(struct rtl8169_private *, int, int);
 790                 int (*read)(struct rtl8169_private *, int);
 791         } mdio_ops;
 792
 793         struct pll_power_ops {
 794                 void (*down)(struct rtl8169_private *);
 795                 void (*up)(struct rtl8169_private *);
 796         } pll_power_ops;
 797
 798         struct jumbo_ops {
 799                 void (*enable)(struct rtl8169_private *);
 800                 void (*disable)(struct rtl8169_private *);
 801         } jumbo_ops;
 802
 803         struct csi_ops {
 804                 void (*write)(struct rtl8169_private *, int, int);
 805                 u32 (*read)(struct rtl8169_private *, int);
 806         } csi_ops;
 807
 808         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 809         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 810         void (*phy_reset_enable)(struct rtl8169_private *tp);
 811         void (*hw_start)(struct net_device *);
 812         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 813         unsigned int (*link_ok)(void __iomem *);
 814         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 815         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 816
 817         struct {
 818                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 819                 struct mutex mutex;
 820                 struct work_struct work;
 821         } wk;
 822
 823         unsigned features;
 824
 825         struct mii_if_info mii;
 826         struct rtl8169_counters counters;
 827         u32 saved_wolopts;
 828         u32 opts1_mask;
 829
 830         struct rtl_fw {
 831                 const struct firmware *fw;
 832
 833 #define RTL_VER_SIZE            32
 834
 835                 char version[RTL_VER_SIZE];
 836
 837                 struct rtl_fw_phy_action {
 838                         __le32 *code;
 839                         size_t size;
 840                 } phy_action;
 841         } *rtl_fw;
 842 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 843
 844         u32 ocp_base;
 845 };
 846
 847 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 848 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 849 module_param(use_dac, int, 0);
 850 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 851 module_param_named(debug, debug.msg_enable, int, 0);
 852 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 853 MODULE_LICENSE("GPL");
 854 MODULE_VERSION(RTL8169_VERSION);
 855 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 856 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 857 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 858 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 859 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 860 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 861 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 862 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 863 MODULE_FIRMWARE(FIRMWARE_8402_1);
 864 MODULE_FIRMWARE(FIRMWARE_8411_1);
 865 MODULE_FIRMWARE(FIRMWARE_8411_2);
 866 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 867 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 868 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 869 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 870 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 871 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 872 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 873 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 874
 875 static void rtl_lock_work(struct rtl8169_private *tp)
 876 {
 877         mutex_lock(&tp->wk.mutex);
 878 }
 879
 880 static void rtl_unlock_work(struct rtl8169_private *tp)
 881 {
 882         mutex_unlock(&tp->wk.mutex);
 883 }
 884
 885 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 886 {
 887         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 888                                            PCI_EXP_DEVCTL_READRQ, force);
 889 }
 890
 891 struct rtl_cond {
 892         bool (*check)(struct rtl8169_private *);
 893         const char *msg;
 894 };
 895
 896 static void rtl_udelay(unsigned int d)
 897 {
 898         udelay(d);
 899 }
 900
 901 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 902                           void (*delay)(unsigned int), unsigned int d, int n,
 903                           bool high)
 904 {
 905         int i;
 906
 907         for (i = 0; i < n; i++) {
 908                 delay(d);
 909                 if (c->check(tp) == high)
 910                         return true;
 911         }
 912         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 913                   c->msg, !high, n, d);
 914         return false;
 915 }
 916
 917 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 918                                       const struct rtl_cond *c,
 919                                       unsigned int d, int n)
 920 {
 921         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 922 }
 923
 924 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 925                                      const struct rtl_cond *c,
 926                                      unsigned int d, int n)
 927 {
 928         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 929 }
 930
 931 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 932                                       const struct rtl_cond *c,
 933                                       unsigned int d, int n)
 934 {
 935         return rtl_loop_wait(tp, c, msleep, d, n, true);
 936 }
 937
 938 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 939                                      const struct rtl_cond *c,
 940                                      unsigned int d, int n)
 941 {
 942         return rtl_loop_wait(tp, c, msleep, d, n, false);
 943 }
 944
 945 #define DECLARE_RTL_COND(name)                          \
 946 static bool name ## _check(struct rtl8169_private *);   \
 947                                                         \
 948 static const struct rtl_cond name = {                   \
 949         .check  = name ## _check,                       \
 950         .msg    = #name                                 \
 951 };                                                      \
 952                                                         \
 953 static bool name ## _check(struct rtl8169_private *tp)
 954
 955 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 956 {
 957         if (reg & 0xffff0001) {
 958                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 959                 return true;
 960         }
 961         return false;
 962 }
 963
 964 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 965 {
 966         void __iomem *ioaddr = tp->mmio_addr;
 967
 968         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 969 }
 970
 971 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 972 {
 973         void __iomem *ioaddr = tp->mmio_addr;
 974
 975         if (rtl_ocp_reg_failure(tp, reg))
 976                 return;
 977
 978         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 979
 980         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 981 }
 982
 983 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 984 {
 985         void __iomem *ioaddr = tp->mmio_addr;
 986
 987         if (rtl_ocp_reg_failure(tp, reg))
 988                 return 0;
 989
 990         RTL_W32(GPHY_OCP, reg << 15);
 991
 992         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 993                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
 994 }
 995
 996 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 997 {
 998         void __iomem *ioaddr = tp->mmio_addr;
 999
1000         if (rtl_ocp_reg_failure(tp, reg))
1001                 return;
1002
1003         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1004 }
1005
1006 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1007 {
1008         void __iomem *ioaddr = tp->mmio_addr;
1009
1010         if (rtl_ocp_reg_failure(tp, reg))
1011                 return 0;
1012
1013         RTL_W32(OCPDR, reg << 15);
1014
1015         return RTL_R32(OCPDR);
1016 }
1017
1018 #define OCP_STD_PHY_BASE        0xa400
1019
1020 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1021 {
1022         if (reg == 0x1f) {
1023                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1024                 return;
1025         }
1026
1027         if (tp->ocp_base != OCP_STD_PHY_BASE)
1028                 reg -= 0x10;
1029
1030         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1031 }
1032
1033 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1034 {
1035         if (tp->ocp_base != OCP_STD_PHY_BASE)
1036                 reg -= 0x10;
1037
1038         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1039 }
1040
1041 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1042 {
1043         if (reg == 0x1f) {
1044                 tp->ocp_base = value << 4;
1045                 return;
1046         }
1047
1048         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1049 }
1050
1051 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1052 {
1053         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1054 }
1055
1056 DECLARE_RTL_COND(rtl_phyar_cond)
1057 {
1058         void __iomem *ioaddr = tp->mmio_addr;
1059
1060         return RTL_R32(PHYAR) & 0x80000000;
1061 }
1062
1063 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1064 {
1065         void __iomem *ioaddr = tp->mmio_addr;
1066
1067         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1068
1069         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1070         /*
1071          * According to hardware specs a 20us delay is required after write
1072          * complete indication, but before sending next command.
1073          */
1074         udelay(20);
1075 }
1076
1077 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1078 {
1079         void __iomem *ioaddr = tp->mmio_addr;
1080         int value;
1081
1082         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1083
1084         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1085                 RTL_R32(PHYAR) & 0xffff : ~0;
1086
1087         /*
1088          * According to hardware specs a 20us delay is required after read
1089          * complete indication, but before sending next command.
1090          */
1091         udelay(20);
1092
1093         return value;
1094 }
1095
1096 DECLARE_RTL_COND(rtl_ocpar_cond)
1097 {
1098         void __iomem *ioaddr = tp->mmio_addr;
1099
1100         return RTL_R32(OCPAR) & OCPAR_FLAG;
1101 }
1102
1103 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1104 {
1105         void __iomem *ioaddr = tp->mmio_addr;
1106
1107         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1108         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1109         RTL_W32(EPHY_RXER_NUM, 0);
1110
1111         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1112 }
1113
1114 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1115 {
1116         r8168dp_1_mdio_access(tp, reg,
1117                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1118 }
1119
1120 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1121 {
1122         void __iomem *ioaddr = tp->mmio_addr;
1123
1124         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1125
1126         mdelay(1);
1127         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1128         RTL_W32(EPHY_RXER_NUM, 0);
1129
1130         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1131                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1132 }
1133
1134 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1135
1136 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1137 {
1138         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1139 }
1140
1141 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1142 {
1143         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1144 }
1145
1146 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1147 {
1148         void __iomem *ioaddr = tp->mmio_addr;
1149
1150         r8168dp_2_mdio_start(ioaddr);
1151
1152         r8169_mdio_write(tp, reg, value);
1153
1154         r8168dp_2_mdio_stop(ioaddr);
1155 }
1156
1157 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1158 {
1159         void __iomem *ioaddr = tp->mmio_addr;
1160         int value;
1161
1162         r8168dp_2_mdio_start(ioaddr);
1163
1164         value = r8169_mdio_read(tp, reg);
1165
1166         r8168dp_2_mdio_stop(ioaddr);
1167
1168         return value;
1169 }
1170
1171 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1172 {
1173         tp->mdio_ops.write(tp, location, val);
1174 }
1175
1176 static int rtl_readphy(struct rtl8169_private *tp, int location)
1177 {
1178         return tp->mdio_ops.read(tp, location);
1179 }
1180
1181 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1182 {
1183         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1184 }
1185
1186 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1187 {
1188         int val;
1189
1190         val = rtl_readphy(tp, reg_addr);
1191         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1192 }
1193
1194 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1195                            int val)
1196 {
1197         struct rtl8169_private *tp = netdev_priv(dev);
1198
1199         rtl_writephy(tp, location, val);
1200 }
1201
1202 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1203 {
1204         struct rtl8169_private *tp = netdev_priv(dev);
1205
1206         return rtl_readphy(tp, location);
1207 }
1208
1209 DECLARE_RTL_COND(rtl_ephyar_cond)
1210 {
1211         void __iomem *ioaddr = tp->mmio_addr;
1212
1213         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1214 }
1215
1216 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1217 {
1218         void __iomem *ioaddr = tp->mmio_addr;
1219
1220         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1221                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1222
1223         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1224
1225         udelay(10);
1226 }
1227
1228 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1229 {
1230         void __iomem *ioaddr = tp->mmio_addr;
1231
1232         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1233
1234         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1235                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1236 }
1237
1238 DECLARE_RTL_COND(rtl_eriar_cond)
1239 {
1240         void __iomem *ioaddr = tp->mmio_addr;
1241
1242         return RTL_R32(ERIAR) & ERIAR_FLAG;
1243 }
1244
1245 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1246                           u32 val, int type)
1247 {
1248         void __iomem *ioaddr = tp->mmio_addr;
1249
1250         BUG_ON((addr & 3) || (mask == 0));
1251         RTL_W32(ERIDR, val);
1252         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1253
1254         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1255 }
1256
1257 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1258 {
1259         void __iomem *ioaddr = tp->mmio_addr;
1260
1261         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1262
1263         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1264                 RTL_R32(ERIDR) : ~0;
1265 }
1266
1267 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1268                          u32 m, int type)
1269 {
1270         u32 val;
1271
1272         val = rtl_eri_read(tp, addr, type);
1273         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1274 }
1275
1276 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1277 {
1278         void __iomem *ioaddr = tp->mmio_addr;
1279
1280         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1281         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1282                 RTL_R32(OCPDR) : ~0;
1283 }
1284
1285 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1286 {
1287         return rtl_eri_read(tp, reg, ERIAR_OOB);
1288 }
1289
1290 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1291 {
1292         switch (tp->mac_version) {
1293         case RTL_GIGA_MAC_VER_27:
1294         case RTL_GIGA_MAC_VER_28:
1295         case RTL_GIGA_MAC_VER_31:
1296                 return r8168dp_ocp_read(tp, mask, reg);
1297         case RTL_GIGA_MAC_VER_49:
1298         case RTL_GIGA_MAC_VER_50:
1299         case RTL_GIGA_MAC_VER_51:
1300                 return r8168ep_ocp_read(tp, mask, reg);
1301         default:
1302                 BUG();
1303                 return ~0;
1304         }
1305 }
1306
1307 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1308                               u32 data)
1309 {
1310         void __iomem *ioaddr = tp->mmio_addr;
1311
1312         RTL_W32(OCPDR, data);
1313         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1314         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1315 }
1316
1317 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1318                               u32 data)
1319 {
1320         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1321                       data, ERIAR_OOB);
1322 }
1323
1324 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1325 {
1326         switch (tp->mac_version) {
1327         case RTL_GIGA_MAC_VER_27:
1328         case RTL_GIGA_MAC_VER_28:
1329         case RTL_GIGA_MAC_VER_31:
1330                 r8168dp_ocp_write(tp, mask, reg, data);
1331                 break;
1332         case RTL_GIGA_MAC_VER_49:
1333         case RTL_GIGA_MAC_VER_50:
1334         case RTL_GIGA_MAC_VER_51:
1335                 r8168ep_ocp_write(tp, mask, reg, data);
1336                 break;
1337         default:
1338                 BUG();
1339                 break;
1340         }
1341 }
1342
1343 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1344 {
1345         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1346
1347         ocp_write(tp, 0x1, 0x30, 0x00000001);
1348 }
1349
1350 #define OOB_CMD_RESET           0x00
1351 #define OOB_CMD_DRIVER_START    0x05
1352 #define OOB_CMD_DRIVER_STOP     0x06
1353
1354 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1355 {
1356         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1357 }
1358
1359 DECLARE_RTL_COND(rtl_ocp_read_cond)
1360 {
1361         u16 reg;
1362
1363         reg = rtl8168_get_ocp_reg(tp);
1364
1365         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1366 }
1367
1368 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1369 {
1370         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1371 }
1372
1373 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1374 {
1375         void __iomem *ioaddr = tp->mmio_addr;
1376
1377         return RTL_R8(IBISR0) & 0x02;
1378 }
1379
1380 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1381 {
1382         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1383         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1384 }
1385
1386 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1387 {
1388         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1389         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1390         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1391 }
1392
1393 static void rtl8168_driver_start(struct rtl8169_private *tp)
1394 {
1395         switch (tp->mac_version) {
1396         case RTL_GIGA_MAC_VER_27:
1397         case RTL_GIGA_MAC_VER_28:
1398         case RTL_GIGA_MAC_VER_31:
1399                 rtl8168dp_driver_start(tp);
1400                 break;
1401         case RTL_GIGA_MAC_VER_49:
1402         case RTL_GIGA_MAC_VER_50:
1403         case RTL_GIGA_MAC_VER_51:
1404                 rtl8168ep_driver_start(tp);
1405                 break;
1406         default:
1407                 BUG();
1408                 break;
1409         }
1410 }
1411
1412 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1413 {
1414         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1415         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1416 }
1417
1418 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1419 {
1420         void __iomem *ioaddr = tp->mmio_addr;
1421
1422         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1423         rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1424         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1425         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1426         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1427         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1428         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1429 }
1430
1431 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1432 {
1433         switch (tp->mac_version) {
1434         case RTL_GIGA_MAC_VER_27:
1435         case RTL_GIGA_MAC_VER_28:
1436         case RTL_GIGA_MAC_VER_31:
1437                 rtl8168dp_driver_stop(tp);
1438                 break;
1439         case RTL_GIGA_MAC_VER_49:
1440         case RTL_GIGA_MAC_VER_50:
1441         case RTL_GIGA_MAC_VER_51:
1442                 rtl8168ep_driver_stop(tp);
1443                 break;
1444         default:
1445                 BUG();
1446                 break;
1447         }
1448 }
1449
1450 static int r8168dp_check_dash(struct rtl8169_private *tp)
1451 {
1452         u16 reg = rtl8168_get_ocp_reg(tp);
1453
1454         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1455 }
1456
1457 static int r8168ep_check_dash(struct rtl8169_private *tp)
1458 {
1459         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1460 }
1461
1462 static int r8168_check_dash(struct rtl8169_private *tp)
1463 {
1464         switch (tp->mac_version) {
1465         case RTL_GIGA_MAC_VER_27:
1466         case RTL_GIGA_MAC_VER_28:
1467         case RTL_GIGA_MAC_VER_31:
1468                 return r8168dp_check_dash(tp);
1469         case RTL_GIGA_MAC_VER_49:
1470         case RTL_GIGA_MAC_VER_50:
1471         case RTL_GIGA_MAC_VER_51:
1472                 return r8168ep_check_dash(tp);
1473         default:
1474                 return 0;
1475         }
1476 }
1477
1478 struct exgmac_reg {
1479         u16 addr;
1480         u16 mask;
1481         u32 val;
1482 };
1483
1484 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1485                                    const struct exgmac_reg *r, int len)
1486 {
1487         while (len-- > 0) {
1488                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1489                 r++;
1490         }
1491 }
1492
1493 DECLARE_RTL_COND(rtl_efusear_cond)
1494 {
1495         void __iomem *ioaddr = tp->mmio_addr;
1496
1497         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1498 }
1499
1500 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1501 {
1502         void __iomem *ioaddr = tp->mmio_addr;
1503
1504         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1505
1506         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1507                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1508 }
1509
1510 static u16 rtl_get_events(struct rtl8169_private *tp)
1511 {
1512         void __iomem *ioaddr = tp->mmio_addr;
1513
1514         return RTL_R16(IntrStatus);
1515 }
1516
1517 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1518 {
1519         void __iomem *ioaddr = tp->mmio_addr;
1520
1521         RTL_W16(IntrStatus, bits);
1522         mmiowb();
1523 }
1524
1525 static void rtl_irq_disable(struct rtl8169_private *tp)
1526 {
1527         void __iomem *ioaddr = tp->mmio_addr;
1528
1529         RTL_W16(IntrMask, 0);
1530         mmiowb();
1531 }
1532
1533 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1534 {
1535         void __iomem *ioaddr = tp->mmio_addr;
1536
1537         RTL_W16(IntrMask, bits);
1538 }
1539
1540 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1541 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1542 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1543
1544 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1545 {
1546         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1547 }
1548
1549 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1550 {
1551         void __iomem *ioaddr = tp->mmio_addr;
1552
1553         rtl_irq_disable(tp);
1554         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1555         RTL_R8(ChipCmd);
1556 }
1557
1558 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1559 {
1560         void __iomem *ioaddr = tp->mmio_addr;
1561
1562         return RTL_R32(TBICSR) & TBIReset;
1563 }
1564
1565 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1566 {
1567         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1568 }
1569
1570 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1571 {
1572         return RTL_R32(TBICSR) & TBILinkOk;
1573 }
1574
1575 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1576 {
1577         return RTL_R8(PHYstatus) & LinkStatus;
1578 }
1579
1580 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1581 {
1582         void __iomem *ioaddr = tp->mmio_addr;
1583
1584         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1585 }
1586
1587 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1588 {
1589         unsigned int val;
1590
1591         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1592         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1593 }
1594
1595 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1596 {
1597         void __iomem *ioaddr = tp->mmio_addr;
1598         struct net_device *dev = tp->dev;
1599
1600         if (!netif_running(dev))
1601                 return;
1602
1603         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1604             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1605                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1606                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1607                                       ERIAR_EXGMAC);
1608                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1609                                       ERIAR_EXGMAC);
1610                 } else if (RTL_R8(PHYstatus) & _100bps) {
1611                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1612                                       ERIAR_EXGMAC);
1613                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1614                                       ERIAR_EXGMAC);
1615                 } else {
1616                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1617                                       ERIAR_EXGMAC);
1618                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1619                                       ERIAR_EXGMAC);
1620                 }
1621                 /* Reset packet filter */
1622                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1623                              ERIAR_EXGMAC);
1624                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1625                              ERIAR_EXGMAC);
1626         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1627                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1628                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1629                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1630                                       ERIAR_EXGMAC);
1631                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1632                                       ERIAR_EXGMAC);
1633                 } else {
1634                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1635                                       ERIAR_EXGMAC);
1636                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1637                                       ERIAR_EXGMAC);
1638                 }
1639         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1640                 if (RTL_R8(PHYstatus) & _10bps) {
1641                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1642                                       ERIAR_EXGMAC);
1643                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1644                                       ERIAR_EXGMAC);
1645                 } else {
1646                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1647                                       ERIAR_EXGMAC);
1648                 }
1649         }
1650 }
1651
1652 static void __rtl8169_check_link_status(struct net_device *dev,
1653                                         struct rtl8169_private *tp,
1654                                         void __iomem *ioaddr, bool pm)
1655 {
1656         if (tp->link_ok(ioaddr)) {
1657                 rtl_link_chg_patch(tp);
1658                 /* This is to cancel a scheduled suspend if there's one. */
1659                 if (pm)
1660                         pm_request_resume(&tp->pci_dev->dev);
1661                 netif_carrier_on(dev);
1662                 if (net_ratelimit())
1663                         netif_info(tp, ifup, dev, "link up\n");
1664         } else {
1665                 netif_carrier_off(dev);
1666                 netif_info(tp, ifdown, dev, "link down\n");
1667                 if (pm)
1668                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1669         }
1670 }
1671
1672 static void rtl8169_check_link_status(struct net_device *dev,
1673                                       struct rtl8169_private *tp,
1674                                       void __iomem *ioaddr)
1675 {
1676         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1677 }
1678
1679 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1680
1681 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1682 {
1683         void __iomem *ioaddr = tp->mmio_addr;
1684         u8 options;
1685         u32 wolopts = 0;
1686
1687         options = RTL_R8(Config1);
1688         if (!(options & PMEnable))
1689                 return 0;
1690
1691         options = RTL_R8(Config3);
1692         if (options & LinkUp)
1693                 wolopts |= WAKE_PHY;
1694         switch (tp->mac_version) {
1695         case RTL_GIGA_MAC_VER_34:
1696         case RTL_GIGA_MAC_VER_35:
1697         case RTL_GIGA_MAC_VER_36:
1698         case RTL_GIGA_MAC_VER_37:
1699         case RTL_GIGA_MAC_VER_38:
1700         case RTL_GIGA_MAC_VER_40:
1701         case RTL_GIGA_MAC_VER_41:
1702         case RTL_GIGA_MAC_VER_42:
1703         case RTL_GIGA_MAC_VER_43:
1704         case RTL_GIGA_MAC_VER_44:
1705         case RTL_GIGA_MAC_VER_45:
1706         case RTL_GIGA_MAC_VER_46:
1707         case RTL_GIGA_MAC_VER_47:
1708         case RTL_GIGA_MAC_VER_48:
1709         case RTL_GIGA_MAC_VER_49:
1710         case RTL_GIGA_MAC_VER_50:
1711         case RTL_GIGA_MAC_VER_51:
1712                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1713                         wolopts |= WAKE_MAGIC;
1714                 break;
1715         default:
1716                 if (options & MagicPacket)
1717                         wolopts |= WAKE_MAGIC;
1718                 break;
1719         }
1720
1721         options = RTL_R8(Config5);
1722         if (options & UWF)
1723                 wolopts |= WAKE_UCAST;
1724         if (options & BWF)
1725                 wolopts |= WAKE_BCAST;
1726         if (options & MWF)
1727                 wolopts |= WAKE_MCAST;
1728
1729         return wolopts;
1730 }
1731
1732 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1733 {
1734         struct rtl8169_private *tp = netdev_priv(dev);
1735
1736         rtl_lock_work(tp);
1737
1738         wol->supported = WAKE_ANY;
1739         wol->wolopts = __rtl8169_get_wol(tp);
1740
1741         rtl_unlock_work(tp);
1742 }
1743
1744 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1745 {
1746         void __iomem *ioaddr = tp->mmio_addr;
1747         unsigned int i, tmp;
1748         static const struct {
1749                 u32 opt;
1750                 u16 reg;
1751                 u8  mask;
1752         } cfg[] = {
1753                 { WAKE_PHY,   Config3, LinkUp },
1754                 { WAKE_UCAST, Config5, UWF },
1755                 { WAKE_BCAST, Config5, BWF },
1756                 { WAKE_MCAST, Config5, MWF },
1757                 { WAKE_ANY,   Config5, LanWake },
1758                 { WAKE_MAGIC, Config3, MagicPacket }
1759         };
1760         u8 options;
1761
1762         RTL_W8(Cfg9346, Cfg9346_Unlock);
1763
1764         switch (tp->mac_version) {
1765         case RTL_GIGA_MAC_VER_34:
1766         case RTL_GIGA_MAC_VER_35:
1767         case RTL_GIGA_MAC_VER_36:
1768         case RTL_GIGA_MAC_VER_37:
1769         case RTL_GIGA_MAC_VER_38:
1770         case RTL_GIGA_MAC_VER_40:
1771         case RTL_GIGA_MAC_VER_41:
1772         case RTL_GIGA_MAC_VER_42:
1773         case RTL_GIGA_MAC_VER_43:
1774         case RTL_GIGA_MAC_VER_44:
1775         case RTL_GIGA_MAC_VER_45:
1776         case RTL_GIGA_MAC_VER_46:
1777         case RTL_GIGA_MAC_VER_47:
1778         case RTL_GIGA_MAC_VER_48:
1779         case RTL_GIGA_MAC_VER_49:
1780         case RTL_GIGA_MAC_VER_50:
1781         case RTL_GIGA_MAC_VER_51:
1782                 tmp = ARRAY_SIZE(cfg) - 1;
1783                 if (wolopts & WAKE_MAGIC)
1784                         rtl_w0w1_eri(tp,
1785                                      0x0dc,
1786                                      ERIAR_MASK_0100,
1787                                      MagicPacket_v2,
1788                                      0x0000,
1789                                      ERIAR_EXGMAC);
1790                 else
1791                         rtl_w0w1_eri(tp,
1792                                      0x0dc,
1793                                      ERIAR_MASK_0100,
1794                                      0x0000,
1795                                      MagicPacket_v2,
1796                                      ERIAR_EXGMAC);
1797                 break;
1798         default:
1799                 tmp = ARRAY_SIZE(cfg);
1800                 break;
1801         }
1802
1803         for (i = 0; i < tmp; i++) {
1804                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1805                 if (wolopts & cfg[i].opt)
1806                         options |= cfg[i].mask;
1807                 RTL_W8(cfg[i].reg, options);
1808         }
1809
1810         switch (tp->mac_version) {
1811         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1812                 options = RTL_R8(Config1) & ~PMEnable;
1813                 if (wolopts)
1814                         options |= PMEnable;
1815                 RTL_W8(Config1, options);
1816                 break;
1817         default:
1818                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1819                 if (wolopts)
1820                         options |= PME_SIGNAL;
1821                 RTL_W8(Config2, options);
1822                 break;
1823         }
1824
1825         RTL_W8(Cfg9346, Cfg9346_Lock);
1826 }
1827
1828 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1829 {
1830         struct rtl8169_private *tp = netdev_priv(dev);
1831
1832         rtl_lock_work(tp);
1833
1834         if (wol->wolopts)
1835                 tp->features |= RTL_FEATURE_WOL;
1836         else
1837                 tp->features &= ~RTL_FEATURE_WOL;
1838         __rtl8169_set_wol(tp, wol->wolopts);
1839
1840         rtl_unlock_work(tp);
1841
1842         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1843
1844         return 0;
1845 }
1846
1847 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1848 {
1849         return rtl_chip_infos[tp->mac_version].fw_name;
1850 }
1851
1852 static void rtl8169_get_drvinfo(struct net_device *dev,
1853                                 struct ethtool_drvinfo *info)
1854 {
1855         struct rtl8169_private *tp = netdev_priv(dev);
1856         struct rtl_fw *rtl_fw = tp->rtl_fw;
1857
1858         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1859         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1860         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1861         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1862         if (!IS_ERR_OR_NULL(rtl_fw))
1863                 strlcpy(info->fw_version, rtl_fw->version,
1864                         sizeof(info->fw_version));
1865 }
1866
1867 static int rtl8169_get_regs_len(struct net_device *dev)
1868 {
1869         return R8169_REGS_SIZE;
1870 }
1871
1872 static int rtl8169_set_speed_tbi(struct net_device *dev,
1873                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1874 {
1875         struct rtl8169_private *tp = netdev_priv(dev);
1876         void __iomem *ioaddr = tp->mmio_addr;
1877         int ret = 0;
1878         u32 reg;
1879
1880         reg = RTL_R32(TBICSR);
1881         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1882             (duplex == DUPLEX_FULL)) {
1883                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1884         } else if (autoneg == AUTONEG_ENABLE)
1885                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1886         else {
1887                 netif_warn(tp, link, dev,
1888                            "incorrect speed setting refused in TBI mode\n");
1889                 ret = -EOPNOTSUPP;
1890         }
1891
1892         return ret;
1893 }
1894
1895 static int rtl8169_set_speed_xmii(struct net_device *dev,
1896                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1897 {
1898         struct rtl8169_private *tp = netdev_priv(dev);
1899         int giga_ctrl, bmcr;
1900         int rc = -EINVAL;
1901
1902         rtl_writephy(tp, 0x1f, 0x0000);
1903
1904         if (autoneg == AUTONEG_ENABLE) {
1905                 int auto_nego;
1906
1907                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1908                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1909                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1910
1911                 if (adv & ADVERTISED_10baseT_Half)
1912                         auto_nego |= ADVERTISE_10HALF;
1913                 if (adv & ADVERTISED_10baseT_Full)
1914                         auto_nego |= ADVERTISE_10FULL;
1915                 if (adv & ADVERTISED_100baseT_Half)
1916                         auto_nego |= ADVERTISE_100HALF;
1917                 if (adv & ADVERTISED_100baseT_Full)
1918                         auto_nego |= ADVERTISE_100FULL;
1919
1920                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1921
1922                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1923                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1924
1925                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1926                 if (tp->mii.supports_gmii) {
1927                         if (adv & ADVERTISED_1000baseT_Half)
1928                                 giga_ctrl |= ADVERTISE_1000HALF;
1929                         if (adv & ADVERTISED_1000baseT_Full)
1930                                 giga_ctrl |= ADVERTISE_1000FULL;
1931                 } else if (adv & (ADVERTISED_1000baseT_Half |
1932                                   ADVERTISED_1000baseT_Full)) {
1933                         netif_info(tp, link, dev,
1934                                    "PHY does not support 1000Mbps\n");
1935                         goto out;
1936                 }
1937
1938                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1939
1940                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1941                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1942         } else {
1943                 giga_ctrl = 0;
1944
1945                 if (speed == SPEED_10)
1946                         bmcr = 0;
1947                 else if (speed == SPEED_100)
1948                         bmcr = BMCR_SPEED100;
1949                 else
1950                         goto out;
1951
1952                 if (duplex == DUPLEX_FULL)
1953                         bmcr |= BMCR_FULLDPLX;
1954         }
1955
1956         rtl_writephy(tp, MII_BMCR, bmcr);
1957
1958         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1959             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1960                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1961                         rtl_writephy(tp, 0x17, 0x2138);
1962                         rtl_writephy(tp, 0x0e, 0x0260);
1963                 } else {
1964                         rtl_writephy(tp, 0x17, 0x2108);
1965                         rtl_writephy(tp, 0x0e, 0x0000);
1966                 }
1967         }
1968
1969         rc = 0;
1970 out:
1971         return rc;
1972 }
1973
1974 static int rtl8169_set_speed(struct net_device *dev,
1975                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1976 {
1977         struct rtl8169_private *tp = netdev_priv(dev);
1978         int ret;
1979
1980         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1981         if (ret < 0)
1982                 goto out;
1983
1984         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1985             (advertising & ADVERTISED_1000baseT_Full)) {
1986                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1987         }
1988 out:
1989         return ret;
1990 }
1991
1992 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1993 {
1994         struct rtl8169_private *tp = netdev_priv(dev);
1995         int ret;
1996
1997         del_timer_sync(&tp->timer);
1998
1999         rtl_lock_work(tp);
2000         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2001                                 cmd->duplex, cmd->advertising);
2002         rtl_unlock_work(tp);
2003
2004         return ret;
2005 }
2006
2007 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2008         netdev_features_t features)
2009 {
2010         struct rtl8169_private *tp = netdev_priv(dev);
2011
2012         if (dev->mtu > TD_MSS_MAX)
2013                 features &= ~NETIF_F_ALL_TSO;
2014
2015         if (dev->mtu > JUMBO_1K &&
2016             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2017                 features &= ~NETIF_F_IP_CSUM;
2018
2019         return features;
2020 }
2021
2022 static void __rtl8169_set_features(struct net_device *dev,
2023                                    netdev_features_t features)
2024 {
2025         struct rtl8169_private *tp = netdev_priv(dev);
2026         void __iomem *ioaddr = tp->mmio_addr;
2027         u32 rx_config;
2028
2029         rx_config = RTL_R32(RxConfig);
2030         if (features & NETIF_F_RXALL)
2031                 rx_config |= (AcceptErr | AcceptRunt);
2032         else
2033                 rx_config &= ~(AcceptErr | AcceptRunt);
2034
2035         RTL_W32(RxConfig, rx_config);
2036
2037         if (features & NETIF_F_RXCSUM)
2038                 tp->cp_cmd |= RxChkSum;
2039         else
2040                 tp->cp_cmd &= ~RxChkSum;
2041
2042         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2043                 tp->cp_cmd |= RxVlan;
2044         else
2045                 tp->cp_cmd &= ~RxVlan;
2046
2047         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2048
2049         RTL_W16(CPlusCmd, tp->cp_cmd);
2050         RTL_R16(CPlusCmd);
2051 }
2052
2053 static int rtl8169_set_features(struct net_device *dev,
2054                                 netdev_features_t features)
2055 {
2056         struct rtl8169_private *tp = netdev_priv(dev);
2057
2058         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2059
2060         rtl_lock_work(tp);
2061         if (features ^ dev->features)
2062                 __rtl8169_set_features(dev, features);
2063         rtl_unlock_work(tp);
2064
2065         return 0;
2066 }
2067
2068
2069 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2070 {
2071         return (vlan_tx_tag_present(skb)) ?
2072                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
2073 }
2074
2075 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2076 {
2077         u32 opts2 = le32_to_cpu(desc->opts2);
2078
2079         if (opts2 & RxVlanTag)
2080                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2081 }
2082
2083 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2084 {
2085         struct rtl8169_private *tp = netdev_priv(dev);
2086         void __iomem *ioaddr = tp->mmio_addr;
2087         u32 status;
2088
2089         cmd->supported =
2090                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2091         cmd->port = PORT_FIBRE;
2092         cmd->transceiver = XCVR_INTERNAL;
2093
2094         status = RTL_R32(TBICSR);
2095         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2096         cmd->autoneg = !!(status & TBINwEnable);
2097
2098         ethtool_cmd_speed_set(cmd, SPEED_1000);
2099         cmd->duplex = DUPLEX_FULL; /* Always set */
2100
2101         return 0;
2102 }
2103
2104 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2105 {
2106         struct rtl8169_private *tp = netdev_priv(dev);
2107
2108         return mii_ethtool_gset(&tp->mii, cmd);
2109 }
2110
2111 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2112 {
2113         struct rtl8169_private *tp = netdev_priv(dev);
2114         int rc;
2115
2116         rtl_lock_work(tp);
2117         rc = tp->get_settings(dev, cmd);
2118         rtl_unlock_work(tp);
2119
2120         return rc;
2121 }
2122
2123 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2124                              void *p)
2125 {
2126         struct rtl8169_private *tp = netdev_priv(dev);
2127         u32 __iomem *data = tp->mmio_addr;
2128         u32 *dw = p;
2129         int i;
2130
2131         rtl_lock_work(tp);
2132         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2133                 memcpy_fromio(dw++, data++, 4);
2134         rtl_unlock_work(tp);
2135 }
2136
2137 static u32 rtl8169_get_msglevel(struct net_device *dev)
2138 {
2139         struct rtl8169_private *tp = netdev_priv(dev);
2140
2141         return tp->msg_enable;
2142 }
2143
2144 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2145 {
2146         struct rtl8169_private *tp = netdev_priv(dev);
2147
2148         tp->msg_enable = value;
2149 }
2150
2151 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2152         "tx_packets",
2153         "rx_packets",
2154         "tx_errors",
2155         "rx_errors",
2156         "rx_missed",
2157         "align_errors",
2158         "tx_single_collisions",
2159         "tx_multi_collisions",
2160         "unicast",
2161         "broadcast",
2162         "multicast",
2163         "tx_aborted",
2164         "tx_underrun",
2165 };
2166
2167 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2168 {
2169         switch (sset) {
2170         case ETH_SS_STATS:
2171                 return ARRAY_SIZE(rtl8169_gstrings);
2172         default:
2173                 return -EOPNOTSUPP;
2174         }
2175 }
2176
2177 DECLARE_RTL_COND(rtl_counters_cond)
2178 {
2179         void __iomem *ioaddr = tp->mmio_addr;
2180
2181         return RTL_R32(CounterAddrLow) & CounterDump;
2182 }
2183
2184 static void rtl8169_update_counters(struct net_device *dev)
2185 {
2186         struct rtl8169_private *tp = netdev_priv(dev);
2187         void __iomem *ioaddr = tp->mmio_addr;
2188         struct device *d = &tp->pci_dev->dev;
2189         struct rtl8169_counters *counters;
2190         dma_addr_t paddr;
2191         u32 cmd;
2192
2193         /*
2194          * Some chips are unable to dump tally counters when the receiver
2195          * is disabled.
2196          */
2197         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2198                 return;
2199
2200         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
2201         if (!counters)
2202                 return;
2203
2204         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2205         cmd = (u64)paddr & DMA_BIT_MASK(32);
2206         RTL_W32(CounterAddrLow, cmd);
2207         RTL_W32(CounterAddrLow, cmd | CounterDump);
2208
2209         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2210                 memcpy(&tp->counters, counters, sizeof(*counters));
2211
2212         RTL_W32(CounterAddrLow, 0);
2213         RTL_W32(CounterAddrHigh, 0);
2214
2215         dma_free_coherent(d, sizeof(*counters), counters, paddr);
2216 }
2217
2218 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2219                                       struct ethtool_stats *stats, u64 *data)
2220 {
2221         struct rtl8169_private *tp = netdev_priv(dev);
2222
2223         ASSERT_RTNL();
2224
2225         rtl8169_update_counters(dev);
2226
2227         data[0] = le64_to_cpu(tp->counters.tx_packets);
2228         data[1] = le64_to_cpu(tp->counters.rx_packets);
2229         data[2] = le64_to_cpu(tp->counters.tx_errors);
2230         data[3] = le32_to_cpu(tp->counters.rx_errors);
2231         data[4] = le16_to_cpu(tp->counters.rx_missed);
2232         data[5] = le16_to_cpu(tp->counters.align_errors);
2233         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2234         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2235         data[8] = le64_to_cpu(tp->counters.rx_unicast);
2236         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2237         data[10] = le32_to_cpu(tp->counters.rx_multicast);
2238         data[11] = le16_to_cpu(tp->counters.tx_aborted);
2239         data[12] = le16_to_cpu(tp->counters.tx_underun);
2240 }
2241
2242 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2243 {
2244         switch(stringset) {
2245         case ETH_SS_STATS:
2246                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2247                 break;
2248         }
2249 }
2250
2251 static const struct ethtool_ops rtl8169_ethtool_ops = {
2252         .get_drvinfo            = rtl8169_get_drvinfo,
2253         .get_regs_len           = rtl8169_get_regs_len,
2254         .get_link               = ethtool_op_get_link,
2255         .get_settings           = rtl8169_get_settings,
2256         .set_settings           = rtl8169_set_settings,
2257         .get_msglevel           = rtl8169_get_msglevel,
2258         .set_msglevel           = rtl8169_set_msglevel,
2259         .get_regs               = rtl8169_get_regs,
2260         .get_wol                = rtl8169_get_wol,
2261         .set_wol                = rtl8169_set_wol,
2262         .get_strings            = rtl8169_get_strings,
2263         .get_sset_count         = rtl8169_get_sset_count,
2264         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2265         .get_ts_info            = ethtool_op_get_ts_info,
2266 };
2267
2268 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2269                                     struct net_device *dev, u8 default_version)
2270 {
2271         void __iomem *ioaddr = tp->mmio_addr;
2272         /*
2273          * The driver currently handles the 8168Bf and the 8168Be identically
2274          * but they can be identified more specifically through the test below
2275          * if needed:
2276          *
2277          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2278          *
2279          * Same thing for the 8101Eb and the 8101Ec:
2280          *
2281          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2282          */
2283         static const struct rtl_mac_info {
2284                 u32 mask;
2285                 u32 val;
2286                 int mac_version;
2287         } mac_info[] = {
2288                 /* 8168EP family. */
2289                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2290                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2291                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2292
2293                 /* 8168H family. */
2294                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2295                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2296
2297                 /* 8168G family. */
2298                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2299                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2300                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2301                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2302
2303                 /* 8168F family. */
2304                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2305                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2306                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2307
2308                 /* 8168E family. */
2309                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2310                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2311                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2312                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2313
2314                 /* 8168D family. */
2315                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2316                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2317                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2318
2319                 /* 8168DP family. */
2320                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2321                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2322                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2323
2324                 /* 8168C family. */
2325                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2326                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2327                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2328                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2329                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2330                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2331                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2332                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2333                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2334
2335                 /* 8168B family. */
2336                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2337                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2338                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2339                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2340
2341                 /* 8101 family. */
2342                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2343                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2344                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2345                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2346                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2347                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2348                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2349                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2350                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2351                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2352                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2353                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2354                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2355                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2356                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2357                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2358                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2359                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2360                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2361                 /* FIXME: where did these entries come from ? -- FR */
2362                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2363                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2364
2365                 /* 8110 family. */
2366                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2367                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2368                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2369                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2370                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2371                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2372
2373                 /* Catch-all */
2374                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2375         };
2376         const struct rtl_mac_info *p = mac_info;
2377         u32 reg;
2378
2379         reg = RTL_R32(TxConfig);
2380         while ((reg & p->mask) != p->val)
2381                 p++;
2382         tp->mac_version = p->mac_version;
2383
2384         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2385                 netif_notice(tp, probe, dev,
2386                              "unknown MAC, using family default\n");
2387                 tp->mac_version = default_version;
2388         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2389                 tp->mac_version = tp->mii.supports_gmii ?
2390                                   RTL_GIGA_MAC_VER_42 :
2391                                   RTL_GIGA_MAC_VER_43;
2392         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2393                 tp->mac_version = tp->mii.supports_gmii ?
2394                                   RTL_GIGA_MAC_VER_45 :
2395                                   RTL_GIGA_MAC_VER_47;
2396         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2397                 tp->mac_version = tp->mii.supports_gmii ?
2398                                   RTL_GIGA_MAC_VER_46 :
2399                                   RTL_GIGA_MAC_VER_48;
2400         }
2401 }
2402
2403 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2404 {
2405         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2406 }
2407
2408 struct phy_reg {
2409         u16 reg;
2410         u16 val;
2411 };
2412
2413 static void rtl_writephy_batch(struct rtl8169_private *tp,
2414                                const struct phy_reg *regs, int len)
2415 {
2416         while (len-- > 0) {
2417                 rtl_writephy(tp, regs->reg, regs->val);
2418                 regs++;
2419         }
2420 }
2421
2422 #define PHY_READ                0x00000000
2423 #define PHY_DATA_OR             0x10000000
2424 #define PHY_DATA_AND            0x20000000
2425 #define PHY_BJMPN               0x30000000
2426 #define PHY_MDIO_CHG            0x40000000
2427 #define PHY_CLEAR_READCOUNT     0x70000000
2428 #define PHY_WRITE               0x80000000
2429 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2430 #define PHY_COMP_EQ_SKIPN       0xa0000000
2431 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2432 #define PHY_WRITE_PREVIOUS      0xc0000000
2433 #define PHY_SKIPN               0xd0000000
2434 #define PHY_DELAY_MS            0xe0000000
2435
2436 struct fw_info {
2437         u32     magic;
2438         char    version[RTL_VER_SIZE];
2439         __le32  fw_start;
2440         __le32  fw_len;
2441         u8      chksum;
2442 } __packed;
2443
2444 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2445
2446 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2447 {
2448         const struct firmware *fw = rtl_fw->fw;
2449         struct fw_info *fw_info = (struct fw_info *)fw->data;
2450         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2451         char *version = rtl_fw->version;
2452         bool rc = false;
2453
2454         if (fw->size < FW_OPCODE_SIZE)
2455                 goto out;
2456
2457         if (!fw_info->magic) {
2458                 size_t i, size, start;
2459                 u8 checksum = 0;
2460
2461                 if (fw->size < sizeof(*fw_info))
2462                         goto out;
2463
2464                 for (i = 0; i < fw->size; i++)
2465                         checksum += fw->data[i];
2466                 if (checksum != 0)
2467                         goto out;
2468
2469                 start = le32_to_cpu(fw_info->fw_start);
2470                 if (start > fw->size)
2471                         goto out;
2472
2473                 size = le32_to_cpu(fw_info->fw_len);
2474                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2475                         goto out;
2476
2477                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2478
2479                 pa->code = (__le32 *)(fw->data + start);
2480                 pa->size = size;
2481         } else {
2482                 if (fw->size % FW_OPCODE_SIZE)
2483                         goto out;
2484
2485                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2486
2487                 pa->code = (__le32 *)fw->data;
2488                 pa->size = fw->size / FW_OPCODE_SIZE;
2489         }
2490         version[RTL_VER_SIZE - 1] = 0;
2491
2492         rc = true;
2493 out:
2494         return rc;
2495 }
2496
2497 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2498                            struct rtl_fw_phy_action *pa)
2499 {
2500         bool rc = false;
2501         size_t index;
2502
2503         for (index = 0; index < pa->size; index++) {
2504                 u32 action = le32_to_cpu(pa->code[index]);
2505                 u32 regno = (action & 0x0fff0000) >> 16;
2506
2507                 switch(action & 0xf0000000) {
2508                 case PHY_READ:
2509                 case PHY_DATA_OR:
2510                 case PHY_DATA_AND:
2511                 case PHY_MDIO_CHG:
2512                 case PHY_CLEAR_READCOUNT:
2513                 case PHY_WRITE:
2514                 case PHY_WRITE_PREVIOUS:
2515                 case PHY_DELAY_MS:
2516                         break;
2517
2518                 case PHY_BJMPN:
2519                         if (regno > index) {
2520                                 netif_err(tp, ifup, tp->dev,
2521                                           "Out of range of firmware\n");
2522                                 goto out;
2523                         }
2524                         break;
2525                 case PHY_READCOUNT_EQ_SKIP:
2526                         if (index + 2 >= pa->size) {
2527                                 netif_err(tp, ifup, tp->dev,
2528                                           "Out of range of firmware\n");
2529                                 goto out;
2530                         }
2531                         break;
2532                 case PHY_COMP_EQ_SKIPN:
2533                 case PHY_COMP_NEQ_SKIPN:
2534                 case PHY_SKIPN:
2535                         if (index + 1 + regno >= pa->size) {
2536                                 netif_err(tp, ifup, tp->dev,
2537                                           "Out of range of firmware\n");
2538                                 goto out;
2539                         }
2540                         break;
2541
2542                 default:
2543                         netif_err(tp, ifup, tp->dev,
2544                                   "Invalid action 0x%08x\n", action);
2545                         goto out;
2546                 }
2547         }
2548         rc = true;
2549 out:
2550         return rc;
2551 }
2552
2553 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2554 {
2555         struct net_device *dev = tp->dev;
2556         int rc = -EINVAL;
2557
2558         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2559                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2560                 goto out;
2561         }
2562
2563         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2564                 rc = 0;
2565 out:
2566         return rc;
2567 }
2568
2569 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2570 {
2571         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2572         struct mdio_ops org, *ops = &tp->mdio_ops;
2573         u32 predata, count;
2574         size_t index;
2575
2576         predata = count = 0;
2577         org.write = ops->write;
2578         org.read = ops->read;
2579
2580         for (index = 0; index < pa->size; ) {
2581                 u32 action = le32_to_cpu(pa->code[index]);
2582                 u32 data = action & 0x0000ffff;
2583                 u32 regno = (action & 0x0fff0000) >> 16;
2584
2585                 if (!action)
2586                         break;
2587
2588                 switch(action & 0xf0000000) {
2589                 case PHY_READ:
2590                         predata = rtl_readphy(tp, regno);
2591                         count++;
2592                         index++;
2593                         break;
2594                 case PHY_DATA_OR:
2595                         predata |= data;
2596                         index++;
2597                         break;
2598                 case PHY_DATA_AND:
2599                         predata &= data;
2600                         index++;
2601                         break;
2602                 case PHY_BJMPN:
2603                         index -= regno;
2604                         break;
2605                 case PHY_MDIO_CHG:
2606                         if (data == 0) {
2607                                 ops->write = org.write;
2608                                 ops->read = org.read;
2609                         } else if (data == 1) {
2610                                 ops->write = mac_mcu_write;
2611                                 ops->read = mac_mcu_read;
2612                         }
2613
2614                         index++;
2615                         break;
2616                 case PHY_CLEAR_READCOUNT:
2617                         count = 0;
2618                         index++;
2619                         break;
2620                 case PHY_WRITE:
2621                         rtl_writephy(tp, regno, data);
2622                         index++;
2623                         break;
2624                 case PHY_READCOUNT_EQ_SKIP:
2625                         index += (count == data) ? 2 : 1;
2626                         break;
2627                 case PHY_COMP_EQ_SKIPN:
2628                         if (predata == data)
2629                                 index += regno;
2630                         index++;
2631                         break;
2632                 case PHY_COMP_NEQ_SKIPN:
2633                         if (predata != data)
2634                                 index += regno;
2635                         index++;
2636                         break;
2637                 case PHY_WRITE_PREVIOUS:
2638                         rtl_writephy(tp, regno, predata);
2639                         index++;
2640                         break;
2641                 case PHY_SKIPN:
2642                         index += regno + 1;
2643                         break;
2644                 case PHY_DELAY_MS:
2645                         mdelay(data);
2646                         index++;
2647                         break;
2648
2649                 default:
2650                         BUG();
2651                 }
2652         }
2653
2654         ops->write = org.write;
2655         ops->read = org.read;
2656 }
2657
2658 static void rtl_release_firmware(struct rtl8169_private *tp)
2659 {
2660         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2661                 release_firmware(tp->rtl_fw->fw);
2662                 kfree(tp->rtl_fw);
2663         }
2664         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2665 }
2666
2667 static void rtl_apply_firmware(struct rtl8169_private *tp)
2668 {
2669         struct rtl_fw *rtl_fw = tp->rtl_fw;
2670
2671         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2672         if (!IS_ERR_OR_NULL(rtl_fw))
2673                 rtl_phy_write_fw(tp, rtl_fw);
2674 }
2675
2676 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2677 {
2678         if (rtl_readphy(tp, reg) != val)
2679                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2680         else
2681                 rtl_apply_firmware(tp);
2682 }
2683
2684 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2685 {
2686         static const struct phy_reg phy_reg_init[] = {
2687                 { 0x1f, 0x0001 },
2688                 { 0x06, 0x006e },
2689                 { 0x08, 0x0708 },
2690                 { 0x15, 0x4000 },
2691                 { 0x18, 0x65c7 },
2692
2693                 { 0x1f, 0x0001 },
2694                 { 0x03, 0x00a1 },
2695                 { 0x02, 0x0008 },
2696                 { 0x01, 0x0120 },
2697                 { 0x00, 0x1000 },
2698                 { 0x04, 0x0800 },
2699                 { 0x04, 0x0000 },
2700
2701                 { 0x03, 0xff41 },
2702                 { 0x02, 0xdf60 },
2703                 { 0x01, 0x0140 },
2704                 { 0x00, 0x0077 },
2705                 { 0x04, 0x7800 },
2706                 { 0x04, 0x7000 },
2707
2708                 { 0x03, 0x802f },
2709                 { 0x02, 0x4f02 },
2710                 { 0x01, 0x0409 },
2711                 { 0x00, 0xf0f9 },
2712                 { 0x04, 0x9800 },
2713                 { 0x04, 0x9000 },
2714
2715                 { 0x03, 0xdf01 },
2716                 { 0x02, 0xdf20 },
2717                 { 0x01, 0xff95 },
2718                 { 0x00, 0xba00 },
2719                 { 0x04, 0xa800 },
2720                 { 0x04, 0xa000 },
2721
2722                 { 0x03, 0xff41 },
2723                 { 0x02, 0xdf20 },
2724                 { 0x01, 0x0140 },
2725                 { 0x00, 0x00bb },
2726                 { 0x04, 0xb800 },
2727                 { 0x04, 0xb000 },
2728
2729                 { 0x03, 0xdf41 },
2730                 { 0x02, 0xdc60 },
2731                 { 0x01, 0x6340 },
2732                 { 0x00, 0x007d },
2733                 { 0x04, 0xd800 },
2734                 { 0x04, 0xd000 },
2735
2736                 { 0x03, 0xdf01 },
2737                 { 0x02, 0xdf20 },
2738                 { 0x01, 0x100a },
2739                 { 0x00, 0xa0ff },
2740                 { 0x04, 0xf800 },
2741                 { 0x04, 0xf000 },
2742
2743                 { 0x1f, 0x0000 },
2744                 { 0x0b, 0x0000 },
2745                 { 0x00, 0x9200 }
2746         };
2747
2748         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2749 }
2750
2751 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2752 {
2753         static const struct phy_reg phy_reg_init[] = {
2754                 { 0x1f, 0x0002 },
2755                 { 0x01, 0x90d0 },
2756                 { 0x1f, 0x0000 }
2757         };
2758
2759         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2760 }
2761
2762 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2763 {
2764         struct pci_dev *pdev = tp->pci_dev;
2765
2766         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2767             (pdev->subsystem_device != 0xe000))
2768                 return;
2769
2770         rtl_writephy(tp, 0x1f, 0x0001);
2771         rtl_writephy(tp, 0x10, 0xf01b);
2772         rtl_writephy(tp, 0x1f, 0x0000);
2773 }
2774
2775 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2776 {
2777         static const struct phy_reg phy_reg_init[] = {
2778                 { 0x1f, 0x0001 },
2779                 { 0x04, 0x0000 },
2780                 { 0x03, 0x00a1 },
2781                 { 0x02, 0x0008 },
2782                 { 0x01, 0x0120 },
2783                 { 0x00, 0x1000 },
2784                 { 0x04, 0x0800 },
2785                 { 0x04, 0x9000 },
2786                 { 0x03, 0x802f },
2787                 { 0x02, 0x4f02 },
2788                 { 0x01, 0x0409 },
2789                 { 0x00, 0xf099 },
2790                 { 0x04, 0x9800 },
2791                 { 0x04, 0xa000 },
2792                 { 0x03, 0xdf01 },
2793                 { 0x02, 0xdf20 },
2794                 { 0x01, 0xff95 },
2795                 { 0x00, 0xba00 },
2796                 { 0x04, 0xa800 },
2797                 { 0x04, 0xf000 },
2798                 { 0x03, 0xdf01 },
2799                 { 0x02, 0xdf20 },
2800                 { 0x01, 0x101a },
2801                 { 0x00, 0xa0ff },
2802                 { 0x04, 0xf800 },
2803                 { 0x04, 0x0000 },
2804                 { 0x1f, 0x0000 },
2805
2806                 { 0x1f, 0x0001 },
2807                 { 0x10, 0xf41b },
2808                 { 0x14, 0xfb54 },
2809                 { 0x18, 0xf5c7 },
2810                 { 0x1f, 0x0000 },
2811
2812                 { 0x1f, 0x0001 },
2813                 { 0x17, 0x0cc0 },
2814                 { 0x1f, 0x0000 }
2815         };
2816
2817         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2818
2819         rtl8169scd_hw_phy_config_quirk(tp);
2820 }
2821
2822 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2823 {
2824         static const struct phy_reg phy_reg_init[] = {
2825                 { 0x1f, 0x0001 },
2826                 { 0x04, 0x0000 },
2827                 { 0x03, 0x00a1 },
2828                 { 0x02, 0x0008 },
2829                 { 0x01, 0x0120 },
2830                 { 0x00, 0x1000 },
2831                 { 0x04, 0x0800 },
2832                 { 0x04, 0x9000 },
2833                 { 0x03, 0x802f },
2834                 { 0x02, 0x4f02 },
2835                 { 0x01, 0x0409 },
2836                 { 0x00, 0xf099 },
2837                 { 0x04, 0x9800 },
2838                 { 0x04, 0xa000 },
2839                 { 0x03, 0xdf01 },
2840                 { 0x02, 0xdf20 },
2841                 { 0x01, 0xff95 },
2842                 { 0x00, 0xba00 },
2843                 { 0x04, 0xa800 },
2844                 { 0x04, 0xf000 },
2845                 { 0x03, 0xdf01 },
2846                 { 0x02, 0xdf20 },
2847                 { 0x01, 0x101a },
2848                 { 0x00, 0xa0ff },
2849                 { 0x04, 0xf800 },
2850                 { 0x04, 0x0000 },
2851                 { 0x1f, 0x0000 },
2852
2853                 { 0x1f, 0x0001 },
2854                 { 0x0b, 0x8480 },
2855                 { 0x1f, 0x0000 },
2856
2857                 { 0x1f, 0x0001 },
2858                 { 0x18, 0x67c7 },
2859                 { 0x04, 0x2000 },
2860                 { 0x03, 0x002f },
2861                 { 0x02, 0x4360 },
2862                 { 0x01, 0x0109 },
2863                 { 0x00, 0x3022 },
2864                 { 0x04, 0x2800 },
2865                 { 0x1f, 0x0000 },
2866
2867                 { 0x1f, 0x0001 },
2868                 { 0x17, 0x0cc0 },
2869                 { 0x1f, 0x0000 }
2870         };
2871
2872         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2873 }
2874
2875 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2876 {
2877         static const struct phy_reg phy_reg_init[] = {
2878                 { 0x10, 0xf41b },
2879                 { 0x1f, 0x0000 }
2880         };
2881
2882         rtl_writephy(tp, 0x1f, 0x0001);
2883         rtl_patchphy(tp, 0x16, 1 << 0);
2884
2885         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2886 }
2887
2888 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2889 {
2890         static const struct phy_reg phy_reg_init[] = {
2891                 { 0x1f, 0x0001 },
2892                 { 0x10, 0xf41b },
2893                 { 0x1f, 0x0000 }
2894         };
2895
2896         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2897 }
2898
2899 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2900 {
2901         static const struct phy_reg phy_reg_init[] = {
2902                 { 0x1f, 0x0000 },
2903                 { 0x1d, 0x0f00 },
2904                 { 0x1f, 0x0002 },
2905                 { 0x0c, 0x1ec8 },
2906                 { 0x1f, 0x0000 }
2907         };
2908
2909         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2910 }
2911
2912 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2913 {
2914         static const struct phy_reg phy_reg_init[] = {
2915                 { 0x1f, 0x0001 },
2916                 { 0x1d, 0x3d98 },
2917                 { 0x1f, 0x0000 }
2918         };
2919
2920         rtl_writephy(tp, 0x1f, 0x0000);
2921         rtl_patchphy(tp, 0x14, 1 << 5);
2922         rtl_patchphy(tp, 0x0d, 1 << 5);
2923
2924         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2925 }
2926
2927 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2928 {
2929         static const struct phy_reg phy_reg_init[] = {
2930                 { 0x1f, 0x0001 },
2931                 { 0x12, 0x2300 },
2932                 { 0x1f, 0x0002 },
2933                 { 0x00, 0x88d4 },
2934                 { 0x01, 0x82b1 },
2935                 { 0x03, 0x7002 },
2936                 { 0x08, 0x9e30 },
2937                 { 0x09, 0x01f0 },
2938                 { 0x0a, 0x5500 },
2939                 { 0x0c, 0x00c8 },
2940                 { 0x1f, 0x0003 },
2941                 { 0x12, 0xc096 },
2942                 { 0x16, 0x000a },
2943                 { 0x1f, 0x0000 },
2944                 { 0x1f, 0x0000 },
2945                 { 0x09, 0x2000 },
2946                 { 0x09, 0x0000 }
2947         };
2948
2949         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2950
2951         rtl_patchphy(tp, 0x14, 1 << 5);
2952         rtl_patchphy(tp, 0x0d, 1 << 5);
2953         rtl_writephy(tp, 0x1f, 0x0000);
2954 }
2955
2956 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2957 {
2958         static const struct phy_reg phy_reg_init[] = {
2959                 { 0x1f, 0x0001 },
2960                 { 0x12, 0x2300 },
2961                 { 0x03, 0x802f },
2962                 { 0x02, 0x4f02 },
2963                 { 0x01, 0x0409 },
2964                 { 0x00, 0xf099 },
2965                 { 0x04, 0x9800 },
2966                 { 0x04, 0x9000 },
2967                 { 0x1d, 0x3d98 },
2968                 { 0x1f, 0x0002 },
2969                 { 0x0c, 0x7eb8 },
2970                 { 0x06, 0x0761 },
2971                 { 0x1f, 0x0003 },
2972                 { 0x16, 0x0f0a },
2973                 { 0x1f, 0x0000 }
2974         };
2975
2976         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2977
2978         rtl_patchphy(tp, 0x16, 1 << 0);
2979         rtl_patchphy(tp, 0x14, 1 << 5);
2980         rtl_patchphy(tp, 0x0d, 1 << 5);
2981         rtl_writephy(tp, 0x1f, 0x0000);
2982 }
2983
2984 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2985 {
2986         static const struct phy_reg phy_reg_init[] = {
2987                 { 0x1f, 0x0001 },
2988                 { 0x12, 0x2300 },
2989                 { 0x1d, 0x3d98 },
2990                 { 0x1f, 0x0002 },
2991                 { 0x0c, 0x7eb8 },
2992                 { 0x06, 0x5461 },
2993                 { 0x1f, 0x0003 },
2994                 { 0x16, 0x0f0a },
2995                 { 0x1f, 0x0000 }
2996         };
2997
2998         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2999
3000         rtl_patchphy(tp, 0x16, 1 << 0);
3001         rtl_patchphy(tp, 0x14, 1 << 5);
3002         rtl_patchphy(tp, 0x0d, 1 << 5);
3003         rtl_writephy(tp, 0x1f, 0x0000);
3004 }
3005
3006 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3007 {
3008         rtl8168c_3_hw_phy_config(tp);
3009 }
3010
3011 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3012 {
3013         static const struct phy_reg phy_reg_init_0[] = {
3014                 /* Channel Estimation */
3015                 { 0x1f, 0x0001 },
3016                 { 0x06, 0x4064 },
3017                 { 0x07, 0x2863 },
3018                 { 0x08, 0x059c },
3019                 { 0x09, 0x26b4 },
3020                 { 0x0a, 0x6a19 },
3021                 { 0x0b, 0xdcc8 },
3022                 { 0x10, 0xf06d },
3023                 { 0x14, 0x7f68 },
3024                 { 0x18, 0x7fd9 },
3025                 { 0x1c, 0xf0ff },
3026                 { 0x1d, 0x3d9c },
3027                 { 0x1f, 0x0003 },
3028                 { 0x12, 0xf49f },
3029                 { 0x13, 0x070b },
3030                 { 0x1a, 0x05ad },
3031                 { 0x14, 0x94c0 },
3032
3033                 /*
3034                  * Tx Error Issue
3035                  * Enhance line driver power
3036                  */
3037                 { 0x1f, 0x0002 },
3038                 { 0x06, 0x5561 },
3039                 { 0x1f, 0x0005 },
3040                 { 0x05, 0x8332 },
3041                 { 0x06, 0x5561 },
3042
3043                 /*
3044                  * Can not link to 1Gbps with bad cable
3045                  * Decrease SNR threshold form 21.07dB to 19.04dB
3046                  */
3047                 { 0x1f, 0x0001 },
3048                 { 0x17, 0x0cc0 },
3049
3050                 { 0x1f, 0x0000 },
3051                 { 0x0d, 0xf880 }
3052         };
3053
3054         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3055
3056         /*
3057          * Rx Error Issue
3058          * Fine Tune Switching regulator parameter
3059          */
3060         rtl_writephy(tp, 0x1f, 0x0002);
3061         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3062         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3063
3064         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3065                 static const struct phy_reg phy_reg_init[] = {
3066                         { 0x1f, 0x0002 },
3067                         { 0x05, 0x669a },
3068                         { 0x1f, 0x0005 },
3069                         { 0x05, 0x8330 },
3070                         { 0x06, 0x669a },
3071                         { 0x1f, 0x0002 }
3072                 };
3073                 int val;
3074
3075                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3076
3077                 val = rtl_readphy(tp, 0x0d);
3078
3079                 if ((val & 0x00ff) != 0x006c) {
3080                         static const u32 set[] = {
3081                                 0x0065, 0x0066, 0x0067, 0x0068,
3082                                 0x0069, 0x006a, 0x006b, 0x006c
3083                         };
3084                         int i;
3085
3086                         rtl_writephy(tp, 0x1f, 0x0002);
3087
3088                         val &= 0xff00;
3089                         for (i = 0; i < ARRAY_SIZE(set); i++)
3090                                 rtl_writephy(tp, 0x0d, val | set[i]);
3091                 }
3092         } else {
3093                 static const struct phy_reg phy_reg_init[] = {
3094                         { 0x1f, 0x0002 },
3095                         { 0x05, 0x6662 },
3096                         { 0x1f, 0x0005 },
3097                         { 0x05, 0x8330 },
3098                         { 0x06, 0x6662 }
3099                 };
3100
3101                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3102         }
3103
3104         /* RSET couple improve */
3105         rtl_writephy(tp, 0x1f, 0x0002);
3106         rtl_patchphy(tp, 0x0d, 0x0300);
3107         rtl_patchphy(tp, 0x0f, 0x0010);
3108
3109         /* Fine tune PLL performance */
3110         rtl_writephy(tp, 0x1f, 0x0002);
3111         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3112         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3113
3114         rtl_writephy(tp, 0x1f, 0x0005);
3115         rtl_writephy(tp, 0x05, 0x001b);
3116
3117         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3118
3119         rtl_writephy(tp, 0x1f, 0x0000);
3120 }
3121
3122 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3123 {
3124         static const struct phy_reg phy_reg_init_0[] = {
3125                 /* Channel Estimation */
3126                 { 0x1f, 0x0001 },
3127                 { 0x06, 0x4064 },
3128                 { 0x07, 0x2863 },
3129                 { 0x08, 0x059c },
3130                 { 0x09, 0x26b4 },
3131                 { 0x0a, 0x6a19 },
3132                 { 0x0b, 0xdcc8 },
3133                 { 0x10, 0xf06d },
3134                 { 0x14, 0x7f68 },
3135                 { 0x18, 0x7fd9 },
3136                 { 0x1c, 0xf0ff },
3137                 { 0x1d, 0x3d9c },
3138                 { 0x1f, 0x0003 },
3139                 { 0x12, 0xf49f },
3140                 { 0x13, 0x070b },
3141                 { 0x1a, 0x05ad },
3142                 { 0x14, 0x94c0 },
3143
3144                 /*
3145                  * Tx Error Issue
3146                  * Enhance line driver power
3147                  */
3148                 { 0x1f, 0x0002 },
3149                 { 0x06, 0x5561 },
3150                 { 0x1f, 0x0005 },
3151                 { 0x05, 0x8332 },
3152                 { 0x06, 0x5561 },
3153
3154                 /*
3155                  * Can not link to 1Gbps with bad cable
3156                  * Decrease SNR threshold form 21.07dB to 19.04dB
3157                  */
3158                 { 0x1f, 0x0001 },
3159                 { 0x17, 0x0cc0 },
3160
3161                 { 0x1f, 0x0000 },
3162                 { 0x0d, 0xf880 }
3163         };
3164
3165         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3166
3167         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3168                 static const struct phy_reg phy_reg_init[] = {
3169                         { 0x1f, 0x0002 },
3170                         { 0x05, 0x669a },
3171                         { 0x1f, 0x0005 },
3172                         { 0x05, 0x8330 },
3173                         { 0x06, 0x669a },
3174
3175                         { 0x1f, 0x0002 }
3176                 };
3177                 int val;
3178
3179                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3180
3181                 val = rtl_readphy(tp, 0x0d);
3182                 if ((val & 0x00ff) != 0x006c) {
3183                         static const u32 set[] = {
3184                                 0x0065, 0x0066, 0x0067, 0x0068,
3185                                 0x0069, 0x006a, 0x006b, 0x006c
3186                         };
3187                         int i;
3188
3189                         rtl_writephy(tp, 0x1f, 0x0002);
3190
3191                         val &= 0xff00;
3192                         for (i = 0; i < ARRAY_SIZE(set); i++)
3193                                 rtl_writephy(tp, 0x0d, val | set[i]);
3194                 }
3195         } else {
3196                 static const struct phy_reg phy_reg_init[] = {
3197                         { 0x1f, 0x0002 },
3198                         { 0x05, 0x2642 },
3199                         { 0x1f, 0x0005 },
3200                         { 0x05, 0x8330 },
3201                         { 0x06, 0x2642 }
3202                 };
3203
3204                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3205         }
3206
3207         /* Fine tune PLL performance */
3208         rtl_writephy(tp, 0x1f, 0x0002);
3209         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3210         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3211
3212         /* Switching regulator Slew rate */
3213         rtl_writephy(tp, 0x1f, 0x0002);
3214         rtl_patchphy(tp, 0x0f, 0x0017);
3215
3216         rtl_writephy(tp, 0x1f, 0x0005);
3217         rtl_writephy(tp, 0x05, 0x001b);
3218
3219         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3220
3221         rtl_writephy(tp, 0x1f, 0x0000);
3222 }
3223
3224 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3225 {
3226         static const struct phy_reg phy_reg_init[] = {
3227                 { 0x1f, 0x0002 },
3228                 { 0x10, 0x0008 },
3229                 { 0x0d, 0x006c },
3230
3231                 { 0x1f, 0x0000 },
3232                 { 0x0d, 0xf880 },
3233
3234                 { 0x1f, 0x0001 },
3235                 { 0x17, 0x0cc0 },
3236
3237                 { 0x1f, 0x0001 },
3238                 { 0x0b, 0xa4d8 },
3239                 { 0x09, 0x281c },
3240                 { 0x07, 0x2883 },
3241                 { 0x0a, 0x6b35 },
3242                 { 0x1d, 0x3da4 },
3243                 { 0x1c, 0xeffd },
3244                 { 0x14, 0x7f52 },
3245                 { 0x18, 0x7fc6 },
3246                 { 0x08, 0x0601 },
3247                 { 0x06, 0x4063 },
3248                 { 0x10, 0xf074 },
3249                 { 0x1f, 0x0003 },
3250                 { 0x13, 0x0789 },
3251                 { 0x12, 0xf4bd },
3252                 { 0x1a, 0x04fd },
3253                 { 0x14, 0x84b0 },
3254                 { 0x1f, 0x0000 },
3255                 { 0x00, 0x9200 },
3256
3257                 { 0x1f, 0x0005 },
3258                 { 0x01, 0x0340 },
3259                 { 0x1f, 0x0001 },
3260                 { 0x04, 0x4000 },
3261                 { 0x03, 0x1d21 },
3262                 { 0x02, 0x0c32 },
3263                 { 0x01, 0x0200 },
3264                 { 0x00, 0x5554 },
3265                 { 0x04, 0x4800 },
3266                 { 0x04, 0x4000 },
3267                 { 0x04, 0xf000 },
3268                 { 0x03, 0xdf01 },
3269                 { 0x02, 0xdf20 },
3270                 { 0x01, 0x101a },
3271                 { 0x00, 0xa0ff },
3272                 { 0x04, 0xf800 },
3273                 { 0x04, 0xf000 },
3274                 { 0x1f, 0x0000 },
3275
3276                 { 0x1f, 0x0007 },
3277                 { 0x1e, 0x0023 },
3278                 { 0x16, 0x0000 },
3279                 { 0x1f, 0x0000 }
3280         };
3281
3282         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3283 }
3284
3285 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3286 {
3287         static const struct phy_reg phy_reg_init[] = {
3288                 { 0x1f, 0x0001 },
3289                 { 0x17, 0x0cc0 },
3290
3291                 { 0x1f, 0x0007 },
3292                 { 0x1e, 0x002d },
3293                 { 0x18, 0x0040 },
3294                 { 0x1f, 0x0000 }
3295         };
3296
3297         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3298         rtl_patchphy(tp, 0x0d, 1 << 5);
3299 }
3300
3301 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3302 {
3303         static const struct phy_reg phy_reg_init[] = {
3304                 /* Enable Delay cap */
3305                 { 0x1f, 0x0005 },
3306                 { 0x05, 0x8b80 },
3307                 { 0x06, 0xc896 },
3308                 { 0x1f, 0x0000 },
3309
3310                 /* Channel estimation fine tune */
3311                 { 0x1f, 0x0001 },
3312                 { 0x0b, 0x6c20 },
3313                 { 0x07, 0x2872 },
3314                 { 0x1c, 0xefff },
3315                 { 0x1f, 0x0003 },
3316                 { 0x14, 0x6420 },
3317                 { 0x1f, 0x0000 },
3318
3319                 /* Update PFM & 10M TX idle timer */
3320                 { 0x1f, 0x0007 },
3321                 { 0x1e, 0x002f },
3322                 { 0x15, 0x1919 },
3323                 { 0x1f, 0x0000 },
3324
3325                 { 0x1f, 0x0007 },
3326                 { 0x1e, 0x00ac },
3327                 { 0x18, 0x0006 },
3328                 { 0x1f, 0x0000 }
3329         };
3330
3331         rtl_apply_firmware(tp);
3332
3333         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3334
3335         /* DCO enable for 10M IDLE Power */
3336         rtl_writephy(tp, 0x1f, 0x0007);
3337         rtl_writephy(tp, 0x1e, 0x0023);
3338         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3339         rtl_writephy(tp, 0x1f, 0x0000);
3340
3341         /* For impedance matching */
3342         rtl_writephy(tp, 0x1f, 0x0002);
3343         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3344         rtl_writephy(tp, 0x1f, 0x0000);
3345
3346         /* PHY auto speed down */
3347         rtl_writephy(tp, 0x1f, 0x0007);
3348         rtl_writephy(tp, 0x1e, 0x002d);
3349         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3350         rtl_writephy(tp, 0x1f, 0x0000);
3351         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3352
3353         rtl_writephy(tp, 0x1f, 0x0005);
3354         rtl_writephy(tp, 0x05, 0x8b86);
3355         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3356         rtl_writephy(tp, 0x1f, 0x0000);
3357
3358         rtl_writephy(tp, 0x1f, 0x0005);
3359         rtl_writephy(tp, 0x05, 0x8b85);
3360         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3361         rtl_writephy(tp, 0x1f, 0x0007);
3362         rtl_writephy(tp, 0x1e, 0x0020);
3363         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3364         rtl_writephy(tp, 0x1f, 0x0006);
3365         rtl_writephy(tp, 0x00, 0x5a00);
3366         rtl_writephy(tp, 0x1f, 0x0000);
3367         rtl_writephy(tp, 0x0d, 0x0007);
3368         rtl_writephy(tp, 0x0e, 0x003c);
3369         rtl_writephy(tp, 0x0d, 0x4007);
3370         rtl_writephy(tp, 0x0e, 0x0000);
3371         rtl_writephy(tp, 0x0d, 0x0000);
3372 }
3373
3374 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3375 {
3376         const u16 w[] = {
3377                 addr[0] | (addr[1] << 8),
3378                 addr[2] | (addr[3] << 8),
3379                 addr[4] | (addr[5] << 8)
3380         };
3381         const struct exgmac_reg e[] = {
3382                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3383                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3384                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3385                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3386         };
3387
3388         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3389 }
3390
3391 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3392 {
3393         static const struct phy_reg phy_reg_init[] = {
3394                 /* Enable Delay cap */
3395                 { 0x1f, 0x0004 },
3396                 { 0x1f, 0x0007 },
3397                 { 0x1e, 0x00ac },
3398                 { 0x18, 0x0006 },
3399                 { 0x1f, 0x0002 },
3400                 { 0x1f, 0x0000 },
3401                 { 0x1f, 0x0000 },
3402
3403                 /* Channel estimation fine tune */
3404                 { 0x1f, 0x0003 },
3405                 { 0x09, 0xa20f },
3406                 { 0x1f, 0x0000 },
3407                 { 0x1f, 0x0000 },
3408
3409                 /* Green Setting */
3410                 { 0x1f, 0x0005 },
3411                 { 0x05, 0x8b5b },
3412                 { 0x06, 0x9222 },
3413                 { 0x05, 0x8b6d },
3414                 { 0x06, 0x8000 },
3415                 { 0x05, 0x8b76 },
3416                 { 0x06, 0x8000 },
3417                 { 0x1f, 0x0000 }
3418         };
3419
3420         rtl_apply_firmware(tp);
3421
3422         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3423
3424         /* For 4-corner performance improve */
3425         rtl_writephy(tp, 0x1f, 0x0005);
3426         rtl_writephy(tp, 0x05, 0x8b80);
3427         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3428         rtl_writephy(tp, 0x1f, 0x0000);
3429
3430         /* PHY auto speed down */
3431         rtl_writephy(tp, 0x1f, 0x0004);
3432         rtl_writephy(tp, 0x1f, 0x0007);
3433         rtl_writephy(tp, 0x1e, 0x002d);
3434         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3435         rtl_writephy(tp, 0x1f, 0x0002);
3436         rtl_writephy(tp, 0x1f, 0x0000);
3437         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3438
3439         /* improve 10M EEE waveform */
3440         rtl_writephy(tp, 0x1f, 0x0005);
3441         rtl_writephy(tp, 0x05, 0x8b86);
3442         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3443         rtl_writephy(tp, 0x1f, 0x0000);
3444
3445         /* Improve 2-pair detection performance */
3446         rtl_writephy(tp, 0x1f, 0x0005);
3447         rtl_writephy(tp, 0x05, 0x8b85);
3448         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3449         rtl_writephy(tp, 0x1f, 0x0000);
3450
3451         /* EEE setting */
3452         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3453         rtl_writephy(tp, 0x1f, 0x0005);
3454         rtl_writephy(tp, 0x05, 0x8b85);
3455         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3456         rtl_writephy(tp, 0x1f, 0x0004);
3457         rtl_writephy(tp, 0x1f, 0x0007);
3458         rtl_writephy(tp, 0x1e, 0x0020);
3459         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3460         rtl_writephy(tp, 0x1f, 0x0002);
3461         rtl_writephy(tp, 0x1f, 0x0000);
3462         rtl_writephy(tp, 0x0d, 0x0007);
3463         rtl_writephy(tp, 0x0e, 0x003c);
3464         rtl_writephy(tp, 0x0d, 0x4007);
3465         rtl_writephy(tp, 0x0e, 0x0000);
3466         rtl_writephy(tp, 0x0d, 0x0000);
3467
3468         /* Green feature */
3469         rtl_writephy(tp, 0x1f, 0x0003);
3470         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3471         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3472         rtl_writephy(tp, 0x1f, 0x0000);
3473
3474         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3475         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3476 }
3477
3478 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3479 {
3480         /* For 4-corner performance improve */
3481         rtl_writephy(tp, 0x1f, 0x0005);
3482         rtl_writephy(tp, 0x05, 0x8b80);
3483         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3484         rtl_writephy(tp, 0x1f, 0x0000);
3485
3486         /* PHY auto speed down */
3487         rtl_writephy(tp, 0x1f, 0x0007);
3488         rtl_writephy(tp, 0x1e, 0x002d);
3489         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3490         rtl_writephy(tp, 0x1f, 0x0000);
3491         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3492
3493         /* Improve 10M EEE waveform */
3494         rtl_writephy(tp, 0x1f, 0x0005);
3495         rtl_writephy(tp, 0x05, 0x8b86);
3496         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3497         rtl_writephy(tp, 0x1f, 0x0000);
3498 }
3499
3500 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3501 {
3502         static const struct phy_reg phy_reg_init[] = {
3503                 /* Channel estimation fine tune */
3504                 { 0x1f, 0x0003 },
3505                 { 0x09, 0xa20f },
3506                 { 0x1f, 0x0000 },
3507
3508                 /* Modify green table for giga & fnet */
3509                 { 0x1f, 0x0005 },
3510                 { 0x05, 0x8b55 },
3511                 { 0x06, 0x0000 },
3512                 { 0x05, 0x8b5e },
3513                 { 0x06, 0x0000 },
3514                 { 0x05, 0x8b67 },
3515                 { 0x06, 0x0000 },
3516                 { 0x05, 0x8b70 },
3517                 { 0x06, 0x0000 },
3518                 { 0x1f, 0x0000 },
3519                 { 0x1f, 0x0007 },
3520                 { 0x1e, 0x0078 },
3521                 { 0x17, 0x0000 },
3522                 { 0x19, 0x00fb },
3523                 { 0x1f, 0x0000 },
3524
3525                 /* Modify green table for 10M */
3526                 { 0x1f, 0x0005 },
3527                 { 0x05, 0x8b79 },
3528                 { 0x06, 0xaa00 },
3529                 { 0x1f, 0x0000 },
3530
3531                 /* Disable hiimpedance detection (RTCT) */
3532                 { 0x1f, 0x0003 },
3533                 { 0x01, 0x328a },
3534                 { 0x1f, 0x0000 }
3535         };
3536
3537         rtl_apply_firmware(tp);
3538
3539         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3540
3541         rtl8168f_hw_phy_config(tp);
3542
3543         /* Improve 2-pair detection performance */
3544         rtl_writephy(tp, 0x1f, 0x0005);
3545         rtl_writephy(tp, 0x05, 0x8b85);
3546         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3547         rtl_writephy(tp, 0x1f, 0x0000);
3548 }
3549
3550 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3551 {
3552         rtl_apply_firmware(tp);
3553
3554         rtl8168f_hw_phy_config(tp);
3555 }
3556
3557 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3558 {
3559         static const struct phy_reg phy_reg_init[] = {
3560                 /* Channel estimation fine tune */
3561                 { 0x1f, 0x0003 },
3562                 { 0x09, 0xa20f },
3563                 { 0x1f, 0x0000 },
3564
3565                 /* Modify green table for giga & fnet */
3566                 { 0x1f, 0x0005 },
3567                 { 0x05, 0x8b55 },
3568                 { 0x06, 0x0000 },
3569                 { 0x05, 0x8b5e },
3570                 { 0x06, 0x0000 },
3571                 { 0x05, 0x8b67 },
3572                 { 0x06, 0x0000 },
3573                 { 0x05, 0x8b70 },
3574                 { 0x06, 0x0000 },
3575                 { 0x1f, 0x0000 },
3576                 { 0x1f, 0x0007 },
3577                 { 0x1e, 0x0078 },
3578                 { 0x17, 0x0000 },
3579                 { 0x19, 0x00aa },
3580                 { 0x1f, 0x0000 },
3581
3582                 /* Modify green table for 10M */
3583                 { 0x1f, 0x0005 },
3584                 { 0x05, 0x8b79 },
3585                 { 0x06, 0xaa00 },
3586                 { 0x1f, 0x0000 },
3587
3588                 /* Disable hiimpedance detection (RTCT) */
3589                 { 0x1f, 0x0003 },
3590                 { 0x01, 0x328a },
3591                 { 0x1f, 0x0000 }
3592         };
3593
3594
3595         rtl_apply_firmware(tp);
3596
3597         rtl8168f_hw_phy_config(tp);
3598
3599         /* Improve 2-pair detection performance */
3600         rtl_writephy(tp, 0x1f, 0x0005);
3601         rtl_writephy(tp, 0x05, 0x8b85);
3602         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3603         rtl_writephy(tp, 0x1f, 0x0000);
3604
3605         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3606
3607         /* Modify green table for giga */
3608         rtl_writephy(tp, 0x1f, 0x0005);
3609         rtl_writephy(tp, 0x05, 0x8b54);
3610         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3611         rtl_writephy(tp, 0x05, 0x8b5d);
3612         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3613         rtl_writephy(tp, 0x05, 0x8a7c);
3614         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3615         rtl_writephy(tp, 0x05, 0x8a7f);
3616         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3617         rtl_writephy(tp, 0x05, 0x8a82);
3618         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3619         rtl_writephy(tp, 0x05, 0x8a85);
3620         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3621         rtl_writephy(tp, 0x05, 0x8a88);
3622         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3623         rtl_writephy(tp, 0x1f, 0x0000);
3624
3625         /* uc same-seed solution */
3626         rtl_writephy(tp, 0x1f, 0x0005);
3627         rtl_writephy(tp, 0x05, 0x8b85);
3628         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3629         rtl_writephy(tp, 0x1f, 0x0000);
3630
3631         /* eee setting */
3632         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3633         rtl_writephy(tp, 0x1f, 0x0005);
3634         rtl_writephy(tp, 0x05, 0x8b85);
3635         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3636         rtl_writephy(tp, 0x1f, 0x0004);
3637         rtl_writephy(tp, 0x1f, 0x0007);
3638         rtl_writephy(tp, 0x1e, 0x0020);
3639         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3640         rtl_writephy(tp, 0x1f, 0x0000);
3641         rtl_writephy(tp, 0x0d, 0x0007);
3642         rtl_writephy(tp, 0x0e, 0x003c);
3643         rtl_writephy(tp, 0x0d, 0x4007);
3644         rtl_writephy(tp, 0x0e, 0x0000);
3645         rtl_writephy(tp, 0x0d, 0x0000);
3646
3647         /* Green feature */
3648         rtl_writephy(tp, 0x1f, 0x0003);
3649         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3650         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3651         rtl_writephy(tp, 0x1f, 0x0000);
3652 }
3653
3654 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3655 {
3656         rtl_apply_firmware(tp);
3657
3658         rtl_writephy(tp, 0x1f, 0x0a46);
3659         if (rtl_readphy(tp, 0x10) & 0x0100) {
3660                 rtl_writephy(tp, 0x1f, 0x0bcc);
3661                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3662         } else {
3663                 rtl_writephy(tp, 0x1f, 0x0bcc);
3664                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3665         }
3666
3667         rtl_writephy(tp, 0x1f, 0x0a46);
3668         if (rtl_readphy(tp, 0x13) & 0x0100) {
3669                 rtl_writephy(tp, 0x1f, 0x0c41);
3670                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3671         } else {
3672                 rtl_writephy(tp, 0x1f, 0x0c41);
3673                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3674         }
3675
3676         /* Enable PHY auto speed down */
3677         rtl_writephy(tp, 0x1f, 0x0a44);
3678         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3679
3680         rtl_writephy(tp, 0x1f, 0x0bcc);
3681         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3682         rtl_writephy(tp, 0x1f, 0x0a44);
3683         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3684         rtl_writephy(tp, 0x1f, 0x0a43);
3685         rtl_writephy(tp, 0x13, 0x8084);
3686         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3687         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3688
3689         /* EEE auto-fallback function */
3690         rtl_writephy(tp, 0x1f, 0x0a4b);
3691         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3692
3693         /* Enable UC LPF tune function */
3694         rtl_writephy(tp, 0x1f, 0x0a43);
3695         rtl_writephy(tp, 0x13, 0x8012);
3696         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3697
3698         rtl_writephy(tp, 0x1f, 0x0c42);
3699         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3700
3701         /* Improve SWR Efficiency */
3702         rtl_writephy(tp, 0x1f, 0x0bcd);
3703         rtl_writephy(tp, 0x14, 0x5065);
3704         rtl_writephy(tp, 0x14, 0xd065);
3705         rtl_writephy(tp, 0x1f, 0x0bc8);
3706         rtl_writephy(tp, 0x11, 0x5655);
3707         rtl_writephy(tp, 0x1f, 0x0bcd);
3708         rtl_writephy(tp, 0x14, 0x1065);
3709         rtl_writephy(tp, 0x14, 0x9065);
3710         rtl_writephy(tp, 0x14, 0x1065);
3711
3712         /* Check ALDPS bit, disable it if enabled */
3713         rtl_writephy(tp, 0x1f, 0x0a43);
3714         if (rtl_readphy(tp, 0x10) & 0x0004)
3715                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3716
3717         rtl_writephy(tp, 0x1f, 0x0000);
3718 }
3719
3720 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3721 {
3722         rtl_apply_firmware(tp);
3723 }
3724
3725 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3726 {
3727         u16 dout_tapbin;
3728         u32 data;
3729
3730         rtl_apply_firmware(tp);
3731
3732         /* CHN EST parameters adjust - giga master */
3733         rtl_writephy(tp, 0x1f, 0x0a43);
3734         rtl_writephy(tp, 0x13, 0x809b);
3735         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3736         rtl_writephy(tp, 0x13, 0x80a2);
3737         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3738         rtl_writephy(tp, 0x13, 0x80a4);
3739         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3740         rtl_writephy(tp, 0x13, 0x809c);
3741         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3742         rtl_writephy(tp, 0x1f, 0x0000);
3743
3744         /* CHN EST parameters adjust - giga slave */
3745         rtl_writephy(tp, 0x1f, 0x0a43);
3746         rtl_writephy(tp, 0x13, 0x80ad);
3747         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3748         rtl_writephy(tp, 0x13, 0x80b4);
3749         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3750         rtl_writephy(tp, 0x13, 0x80ac);
3751         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3752         rtl_writephy(tp, 0x1f, 0x0000);
3753
3754         /* CHN EST parameters adjust - fnet */
3755         rtl_writephy(tp, 0x1f, 0x0a43);
3756         rtl_writephy(tp, 0x13, 0x808e);
3757         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3758         rtl_writephy(tp, 0x13, 0x8090);
3759         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3760         rtl_writephy(tp, 0x13, 0x8092);
3761         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3762         rtl_writephy(tp, 0x1f, 0x0000);
3763
3764         /* enable R-tune & PGA-retune function */
3765         dout_tapbin = 0;
3766         rtl_writephy(tp, 0x1f, 0x0a46);
3767         data = rtl_readphy(tp, 0x13);
3768         data &= 3;
3769         data <<= 2;
3770         dout_tapbin |= data;
3771         data = rtl_readphy(tp, 0x12);
3772         data &= 0xc000;
3773         data >>= 14;
3774         dout_tapbin |= data;
3775         dout_tapbin = ~(dout_tapbin^0x08);
3776         dout_tapbin <<= 12;
3777         dout_tapbin &= 0xf000;
3778         rtl_writephy(tp, 0x1f, 0x0a43);
3779         rtl_writephy(tp, 0x13, 0x827a);
3780         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3781         rtl_writephy(tp, 0x13, 0x827b);
3782         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3783         rtl_writephy(tp, 0x13, 0x827c);
3784         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3785         rtl_writephy(tp, 0x13, 0x827d);
3786         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3787
3788         rtl_writephy(tp, 0x1f, 0x0a43);
3789         rtl_writephy(tp, 0x13, 0x0811);
3790         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3791         rtl_writephy(tp, 0x1f, 0x0a42);
3792         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3793         rtl_writephy(tp, 0x1f, 0x0000);
3794
3795         /* enable GPHY 10M */
3796         rtl_writephy(tp, 0x1f, 0x0a44);
3797         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3798         rtl_writephy(tp, 0x1f, 0x0000);
3799
3800         /* SAR ADC performance */
3801         rtl_writephy(tp, 0x1f, 0x0bca);
3802         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3803         rtl_writephy(tp, 0x1f, 0x0000);
3804
3805         rtl_writephy(tp, 0x1f, 0x0a43);
3806         rtl_writephy(tp, 0x13, 0x803f);
3807         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3808         rtl_writephy(tp, 0x13, 0x8047);
3809         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3810         rtl_writephy(tp, 0x13, 0x804f);
3811         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3812         rtl_writephy(tp, 0x13, 0x8057);
3813         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3814         rtl_writephy(tp, 0x13, 0x805f);
3815         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3816         rtl_writephy(tp, 0x13, 0x8067);
3817         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3818         rtl_writephy(tp, 0x13, 0x806f);
3819         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3820         rtl_writephy(tp, 0x1f, 0x0000);
3821
3822         /* disable phy pfm mode */
3823         rtl_writephy(tp, 0x1f, 0x0a44);
3824         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3825         rtl_writephy(tp, 0x1f, 0x0000);
3826
3827         /* Check ALDPS bit, disable it if enabled */
3828         rtl_writephy(tp, 0x1f, 0x0a43);
3829         if (rtl_readphy(tp, 0x10) & 0x0004)
3830                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3831
3832         rtl_writephy(tp, 0x1f, 0x0000);
3833 }
3834
3835 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3836 {
3837         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3838         u16 rlen;
3839         u32 data;
3840
3841         rtl_apply_firmware(tp);
3842
3843         /* CHIN EST parameter update */
3844         rtl_writephy(tp, 0x1f, 0x0a43);
3845         rtl_writephy(tp, 0x13, 0x808a);
3846         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3847         rtl_writephy(tp, 0x1f, 0x0000);
3848
3849         /* enable R-tune & PGA-retune function */
3850         rtl_writephy(tp, 0x1f, 0x0a43);
3851         rtl_writephy(tp, 0x13, 0x0811);
3852         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3853         rtl_writephy(tp, 0x1f, 0x0a42);
3854         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3855         rtl_writephy(tp, 0x1f, 0x0000);
3856
3857         /* enable GPHY 10M */
3858         rtl_writephy(tp, 0x1f, 0x0a44);
3859         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3860         rtl_writephy(tp, 0x1f, 0x0000);
3861
3862         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3863         data = r8168_mac_ocp_read(tp, 0xdd02);
3864         ioffset_p3 = ((data & 0x80)>>7);
3865         ioffset_p3 <<= 3;
3866
3867         data = r8168_mac_ocp_read(tp, 0xdd00);
3868         ioffset_p3 |= ((data & (0xe000))>>13);
3869         ioffset_p2 = ((data & (0x1e00))>>9);
3870         ioffset_p1 = ((data & (0x01e0))>>5);
3871         ioffset_p0 = ((data & 0x0010)>>4);
3872         ioffset_p0 <<= 3;
3873         ioffset_p0 |= (data & (0x07));
3874         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3875
3876         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3877             (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3878                 rtl_writephy(tp, 0x1f, 0x0bcf);
3879                 rtl_writephy(tp, 0x16, data);
3880                 rtl_writephy(tp, 0x1f, 0x0000);
3881         }
3882
3883         /* Modify rlen (TX LPF corner frequency) level */
3884         rtl_writephy(tp, 0x1f, 0x0bcd);
3885         data = rtl_readphy(tp, 0x16);
3886         data &= 0x000f;
3887         rlen = 0;
3888         if (data > 3)
3889                 rlen = data - 3;
3890         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3891         rtl_writephy(tp, 0x17, data);
3892         rtl_writephy(tp, 0x1f, 0x0bcd);
3893         rtl_writephy(tp, 0x1f, 0x0000);
3894
3895         /* disable phy pfm mode */
3896         rtl_writephy(tp, 0x1f, 0x0a44);
3897         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3898         rtl_writephy(tp, 0x1f, 0x0000);
3899
3900         /* Check ALDPS bit, disable it if enabled */
3901         rtl_writephy(tp, 0x1f, 0x0a43);
3902         if (rtl_readphy(tp, 0x10) & 0x0004)
3903                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3904
3905         rtl_writephy(tp, 0x1f, 0x0000);
3906 }
3907
3908 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3909 {
3910         /* Enable PHY auto speed down */
3911         rtl_writephy(tp, 0x1f, 0x0a44);
3912         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3913         rtl_writephy(tp, 0x1f, 0x0000);
3914
3915         /* patch 10M & ALDPS */
3916         rtl_writephy(tp, 0x1f, 0x0bcc);
3917         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3918         rtl_writephy(tp, 0x1f, 0x0a44);
3919         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3920         rtl_writephy(tp, 0x1f, 0x0a43);
3921         rtl_writephy(tp, 0x13, 0x8084);
3922         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3923         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3924         rtl_writephy(tp, 0x1f, 0x0000);
3925
3926         /* Enable EEE auto-fallback function */
3927         rtl_writephy(tp, 0x1f, 0x0a4b);
3928         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3929         rtl_writephy(tp, 0x1f, 0x0000);
3930
3931         /* Enable UC LPF tune function */
3932         rtl_writephy(tp, 0x1f, 0x0a43);
3933         rtl_writephy(tp, 0x13, 0x8012);
3934         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3935         rtl_writephy(tp, 0x1f, 0x0000);
3936
3937         /* set rg_sel_sdm_rate */
3938         rtl_writephy(tp, 0x1f, 0x0c42);
3939         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3940         rtl_writephy(tp, 0x1f, 0x0000);
3941
3942         /* Check ALDPS bit, disable it if enabled */
3943         rtl_writephy(tp, 0x1f, 0x0a43);
3944         if (rtl_readphy(tp, 0x10) & 0x0004)
3945                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3946
3947         rtl_writephy(tp, 0x1f, 0x0000);
3948 }
3949
3950 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3951 {
3952         /* patch 10M & ALDPS */
3953         rtl_writephy(tp, 0x1f, 0x0bcc);
3954         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3955         rtl_writephy(tp, 0x1f, 0x0a44);
3956         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3957         rtl_writephy(tp, 0x1f, 0x0a43);
3958         rtl_writephy(tp, 0x13, 0x8084);
3959         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3960         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3961         rtl_writephy(tp, 0x1f, 0x0000);
3962
3963         /* Enable UC LPF tune function */
3964         rtl_writephy(tp, 0x1f, 0x0a43);
3965         rtl_writephy(tp, 0x13, 0x8012);
3966         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3967         rtl_writephy(tp, 0x1f, 0x0000);
3968
3969         /* Set rg_sel_sdm_rate */
3970         rtl_writephy(tp, 0x1f, 0x0c42);
3971         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3972         rtl_writephy(tp, 0x1f, 0x0000);
3973
3974         /* Channel estimation parameters */
3975         rtl_writephy(tp, 0x1f, 0x0a43);
3976         rtl_writephy(tp, 0x13, 0x80f3);
3977         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3978         rtl_writephy(tp, 0x13, 0x80f0);
3979         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3980         rtl_writephy(tp, 0x13, 0x80ef);
3981         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3982         rtl_writephy(tp, 0x13, 0x80f6);
3983         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3984         rtl_writephy(tp, 0x13, 0x80ec);
3985         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3986         rtl_writephy(tp, 0x13, 0x80ed);
3987         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3988         rtl_writephy(tp, 0x13, 0x80f2);
3989         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3990         rtl_writephy(tp, 0x13, 0x80f4);
3991         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3992         rtl_writephy(tp, 0x1f, 0x0a43);
3993         rtl_writephy(tp, 0x13, 0x8110);
3994         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3995         rtl_writephy(tp, 0x13, 0x810f);
3996         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3997         rtl_writephy(tp, 0x13, 0x8111);
3998         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3999         rtl_writephy(tp, 0x13, 0x8113);
4000         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4001         rtl_writephy(tp, 0x13, 0x8115);
4002         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4003         rtl_writephy(tp, 0x13, 0x810e);
4004         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4005         rtl_writephy(tp, 0x13, 0x810c);
4006         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4007         rtl_writephy(tp, 0x13, 0x810b);
4008         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4009         rtl_writephy(tp, 0x1f, 0x0a43);
4010         rtl_writephy(tp, 0x13, 0x80d1);
4011         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4012         rtl_writephy(tp, 0x13, 0x80cd);
4013         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4014         rtl_writephy(tp, 0x13, 0x80d3);
4015         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4016         rtl_writephy(tp, 0x13, 0x80d5);
4017         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4018         rtl_writephy(tp, 0x13, 0x80d7);
4019         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4020
4021         /* Force PWM-mode */
4022         rtl_writephy(tp, 0x1f, 0x0bcd);
4023         rtl_writephy(tp, 0x14, 0x5065);
4024         rtl_writephy(tp, 0x14, 0xd065);
4025         rtl_writephy(tp, 0x1f, 0x0bc8);
4026         rtl_writephy(tp, 0x12, 0x00ed);
4027         rtl_writephy(tp, 0x1f, 0x0bcd);
4028         rtl_writephy(tp, 0x14, 0x1065);
4029         rtl_writephy(tp, 0x14, 0x9065);
4030         rtl_writephy(tp, 0x14, 0x1065);
4031         rtl_writephy(tp, 0x1f, 0x0000);
4032
4033         /* Check ALDPS bit, disable it if enabled */
4034         rtl_writephy(tp, 0x1f, 0x0a43);
4035         if (rtl_readphy(tp, 0x10) & 0x0004)
4036                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4037
4038         rtl_writephy(tp, 0x1f, 0x0000);
4039 }
4040
4041 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4042 {
4043         static const struct phy_reg phy_reg_init[] = {
4044                 { 0x1f, 0x0003 },
4045                 { 0x08, 0x441d },
4046                 { 0x01, 0x9100 },
4047                 { 0x1f, 0x0000 }
4048         };
4049
4050         rtl_writephy(tp, 0x1f, 0x0000);
4051         rtl_patchphy(tp, 0x11, 1 << 12);
4052         rtl_patchphy(tp, 0x19, 1 << 13);
4053         rtl_patchphy(tp, 0x10, 1 << 15);
4054
4055         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4056 }
4057
4058 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4059 {
4060         static const struct phy_reg phy_reg_init[] = {
4061                 { 0x1f, 0x0005 },
4062                 { 0x1a, 0x0000 },
4063                 { 0x1f, 0x0000 },
4064
4065                 { 0x1f, 0x0004 },
4066                 { 0x1c, 0x0000 },
4067                 { 0x1f, 0x0000 },
4068
4069                 { 0x1f, 0x0001 },
4070                 { 0x15, 0x7701 },
4071                 { 0x1f, 0x0000 }
4072         };
4073
4074         /* Disable ALDPS before ram code */
4075         rtl_writephy(tp, 0x1f, 0x0000);
4076         rtl_writephy(tp, 0x18, 0x0310);
4077         msleep(100);
4078
4079         rtl_apply_firmware(tp);
4080
4081         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4082 }
4083
4084 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4085 {
4086         /* Disable ALDPS before setting firmware */
4087         rtl_writephy(tp, 0x1f, 0x0000);
4088         rtl_writephy(tp, 0x18, 0x0310);
4089         msleep(20);
4090
4091         rtl_apply_firmware(tp);
4092
4093         /* EEE setting */
4094         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4095         rtl_writephy(tp, 0x1f, 0x0004);
4096         rtl_writephy(tp, 0x10, 0x401f);
4097         rtl_writephy(tp, 0x19, 0x7030);
4098         rtl_writephy(tp, 0x1f, 0x0000);
4099 }
4100
4101 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4102 {
4103         static const struct phy_reg phy_reg_init[] = {
4104                 { 0x1f, 0x0004 },
4105                 { 0x10, 0xc07f },
4106                 { 0x19, 0x7030 },
4107                 { 0x1f, 0x0000 }
4108         };
4109
4110         /* Disable ALDPS before ram code */
4111         rtl_writephy(tp, 0x1f, 0x0000);
4112         rtl_writephy(tp, 0x18, 0x0310);
4113         msleep(100);
4114
4115         rtl_apply_firmware(tp);
4116
4117         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4118         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4119
4120         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4121 }
4122
4123 static void rtl_hw_phy_config(struct net_device *dev)
4124 {
4125         struct rtl8169_private *tp = netdev_priv(dev);
4126
4127         rtl8169_print_mac_version(tp);
4128
4129         switch (tp->mac_version) {
4130         case RTL_GIGA_MAC_VER_01:
4131                 break;
4132         case RTL_GIGA_MAC_VER_02:
4133         case RTL_GIGA_MAC_VER_03:
4134                 rtl8169s_hw_phy_config(tp);
4135                 break;
4136         case RTL_GIGA_MAC_VER_04:
4137                 rtl8169sb_hw_phy_config(tp);
4138                 break;
4139         case RTL_GIGA_MAC_VER_05:
4140                 rtl8169scd_hw_phy_config(tp);
4141                 break;
4142         case RTL_GIGA_MAC_VER_06:
4143                 rtl8169sce_hw_phy_config(tp);
4144                 break;
4145         case RTL_GIGA_MAC_VER_07:
4146         case RTL_GIGA_MAC_VER_08:
4147         case RTL_GIGA_MAC_VER_09:
4148                 rtl8102e_hw_phy_config(tp);
4149                 break;
4150         case RTL_GIGA_MAC_VER_11:
4151                 rtl8168bb_hw_phy_config(tp);
4152                 break;
4153         case RTL_GIGA_MAC_VER_12:
4154                 rtl8168bef_hw_phy_config(tp);
4155                 break;
4156         case RTL_GIGA_MAC_VER_17:
4157                 rtl8168bef_hw_phy_config(tp);
4158                 break;
4159         case RTL_GIGA_MAC_VER_18:
4160                 rtl8168cp_1_hw_phy_config(tp);
4161                 break;
4162         case RTL_GIGA_MAC_VER_19:
4163                 rtl8168c_1_hw_phy_config(tp);
4164                 break;
4165         case RTL_GIGA_MAC_VER_20:
4166                 rtl8168c_2_hw_phy_config(tp);
4167                 break;
4168         case RTL_GIGA_MAC_VER_21:
4169                 rtl8168c_3_hw_phy_config(tp);
4170                 break;
4171         case RTL_GIGA_MAC_VER_22:
4172                 rtl8168c_4_hw_phy_config(tp);
4173                 break;
4174         case RTL_GIGA_MAC_VER_23:
4175         case RTL_GIGA_MAC_VER_24:
4176                 rtl8168cp_2_hw_phy_config(tp);
4177                 break;
4178         case RTL_GIGA_MAC_VER_25:
4179                 rtl8168d_1_hw_phy_config(tp);
4180                 break;
4181         case RTL_GIGA_MAC_VER_26:
4182                 rtl8168d_2_hw_phy_config(tp);
4183                 break;
4184         case RTL_GIGA_MAC_VER_27:
4185                 rtl8168d_3_hw_phy_config(tp);
4186                 break;
4187         case RTL_GIGA_MAC_VER_28:
4188                 rtl8168d_4_hw_phy_config(tp);
4189                 break;
4190         case RTL_GIGA_MAC_VER_29:
4191         case RTL_GIGA_MAC_VER_30:
4192                 rtl8105e_hw_phy_config(tp);
4193                 break;
4194         case RTL_GIGA_MAC_VER_31:
4195                 /* None. */
4196                 break;
4197         case RTL_GIGA_MAC_VER_32:
4198         case RTL_GIGA_MAC_VER_33:
4199                 rtl8168e_1_hw_phy_config(tp);
4200                 break;
4201         case RTL_GIGA_MAC_VER_34:
4202                 rtl8168e_2_hw_phy_config(tp);
4203                 break;
4204         case RTL_GIGA_MAC_VER_35:
4205                 rtl8168f_1_hw_phy_config(tp);
4206                 break;
4207         case RTL_GIGA_MAC_VER_36:
4208                 rtl8168f_2_hw_phy_config(tp);
4209                 break;
4210
4211         case RTL_GIGA_MAC_VER_37:
4212                 rtl8402_hw_phy_config(tp);
4213                 break;
4214
4215         case RTL_GIGA_MAC_VER_38:
4216                 rtl8411_hw_phy_config(tp);
4217                 break;
4218
4219         case RTL_GIGA_MAC_VER_39:
4220                 rtl8106e_hw_phy_config(tp);
4221                 break;
4222
4223         case RTL_GIGA_MAC_VER_40:
4224                 rtl8168g_1_hw_phy_config(tp);
4225                 break;
4226         case RTL_GIGA_MAC_VER_42:
4227         case RTL_GIGA_MAC_VER_43:
4228         case RTL_GIGA_MAC_VER_44:
4229                 rtl8168g_2_hw_phy_config(tp);
4230                 break;
4231         case RTL_GIGA_MAC_VER_45:
4232         case RTL_GIGA_MAC_VER_47:
4233                 rtl8168h_1_hw_phy_config(tp);
4234                 break;
4235         case RTL_GIGA_MAC_VER_46:
4236         case RTL_GIGA_MAC_VER_48:
4237                 rtl8168h_2_hw_phy_config(tp);
4238                 break;
4239
4240         case RTL_GIGA_MAC_VER_49:
4241                 rtl8168ep_1_hw_phy_config(tp);
4242                 break;
4243         case RTL_GIGA_MAC_VER_50:
4244         case RTL_GIGA_MAC_VER_51:
4245                 rtl8168ep_2_hw_phy_config(tp);
4246                 break;
4247
4248         case RTL_GIGA_MAC_VER_41:
4249         default:
4250                 break;
4251         }
4252 }
4253
4254 static void rtl_phy_work(struct rtl8169_private *tp)
4255 {
4256         struct timer_list *timer = &tp->timer;
4257         void __iomem *ioaddr = tp->mmio_addr;
4258         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4259
4260         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4261
4262         if (tp->phy_reset_pending(tp)) {
4263                 /*
4264                  * A busy loop could burn quite a few cycles on nowadays CPU.
4265                  * Let's delay the execution of the timer for a few ticks.
4266                  */
4267                 timeout = HZ/10;
4268                 goto out_mod_timer;
4269         }
4270
4271         if (tp->link_ok(ioaddr))
4272                 return;
4273
4274         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4275
4276         tp->phy_reset_enable(tp);
4277
4278 out_mod_timer:
4279         mod_timer(timer, jiffies + timeout);
4280 }
4281
4282 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4283 {
4284         if (!test_and_set_bit(flag, tp->wk.flags))
4285                 schedule_work(&tp->wk.work);
4286 }
4287
4288 static void rtl8169_phy_timer(unsigned long __opaque)
4289 {
4290         struct net_device *dev = (struct net_device *)__opaque;
4291         struct rtl8169_private *tp = netdev_priv(dev);
4292
4293         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4294 }
4295
4296 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4297                                   void __iomem *ioaddr)
4298 {
4299         iounmap(ioaddr);
4300         pci_release_regions(pdev);
4301         pci_clear_mwi(pdev);
4302         pci_disable_device(pdev);
4303         free_netdev(dev);
4304 }
4305
4306 DECLARE_RTL_COND(rtl_phy_reset_cond)
4307 {
4308         return tp->phy_reset_pending(tp);
4309 }
4310
4311 static void rtl8169_phy_reset(struct net_device *dev,
4312                               struct rtl8169_private *tp)
4313 {
4314         tp->phy_reset_enable(tp);
4315         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4316 }
4317
4318 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4319 {
4320         void __iomem *ioaddr = tp->mmio_addr;
4321
4322         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4323             (RTL_R8(PHYstatus) & TBI_Enable);
4324 }
4325
4326 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4327 {
4328         void __iomem *ioaddr = tp->mmio_addr;
4329
4330         rtl_hw_phy_config(dev);
4331
4332         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4333                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4334                 RTL_W8(0x82, 0x01);
4335         }
4336
4337         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4338
4339         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4340                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4341
4342         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4343                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4344                 RTL_W8(0x82, 0x01);
4345                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4346                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4347         }
4348
4349         rtl8169_phy_reset(dev, tp);
4350
4351         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4352                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4353                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4354                           (tp->mii.supports_gmii ?
4355                            ADVERTISED_1000baseT_Half |
4356                            ADVERTISED_1000baseT_Full : 0));
4357
4358         if (rtl_tbi_enabled(tp))
4359                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4360 }
4361
4362 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4363 {
4364         void __iomem *ioaddr = tp->mmio_addr;
4365
4366         rtl_lock_work(tp);
4367
4368         RTL_W8(Cfg9346, Cfg9346_Unlock);
4369
4370         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4371         RTL_R32(MAC4);
4372
4373         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4374         RTL_R32(MAC0);
4375
4376         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4377                 rtl_rar_exgmac_set(tp, addr);
4378
4379         RTL_W8(Cfg9346, Cfg9346_Lock);
4380
4381         rtl_unlock_work(tp);
4382 }
4383
4384 static int rtl_set_mac_address(struct net_device *dev, void *p)
4385 {
4386         struct rtl8169_private *tp = netdev_priv(dev);
4387         struct sockaddr *addr = p;
4388
4389         if (!is_valid_ether_addr(addr->sa_data))
4390                 return -EADDRNOTAVAIL;
4391
4392         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4393
4394         rtl_rar_set(tp, dev->dev_addr);
4395
4396         return 0;
4397 }
4398
4399 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4400 {
4401         struct rtl8169_private *tp = netdev_priv(dev);
4402         struct mii_ioctl_data *data = if_mii(ifr);
4403
4404         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4405 }
4406
4407 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4408                           struct mii_ioctl_data *data, int cmd)
4409 {
4410         switch (cmd) {
4411         case SIOCGMIIPHY:
4412                 data->phy_id = 32; /* Internal PHY */
4413                 return 0;
4414
4415         case SIOCGMIIREG:
4416                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4417                 return 0;
4418
4419         case SIOCSMIIREG:
4420                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4421                 return 0;
4422         }
4423         return -EOPNOTSUPP;
4424 }
4425
4426 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4427 {
4428         return -EOPNOTSUPP;
4429 }
4430
4431 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4432 {
4433         if (tp->features & RTL_FEATURE_MSI) {
4434                 pci_disable_msi(pdev);
4435                 tp->features &= ~RTL_FEATURE_MSI;
4436         }
4437 }
4438
4439 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4440 {
4441         struct mdio_ops *ops = &tp->mdio_ops;
4442
4443         switch (tp->mac_version) {
4444         case RTL_GIGA_MAC_VER_27:
4445                 ops->write      = r8168dp_1_mdio_write;
4446                 ops->read       = r8168dp_1_mdio_read;
4447                 break;
4448         case RTL_GIGA_MAC_VER_28:
4449         case RTL_GIGA_MAC_VER_31:
4450                 ops->write      = r8168dp_2_mdio_write;
4451                 ops->read       = r8168dp_2_mdio_read;
4452                 break;
4453         case RTL_GIGA_MAC_VER_40:
4454         case RTL_GIGA_MAC_VER_41:
4455         case RTL_GIGA_MAC_VER_42:
4456         case RTL_GIGA_MAC_VER_43:
4457         case RTL_GIGA_MAC_VER_44:
4458         case RTL_GIGA_MAC_VER_45:
4459         case RTL_GIGA_MAC_VER_46:
4460         case RTL_GIGA_MAC_VER_47:
4461         case RTL_GIGA_MAC_VER_48:
4462         case RTL_GIGA_MAC_VER_49:
4463         case RTL_GIGA_MAC_VER_50:
4464         case RTL_GIGA_MAC_VER_51:
4465                 ops->write      = r8168g_mdio_write;
4466                 ops->read       = r8168g_mdio_read;
4467                 break;
4468         default:
4469                 ops->write      = r8169_mdio_write;
4470                 ops->read       = r8169_mdio_read;
4471                 break;
4472         }
4473 }
4474
4475 static void rtl_speed_down(struct rtl8169_private *tp)
4476 {
4477         u32 adv;
4478         int lpa;
4479
4480         rtl_writephy(tp, 0x1f, 0x0000);
4481         lpa = rtl_readphy(tp, MII_LPA);
4482
4483         if (lpa & (LPA_10HALF | LPA_10FULL))
4484                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4485         else if (lpa & (LPA_100HALF | LPA_100FULL))
4486                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4487                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4488         else
4489                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4490                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4491                       (tp->mii.supports_gmii ?
4492                        ADVERTISED_1000baseT_Half |
4493                        ADVERTISED_1000baseT_Full : 0);
4494
4495         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4496                           adv);
4497 }
4498
4499 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4500 {
4501         void __iomem *ioaddr = tp->mmio_addr;
4502
4503         switch (tp->mac_version) {
4504         case RTL_GIGA_MAC_VER_25:
4505         case RTL_GIGA_MAC_VER_26:
4506         case RTL_GIGA_MAC_VER_29:
4507         case RTL_GIGA_MAC_VER_30:
4508         case RTL_GIGA_MAC_VER_32:
4509         case RTL_GIGA_MAC_VER_33:
4510         case RTL_GIGA_MAC_VER_34:
4511         case RTL_GIGA_MAC_VER_37:
4512         case RTL_GIGA_MAC_VER_38:
4513         case RTL_GIGA_MAC_VER_39:
4514         case RTL_GIGA_MAC_VER_40:
4515         case RTL_GIGA_MAC_VER_41:
4516         case RTL_GIGA_MAC_VER_42:
4517         case RTL_GIGA_MAC_VER_43:
4518         case RTL_GIGA_MAC_VER_44:
4519         case RTL_GIGA_MAC_VER_45:
4520         case RTL_GIGA_MAC_VER_46:
4521         case RTL_GIGA_MAC_VER_47:
4522         case RTL_GIGA_MAC_VER_48:
4523         case RTL_GIGA_MAC_VER_49:
4524         case RTL_GIGA_MAC_VER_50:
4525         case RTL_GIGA_MAC_VER_51:
4526                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4527                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4528                 break;
4529         default:
4530                 break;
4531         }
4532 }
4533
4534 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4535 {
4536         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4537                 return false;
4538
4539         rtl_speed_down(tp);
4540         rtl_wol_suspend_quirk(tp);
4541
4542         return true;
4543 }
4544
4545 static void r810x_phy_power_down(struct rtl8169_private *tp)
4546 {
4547         rtl_writephy(tp, 0x1f, 0x0000);
4548         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4549 }
4550
4551 static void r810x_phy_power_up(struct rtl8169_private *tp)
4552 {
4553         rtl_writephy(tp, 0x1f, 0x0000);
4554         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4555 }
4556
4557 static void r810x_pll_power_down(struct rtl8169_private *tp)
4558 {
4559         void __iomem *ioaddr = tp->mmio_addr;
4560
4561         if (rtl_wol_pll_power_down(tp))
4562                 return;
4563
4564         r810x_phy_power_down(tp);
4565
4566         switch (tp->mac_version) {
4567         case RTL_GIGA_MAC_VER_07:
4568         case RTL_GIGA_MAC_VER_08:
4569         case RTL_GIGA_MAC_VER_09:
4570         case RTL_GIGA_MAC_VER_10:
4571         case RTL_GIGA_MAC_VER_13:
4572         case RTL_GIGA_MAC_VER_16:
4573                 break;
4574         default:
4575                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4576                 break;
4577         }
4578 }
4579
4580 static void r810x_pll_power_up(struct rtl8169_private *tp)
4581 {
4582         void __iomem *ioaddr = tp->mmio_addr;
4583
4584         r810x_phy_power_up(tp);
4585
4586         switch (tp->mac_version) {
4587         case RTL_GIGA_MAC_VER_07:
4588         case RTL_GIGA_MAC_VER_08:
4589         case RTL_GIGA_MAC_VER_09:
4590         case RTL_GIGA_MAC_VER_10:
4591         case RTL_GIGA_MAC_VER_13:
4592         case RTL_GIGA_MAC_VER_16:
4593                 break;
4594         case RTL_GIGA_MAC_VER_47:
4595         case RTL_GIGA_MAC_VER_48:
4596                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4597                 break;
4598         default:
4599                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4600                 break;
4601         }
4602 }
4603
4604 static void r8168_phy_power_up(struct rtl8169_private *tp)
4605 {
4606         rtl_writephy(tp, 0x1f, 0x0000);
4607         switch (tp->mac_version) {
4608         case RTL_GIGA_MAC_VER_11:
4609         case RTL_GIGA_MAC_VER_12:
4610         case RTL_GIGA_MAC_VER_17:
4611         case RTL_GIGA_MAC_VER_18:
4612         case RTL_GIGA_MAC_VER_19:
4613         case RTL_GIGA_MAC_VER_20:
4614         case RTL_GIGA_MAC_VER_21:
4615         case RTL_GIGA_MAC_VER_22:
4616         case RTL_GIGA_MAC_VER_23:
4617         case RTL_GIGA_MAC_VER_24:
4618         case RTL_GIGA_MAC_VER_25:
4619         case RTL_GIGA_MAC_VER_26:
4620         case RTL_GIGA_MAC_VER_27:
4621         case RTL_GIGA_MAC_VER_28:
4622         case RTL_GIGA_MAC_VER_31:
4623                 rtl_writephy(tp, 0x0e, 0x0000);
4624                 break;
4625         default:
4626                 break;
4627         }
4628         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4629 }
4630
4631 static void r8168_phy_power_down(struct rtl8169_private *tp)
4632 {
4633         rtl_writephy(tp, 0x1f, 0x0000);
4634         switch (tp->mac_version) {
4635         case RTL_GIGA_MAC_VER_32:
4636         case RTL_GIGA_MAC_VER_33:
4637         case RTL_GIGA_MAC_VER_40:
4638         case RTL_GIGA_MAC_VER_41:
4639                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4640                 break;
4641
4642         case RTL_GIGA_MAC_VER_11:
4643         case RTL_GIGA_MAC_VER_12:
4644         case RTL_GIGA_MAC_VER_17:
4645         case RTL_GIGA_MAC_VER_18:
4646         case RTL_GIGA_MAC_VER_19:
4647         case RTL_GIGA_MAC_VER_20:
4648         case RTL_GIGA_MAC_VER_21:
4649         case RTL_GIGA_MAC_VER_22:
4650         case RTL_GIGA_MAC_VER_23:
4651         case RTL_GIGA_MAC_VER_24:
4652         case RTL_GIGA_MAC_VER_25:
4653         case RTL_GIGA_MAC_VER_26:
4654         case RTL_GIGA_MAC_VER_27:
4655         case RTL_GIGA_MAC_VER_28:
4656         case RTL_GIGA_MAC_VER_31:
4657                 rtl_writephy(tp, 0x0e, 0x0200);
4658         default:
4659                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4660                 break;
4661         }
4662 }
4663
4664 static void r8168_pll_power_down(struct rtl8169_private *tp)
4665 {
4666         void __iomem *ioaddr = tp->mmio_addr;
4667
4668         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4669              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4670              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4671              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4672              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4673              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4674             r8168_check_dash(tp)) {
4675                 return;
4676         }
4677
4678         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4679              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4680             (RTL_R16(CPlusCmd) & ASF)) {
4681                 return;
4682         }
4683
4684         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4685             tp->mac_version == RTL_GIGA_MAC_VER_33)
4686                 rtl_ephy_write(tp, 0x19, 0xff64);
4687
4688         if (rtl_wol_pll_power_down(tp))
4689                 return;
4690
4691         r8168_phy_power_down(tp);
4692
4693         switch (tp->mac_version) {
4694         case RTL_GIGA_MAC_VER_25:
4695         case RTL_GIGA_MAC_VER_26:
4696         case RTL_GIGA_MAC_VER_27:
4697         case RTL_GIGA_MAC_VER_28:
4698         case RTL_GIGA_MAC_VER_31:
4699         case RTL_GIGA_MAC_VER_32:
4700         case RTL_GIGA_MAC_VER_33:
4701         case RTL_GIGA_MAC_VER_44:
4702         case RTL_GIGA_MAC_VER_45:
4703         case RTL_GIGA_MAC_VER_46:
4704         case RTL_GIGA_MAC_VER_50:
4705         case RTL_GIGA_MAC_VER_51:
4706                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4707                 break;
4708         case RTL_GIGA_MAC_VER_40:
4709         case RTL_GIGA_MAC_VER_41:
4710         case RTL_GIGA_MAC_VER_49:
4711                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4712                              0xfc000000, ERIAR_EXGMAC);
4713                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4714                 break;
4715         }
4716 }
4717
4718 static void r8168_pll_power_up(struct rtl8169_private *tp)
4719 {
4720         void __iomem *ioaddr = tp->mmio_addr;
4721
4722         switch (tp->mac_version) {
4723         case RTL_GIGA_MAC_VER_25:
4724         case RTL_GIGA_MAC_VER_26:
4725         case RTL_GIGA_MAC_VER_27:
4726         case RTL_GIGA_MAC_VER_28:
4727         case RTL_GIGA_MAC_VER_31:
4728         case RTL_GIGA_MAC_VER_32:
4729         case RTL_GIGA_MAC_VER_33:
4730                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4731                 break;
4732         case RTL_GIGA_MAC_VER_44:
4733         case RTL_GIGA_MAC_VER_45:
4734         case RTL_GIGA_MAC_VER_46:
4735         case RTL_GIGA_MAC_VER_50:
4736         case RTL_GIGA_MAC_VER_51:
4737                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4738                 break;
4739         case RTL_GIGA_MAC_VER_40:
4740         case RTL_GIGA_MAC_VER_41:
4741         case RTL_GIGA_MAC_VER_49:
4742                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4743                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4744                              0x00000000, ERIAR_EXGMAC);
4745                 break;
4746         }
4747
4748         r8168_phy_power_up(tp);
4749 }
4750
4751 static void rtl_generic_op(struct rtl8169_private *tp,
4752                            void (*op)(struct rtl8169_private *))
4753 {
4754         if (op)
4755                 op(tp);
4756 }
4757
4758 static void rtl_pll_power_down(struct rtl8169_private *tp)
4759 {
4760         rtl_generic_op(tp, tp->pll_power_ops.down);
4761 }
4762
4763 static void rtl_pll_power_up(struct rtl8169_private *tp)
4764 {
4765         rtl_generic_op(tp, tp->pll_power_ops.up);
4766 }
4767
4768 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4769 {
4770         struct pll_power_ops *ops = &tp->pll_power_ops;
4771
4772         switch (tp->mac_version) {
4773         case RTL_GIGA_MAC_VER_07:
4774         case RTL_GIGA_MAC_VER_08:
4775         case RTL_GIGA_MAC_VER_09:
4776         case RTL_GIGA_MAC_VER_10:
4777         case RTL_GIGA_MAC_VER_16:
4778         case RTL_GIGA_MAC_VER_29:
4779         case RTL_GIGA_MAC_VER_30:
4780         case RTL_GIGA_MAC_VER_37:
4781         case RTL_GIGA_MAC_VER_39:
4782         case RTL_GIGA_MAC_VER_43:
4783         case RTL_GIGA_MAC_VER_47:
4784         case RTL_GIGA_MAC_VER_48:
4785                 ops->down       = r810x_pll_power_down;
4786                 ops->up         = r810x_pll_power_up;
4787                 break;
4788
4789         case RTL_GIGA_MAC_VER_11:
4790         case RTL_GIGA_MAC_VER_12:
4791         case RTL_GIGA_MAC_VER_17:
4792         case RTL_GIGA_MAC_VER_18:
4793         case RTL_GIGA_MAC_VER_19:
4794         case RTL_GIGA_MAC_VER_20:
4795         case RTL_GIGA_MAC_VER_21:
4796         case RTL_GIGA_MAC_VER_22:
4797         case RTL_GIGA_MAC_VER_23:
4798         case RTL_GIGA_MAC_VER_24:
4799         case RTL_GIGA_MAC_VER_25:
4800         case RTL_GIGA_MAC_VER_26:
4801         case RTL_GIGA_MAC_VER_27:
4802         case RTL_GIGA_MAC_VER_28:
4803         case RTL_GIGA_MAC_VER_31:
4804         case RTL_GIGA_MAC_VER_32:
4805         case RTL_GIGA_MAC_VER_33:
4806         case RTL_GIGA_MAC_VER_34:
4807         case RTL_GIGA_MAC_VER_35:
4808         case RTL_GIGA_MAC_VER_36:
4809         case RTL_GIGA_MAC_VER_38:
4810         case RTL_GIGA_MAC_VER_40:
4811         case RTL_GIGA_MAC_VER_41:
4812         case RTL_GIGA_MAC_VER_42:
4813         case RTL_GIGA_MAC_VER_44:
4814         case RTL_GIGA_MAC_VER_45:
4815         case RTL_GIGA_MAC_VER_46:
4816         case RTL_GIGA_MAC_VER_49:
4817         case RTL_GIGA_MAC_VER_50:
4818         case RTL_GIGA_MAC_VER_51:
4819                 ops->down       = r8168_pll_power_down;
4820                 ops->up         = r8168_pll_power_up;
4821                 break;
4822
4823         default:
4824                 ops->down       = NULL;
4825                 ops->up         = NULL;
4826                 break;
4827         }
4828 }
4829
4830 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4831 {
4832         void __iomem *ioaddr = tp->mmio_addr;
4833
4834         switch (tp->mac_version) {
4835         case RTL_GIGA_MAC_VER_01:
4836         case RTL_GIGA_MAC_VER_02:
4837         case RTL_GIGA_MAC_VER_03:
4838         case RTL_GIGA_MAC_VER_04:
4839         case RTL_GIGA_MAC_VER_05:
4840         case RTL_GIGA_MAC_VER_06:
4841         case RTL_GIGA_MAC_VER_10:
4842         case RTL_GIGA_MAC_VER_11:
4843         case RTL_GIGA_MAC_VER_12:
4844         case RTL_GIGA_MAC_VER_13:
4845         case RTL_GIGA_MAC_VER_14:
4846         case RTL_GIGA_MAC_VER_15:
4847         case RTL_GIGA_MAC_VER_16:
4848         case RTL_GIGA_MAC_VER_17:
4849                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4850                 break;
4851         case RTL_GIGA_MAC_VER_18:
4852         case RTL_GIGA_MAC_VER_19:
4853         case RTL_GIGA_MAC_VER_20:
4854         case RTL_GIGA_MAC_VER_21:
4855         case RTL_GIGA_MAC_VER_22:
4856         case RTL_GIGA_MAC_VER_23:
4857         case RTL_GIGA_MAC_VER_24:
4858         case RTL_GIGA_MAC_VER_34:
4859         case RTL_GIGA_MAC_VER_35:
4860                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4861                 break;
4862         case RTL_GIGA_MAC_VER_40:
4863                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4864                 break;
4865         case RTL_GIGA_MAC_VER_41:
4866         case RTL_GIGA_MAC_VER_42:
4867         case RTL_GIGA_MAC_VER_43:
4868         case RTL_GIGA_MAC_VER_44:
4869         case RTL_GIGA_MAC_VER_45:
4870         case RTL_GIGA_MAC_VER_46:
4871         case RTL_GIGA_MAC_VER_47:
4872         case RTL_GIGA_MAC_VER_48:
4873         case RTL_GIGA_MAC_VER_49:
4874         case RTL_GIGA_MAC_VER_50:
4875         case RTL_GIGA_MAC_VER_51:
4876                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4877                 break;
4878         default:
4879                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4880                 break;
4881         }
4882 }
4883
4884 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4885 {
4886         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4887 }
4888
4889 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4890 {
4891         void __iomem *ioaddr = tp->mmio_addr;
4892
4893         RTL_W8(Cfg9346, Cfg9346_Unlock);
4894         rtl_generic_op(tp, tp->jumbo_ops.enable);
4895         RTL_W8(Cfg9346, Cfg9346_Lock);
4896 }
4897
4898 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4899 {
4900         void __iomem *ioaddr = tp->mmio_addr;
4901
4902         RTL_W8(Cfg9346, Cfg9346_Unlock);
4903         rtl_generic_op(tp, tp->jumbo_ops.disable);
4904         RTL_W8(Cfg9346, Cfg9346_Lock);
4905 }
4906
4907 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4908 {
4909         void __iomem *ioaddr = tp->mmio_addr;
4910
4911         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4912         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4913         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4914 }
4915
4916 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4917 {
4918         void __iomem *ioaddr = tp->mmio_addr;
4919
4920         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4921         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4922         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4923 }
4924
4925 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4926 {
4927         void __iomem *ioaddr = tp->mmio_addr;
4928
4929         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4930 }
4931
4932 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4933 {
4934         void __iomem *ioaddr = tp->mmio_addr;
4935
4936         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4937 }
4938
4939 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4940 {
4941         void __iomem *ioaddr = tp->mmio_addr;
4942
4943         RTL_W8(MaxTxPacketSize, 0x3f);
4944         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4945         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4946         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4947 }
4948
4949 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4950 {
4951         void __iomem *ioaddr = tp->mmio_addr;
4952
4953         RTL_W8(MaxTxPacketSize, 0x0c);
4954         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4955         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4956         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4957 }
4958
4959 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4960 {
4961         rtl_tx_performance_tweak(tp->pci_dev,
4962                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4963 }
4964
4965 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4966 {
4967         rtl_tx_performance_tweak(tp->pci_dev,
4968                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4969 }
4970
4971 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4972 {
4973         void __iomem *ioaddr = tp->mmio_addr;
4974
4975         r8168b_0_hw_jumbo_enable(tp);
4976
4977         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4978 }
4979
4980 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4981 {
4982         void __iomem *ioaddr = tp->mmio_addr;
4983
4984         r8168b_0_hw_jumbo_disable(tp);
4985
4986         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4987 }
4988
4989 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4990 {
4991         struct jumbo_ops *ops = &tp->jumbo_ops;
4992
4993         switch (tp->mac_version) {
4994         case RTL_GIGA_MAC_VER_11:
4995                 ops->disable    = r8168b_0_hw_jumbo_disable;
4996                 ops->enable     = r8168b_0_hw_jumbo_enable;
4997                 break;
4998         case RTL_GIGA_MAC_VER_12:
4999         case RTL_GIGA_MAC_VER_17:
5000                 ops->disable    = r8168b_1_hw_jumbo_disable;
5001                 ops->enable     = r8168b_1_hw_jumbo_enable;
5002                 break;
5003         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5004         case RTL_GIGA_MAC_VER_19:
5005         case RTL_GIGA_MAC_VER_20:
5006         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5007         case RTL_GIGA_MAC_VER_22:
5008         case RTL_GIGA_MAC_VER_23:
5009         case RTL_GIGA_MAC_VER_24:
5010         case RTL_GIGA_MAC_VER_25:
5011         case RTL_GIGA_MAC_VER_26:
5012                 ops->disable    = r8168c_hw_jumbo_disable;
5013                 ops->enable     = r8168c_hw_jumbo_enable;
5014                 break;
5015         case RTL_GIGA_MAC_VER_27:
5016         case RTL_GIGA_MAC_VER_28:
5017                 ops->disable    = r8168dp_hw_jumbo_disable;
5018                 ops->enable     = r8168dp_hw_jumbo_enable;
5019                 break;
5020         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5021         case RTL_GIGA_MAC_VER_32:
5022         case RTL_GIGA_MAC_VER_33:
5023         case RTL_GIGA_MAC_VER_34:
5024                 ops->disable    = r8168e_hw_jumbo_disable;
5025                 ops->enable     = r8168e_hw_jumbo_enable;
5026                 break;
5027
5028         /*
5029          * No action needed for jumbo frames with 8169.
5030          * No jumbo for 810x at all.
5031          */
5032         case RTL_GIGA_MAC_VER_40:
5033         case RTL_GIGA_MAC_VER_41:
5034         case RTL_GIGA_MAC_VER_42:
5035         case RTL_GIGA_MAC_VER_43:
5036         case RTL_GIGA_MAC_VER_44:
5037         case RTL_GIGA_MAC_VER_45:
5038         case RTL_GIGA_MAC_VER_46:
5039         case RTL_GIGA_MAC_VER_47:
5040         case RTL_GIGA_MAC_VER_48:
5041         case RTL_GIGA_MAC_VER_49:
5042         case RTL_GIGA_MAC_VER_50:
5043         case RTL_GIGA_MAC_VER_51:
5044         default:
5045                 ops->disable    = NULL;
5046                 ops->enable     = NULL;
5047                 break;
5048         }
5049 }
5050
5051 DECLARE_RTL_COND(rtl_chipcmd_cond)
5052 {
5053         void __iomem *ioaddr = tp->mmio_addr;
5054
5055         return RTL_R8(ChipCmd) & CmdReset;
5056 }
5057
5058 static void rtl_hw_reset(struct rtl8169_private *tp)
5059 {
5060         void __iomem *ioaddr = tp->mmio_addr;
5061
5062         RTL_W8(ChipCmd, CmdReset);
5063
5064         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5065
5066         netdev_reset_queue(tp->dev);
5067 }
5068
5069 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5070 {
5071         struct rtl_fw *rtl_fw;
5072         const char *name;
5073         int rc = -ENOMEM;
5074
5075         name = rtl_lookup_firmware_name(tp);
5076         if (!name)
5077                 goto out_no_firmware;
5078
5079         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5080         if (!rtl_fw)
5081                 goto err_warn;
5082
5083         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5084         if (rc < 0)
5085                 goto err_free;
5086
5087         rc = rtl_check_firmware(tp, rtl_fw);
5088         if (rc < 0)
5089                 goto err_release_firmware;
5090
5091         tp->rtl_fw = rtl_fw;
5092 out:
5093         return;
5094
5095 err_release_firmware:
5096         release_firmware(rtl_fw->fw);
5097 err_free:
5098         kfree(rtl_fw);
5099 err_warn:
5100         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5101                    name, rc);
5102 out_no_firmware:
5103         tp->rtl_fw = NULL;
5104         goto out;
5105 }
5106
5107 static void rtl_request_firmware(struct rtl8169_private *tp)
5108 {
5109         if (IS_ERR(tp->rtl_fw))
5110                 rtl_request_uncached_firmware(tp);
5111 }
5112
5113 static void rtl_rx_close(struct rtl8169_private *tp)
5114 {
5115         void __iomem *ioaddr = tp->mmio_addr;
5116
5117         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5118 }
5119
5120 DECLARE_RTL_COND(rtl_npq_cond)
5121 {
5122         void __iomem *ioaddr = tp->mmio_addr;
5123
5124         return RTL_R8(TxPoll) & NPQ;
5125 }
5126
5127 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5128 {
5129         void __iomem *ioaddr = tp->mmio_addr;
5130
5131         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5132 }
5133
5134 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5135 {
5136         void __iomem *ioaddr = tp->mmio_addr;
5137
5138         /* Disable interrupts */
5139         rtl8169_irq_mask_and_ack(tp);
5140
5141         rtl_rx_close(tp);
5142
5143         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5144             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5145             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5146                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5147         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5148                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5149                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5150                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5151                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5152                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5153                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5154                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5155                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5156                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5157                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5158                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5159                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5160                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5161                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5162                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5163                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5164                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5165                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5166         } else {
5167                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5168                 udelay(100);
5169         }
5170
5171         rtl_hw_reset(tp);
5172 }
5173
5174 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5175 {
5176         void __iomem *ioaddr = tp->mmio_addr;
5177
5178         /* Set DMA burst size and Interframe Gap Time */
5179         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5180                 (InterFrameGap << TxInterFrameGapShift));
5181 }
5182
5183 static void rtl_hw_start(struct net_device *dev)
5184 {
5185         struct rtl8169_private *tp = netdev_priv(dev);
5186
5187         tp->hw_start(dev);
5188
5189         rtl_irq_enable_all(tp);
5190 }
5191
5192 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5193                                          void __iomem *ioaddr)
5194 {
5195         /*
5196          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5197          * register to be written before TxDescAddrLow to work.
5198          * Switching from MMIO to I/O access fixes the issue as well.
5199          */
5200         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5201         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5202         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5203         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5204 }
5205
5206 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5207 {
5208         u16 cmd;
5209
5210         cmd = RTL_R16(CPlusCmd);
5211         RTL_W16(CPlusCmd, cmd);
5212         return cmd;
5213 }
5214
5215 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5216 {
5217         /* Low hurts. Let's disable the filtering. */
5218         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5219 }
5220
5221 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5222 {
5223         static const struct rtl_cfg2_info {
5224                 u32 mac_version;
5225                 u32 clk;
5226                 u32 val;
5227         } cfg2_info [] = {
5228                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5229                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5230                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5231                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5232         };
5233         const struct rtl_cfg2_info *p = cfg2_info;
5234         unsigned int i;
5235         u32 clk;
5236
5237         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5238         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5239                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5240                         RTL_W32(0x7c, p->val);
5241                         break;
5242                 }
5243         }
5244 }
5245
5246 static void rtl_set_rx_mode(struct net_device *dev)
5247 {
5248         struct rtl8169_private *tp = netdev_priv(dev);
5249         void __iomem *ioaddr = tp->mmio_addr;
5250         u32 mc_filter[2];       /* Multicast hash filter */
5251         int rx_mode;
5252         u32 tmp = 0;
5253
5254         if (dev->flags & IFF_PROMISC) {
5255                 /* Unconditionally log net taps. */
5256                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5257                 rx_mode =
5258                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5259                     AcceptAllPhys;
5260                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5261         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5262                    (dev->flags & IFF_ALLMULTI)) {
5263                 /* Too many to filter perfectly -- accept all multicasts. */
5264                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5265                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5266         } else {
5267                 struct netdev_hw_addr *ha;
5268
5269                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5270                 mc_filter[1] = mc_filter[0] = 0;
5271                 netdev_for_each_mc_addr(ha, dev) {
5272                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5273                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5274                         rx_mode |= AcceptMulticast;
5275                 }
5276         }
5277
5278         if (dev->features & NETIF_F_RXALL)
5279                 rx_mode |= (AcceptErr | AcceptRunt);
5280
5281         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5282
5283         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5284                 u32 data = mc_filter[0];
5285
5286                 mc_filter[0] = swab32(mc_filter[1]);
5287                 mc_filter[1] = swab32(data);
5288         }
5289
5290         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5291                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5292
5293         RTL_W32(MAR0 + 4, mc_filter[1]);
5294         RTL_W32(MAR0 + 0, mc_filter[0]);
5295
5296         RTL_W32(RxConfig, tmp);
5297 }
5298
5299 static void rtl_hw_start_8169(struct net_device *dev)
5300 {
5301         struct rtl8169_private *tp = netdev_priv(dev);
5302         void __iomem *ioaddr = tp->mmio_addr;
5303         struct pci_dev *pdev = tp->pci_dev;
5304
5305         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5306                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5307                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5308         }
5309
5310         RTL_W8(Cfg9346, Cfg9346_Unlock);
5311         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5312             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5313             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5314             tp->mac_version == RTL_GIGA_MAC_VER_04)
5315                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5316
5317         rtl_init_rxcfg(tp);
5318
5319         RTL_W8(EarlyTxThres, NoEarlyTx);
5320
5321         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5322
5323         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5324             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5325             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5326             tp->mac_version == RTL_GIGA_MAC_VER_04)
5327                 rtl_set_rx_tx_config_registers(tp);
5328
5329         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5330
5331         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5332             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5333                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5334                         "Bit-3 and bit-14 MUST be 1\n");
5335                 tp->cp_cmd |= (1 << 14);
5336         }
5337
5338         RTL_W16(CPlusCmd, tp->cp_cmd);
5339
5340         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5341
5342         /*
5343          * Undocumented corner. Supposedly:
5344          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5345          */
5346         RTL_W16(IntrMitigate, 0x0000);
5347
5348         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5349
5350         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5351             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5352             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5353             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5354                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5355                 rtl_set_rx_tx_config_registers(tp);
5356         }
5357
5358         RTL_W8(Cfg9346, Cfg9346_Lock);
5359
5360         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5361         RTL_R8(IntrMask);
5362
5363         RTL_W32(RxMissed, 0);
5364
5365         rtl_set_rx_mode(dev);
5366
5367         /* no early-rx interrupts */
5368         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5369 }
5370
5371 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5372 {
5373         if (tp->csi_ops.write)
5374                 tp->csi_ops.write(tp, addr, value);
5375 }
5376
5377 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5378 {
5379         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5380 }
5381
5382 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5383 {
5384         u32 csi;
5385
5386         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5387         rtl_csi_write(tp, 0x070c, csi | bits);
5388 }
5389
5390 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5391 {
5392         rtl_csi_access_enable(tp, 0x17000000);
5393 }
5394
5395 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5396 {
5397         rtl_csi_access_enable(tp, 0x27000000);
5398 }
5399
5400 DECLARE_RTL_COND(rtl_csiar_cond)
5401 {
5402         void __iomem *ioaddr = tp->mmio_addr;
5403
5404         return RTL_R32(CSIAR) & CSIAR_FLAG;
5405 }
5406
5407 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5408 {
5409         void __iomem *ioaddr = tp->mmio_addr;
5410
5411         RTL_W32(CSIDR, value);
5412         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5413                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5414
5415         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5416 }
5417
5418 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5419 {
5420         void __iomem *ioaddr = tp->mmio_addr;
5421
5422         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5423                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5424
5425         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5426                 RTL_R32(CSIDR) : ~0;
5427 }
5428
5429 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5430 {
5431         void __iomem *ioaddr = tp->mmio_addr;
5432
5433         RTL_W32(CSIDR, value);
5434         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5435                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5436                 CSIAR_FUNC_NIC);
5437
5438         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5439 }
5440
5441 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5442 {
5443         void __iomem *ioaddr = tp->mmio_addr;
5444
5445         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5446                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5447
5448         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5449                 RTL_R32(CSIDR) : ~0;
5450 }
5451
5452 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5453 {
5454         void __iomem *ioaddr = tp->mmio_addr;
5455
5456         RTL_W32(CSIDR, value);
5457         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5458                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5459                 CSIAR_FUNC_NIC2);
5460
5461         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5462 }
5463
5464 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5465 {
5466         void __iomem *ioaddr = tp->mmio_addr;
5467
5468         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5469                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5470
5471         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5472                 RTL_R32(CSIDR) : ~0;
5473 }
5474
5475 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5476 {
5477         struct csi_ops *ops = &tp->csi_ops;
5478
5479         switch (tp->mac_version) {
5480         case RTL_GIGA_MAC_VER_01:
5481         case RTL_GIGA_MAC_VER_02:
5482         case RTL_GIGA_MAC_VER_03:
5483         case RTL_GIGA_MAC_VER_04:
5484         case RTL_GIGA_MAC_VER_05:
5485         case RTL_GIGA_MAC_VER_06:
5486         case RTL_GIGA_MAC_VER_10:
5487         case RTL_GIGA_MAC_VER_11:
5488         case RTL_GIGA_MAC_VER_12:
5489         case RTL_GIGA_MAC_VER_13:
5490         case RTL_GIGA_MAC_VER_14:
5491         case RTL_GIGA_MAC_VER_15:
5492         case RTL_GIGA_MAC_VER_16:
5493         case RTL_GIGA_MAC_VER_17:
5494                 ops->write      = NULL;
5495                 ops->read       = NULL;
5496                 break;
5497
5498         case RTL_GIGA_MAC_VER_37:
5499         case RTL_GIGA_MAC_VER_38:
5500                 ops->write      = r8402_csi_write;
5501                 ops->read       = r8402_csi_read;
5502                 break;
5503
5504         case RTL_GIGA_MAC_VER_44:
5505                 ops->write      = r8411_csi_write;
5506                 ops->read       = r8411_csi_read;
5507                 break;
5508
5509         default:
5510                 ops->write      = r8169_csi_write;
5511                 ops->read       = r8169_csi_read;
5512                 break;
5513         }
5514 }
5515
5516 struct ephy_info {
5517         unsigned int offset;
5518         u16 mask;
5519         u16 bits;
5520 };
5521
5522 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5523                           int len)
5524 {
5525         u16 w;
5526
5527         while (len-- > 0) {
5528                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5529                 rtl_ephy_write(tp, e->offset, w);
5530                 e++;
5531         }
5532 }
5533
5534 static void rtl_disable_clock_request(struct pci_dev *pdev)
5535 {
5536         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5537                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5538 }
5539
5540 static void rtl_enable_clock_request(struct pci_dev *pdev)
5541 {
5542         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5543                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5544 }
5545
5546 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5547 {
5548         void __iomem *ioaddr = tp->mmio_addr;
5549         u8 data;
5550
5551         data = RTL_R8(Config3);
5552
5553         if (enable)
5554                 data |= Rdy_to_L23;
5555         else
5556                 data &= ~Rdy_to_L23;
5557
5558         RTL_W8(Config3, data);
5559 }
5560
5561 #define R8168_CPCMD_QUIRK_MASK (\
5562         EnableBist | \
5563         Mac_dbgo_oe | \
5564         Force_half_dup | \
5565         Force_rxflow_en | \
5566         Force_txflow_en | \
5567         Cxpl_dbg_sel | \
5568         ASF | \
5569         PktCntrDisable | \
5570         Mac_dbgo_sel)
5571
5572 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5573 {
5574         void __iomem *ioaddr = tp->mmio_addr;
5575         struct pci_dev *pdev = tp->pci_dev;
5576
5577         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5578
5579         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5580
5581         if (tp->dev->mtu <= ETH_DATA_LEN) {
5582                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5583                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5584         }
5585 }
5586
5587 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5588 {
5589         void __iomem *ioaddr = tp->mmio_addr;
5590
5591         rtl_hw_start_8168bb(tp);
5592
5593         RTL_W8(MaxTxPacketSize, TxPacketMax);
5594
5595         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5596 }
5597
5598 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5599 {
5600         void __iomem *ioaddr = tp->mmio_addr;
5601         struct pci_dev *pdev = tp->pci_dev;
5602
5603         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5604
5605         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5606
5607         if (tp->dev->mtu <= ETH_DATA_LEN)
5608                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5609
5610         rtl_disable_clock_request(pdev);
5611
5612         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5613 }
5614
5615 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5616 {
5617         static const struct ephy_info e_info_8168cp[] = {
5618                 { 0x01, 0,      0x0001 },
5619                 { 0x02, 0x0800, 0x1000 },
5620                 { 0x03, 0,      0x0042 },
5621                 { 0x06, 0x0080, 0x0000 },
5622                 { 0x07, 0,      0x2000 }
5623         };
5624
5625         rtl_csi_access_enable_2(tp);
5626
5627         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5628
5629         __rtl_hw_start_8168cp(tp);
5630 }
5631
5632 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5633 {
5634         void __iomem *ioaddr = tp->mmio_addr;
5635         struct pci_dev *pdev = tp->pci_dev;
5636
5637         rtl_csi_access_enable_2(tp);
5638
5639         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5640
5641         if (tp->dev->mtu <= ETH_DATA_LEN)
5642                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5643
5644         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5645 }
5646
5647 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5648 {
5649         void __iomem *ioaddr = tp->mmio_addr;
5650         struct pci_dev *pdev = tp->pci_dev;
5651
5652         rtl_csi_access_enable_2(tp);
5653
5654         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5655
5656         /* Magic. */
5657         RTL_W8(DBG_REG, 0x20);
5658
5659         RTL_W8(MaxTxPacketSize, TxPacketMax);
5660
5661         if (tp->dev->mtu <= ETH_DATA_LEN)
5662                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5663
5664         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5665 }
5666
5667 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5668 {
5669         void __iomem *ioaddr = tp->mmio_addr;
5670         static const struct ephy_info e_info_8168c_1[] = {
5671                 { 0x02, 0x0800, 0x1000 },
5672                 { 0x03, 0,      0x0002 },
5673                 { 0x06, 0x0080, 0x0000 }
5674         };
5675
5676         rtl_csi_access_enable_2(tp);
5677
5678         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5679
5680         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5681
5682         __rtl_hw_start_8168cp(tp);
5683 }
5684
5685 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5686 {
5687         static const struct ephy_info e_info_8168c_2[] = {
5688                 { 0x01, 0,      0x0001 },
5689                 { 0x03, 0x0400, 0x0220 }
5690         };
5691
5692         rtl_csi_access_enable_2(tp);
5693
5694         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5695
5696         __rtl_hw_start_8168cp(tp);
5697 }
5698
5699 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5700 {
5701         rtl_hw_start_8168c_2(tp);
5702 }
5703
5704 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5705 {
5706         rtl_csi_access_enable_2(tp);
5707
5708         __rtl_hw_start_8168cp(tp);
5709 }
5710
5711 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5712 {
5713         void __iomem *ioaddr = tp->mmio_addr;
5714         struct pci_dev *pdev = tp->pci_dev;
5715
5716         rtl_csi_access_enable_2(tp);
5717
5718         rtl_disable_clock_request(pdev);
5719
5720         RTL_W8(MaxTxPacketSize, TxPacketMax);
5721
5722         if (tp->dev->mtu <= ETH_DATA_LEN)
5723                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5724
5725         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5726 }
5727
5728 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5729 {
5730         void __iomem *ioaddr = tp->mmio_addr;
5731         struct pci_dev *pdev = tp->pci_dev;
5732
5733         rtl_csi_access_enable_1(tp);
5734
5735         if (tp->dev->mtu <= ETH_DATA_LEN)
5736                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5737
5738         RTL_W8(MaxTxPacketSize, TxPacketMax);
5739
5740         rtl_disable_clock_request(pdev);
5741 }
5742
5743 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5744 {
5745         void __iomem *ioaddr = tp->mmio_addr;
5746         struct pci_dev *pdev = tp->pci_dev;
5747         static const struct ephy_info e_info_8168d_4[] = {
5748                 { 0x0b, ~0,     0x48 },
5749                 { 0x19, 0x20,   0x50 },
5750                 { 0x0c, ~0,     0x20 }
5751         };
5752         int i;
5753
5754         rtl_csi_access_enable_1(tp);
5755
5756         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5757
5758         RTL_W8(MaxTxPacketSize, TxPacketMax);
5759
5760         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5761                 const struct ephy_info *e = e_info_8168d_4 + i;
5762                 u16 w;
5763
5764                 w = rtl_ephy_read(tp, e->offset);
5765                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5766         }
5767
5768         rtl_enable_clock_request(pdev);
5769 }
5770
5771 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5772 {
5773         void __iomem *ioaddr = tp->mmio_addr;
5774         struct pci_dev *pdev = tp->pci_dev;
5775         static const struct ephy_info e_info_8168e_1[] = {
5776                 { 0x00, 0x0200, 0x0100 },
5777                 { 0x00, 0x0000, 0x0004 },
5778                 { 0x06, 0x0002, 0x0001 },
5779                 { 0x06, 0x0000, 0x0030 },
5780                 { 0x07, 0x0000, 0x2000 },
5781                 { 0x00, 0x0000, 0x0020 },
5782                 { 0x03, 0x5800, 0x2000 },
5783                 { 0x03, 0x0000, 0x0001 },
5784                 { 0x01, 0x0800, 0x1000 },
5785                 { 0x07, 0x0000, 0x4000 },
5786                 { 0x1e, 0x0000, 0x2000 },
5787                 { 0x19, 0xffff, 0xfe6c },
5788                 { 0x0a, 0x0000, 0x0040 }
5789         };
5790
5791         rtl_csi_access_enable_2(tp);
5792
5793         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5794
5795         if (tp->dev->mtu <= ETH_DATA_LEN)
5796                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5797
5798         RTL_W8(MaxTxPacketSize, TxPacketMax);
5799
5800         rtl_disable_clock_request(pdev);
5801
5802         /* Reset tx FIFO pointer */
5803         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5804         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5805
5806         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5807 }
5808
5809 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5810 {
5811         void __iomem *ioaddr = tp->mmio_addr;
5812         struct pci_dev *pdev = tp->pci_dev;
5813         static const struct ephy_info e_info_8168e_2[] = {
5814                 { 0x09, 0x0000, 0x0080 },
5815                 { 0x19, 0x0000, 0x0224 }
5816         };
5817
5818         rtl_csi_access_enable_1(tp);
5819
5820         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5821
5822         if (tp->dev->mtu <= ETH_DATA_LEN)
5823                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5824
5825         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5826         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5827         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5828         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5829         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5830         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5831         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5832         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5833
5834         RTL_W8(MaxTxPacketSize, EarlySize);
5835
5836         rtl_disable_clock_request(pdev);
5837
5838         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5839         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5840
5841         /* Adjust EEE LED frequency */
5842         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5843
5844         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5845         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5846         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5847 }
5848
5849 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5850 {
5851         void __iomem *ioaddr = tp->mmio_addr;
5852         struct pci_dev *pdev = tp->pci_dev;
5853
5854         rtl_csi_access_enable_2(tp);
5855
5856         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5857
5858         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5859         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5860         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5861         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5862         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5863         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5864         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5865         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5866         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5867         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5868
5869         RTL_W8(MaxTxPacketSize, EarlySize);
5870
5871         rtl_disable_clock_request(pdev);
5872
5873         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5874         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5875         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5876         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5877         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5878 }
5879
5880 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5881 {
5882         void __iomem *ioaddr = tp->mmio_addr;
5883         static const struct ephy_info e_info_8168f_1[] = {
5884                 { 0x06, 0x00c0, 0x0020 },
5885                 { 0x08, 0x0001, 0x0002 },
5886                 { 0x09, 0x0000, 0x0080 },
5887                 { 0x19, 0x0000, 0x0224 }
5888         };
5889
5890         rtl_hw_start_8168f(tp);
5891
5892         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5893
5894         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5895
5896         /* Adjust EEE LED frequency */
5897         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5898 }
5899
5900 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5901 {
5902         static const struct ephy_info e_info_8168f_1[] = {
5903                 { 0x06, 0x00c0, 0x0020 },
5904                 { 0x0f, 0xffff, 0x5200 },
5905                 { 0x1e, 0x0000, 0x4000 },
5906                 { 0x19, 0x0000, 0x0224 }
5907         };
5908
5909         rtl_hw_start_8168f(tp);
5910         rtl_pcie_state_l2l3_enable(tp, false);
5911
5912         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5913
5914         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5915 }
5916
5917 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5918 {
5919         void __iomem *ioaddr = tp->mmio_addr;
5920         struct pci_dev *pdev = tp->pci_dev;
5921
5922         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5923
5924         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5925         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5926         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5927         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5928
5929         rtl_csi_access_enable_1(tp);
5930
5931         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5932
5933         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5934         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5935         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5936
5937         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5938         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5939         RTL_W8(MaxTxPacketSize, EarlySize);
5940
5941         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5942         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5943
5944         /* Adjust EEE LED frequency */
5945         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5946
5947         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5948         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5949
5950         rtl_pcie_state_l2l3_enable(tp, false);
5951 }
5952
5953 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5954 {
5955         void __iomem *ioaddr = tp->mmio_addr;
5956         static const struct ephy_info e_info_8168g_2[] = {
5957                 { 0x00, 0x0000, 0x0008 },
5958                 { 0x0c, 0x3df0, 0x0200 },
5959                 { 0x19, 0xffff, 0xfc00 },
5960                 { 0x1e, 0xffff, 0x20eb }
5961         };
5962
5963         rtl_hw_start_8168g_1(tp);
5964
5965         /* disable aspm and clock request before access ephy */
5966         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5967         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5968         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5969 }
5970
5971 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5972 {
5973         void __iomem *ioaddr = tp->mmio_addr;
5974         static const struct ephy_info e_info_8411_2[] = {
5975                 { 0x00, 0x0000, 0x0008 },
5976                 { 0x0c, 0x3df0, 0x0200 },
5977                 { 0x0f, 0xffff, 0x5200 },
5978                 { 0x19, 0x0020, 0x0000 },
5979                 { 0x1e, 0x0000, 0x2000 }
5980         };
5981
5982         rtl_hw_start_8168g_1(tp);
5983
5984         /* disable aspm and clock request before access ephy */
5985         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5986         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5987         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5988 }
5989
5990 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5991 {
5992         void __iomem *ioaddr = tp->mmio_addr;
5993         struct pci_dev *pdev = tp->pci_dev;
5994         u16 rg_saw_cnt;
5995         u32 data;
5996         static const struct ephy_info e_info_8168h_1[] = {
5997                 { 0x1e, 0x0800, 0x0001 },
5998                 { 0x1d, 0x0000, 0x0800 },
5999                 { 0x05, 0xffff, 0x2089 },
6000                 { 0x06, 0xffff, 0x5881 },
6001                 { 0x04, 0xffff, 0x154a },
6002                 { 0x01, 0xffff, 0x068b }
6003         };
6004
6005         /* disable aspm and clock request before access ephy */
6006         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6007         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6008         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6009
6010         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6011
6012         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6013         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6014         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6015         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6016
6017         rtl_csi_access_enable_1(tp);
6018
6019         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6020
6021         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6022         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6023
6024         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6025
6026         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6027
6028         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6029
6030         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6031         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6032         RTL_W8(MaxTxPacketSize, EarlySize);
6033
6034         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6035         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6036
6037         /* Adjust EEE LED frequency */
6038         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6039
6040         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6041         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6042
6043         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6044
6045         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6046
6047         rtl_pcie_state_l2l3_enable(tp, false);
6048
6049         rtl_writephy(tp, 0x1f, 0x0c42);
6050         rg_saw_cnt = rtl_readphy(tp, 0x13);
6051         rtl_writephy(tp, 0x1f, 0x0000);
6052         if (rg_saw_cnt > 0) {
6053                 u16 sw_cnt_1ms_ini;
6054
6055                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6056                 sw_cnt_1ms_ini &= 0x0fff;
6057                 data = r8168_mac_ocp_read(tp, 0xd412);
6058                 data &= 0x0fff;
6059                 data |= sw_cnt_1ms_ini;
6060                 r8168_mac_ocp_write(tp, 0xd412, data);
6061         }
6062
6063         data = r8168_mac_ocp_read(tp, 0xe056);
6064         data &= 0xf0;
6065         data |= 0x07;
6066         r8168_mac_ocp_write(tp, 0xe056, data);
6067
6068         data = r8168_mac_ocp_read(tp, 0xe052);
6069         data &= 0x8008;
6070         data |= 0x6000;
6071         r8168_mac_ocp_write(tp, 0xe052, data);
6072
6073         data = r8168_mac_ocp_read(tp, 0xe0d6);
6074         data &= 0x01ff;
6075         data |= 0x017f;
6076         r8168_mac_ocp_write(tp, 0xe0d6, data);
6077
6078         data = r8168_mac_ocp_read(tp, 0xd420);
6079         data &= 0x0fff;
6080         data |= 0x047f;
6081         r8168_mac_ocp_write(tp, 0xd420, data);
6082
6083         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6084         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6085         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6086         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6087 }
6088
6089 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6090 {
6091         void __iomem *ioaddr = tp->mmio_addr;
6092         struct pci_dev *pdev = tp->pci_dev;
6093
6094         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6095
6096         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6097         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6098         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6099         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6100
6101         rtl_csi_access_enable_1(tp);
6102
6103         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6104
6105         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6106         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6107
6108         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6109
6110         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6111
6112         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6113         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6114         RTL_W8(MaxTxPacketSize, EarlySize);
6115
6116         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6117         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6118
6119         /* Adjust EEE LED frequency */
6120         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6121
6122         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6123
6124         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6125
6126         rtl_pcie_state_l2l3_enable(tp, false);
6127 }
6128
6129 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6130 {
6131         void __iomem *ioaddr = tp->mmio_addr;
6132         static const struct ephy_info e_info_8168ep_1[] = {
6133                 { 0x00, 0xffff, 0x10ab },
6134                 { 0x06, 0xffff, 0xf030 },
6135                 { 0x08, 0xffff, 0x2006 },
6136                 { 0x0d, 0xffff, 0x1666 },
6137                 { 0x0c, 0x3ff0, 0x0000 }
6138         };
6139
6140         /* disable aspm and clock request before access ephy */
6141         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6142         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6143         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6144
6145         rtl_hw_start_8168ep(tp);
6146 }
6147
6148 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6149 {
6150         void __iomem *ioaddr = tp->mmio_addr;
6151         static const struct ephy_info e_info_8168ep_2[] = {
6152                 { 0x00, 0xffff, 0x10a3 },
6153                 { 0x19, 0xffff, 0xfc00 },
6154                 { 0x1e, 0xffff, 0x20ea }
6155         };
6156
6157         /* disable aspm and clock request before access ephy */
6158         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6159         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6160         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6161
6162         rtl_hw_start_8168ep(tp);
6163
6164         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6165         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6166 }
6167
6168 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6169 {
6170         void __iomem *ioaddr = tp->mmio_addr;
6171         u32 data;
6172         static const struct ephy_info e_info_8168ep_3[] = {
6173                 { 0x00, 0xffff, 0x10a3 },
6174                 { 0x19, 0xffff, 0x7c00 },
6175                 { 0x1e, 0xffff, 0x20eb },
6176                 { 0x0d, 0xffff, 0x1666 }
6177         };
6178
6179         /* disable aspm and clock request before access ephy */
6180         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6181         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6182         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6183
6184         rtl_hw_start_8168ep(tp);
6185
6186         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6187         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6188
6189         data = r8168_mac_ocp_read(tp, 0xd3e2);
6190         data &= 0xf000;
6191         data |= 0x0271;
6192         r8168_mac_ocp_write(tp, 0xd3e2, data);
6193
6194         data = r8168_mac_ocp_read(tp, 0xd3e4);
6195         data &= 0xff00;
6196         r8168_mac_ocp_write(tp, 0xd3e4, data);
6197
6198         data = r8168_mac_ocp_read(tp, 0xe860);
6199         data |= 0x0080;
6200         r8168_mac_ocp_write(tp, 0xe860, data);
6201 }
6202
6203 static void rtl_hw_start_8168(struct net_device *dev)
6204 {
6205         struct rtl8169_private *tp = netdev_priv(dev);
6206         void __iomem *ioaddr = tp->mmio_addr;
6207
6208         RTL_W8(Cfg9346, Cfg9346_Unlock);
6209
6210         RTL_W8(MaxTxPacketSize, TxPacketMax);
6211
6212         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6213
6214         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6215
6216         RTL_W16(CPlusCmd, tp->cp_cmd);
6217
6218         RTL_W16(IntrMitigate, 0x5151);
6219
6220         /* Work around for RxFIFO overflow. */
6221         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6222                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6223                 tp->event_slow &= ~RxOverflow;
6224         }
6225
6226         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6227
6228         rtl_set_rx_tx_config_registers(tp);
6229
6230         RTL_R8(IntrMask);
6231
6232         switch (tp->mac_version) {
6233         case RTL_GIGA_MAC_VER_11:
6234                 rtl_hw_start_8168bb(tp);
6235                 break;
6236
6237         case RTL_GIGA_MAC_VER_12:
6238         case RTL_GIGA_MAC_VER_17:
6239                 rtl_hw_start_8168bef(tp);
6240                 break;
6241
6242         case RTL_GIGA_MAC_VER_18:
6243                 rtl_hw_start_8168cp_1(tp);
6244                 break;
6245
6246         case RTL_GIGA_MAC_VER_19:
6247                 rtl_hw_start_8168c_1(tp);
6248                 break;
6249
6250         case RTL_GIGA_MAC_VER_20:
6251                 rtl_hw_start_8168c_2(tp);
6252                 break;
6253
6254         case RTL_GIGA_MAC_VER_21:
6255                 rtl_hw_start_8168c_3(tp);
6256                 break;
6257
6258         case RTL_GIGA_MAC_VER_22:
6259                 rtl_hw_start_8168c_4(tp);
6260                 break;
6261
6262         case RTL_GIGA_MAC_VER_23:
6263                 rtl_hw_start_8168cp_2(tp);
6264                 break;
6265
6266         case RTL_GIGA_MAC_VER_24:
6267                 rtl_hw_start_8168cp_3(tp);
6268                 break;
6269
6270         case RTL_GIGA_MAC_VER_25:
6271         case RTL_GIGA_MAC_VER_26:
6272         case RTL_GIGA_MAC_VER_27:
6273                 rtl_hw_start_8168d(tp);
6274                 break;
6275
6276         case RTL_GIGA_MAC_VER_28:
6277                 rtl_hw_start_8168d_4(tp);
6278                 break;
6279
6280         case RTL_GIGA_MAC_VER_31:
6281                 rtl_hw_start_8168dp(tp);
6282                 break;
6283
6284         case RTL_GIGA_MAC_VER_32:
6285         case RTL_GIGA_MAC_VER_33:
6286                 rtl_hw_start_8168e_1(tp);
6287                 break;
6288         case RTL_GIGA_MAC_VER_34:
6289                 rtl_hw_start_8168e_2(tp);
6290                 break;
6291
6292         case RTL_GIGA_MAC_VER_35:
6293         case RTL_GIGA_MAC_VER_36:
6294                 rtl_hw_start_8168f_1(tp);
6295                 break;
6296
6297         case RTL_GIGA_MAC_VER_38:
6298                 rtl_hw_start_8411(tp);
6299                 break;
6300
6301         case RTL_GIGA_MAC_VER_40:
6302         case RTL_GIGA_MAC_VER_41:
6303                 rtl_hw_start_8168g_1(tp);
6304                 break;
6305         case RTL_GIGA_MAC_VER_42:
6306                 rtl_hw_start_8168g_2(tp);
6307                 break;
6308
6309         case RTL_GIGA_MAC_VER_44:
6310                 rtl_hw_start_8411_2(tp);
6311                 break;
6312
6313         case RTL_GIGA_MAC_VER_45:
6314         case RTL_GIGA_MAC_VER_46:
6315                 rtl_hw_start_8168h_1(tp);
6316                 break;
6317
6318         case RTL_GIGA_MAC_VER_49:
6319                 rtl_hw_start_8168ep_1(tp);
6320                 break;
6321
6322         case RTL_GIGA_MAC_VER_50:
6323                 rtl_hw_start_8168ep_2(tp);
6324                 break;
6325
6326         case RTL_GIGA_MAC_VER_51:
6327                 rtl_hw_start_8168ep_3(tp);
6328                 break;
6329
6330         default:
6331                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6332                         dev->name, tp->mac_version);
6333                 break;
6334         }
6335
6336         RTL_W8(Cfg9346, Cfg9346_Lock);
6337
6338         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6339
6340         rtl_set_rx_mode(dev);
6341
6342         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6343 }
6344
6345 #define R810X_CPCMD_QUIRK_MASK (\
6346         EnableBist | \
6347         Mac_dbgo_oe | \
6348         Force_half_dup | \
6349         Force_rxflow_en | \
6350         Force_txflow_en | \
6351         Cxpl_dbg_sel | \
6352         ASF | \
6353         PktCntrDisable | \
6354         Mac_dbgo_sel)
6355
6356 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6357 {
6358         void __iomem *ioaddr = tp->mmio_addr;
6359         struct pci_dev *pdev = tp->pci_dev;
6360         static const struct ephy_info e_info_8102e_1[] = {
6361                 { 0x01, 0, 0x6e65 },
6362                 { 0x02, 0, 0x091f },
6363                 { 0x03, 0, 0xc2f9 },
6364                 { 0x06, 0, 0xafb5 },
6365                 { 0x07, 0, 0x0e00 },
6366                 { 0x19, 0, 0xec80 },
6367                 { 0x01, 0, 0x2e65 },
6368                 { 0x01, 0, 0x6e65 }
6369         };
6370         u8 cfg1;
6371
6372         rtl_csi_access_enable_2(tp);
6373
6374         RTL_W8(DBG_REG, FIX_NAK_1);
6375
6376         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6377
6378         RTL_W8(Config1,
6379                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6380         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6381
6382         cfg1 = RTL_R8(Config1);
6383         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6384                 RTL_W8(Config1, cfg1 & ~LEDS0);
6385
6386         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6387 }
6388
6389 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6390 {
6391         void __iomem *ioaddr = tp->mmio_addr;
6392         struct pci_dev *pdev = tp->pci_dev;
6393
6394         rtl_csi_access_enable_2(tp);
6395
6396         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6397
6398         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6399         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6400 }
6401
6402 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6403 {
6404         rtl_hw_start_8102e_2(tp);
6405
6406         rtl_ephy_write(tp, 0x03, 0xc2f9);
6407 }
6408
6409 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6410 {
6411         void __iomem *ioaddr = tp->mmio_addr;
6412         static const struct ephy_info e_info_8105e_1[] = {
6413                 { 0x07, 0, 0x4000 },
6414                 { 0x19, 0, 0x0200 },
6415                 { 0x19, 0, 0x0020 },
6416                 { 0x1e, 0, 0x2000 },
6417                 { 0x03, 0, 0x0001 },
6418                 { 0x19, 0, 0x0100 },
6419                 { 0x19, 0, 0x0004 },
6420                 { 0x0a, 0, 0x0020 }
6421         };
6422
6423         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6424         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6425
6426         /* Disable Early Tally Counter */
6427         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6428
6429         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6430         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6431
6432         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6433
6434         rtl_pcie_state_l2l3_enable(tp, false);
6435 }
6436
6437 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6438 {
6439         rtl_hw_start_8105e_1(tp);
6440         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6441 }
6442
6443 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6444 {
6445         void __iomem *ioaddr = tp->mmio_addr;
6446         static const struct ephy_info e_info_8402[] = {
6447                 { 0x19, 0xffff, 0xff64 },
6448                 { 0x1e, 0, 0x4000 }
6449         };
6450
6451         rtl_csi_access_enable_2(tp);
6452
6453         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6454         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6455
6456         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6457         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6458
6459         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6460
6461         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6462
6463         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6464         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6465         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6466         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6467         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6468         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6469         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6470
6471         rtl_pcie_state_l2l3_enable(tp, false);
6472 }
6473
6474 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6475 {
6476         void __iomem *ioaddr = tp->mmio_addr;
6477
6478         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6479         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6480
6481         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6482         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6483         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6484
6485         rtl_pcie_state_l2l3_enable(tp, false);
6486 }
6487
6488 static void rtl_hw_start_8101(struct net_device *dev)
6489 {
6490         struct rtl8169_private *tp = netdev_priv(dev);
6491         void __iomem *ioaddr = tp->mmio_addr;
6492         struct pci_dev *pdev = tp->pci_dev;
6493
6494         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6495                 tp->event_slow &= ~RxFIFOOver;
6496
6497         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6498             tp->mac_version == RTL_GIGA_MAC_VER_16)
6499                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6500                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6501
6502         RTL_W8(Cfg9346, Cfg9346_Unlock);
6503
6504         RTL_W8(MaxTxPacketSize, TxPacketMax);
6505
6506         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6507
6508         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6509         RTL_W16(CPlusCmd, tp->cp_cmd);
6510
6511         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6512
6513         rtl_set_rx_tx_config_registers(tp);
6514
6515         switch (tp->mac_version) {
6516         case RTL_GIGA_MAC_VER_07:
6517                 rtl_hw_start_8102e_1(tp);
6518                 break;
6519
6520         case RTL_GIGA_MAC_VER_08:
6521                 rtl_hw_start_8102e_3(tp);
6522                 break;
6523
6524         case RTL_GIGA_MAC_VER_09:
6525                 rtl_hw_start_8102e_2(tp);
6526                 break;
6527
6528         case RTL_GIGA_MAC_VER_29:
6529                 rtl_hw_start_8105e_1(tp);
6530                 break;
6531         case RTL_GIGA_MAC_VER_30:
6532                 rtl_hw_start_8105e_2(tp);
6533                 break;
6534
6535         case RTL_GIGA_MAC_VER_37:
6536                 rtl_hw_start_8402(tp);
6537                 break;
6538
6539         case RTL_GIGA_MAC_VER_39:
6540                 rtl_hw_start_8106(tp);
6541                 break;
6542         case RTL_GIGA_MAC_VER_43:
6543                 rtl_hw_start_8168g_2(tp);
6544                 break;
6545         case RTL_GIGA_MAC_VER_47:
6546         case RTL_GIGA_MAC_VER_48:
6547                 rtl_hw_start_8168h_1(tp);
6548                 break;
6549         }
6550
6551         RTL_W8(Cfg9346, Cfg9346_Lock);
6552
6553         RTL_W16(IntrMitigate, 0x0000);
6554
6555         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6556
6557         rtl_set_rx_mode(dev);
6558
6559         RTL_R8(IntrMask);
6560
6561         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6562 }
6563
6564 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6565 {
6566         struct rtl8169_private *tp = netdev_priv(dev);
6567
6568         if (new_mtu < ETH_ZLEN ||
6569             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6570                 return -EINVAL;
6571
6572         if (new_mtu > ETH_DATA_LEN)
6573                 rtl_hw_jumbo_enable(tp);
6574         else
6575                 rtl_hw_jumbo_disable(tp);
6576
6577         dev->mtu = new_mtu;
6578         netdev_update_features(dev);
6579
6580         return 0;
6581 }
6582
6583 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6584 {
6585         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6586         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6587 }
6588
6589 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6590                                      void **data_buff, struct RxDesc *desc)
6591 {
6592         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6593                          DMA_FROM_DEVICE);
6594
6595         kfree(*data_buff);
6596         *data_buff = NULL;
6597         rtl8169_make_unusable_by_asic(desc);
6598 }
6599
6600 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6601 {
6602         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6603
6604         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6605 }
6606
6607 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6608                                        u32 rx_buf_sz)
6609 {
6610         desc->addr = cpu_to_le64(mapping);
6611         wmb();
6612         rtl8169_mark_to_asic(desc, rx_buf_sz);
6613 }
6614
6615 static inline void *rtl8169_align(void *data)
6616 {
6617         return (void *)ALIGN((long)data, 16);
6618 }
6619
6620 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6621                                              struct RxDesc *desc)
6622 {
6623         void *data;
6624         dma_addr_t mapping;
6625         struct device *d = &tp->pci_dev->dev;
6626         struct net_device *dev = tp->dev;
6627         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6628
6629         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6630         if (!data)
6631                 return NULL;
6632
6633         if (rtl8169_align(data) != data) {
6634                 kfree(data);
6635                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6636                 if (!data)
6637                         return NULL;
6638         }
6639
6640         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6641                                  DMA_FROM_DEVICE);
6642         if (unlikely(dma_mapping_error(d, mapping))) {
6643                 if (net_ratelimit())
6644                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6645                 goto err_out;
6646         }
6647
6648         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6649         return data;
6650
6651 err_out:
6652         kfree(data);
6653         return NULL;
6654 }
6655
6656 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6657 {
6658         unsigned int i;
6659
6660         for (i = 0; i < NUM_RX_DESC; i++) {
6661                 if (tp->Rx_databuff[i]) {
6662                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6663                                             tp->RxDescArray + i);
6664                 }
6665         }
6666 }
6667
6668 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6669 {
6670         desc->opts1 |= cpu_to_le32(RingEnd);
6671 }
6672
6673 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6674 {
6675         unsigned int i;
6676
6677         for (i = 0; i < NUM_RX_DESC; i++) {
6678                 void *data;
6679
6680                 if (tp->Rx_databuff[i])
6681                         continue;
6682
6683                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6684                 if (!data) {
6685                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6686                         goto err_out;
6687                 }
6688                 tp->Rx_databuff[i] = data;
6689         }
6690
6691         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6692         return 0;
6693
6694 err_out:
6695         rtl8169_rx_clear(tp);
6696         return -ENOMEM;
6697 }
6698
6699 static int rtl8169_init_ring(struct net_device *dev)
6700 {
6701         struct rtl8169_private *tp = netdev_priv(dev);
6702
6703         rtl8169_init_ring_indexes(tp);
6704
6705         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6706         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6707
6708         return rtl8169_rx_fill(tp);
6709 }
6710
6711 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6712                                  struct TxDesc *desc)
6713 {
6714         unsigned int len = tx_skb->len;
6715
6716         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6717
6718         desc->opts1 = 0x00;
6719         desc->opts2 = 0x00;
6720         desc->addr = 0x00;
6721         tx_skb->len = 0;
6722 }
6723
6724 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6725                                    unsigned int n)
6726 {
6727         unsigned int i;
6728
6729         for (i = 0; i < n; i++) {
6730                 unsigned int entry = (start + i) % NUM_TX_DESC;
6731                 struct ring_info *tx_skb = tp->tx_skb + entry;
6732                 unsigned int len = tx_skb->len;
6733
6734                 if (len) {
6735                         struct sk_buff *skb = tx_skb->skb;
6736
6737                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6738                                              tp->TxDescArray + entry);
6739                         if (skb) {
6740                                 tp->dev->stats.tx_dropped++;
6741                                 dev_kfree_skb_any(skb);
6742                                 tx_skb->skb = NULL;
6743                         }
6744                 }
6745         }
6746 }
6747
6748 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6749 {
6750         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6751         tp->cur_tx = tp->dirty_tx = 0;
6752 }
6753
6754 static void rtl_reset_work(struct rtl8169_private *tp)
6755 {
6756         struct net_device *dev = tp->dev;
6757         int i;
6758
6759         napi_disable(&tp->napi);
6760         netif_stop_queue(dev);
6761         synchronize_sched();
6762
6763         rtl8169_hw_reset(tp);
6764
6765         for (i = 0; i < NUM_RX_DESC; i++)
6766                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6767
6768         rtl8169_tx_clear(tp);
6769         rtl8169_init_ring_indexes(tp);
6770
6771         napi_enable(&tp->napi);
6772         rtl_hw_start(dev);
6773         netif_wake_queue(dev);
6774         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6775 }
6776
6777 static void rtl8169_tx_timeout(struct net_device *dev)
6778 {
6779         struct rtl8169_private *tp = netdev_priv(dev);
6780
6781         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6782 }
6783
6784 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6785                               u32 *opts)
6786 {
6787         struct skb_shared_info *info = skb_shinfo(skb);
6788         unsigned int cur_frag, entry;
6789         struct TxDesc *uninitialized_var(txd);
6790         struct device *d = &tp->pci_dev->dev;
6791
6792         entry = tp->cur_tx;
6793         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6794                 const skb_frag_t *frag = info->frags + cur_frag;
6795                 dma_addr_t mapping;
6796                 u32 status, len;
6797                 void *addr;
6798
6799                 entry = (entry + 1) % NUM_TX_DESC;
6800
6801                 txd = tp->TxDescArray + entry;
6802                 len = skb_frag_size(frag);
6803                 addr = skb_frag_address(frag);
6804                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6805                 if (unlikely(dma_mapping_error(d, mapping))) {
6806                         if (net_ratelimit())
6807                                 netif_err(tp, drv, tp->dev,
6808                                           "Failed to map TX fragments DMA!\n");
6809                         goto err_out;
6810                 }
6811
6812                 /* Anti gcc 2.95.3 bugware (sic) */
6813                 status = opts[0] | len |
6814                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6815
6816                 txd->opts1 = cpu_to_le32(status);
6817                 txd->opts2 = cpu_to_le32(opts[1]);
6818                 txd->addr = cpu_to_le64(mapping);
6819
6820                 tp->tx_skb[entry].len = len;
6821         }
6822
6823         if (cur_frag) {
6824                 tp->tx_skb[entry].skb = skb;
6825                 txd->opts1 |= cpu_to_le32(LastFrag);
6826         }
6827
6828         return cur_frag;
6829
6830 err_out:
6831         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6832         return -EIO;
6833 }
6834
6835 static bool rtl_skb_pad(struct sk_buff *skb)
6836 {
6837         if (skb_padto(skb, ETH_ZLEN))
6838                 return false;
6839         skb_put(skb, ETH_ZLEN - skb->len);
6840         return true;
6841 }
6842
6843 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6844 {
6845         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6846 }
6847
6848 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6849                                       struct net_device *dev);
6850 /* r8169_csum_workaround()
6851  * The hw limites the value the transport offset. When the offset is out of the
6852  * range, calculate the checksum by sw.
6853  */
6854 static void r8169_csum_workaround(struct rtl8169_private *tp,
6855                                   struct sk_buff *skb)
6856 {
6857         if (skb_shinfo(skb)->gso_size) {
6858                 netdev_features_t features = tp->dev->features;
6859                 struct sk_buff *segs, *nskb;
6860
6861                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6862                 segs = skb_gso_segment(skb, features);
6863                 if (IS_ERR(segs) || !segs)
6864                         goto drop;
6865
6866                 do {
6867                         nskb = segs;
6868                         segs = segs->next;
6869                         nskb->next = NULL;
6870                         rtl8169_start_xmit(nskb, tp->dev);
6871                 } while (segs);
6872
6873                 dev_kfree_skb(skb);
6874         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6875                 if (skb_checksum_help(skb) < 0)
6876                         goto drop;
6877
6878                 rtl8169_start_xmit(skb, tp->dev);
6879         } else {
6880                 struct net_device_stats *stats;
6881
6882 drop:
6883                 stats = &tp->dev->stats;
6884                 stats->tx_dropped++;
6885                 dev_kfree_skb(skb);
6886         }
6887 }
6888
6889 /* msdn_giant_send_check()
6890  * According to the document of microsoft, the TCP Pseudo Header excludes the
6891  * packet length for IPv6 TCP large packets.
6892  */
6893 static int msdn_giant_send_check(struct sk_buff *skb)
6894 {
6895         const struct ipv6hdr *ipv6h;
6896         struct tcphdr *th;
6897         int ret;
6898
6899         ret = skb_cow_head(skb, 0);
6900         if (ret)
6901                 return ret;
6902
6903         ipv6h = ipv6_hdr(skb);
6904         th = tcp_hdr(skb);
6905
6906         th->check = 0;
6907         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6908
6909         return ret;
6910 }
6911
6912 static inline __be16 get_protocol(struct sk_buff *skb)
6913 {
6914         __be16 protocol;
6915
6916         if (skb->protocol == htons(ETH_P_8021Q))
6917                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6918         else
6919                 protocol = skb->protocol;
6920
6921         return protocol;
6922 }
6923
6924 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6925                                 struct sk_buff *skb, u32 *opts)
6926 {
6927         u32 mss = skb_shinfo(skb)->gso_size;
6928
6929         if (mss) {
6930                 opts[0] |= TD_LSO;
6931                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6932         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6933                 const struct iphdr *ip = ip_hdr(skb);
6934
6935                 if (ip->protocol == IPPROTO_TCP)
6936                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6937                 else if (ip->protocol == IPPROTO_UDP)
6938                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6939                 else
6940                         WARN_ON_ONCE(1);
6941         }
6942
6943         return true;
6944 }
6945
6946 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6947                                 struct sk_buff *skb, u32 *opts)
6948 {
6949         u32 transport_offset = (u32)skb_transport_offset(skb);
6950         u32 mss = skb_shinfo(skb)->gso_size;
6951
6952         if (mss) {
6953                 if (transport_offset > GTTCPHO_MAX) {
6954                         netif_warn(tp, tx_err, tp->dev,
6955                                    "Invalid transport offset 0x%x for TSO\n",
6956                                    transport_offset);
6957                         return false;
6958                 }
6959
6960                 switch (get_protocol(skb)) {
6961                 case htons(ETH_P_IP):
6962                         opts[0] |= TD1_GTSENV4;
6963                         break;
6964
6965                 case htons(ETH_P_IPV6):
6966                         if (msdn_giant_send_check(skb))
6967                                 return false;
6968
6969                         opts[0] |= TD1_GTSENV6;
6970                         break;
6971
6972                 default:
6973                         WARN_ON_ONCE(1);
6974                         break;
6975                 }
6976
6977                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6978                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6979         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6980                 u8 ip_protocol;
6981
6982                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6983                         return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
6984
6985                 if (transport_offset > TCPHO_MAX) {
6986                         netif_warn(tp, tx_err, tp->dev,
6987                                    "Invalid transport offset 0x%x\n",
6988                                    transport_offset);
6989                         return false;
6990                 }
6991
6992                 switch (get_protocol(skb)) {
6993                 case htons(ETH_P_IP):
6994                         opts[1] |= TD1_IPv4_CS;
6995                         ip_protocol = ip_hdr(skb)->protocol;
6996                         break;
6997
6998                 case htons(ETH_P_IPV6):
6999                         opts[1] |= TD1_IPv6_CS;
7000                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7001                         break;
7002
7003                 default:
7004                         ip_protocol = IPPROTO_RAW;
7005                         break;
7006                 }
7007
7008                 if (ip_protocol == IPPROTO_TCP)
7009                         opts[1] |= TD1_TCP_CS;
7010                 else if (ip_protocol == IPPROTO_UDP)
7011                         opts[1] |= TD1_UDP_CS;
7012                 else
7013                         WARN_ON_ONCE(1);
7014
7015                 opts[1] |= transport_offset << TCPHO_SHIFT;
7016         } else {
7017                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7018                         return rtl_skb_pad(skb);
7019         }
7020
7021         return true;
7022 }
7023
7024 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7025                                       struct net_device *dev)
7026 {
7027         struct rtl8169_private *tp = netdev_priv(dev);
7028         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7029         struct TxDesc *txd = tp->TxDescArray + entry;
7030         void __iomem *ioaddr = tp->mmio_addr;
7031         struct device *d = &tp->pci_dev->dev;
7032         dma_addr_t mapping;
7033         u32 status, len;
7034         u32 opts[2];
7035         int frags;
7036
7037         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7038                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7039                 goto err_stop_0;
7040         }
7041
7042         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7043                 goto err_stop_0;
7044
7045         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7046         opts[0] = DescOwn;
7047
7048         if (!tp->tso_csum(tp, skb, opts)) {
7049                 r8169_csum_workaround(tp, skb);
7050                 return NETDEV_TX_OK;
7051         }
7052
7053         len = skb_headlen(skb);
7054         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7055         if (unlikely(dma_mapping_error(d, mapping))) {
7056                 if (net_ratelimit())
7057                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7058                 goto err_dma_0;
7059         }
7060
7061         tp->tx_skb[entry].len = len;
7062         txd->addr = cpu_to_le64(mapping);
7063
7064         frags = rtl8169_xmit_frags(tp, skb, opts);
7065         if (frags < 0)
7066                 goto err_dma_1;
7067         else if (frags)
7068                 opts[0] |= FirstFrag;
7069         else {
7070                 opts[0] |= FirstFrag | LastFrag;
7071                 tp->tx_skb[entry].skb = skb;
7072         }
7073
7074         txd->opts2 = cpu_to_le32(opts[1]);
7075
7076         netdev_sent_queue(dev, skb->len);
7077
7078         skb_tx_timestamp(skb);
7079
7080         wmb();
7081
7082         /* Anti gcc 2.95.3 bugware (sic) */
7083         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7084         txd->opts1 = cpu_to_le32(status);
7085
7086         tp->cur_tx += frags + 1;
7087
7088         wmb();
7089
7090         RTL_W8(TxPoll, NPQ);
7091
7092         mmiowb();
7093
7094         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7095                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7096                  * not miss a ring update when it notices a stopped queue.
7097                  */
7098                 smp_wmb();
7099                 netif_stop_queue(dev);
7100                 /* Sync with rtl_tx:
7101                  * - publish queue status and cur_tx ring index (write barrier)
7102                  * - refresh dirty_tx ring index (read barrier).
7103                  * May the current thread have a pessimistic view of the ring
7104                  * status and forget to wake up queue, a racing rtl_tx thread
7105                  * can't.
7106                  */
7107                 smp_mb();
7108                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7109                         netif_wake_queue(dev);
7110         }
7111
7112         return NETDEV_TX_OK;
7113
7114 err_dma_1:
7115         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7116 err_dma_0:
7117         dev_kfree_skb_any(skb);
7118         dev->stats.tx_dropped++;
7119         return NETDEV_TX_OK;
7120
7121 err_stop_0:
7122         netif_stop_queue(dev);
7123         dev->stats.tx_dropped++;
7124         return NETDEV_TX_BUSY;
7125 }
7126
7127 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7128 {
7129         struct rtl8169_private *tp = netdev_priv(dev);
7130         struct pci_dev *pdev = tp->pci_dev;
7131         u16 pci_status, pci_cmd;
7132
7133         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7134         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7135
7136         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7137                   pci_cmd, pci_status);
7138
7139         /*
7140          * The recovery sequence below admits a very elaborated explanation:
7141          * - it seems to work;
7142          * - I did not see what else could be done;
7143          * - it makes iop3xx happy.
7144          *
7145          * Feel free to adjust to your needs.
7146          */
7147         if (pdev->broken_parity_status)
7148                 pci_cmd &= ~PCI_COMMAND_PARITY;
7149         else
7150                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7151
7152         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7153
7154         pci_write_config_word(pdev, PCI_STATUS,
7155                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7156                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7157                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7158
7159         /* The infamous DAC f*ckup only happens at boot time */
7160         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7161                 void __iomem *ioaddr = tp->mmio_addr;
7162
7163                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7164                 tp->cp_cmd &= ~PCIDAC;
7165                 RTL_W16(CPlusCmd, tp->cp_cmd);
7166                 dev->features &= ~NETIF_F_HIGHDMA;
7167         }
7168
7169         rtl8169_hw_reset(tp);
7170
7171         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7172 }
7173
7174 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7175 {
7176         unsigned int dirty_tx, tx_left;
7177         unsigned int bytes_compl = 0, pkts_compl = 0;
7178
7179         dirty_tx = tp->dirty_tx;
7180         smp_rmb();
7181         tx_left = tp->cur_tx - dirty_tx;
7182
7183         while (tx_left > 0) {
7184                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7185                 struct ring_info *tx_skb = tp->tx_skb + entry;
7186                 u32 status;
7187
7188                 rmb();
7189                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7190                 if (status & DescOwn)
7191                         break;
7192
7193                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7194                                      tp->TxDescArray + entry);
7195                 if (status & LastFrag) {
7196                         pkts_compl++;
7197                         bytes_compl += tx_skb->skb->len;
7198                         dev_kfree_skb_any(tx_skb->skb);
7199                         tx_skb->skb = NULL;
7200                 }
7201                 dirty_tx++;
7202                 tx_left--;
7203         }
7204
7205         if (tp->dirty_tx != dirty_tx) {
7206                 netdev_completed_queue(tp->dev, pkts_compl, bytes_compl);
7207
7208                 u64_stats_update_begin(&tp->tx_stats.syncp);
7209                 tp->tx_stats.packets += pkts_compl;
7210                 tp->tx_stats.bytes += bytes_compl;
7211                 u64_stats_update_end(&tp->tx_stats.syncp);
7212
7213                 tp->dirty_tx = dirty_tx;
7214                 /* Sync with rtl8169_start_xmit:
7215                  * - publish dirty_tx ring index (write barrier)
7216                  * - refresh cur_tx ring index and queue status (read barrier)
7217                  * May the current thread miss the stopped queue condition,
7218                  * a racing xmit thread can only have a right view of the
7219                  * ring status.
7220                  */
7221                 smp_mb();
7222                 if (netif_queue_stopped(dev) &&
7223                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7224                         netif_wake_queue(dev);
7225                 }
7226                 /*
7227                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7228                  * too close. Let's kick an extra TxPoll request when a burst
7229                  * of start_xmit activity is detected (if it is not detected,
7230                  * it is slow enough). -- FR
7231                  */
7232                 if (tp->cur_tx != dirty_tx) {
7233                         void __iomem *ioaddr = tp->mmio_addr;
7234
7235                         RTL_W8(TxPoll, NPQ);
7236                 }
7237         }
7238 }
7239
7240 static inline int rtl8169_fragmented_frame(u32 status)
7241 {
7242         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7243 }
7244
7245 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7246 {
7247         u32 status = opts1 & RxProtoMask;
7248
7249         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7250             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7251                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7252         else
7253                 skb_checksum_none_assert(skb);
7254 }
7255
7256 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7257                                            struct rtl8169_private *tp,
7258                                            int pkt_size,
7259                                            dma_addr_t addr)
7260 {
7261         struct sk_buff *skb;
7262         struct device *d = &tp->pci_dev->dev;
7263
7264         data = rtl8169_align(data);
7265         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7266         prefetch(data);
7267         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
7268         if (skb)
7269                 memcpy(skb->data, data, pkt_size);
7270         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7271
7272         return skb;
7273 }
7274
7275 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7276 {
7277         unsigned int cur_rx, rx_left;
7278         unsigned int count;
7279
7280         cur_rx = tp->cur_rx;
7281
7282         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7283                 unsigned int entry = cur_rx % NUM_RX_DESC;
7284                 struct RxDesc *desc = tp->RxDescArray + entry;
7285                 u32 status;
7286
7287                 rmb();
7288                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7289
7290                 if (status & DescOwn)
7291                         break;
7292                 if (unlikely(status & RxRES)) {
7293                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7294                                    status);
7295                         dev->stats.rx_errors++;
7296                         if (status & (RxRWT | RxRUNT))
7297                                 dev->stats.rx_length_errors++;
7298                         if (status & RxCRC)
7299                                 dev->stats.rx_crc_errors++;
7300                         if (status & RxFOVF) {
7301                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7302                                 dev->stats.rx_fifo_errors++;
7303                         }
7304                         if ((status & (RxRUNT | RxCRC)) &&
7305                             !(status & (RxRWT | RxFOVF)) &&
7306                             (dev->features & NETIF_F_RXALL))
7307                                 goto process_pkt;
7308                 } else {
7309                         struct sk_buff *skb;
7310                         dma_addr_t addr;
7311                         int pkt_size;
7312
7313 process_pkt:
7314                         addr = le64_to_cpu(desc->addr);
7315                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7316                                 pkt_size = (status & 0x00003fff) - 4;
7317                         else
7318                                 pkt_size = status & 0x00003fff;
7319
7320                         /*
7321                          * The driver does not support incoming fragmented
7322                          * frames. They are seen as a symptom of over-mtu
7323                          * sized frames.
7324                          */
7325                         if (unlikely(rtl8169_fragmented_frame(status))) {
7326                                 dev->stats.rx_dropped++;
7327                                 dev->stats.rx_length_errors++;
7328                                 goto release_descriptor;
7329                         }
7330
7331                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7332                                                   tp, pkt_size, addr);
7333                         if (!skb) {
7334                                 dev->stats.rx_dropped++;
7335                                 goto release_descriptor;
7336                         }
7337
7338                         rtl8169_rx_csum(skb, status);
7339                         skb_put(skb, pkt_size);
7340                         skb->protocol = eth_type_trans(skb, dev);
7341
7342                         rtl8169_rx_vlan_tag(desc, skb);
7343
7344                         napi_gro_receive(&tp->napi, skb);
7345
7346                         u64_stats_update_begin(&tp->rx_stats.syncp);
7347                         tp->rx_stats.packets++;
7348                         tp->rx_stats.bytes += pkt_size;
7349                         u64_stats_update_end(&tp->rx_stats.syncp);
7350                 }
7351 release_descriptor:
7352                 desc->opts2 = 0;
7353                 wmb();
7354                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7355         }
7356
7357         count = cur_rx - tp->cur_rx;
7358         tp->cur_rx = cur_rx;
7359
7360         return count;
7361 }
7362
7363 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7364 {
7365         struct net_device *dev = dev_instance;
7366         struct rtl8169_private *tp = netdev_priv(dev);
7367         int handled = 0;
7368         u16 status;
7369
7370         status = rtl_get_events(tp);
7371         if (status && status != 0xffff) {
7372                 status &= RTL_EVENT_NAPI | tp->event_slow;
7373                 if (status) {
7374                         handled = 1;
7375
7376                         rtl_irq_disable(tp);
7377                         napi_schedule(&tp->napi);
7378                 }
7379         }
7380         return IRQ_RETVAL(handled);
7381 }
7382
7383 /*
7384  * Workqueue context.
7385  */
7386 static void rtl_slow_event_work(struct rtl8169_private *tp)
7387 {
7388         struct net_device *dev = tp->dev;
7389         u16 status;
7390
7391         status = rtl_get_events(tp) & tp->event_slow;
7392         rtl_ack_events(tp, status);
7393
7394         if (unlikely(status & RxFIFOOver)) {
7395                 switch (tp->mac_version) {
7396                 /* Work around for rx fifo overflow */
7397                 case RTL_GIGA_MAC_VER_11:
7398                         netif_stop_queue(dev);
7399                         /* XXX - Hack alert. See rtl_task(). */
7400                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7401                 default:
7402                         break;
7403                 }
7404         }
7405
7406         if (unlikely(status & SYSErr))
7407                 rtl8169_pcierr_interrupt(dev);
7408
7409         if (status & LinkChg)
7410                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7411
7412         rtl_irq_enable_all(tp);
7413 }
7414
7415 static void rtl_task(struct work_struct *work)
7416 {
7417         static const struct {
7418                 int bitnr;
7419                 void (*action)(struct rtl8169_private *);
7420         } rtl_work[] = {
7421                 /* XXX - keep rtl_slow_event_work() as first element. */
7422                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7423                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7424                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7425         };
7426         struct rtl8169_private *tp =
7427                 container_of(work, struct rtl8169_private, wk.work);
7428         struct net_device *dev = tp->dev;
7429         int i;
7430
7431         rtl_lock_work(tp);
7432
7433         if (!netif_running(dev) ||
7434             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7435                 goto out_unlock;
7436
7437         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7438                 bool pending;
7439
7440                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7441                 if (pending)
7442                         rtl_work[i].action(tp);
7443         }
7444
7445 out_unlock:
7446         rtl_unlock_work(tp);
7447 }
7448
7449 static int rtl8169_poll(struct napi_struct *napi, int budget)
7450 {
7451         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7452         struct net_device *dev = tp->dev;
7453         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7454         int work_done= 0;
7455         u16 status;
7456
7457         status = rtl_get_events(tp);
7458         rtl_ack_events(tp, status & ~tp->event_slow);
7459
7460         if (status & RTL_EVENT_NAPI_RX)
7461                 work_done = rtl_rx(dev, tp, (u32) budget);
7462
7463         if (status & RTL_EVENT_NAPI_TX)
7464                 rtl_tx(dev, tp);
7465
7466         if (status & tp->event_slow) {
7467                 enable_mask &= ~tp->event_slow;
7468
7469                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7470         }
7471
7472         if (work_done < budget) {
7473                 napi_complete(napi);
7474
7475                 rtl_irq_enable(tp, enable_mask);
7476                 mmiowb();
7477         }
7478
7479         return work_done;
7480 }
7481
7482 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7483 {
7484         struct rtl8169_private *tp = netdev_priv(dev);
7485
7486         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7487                 return;
7488
7489         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7490         RTL_W32(RxMissed, 0);
7491 }
7492
7493 static void rtl8169_down(struct net_device *dev)
7494 {
7495         struct rtl8169_private *tp = netdev_priv(dev);
7496         void __iomem *ioaddr = tp->mmio_addr;
7497
7498         del_timer_sync(&tp->timer);
7499
7500         napi_disable(&tp->napi);
7501         netif_stop_queue(dev);
7502
7503         rtl8169_hw_reset(tp);
7504         /*
7505          * At this point device interrupts can not be enabled in any function,
7506          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7507          * and napi is disabled (rtl8169_poll).
7508          */
7509         rtl8169_rx_missed(dev, ioaddr);
7510
7511         /* Give a racing hard_start_xmit a few cycles to complete. */
7512         synchronize_sched();
7513
7514         rtl8169_tx_clear(tp);
7515
7516         rtl8169_rx_clear(tp);
7517
7518         rtl_pll_power_down(tp);
7519 }
7520
7521 static int rtl8169_close(struct net_device *dev)
7522 {
7523         struct rtl8169_private *tp = netdev_priv(dev);
7524         struct pci_dev *pdev = tp->pci_dev;
7525
7526         pm_runtime_get_sync(&pdev->dev);
7527
7528         /* Update counters before going down */
7529         rtl8169_update_counters(dev);
7530
7531         rtl_lock_work(tp);
7532         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7533
7534         rtl8169_down(dev);
7535         rtl_unlock_work(tp);
7536
7537         cancel_work_sync(&tp->wk.work);
7538
7539         free_irq(pdev->irq, dev);
7540
7541         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7542                           tp->RxPhyAddr);
7543         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7544                           tp->TxPhyAddr);
7545         tp->TxDescArray = NULL;
7546         tp->RxDescArray = NULL;
7547
7548         pm_runtime_put_sync(&pdev->dev);
7549
7550         return 0;
7551 }
7552
7553 #ifdef CONFIG_NET_POLL_CONTROLLER
7554 static void rtl8169_netpoll(struct net_device *dev)
7555 {
7556         struct rtl8169_private *tp = netdev_priv(dev);
7557
7558         rtl8169_interrupt(tp->pci_dev->irq, dev);
7559 }
7560 #endif
7561
7562 static int rtl_open(struct net_device *dev)
7563 {
7564         struct rtl8169_private *tp = netdev_priv(dev);
7565         void __iomem *ioaddr = tp->mmio_addr;
7566         struct pci_dev *pdev = tp->pci_dev;
7567         int retval = -ENOMEM;
7568
7569         pm_runtime_get_sync(&pdev->dev);
7570
7571         /*
7572          * Rx and Tx descriptors needs 256 bytes alignment.
7573          * dma_alloc_coherent provides more.
7574          */
7575         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7576                                              &tp->TxPhyAddr, GFP_KERNEL);
7577         if (!tp->TxDescArray)
7578                 goto err_pm_runtime_put;
7579
7580         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7581                                              &tp->RxPhyAddr, GFP_KERNEL);
7582         if (!tp->RxDescArray)
7583                 goto err_free_tx_0;
7584
7585         retval = rtl8169_init_ring(dev);
7586         if (retval < 0)
7587                 goto err_free_rx_1;
7588
7589         INIT_WORK(&tp->wk.work, rtl_task);
7590
7591         smp_mb();
7592
7593         rtl_request_firmware(tp);
7594
7595         retval = request_irq(pdev->irq, rtl8169_interrupt,
7596                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7597                              dev->name, dev);
7598         if (retval < 0)
7599                 goto err_release_fw_2;
7600
7601         rtl_lock_work(tp);
7602
7603         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7604
7605         napi_enable(&tp->napi);
7606
7607         rtl8169_init_phy(dev, tp);
7608
7609         __rtl8169_set_features(dev, dev->features);
7610
7611         rtl_pll_power_up(tp);
7612
7613         rtl_hw_start(dev);
7614
7615         netif_start_queue(dev);
7616
7617         rtl_unlock_work(tp);
7618
7619         tp->saved_wolopts = 0;
7620         pm_runtime_put_noidle(&pdev->dev);
7621
7622         rtl8169_check_link_status(dev, tp, ioaddr);
7623 out:
7624         return retval;
7625
7626 err_release_fw_2:
7627         rtl_release_firmware(tp);
7628         rtl8169_rx_clear(tp);
7629 err_free_rx_1:
7630         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7631                           tp->RxPhyAddr);
7632         tp->RxDescArray = NULL;
7633 err_free_tx_0:
7634         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7635                           tp->TxPhyAddr);
7636         tp->TxDescArray = NULL;
7637 err_pm_runtime_put:
7638         pm_runtime_put_noidle(&pdev->dev);
7639         goto out;
7640 }
7641
7642 static struct rtnl_link_stats64 *
7643 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7644 {
7645         struct rtl8169_private *tp = netdev_priv(dev);
7646         void __iomem *ioaddr = tp->mmio_addr;
7647         unsigned int start;
7648
7649         if (netif_running(dev))
7650                 rtl8169_rx_missed(dev, ioaddr);
7651
7652         do {
7653                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7654                 stats->rx_packets = tp->rx_stats.packets;
7655                 stats->rx_bytes = tp->rx_stats.bytes;
7656         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7657
7658
7659         do {
7660                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7661                 stats->tx_packets = tp->tx_stats.packets;
7662                 stats->tx_bytes = tp->tx_stats.bytes;
7663         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7664
7665         stats->rx_dropped       = dev->stats.rx_dropped;
7666         stats->tx_dropped       = dev->stats.tx_dropped;
7667         stats->rx_length_errors = dev->stats.rx_length_errors;
7668         stats->rx_errors        = dev->stats.rx_errors;
7669         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7670         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7671         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7672
7673         return stats;
7674 }
7675
7676 static void rtl8169_net_suspend(struct net_device *dev)
7677 {
7678         struct rtl8169_private *tp = netdev_priv(dev);
7679
7680         if (!netif_running(dev))
7681                 return;
7682
7683         netif_device_detach(dev);
7684         netif_stop_queue(dev);
7685
7686         rtl_lock_work(tp);
7687         napi_disable(&tp->napi);
7688         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7689         rtl_unlock_work(tp);
7690
7691         rtl_pll_power_down(tp);
7692 }
7693
7694 #ifdef CONFIG_PM
7695
7696 static int rtl8169_suspend(struct device *device)
7697 {
7698         struct pci_dev *pdev = to_pci_dev(device);
7699         struct net_device *dev = pci_get_drvdata(pdev);
7700
7701         rtl8169_net_suspend(dev);
7702
7703         return 0;
7704 }
7705
7706 static void __rtl8169_resume(struct net_device *dev)
7707 {
7708         struct rtl8169_private *tp = netdev_priv(dev);
7709
7710         netif_device_attach(dev);
7711
7712         rtl_pll_power_up(tp);
7713
7714         rtl_lock_work(tp);
7715         napi_enable(&tp->napi);
7716         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7717         rtl_unlock_work(tp);
7718
7719         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7720 }
7721
7722 static int rtl8169_resume(struct device *device)
7723 {
7724         struct pci_dev *pdev = to_pci_dev(device);
7725         struct net_device *dev = pci_get_drvdata(pdev);
7726         struct rtl8169_private *tp = netdev_priv(dev);
7727
7728         rtl8169_init_phy(dev, tp);
7729
7730         if (netif_running(dev))
7731                 __rtl8169_resume(dev);
7732
7733         return 0;
7734 }
7735
7736 static int rtl8169_runtime_suspend(struct device *device)
7737 {
7738         struct pci_dev *pdev = to_pci_dev(device);
7739         struct net_device *dev = pci_get_drvdata(pdev);
7740         struct rtl8169_private *tp = netdev_priv(dev);
7741
7742         if (!tp->TxDescArray)
7743                 return 0;
7744
7745         rtl_lock_work(tp);
7746         tp->saved_wolopts = __rtl8169_get_wol(tp);
7747         __rtl8169_set_wol(tp, WAKE_ANY);
7748         rtl_unlock_work(tp);
7749
7750         rtl8169_net_suspend(dev);
7751
7752         return 0;
7753 }
7754
7755 static int rtl8169_runtime_resume(struct device *device)
7756 {
7757         struct pci_dev *pdev = to_pci_dev(device);
7758         struct net_device *dev = pci_get_drvdata(pdev);
7759         struct rtl8169_private *tp = netdev_priv(dev);
7760
7761         if (!tp->TxDescArray)
7762                 return 0;
7763
7764         rtl_lock_work(tp);
7765         __rtl8169_set_wol(tp, tp->saved_wolopts);
7766         tp->saved_wolopts = 0;
7767         rtl_unlock_work(tp);
7768
7769         rtl8169_init_phy(dev, tp);
7770
7771         __rtl8169_resume(dev);
7772
7773         return 0;
7774 }
7775
7776 static int rtl8169_runtime_idle(struct device *device)
7777 {
7778         struct pci_dev *pdev = to_pci_dev(device);
7779         struct net_device *dev = pci_get_drvdata(pdev);
7780         struct rtl8169_private *tp = netdev_priv(dev);
7781
7782         return tp->TxDescArray ? -EBUSY : 0;
7783 }
7784
7785 static const struct dev_pm_ops rtl8169_pm_ops = {
7786         .suspend                = rtl8169_suspend,
7787         .resume                 = rtl8169_resume,
7788         .freeze                 = rtl8169_suspend,
7789         .thaw                   = rtl8169_resume,
7790         .poweroff               = rtl8169_suspend,
7791         .restore                = rtl8169_resume,
7792         .runtime_suspend        = rtl8169_runtime_suspend,
7793         .runtime_resume         = rtl8169_runtime_resume,
7794         .runtime_idle           = rtl8169_runtime_idle,
7795 };
7796
7797 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7798
7799 #else /* !CONFIG_PM */
7800
7801 #define RTL8169_PM_OPS  NULL
7802
7803 #endif /* !CONFIG_PM */
7804
7805 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7806 {
7807         void __iomem *ioaddr = tp->mmio_addr;
7808
7809         /* WoL fails with 8168b when the receiver is disabled. */
7810         switch (tp->mac_version) {
7811         case RTL_GIGA_MAC_VER_11:
7812         case RTL_GIGA_MAC_VER_12:
7813         case RTL_GIGA_MAC_VER_17:
7814                 pci_clear_master(tp->pci_dev);
7815
7816                 RTL_W8(ChipCmd, CmdRxEnb);
7817                 /* PCI commit */
7818                 RTL_R8(ChipCmd);
7819                 break;
7820         default:
7821                 break;
7822         }
7823 }
7824
7825 static void rtl_shutdown(struct pci_dev *pdev)
7826 {
7827         struct net_device *dev = pci_get_drvdata(pdev);
7828         struct rtl8169_private *tp = netdev_priv(dev);
7829         struct device *d = &pdev->dev;
7830
7831         pm_runtime_get_sync(d);
7832
7833         rtl8169_net_suspend(dev);
7834
7835         /* Restore original MAC address */
7836         rtl_rar_set(tp, dev->perm_addr);
7837
7838         rtl8169_hw_reset(tp);
7839
7840         if (system_state == SYSTEM_POWER_OFF) {
7841                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7842                         rtl_wol_suspend_quirk(tp);
7843                         rtl_wol_shutdown_quirk(tp);
7844                 }
7845
7846                 pci_wake_from_d3(pdev, true);
7847                 pci_set_power_state(pdev, PCI_D3hot);
7848         }
7849
7850         pm_runtime_put_noidle(d);
7851 }
7852
7853 static void rtl_remove_one(struct pci_dev *pdev)
7854 {
7855         struct net_device *dev = pci_get_drvdata(pdev);
7856         struct rtl8169_private *tp = netdev_priv(dev);
7857
7858         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7859              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7860              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7861              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7862              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7863              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7864             r8168_check_dash(tp)) {
7865                 rtl8168_driver_stop(tp);
7866         }
7867
7868         netif_napi_del(&tp->napi);
7869
7870         unregister_netdev(dev);
7871
7872         rtl_release_firmware(tp);
7873
7874         if (pci_dev_run_wake(pdev))
7875                 pm_runtime_get_noresume(&pdev->dev);
7876
7877         /* restore original MAC address */
7878         rtl_rar_set(tp, dev->perm_addr);
7879
7880         rtl_disable_msi(pdev, tp);
7881         rtl8169_release_board(pdev, dev, tp->mmio_addr);
7882 }
7883
7884 static const struct net_device_ops rtl_netdev_ops = {
7885         .ndo_open               = rtl_open,
7886         .ndo_stop               = rtl8169_close,
7887         .ndo_get_stats64        = rtl8169_get_stats64,
7888         .ndo_start_xmit         = rtl8169_start_xmit,
7889         .ndo_tx_timeout         = rtl8169_tx_timeout,
7890         .ndo_validate_addr      = eth_validate_addr,
7891         .ndo_change_mtu         = rtl8169_change_mtu,
7892         .ndo_fix_features       = rtl8169_fix_features,
7893         .ndo_set_features       = rtl8169_set_features,
7894         .ndo_set_mac_address    = rtl_set_mac_address,
7895         .ndo_do_ioctl           = rtl8169_ioctl,
7896         .ndo_set_rx_mode        = rtl_set_rx_mode,
7897 #ifdef CONFIG_NET_POLL_CONTROLLER
7898         .ndo_poll_controller    = rtl8169_netpoll,
7899 #endif
7900
7901 };
7902
7903 static const struct rtl_cfg_info {
7904         void (*hw_start)(struct net_device *);
7905         unsigned int region;
7906         unsigned int align;
7907         u16 event_slow;
7908         unsigned features;
7909         u8 default_ver;
7910 } rtl_cfg_infos [] = {
7911         [RTL_CFG_0] = {
7912                 .hw_start       = rtl_hw_start_8169,
7913                 .region         = 1,
7914                 .align          = 0,
7915                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7916                 .features       = RTL_FEATURE_GMII,
7917                 .default_ver    = RTL_GIGA_MAC_VER_01,
7918         },
7919         [RTL_CFG_1] = {
7920                 .hw_start       = rtl_hw_start_8168,
7921                 .region         = 2,
7922                 .align          = 8,
7923                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7924                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7925                 .default_ver    = RTL_GIGA_MAC_VER_11,
7926         },
7927         [RTL_CFG_2] = {
7928                 .hw_start       = rtl_hw_start_8101,
7929                 .region         = 2,
7930                 .align          = 8,
7931                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7932                                   PCSTimeout,
7933                 .features       = RTL_FEATURE_MSI,
7934                 .default_ver    = RTL_GIGA_MAC_VER_13,
7935         }
7936 };
7937
7938 /* Cfg9346_Unlock assumed. */
7939 static unsigned rtl_try_msi(struct rtl8169_private *tp,
7940                             const struct rtl_cfg_info *cfg)
7941 {
7942         void __iomem *ioaddr = tp->mmio_addr;
7943         unsigned msi = 0;
7944         u8 cfg2;
7945
7946         cfg2 = RTL_R8(Config2) & ~MSIEnable;
7947         if (cfg->features & RTL_FEATURE_MSI) {
7948                 if (pci_enable_msi(tp->pci_dev)) {
7949                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7950                 } else {
7951                         cfg2 |= MSIEnable;
7952                         msi = RTL_FEATURE_MSI;
7953                 }
7954         }
7955         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7956                 RTL_W8(Config2, cfg2);
7957         return msi;
7958 }
7959
7960 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7961 {
7962         void __iomem *ioaddr = tp->mmio_addr;
7963
7964         return RTL_R8(MCU) & LINK_LIST_RDY;
7965 }
7966
7967 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7968 {
7969         void __iomem *ioaddr = tp->mmio_addr;
7970
7971         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7972 }
7973
7974 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7975 {
7976         void __iomem *ioaddr = tp->mmio_addr;
7977         u32 data;
7978
7979         tp->ocp_base = OCP_STD_PHY_BASE;
7980
7981         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7982
7983         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7984                 return;
7985
7986         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7987                 return;
7988
7989         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7990         msleep(1);
7991         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7992
7993         data = r8168_mac_ocp_read(tp, 0xe8de);
7994         data &= ~(1 << 14);
7995         r8168_mac_ocp_write(tp, 0xe8de, data);
7996
7997         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7998                 return;
7999
8000         data = r8168_mac_ocp_read(tp, 0xe8de);
8001         data |= (1 << 15);
8002         r8168_mac_ocp_write(tp, 0xe8de, data);
8003
8004         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8005                 return;
8006 }
8007
8008 static void rtl_hw_initialize(struct rtl8169_private *tp)
8009 {
8010         switch (tp->mac_version) {
8011         case RTL_GIGA_MAC_VER_40:
8012         case RTL_GIGA_MAC_VER_41:
8013         case RTL_GIGA_MAC_VER_42:
8014         case RTL_GIGA_MAC_VER_43:
8015         case RTL_GIGA_MAC_VER_44:
8016         case RTL_GIGA_MAC_VER_45:
8017         case RTL_GIGA_MAC_VER_46:
8018         case RTL_GIGA_MAC_VER_47:
8019         case RTL_GIGA_MAC_VER_48:
8020         case RTL_GIGA_MAC_VER_49:
8021         case RTL_GIGA_MAC_VER_50:
8022         case RTL_GIGA_MAC_VER_51:
8023                 rtl_hw_init_8168g(tp);
8024                 break;
8025
8026         default:
8027                 break;
8028         }
8029 }
8030
8031 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8032 {
8033         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8034         const unsigned int region = cfg->region;
8035         struct rtl8169_private *tp;
8036         struct mii_if_info *mii;
8037         struct net_device *dev;
8038         void __iomem *ioaddr;
8039         int chipset, i;
8040         int rc;
8041
8042         if (netif_msg_drv(&debug)) {
8043                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8044                        MODULENAME, RTL8169_VERSION);
8045         }
8046
8047         dev = alloc_etherdev(sizeof (*tp));
8048         if (!dev) {
8049                 rc = -ENOMEM;
8050                 goto out;
8051         }
8052
8053         SET_NETDEV_DEV(dev, &pdev->dev);
8054         dev->netdev_ops = &rtl_netdev_ops;
8055         tp = netdev_priv(dev);
8056         tp->dev = dev;
8057         tp->pci_dev = pdev;
8058         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8059
8060         mii = &tp->mii;
8061         mii->dev = dev;
8062         mii->mdio_read = rtl_mdio_read;
8063         mii->mdio_write = rtl_mdio_write;
8064         mii->phy_id_mask = 0x1f;
8065         mii->reg_num_mask = 0x1f;
8066         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8067
8068         /* disable ASPM completely as that cause random device stop working
8069          * problems as well as full system hangs for some PCIe devices users */
8070         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8071                                      PCIE_LINK_STATE_CLKPM);
8072
8073         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8074         rc = pci_enable_device(pdev);
8075         if (rc < 0) {
8076                 netif_err(tp, probe, dev, "enable failure\n");
8077                 goto err_out_free_dev_1;
8078         }
8079
8080         if (pci_set_mwi(pdev) < 0)
8081                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8082
8083         /* make sure PCI base addr 1 is MMIO */
8084         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8085                 netif_err(tp, probe, dev,
8086                           "region #%d not an MMIO resource, aborting\n",
8087                           region);
8088                 rc = -ENODEV;
8089                 goto err_out_mwi_2;
8090         }
8091
8092         /* check for weird/broken PCI region reporting */
8093         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8094                 netif_err(tp, probe, dev,
8095                           "Invalid PCI region size(s), aborting\n");
8096                 rc = -ENODEV;
8097                 goto err_out_mwi_2;
8098         }
8099
8100         rc = pci_request_regions(pdev, MODULENAME);
8101         if (rc < 0) {
8102                 netif_err(tp, probe, dev, "could not request regions\n");
8103                 goto err_out_mwi_2;
8104         }
8105
8106         tp->cp_cmd = 0;
8107
8108         if ((sizeof(dma_addr_t) > 4) &&
8109             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8110                 tp->cp_cmd |= PCIDAC;
8111                 dev->features |= NETIF_F_HIGHDMA;
8112         } else {
8113                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8114                 if (rc < 0) {
8115                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8116                         goto err_out_free_res_3;
8117                 }
8118         }
8119
8120         /* ioremap MMIO region */
8121         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8122         if (!ioaddr) {
8123                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8124                 rc = -EIO;
8125                 goto err_out_free_res_3;
8126         }
8127         tp->mmio_addr = ioaddr;
8128
8129         if (!pci_is_pcie(pdev))
8130                 netif_info(tp, probe, dev, "not PCI Express\n");
8131
8132         /* Identify chip attached to board */
8133         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8134
8135         rtl_init_rxcfg(tp);
8136
8137         rtl_irq_disable(tp);
8138
8139         rtl_hw_initialize(tp);
8140
8141         rtl_hw_reset(tp);
8142
8143         rtl_ack_events(tp, 0xffff);
8144
8145         pci_set_master(pdev);
8146
8147         rtl_init_mdio_ops(tp);
8148         rtl_init_pll_power_ops(tp);
8149         rtl_init_jumbo_ops(tp);
8150         rtl_init_csi_ops(tp);
8151
8152         rtl8169_print_mac_version(tp);
8153
8154         chipset = tp->mac_version;
8155         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8156
8157         RTL_W8(Cfg9346, Cfg9346_Unlock);
8158         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8159         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8160         switch (tp->mac_version) {
8161         case RTL_GIGA_MAC_VER_34:
8162         case RTL_GIGA_MAC_VER_35:
8163         case RTL_GIGA_MAC_VER_36:
8164         case RTL_GIGA_MAC_VER_37:
8165         case RTL_GIGA_MAC_VER_38:
8166         case RTL_GIGA_MAC_VER_40:
8167         case RTL_GIGA_MAC_VER_41:
8168         case RTL_GIGA_MAC_VER_42:
8169         case RTL_GIGA_MAC_VER_43:
8170         case RTL_GIGA_MAC_VER_44:
8171         case RTL_GIGA_MAC_VER_45:
8172         case RTL_GIGA_MAC_VER_46:
8173         case RTL_GIGA_MAC_VER_47:
8174         case RTL_GIGA_MAC_VER_48:
8175         case RTL_GIGA_MAC_VER_49:
8176         case RTL_GIGA_MAC_VER_50:
8177         case RTL_GIGA_MAC_VER_51:
8178                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8179                         tp->features |= RTL_FEATURE_WOL;
8180                 if ((RTL_R8(Config3) & LinkUp) != 0)
8181                         tp->features |= RTL_FEATURE_WOL;
8182                 break;
8183         default:
8184                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8185                         tp->features |= RTL_FEATURE_WOL;
8186                 break;
8187         }
8188         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8189                 tp->features |= RTL_FEATURE_WOL;
8190         tp->features |= rtl_try_msi(tp, cfg);
8191         RTL_W8(Cfg9346, Cfg9346_Lock);
8192
8193         if (rtl_tbi_enabled(tp)) {
8194                 tp->set_speed = rtl8169_set_speed_tbi;
8195                 tp->get_settings = rtl8169_gset_tbi;
8196                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8197                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8198                 tp->link_ok = rtl8169_tbi_link_ok;
8199                 tp->do_ioctl = rtl_tbi_ioctl;
8200         } else {
8201                 tp->set_speed = rtl8169_set_speed_xmii;
8202                 tp->get_settings = rtl8169_gset_xmii;
8203                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8204                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8205                 tp->link_ok = rtl8169_xmii_link_ok;
8206                 tp->do_ioctl = rtl_xmii_ioctl;
8207         }
8208
8209         mutex_init(&tp->wk.mutex);
8210         u64_stats_init(&tp->rx_stats.syncp);
8211         u64_stats_init(&tp->tx_stats.syncp);
8212
8213         /* Get MAC address */
8214         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8215             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8216             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8217             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8218             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8219             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8220             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8221             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8222             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8223             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8224             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8225             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8226             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8227             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8228             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8229             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8230                 u16 mac_addr[3];
8231
8232                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8233                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8234
8235                 if (is_valid_ether_addr((u8 *)mac_addr))
8236                         rtl_rar_set(tp, (u8 *)mac_addr);
8237         }
8238         for (i = 0; i < ETH_ALEN; i++)
8239                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8240
8241         dev->ethtool_ops = &rtl8169_ethtool_ops;
8242         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8243
8244         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8245
8246         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8247          * properly for all devices */
8248         dev->features |= NETIF_F_RXCSUM |
8249                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8250
8251         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8252                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8253                 NETIF_F_HW_VLAN_CTAG_RX;
8254         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8255                 NETIF_F_HIGHDMA;
8256
8257         tp->cp_cmd |= RxChkSum | RxVlan;
8258
8259         /*
8260          * Pretend we are using VLANs; This bypasses a nasty bug where
8261          * Interrupts stop flowing on high load on 8110SCd controllers.
8262          */
8263         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8264                 /* Disallow toggling */
8265                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8266
8267         if (tp->txd_version == RTL_TD_0)
8268                 tp->tso_csum = rtl8169_tso_csum_v1;
8269         else if (tp->txd_version == RTL_TD_1) {
8270                 tp->tso_csum = rtl8169_tso_csum_v2;
8271                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8272         } else
8273                 WARN_ON_ONCE(1);
8274
8275         dev->hw_features |= NETIF_F_RXALL;
8276         dev->hw_features |= NETIF_F_RXFCS;
8277
8278         tp->hw_start = cfg->hw_start;
8279         tp->event_slow = cfg->event_slow;
8280
8281         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8282                 ~(RxBOVF | RxFOVF) : ~0;
8283
8284         init_timer(&tp->timer);
8285         tp->timer.data = (unsigned long) dev;
8286         tp->timer.function = rtl8169_phy_timer;
8287
8288         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8289
8290         rc = register_netdev(dev);
8291         if (rc < 0)
8292                 goto err_out_msi_4;
8293
8294         pci_set_drvdata(pdev, dev);
8295
8296         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8297                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8298                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8299         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8300                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8301                            "tx checksumming: %s]\n",
8302                            rtl_chip_infos[chipset].jumbo_max,
8303                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8304         }
8305
8306         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8307              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8308              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8309              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8310              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8311              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8312             r8168_check_dash(tp)) {
8313                 rtl8168_driver_start(tp);
8314         }
8315
8316         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8317
8318         if (pci_dev_run_wake(pdev))
8319                 pm_runtime_put_noidle(&pdev->dev);
8320
8321         netif_carrier_off(dev);
8322
8323 out:
8324         return rc;
8325
8326 err_out_msi_4:
8327         netif_napi_del(&tp->napi);
8328         rtl_disable_msi(pdev, tp);
8329         iounmap(ioaddr);
8330 err_out_free_res_3:
8331         pci_release_regions(pdev);
8332 err_out_mwi_2:
8333         pci_clear_mwi(pdev);
8334         pci_disable_device(pdev);
8335 err_out_free_dev_1:
8336         free_netdev(dev);
8337         goto out;
8338 }
8339
8340 static struct pci_driver rtl8169_pci_driver = {
8341         .name           = MODULENAME,
8342         .id_table       = rtl8169_pci_tbl,
8343         .probe          = rtl_init_one,
8344         .remove         = rtl_remove_one,
8345         .shutdown       = rtl_shutdown,
8346         .driver.pm      = RTL8169_PM_OPS,
8347 };
8348
8349 module_pci_driver(rtl8169_pci_driver);