drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 332         { PCI_VENDOR_ID_DLINK,                  0x4300,
 333                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 334         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 338         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 339                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 340         { 0x0001,                               0x8168,
 341                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 342         {0,},
 343 };
 344
 345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 346
 347 static int rx_buf_sz = 16383;
 348 static int use_dac;
 349 static struct {
 350         u32 msg_enable;
 351 } debug = { -1 };
 352
 353 enum rtl_registers {
 354         MAC0            = 0,    /* Ethernet hardware address. */
 355         MAC4            = 4,
 356         MAR0            = 8,    /* Multicast filter. */
 357         CounterAddrLow          = 0x10,
 358         CounterAddrHigh         = 0x14,
 359         TxDescStartAddrLow      = 0x20,
 360         TxDescStartAddrHigh     = 0x24,
 361         TxHDescStartAddrLow     = 0x28,
 362         TxHDescStartAddrHigh    = 0x2c,
 363         FLASH           = 0x30,
 364         ERSR            = 0x36,
 365         ChipCmd         = 0x37,
 366         TxPoll          = 0x38,
 367         IntrMask        = 0x3c,
 368         IntrStatus      = 0x3e,
 369
 370         TxConfig        = 0x40,
 371 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 372 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 373
 374         RxConfig        = 0x44,
 375 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 376 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 377 #define RXCFG_FIFO_SHIFT                13
 378                                         /* No threshold before first PCI xfer */
 379 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 380 #define RX_EARLY_OFF                    (1 << 11)
 381 #define RXCFG_DMA_SHIFT                 8
 382                                         /* Unlimited maximum PCI burst. */
 383 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 384
 385         RxMissed        = 0x4c,
 386         Cfg9346         = 0x50,
 387         Config0         = 0x51,
 388         Config1         = 0x52,
 389         Config2         = 0x53,
 390 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 391
 392         Config3         = 0x54,
 393         Config4         = 0x55,
 394         Config5         = 0x56,
 395         MultiIntr       = 0x5c,
 396         PHYAR           = 0x60,
 397         PHYstatus       = 0x6c,
 398         RxMaxSize       = 0xda,
 399         CPlusCmd        = 0xe0,
 400         IntrMitigate    = 0xe2,
 401         RxDescAddrLow   = 0xe4,
 402         RxDescAddrHigh  = 0xe8,
 403         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 404
 405 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 406
 407         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 408
 409 #define TxPacketMax     (8064 >> 7)
 410 #define EarlySize       0x27
 411
 412         FuncEvent       = 0xf0,
 413         FuncEventMask   = 0xf4,
 414         FuncPresetState = 0xf8,
 415         IBCR0           = 0xf8,
 416         IBCR2           = 0xf9,
 417         IBIMR0          = 0xfa,
 418         IBISR0          = 0xfb,
 419         FuncForceEvent  = 0xfc,
 420 };
 421
 422 enum rtl8110_registers {
 423         TBICSR                  = 0x64,
 424         TBI_ANAR                = 0x68,
 425         TBI_LPAR                = 0x6a,
 426 };
 427
 428 enum rtl8168_8101_registers {
 429         CSIDR                   = 0x64,
 430         CSIAR                   = 0x68,
 431 #define CSIAR_FLAG                      0x80000000
 432 #define CSIAR_WRITE_CMD                 0x80000000
 433 #define CSIAR_BYTE_ENABLE               0x0f
 434 #define CSIAR_BYTE_ENABLE_SHIFT         12
 435 #define CSIAR_ADDR_MASK                 0x0fff
 436 #define CSIAR_FUNC_CARD                 0x00000000
 437 #define CSIAR_FUNC_SDIO                 0x00010000
 438 #define CSIAR_FUNC_NIC                  0x00020000
 439 #define CSIAR_FUNC_NIC2                 0x00010000
 440         PMCH                    = 0x6f,
 441         EPHYAR                  = 0x80,
 442 #define EPHYAR_FLAG                     0x80000000
 443 #define EPHYAR_WRITE_CMD                0x80000000
 444 #define EPHYAR_REG_MASK                 0x1f
 445 #define EPHYAR_REG_SHIFT                16
 446 #define EPHYAR_DATA_MASK                0xffff
 447         DLLPR                   = 0xd0,
 448 #define PFM_EN                          (1 << 6)
 449 #define TX_10M_PS_EN                    (1 << 7)
 450         DBG_REG                 = 0xd1,
 451 #define FIX_NAK_1                       (1 << 4)
 452 #define FIX_NAK_2                       (1 << 3)
 453         TWSI                    = 0xd2,
 454         MCU                     = 0xd3,
 455 #define NOW_IS_OOB                      (1 << 7)
 456 #define TX_EMPTY                        (1 << 5)
 457 #define RX_EMPTY                        (1 << 4)
 458 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 459 #define EN_NDP                          (1 << 3)
 460 #define EN_OOB_RESET                    (1 << 2)
 461 #define LINK_LIST_RDY                   (1 << 1)
 462         EFUSEAR                 = 0xdc,
 463 #define EFUSEAR_FLAG                    0x80000000
 464 #define EFUSEAR_WRITE_CMD               0x80000000
 465 #define EFUSEAR_READ_CMD                0x00000000
 466 #define EFUSEAR_REG_MASK                0x03ff
 467 #define EFUSEAR_REG_SHIFT               8
 468 #define EFUSEAR_DATA_MASK               0xff
 469         MISC_1                  = 0xf2,
 470 #define PFM_D3COLD_EN                   (1 << 6)
 471 };
 472
 473 enum rtl8168_registers {
 474         LED_FREQ                = 0x1a,
 475         EEE_LED                 = 0x1b,
 476         ERIDR                   = 0x70,
 477         ERIAR                   = 0x74,
 478 #define ERIAR_FLAG                      0x80000000
 479 #define ERIAR_WRITE_CMD                 0x80000000
 480 #define ERIAR_READ_CMD                  0x00000000
 481 #define ERIAR_ADDR_BYTE_ALIGN           4
 482 #define ERIAR_TYPE_SHIFT                16
 483 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 484 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 485 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 486 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 487 #define ERIAR_MASK_SHIFT                12
 488 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 489 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 490 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 491 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 492 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 493         EPHY_RXER_NUM           = 0x7c,
 494         OCPDR                   = 0xb0, /* OCP GPHY access */
 495 #define OCPDR_WRITE_CMD                 0x80000000
 496 #define OCPDR_READ_CMD                  0x00000000
 497 #define OCPDR_REG_MASK                  0x7f
 498 #define OCPDR_GPHY_REG_SHIFT            16
 499 #define OCPDR_DATA_MASK                 0xffff
 500         OCPAR                   = 0xb4,
 501 #define OCPAR_FLAG                      0x80000000
 502 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 503 #define OCPAR_GPHY_READ_CMD             0x0000f060
 504         GPHY_OCP                = 0xb8,
 505         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 506         MISC                    = 0xf0, /* 8168e only. */
 507 #define TXPLA_RST                       (1 << 29)
 508 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 509 #define PWM_EN                          (1 << 22)
 510 #define RXDV_GATED_EN                   (1 << 19)
 511 #define EARLY_TALLY_EN                  (1 << 16)
 512 };
 513
 514 enum rtl_register_content {
 515         /* InterruptStatusBits */
 516         SYSErr          = 0x8000,
 517         PCSTimeout      = 0x4000,
 518         SWInt           = 0x0100,
 519         TxDescUnavail   = 0x0080,
 520         RxFIFOOver      = 0x0040,
 521         LinkChg         = 0x0020,
 522         RxOverflow      = 0x0010,
 523         TxErr           = 0x0008,
 524         TxOK            = 0x0004,
 525         RxErr           = 0x0002,
 526         RxOK            = 0x0001,
 527
 528         /* RxStatusDesc */
 529         RxBOVF  = (1 << 24),
 530         RxFOVF  = (1 << 23),
 531         RxRWT   = (1 << 22),
 532         RxRES   = (1 << 21),
 533         RxRUNT  = (1 << 20),
 534         RxCRC   = (1 << 19),
 535
 536         /* ChipCmdBits */
 537         StopReq         = 0x80,
 538         CmdReset        = 0x10,
 539         CmdRxEnb        = 0x08,
 540         CmdTxEnb        = 0x04,
 541         RxBufEmpty      = 0x01,
 542
 543         /* TXPoll register p.5 */
 544         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 545         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 546         FSWInt          = 0x01,         /* Forced software interrupt */
 547
 548         /* Cfg9346Bits */
 549         Cfg9346_Lock    = 0x00,
 550         Cfg9346_Unlock  = 0xc0,
 551
 552         /* rx_mode_bits */
 553         AcceptErr       = 0x20,
 554         AcceptRunt      = 0x10,
 555         AcceptBroadcast = 0x08,
 556         AcceptMulticast = 0x04,
 557         AcceptMyPhys    = 0x02,
 558         AcceptAllPhys   = 0x01,
 559 #define RX_CONFIG_ACCEPT_MASK           0x3f
 560
 561         /* TxConfigBits */
 562         TxInterFrameGapShift = 24,
 563         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 564
 565         /* Config1 register p.24 */
 566         LEDS1           = (1 << 7),
 567         LEDS0           = (1 << 6),
 568         Speed_down      = (1 << 4),
 569         MEMMAP          = (1 << 3),
 570         IOMAP           = (1 << 2),
 571         VPD             = (1 << 1),
 572         PMEnable        = (1 << 0),     /* Power Management Enable */
 573
 574         /* Config2 register p. 25 */
 575         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 576         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 577         PCI_Clock_66MHz = 0x01,
 578         PCI_Clock_33MHz = 0x00,
 579
 580         /* Config3 register p.25 */
 581         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 582         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 583         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 584         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 585         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 586
 587         /* Config4 register */
 588         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 589
 590         /* Config5 register p.27 */
 591         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 592         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 593         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 594         Spi_en          = (1 << 3),
 595         LanWake         = (1 << 1),     /* LanWake enable/disable */
 596         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 597         ASPM_en         = (1 << 0),     /* ASPM enable */
 598
 599         /* TBICSR p.28 */
 600         TBIReset        = 0x80000000,
 601         TBILoopback     = 0x40000000,
 602         TBINwEnable     = 0x20000000,
 603         TBINwRestart    = 0x10000000,
 604         TBILinkOk       = 0x02000000,
 605         TBINwComplete   = 0x01000000,
 606
 607         /* CPlusCmd p.31 */
 608         EnableBist      = (1 << 15),    // 8168 8101
 609         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 610         Normal_mode     = (1 << 13),    // unused
 611         Force_half_dup  = (1 << 12),    // 8168 8101
 612         Force_rxflow_en = (1 << 11),    // 8168 8101
 613         Force_txflow_en = (1 << 10),    // 8168 8101
 614         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 615         ASF             = (1 << 8),     // 8168 8101
 616         PktCntrDisable  = (1 << 7),     // 8168 8101
 617         Mac_dbgo_sel    = 0x001c,       // 8168
 618         RxVlan          = (1 << 6),
 619         RxChkSum        = (1 << 5),
 620         PCIDAC          = (1 << 4),
 621         PCIMulRW        = (1 << 3),
 622         INTT_0          = 0x0000,       // 8168
 623         INTT_1          = 0x0001,       // 8168
 624         INTT_2          = 0x0002,       // 8168
 625         INTT_3          = 0x0003,       // 8168
 626
 627         /* rtl8169_PHYstatus */
 628         TBI_Enable      = 0x80,
 629         TxFlowCtrl      = 0x40,
 630         RxFlowCtrl      = 0x20,
 631         _1000bpsF       = 0x10,
 632         _100bps         = 0x08,
 633         _10bps          = 0x04,
 634         LinkStatus      = 0x02,
 635         FullDup         = 0x01,
 636
 637         /* _TBICSRBit */
 638         TBILinkOK       = 0x02000000,
 639
 640         /* ResetCounterCommand */
 641         CounterReset    = 0x1,
 642
 643         /* DumpCounterCommand */
 644         CounterDump     = 0x8,
 645
 646         /* magic enable v2 */
 647         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 648 };
 649
 650 enum rtl_desc_bit {
 651         /* First doubleword. */
 652         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 653         RingEnd         = (1 << 30), /* End of descriptor ring */
 654         FirstFrag       = (1 << 29), /* First segment of a packet */
 655         LastFrag        = (1 << 28), /* Final segment of a packet */
 656 };
 657
 658 /* Generic case. */
 659 enum rtl_tx_desc_bit {
 660         /* First doubleword. */
 661         TD_LSO          = (1 << 27),            /* Large Send Offload */
 662 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 663
 664         /* Second doubleword. */
 665         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 666 };
 667
 668 /* 8169, 8168b and 810x except 8102e. */
 669 enum rtl_tx_desc_bit_0 {
 670         /* First doubleword. */
 671 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 672         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 673         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 674         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 675 };
 676
 677 /* 8102e, 8168c and beyond. */
 678 enum rtl_tx_desc_bit_1 {
 679         /* First doubleword. */
 680         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 681         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 682 #define GTTCPHO_SHIFT                   18
 683 #define GTTCPHO_MAX                     0x7fU
 684
 685         /* Second doubleword. */
 686 #define TCPHO_SHIFT                     18
 687 #define TCPHO_MAX                       0x3ffU
 688 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 689         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 690         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 691         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 692         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 693 };
 694
 695 enum rtl_rx_desc_bit {
 696         /* Rx private */
 697         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 698         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 699
 700 #define RxProtoUDP      (PID1)
 701 #define RxProtoTCP      (PID0)
 702 #define RxProtoIP       (PID1 | PID0)
 703 #define RxProtoMask     RxProtoIP
 704
 705         IPFail          = (1 << 16), /* IP checksum failed */
 706         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 707         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 708         RxVlanTag       = (1 << 16), /* VLAN tag available */
 709 };
 710
 711 #define RsvdMask        0x3fffc000
 712
 713 struct TxDesc {
 714         __le32 opts1;
 715         __le32 opts2;
 716         __le64 addr;
 717 };
 718
 719 struct RxDesc {
 720         __le32 opts1;
 721         __le32 opts2;
 722         __le64 addr;
 723 };
 724
 725 struct ring_info {
 726         struct sk_buff  *skb;
 727         u32             len;
 728         u8              __pad[sizeof(void *) - sizeof(u32)];
 729 };
 730
 731 enum features {
 732         RTL_FEATURE_WOL         = (1 << 0),
 733         RTL_FEATURE_MSI         = (1 << 1),
 734         RTL_FEATURE_GMII        = (1 << 2),
 735 };
 736
 737 struct rtl8169_counters {
 738         __le64  tx_packets;
 739         __le64  rx_packets;
 740         __le64  tx_errors;
 741         __le32  rx_errors;
 742         __le16  rx_missed;
 743         __le16  align_errors;
 744         __le32  tx_one_collision;
 745         __le32  tx_multi_collision;
 746         __le64  rx_unicast;
 747         __le64  rx_broadcast;
 748         __le32  rx_multicast;
 749         __le16  tx_aborted;
 750         __le16  tx_underun;
 751 };
 752
 753 struct rtl8169_tc_offsets {
 754         bool    inited;
 755         __le64  tx_errors;
 756         __le32  tx_multi_collision;
 757         __le16  tx_aborted;
 758 };
 759
 760 enum rtl_flag {
 761         RTL_FLAG_TASK_ENABLED,
 762         RTL_FLAG_TASK_SLOW_PENDING,
 763         RTL_FLAG_TASK_RESET_PENDING,
 764         RTL_FLAG_TASK_PHY_PENDING,
 765         RTL_FLAG_MAX
 766 };
 767
 768 struct rtl8169_stats {
 769         u64                     packets;
 770         u64                     bytes;
 771         struct u64_stats_sync   syncp;
 772 };
 773
 774 struct rtl8169_private {
 775         void __iomem *mmio_addr;        /* memory map physical address */
 776         struct pci_dev *pci_dev;
 777         struct net_device *dev;
 778         struct napi_struct napi;
 779         u32 msg_enable;
 780         u16 txd_version;
 781         u16 mac_version;
 782         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 783         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 784         u32 dirty_tx;
 785         struct rtl8169_stats rx_stats;
 786         struct rtl8169_stats tx_stats;
 787         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 788         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 789         dma_addr_t TxPhyAddr;
 790         dma_addr_t RxPhyAddr;
 791         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 792         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 793         struct timer_list timer;
 794         u16 cp_cmd;
 795
 796         u16 event_slow;
 797
 798         struct mdio_ops {
 799                 void (*write)(struct rtl8169_private *, int, int);
 800                 int (*read)(struct rtl8169_private *, int);
 801         } mdio_ops;
 802
 803         struct pll_power_ops {
 804                 void (*down)(struct rtl8169_private *);
 805                 void (*up)(struct rtl8169_private *);
 806         } pll_power_ops;
 807
 808         struct jumbo_ops {
 809                 void (*enable)(struct rtl8169_private *);
 810                 void (*disable)(struct rtl8169_private *);
 811         } jumbo_ops;
 812
 813         struct csi_ops {
 814                 void (*write)(struct rtl8169_private *, int, int);
 815                 u32 (*read)(struct rtl8169_private *, int);
 816         } csi_ops;
 817
 818         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 819         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 820         void (*phy_reset_enable)(struct rtl8169_private *tp);
 821         void (*hw_start)(struct net_device *);
 822         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 823         unsigned int (*link_ok)(void __iomem *);
 824         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 825         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 826
 827         struct {
 828                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 829                 struct mutex mutex;
 830                 struct work_struct work;
 831         } wk;
 832
 833         unsigned features;
 834
 835         struct mii_if_info mii;
 836         struct rtl8169_counters counters;
 837         struct rtl8169_tc_offsets tc_offset;
 838         u32 saved_wolopts;
 839         u32 opts1_mask;
 840
 841         struct rtl_fw {
 842                 const struct firmware *fw;
 843
 844 #define RTL_VER_SIZE            32
 845
 846                 char version[RTL_VER_SIZE];
 847
 848                 struct rtl_fw_phy_action {
 849                         __le32 *code;
 850                         size_t size;
 851                 } phy_action;
 852         } *rtl_fw;
 853 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 854
 855         u32 ocp_base;
 856 };
 857
 858 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 859 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 860 module_param(use_dac, int, 0);
 861 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 862 module_param_named(debug, debug.msg_enable, int, 0);
 863 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 864 MODULE_LICENSE("GPL");
 865 MODULE_VERSION(RTL8169_VERSION);
 866 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 867 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 868 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 869 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 870 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 871 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 872 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 873 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 874 MODULE_FIRMWARE(FIRMWARE_8402_1);
 875 MODULE_FIRMWARE(FIRMWARE_8411_1);
 876 MODULE_FIRMWARE(FIRMWARE_8411_2);
 877 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 878 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 879 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 880 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 881 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 882 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 883 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 884 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 885
 886 static void rtl_lock_work(struct rtl8169_private *tp)
 887 {
 888         mutex_lock(&tp->wk.mutex);
 889 }
 890
 891 static void rtl_unlock_work(struct rtl8169_private *tp)
 892 {
 893         mutex_unlock(&tp->wk.mutex);
 894 }
 895
 896 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 897 {
 898         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 899                                            PCI_EXP_DEVCTL_READRQ, force);
 900 }
 901
 902 struct rtl_cond {
 903         bool (*check)(struct rtl8169_private *);
 904         const char *msg;
 905 };
 906
 907 static void rtl_udelay(unsigned int d)
 908 {
 909         udelay(d);
 910 }
 911
 912 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 913                           void (*delay)(unsigned int), unsigned int d, int n,
 914                           bool high)
 915 {
 916         int i;
 917
 918         for (i = 0; i < n; i++) {
 919                 delay(d);
 920                 if (c->check(tp) == high)
 921                         return true;
 922         }
 923         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 924                   c->msg, !high, n, d);
 925         return false;
 926 }
 927
 928 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 929                                       const struct rtl_cond *c,
 930                                       unsigned int d, int n)
 931 {
 932         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 933 }
 934
 935 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 936                                      const struct rtl_cond *c,
 937                                      unsigned int d, int n)
 938 {
 939         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 940 }
 941
 942 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 943                                       const struct rtl_cond *c,
 944                                       unsigned int d, int n)
 945 {
 946         return rtl_loop_wait(tp, c, msleep, d, n, true);
 947 }
 948
 949 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 950                                      const struct rtl_cond *c,
 951                                      unsigned int d, int n)
 952 {
 953         return rtl_loop_wait(tp, c, msleep, d, n, false);
 954 }
 955
 956 #define DECLARE_RTL_COND(name)                          \
 957 static bool name ## _check(struct rtl8169_private *);   \
 958                                                         \
 959 static const struct rtl_cond name = {                   \
 960         .check  = name ## _check,                       \
 961         .msg    = #name                                 \
 962 };                                                      \
 963                                                         \
 964 static bool name ## _check(struct rtl8169_private *tp)
 965
 966 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 967 {
 968         if (reg & 0xffff0001) {
 969                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 970                 return true;
 971         }
 972         return false;
 973 }
 974
 975 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 976 {
 977         void __iomem *ioaddr = tp->mmio_addr;
 978
 979         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 980 }
 981
 982 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 983 {
 984         void __iomem *ioaddr = tp->mmio_addr;
 985
 986         if (rtl_ocp_reg_failure(tp, reg))
 987                 return;
 988
 989         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 990
 991         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 992 }
 993
 994 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 995 {
 996         void __iomem *ioaddr = tp->mmio_addr;
 997
 998         if (rtl_ocp_reg_failure(tp, reg))
 999                 return 0;
1000
1001         RTL_W32(GPHY_OCP, reg << 15);
1002
1003         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1004                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1005 }
1006
1007 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1008 {
1009         void __iomem *ioaddr = tp->mmio_addr;
1010
1011         if (rtl_ocp_reg_failure(tp, reg))
1012                 return;
1013
1014         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1015 }
1016
1017 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1018 {
1019         void __iomem *ioaddr = tp->mmio_addr;
1020
1021         if (rtl_ocp_reg_failure(tp, reg))
1022                 return 0;
1023
1024         RTL_W32(OCPDR, reg << 15);
1025
1026         return RTL_R32(OCPDR);
1027 }
1028
1029 #define OCP_STD_PHY_BASE        0xa400
1030
1031 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1032 {
1033         if (reg == 0x1f) {
1034                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1035                 return;
1036         }
1037
1038         if (tp->ocp_base != OCP_STD_PHY_BASE)
1039                 reg -= 0x10;
1040
1041         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1042 }
1043
1044 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1045 {
1046         if (tp->ocp_base != OCP_STD_PHY_BASE)
1047                 reg -= 0x10;
1048
1049         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1050 }
1051
1052 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1053 {
1054         if (reg == 0x1f) {
1055                 tp->ocp_base = value << 4;
1056                 return;
1057         }
1058
1059         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1060 }
1061
1062 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1063 {
1064         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1065 }
1066
1067 DECLARE_RTL_COND(rtl_phyar_cond)
1068 {
1069         void __iomem *ioaddr = tp->mmio_addr;
1070
1071         return RTL_R32(PHYAR) & 0x80000000;
1072 }
1073
1074 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1075 {
1076         void __iomem *ioaddr = tp->mmio_addr;
1077
1078         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1079
1080         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1081         /*
1082          * According to hardware specs a 20us delay is required after write
1083          * complete indication, but before sending next command.
1084          */
1085         udelay(20);
1086 }
1087
1088 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1089 {
1090         void __iomem *ioaddr = tp->mmio_addr;
1091         int value;
1092
1093         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1094
1095         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1096                 RTL_R32(PHYAR) & 0xffff : ~0;
1097
1098         /*
1099          * According to hardware specs a 20us delay is required after read
1100          * complete indication, but before sending next command.
1101          */
1102         udelay(20);
1103
1104         return value;
1105 }
1106
1107 DECLARE_RTL_COND(rtl_ocpar_cond)
1108 {
1109         void __iomem *ioaddr = tp->mmio_addr;
1110
1111         return RTL_R32(OCPAR) & OCPAR_FLAG;
1112 }
1113
1114 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1115 {
1116         void __iomem *ioaddr = tp->mmio_addr;
1117
1118         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1119         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1120         RTL_W32(EPHY_RXER_NUM, 0);
1121
1122         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1123 }
1124
1125 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1126 {
1127         r8168dp_1_mdio_access(tp, reg,
1128                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1129 }
1130
1131 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1132 {
1133         void __iomem *ioaddr = tp->mmio_addr;
1134
1135         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1136
1137         mdelay(1);
1138         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1139         RTL_W32(EPHY_RXER_NUM, 0);
1140
1141         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1142                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1143 }
1144
1145 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1146
1147 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1148 {
1149         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1150 }
1151
1152 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1153 {
1154         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1155 }
1156
1157 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1158 {
1159         void __iomem *ioaddr = tp->mmio_addr;
1160
1161         r8168dp_2_mdio_start(ioaddr);
1162
1163         r8169_mdio_write(tp, reg, value);
1164
1165         r8168dp_2_mdio_stop(ioaddr);
1166 }
1167
1168 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1169 {
1170         void __iomem *ioaddr = tp->mmio_addr;
1171         int value;
1172
1173         r8168dp_2_mdio_start(ioaddr);
1174
1175         value = r8169_mdio_read(tp, reg);
1176
1177         r8168dp_2_mdio_stop(ioaddr);
1178
1179         return value;
1180 }
1181
1182 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1183 {
1184         tp->mdio_ops.write(tp, location, val);
1185 }
1186
1187 static int rtl_readphy(struct rtl8169_private *tp, int location)
1188 {
1189         return tp->mdio_ops.read(tp, location);
1190 }
1191
1192 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1193 {
1194         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1195 }
1196
1197 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1198 {
1199         int val;
1200
1201         val = rtl_readphy(tp, reg_addr);
1202         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1203 }
1204
1205 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1206                            int val)
1207 {
1208         struct rtl8169_private *tp = netdev_priv(dev);
1209
1210         rtl_writephy(tp, location, val);
1211 }
1212
1213 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1214 {
1215         struct rtl8169_private *tp = netdev_priv(dev);
1216
1217         return rtl_readphy(tp, location);
1218 }
1219
1220 DECLARE_RTL_COND(rtl_ephyar_cond)
1221 {
1222         void __iomem *ioaddr = tp->mmio_addr;
1223
1224         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1225 }
1226
1227 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1228 {
1229         void __iomem *ioaddr = tp->mmio_addr;
1230
1231         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1232                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1233
1234         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1235
1236         udelay(10);
1237 }
1238
1239 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1240 {
1241         void __iomem *ioaddr = tp->mmio_addr;
1242
1243         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1244
1245         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1246                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1247 }
1248
1249 DECLARE_RTL_COND(rtl_eriar_cond)
1250 {
1251         void __iomem *ioaddr = tp->mmio_addr;
1252
1253         return RTL_R32(ERIAR) & ERIAR_FLAG;
1254 }
1255
1256 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1257                           u32 val, int type)
1258 {
1259         void __iomem *ioaddr = tp->mmio_addr;
1260
1261         BUG_ON((addr & 3) || (mask == 0));
1262         RTL_W32(ERIDR, val);
1263         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1264
1265         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1266 }
1267
1268 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1269 {
1270         void __iomem *ioaddr = tp->mmio_addr;
1271
1272         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1273
1274         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1275                 RTL_R32(ERIDR) : ~0;
1276 }
1277
1278 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1279                          u32 m, int type)
1280 {
1281         u32 val;
1282
1283         val = rtl_eri_read(tp, addr, type);
1284         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1285 }
1286
1287 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1288 {
1289         void __iomem *ioaddr = tp->mmio_addr;
1290
1291         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1292         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1293                 RTL_R32(OCPDR) : ~0;
1294 }
1295
1296 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1297 {
1298         return rtl_eri_read(tp, reg, ERIAR_OOB);
1299 }
1300
1301 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1302 {
1303         switch (tp->mac_version) {
1304         case RTL_GIGA_MAC_VER_27:
1305         case RTL_GIGA_MAC_VER_28:
1306         case RTL_GIGA_MAC_VER_31:
1307                 return r8168dp_ocp_read(tp, mask, reg);
1308         case RTL_GIGA_MAC_VER_49:
1309         case RTL_GIGA_MAC_VER_50:
1310         case RTL_GIGA_MAC_VER_51:
1311                 return r8168ep_ocp_read(tp, mask, reg);
1312         default:
1313                 BUG();
1314                 return ~0;
1315         }
1316 }
1317
1318 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1319                               u32 data)
1320 {
1321         void __iomem *ioaddr = tp->mmio_addr;
1322
1323         RTL_W32(OCPDR, data);
1324         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1325         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1326 }
1327
1328 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1329                               u32 data)
1330 {
1331         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1332                       data, ERIAR_OOB);
1333 }
1334
1335 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1336 {
1337         switch (tp->mac_version) {
1338         case RTL_GIGA_MAC_VER_27:
1339         case RTL_GIGA_MAC_VER_28:
1340         case RTL_GIGA_MAC_VER_31:
1341                 r8168dp_ocp_write(tp, mask, reg, data);
1342                 break;
1343         case RTL_GIGA_MAC_VER_49:
1344         case RTL_GIGA_MAC_VER_50:
1345         case RTL_GIGA_MAC_VER_51:
1346                 r8168ep_ocp_write(tp, mask, reg, data);
1347                 break;
1348         default:
1349                 BUG();
1350                 break;
1351         }
1352 }
1353
1354 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1355 {
1356         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1357
1358         ocp_write(tp, 0x1, 0x30, 0x00000001);
1359 }
1360
1361 #define OOB_CMD_RESET           0x00
1362 #define OOB_CMD_DRIVER_START    0x05
1363 #define OOB_CMD_DRIVER_STOP     0x06
1364
1365 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1366 {
1367         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1368 }
1369
1370 DECLARE_RTL_COND(rtl_ocp_read_cond)
1371 {
1372         u16 reg;
1373
1374         reg = rtl8168_get_ocp_reg(tp);
1375
1376         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1377 }
1378
1379 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1380 {
1381         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1382 }
1383
1384 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1385 {
1386         void __iomem *ioaddr = tp->mmio_addr;
1387
1388         return RTL_R8(IBISR0) & 0x02;
1389 }
1390
1391 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1392 {
1393         void __iomem *ioaddr = tp->mmio_addr;
1394
1395         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1396         rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1397         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1398         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1399 }
1400
1401 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1402 {
1403         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1404         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1405 }
1406
1407 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1408 {
1409         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1410         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1411         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1412 }
1413
1414 static void rtl8168_driver_start(struct rtl8169_private *tp)
1415 {
1416         switch (tp->mac_version) {
1417         case RTL_GIGA_MAC_VER_27:
1418         case RTL_GIGA_MAC_VER_28:
1419         case RTL_GIGA_MAC_VER_31:
1420                 rtl8168dp_driver_start(tp);
1421                 break;
1422         case RTL_GIGA_MAC_VER_49:
1423         case RTL_GIGA_MAC_VER_50:
1424         case RTL_GIGA_MAC_VER_51:
1425                 rtl8168ep_driver_start(tp);
1426                 break;
1427         default:
1428                 BUG();
1429                 break;
1430         }
1431 }
1432
1433 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1434 {
1435         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1436         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1437 }
1438
1439 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1440 {
1441         rtl8168ep_stop_cmac(tp);
1442         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1443         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1444         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1445 }
1446
1447 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1448 {
1449         switch (tp->mac_version) {
1450         case RTL_GIGA_MAC_VER_27:
1451         case RTL_GIGA_MAC_VER_28:
1452         case RTL_GIGA_MAC_VER_31:
1453                 rtl8168dp_driver_stop(tp);
1454                 break;
1455         case RTL_GIGA_MAC_VER_49:
1456         case RTL_GIGA_MAC_VER_50:
1457         case RTL_GIGA_MAC_VER_51:
1458                 rtl8168ep_driver_stop(tp);
1459                 break;
1460         default:
1461                 BUG();
1462                 break;
1463         }
1464 }
1465
1466 static int r8168dp_check_dash(struct rtl8169_private *tp)
1467 {
1468         u16 reg = rtl8168_get_ocp_reg(tp);
1469
1470         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1471 }
1472
1473 static int r8168ep_check_dash(struct rtl8169_private *tp)
1474 {
1475         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1476 }
1477
1478 static int r8168_check_dash(struct rtl8169_private *tp)
1479 {
1480         switch (tp->mac_version) {
1481         case RTL_GIGA_MAC_VER_27:
1482         case RTL_GIGA_MAC_VER_28:
1483         case RTL_GIGA_MAC_VER_31:
1484                 return r8168dp_check_dash(tp);
1485         case RTL_GIGA_MAC_VER_49:
1486         case RTL_GIGA_MAC_VER_50:
1487         case RTL_GIGA_MAC_VER_51:
1488                 return r8168ep_check_dash(tp);
1489         default:
1490                 return 0;
1491         }
1492 }
1493
1494 struct exgmac_reg {
1495         u16 addr;
1496         u16 mask;
1497         u32 val;
1498 };
1499
1500 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1501                                    const struct exgmac_reg *r, int len)
1502 {
1503         while (len-- > 0) {
1504                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1505                 r++;
1506         }
1507 }
1508
1509 DECLARE_RTL_COND(rtl_efusear_cond)
1510 {
1511         void __iomem *ioaddr = tp->mmio_addr;
1512
1513         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1514 }
1515
1516 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1517 {
1518         void __iomem *ioaddr = tp->mmio_addr;
1519
1520         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1521
1522         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1523                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1524 }
1525
1526 static u16 rtl_get_events(struct rtl8169_private *tp)
1527 {
1528         void __iomem *ioaddr = tp->mmio_addr;
1529
1530         return RTL_R16(IntrStatus);
1531 }
1532
1533 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1534 {
1535         void __iomem *ioaddr = tp->mmio_addr;
1536
1537         RTL_W16(IntrStatus, bits);
1538         mmiowb();
1539 }
1540
1541 static void rtl_irq_disable(struct rtl8169_private *tp)
1542 {
1543         void __iomem *ioaddr = tp->mmio_addr;
1544
1545         RTL_W16(IntrMask, 0);
1546         mmiowb();
1547 }
1548
1549 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1550 {
1551         void __iomem *ioaddr = tp->mmio_addr;
1552
1553         RTL_W16(IntrMask, bits);
1554 }
1555
1556 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1557 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1558 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1559
1560 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1561 {
1562         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1563 }
1564
1565 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1566 {
1567         void __iomem *ioaddr = tp->mmio_addr;
1568
1569         rtl_irq_disable(tp);
1570         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1571         RTL_R8(ChipCmd);
1572 }
1573
1574 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1575 {
1576         void __iomem *ioaddr = tp->mmio_addr;
1577
1578         return RTL_R32(TBICSR) & TBIReset;
1579 }
1580
1581 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1582 {
1583         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1584 }
1585
1586 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1587 {
1588         return RTL_R32(TBICSR) & TBILinkOk;
1589 }
1590
1591 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1592 {
1593         return RTL_R8(PHYstatus) & LinkStatus;
1594 }
1595
1596 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1597 {
1598         void __iomem *ioaddr = tp->mmio_addr;
1599
1600         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1601 }
1602
1603 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1604 {
1605         unsigned int val;
1606
1607         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1608         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1609 }
1610
1611 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1612 {
1613         void __iomem *ioaddr = tp->mmio_addr;
1614         struct net_device *dev = tp->dev;
1615
1616         if (!netif_running(dev))
1617                 return;
1618
1619         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1620             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1621                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1622                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1623                                       ERIAR_EXGMAC);
1624                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1625                                       ERIAR_EXGMAC);
1626                 } else if (RTL_R8(PHYstatus) & _100bps) {
1627                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1628                                       ERIAR_EXGMAC);
1629                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1630                                       ERIAR_EXGMAC);
1631                 } else {
1632                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1633                                       ERIAR_EXGMAC);
1634                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1635                                       ERIAR_EXGMAC);
1636                 }
1637                 /* Reset packet filter */
1638                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1639                              ERIAR_EXGMAC);
1640                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1641                              ERIAR_EXGMAC);
1642         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1643                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1644                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1645                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1646                                       ERIAR_EXGMAC);
1647                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1648                                       ERIAR_EXGMAC);
1649                 } else {
1650                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1651                                       ERIAR_EXGMAC);
1652                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1653                                       ERIAR_EXGMAC);
1654                 }
1655         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1656                 if (RTL_R8(PHYstatus) & _10bps) {
1657                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1658                                       ERIAR_EXGMAC);
1659                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1660                                       ERIAR_EXGMAC);
1661                 } else {
1662                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1663                                       ERIAR_EXGMAC);
1664                 }
1665         }
1666 }
1667
1668 static void __rtl8169_check_link_status(struct net_device *dev,
1669                                         struct rtl8169_private *tp,
1670                                         void __iomem *ioaddr, bool pm)
1671 {
1672         if (tp->link_ok(ioaddr)) {
1673                 rtl_link_chg_patch(tp);
1674                 /* This is to cancel a scheduled suspend if there's one. */
1675                 if (pm)
1676                         pm_request_resume(&tp->pci_dev->dev);
1677                 netif_carrier_on(dev);
1678                 if (net_ratelimit())
1679                         netif_info(tp, ifup, dev, "link up\n");
1680         } else {
1681                 netif_carrier_off(dev);
1682                 netif_info(tp, ifdown, dev, "link down\n");
1683                 if (pm)
1684                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1685         }
1686 }
1687
1688 static void rtl8169_check_link_status(struct net_device *dev,
1689                                       struct rtl8169_private *tp,
1690                                       void __iomem *ioaddr)
1691 {
1692         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1693 }
1694
1695 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1696
1697 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1698 {
1699         void __iomem *ioaddr = tp->mmio_addr;
1700         u8 options;
1701         u32 wolopts = 0;
1702
1703         options = RTL_R8(Config1);
1704         if (!(options & PMEnable))
1705                 return 0;
1706
1707         options = RTL_R8(Config3);
1708         if (options & LinkUp)
1709                 wolopts |= WAKE_PHY;
1710         switch (tp->mac_version) {
1711         case RTL_GIGA_MAC_VER_34:
1712         case RTL_GIGA_MAC_VER_35:
1713         case RTL_GIGA_MAC_VER_36:
1714         case RTL_GIGA_MAC_VER_37:
1715         case RTL_GIGA_MAC_VER_38:
1716         case RTL_GIGA_MAC_VER_40:
1717         case RTL_GIGA_MAC_VER_41:
1718         case RTL_GIGA_MAC_VER_42:
1719         case RTL_GIGA_MAC_VER_43:
1720         case RTL_GIGA_MAC_VER_44:
1721         case RTL_GIGA_MAC_VER_45:
1722         case RTL_GIGA_MAC_VER_46:
1723         case RTL_GIGA_MAC_VER_47:
1724         case RTL_GIGA_MAC_VER_48:
1725         case RTL_GIGA_MAC_VER_49:
1726         case RTL_GIGA_MAC_VER_50:
1727         case RTL_GIGA_MAC_VER_51:
1728                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1729                         wolopts |= WAKE_MAGIC;
1730                 break;
1731         default:
1732                 if (options & MagicPacket)
1733                         wolopts |= WAKE_MAGIC;
1734                 break;
1735         }
1736
1737         options = RTL_R8(Config5);
1738         if (options & UWF)
1739                 wolopts |= WAKE_UCAST;
1740         if (options & BWF)
1741                 wolopts |= WAKE_BCAST;
1742         if (options & MWF)
1743                 wolopts |= WAKE_MCAST;
1744
1745         return wolopts;
1746 }
1747
1748 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1749 {
1750         struct rtl8169_private *tp = netdev_priv(dev);
1751
1752         rtl_lock_work(tp);
1753
1754         wol->supported = WAKE_ANY;
1755         wol->wolopts = __rtl8169_get_wol(tp);
1756
1757         rtl_unlock_work(tp);
1758 }
1759
1760 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1761 {
1762         void __iomem *ioaddr = tp->mmio_addr;
1763         unsigned int i, tmp;
1764         static const struct {
1765                 u32 opt;
1766                 u16 reg;
1767                 u8  mask;
1768         } cfg[] = {
1769                 { WAKE_PHY,   Config3, LinkUp },
1770                 { WAKE_UCAST, Config5, UWF },
1771                 { WAKE_BCAST, Config5, BWF },
1772                 { WAKE_MCAST, Config5, MWF },
1773                 { WAKE_ANY,   Config5, LanWake },
1774                 { WAKE_MAGIC, Config3, MagicPacket }
1775         };
1776         u8 options;
1777
1778         RTL_W8(Cfg9346, Cfg9346_Unlock);
1779
1780         switch (tp->mac_version) {
1781         case RTL_GIGA_MAC_VER_34:
1782         case RTL_GIGA_MAC_VER_35:
1783         case RTL_GIGA_MAC_VER_36:
1784         case RTL_GIGA_MAC_VER_37:
1785         case RTL_GIGA_MAC_VER_38:
1786         case RTL_GIGA_MAC_VER_40:
1787         case RTL_GIGA_MAC_VER_41:
1788         case RTL_GIGA_MAC_VER_42:
1789         case RTL_GIGA_MAC_VER_43:
1790         case RTL_GIGA_MAC_VER_44:
1791         case RTL_GIGA_MAC_VER_45:
1792         case RTL_GIGA_MAC_VER_46:
1793         case RTL_GIGA_MAC_VER_47:
1794         case RTL_GIGA_MAC_VER_48:
1795         case RTL_GIGA_MAC_VER_49:
1796         case RTL_GIGA_MAC_VER_50:
1797         case RTL_GIGA_MAC_VER_51:
1798                 tmp = ARRAY_SIZE(cfg) - 1;
1799                 if (wolopts & WAKE_MAGIC)
1800                         rtl_w0w1_eri(tp,
1801                                      0x0dc,
1802                                      ERIAR_MASK_0100,
1803                                      MagicPacket_v2,
1804                                      0x0000,
1805                                      ERIAR_EXGMAC);
1806                 else
1807                         rtl_w0w1_eri(tp,
1808                                      0x0dc,
1809                                      ERIAR_MASK_0100,
1810                                      0x0000,
1811                                      MagicPacket_v2,
1812                                      ERIAR_EXGMAC);
1813                 break;
1814         default:
1815                 tmp = ARRAY_SIZE(cfg);
1816                 break;
1817         }
1818
1819         for (i = 0; i < tmp; i++) {
1820                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1821                 if (wolopts & cfg[i].opt)
1822                         options |= cfg[i].mask;
1823                 RTL_W8(cfg[i].reg, options);
1824         }
1825
1826         switch (tp->mac_version) {
1827         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1828                 options = RTL_R8(Config1) & ~PMEnable;
1829                 if (wolopts)
1830                         options |= PMEnable;
1831                 RTL_W8(Config1, options);
1832                 break;
1833         default:
1834                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1835                 if (wolopts)
1836                         options |= PME_SIGNAL;
1837                 RTL_W8(Config2, options);
1838                 break;
1839         }
1840
1841         RTL_W8(Cfg9346, Cfg9346_Lock);
1842 }
1843
1844 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1845 {
1846         struct rtl8169_private *tp = netdev_priv(dev);
1847
1848         rtl_lock_work(tp);
1849
1850         if (wol->wolopts)
1851                 tp->features |= RTL_FEATURE_WOL;
1852         else
1853                 tp->features &= ~RTL_FEATURE_WOL;
1854         __rtl8169_set_wol(tp, wol->wolopts);
1855
1856         rtl_unlock_work(tp);
1857
1858         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1859
1860         return 0;
1861 }
1862
1863 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1864 {
1865         return rtl_chip_infos[tp->mac_version].fw_name;
1866 }
1867
1868 static void rtl8169_get_drvinfo(struct net_device *dev,
1869                                 struct ethtool_drvinfo *info)
1870 {
1871         struct rtl8169_private *tp = netdev_priv(dev);
1872         struct rtl_fw *rtl_fw = tp->rtl_fw;
1873
1874         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1875         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1876         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1877         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1878         if (!IS_ERR_OR_NULL(rtl_fw))
1879                 strlcpy(info->fw_version, rtl_fw->version,
1880                         sizeof(info->fw_version));
1881 }
1882
1883 static int rtl8169_get_regs_len(struct net_device *dev)
1884 {
1885         return R8169_REGS_SIZE;
1886 }
1887
1888 static int rtl8169_set_speed_tbi(struct net_device *dev,
1889                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1890 {
1891         struct rtl8169_private *tp = netdev_priv(dev);
1892         void __iomem *ioaddr = tp->mmio_addr;
1893         int ret = 0;
1894         u32 reg;
1895
1896         reg = RTL_R32(TBICSR);
1897         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1898             (duplex == DUPLEX_FULL)) {
1899                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1900         } else if (autoneg == AUTONEG_ENABLE)
1901                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1902         else {
1903                 netif_warn(tp, link, dev,
1904                            "incorrect speed setting refused in TBI mode\n");
1905                 ret = -EOPNOTSUPP;
1906         }
1907
1908         return ret;
1909 }
1910
1911 static int rtl8169_set_speed_xmii(struct net_device *dev,
1912                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1913 {
1914         struct rtl8169_private *tp = netdev_priv(dev);
1915         int giga_ctrl, bmcr;
1916         int rc = -EINVAL;
1917
1918         rtl_writephy(tp, 0x1f, 0x0000);
1919
1920         if (autoneg == AUTONEG_ENABLE) {
1921                 int auto_nego;
1922
1923                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1924                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1925                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1926
1927                 if (adv & ADVERTISED_10baseT_Half)
1928                         auto_nego |= ADVERTISE_10HALF;
1929                 if (adv & ADVERTISED_10baseT_Full)
1930                         auto_nego |= ADVERTISE_10FULL;
1931                 if (adv & ADVERTISED_100baseT_Half)
1932                         auto_nego |= ADVERTISE_100HALF;
1933                 if (adv & ADVERTISED_100baseT_Full)
1934                         auto_nego |= ADVERTISE_100FULL;
1935
1936                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1937
1938                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1939                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1940
1941                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1942                 if (tp->mii.supports_gmii) {
1943                         if (adv & ADVERTISED_1000baseT_Half)
1944                                 giga_ctrl |= ADVERTISE_1000HALF;
1945                         if (adv & ADVERTISED_1000baseT_Full)
1946                                 giga_ctrl |= ADVERTISE_1000FULL;
1947                 } else if (adv & (ADVERTISED_1000baseT_Half |
1948                                   ADVERTISED_1000baseT_Full)) {
1949                         netif_info(tp, link, dev,
1950                                    "PHY does not support 1000Mbps\n");
1951                         goto out;
1952                 }
1953
1954                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1955
1956                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1957                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1958         } else {
1959                 giga_ctrl = 0;
1960
1961                 if (speed == SPEED_10)
1962                         bmcr = 0;
1963                 else if (speed == SPEED_100)
1964                         bmcr = BMCR_SPEED100;
1965                 else
1966                         goto out;
1967
1968                 if (duplex == DUPLEX_FULL)
1969                         bmcr |= BMCR_FULLDPLX;
1970         }
1971
1972         rtl_writephy(tp, MII_BMCR, bmcr);
1973
1974         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1975             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1976                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1977                         rtl_writephy(tp, 0x17, 0x2138);
1978                         rtl_writephy(tp, 0x0e, 0x0260);
1979                 } else {
1980                         rtl_writephy(tp, 0x17, 0x2108);
1981                         rtl_writephy(tp, 0x0e, 0x0000);
1982                 }
1983         }
1984
1985         rc = 0;
1986 out:
1987         return rc;
1988 }
1989
1990 static int rtl8169_set_speed(struct net_device *dev,
1991                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1992 {
1993         struct rtl8169_private *tp = netdev_priv(dev);
1994         int ret;
1995
1996         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1997         if (ret < 0)
1998                 goto out;
1999
2000         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2001             (advertising & ADVERTISED_1000baseT_Full)) {
2002                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2003         }
2004 out:
2005         return ret;
2006 }
2007
2008 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2009 {
2010         struct rtl8169_private *tp = netdev_priv(dev);
2011         int ret;
2012
2013         del_timer_sync(&tp->timer);
2014
2015         rtl_lock_work(tp);
2016         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2017                                 cmd->duplex, cmd->advertising);
2018         rtl_unlock_work(tp);
2019
2020         return ret;
2021 }
2022
2023 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2024         netdev_features_t features)
2025 {
2026         struct rtl8169_private *tp = netdev_priv(dev);
2027
2028         if (dev->mtu > TD_MSS_MAX)
2029                 features &= ~NETIF_F_ALL_TSO;
2030
2031         if (dev->mtu > JUMBO_1K &&
2032             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2033                 features &= ~NETIF_F_IP_CSUM;
2034
2035         return features;
2036 }
2037
2038 static void __rtl8169_set_features(struct net_device *dev,
2039                                    netdev_features_t features)
2040 {
2041         struct rtl8169_private *tp = netdev_priv(dev);
2042         void __iomem *ioaddr = tp->mmio_addr;
2043         u32 rx_config;
2044
2045         rx_config = RTL_R32(RxConfig);
2046         if (features & NETIF_F_RXALL)
2047                 rx_config |= (AcceptErr | AcceptRunt);
2048         else
2049                 rx_config &= ~(AcceptErr | AcceptRunt);
2050
2051         RTL_W32(RxConfig, rx_config);
2052
2053         if (features & NETIF_F_RXCSUM)
2054                 tp->cp_cmd |= RxChkSum;
2055         else
2056                 tp->cp_cmd &= ~RxChkSum;
2057
2058         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2059                 tp->cp_cmd |= RxVlan;
2060         else
2061                 tp->cp_cmd &= ~RxVlan;
2062
2063         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2064
2065         RTL_W16(CPlusCmd, tp->cp_cmd);
2066         RTL_R16(CPlusCmd);
2067 }
2068
2069 static int rtl8169_set_features(struct net_device *dev,
2070                                 netdev_features_t features)
2071 {
2072         struct rtl8169_private *tp = netdev_priv(dev);
2073
2074         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2075
2076         rtl_lock_work(tp);
2077         if (features ^ dev->features)
2078                 __rtl8169_set_features(dev, features);
2079         rtl_unlock_work(tp);
2080
2081         return 0;
2082 }
2083
2084
2085 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2086 {
2087         return (skb_vlan_tag_present(skb)) ?
2088                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2089 }
2090
2091 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2092 {
2093         u32 opts2 = le32_to_cpu(desc->opts2);
2094
2095         if (opts2 & RxVlanTag)
2096                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2097 }
2098
2099 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2100 {
2101         struct rtl8169_private *tp = netdev_priv(dev);
2102         void __iomem *ioaddr = tp->mmio_addr;
2103         u32 status;
2104
2105         cmd->supported =
2106                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2107         cmd->port = PORT_FIBRE;
2108         cmd->transceiver = XCVR_INTERNAL;
2109
2110         status = RTL_R32(TBICSR);
2111         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2112         cmd->autoneg = !!(status & TBINwEnable);
2113
2114         ethtool_cmd_speed_set(cmd, SPEED_1000);
2115         cmd->duplex = DUPLEX_FULL; /* Always set */
2116
2117         return 0;
2118 }
2119
2120 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2121 {
2122         struct rtl8169_private *tp = netdev_priv(dev);
2123
2124         return mii_ethtool_gset(&tp->mii, cmd);
2125 }
2126
2127 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2128 {
2129         struct rtl8169_private *tp = netdev_priv(dev);
2130         int rc;
2131
2132         rtl_lock_work(tp);
2133         rc = tp->get_settings(dev, cmd);
2134         rtl_unlock_work(tp);
2135
2136         return rc;
2137 }
2138
2139 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2140                              void *p)
2141 {
2142         struct rtl8169_private *tp = netdev_priv(dev);
2143         u32 __iomem *data = tp->mmio_addr;
2144         u32 *dw = p;
2145         int i;
2146
2147         rtl_lock_work(tp);
2148         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2149                 memcpy_fromio(dw++, data++, 4);
2150         rtl_unlock_work(tp);
2151 }
2152
2153 static u32 rtl8169_get_msglevel(struct net_device *dev)
2154 {
2155         struct rtl8169_private *tp = netdev_priv(dev);
2156
2157         return tp->msg_enable;
2158 }
2159
2160 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2161 {
2162         struct rtl8169_private *tp = netdev_priv(dev);
2163
2164         tp->msg_enable = value;
2165 }
2166
2167 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2168         "tx_packets",
2169         "rx_packets",
2170         "tx_errors",
2171         "rx_errors",
2172         "rx_missed",
2173         "align_errors",
2174         "tx_single_collisions",
2175         "tx_multi_collisions",
2176         "unicast",
2177         "broadcast",
2178         "multicast",
2179         "tx_aborted",
2180         "tx_underrun",
2181 };
2182
2183 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2184 {
2185         switch (sset) {
2186         case ETH_SS_STATS:
2187                 return ARRAY_SIZE(rtl8169_gstrings);
2188         default:
2189                 return -EOPNOTSUPP;
2190         }
2191 }
2192
2193 static struct rtl8169_counters *rtl8169_map_counters(struct net_device *dev,
2194                                                      dma_addr_t *paddr,
2195                                                      u32 counter_cmd)
2196 {
2197         struct rtl8169_private *tp = netdev_priv(dev);
2198         void __iomem *ioaddr = tp->mmio_addr;
2199         struct device *d = &tp->pci_dev->dev;
2200         struct rtl8169_counters *counters;
2201         u32 cmd;
2202
2203         counters = dma_alloc_coherent(d, sizeof(*counters), paddr, GFP_KERNEL);
2204         if (counters) {
2205                 RTL_W32(CounterAddrHigh, (u64)*paddr >> 32);
2206                 cmd = (u64)*paddr & DMA_BIT_MASK(32);
2207                 RTL_W32(CounterAddrLow, cmd);
2208                 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2209         }
2210         return counters;
2211 }
2212
2213 static void rtl8169_unmap_counters (struct net_device *dev,
2214                                     dma_addr_t paddr,
2215                                     struct rtl8169_counters *counters)
2216 {
2217         struct rtl8169_private *tp = netdev_priv(dev);
2218         void __iomem *ioaddr = tp->mmio_addr;
2219         struct device *d = &tp->pci_dev->dev;
2220
2221         RTL_W32(CounterAddrLow, 0);
2222         RTL_W32(CounterAddrHigh, 0);
2223
2224         dma_free_coherent(d, sizeof(*counters), counters, paddr);
2225 }
2226
2227 DECLARE_RTL_COND(rtl_reset_counters_cond)
2228 {
2229         void __iomem *ioaddr = tp->mmio_addr;
2230
2231         return RTL_R32(CounterAddrLow) & CounterReset;
2232 }
2233
2234 static bool rtl8169_reset_counters(struct net_device *dev)
2235 {
2236         struct rtl8169_private *tp = netdev_priv(dev);
2237         struct rtl8169_counters *counters;
2238         dma_addr_t paddr;
2239         bool ret = true;
2240
2241         /*
2242          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2243          * tally counters.
2244          */
2245         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2246                 return true;
2247
2248         counters = rtl8169_map_counters(dev, &paddr, CounterReset);
2249         if (!counters)
2250                 return false;
2251
2252         if (!rtl_udelay_loop_wait_low(tp, &rtl_reset_counters_cond, 10, 1000))
2253                 ret = false;
2254
2255         rtl8169_unmap_counters(dev, paddr, counters);
2256
2257         return ret;
2258 }
2259
2260 DECLARE_RTL_COND(rtl_counters_cond)
2261 {
2262         void __iomem *ioaddr = tp->mmio_addr;
2263
2264         return RTL_R32(CounterAddrLow) & CounterDump;
2265 }
2266
2267 static bool rtl8169_update_counters(struct net_device *dev)
2268 {
2269         struct rtl8169_private *tp = netdev_priv(dev);
2270         void __iomem *ioaddr = tp->mmio_addr;
2271         struct rtl8169_counters *counters;
2272         dma_addr_t paddr;
2273         bool ret = true;
2274
2275         /*
2276          * Some chips are unable to dump tally counters when the receiver
2277          * is disabled.
2278          */
2279         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2280                 return true;
2281
2282         counters = rtl8169_map_counters(dev, &paddr, CounterDump);
2283         if (!counters)
2284                 return false;
2285
2286         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2287                 memcpy(&tp->counters, counters, sizeof(*counters));
2288         else
2289                 ret = false;
2290
2291         rtl8169_unmap_counters(dev, paddr, counters);
2292
2293         return ret;
2294 }
2295
2296 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2297 {
2298         struct rtl8169_private *tp = netdev_priv(dev);
2299         bool ret = false;
2300
2301         /*
2302          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2303          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2304          * reset by a power cycle, while the counter values collected by the
2305          * driver are reset at every driver unload/load cycle.
2306          *
2307          * To make sure the HW values returned by @get_stats64 match the SW
2308          * values, we collect the initial values at first open(*) and use them
2309          * as offsets to normalize the values returned by @get_stats64.
2310          *
2311          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2312          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2313          * set at open time by rtl_hw_start.
2314          */
2315
2316         if (tp->tc_offset.inited)
2317                 return true;
2318
2319         /* If both, reset and update fail, propagate to caller. */
2320         if (rtl8169_reset_counters(dev))
2321                 ret = true;
2322
2323         if (rtl8169_update_counters(dev))
2324                 ret = true;
2325
2326         tp->tc_offset.tx_errors = tp->counters.tx_errors;
2327         tp->tc_offset.tx_multi_collision = tp->counters.tx_multi_collision;
2328         tp->tc_offset.tx_aborted = tp->counters.tx_aborted;
2329         tp->tc_offset.inited = true;
2330
2331         return ret;
2332 }
2333
2334 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2335                                       struct ethtool_stats *stats, u64 *data)
2336 {
2337         struct rtl8169_private *tp = netdev_priv(dev);
2338
2339         ASSERT_RTNL();
2340
2341         rtl8169_update_counters(dev);
2342
2343         data[0] = le64_to_cpu(tp->counters.tx_packets);
2344         data[1] = le64_to_cpu(tp->counters.rx_packets);
2345         data[2] = le64_to_cpu(tp->counters.tx_errors);
2346         data[3] = le32_to_cpu(tp->counters.rx_errors);
2347         data[4] = le16_to_cpu(tp->counters.rx_missed);
2348         data[5] = le16_to_cpu(tp->counters.align_errors);
2349         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2350         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2351         data[8] = le64_to_cpu(tp->counters.rx_unicast);
2352         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2353         data[10] = le32_to_cpu(tp->counters.rx_multicast);
2354         data[11] = le16_to_cpu(tp->counters.tx_aborted);
2355         data[12] = le16_to_cpu(tp->counters.tx_underun);
2356 }
2357
2358 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2359 {
2360         switch(stringset) {
2361         case ETH_SS_STATS:
2362                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2363                 break;
2364         }
2365 }
2366
2367 static const struct ethtool_ops rtl8169_ethtool_ops = {
2368         .get_drvinfo            = rtl8169_get_drvinfo,
2369         .get_regs_len           = rtl8169_get_regs_len,
2370         .get_link               = ethtool_op_get_link,
2371         .get_settings           = rtl8169_get_settings,
2372         .set_settings           = rtl8169_set_settings,
2373         .get_msglevel           = rtl8169_get_msglevel,
2374         .set_msglevel           = rtl8169_set_msglevel,
2375         .get_regs               = rtl8169_get_regs,
2376         .get_wol                = rtl8169_get_wol,
2377         .set_wol                = rtl8169_set_wol,
2378         .get_strings            = rtl8169_get_strings,
2379         .get_sset_count         = rtl8169_get_sset_count,
2380         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2381         .get_ts_info            = ethtool_op_get_ts_info,
2382 };
2383
2384 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2385                                     struct net_device *dev, u8 default_version)
2386 {
2387         void __iomem *ioaddr = tp->mmio_addr;
2388         /*
2389          * The driver currently handles the 8168Bf and the 8168Be identically
2390          * but they can be identified more specifically through the test below
2391          * if needed:
2392          *
2393          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2394          *
2395          * Same thing for the 8101Eb and the 8101Ec:
2396          *
2397          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2398          */
2399         static const struct rtl_mac_info {
2400                 u32 mask;
2401                 u32 val;
2402                 int mac_version;
2403         } mac_info[] = {
2404                 /* 8168EP family. */
2405                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2406                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2407                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2408
2409                 /* 8168H family. */
2410                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2411                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2412
2413                 /* 8168G family. */
2414                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2415                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2416                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2417                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2418
2419                 /* 8168F family. */
2420                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2421                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2422                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2423
2424                 /* 8168E family. */
2425                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2426                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2427                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2428                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2429
2430                 /* 8168D family. */
2431                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2432                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2433                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2434
2435                 /* 8168DP family. */
2436                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2437                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2438                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2439
2440                 /* 8168C family. */
2441                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2442                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2443                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2444                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2445                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2446                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2447                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2448                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2449                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2450
2451                 /* 8168B family. */
2452                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2453                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2454                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2455                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2456
2457                 /* 8101 family. */
2458                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2459                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2460                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2461                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2462                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2463                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2464                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2465                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2466                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2467                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2468                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2469                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2470                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2471                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2472                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2473                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2474                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2475                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2476                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2477                 /* FIXME: where did these entries come from ? -- FR */
2478                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2479                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2480
2481                 /* 8110 family. */
2482                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2483                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2484                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2485                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2486                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2487                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2488
2489                 /* Catch-all */
2490                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2491         };
2492         const struct rtl_mac_info *p = mac_info;
2493         u32 reg;
2494
2495         reg = RTL_R32(TxConfig);
2496         while ((reg & p->mask) != p->val)
2497                 p++;
2498         tp->mac_version = p->mac_version;
2499
2500         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2501                 netif_notice(tp, probe, dev,
2502                              "unknown MAC, using family default\n");
2503                 tp->mac_version = default_version;
2504         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2505                 tp->mac_version = tp->mii.supports_gmii ?
2506                                   RTL_GIGA_MAC_VER_42 :
2507                                   RTL_GIGA_MAC_VER_43;
2508         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2509                 tp->mac_version = tp->mii.supports_gmii ?
2510                                   RTL_GIGA_MAC_VER_45 :
2511                                   RTL_GIGA_MAC_VER_47;
2512         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2513                 tp->mac_version = tp->mii.supports_gmii ?
2514                                   RTL_GIGA_MAC_VER_46 :
2515                                   RTL_GIGA_MAC_VER_48;
2516         }
2517 }
2518
2519 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2520 {
2521         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2522 }
2523
2524 struct phy_reg {
2525         u16 reg;
2526         u16 val;
2527 };
2528
2529 static void rtl_writephy_batch(struct rtl8169_private *tp,
2530                                const struct phy_reg *regs, int len)
2531 {
2532         while (len-- > 0) {
2533                 rtl_writephy(tp, regs->reg, regs->val);
2534                 regs++;
2535         }
2536 }
2537
2538 #define PHY_READ                0x00000000
2539 #define PHY_DATA_OR             0x10000000
2540 #define PHY_DATA_AND            0x20000000
2541 #define PHY_BJMPN               0x30000000
2542 #define PHY_MDIO_CHG            0x40000000
2543 #define PHY_CLEAR_READCOUNT     0x70000000
2544 #define PHY_WRITE               0x80000000
2545 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2546 #define PHY_COMP_EQ_SKIPN       0xa0000000
2547 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2548 #define PHY_WRITE_PREVIOUS      0xc0000000
2549 #define PHY_SKIPN               0xd0000000
2550 #define PHY_DELAY_MS            0xe0000000
2551
2552 struct fw_info {
2553         u32     magic;
2554         char    version[RTL_VER_SIZE];
2555         __le32  fw_start;
2556         __le32  fw_len;
2557         u8      chksum;
2558 } __packed;
2559
2560 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2561
2562 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2563 {
2564         const struct firmware *fw = rtl_fw->fw;
2565         struct fw_info *fw_info = (struct fw_info *)fw->data;
2566         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2567         char *version = rtl_fw->version;
2568         bool rc = false;
2569
2570         if (fw->size < FW_OPCODE_SIZE)
2571                 goto out;
2572
2573         if (!fw_info->magic) {
2574                 size_t i, size, start;
2575                 u8 checksum = 0;
2576
2577                 if (fw->size < sizeof(*fw_info))
2578                         goto out;
2579
2580                 for (i = 0; i < fw->size; i++)
2581                         checksum += fw->data[i];
2582                 if (checksum != 0)
2583                         goto out;
2584
2585                 start = le32_to_cpu(fw_info->fw_start);
2586                 if (start > fw->size)
2587                         goto out;
2588
2589                 size = le32_to_cpu(fw_info->fw_len);
2590                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2591                         goto out;
2592
2593                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2594
2595                 pa->code = (__le32 *)(fw->data + start);
2596                 pa->size = size;
2597         } else {
2598                 if (fw->size % FW_OPCODE_SIZE)
2599                         goto out;
2600
2601                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2602
2603                 pa->code = (__le32 *)fw->data;
2604                 pa->size = fw->size / FW_OPCODE_SIZE;
2605         }
2606         version[RTL_VER_SIZE - 1] = 0;
2607
2608         rc = true;
2609 out:
2610         return rc;
2611 }
2612
2613 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2614                            struct rtl_fw_phy_action *pa)
2615 {
2616         bool rc = false;
2617         size_t index;
2618
2619         for (index = 0; index < pa->size; index++) {
2620                 u32 action = le32_to_cpu(pa->code[index]);
2621                 u32 regno = (action & 0x0fff0000) >> 16;
2622
2623                 switch(action & 0xf0000000) {
2624                 case PHY_READ:
2625                 case PHY_DATA_OR:
2626                 case PHY_DATA_AND:
2627                 case PHY_MDIO_CHG:
2628                 case PHY_CLEAR_READCOUNT:
2629                 case PHY_WRITE:
2630                 case PHY_WRITE_PREVIOUS:
2631                 case PHY_DELAY_MS:
2632                         break;
2633
2634                 case PHY_BJMPN:
2635                         if (regno > index) {
2636                                 netif_err(tp, ifup, tp->dev,
2637                                           "Out of range of firmware\n");
2638                                 goto out;
2639                         }
2640                         break;
2641                 case PHY_READCOUNT_EQ_SKIP:
2642                         if (index + 2 >= pa->size) {
2643                                 netif_err(tp, ifup, tp->dev,
2644                                           "Out of range of firmware\n");
2645                                 goto out;
2646                         }
2647                         break;
2648                 case PHY_COMP_EQ_SKIPN:
2649                 case PHY_COMP_NEQ_SKIPN:
2650                 case PHY_SKIPN:
2651                         if (index + 1 + regno >= pa->size) {
2652                                 netif_err(tp, ifup, tp->dev,
2653                                           "Out of range of firmware\n");
2654                                 goto out;
2655                         }
2656                         break;
2657
2658                 default:
2659                         netif_err(tp, ifup, tp->dev,
2660                                   "Invalid action 0x%08x\n", action);
2661                         goto out;
2662                 }
2663         }
2664         rc = true;
2665 out:
2666         return rc;
2667 }
2668
2669 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2670 {
2671         struct net_device *dev = tp->dev;
2672         int rc = -EINVAL;
2673
2674         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2675                 netif_err(tp, ifup, dev, "invalid firmware\n");
2676                 goto out;
2677         }
2678
2679         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2680                 rc = 0;
2681 out:
2682         return rc;
2683 }
2684
2685 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2686 {
2687         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2688         struct mdio_ops org, *ops = &tp->mdio_ops;
2689         u32 predata, count;
2690         size_t index;
2691
2692         predata = count = 0;
2693         org.write = ops->write;
2694         org.read = ops->read;
2695
2696         for (index = 0; index < pa->size; ) {
2697                 u32 action = le32_to_cpu(pa->code[index]);
2698                 u32 data = action & 0x0000ffff;
2699                 u32 regno = (action & 0x0fff0000) >> 16;
2700
2701                 if (!action)
2702                         break;
2703
2704                 switch(action & 0xf0000000) {
2705                 case PHY_READ:
2706                         predata = rtl_readphy(tp, regno);
2707                         count++;
2708                         index++;
2709                         break;
2710                 case PHY_DATA_OR:
2711                         predata |= data;
2712                         index++;
2713                         break;
2714                 case PHY_DATA_AND:
2715                         predata &= data;
2716                         index++;
2717                         break;
2718                 case PHY_BJMPN:
2719                         index -= regno;
2720                         break;
2721                 case PHY_MDIO_CHG:
2722                         if (data == 0) {
2723                                 ops->write = org.write;
2724                                 ops->read = org.read;
2725                         } else if (data == 1) {
2726                                 ops->write = mac_mcu_write;
2727                                 ops->read = mac_mcu_read;
2728                         }
2729
2730                         index++;
2731                         break;
2732                 case PHY_CLEAR_READCOUNT:
2733                         count = 0;
2734                         index++;
2735                         break;
2736                 case PHY_WRITE:
2737                         rtl_writephy(tp, regno, data);
2738                         index++;
2739                         break;
2740                 case PHY_READCOUNT_EQ_SKIP:
2741                         index += (count == data) ? 2 : 1;
2742                         break;
2743                 case PHY_COMP_EQ_SKIPN:
2744                         if (predata == data)
2745                                 index += regno;
2746                         index++;
2747                         break;
2748                 case PHY_COMP_NEQ_SKIPN:
2749                         if (predata != data)
2750                                 index += regno;
2751                         index++;
2752                         break;
2753                 case PHY_WRITE_PREVIOUS:
2754                         rtl_writephy(tp, regno, predata);
2755                         index++;
2756                         break;
2757                 case PHY_SKIPN:
2758                         index += regno + 1;
2759                         break;
2760                 case PHY_DELAY_MS:
2761                         mdelay(data);
2762                         index++;
2763                         break;
2764
2765                 default:
2766                         BUG();
2767                 }
2768         }
2769
2770         ops->write = org.write;
2771         ops->read = org.read;
2772 }
2773
2774 static void rtl_release_firmware(struct rtl8169_private *tp)
2775 {
2776         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2777                 release_firmware(tp->rtl_fw->fw);
2778                 kfree(tp->rtl_fw);
2779         }
2780         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2781 }
2782
2783 static void rtl_apply_firmware(struct rtl8169_private *tp)
2784 {
2785         struct rtl_fw *rtl_fw = tp->rtl_fw;
2786
2787         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2788         if (!IS_ERR_OR_NULL(rtl_fw))
2789                 rtl_phy_write_fw(tp, rtl_fw);
2790 }
2791
2792 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2793 {
2794         if (rtl_readphy(tp, reg) != val)
2795                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2796         else
2797                 rtl_apply_firmware(tp);
2798 }
2799
2800 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2801 {
2802         static const struct phy_reg phy_reg_init[] = {
2803                 { 0x1f, 0x0001 },
2804                 { 0x06, 0x006e },
2805                 { 0x08, 0x0708 },
2806                 { 0x15, 0x4000 },
2807                 { 0x18, 0x65c7 },
2808
2809                 { 0x1f, 0x0001 },
2810                 { 0x03, 0x00a1 },
2811                 { 0x02, 0x0008 },
2812                 { 0x01, 0x0120 },
2813                 { 0x00, 0x1000 },
2814                 { 0x04, 0x0800 },
2815                 { 0x04, 0x0000 },
2816
2817                 { 0x03, 0xff41 },
2818                 { 0x02, 0xdf60 },
2819                 { 0x01, 0x0140 },
2820                 { 0x00, 0x0077 },
2821                 { 0x04, 0x7800 },
2822                 { 0x04, 0x7000 },
2823
2824                 { 0x03, 0x802f },
2825                 { 0x02, 0x4f02 },
2826                 { 0x01, 0x0409 },
2827                 { 0x00, 0xf0f9 },
2828                 { 0x04, 0x9800 },
2829                 { 0x04, 0x9000 },
2830
2831                 { 0x03, 0xdf01 },
2832                 { 0x02, 0xdf20 },
2833                 { 0x01, 0xff95 },
2834                 { 0x00, 0xba00 },
2835                 { 0x04, 0xa800 },
2836                 { 0x04, 0xa000 },
2837
2838                 { 0x03, 0xff41 },
2839                 { 0x02, 0xdf20 },
2840                 { 0x01, 0x0140 },
2841                 { 0x00, 0x00bb },
2842                 { 0x04, 0xb800 },
2843                 { 0x04, 0xb000 },
2844
2845                 { 0x03, 0xdf41 },
2846                 { 0x02, 0xdc60 },
2847                 { 0x01, 0x6340 },
2848                 { 0x00, 0x007d },
2849                 { 0x04, 0xd800 },
2850                 { 0x04, 0xd000 },
2851
2852                 { 0x03, 0xdf01 },
2853                 { 0x02, 0xdf20 },
2854                 { 0x01, 0x100a },
2855                 { 0x00, 0xa0ff },
2856                 { 0x04, 0xf800 },
2857                 { 0x04, 0xf000 },
2858
2859                 { 0x1f, 0x0000 },
2860                 { 0x0b, 0x0000 },
2861                 { 0x00, 0x9200 }
2862         };
2863
2864         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2865 }
2866
2867 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2868 {
2869         static const struct phy_reg phy_reg_init[] = {
2870                 { 0x1f, 0x0002 },
2871                 { 0x01, 0x90d0 },
2872                 { 0x1f, 0x0000 }
2873         };
2874
2875         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2876 }
2877
2878 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2879 {
2880         struct pci_dev *pdev = tp->pci_dev;
2881
2882         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2883             (pdev->subsystem_device != 0xe000))
2884                 return;
2885
2886         rtl_writephy(tp, 0x1f, 0x0001);
2887         rtl_writephy(tp, 0x10, 0xf01b);
2888         rtl_writephy(tp, 0x1f, 0x0000);
2889 }
2890
2891 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2892 {
2893         static const struct phy_reg phy_reg_init[] = {
2894                 { 0x1f, 0x0001 },
2895                 { 0x04, 0x0000 },
2896                 { 0x03, 0x00a1 },
2897                 { 0x02, 0x0008 },
2898                 { 0x01, 0x0120 },
2899                 { 0x00, 0x1000 },
2900                 { 0x04, 0x0800 },
2901                 { 0x04, 0x9000 },
2902                 { 0x03, 0x802f },
2903                 { 0x02, 0x4f02 },
2904                 { 0x01, 0x0409 },
2905                 { 0x00, 0xf099 },
2906                 { 0x04, 0x9800 },
2907                 { 0x04, 0xa000 },
2908                 { 0x03, 0xdf01 },
2909                 { 0x02, 0xdf20 },
2910                 { 0x01, 0xff95 },
2911                 { 0x00, 0xba00 },
2912                 { 0x04, 0xa800 },
2913                 { 0x04, 0xf000 },
2914                 { 0x03, 0xdf01 },
2915                 { 0x02, 0xdf20 },
2916                 { 0x01, 0x101a },
2917                 { 0x00, 0xa0ff },
2918                 { 0x04, 0xf800 },
2919                 { 0x04, 0x0000 },
2920                 { 0x1f, 0x0000 },
2921
2922                 { 0x1f, 0x0001 },
2923                 { 0x10, 0xf41b },
2924                 { 0x14, 0xfb54 },
2925                 { 0x18, 0xf5c7 },
2926                 { 0x1f, 0x0000 },
2927
2928                 { 0x1f, 0x0001 },
2929                 { 0x17, 0x0cc0 },
2930                 { 0x1f, 0x0000 }
2931         };
2932
2933         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2934
2935         rtl8169scd_hw_phy_config_quirk(tp);
2936 }
2937
2938 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2939 {
2940         static const struct phy_reg phy_reg_init[] = {
2941                 { 0x1f, 0x0001 },
2942                 { 0x04, 0x0000 },
2943                 { 0x03, 0x00a1 },
2944                 { 0x02, 0x0008 },
2945                 { 0x01, 0x0120 },
2946                 { 0x00, 0x1000 },
2947                 { 0x04, 0x0800 },
2948                 { 0x04, 0x9000 },
2949                 { 0x03, 0x802f },
2950                 { 0x02, 0x4f02 },
2951                 { 0x01, 0x0409 },
2952                 { 0x00, 0xf099 },
2953                 { 0x04, 0x9800 },
2954                 { 0x04, 0xa000 },
2955                 { 0x03, 0xdf01 },
2956                 { 0x02, 0xdf20 },
2957                 { 0x01, 0xff95 },
2958                 { 0x00, 0xba00 },
2959                 { 0x04, 0xa800 },
2960                 { 0x04, 0xf000 },
2961                 { 0x03, 0xdf01 },
2962                 { 0x02, 0xdf20 },
2963                 { 0x01, 0x101a },
2964                 { 0x00, 0xa0ff },
2965                 { 0x04, 0xf800 },
2966                 { 0x04, 0x0000 },
2967                 { 0x1f, 0x0000 },
2968
2969                 { 0x1f, 0x0001 },
2970                 { 0x0b, 0x8480 },
2971                 { 0x1f, 0x0000 },
2972
2973                 { 0x1f, 0x0001 },
2974                 { 0x18, 0x67c7 },
2975                 { 0x04, 0x2000 },
2976                 { 0x03, 0x002f },
2977                 { 0x02, 0x4360 },
2978                 { 0x01, 0x0109 },
2979                 { 0x00, 0x3022 },
2980                 { 0x04, 0x2800 },
2981                 { 0x1f, 0x0000 },
2982
2983                 { 0x1f, 0x0001 },
2984                 { 0x17, 0x0cc0 },
2985                 { 0x1f, 0x0000 }
2986         };
2987
2988         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2989 }
2990
2991 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2992 {
2993         static const struct phy_reg phy_reg_init[] = {
2994                 { 0x10, 0xf41b },
2995                 { 0x1f, 0x0000 }
2996         };
2997
2998         rtl_writephy(tp, 0x1f, 0x0001);
2999         rtl_patchphy(tp, 0x16, 1 << 0);
3000
3001         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3002 }
3003
3004 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3005 {
3006         static const struct phy_reg phy_reg_init[] = {
3007                 { 0x1f, 0x0001 },
3008                 { 0x10, 0xf41b },
3009                 { 0x1f, 0x0000 }
3010         };
3011
3012         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3013 }
3014
3015 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3016 {
3017         static const struct phy_reg phy_reg_init[] = {
3018                 { 0x1f, 0x0000 },
3019                 { 0x1d, 0x0f00 },
3020                 { 0x1f, 0x0002 },
3021                 { 0x0c, 0x1ec8 },
3022                 { 0x1f, 0x0000 }
3023         };
3024
3025         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3026 }
3027
3028 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3029 {
3030         static const struct phy_reg phy_reg_init[] = {
3031                 { 0x1f, 0x0001 },
3032                 { 0x1d, 0x3d98 },
3033                 { 0x1f, 0x0000 }
3034         };
3035
3036         rtl_writephy(tp, 0x1f, 0x0000);
3037         rtl_patchphy(tp, 0x14, 1 << 5);
3038         rtl_patchphy(tp, 0x0d, 1 << 5);
3039
3040         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3041 }
3042
3043 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3044 {
3045         static const struct phy_reg phy_reg_init[] = {
3046                 { 0x1f, 0x0001 },
3047                 { 0x12, 0x2300 },
3048                 { 0x1f, 0x0002 },
3049                 { 0x00, 0x88d4 },
3050                 { 0x01, 0x82b1 },
3051                 { 0x03, 0x7002 },
3052                 { 0x08, 0x9e30 },
3053                 { 0x09, 0x01f0 },
3054                 { 0x0a, 0x5500 },
3055                 { 0x0c, 0x00c8 },
3056                 { 0x1f, 0x0003 },
3057                 { 0x12, 0xc096 },
3058                 { 0x16, 0x000a },
3059                 { 0x1f, 0x0000 },
3060                 { 0x1f, 0x0000 },
3061                 { 0x09, 0x2000 },
3062                 { 0x09, 0x0000 }
3063         };
3064
3065         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3066
3067         rtl_patchphy(tp, 0x14, 1 << 5);
3068         rtl_patchphy(tp, 0x0d, 1 << 5);
3069         rtl_writephy(tp, 0x1f, 0x0000);
3070 }
3071
3072 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3073 {
3074         static const struct phy_reg phy_reg_init[] = {
3075                 { 0x1f, 0x0001 },
3076                 { 0x12, 0x2300 },
3077                 { 0x03, 0x802f },
3078                 { 0x02, 0x4f02 },
3079                 { 0x01, 0x0409 },
3080                 { 0x00, 0xf099 },
3081                 { 0x04, 0x9800 },
3082                 { 0x04, 0x9000 },
3083                 { 0x1d, 0x3d98 },
3084                 { 0x1f, 0x0002 },
3085                 { 0x0c, 0x7eb8 },
3086                 { 0x06, 0x0761 },
3087                 { 0x1f, 0x0003 },
3088                 { 0x16, 0x0f0a },
3089                 { 0x1f, 0x0000 }
3090         };
3091
3092         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3093
3094         rtl_patchphy(tp, 0x16, 1 << 0);
3095         rtl_patchphy(tp, 0x14, 1 << 5);
3096         rtl_patchphy(tp, 0x0d, 1 << 5);
3097         rtl_writephy(tp, 0x1f, 0x0000);
3098 }
3099
3100 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3101 {
3102         static const struct phy_reg phy_reg_init[] = {
3103                 { 0x1f, 0x0001 },
3104                 { 0x12, 0x2300 },
3105                 { 0x1d, 0x3d98 },
3106                 { 0x1f, 0x0002 },
3107                 { 0x0c, 0x7eb8 },
3108                 { 0x06, 0x5461 },
3109                 { 0x1f, 0x0003 },
3110                 { 0x16, 0x0f0a },
3111                 { 0x1f, 0x0000 }
3112         };
3113
3114         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3115
3116         rtl_patchphy(tp, 0x16, 1 << 0);
3117         rtl_patchphy(tp, 0x14, 1 << 5);
3118         rtl_patchphy(tp, 0x0d, 1 << 5);
3119         rtl_writephy(tp, 0x1f, 0x0000);
3120 }
3121
3122 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3123 {
3124         rtl8168c_3_hw_phy_config(tp);
3125 }
3126
3127 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3128 {
3129         static const struct phy_reg phy_reg_init_0[] = {
3130                 /* Channel Estimation */
3131                 { 0x1f, 0x0001 },
3132                 { 0x06, 0x4064 },
3133                 { 0x07, 0x2863 },
3134                 { 0x08, 0x059c },
3135                 { 0x09, 0x26b4 },
3136                 { 0x0a, 0x6a19 },
3137                 { 0x0b, 0xdcc8 },
3138                 { 0x10, 0xf06d },
3139                 { 0x14, 0x7f68 },
3140                 { 0x18, 0x7fd9 },
3141                 { 0x1c, 0xf0ff },
3142                 { 0x1d, 0x3d9c },
3143                 { 0x1f, 0x0003 },
3144                 { 0x12, 0xf49f },
3145                 { 0x13, 0x070b },
3146                 { 0x1a, 0x05ad },
3147                 { 0x14, 0x94c0 },
3148
3149                 /*
3150                  * Tx Error Issue
3151                  * Enhance line driver power
3152                  */
3153                 { 0x1f, 0x0002 },
3154                 { 0x06, 0x5561 },
3155                 { 0x1f, 0x0005 },
3156                 { 0x05, 0x8332 },
3157                 { 0x06, 0x5561 },
3158
3159                 /*
3160                  * Can not link to 1Gbps with bad cable
3161                  * Decrease SNR threshold form 21.07dB to 19.04dB
3162                  */
3163                 { 0x1f, 0x0001 },
3164                 { 0x17, 0x0cc0 },
3165
3166                 { 0x1f, 0x0000 },
3167                 { 0x0d, 0xf880 }
3168         };
3169
3170         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3171
3172         /*
3173          * Rx Error Issue
3174          * Fine Tune Switching regulator parameter
3175          */
3176         rtl_writephy(tp, 0x1f, 0x0002);
3177         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3178         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3179
3180         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3181                 static const struct phy_reg phy_reg_init[] = {
3182                         { 0x1f, 0x0002 },
3183                         { 0x05, 0x669a },
3184                         { 0x1f, 0x0005 },
3185                         { 0x05, 0x8330 },
3186                         { 0x06, 0x669a },
3187                         { 0x1f, 0x0002 }
3188                 };
3189                 int val;
3190
3191                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3192
3193                 val = rtl_readphy(tp, 0x0d);
3194
3195                 if ((val & 0x00ff) != 0x006c) {
3196                         static const u32 set[] = {
3197                                 0x0065, 0x0066, 0x0067, 0x0068,
3198                                 0x0069, 0x006a, 0x006b, 0x006c
3199                         };
3200                         int i;
3201
3202                         rtl_writephy(tp, 0x1f, 0x0002);
3203
3204                         val &= 0xff00;
3205                         for (i = 0; i < ARRAY_SIZE(set); i++)
3206                                 rtl_writephy(tp, 0x0d, val | set[i]);
3207                 }
3208         } else {
3209                 static const struct phy_reg phy_reg_init[] = {
3210                         { 0x1f, 0x0002 },
3211                         { 0x05, 0x6662 },
3212                         { 0x1f, 0x0005 },
3213                         { 0x05, 0x8330 },
3214                         { 0x06, 0x6662 }
3215                 };
3216
3217                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3218         }
3219
3220         /* RSET couple improve */
3221         rtl_writephy(tp, 0x1f, 0x0002);
3222         rtl_patchphy(tp, 0x0d, 0x0300);
3223         rtl_patchphy(tp, 0x0f, 0x0010);
3224
3225         /* Fine tune PLL performance */
3226         rtl_writephy(tp, 0x1f, 0x0002);
3227         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3228         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3229
3230         rtl_writephy(tp, 0x1f, 0x0005);
3231         rtl_writephy(tp, 0x05, 0x001b);
3232
3233         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3234
3235         rtl_writephy(tp, 0x1f, 0x0000);
3236 }
3237
3238 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3239 {
3240         static const struct phy_reg phy_reg_init_0[] = {
3241                 /* Channel Estimation */
3242                 { 0x1f, 0x0001 },
3243                 { 0x06, 0x4064 },
3244                 { 0x07, 0x2863 },
3245                 { 0x08, 0x059c },
3246                 { 0x09, 0x26b4 },
3247                 { 0x0a, 0x6a19 },
3248                 { 0x0b, 0xdcc8 },
3249                 { 0x10, 0xf06d },
3250                 { 0x14, 0x7f68 },
3251                 { 0x18, 0x7fd9 },
3252                 { 0x1c, 0xf0ff },
3253                 { 0x1d, 0x3d9c },
3254                 { 0x1f, 0x0003 },
3255                 { 0x12, 0xf49f },
3256                 { 0x13, 0x070b },
3257                 { 0x1a, 0x05ad },
3258                 { 0x14, 0x94c0 },
3259
3260                 /*
3261                  * Tx Error Issue
3262                  * Enhance line driver power
3263                  */
3264                 { 0x1f, 0x0002 },
3265                 { 0x06, 0x5561 },
3266                 { 0x1f, 0x0005 },
3267                 { 0x05, 0x8332 },
3268                 { 0x06, 0x5561 },
3269
3270                 /*
3271                  * Can not link to 1Gbps with bad cable
3272                  * Decrease SNR threshold form 21.07dB to 19.04dB
3273                  */
3274                 { 0x1f, 0x0001 },
3275                 { 0x17, 0x0cc0 },
3276
3277                 { 0x1f, 0x0000 },
3278                 { 0x0d, 0xf880 }
3279         };
3280
3281         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3282
3283         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3284                 static const struct phy_reg phy_reg_init[] = {
3285                         { 0x1f, 0x0002 },
3286                         { 0x05, 0x669a },
3287                         { 0x1f, 0x0005 },
3288                         { 0x05, 0x8330 },
3289                         { 0x06, 0x669a },
3290
3291                         { 0x1f, 0x0002 }
3292                 };
3293                 int val;
3294
3295                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3296
3297                 val = rtl_readphy(tp, 0x0d);
3298                 if ((val & 0x00ff) != 0x006c) {
3299                         static const u32 set[] = {
3300                                 0x0065, 0x0066, 0x0067, 0x0068,
3301                                 0x0069, 0x006a, 0x006b, 0x006c
3302                         };
3303                         int i;
3304
3305                         rtl_writephy(tp, 0x1f, 0x0002);
3306
3307                         val &= 0xff00;
3308                         for (i = 0; i < ARRAY_SIZE(set); i++)
3309                                 rtl_writephy(tp, 0x0d, val | set[i]);
3310                 }
3311         } else {
3312                 static const struct phy_reg phy_reg_init[] = {
3313                         { 0x1f, 0x0002 },
3314                         { 0x05, 0x2642 },
3315                         { 0x1f, 0x0005 },
3316                         { 0x05, 0x8330 },
3317                         { 0x06, 0x2642 }
3318                 };
3319
3320                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3321         }
3322
3323         /* Fine tune PLL performance */
3324         rtl_writephy(tp, 0x1f, 0x0002);
3325         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3326         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3327
3328         /* Switching regulator Slew rate */
3329         rtl_writephy(tp, 0x1f, 0x0002);
3330         rtl_patchphy(tp, 0x0f, 0x0017);
3331
3332         rtl_writephy(tp, 0x1f, 0x0005);
3333         rtl_writephy(tp, 0x05, 0x001b);
3334
3335         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3336
3337         rtl_writephy(tp, 0x1f, 0x0000);
3338 }
3339
3340 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3341 {
3342         static const struct phy_reg phy_reg_init[] = {
3343                 { 0x1f, 0x0002 },
3344                 { 0x10, 0x0008 },
3345                 { 0x0d, 0x006c },
3346
3347                 { 0x1f, 0x0000 },
3348                 { 0x0d, 0xf880 },
3349
3350                 { 0x1f, 0x0001 },
3351                 { 0x17, 0x0cc0 },
3352
3353                 { 0x1f, 0x0001 },
3354                 { 0x0b, 0xa4d8 },
3355                 { 0x09, 0x281c },
3356                 { 0x07, 0x2883 },
3357                 { 0x0a, 0x6b35 },
3358                 { 0x1d, 0x3da4 },
3359                 { 0x1c, 0xeffd },
3360                 { 0x14, 0x7f52 },
3361                 { 0x18, 0x7fc6 },
3362                 { 0x08, 0x0601 },
3363                 { 0x06, 0x4063 },
3364                 { 0x10, 0xf074 },
3365                 { 0x1f, 0x0003 },
3366                 { 0x13, 0x0789 },
3367                 { 0x12, 0xf4bd },
3368                 { 0x1a, 0x04fd },
3369                 { 0x14, 0x84b0 },
3370                 { 0x1f, 0x0000 },
3371                 { 0x00, 0x9200 },
3372
3373                 { 0x1f, 0x0005 },
3374                 { 0x01, 0x0340 },
3375                 { 0x1f, 0x0001 },
3376                 { 0x04, 0x4000 },
3377                 { 0x03, 0x1d21 },
3378                 { 0x02, 0x0c32 },
3379                 { 0x01, 0x0200 },
3380                 { 0x00, 0x5554 },
3381                 { 0x04, 0x4800 },
3382                 { 0x04, 0x4000 },
3383                 { 0x04, 0xf000 },
3384                 { 0x03, 0xdf01 },
3385                 { 0x02, 0xdf20 },
3386                 { 0x01, 0x101a },
3387                 { 0x00, 0xa0ff },
3388                 { 0x04, 0xf800 },
3389                 { 0x04, 0xf000 },
3390                 { 0x1f, 0x0000 },
3391
3392                 { 0x1f, 0x0007 },
3393                 { 0x1e, 0x0023 },
3394                 { 0x16, 0x0000 },
3395                 { 0x1f, 0x0000 }
3396         };
3397
3398         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3399 }
3400
3401 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3402 {
3403         static const struct phy_reg phy_reg_init[] = {
3404                 { 0x1f, 0x0001 },
3405                 { 0x17, 0x0cc0 },
3406
3407                 { 0x1f, 0x0007 },
3408                 { 0x1e, 0x002d },
3409                 { 0x18, 0x0040 },
3410                 { 0x1f, 0x0000 }
3411         };
3412
3413         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3414         rtl_patchphy(tp, 0x0d, 1 << 5);
3415 }
3416
3417 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3418 {
3419         static const struct phy_reg phy_reg_init[] = {
3420                 /* Enable Delay cap */
3421                 { 0x1f, 0x0005 },
3422                 { 0x05, 0x8b80 },
3423                 { 0x06, 0xc896 },
3424                 { 0x1f, 0x0000 },
3425
3426                 /* Channel estimation fine tune */
3427                 { 0x1f, 0x0001 },
3428                 { 0x0b, 0x6c20 },
3429                 { 0x07, 0x2872 },
3430                 { 0x1c, 0xefff },
3431                 { 0x1f, 0x0003 },
3432                 { 0x14, 0x6420 },
3433                 { 0x1f, 0x0000 },
3434
3435                 /* Update PFM & 10M TX idle timer */
3436                 { 0x1f, 0x0007 },
3437                 { 0x1e, 0x002f },
3438                 { 0x15, 0x1919 },
3439                 { 0x1f, 0x0000 },
3440
3441                 { 0x1f, 0x0007 },
3442                 { 0x1e, 0x00ac },
3443                 { 0x18, 0x0006 },
3444                 { 0x1f, 0x0000 }
3445         };
3446
3447         rtl_apply_firmware(tp);
3448
3449         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3450
3451         /* DCO enable for 10M IDLE Power */
3452         rtl_writephy(tp, 0x1f, 0x0007);
3453         rtl_writephy(tp, 0x1e, 0x0023);
3454         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3455         rtl_writephy(tp, 0x1f, 0x0000);
3456
3457         /* For impedance matching */
3458         rtl_writephy(tp, 0x1f, 0x0002);
3459         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3460         rtl_writephy(tp, 0x1f, 0x0000);
3461
3462         /* PHY auto speed down */
3463         rtl_writephy(tp, 0x1f, 0x0007);
3464         rtl_writephy(tp, 0x1e, 0x002d);
3465         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3466         rtl_writephy(tp, 0x1f, 0x0000);
3467         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3468
3469         rtl_writephy(tp, 0x1f, 0x0005);
3470         rtl_writephy(tp, 0x05, 0x8b86);
3471         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3472         rtl_writephy(tp, 0x1f, 0x0000);
3473
3474         rtl_writephy(tp, 0x1f, 0x0005);
3475         rtl_writephy(tp, 0x05, 0x8b85);
3476         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3477         rtl_writephy(tp, 0x1f, 0x0007);
3478         rtl_writephy(tp, 0x1e, 0x0020);
3479         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3480         rtl_writephy(tp, 0x1f, 0x0006);
3481         rtl_writephy(tp, 0x00, 0x5a00);
3482         rtl_writephy(tp, 0x1f, 0x0000);
3483         rtl_writephy(tp, 0x0d, 0x0007);
3484         rtl_writephy(tp, 0x0e, 0x003c);
3485         rtl_writephy(tp, 0x0d, 0x4007);
3486         rtl_writephy(tp, 0x0e, 0x0000);
3487         rtl_writephy(tp, 0x0d, 0x0000);
3488 }
3489
3490 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3491 {
3492         const u16 w[] = {
3493                 addr[0] | (addr[1] << 8),
3494                 addr[2] | (addr[3] << 8),
3495                 addr[4] | (addr[5] << 8)
3496         };
3497         const struct exgmac_reg e[] = {
3498                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3499                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3500                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3501                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3502         };
3503
3504         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3505 }
3506
3507 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3508 {
3509         static const struct phy_reg phy_reg_init[] = {
3510                 /* Enable Delay cap */
3511                 { 0x1f, 0x0004 },
3512                 { 0x1f, 0x0007 },
3513                 { 0x1e, 0x00ac },
3514                 { 0x18, 0x0006 },
3515                 { 0x1f, 0x0002 },
3516                 { 0x1f, 0x0000 },
3517                 { 0x1f, 0x0000 },
3518
3519                 /* Channel estimation fine tune */
3520                 { 0x1f, 0x0003 },
3521                 { 0x09, 0xa20f },
3522                 { 0x1f, 0x0000 },
3523                 { 0x1f, 0x0000 },
3524
3525                 /* Green Setting */
3526                 { 0x1f, 0x0005 },
3527                 { 0x05, 0x8b5b },
3528                 { 0x06, 0x9222 },
3529                 { 0x05, 0x8b6d },
3530                 { 0x06, 0x8000 },
3531                 { 0x05, 0x8b76 },
3532                 { 0x06, 0x8000 },
3533                 { 0x1f, 0x0000 }
3534         };
3535
3536         rtl_apply_firmware(tp);
3537
3538         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3539
3540         /* For 4-corner performance improve */
3541         rtl_writephy(tp, 0x1f, 0x0005);
3542         rtl_writephy(tp, 0x05, 0x8b80);
3543         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3544         rtl_writephy(tp, 0x1f, 0x0000);
3545
3546         /* PHY auto speed down */
3547         rtl_writephy(tp, 0x1f, 0x0004);
3548         rtl_writephy(tp, 0x1f, 0x0007);
3549         rtl_writephy(tp, 0x1e, 0x002d);
3550         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3551         rtl_writephy(tp, 0x1f, 0x0002);
3552         rtl_writephy(tp, 0x1f, 0x0000);
3553         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3554
3555         /* improve 10M EEE waveform */
3556         rtl_writephy(tp, 0x1f, 0x0005);
3557         rtl_writephy(tp, 0x05, 0x8b86);
3558         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3559         rtl_writephy(tp, 0x1f, 0x0000);
3560
3561         /* Improve 2-pair detection performance */
3562         rtl_writephy(tp, 0x1f, 0x0005);
3563         rtl_writephy(tp, 0x05, 0x8b85);
3564         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3565         rtl_writephy(tp, 0x1f, 0x0000);
3566
3567         /* EEE setting */
3568         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3569         rtl_writephy(tp, 0x1f, 0x0005);
3570         rtl_writephy(tp, 0x05, 0x8b85);
3571         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3572         rtl_writephy(tp, 0x1f, 0x0004);
3573         rtl_writephy(tp, 0x1f, 0x0007);
3574         rtl_writephy(tp, 0x1e, 0x0020);
3575         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3576         rtl_writephy(tp, 0x1f, 0x0002);
3577         rtl_writephy(tp, 0x1f, 0x0000);
3578         rtl_writephy(tp, 0x0d, 0x0007);
3579         rtl_writephy(tp, 0x0e, 0x003c);
3580         rtl_writephy(tp, 0x0d, 0x4007);
3581         rtl_writephy(tp, 0x0e, 0x0000);
3582         rtl_writephy(tp, 0x0d, 0x0000);
3583
3584         /* Green feature */
3585         rtl_writephy(tp, 0x1f, 0x0003);
3586         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3587         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3588         rtl_writephy(tp, 0x1f, 0x0000);
3589
3590         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3591         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3592 }
3593
3594 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3595 {
3596         /* For 4-corner performance improve */
3597         rtl_writephy(tp, 0x1f, 0x0005);
3598         rtl_writephy(tp, 0x05, 0x8b80);
3599         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3600         rtl_writephy(tp, 0x1f, 0x0000);
3601
3602         /* PHY auto speed down */
3603         rtl_writephy(tp, 0x1f, 0x0007);
3604         rtl_writephy(tp, 0x1e, 0x002d);
3605         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3606         rtl_writephy(tp, 0x1f, 0x0000);
3607         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3608
3609         /* Improve 10M EEE waveform */
3610         rtl_writephy(tp, 0x1f, 0x0005);
3611         rtl_writephy(tp, 0x05, 0x8b86);
3612         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3613         rtl_writephy(tp, 0x1f, 0x0000);
3614 }
3615
3616 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3617 {
3618         static const struct phy_reg phy_reg_init[] = {
3619                 /* Channel estimation fine tune */
3620                 { 0x1f, 0x0003 },
3621                 { 0x09, 0xa20f },
3622                 { 0x1f, 0x0000 },
3623
3624                 /* Modify green table for giga & fnet */
3625                 { 0x1f, 0x0005 },
3626                 { 0x05, 0x8b55 },
3627                 { 0x06, 0x0000 },
3628                 { 0x05, 0x8b5e },
3629                 { 0x06, 0x0000 },
3630                 { 0x05, 0x8b67 },
3631                 { 0x06, 0x0000 },
3632                 { 0x05, 0x8b70 },
3633                 { 0x06, 0x0000 },
3634                 { 0x1f, 0x0000 },
3635                 { 0x1f, 0x0007 },
3636                 { 0x1e, 0x0078 },
3637                 { 0x17, 0x0000 },
3638                 { 0x19, 0x00fb },
3639                 { 0x1f, 0x0000 },
3640
3641                 /* Modify green table for 10M */
3642                 { 0x1f, 0x0005 },
3643                 { 0x05, 0x8b79 },
3644                 { 0x06, 0xaa00 },
3645                 { 0x1f, 0x0000 },
3646
3647                 /* Disable hiimpedance detection (RTCT) */
3648                 { 0x1f, 0x0003 },
3649                 { 0x01, 0x328a },
3650                 { 0x1f, 0x0000 }
3651         };
3652
3653         rtl_apply_firmware(tp);
3654
3655         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3656
3657         rtl8168f_hw_phy_config(tp);
3658
3659         /* Improve 2-pair detection performance */
3660         rtl_writephy(tp, 0x1f, 0x0005);
3661         rtl_writephy(tp, 0x05, 0x8b85);
3662         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3663         rtl_writephy(tp, 0x1f, 0x0000);
3664 }
3665
3666 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3667 {
3668         rtl_apply_firmware(tp);
3669
3670         rtl8168f_hw_phy_config(tp);
3671 }
3672
3673 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3674 {
3675         static const struct phy_reg phy_reg_init[] = {
3676                 /* Channel estimation fine tune */
3677                 { 0x1f, 0x0003 },
3678                 { 0x09, 0xa20f },
3679                 { 0x1f, 0x0000 },
3680
3681                 /* Modify green table for giga & fnet */
3682                 { 0x1f, 0x0005 },
3683                 { 0x05, 0x8b55 },
3684                 { 0x06, 0x0000 },
3685                 { 0x05, 0x8b5e },
3686                 { 0x06, 0x0000 },
3687                 { 0x05, 0x8b67 },
3688                 { 0x06, 0x0000 },
3689                 { 0x05, 0x8b70 },
3690                 { 0x06, 0x0000 },
3691                 { 0x1f, 0x0000 },
3692                 { 0x1f, 0x0007 },
3693                 { 0x1e, 0x0078 },
3694                 { 0x17, 0x0000 },
3695                 { 0x19, 0x00aa },
3696                 { 0x1f, 0x0000 },
3697
3698                 /* Modify green table for 10M */
3699                 { 0x1f, 0x0005 },
3700                 { 0x05, 0x8b79 },
3701                 { 0x06, 0xaa00 },
3702                 { 0x1f, 0x0000 },
3703
3704                 /* Disable hiimpedance detection (RTCT) */
3705                 { 0x1f, 0x0003 },
3706                 { 0x01, 0x328a },
3707                 { 0x1f, 0x0000 }
3708         };
3709
3710
3711         rtl_apply_firmware(tp);
3712
3713         rtl8168f_hw_phy_config(tp);
3714
3715         /* Improve 2-pair detection performance */
3716         rtl_writephy(tp, 0x1f, 0x0005);
3717         rtl_writephy(tp, 0x05, 0x8b85);
3718         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3719         rtl_writephy(tp, 0x1f, 0x0000);
3720
3721         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3722
3723         /* Modify green table for giga */
3724         rtl_writephy(tp, 0x1f, 0x0005);
3725         rtl_writephy(tp, 0x05, 0x8b54);
3726         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3727         rtl_writephy(tp, 0x05, 0x8b5d);
3728         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3729         rtl_writephy(tp, 0x05, 0x8a7c);
3730         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3731         rtl_writephy(tp, 0x05, 0x8a7f);
3732         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3733         rtl_writephy(tp, 0x05, 0x8a82);
3734         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3735         rtl_writephy(tp, 0x05, 0x8a85);
3736         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3737         rtl_writephy(tp, 0x05, 0x8a88);
3738         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3739         rtl_writephy(tp, 0x1f, 0x0000);
3740
3741         /* uc same-seed solution */
3742         rtl_writephy(tp, 0x1f, 0x0005);
3743         rtl_writephy(tp, 0x05, 0x8b85);
3744         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3745         rtl_writephy(tp, 0x1f, 0x0000);
3746
3747         /* eee setting */
3748         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3749         rtl_writephy(tp, 0x1f, 0x0005);
3750         rtl_writephy(tp, 0x05, 0x8b85);
3751         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3752         rtl_writephy(tp, 0x1f, 0x0004);
3753         rtl_writephy(tp, 0x1f, 0x0007);
3754         rtl_writephy(tp, 0x1e, 0x0020);
3755         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3756         rtl_writephy(tp, 0x1f, 0x0000);
3757         rtl_writephy(tp, 0x0d, 0x0007);
3758         rtl_writephy(tp, 0x0e, 0x003c);
3759         rtl_writephy(tp, 0x0d, 0x4007);
3760         rtl_writephy(tp, 0x0e, 0x0000);
3761         rtl_writephy(tp, 0x0d, 0x0000);
3762
3763         /* Green feature */
3764         rtl_writephy(tp, 0x1f, 0x0003);
3765         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3766         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3767         rtl_writephy(tp, 0x1f, 0x0000);
3768 }
3769
3770 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3771 {
3772         rtl_apply_firmware(tp);
3773
3774         rtl_writephy(tp, 0x1f, 0x0a46);
3775         if (rtl_readphy(tp, 0x10) & 0x0100) {
3776                 rtl_writephy(tp, 0x1f, 0x0bcc);
3777                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3778         } else {
3779                 rtl_writephy(tp, 0x1f, 0x0bcc);
3780                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3781         }
3782
3783         rtl_writephy(tp, 0x1f, 0x0a46);
3784         if (rtl_readphy(tp, 0x13) & 0x0100) {
3785                 rtl_writephy(tp, 0x1f, 0x0c41);
3786                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3787         } else {
3788                 rtl_writephy(tp, 0x1f, 0x0c41);
3789                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3790         }
3791
3792         /* Enable PHY auto speed down */
3793         rtl_writephy(tp, 0x1f, 0x0a44);
3794         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3795
3796         rtl_writephy(tp, 0x1f, 0x0bcc);
3797         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3798         rtl_writephy(tp, 0x1f, 0x0a44);
3799         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3800         rtl_writephy(tp, 0x1f, 0x0a43);
3801         rtl_writephy(tp, 0x13, 0x8084);
3802         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3803         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3804
3805         /* EEE auto-fallback function */
3806         rtl_writephy(tp, 0x1f, 0x0a4b);
3807         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3808
3809         /* Enable UC LPF tune function */
3810         rtl_writephy(tp, 0x1f, 0x0a43);
3811         rtl_writephy(tp, 0x13, 0x8012);
3812         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3813
3814         rtl_writephy(tp, 0x1f, 0x0c42);
3815         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3816
3817         /* Improve SWR Efficiency */
3818         rtl_writephy(tp, 0x1f, 0x0bcd);
3819         rtl_writephy(tp, 0x14, 0x5065);
3820         rtl_writephy(tp, 0x14, 0xd065);
3821         rtl_writephy(tp, 0x1f, 0x0bc8);
3822         rtl_writephy(tp, 0x11, 0x5655);
3823         rtl_writephy(tp, 0x1f, 0x0bcd);
3824         rtl_writephy(tp, 0x14, 0x1065);
3825         rtl_writephy(tp, 0x14, 0x9065);
3826         rtl_writephy(tp, 0x14, 0x1065);
3827
3828         /* Check ALDPS bit, disable it if enabled */
3829         rtl_writephy(tp, 0x1f, 0x0a43);
3830         if (rtl_readphy(tp, 0x10) & 0x0004)
3831                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3832
3833         rtl_writephy(tp, 0x1f, 0x0000);
3834 }
3835
3836 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3837 {
3838         rtl_apply_firmware(tp);
3839 }
3840
3841 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3842 {
3843         u16 dout_tapbin;
3844         u32 data;
3845
3846         rtl_apply_firmware(tp);
3847
3848         /* CHN EST parameters adjust - giga master */
3849         rtl_writephy(tp, 0x1f, 0x0a43);
3850         rtl_writephy(tp, 0x13, 0x809b);
3851         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3852         rtl_writephy(tp, 0x13, 0x80a2);
3853         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3854         rtl_writephy(tp, 0x13, 0x80a4);
3855         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3856         rtl_writephy(tp, 0x13, 0x809c);
3857         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3858         rtl_writephy(tp, 0x1f, 0x0000);
3859
3860         /* CHN EST parameters adjust - giga slave */
3861         rtl_writephy(tp, 0x1f, 0x0a43);
3862         rtl_writephy(tp, 0x13, 0x80ad);
3863         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3864         rtl_writephy(tp, 0x13, 0x80b4);
3865         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3866         rtl_writephy(tp, 0x13, 0x80ac);
3867         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3868         rtl_writephy(tp, 0x1f, 0x0000);
3869
3870         /* CHN EST parameters adjust - fnet */
3871         rtl_writephy(tp, 0x1f, 0x0a43);
3872         rtl_writephy(tp, 0x13, 0x808e);
3873         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3874         rtl_writephy(tp, 0x13, 0x8090);
3875         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3876         rtl_writephy(tp, 0x13, 0x8092);
3877         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3878         rtl_writephy(tp, 0x1f, 0x0000);
3879
3880         /* enable R-tune & PGA-retune function */
3881         dout_tapbin = 0;
3882         rtl_writephy(tp, 0x1f, 0x0a46);
3883         data = rtl_readphy(tp, 0x13);
3884         data &= 3;
3885         data <<= 2;
3886         dout_tapbin |= data;
3887         data = rtl_readphy(tp, 0x12);
3888         data &= 0xc000;
3889         data >>= 14;
3890         dout_tapbin |= data;
3891         dout_tapbin = ~(dout_tapbin^0x08);
3892         dout_tapbin <<= 12;
3893         dout_tapbin &= 0xf000;
3894         rtl_writephy(tp, 0x1f, 0x0a43);
3895         rtl_writephy(tp, 0x13, 0x827a);
3896         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3897         rtl_writephy(tp, 0x13, 0x827b);
3898         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3899         rtl_writephy(tp, 0x13, 0x827c);
3900         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3901         rtl_writephy(tp, 0x13, 0x827d);
3902         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3903
3904         rtl_writephy(tp, 0x1f, 0x0a43);
3905         rtl_writephy(tp, 0x13, 0x0811);
3906         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3907         rtl_writephy(tp, 0x1f, 0x0a42);
3908         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3909         rtl_writephy(tp, 0x1f, 0x0000);
3910
3911         /* enable GPHY 10M */
3912         rtl_writephy(tp, 0x1f, 0x0a44);
3913         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3914         rtl_writephy(tp, 0x1f, 0x0000);
3915
3916         /* SAR ADC performance */
3917         rtl_writephy(tp, 0x1f, 0x0bca);
3918         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3919         rtl_writephy(tp, 0x1f, 0x0000);
3920
3921         rtl_writephy(tp, 0x1f, 0x0a43);
3922         rtl_writephy(tp, 0x13, 0x803f);
3923         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3924         rtl_writephy(tp, 0x13, 0x8047);
3925         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3926         rtl_writephy(tp, 0x13, 0x804f);
3927         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3928         rtl_writephy(tp, 0x13, 0x8057);
3929         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3930         rtl_writephy(tp, 0x13, 0x805f);
3931         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3932         rtl_writephy(tp, 0x13, 0x8067);
3933         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3934         rtl_writephy(tp, 0x13, 0x806f);
3935         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3936         rtl_writephy(tp, 0x1f, 0x0000);
3937
3938         /* disable phy pfm mode */
3939         rtl_writephy(tp, 0x1f, 0x0a44);
3940         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3941         rtl_writephy(tp, 0x1f, 0x0000);
3942
3943         /* Check ALDPS bit, disable it if enabled */
3944         rtl_writephy(tp, 0x1f, 0x0a43);
3945         if (rtl_readphy(tp, 0x10) & 0x0004)
3946                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3947
3948         rtl_writephy(tp, 0x1f, 0x0000);
3949 }
3950
3951 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3952 {
3953         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3954         u16 rlen;
3955         u32 data;
3956
3957         rtl_apply_firmware(tp);
3958
3959         /* CHIN EST parameter update */
3960         rtl_writephy(tp, 0x1f, 0x0a43);
3961         rtl_writephy(tp, 0x13, 0x808a);
3962         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3963         rtl_writephy(tp, 0x1f, 0x0000);
3964
3965         /* enable R-tune & PGA-retune function */
3966         rtl_writephy(tp, 0x1f, 0x0a43);
3967         rtl_writephy(tp, 0x13, 0x0811);
3968         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3969         rtl_writephy(tp, 0x1f, 0x0a42);
3970         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3971         rtl_writephy(tp, 0x1f, 0x0000);
3972
3973         /* enable GPHY 10M */
3974         rtl_writephy(tp, 0x1f, 0x0a44);
3975         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3976         rtl_writephy(tp, 0x1f, 0x0000);
3977
3978         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3979         data = r8168_mac_ocp_read(tp, 0xdd02);
3980         ioffset_p3 = ((data & 0x80)>>7);
3981         ioffset_p3 <<= 3;
3982
3983         data = r8168_mac_ocp_read(tp, 0xdd00);
3984         ioffset_p3 |= ((data & (0xe000))>>13);
3985         ioffset_p2 = ((data & (0x1e00))>>9);
3986         ioffset_p1 = ((data & (0x01e0))>>5);
3987         ioffset_p0 = ((data & 0x0010)>>4);
3988         ioffset_p0 <<= 3;
3989         ioffset_p0 |= (data & (0x07));
3990         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3991
3992         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3993             (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3994                 rtl_writephy(tp, 0x1f, 0x0bcf);
3995                 rtl_writephy(tp, 0x16, data);
3996                 rtl_writephy(tp, 0x1f, 0x0000);
3997         }
3998
3999         /* Modify rlen (TX LPF corner frequency) level */
4000         rtl_writephy(tp, 0x1f, 0x0bcd);
4001         data = rtl_readphy(tp, 0x16);
4002         data &= 0x000f;
4003         rlen = 0;
4004         if (data > 3)
4005                 rlen = data - 3;
4006         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4007         rtl_writephy(tp, 0x17, data);
4008         rtl_writephy(tp, 0x1f, 0x0bcd);
4009         rtl_writephy(tp, 0x1f, 0x0000);
4010
4011         /* disable phy pfm mode */
4012         rtl_writephy(tp, 0x1f, 0x0a44);
4013         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
4014         rtl_writephy(tp, 0x1f, 0x0000);
4015
4016         /* Check ALDPS bit, disable it if enabled */
4017         rtl_writephy(tp, 0x1f, 0x0a43);
4018         if (rtl_readphy(tp, 0x10) & 0x0004)
4019                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4020
4021         rtl_writephy(tp, 0x1f, 0x0000);
4022 }
4023
4024 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4025 {
4026         /* Enable PHY auto speed down */
4027         rtl_writephy(tp, 0x1f, 0x0a44);
4028         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4029         rtl_writephy(tp, 0x1f, 0x0000);
4030
4031         /* patch 10M & ALDPS */
4032         rtl_writephy(tp, 0x1f, 0x0bcc);
4033         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4034         rtl_writephy(tp, 0x1f, 0x0a44);
4035         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4036         rtl_writephy(tp, 0x1f, 0x0a43);
4037         rtl_writephy(tp, 0x13, 0x8084);
4038         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4039         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4040         rtl_writephy(tp, 0x1f, 0x0000);
4041
4042         /* Enable EEE auto-fallback function */
4043         rtl_writephy(tp, 0x1f, 0x0a4b);
4044         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4045         rtl_writephy(tp, 0x1f, 0x0000);
4046
4047         /* Enable UC LPF tune function */
4048         rtl_writephy(tp, 0x1f, 0x0a43);
4049         rtl_writephy(tp, 0x13, 0x8012);
4050         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4051         rtl_writephy(tp, 0x1f, 0x0000);
4052
4053         /* set rg_sel_sdm_rate */
4054         rtl_writephy(tp, 0x1f, 0x0c42);
4055         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4056         rtl_writephy(tp, 0x1f, 0x0000);
4057
4058         /* Check ALDPS bit, disable it if enabled */
4059         rtl_writephy(tp, 0x1f, 0x0a43);
4060         if (rtl_readphy(tp, 0x10) & 0x0004)
4061                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4062
4063         rtl_writephy(tp, 0x1f, 0x0000);
4064 }
4065
4066 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4067 {
4068         /* patch 10M & ALDPS */
4069         rtl_writephy(tp, 0x1f, 0x0bcc);
4070         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4071         rtl_writephy(tp, 0x1f, 0x0a44);
4072         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4073         rtl_writephy(tp, 0x1f, 0x0a43);
4074         rtl_writephy(tp, 0x13, 0x8084);
4075         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4076         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4077         rtl_writephy(tp, 0x1f, 0x0000);
4078
4079         /* Enable UC LPF tune function */
4080         rtl_writephy(tp, 0x1f, 0x0a43);
4081         rtl_writephy(tp, 0x13, 0x8012);
4082         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4083         rtl_writephy(tp, 0x1f, 0x0000);
4084
4085         /* Set rg_sel_sdm_rate */
4086         rtl_writephy(tp, 0x1f, 0x0c42);
4087         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4088         rtl_writephy(tp, 0x1f, 0x0000);
4089
4090         /* Channel estimation parameters */
4091         rtl_writephy(tp, 0x1f, 0x0a43);
4092         rtl_writephy(tp, 0x13, 0x80f3);
4093         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4094         rtl_writephy(tp, 0x13, 0x80f0);
4095         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4096         rtl_writephy(tp, 0x13, 0x80ef);
4097         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4098         rtl_writephy(tp, 0x13, 0x80f6);
4099         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4100         rtl_writephy(tp, 0x13, 0x80ec);
4101         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4102         rtl_writephy(tp, 0x13, 0x80ed);
4103         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4104         rtl_writephy(tp, 0x13, 0x80f2);
4105         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4106         rtl_writephy(tp, 0x13, 0x80f4);
4107         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4108         rtl_writephy(tp, 0x1f, 0x0a43);
4109         rtl_writephy(tp, 0x13, 0x8110);
4110         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4111         rtl_writephy(tp, 0x13, 0x810f);
4112         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4113         rtl_writephy(tp, 0x13, 0x8111);
4114         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4115         rtl_writephy(tp, 0x13, 0x8113);
4116         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4117         rtl_writephy(tp, 0x13, 0x8115);
4118         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4119         rtl_writephy(tp, 0x13, 0x810e);
4120         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4121         rtl_writephy(tp, 0x13, 0x810c);
4122         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4123         rtl_writephy(tp, 0x13, 0x810b);
4124         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4125         rtl_writephy(tp, 0x1f, 0x0a43);
4126         rtl_writephy(tp, 0x13, 0x80d1);
4127         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4128         rtl_writephy(tp, 0x13, 0x80cd);
4129         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4130         rtl_writephy(tp, 0x13, 0x80d3);
4131         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4132         rtl_writephy(tp, 0x13, 0x80d5);
4133         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4134         rtl_writephy(tp, 0x13, 0x80d7);
4135         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4136
4137         /* Force PWM-mode */
4138         rtl_writephy(tp, 0x1f, 0x0bcd);
4139         rtl_writephy(tp, 0x14, 0x5065);
4140         rtl_writephy(tp, 0x14, 0xd065);
4141         rtl_writephy(tp, 0x1f, 0x0bc8);
4142         rtl_writephy(tp, 0x12, 0x00ed);
4143         rtl_writephy(tp, 0x1f, 0x0bcd);
4144         rtl_writephy(tp, 0x14, 0x1065);
4145         rtl_writephy(tp, 0x14, 0x9065);
4146         rtl_writephy(tp, 0x14, 0x1065);
4147         rtl_writephy(tp, 0x1f, 0x0000);
4148
4149         /* Check ALDPS bit, disable it if enabled */
4150         rtl_writephy(tp, 0x1f, 0x0a43);
4151         if (rtl_readphy(tp, 0x10) & 0x0004)
4152                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4153
4154         rtl_writephy(tp, 0x1f, 0x0000);
4155 }
4156
4157 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4158 {
4159         static const struct phy_reg phy_reg_init[] = {
4160                 { 0x1f, 0x0003 },
4161                 { 0x08, 0x441d },
4162                 { 0x01, 0x9100 },
4163                 { 0x1f, 0x0000 }
4164         };
4165
4166         rtl_writephy(tp, 0x1f, 0x0000);
4167         rtl_patchphy(tp, 0x11, 1 << 12);
4168         rtl_patchphy(tp, 0x19, 1 << 13);
4169         rtl_patchphy(tp, 0x10, 1 << 15);
4170
4171         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4172 }
4173
4174 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4175 {
4176         static const struct phy_reg phy_reg_init[] = {
4177                 { 0x1f, 0x0005 },
4178                 { 0x1a, 0x0000 },
4179                 { 0x1f, 0x0000 },
4180
4181                 { 0x1f, 0x0004 },
4182                 { 0x1c, 0x0000 },
4183                 { 0x1f, 0x0000 },
4184
4185                 { 0x1f, 0x0001 },
4186                 { 0x15, 0x7701 },
4187                 { 0x1f, 0x0000 }
4188         };
4189
4190         /* Disable ALDPS before ram code */
4191         rtl_writephy(tp, 0x1f, 0x0000);
4192         rtl_writephy(tp, 0x18, 0x0310);
4193         msleep(100);
4194
4195         rtl_apply_firmware(tp);
4196
4197         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4198 }
4199
4200 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4201 {
4202         /* Disable ALDPS before setting firmware */
4203         rtl_writephy(tp, 0x1f, 0x0000);
4204         rtl_writephy(tp, 0x18, 0x0310);
4205         msleep(20);
4206
4207         rtl_apply_firmware(tp);
4208
4209         /* EEE setting */
4210         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4211         rtl_writephy(tp, 0x1f, 0x0004);
4212         rtl_writephy(tp, 0x10, 0x401f);
4213         rtl_writephy(tp, 0x19, 0x7030);
4214         rtl_writephy(tp, 0x1f, 0x0000);
4215 }
4216
4217 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4218 {
4219         static const struct phy_reg phy_reg_init[] = {
4220                 { 0x1f, 0x0004 },
4221                 { 0x10, 0xc07f },
4222                 { 0x19, 0x7030 },
4223                 { 0x1f, 0x0000 }
4224         };
4225
4226         /* Disable ALDPS before ram code */
4227         rtl_writephy(tp, 0x1f, 0x0000);
4228         rtl_writephy(tp, 0x18, 0x0310);
4229         msleep(100);
4230
4231         rtl_apply_firmware(tp);
4232
4233         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4234         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4235
4236         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4237 }
4238
4239 static void rtl_hw_phy_config(struct net_device *dev)
4240 {
4241         struct rtl8169_private *tp = netdev_priv(dev);
4242
4243         rtl8169_print_mac_version(tp);
4244
4245         switch (tp->mac_version) {
4246         case RTL_GIGA_MAC_VER_01:
4247                 break;
4248         case RTL_GIGA_MAC_VER_02:
4249         case RTL_GIGA_MAC_VER_03:
4250                 rtl8169s_hw_phy_config(tp);
4251                 break;
4252         case RTL_GIGA_MAC_VER_04:
4253                 rtl8169sb_hw_phy_config(tp);
4254                 break;
4255         case RTL_GIGA_MAC_VER_05:
4256                 rtl8169scd_hw_phy_config(tp);
4257                 break;
4258         case RTL_GIGA_MAC_VER_06:
4259                 rtl8169sce_hw_phy_config(tp);
4260                 break;
4261         case RTL_GIGA_MAC_VER_07:
4262         case RTL_GIGA_MAC_VER_08:
4263         case RTL_GIGA_MAC_VER_09:
4264                 rtl8102e_hw_phy_config(tp);
4265                 break;
4266         case RTL_GIGA_MAC_VER_11:
4267                 rtl8168bb_hw_phy_config(tp);
4268                 break;
4269         case RTL_GIGA_MAC_VER_12:
4270                 rtl8168bef_hw_phy_config(tp);
4271                 break;
4272         case RTL_GIGA_MAC_VER_17:
4273                 rtl8168bef_hw_phy_config(tp);
4274                 break;
4275         case RTL_GIGA_MAC_VER_18:
4276                 rtl8168cp_1_hw_phy_config(tp);
4277                 break;
4278         case RTL_GIGA_MAC_VER_19:
4279                 rtl8168c_1_hw_phy_config(tp);
4280                 break;
4281         case RTL_GIGA_MAC_VER_20:
4282                 rtl8168c_2_hw_phy_config(tp);
4283                 break;
4284         case RTL_GIGA_MAC_VER_21:
4285                 rtl8168c_3_hw_phy_config(tp);
4286                 break;
4287         case RTL_GIGA_MAC_VER_22:
4288                 rtl8168c_4_hw_phy_config(tp);
4289                 break;
4290         case RTL_GIGA_MAC_VER_23:
4291         case RTL_GIGA_MAC_VER_24:
4292                 rtl8168cp_2_hw_phy_config(tp);
4293                 break;
4294         case RTL_GIGA_MAC_VER_25:
4295                 rtl8168d_1_hw_phy_config(tp);
4296                 break;
4297         case RTL_GIGA_MAC_VER_26:
4298                 rtl8168d_2_hw_phy_config(tp);
4299                 break;
4300         case RTL_GIGA_MAC_VER_27:
4301                 rtl8168d_3_hw_phy_config(tp);
4302                 break;
4303         case RTL_GIGA_MAC_VER_28:
4304                 rtl8168d_4_hw_phy_config(tp);
4305                 break;
4306         case RTL_GIGA_MAC_VER_29:
4307         case RTL_GIGA_MAC_VER_30:
4308                 rtl8105e_hw_phy_config(tp);
4309                 break;
4310         case RTL_GIGA_MAC_VER_31:
4311                 /* None. */
4312                 break;
4313         case RTL_GIGA_MAC_VER_32:
4314         case RTL_GIGA_MAC_VER_33:
4315                 rtl8168e_1_hw_phy_config(tp);
4316                 break;
4317         case RTL_GIGA_MAC_VER_34:
4318                 rtl8168e_2_hw_phy_config(tp);
4319                 break;
4320         case RTL_GIGA_MAC_VER_35:
4321                 rtl8168f_1_hw_phy_config(tp);
4322                 break;
4323         case RTL_GIGA_MAC_VER_36:
4324                 rtl8168f_2_hw_phy_config(tp);
4325                 break;
4326
4327         case RTL_GIGA_MAC_VER_37:
4328                 rtl8402_hw_phy_config(tp);
4329                 break;
4330
4331         case RTL_GIGA_MAC_VER_38:
4332                 rtl8411_hw_phy_config(tp);
4333                 break;
4334
4335         case RTL_GIGA_MAC_VER_39:
4336                 rtl8106e_hw_phy_config(tp);
4337                 break;
4338
4339         case RTL_GIGA_MAC_VER_40:
4340                 rtl8168g_1_hw_phy_config(tp);
4341                 break;
4342         case RTL_GIGA_MAC_VER_42:
4343         case RTL_GIGA_MAC_VER_43:
4344         case RTL_GIGA_MAC_VER_44:
4345                 rtl8168g_2_hw_phy_config(tp);
4346                 break;
4347         case RTL_GIGA_MAC_VER_45:
4348         case RTL_GIGA_MAC_VER_47:
4349                 rtl8168h_1_hw_phy_config(tp);
4350                 break;
4351         case RTL_GIGA_MAC_VER_46:
4352         case RTL_GIGA_MAC_VER_48:
4353                 rtl8168h_2_hw_phy_config(tp);
4354                 break;
4355
4356         case RTL_GIGA_MAC_VER_49:
4357                 rtl8168ep_1_hw_phy_config(tp);
4358                 break;
4359         case RTL_GIGA_MAC_VER_50:
4360         case RTL_GIGA_MAC_VER_51:
4361                 rtl8168ep_2_hw_phy_config(tp);
4362                 break;
4363
4364         case RTL_GIGA_MAC_VER_41:
4365         default:
4366                 break;
4367         }
4368 }
4369
4370 static void rtl_phy_work(struct rtl8169_private *tp)
4371 {
4372         struct timer_list *timer = &tp->timer;
4373         void __iomem *ioaddr = tp->mmio_addr;
4374         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4375
4376         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4377
4378         if (tp->phy_reset_pending(tp)) {
4379                 /*
4380                  * A busy loop could burn quite a few cycles on nowadays CPU.
4381                  * Let's delay the execution of the timer for a few ticks.
4382                  */
4383                 timeout = HZ/10;
4384                 goto out_mod_timer;
4385         }
4386
4387         if (tp->link_ok(ioaddr))
4388                 return;
4389
4390         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4391
4392         tp->phy_reset_enable(tp);
4393
4394 out_mod_timer:
4395         mod_timer(timer, jiffies + timeout);
4396 }
4397
4398 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4399 {
4400         if (!test_and_set_bit(flag, tp->wk.flags))
4401                 schedule_work(&tp->wk.work);
4402 }
4403
4404 static void rtl8169_phy_timer(unsigned long __opaque)
4405 {
4406         struct net_device *dev = (struct net_device *)__opaque;
4407         struct rtl8169_private *tp = netdev_priv(dev);
4408
4409         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4410 }
4411
4412 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4413                                   void __iomem *ioaddr)
4414 {
4415         iounmap(ioaddr);
4416         pci_release_regions(pdev);
4417         pci_clear_mwi(pdev);
4418         pci_disable_device(pdev);
4419         free_netdev(dev);
4420 }
4421
4422 DECLARE_RTL_COND(rtl_phy_reset_cond)
4423 {
4424         return tp->phy_reset_pending(tp);
4425 }
4426
4427 static void rtl8169_phy_reset(struct net_device *dev,
4428                               struct rtl8169_private *tp)
4429 {
4430         tp->phy_reset_enable(tp);
4431         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4432 }
4433
4434 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4435 {
4436         void __iomem *ioaddr = tp->mmio_addr;
4437
4438         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4439             (RTL_R8(PHYstatus) & TBI_Enable);
4440 }
4441
4442 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4443 {
4444         void __iomem *ioaddr = tp->mmio_addr;
4445
4446         rtl_hw_phy_config(dev);
4447
4448         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4449                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4450                 RTL_W8(0x82, 0x01);
4451         }
4452
4453         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4454
4455         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4456                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4457
4458         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4459                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4460                 RTL_W8(0x82, 0x01);
4461                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4462                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4463         }
4464
4465         rtl8169_phy_reset(dev, tp);
4466
4467         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4468                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4469                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4470                           (tp->mii.supports_gmii ?
4471                            ADVERTISED_1000baseT_Half |
4472                            ADVERTISED_1000baseT_Full : 0));
4473
4474         if (rtl_tbi_enabled(tp))
4475                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4476 }
4477
4478 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4479 {
4480         void __iomem *ioaddr = tp->mmio_addr;
4481
4482         rtl_lock_work(tp);
4483
4484         RTL_W8(Cfg9346, Cfg9346_Unlock);
4485
4486         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4487         RTL_R32(MAC4);
4488
4489         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4490         RTL_R32(MAC0);
4491
4492         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4493                 rtl_rar_exgmac_set(tp, addr);
4494
4495         RTL_W8(Cfg9346, Cfg9346_Lock);
4496
4497         rtl_unlock_work(tp);
4498 }
4499
4500 static int rtl_set_mac_address(struct net_device *dev, void *p)
4501 {
4502         struct rtl8169_private *tp = netdev_priv(dev);
4503         struct sockaddr *addr = p;
4504
4505         if (!is_valid_ether_addr(addr->sa_data))
4506                 return -EADDRNOTAVAIL;
4507
4508         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4509
4510         rtl_rar_set(tp, dev->dev_addr);
4511
4512         return 0;
4513 }
4514
4515 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4516 {
4517         struct rtl8169_private *tp = netdev_priv(dev);
4518         struct mii_ioctl_data *data = if_mii(ifr);
4519
4520         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4521 }
4522
4523 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4524                           struct mii_ioctl_data *data, int cmd)
4525 {
4526         switch (cmd) {
4527         case SIOCGMIIPHY:
4528                 data->phy_id = 32; /* Internal PHY */
4529                 return 0;
4530
4531         case SIOCGMIIREG:
4532                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4533                 return 0;
4534
4535         case SIOCSMIIREG:
4536                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4537                 return 0;
4538         }
4539         return -EOPNOTSUPP;
4540 }
4541
4542 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4543 {
4544         return -EOPNOTSUPP;
4545 }
4546
4547 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4548 {
4549         if (tp->features & RTL_FEATURE_MSI) {
4550                 pci_disable_msi(pdev);
4551                 tp->features &= ~RTL_FEATURE_MSI;
4552         }
4553 }
4554
4555 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4556 {
4557         struct mdio_ops *ops = &tp->mdio_ops;
4558
4559         switch (tp->mac_version) {
4560         case RTL_GIGA_MAC_VER_27:
4561                 ops->write      = r8168dp_1_mdio_write;
4562                 ops->read       = r8168dp_1_mdio_read;
4563                 break;
4564         case RTL_GIGA_MAC_VER_28:
4565         case RTL_GIGA_MAC_VER_31:
4566                 ops->write      = r8168dp_2_mdio_write;
4567                 ops->read       = r8168dp_2_mdio_read;
4568                 break;
4569         case RTL_GIGA_MAC_VER_40:
4570         case RTL_GIGA_MAC_VER_41:
4571         case RTL_GIGA_MAC_VER_42:
4572         case RTL_GIGA_MAC_VER_43:
4573         case RTL_GIGA_MAC_VER_44:
4574         case RTL_GIGA_MAC_VER_45:
4575         case RTL_GIGA_MAC_VER_46:
4576         case RTL_GIGA_MAC_VER_47:
4577         case RTL_GIGA_MAC_VER_48:
4578         case RTL_GIGA_MAC_VER_49:
4579         case RTL_GIGA_MAC_VER_50:
4580         case RTL_GIGA_MAC_VER_51:
4581                 ops->write      = r8168g_mdio_write;
4582                 ops->read       = r8168g_mdio_read;
4583                 break;
4584         default:
4585                 ops->write      = r8169_mdio_write;
4586                 ops->read       = r8169_mdio_read;
4587                 break;
4588         }
4589 }
4590
4591 static void rtl_speed_down(struct rtl8169_private *tp)
4592 {
4593         u32 adv;
4594         int lpa;
4595
4596         rtl_writephy(tp, 0x1f, 0x0000);
4597         lpa = rtl_readphy(tp, MII_LPA);
4598
4599         if (lpa & (LPA_10HALF | LPA_10FULL))
4600                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4601         else if (lpa & (LPA_100HALF | LPA_100FULL))
4602                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4603                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4604         else
4605                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4606                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4607                       (tp->mii.supports_gmii ?
4608                        ADVERTISED_1000baseT_Half |
4609                        ADVERTISED_1000baseT_Full : 0);
4610
4611         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4612                           adv);
4613 }
4614
4615 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4616 {
4617         void __iomem *ioaddr = tp->mmio_addr;
4618
4619         switch (tp->mac_version) {
4620         case RTL_GIGA_MAC_VER_25:
4621         case RTL_GIGA_MAC_VER_26:
4622         case RTL_GIGA_MAC_VER_29:
4623         case RTL_GIGA_MAC_VER_30:
4624         case RTL_GIGA_MAC_VER_32:
4625         case RTL_GIGA_MAC_VER_33:
4626         case RTL_GIGA_MAC_VER_34:
4627         case RTL_GIGA_MAC_VER_37:
4628         case RTL_GIGA_MAC_VER_38:
4629         case RTL_GIGA_MAC_VER_39:
4630         case RTL_GIGA_MAC_VER_40:
4631         case RTL_GIGA_MAC_VER_41:
4632         case RTL_GIGA_MAC_VER_42:
4633         case RTL_GIGA_MAC_VER_43:
4634         case RTL_GIGA_MAC_VER_44:
4635         case RTL_GIGA_MAC_VER_45:
4636         case RTL_GIGA_MAC_VER_46:
4637         case RTL_GIGA_MAC_VER_47:
4638         case RTL_GIGA_MAC_VER_48:
4639         case RTL_GIGA_MAC_VER_49:
4640         case RTL_GIGA_MAC_VER_50:
4641         case RTL_GIGA_MAC_VER_51:
4642                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4643                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4644                 break;
4645         default:
4646                 break;
4647         }
4648 }
4649
4650 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4651 {
4652         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4653                 return false;
4654
4655         rtl_speed_down(tp);
4656         rtl_wol_suspend_quirk(tp);
4657
4658         return true;
4659 }
4660
4661 static void r810x_phy_power_down(struct rtl8169_private *tp)
4662 {
4663         rtl_writephy(tp, 0x1f, 0x0000);
4664         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4665 }
4666
4667 static void r810x_phy_power_up(struct rtl8169_private *tp)
4668 {
4669         rtl_writephy(tp, 0x1f, 0x0000);
4670         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4671 }
4672
4673 static void r810x_pll_power_down(struct rtl8169_private *tp)
4674 {
4675         void __iomem *ioaddr = tp->mmio_addr;
4676
4677         if (rtl_wol_pll_power_down(tp))
4678                 return;
4679
4680         r810x_phy_power_down(tp);
4681
4682         switch (tp->mac_version) {
4683         case RTL_GIGA_MAC_VER_07:
4684         case RTL_GIGA_MAC_VER_08:
4685         case RTL_GIGA_MAC_VER_09:
4686         case RTL_GIGA_MAC_VER_10:
4687         case RTL_GIGA_MAC_VER_13:
4688         case RTL_GIGA_MAC_VER_16:
4689                 break;
4690         default:
4691                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4692                 break;
4693         }
4694 }
4695
4696 static void r810x_pll_power_up(struct rtl8169_private *tp)
4697 {
4698         void __iomem *ioaddr = tp->mmio_addr;
4699
4700         r810x_phy_power_up(tp);
4701
4702         switch (tp->mac_version) {
4703         case RTL_GIGA_MAC_VER_07:
4704         case RTL_GIGA_MAC_VER_08:
4705         case RTL_GIGA_MAC_VER_09:
4706         case RTL_GIGA_MAC_VER_10:
4707         case RTL_GIGA_MAC_VER_13:
4708         case RTL_GIGA_MAC_VER_16:
4709                 break;
4710         case RTL_GIGA_MAC_VER_47:
4711         case RTL_GIGA_MAC_VER_48:
4712                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4713                 break;
4714         default:
4715                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4716                 break;
4717         }
4718 }
4719
4720 static void r8168_phy_power_up(struct rtl8169_private *tp)
4721 {
4722         rtl_writephy(tp, 0x1f, 0x0000);
4723         switch (tp->mac_version) {
4724         case RTL_GIGA_MAC_VER_11:
4725         case RTL_GIGA_MAC_VER_12:
4726         case RTL_GIGA_MAC_VER_17:
4727         case RTL_GIGA_MAC_VER_18:
4728         case RTL_GIGA_MAC_VER_19:
4729         case RTL_GIGA_MAC_VER_20:
4730         case RTL_GIGA_MAC_VER_21:
4731         case RTL_GIGA_MAC_VER_22:
4732         case RTL_GIGA_MAC_VER_23:
4733         case RTL_GIGA_MAC_VER_24:
4734         case RTL_GIGA_MAC_VER_25:
4735         case RTL_GIGA_MAC_VER_26:
4736         case RTL_GIGA_MAC_VER_27:
4737         case RTL_GIGA_MAC_VER_28:
4738         case RTL_GIGA_MAC_VER_31:
4739                 rtl_writephy(tp, 0x0e, 0x0000);
4740                 break;
4741         default:
4742                 break;
4743         }
4744         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4745 }
4746
4747 static void r8168_phy_power_down(struct rtl8169_private *tp)
4748 {
4749         rtl_writephy(tp, 0x1f, 0x0000);
4750         switch (tp->mac_version) {
4751         case RTL_GIGA_MAC_VER_32:
4752         case RTL_GIGA_MAC_VER_33:
4753         case RTL_GIGA_MAC_VER_40:
4754         case RTL_GIGA_MAC_VER_41:
4755                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4756                 break;
4757
4758         case RTL_GIGA_MAC_VER_11:
4759         case RTL_GIGA_MAC_VER_12:
4760         case RTL_GIGA_MAC_VER_17:
4761         case RTL_GIGA_MAC_VER_18:
4762         case RTL_GIGA_MAC_VER_19:
4763         case RTL_GIGA_MAC_VER_20:
4764         case RTL_GIGA_MAC_VER_21:
4765         case RTL_GIGA_MAC_VER_22:
4766         case RTL_GIGA_MAC_VER_23:
4767         case RTL_GIGA_MAC_VER_24:
4768         case RTL_GIGA_MAC_VER_25:
4769         case RTL_GIGA_MAC_VER_26:
4770         case RTL_GIGA_MAC_VER_27:
4771         case RTL_GIGA_MAC_VER_28:
4772         case RTL_GIGA_MAC_VER_31:
4773                 rtl_writephy(tp, 0x0e, 0x0200);
4774         default:
4775                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4776                 break;
4777         }
4778 }
4779
4780 static void r8168_pll_power_down(struct rtl8169_private *tp)
4781 {
4782         void __iomem *ioaddr = tp->mmio_addr;
4783
4784         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4785              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4786              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4787              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4788              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4789              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4790             r8168_check_dash(tp)) {
4791                 return;
4792         }
4793
4794         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4795              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4796             (RTL_R16(CPlusCmd) & ASF)) {
4797                 return;
4798         }
4799
4800         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4801             tp->mac_version == RTL_GIGA_MAC_VER_33)
4802                 rtl_ephy_write(tp, 0x19, 0xff64);
4803
4804         if (rtl_wol_pll_power_down(tp))
4805                 return;
4806
4807         r8168_phy_power_down(tp);
4808
4809         switch (tp->mac_version) {
4810         case RTL_GIGA_MAC_VER_25:
4811         case RTL_GIGA_MAC_VER_26:
4812         case RTL_GIGA_MAC_VER_27:
4813         case RTL_GIGA_MAC_VER_28:
4814         case RTL_GIGA_MAC_VER_31:
4815         case RTL_GIGA_MAC_VER_32:
4816         case RTL_GIGA_MAC_VER_33:
4817         case RTL_GIGA_MAC_VER_44:
4818         case RTL_GIGA_MAC_VER_45:
4819         case RTL_GIGA_MAC_VER_46:
4820         case RTL_GIGA_MAC_VER_50:
4821         case RTL_GIGA_MAC_VER_51:
4822                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4823                 break;
4824         case RTL_GIGA_MAC_VER_40:
4825         case RTL_GIGA_MAC_VER_41:
4826         case RTL_GIGA_MAC_VER_49:
4827                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4828                              0xfc000000, ERIAR_EXGMAC);
4829                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4830                 break;
4831         }
4832 }
4833
4834 static void r8168_pll_power_up(struct rtl8169_private *tp)
4835 {
4836         void __iomem *ioaddr = tp->mmio_addr;
4837
4838         switch (tp->mac_version) {
4839         case RTL_GIGA_MAC_VER_25:
4840         case RTL_GIGA_MAC_VER_26:
4841         case RTL_GIGA_MAC_VER_27:
4842         case RTL_GIGA_MAC_VER_28:
4843         case RTL_GIGA_MAC_VER_31:
4844         case RTL_GIGA_MAC_VER_32:
4845         case RTL_GIGA_MAC_VER_33:
4846                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4847                 break;
4848         case RTL_GIGA_MAC_VER_44:
4849         case RTL_GIGA_MAC_VER_45:
4850         case RTL_GIGA_MAC_VER_46:
4851         case RTL_GIGA_MAC_VER_50:
4852         case RTL_GIGA_MAC_VER_51:
4853                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4854                 break;
4855         case RTL_GIGA_MAC_VER_40:
4856         case RTL_GIGA_MAC_VER_41:
4857         case RTL_GIGA_MAC_VER_49:
4858                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4859                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4860                              0x00000000, ERIAR_EXGMAC);
4861                 break;
4862         }
4863
4864         r8168_phy_power_up(tp);
4865 }
4866
4867 static void rtl_generic_op(struct rtl8169_private *tp,
4868                            void (*op)(struct rtl8169_private *))
4869 {
4870         if (op)
4871                 op(tp);
4872 }
4873
4874 static void rtl_pll_power_down(struct rtl8169_private *tp)
4875 {
4876         rtl_generic_op(tp, tp->pll_power_ops.down);
4877 }
4878
4879 static void rtl_pll_power_up(struct rtl8169_private *tp)
4880 {
4881         rtl_generic_op(tp, tp->pll_power_ops.up);
4882 }
4883
4884 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4885 {
4886         struct pll_power_ops *ops = &tp->pll_power_ops;
4887
4888         switch (tp->mac_version) {
4889         case RTL_GIGA_MAC_VER_07:
4890         case RTL_GIGA_MAC_VER_08:
4891         case RTL_GIGA_MAC_VER_09:
4892         case RTL_GIGA_MAC_VER_10:
4893         case RTL_GIGA_MAC_VER_16:
4894         case RTL_GIGA_MAC_VER_29:
4895         case RTL_GIGA_MAC_VER_30:
4896         case RTL_GIGA_MAC_VER_37:
4897         case RTL_GIGA_MAC_VER_39:
4898         case RTL_GIGA_MAC_VER_43:
4899         case RTL_GIGA_MAC_VER_47:
4900         case RTL_GIGA_MAC_VER_48:
4901                 ops->down       = r810x_pll_power_down;
4902                 ops->up         = r810x_pll_power_up;
4903                 break;
4904
4905         case RTL_GIGA_MAC_VER_11:
4906         case RTL_GIGA_MAC_VER_12:
4907         case RTL_GIGA_MAC_VER_17:
4908         case RTL_GIGA_MAC_VER_18:
4909         case RTL_GIGA_MAC_VER_19:
4910         case RTL_GIGA_MAC_VER_20:
4911         case RTL_GIGA_MAC_VER_21:
4912         case RTL_GIGA_MAC_VER_22:
4913         case RTL_GIGA_MAC_VER_23:
4914         case RTL_GIGA_MAC_VER_24:
4915         case RTL_GIGA_MAC_VER_25:
4916         case RTL_GIGA_MAC_VER_26:
4917         case RTL_GIGA_MAC_VER_27:
4918         case RTL_GIGA_MAC_VER_28:
4919         case RTL_GIGA_MAC_VER_31:
4920         case RTL_GIGA_MAC_VER_32:
4921         case RTL_GIGA_MAC_VER_33:
4922         case RTL_GIGA_MAC_VER_34:
4923         case RTL_GIGA_MAC_VER_35:
4924         case RTL_GIGA_MAC_VER_36:
4925         case RTL_GIGA_MAC_VER_38:
4926         case RTL_GIGA_MAC_VER_40:
4927         case RTL_GIGA_MAC_VER_41:
4928         case RTL_GIGA_MAC_VER_42:
4929         case RTL_GIGA_MAC_VER_44:
4930         case RTL_GIGA_MAC_VER_45:
4931         case RTL_GIGA_MAC_VER_46:
4932         case RTL_GIGA_MAC_VER_49:
4933         case RTL_GIGA_MAC_VER_50:
4934         case RTL_GIGA_MAC_VER_51:
4935                 ops->down       = r8168_pll_power_down;
4936                 ops->up         = r8168_pll_power_up;
4937                 break;
4938
4939         default:
4940                 ops->down       = NULL;
4941                 ops->up         = NULL;
4942                 break;
4943         }
4944 }
4945
4946 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4947 {
4948         void __iomem *ioaddr = tp->mmio_addr;
4949
4950         switch (tp->mac_version) {
4951         case RTL_GIGA_MAC_VER_01:
4952         case RTL_GIGA_MAC_VER_02:
4953         case RTL_GIGA_MAC_VER_03:
4954         case RTL_GIGA_MAC_VER_04:
4955         case RTL_GIGA_MAC_VER_05:
4956         case RTL_GIGA_MAC_VER_06:
4957         case RTL_GIGA_MAC_VER_10:
4958         case RTL_GIGA_MAC_VER_11:
4959         case RTL_GIGA_MAC_VER_12:
4960         case RTL_GIGA_MAC_VER_13:
4961         case RTL_GIGA_MAC_VER_14:
4962         case RTL_GIGA_MAC_VER_15:
4963         case RTL_GIGA_MAC_VER_16:
4964         case RTL_GIGA_MAC_VER_17:
4965                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4966                 break;
4967         case RTL_GIGA_MAC_VER_18:
4968         case RTL_GIGA_MAC_VER_19:
4969         case RTL_GIGA_MAC_VER_20:
4970         case RTL_GIGA_MAC_VER_21:
4971         case RTL_GIGA_MAC_VER_22:
4972         case RTL_GIGA_MAC_VER_23:
4973         case RTL_GIGA_MAC_VER_24:
4974         case RTL_GIGA_MAC_VER_34:
4975         case RTL_GIGA_MAC_VER_35:
4976                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4977                 break;
4978         case RTL_GIGA_MAC_VER_40:
4979                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4980                 break;
4981         case RTL_GIGA_MAC_VER_41:
4982         case RTL_GIGA_MAC_VER_42:
4983         case RTL_GIGA_MAC_VER_43:
4984         case RTL_GIGA_MAC_VER_44:
4985         case RTL_GIGA_MAC_VER_45:
4986         case RTL_GIGA_MAC_VER_46:
4987         case RTL_GIGA_MAC_VER_47:
4988         case RTL_GIGA_MAC_VER_48:
4989                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4990                 break;
4991         case RTL_GIGA_MAC_VER_49:
4992         case RTL_GIGA_MAC_VER_50:
4993         case RTL_GIGA_MAC_VER_51:
4994                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4995                 break;
4996         default:
4997                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4998                 break;
4999         }
5000 }
5001
5002 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5003 {
5004         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5005 }
5006
5007 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5008 {
5009         void __iomem *ioaddr = tp->mmio_addr;
5010
5011         RTL_W8(Cfg9346, Cfg9346_Unlock);
5012         rtl_generic_op(tp, tp->jumbo_ops.enable);
5013         RTL_W8(Cfg9346, Cfg9346_Lock);
5014 }
5015
5016 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5017 {
5018         void __iomem *ioaddr = tp->mmio_addr;
5019
5020         RTL_W8(Cfg9346, Cfg9346_Unlock);
5021         rtl_generic_op(tp, tp->jumbo_ops.disable);
5022         RTL_W8(Cfg9346, Cfg9346_Lock);
5023 }
5024
5025 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5026 {
5027         void __iomem *ioaddr = tp->mmio_addr;
5028
5029         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5030         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5031         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5032 }
5033
5034 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5035 {
5036         void __iomem *ioaddr = tp->mmio_addr;
5037
5038         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5039         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5040         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5041 }
5042
5043 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5044 {
5045         void __iomem *ioaddr = tp->mmio_addr;
5046
5047         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5048 }
5049
5050 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5051 {
5052         void __iomem *ioaddr = tp->mmio_addr;
5053
5054         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5055 }
5056
5057 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5058 {
5059         void __iomem *ioaddr = tp->mmio_addr;
5060
5061         RTL_W8(MaxTxPacketSize, 0x3f);
5062         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5063         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5064         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5065 }
5066
5067 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5068 {
5069         void __iomem *ioaddr = tp->mmio_addr;
5070
5071         RTL_W8(MaxTxPacketSize, 0x0c);
5072         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5073         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5074         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5075 }
5076
5077 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5078 {
5079         rtl_tx_performance_tweak(tp->pci_dev,
5080                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5081 }
5082
5083 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5084 {
5085         rtl_tx_performance_tweak(tp->pci_dev,
5086                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5087 }
5088
5089 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5090 {
5091         void __iomem *ioaddr = tp->mmio_addr;
5092
5093         r8168b_0_hw_jumbo_enable(tp);
5094
5095         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5096 }
5097
5098 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5099 {
5100         void __iomem *ioaddr = tp->mmio_addr;
5101
5102         r8168b_0_hw_jumbo_disable(tp);
5103
5104         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5105 }
5106
5107 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5108 {
5109         struct jumbo_ops *ops = &tp->jumbo_ops;
5110
5111         switch (tp->mac_version) {
5112         case RTL_GIGA_MAC_VER_11:
5113                 ops->disable    = r8168b_0_hw_jumbo_disable;
5114                 ops->enable     = r8168b_0_hw_jumbo_enable;
5115                 break;
5116         case RTL_GIGA_MAC_VER_12:
5117         case RTL_GIGA_MAC_VER_17:
5118                 ops->disable    = r8168b_1_hw_jumbo_disable;
5119                 ops->enable     = r8168b_1_hw_jumbo_enable;
5120                 break;
5121         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5122         case RTL_GIGA_MAC_VER_19:
5123         case RTL_GIGA_MAC_VER_20:
5124         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5125         case RTL_GIGA_MAC_VER_22:
5126         case RTL_GIGA_MAC_VER_23:
5127         case RTL_GIGA_MAC_VER_24:
5128         case RTL_GIGA_MAC_VER_25:
5129         case RTL_GIGA_MAC_VER_26:
5130                 ops->disable    = r8168c_hw_jumbo_disable;
5131                 ops->enable     = r8168c_hw_jumbo_enable;
5132                 break;
5133         case RTL_GIGA_MAC_VER_27:
5134         case RTL_GIGA_MAC_VER_28:
5135                 ops->disable    = r8168dp_hw_jumbo_disable;
5136                 ops->enable     = r8168dp_hw_jumbo_enable;
5137                 break;
5138         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5139         case RTL_GIGA_MAC_VER_32:
5140         case RTL_GIGA_MAC_VER_33:
5141         case RTL_GIGA_MAC_VER_34:
5142                 ops->disable    = r8168e_hw_jumbo_disable;
5143                 ops->enable     = r8168e_hw_jumbo_enable;
5144                 break;
5145
5146         /*
5147          * No action needed for jumbo frames with 8169.
5148          * No jumbo for 810x at all.
5149          */
5150         case RTL_GIGA_MAC_VER_40:
5151         case RTL_GIGA_MAC_VER_41:
5152         case RTL_GIGA_MAC_VER_42:
5153         case RTL_GIGA_MAC_VER_43:
5154         case RTL_GIGA_MAC_VER_44:
5155         case RTL_GIGA_MAC_VER_45:
5156         case RTL_GIGA_MAC_VER_46:
5157         case RTL_GIGA_MAC_VER_47:
5158         case RTL_GIGA_MAC_VER_48:
5159         case RTL_GIGA_MAC_VER_49:
5160         case RTL_GIGA_MAC_VER_50:
5161         case RTL_GIGA_MAC_VER_51:
5162         default:
5163                 ops->disable    = NULL;
5164                 ops->enable     = NULL;
5165                 break;
5166         }
5167 }
5168
5169 DECLARE_RTL_COND(rtl_chipcmd_cond)
5170 {
5171         void __iomem *ioaddr = tp->mmio_addr;
5172
5173         return RTL_R8(ChipCmd) & CmdReset;
5174 }
5175
5176 static void rtl_hw_reset(struct rtl8169_private *tp)
5177 {
5178         void __iomem *ioaddr = tp->mmio_addr;
5179
5180         RTL_W8(ChipCmd, CmdReset);
5181
5182         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5183 }
5184
5185 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5186 {
5187         struct rtl_fw *rtl_fw;
5188         const char *name;
5189         int rc = -ENOMEM;
5190
5191         name = rtl_lookup_firmware_name(tp);
5192         if (!name)
5193                 goto out_no_firmware;
5194
5195         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5196         if (!rtl_fw)
5197                 goto err_warn;
5198
5199         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5200         if (rc < 0)
5201                 goto err_free;
5202
5203         rc = rtl_check_firmware(tp, rtl_fw);
5204         if (rc < 0)
5205                 goto err_release_firmware;
5206
5207         tp->rtl_fw = rtl_fw;
5208 out:
5209         return;
5210
5211 err_release_firmware:
5212         release_firmware(rtl_fw->fw);
5213 err_free:
5214         kfree(rtl_fw);
5215 err_warn:
5216         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5217                    name, rc);
5218 out_no_firmware:
5219         tp->rtl_fw = NULL;
5220         goto out;
5221 }
5222
5223 static void rtl_request_firmware(struct rtl8169_private *tp)
5224 {
5225         if (IS_ERR(tp->rtl_fw))
5226                 rtl_request_uncached_firmware(tp);
5227 }
5228
5229 static void rtl_rx_close(struct rtl8169_private *tp)
5230 {
5231         void __iomem *ioaddr = tp->mmio_addr;
5232
5233         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5234 }
5235
5236 DECLARE_RTL_COND(rtl_npq_cond)
5237 {
5238         void __iomem *ioaddr = tp->mmio_addr;
5239
5240         return RTL_R8(TxPoll) & NPQ;
5241 }
5242
5243 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5244 {
5245         void __iomem *ioaddr = tp->mmio_addr;
5246
5247         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5248 }
5249
5250 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5251 {
5252         void __iomem *ioaddr = tp->mmio_addr;
5253
5254         /* Disable interrupts */
5255         rtl8169_irq_mask_and_ack(tp);
5256
5257         rtl_rx_close(tp);
5258
5259         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5260             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5261             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5262                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5263         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5264                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5265                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5266                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5267                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5268                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5269                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5270                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5271                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5272                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5273                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5274                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5275                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5276                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5277                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5278                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5279                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5280                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5281                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5282         } else {
5283                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5284                 udelay(100);
5285         }
5286
5287         rtl_hw_reset(tp);
5288 }
5289
5290 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5291 {
5292         void __iomem *ioaddr = tp->mmio_addr;
5293
5294         /* Set DMA burst size and Interframe Gap Time */
5295         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5296                 (InterFrameGap << TxInterFrameGapShift));
5297 }
5298
5299 static void rtl_hw_start(struct net_device *dev)
5300 {
5301         struct rtl8169_private *tp = netdev_priv(dev);
5302
5303         tp->hw_start(dev);
5304
5305         rtl_irq_enable_all(tp);
5306 }
5307
5308 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5309                                          void __iomem *ioaddr)
5310 {
5311         /*
5312          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5313          * register to be written before TxDescAddrLow to work.
5314          * Switching from MMIO to I/O access fixes the issue as well.
5315          */
5316         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5317         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5318         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5319         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5320 }
5321
5322 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5323 {
5324         u16 cmd;
5325
5326         cmd = RTL_R16(CPlusCmd);
5327         RTL_W16(CPlusCmd, cmd);
5328         return cmd;
5329 }
5330
5331 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5332 {
5333         /* Low hurts. Let's disable the filtering. */
5334         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5335 }
5336
5337 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5338 {
5339         static const struct rtl_cfg2_info {
5340                 u32 mac_version;
5341                 u32 clk;
5342                 u32 val;
5343         } cfg2_info [] = {
5344                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5345                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5346                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5347                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5348         };
5349         const struct rtl_cfg2_info *p = cfg2_info;
5350         unsigned int i;
5351         u32 clk;
5352
5353         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5354         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5355                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5356                         RTL_W32(0x7c, p->val);
5357                         break;
5358                 }
5359         }
5360 }
5361
5362 static void rtl_set_rx_mode(struct net_device *dev)
5363 {
5364         struct rtl8169_private *tp = netdev_priv(dev);
5365         void __iomem *ioaddr = tp->mmio_addr;
5366         u32 mc_filter[2];       /* Multicast hash filter */
5367         int rx_mode;
5368         u32 tmp = 0;
5369
5370         if (dev->flags & IFF_PROMISC) {
5371                 /* Unconditionally log net taps. */
5372                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5373                 rx_mode =
5374                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5375                     AcceptAllPhys;
5376                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5377         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5378                    (dev->flags & IFF_ALLMULTI)) {
5379                 /* Too many to filter perfectly -- accept all multicasts. */
5380                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5381                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5382         } else {
5383                 struct netdev_hw_addr *ha;
5384
5385                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5386                 mc_filter[1] = mc_filter[0] = 0;
5387                 netdev_for_each_mc_addr(ha, dev) {
5388                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5389                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5390                         rx_mode |= AcceptMulticast;
5391                 }
5392         }
5393
5394         if (dev->features & NETIF_F_RXALL)
5395                 rx_mode |= (AcceptErr | AcceptRunt);
5396
5397         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5398
5399         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5400                 u32 data = mc_filter[0];
5401
5402                 mc_filter[0] = swab32(mc_filter[1]);
5403                 mc_filter[1] = swab32(data);
5404         }
5405
5406         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5407                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5408
5409         RTL_W32(MAR0 + 4, mc_filter[1]);
5410         RTL_W32(MAR0 + 0, mc_filter[0]);
5411
5412         RTL_W32(RxConfig, tmp);
5413 }
5414
5415 static void rtl_hw_start_8169(struct net_device *dev)
5416 {
5417         struct rtl8169_private *tp = netdev_priv(dev);
5418         void __iomem *ioaddr = tp->mmio_addr;
5419         struct pci_dev *pdev = tp->pci_dev;
5420
5421         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5422                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5423                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5424         }
5425
5426         RTL_W8(Cfg9346, Cfg9346_Unlock);
5427         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5428             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5429             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5430             tp->mac_version == RTL_GIGA_MAC_VER_04)
5431                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5432
5433         rtl_init_rxcfg(tp);
5434
5435         RTL_W8(EarlyTxThres, NoEarlyTx);
5436
5437         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5438
5439         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5440             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5441             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5442             tp->mac_version == RTL_GIGA_MAC_VER_04)
5443                 rtl_set_rx_tx_config_registers(tp);
5444
5445         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5446
5447         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5448             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5449                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5450                         "Bit-3 and bit-14 MUST be 1\n");
5451                 tp->cp_cmd |= (1 << 14);
5452         }
5453
5454         RTL_W16(CPlusCmd, tp->cp_cmd);
5455
5456         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5457
5458         /*
5459          * Undocumented corner. Supposedly:
5460          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5461          */
5462         RTL_W16(IntrMitigate, 0x0000);
5463
5464         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5465
5466         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5467             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5468             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5469             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5470                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5471                 rtl_set_rx_tx_config_registers(tp);
5472         }
5473
5474         RTL_W8(Cfg9346, Cfg9346_Lock);
5475
5476         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5477         RTL_R8(IntrMask);
5478
5479         RTL_W32(RxMissed, 0);
5480
5481         rtl_set_rx_mode(dev);
5482
5483         /* no early-rx interrupts */
5484         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5485 }
5486
5487 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5488 {
5489         if (tp->csi_ops.write)
5490                 tp->csi_ops.write(tp, addr, value);
5491 }
5492
5493 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5494 {
5495         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5496 }
5497
5498 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5499 {
5500         u32 csi;
5501
5502         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5503         rtl_csi_write(tp, 0x070c, csi | bits);
5504 }
5505
5506 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5507 {
5508         rtl_csi_access_enable(tp, 0x17000000);
5509 }
5510
5511 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5512 {
5513         rtl_csi_access_enable(tp, 0x27000000);
5514 }
5515
5516 DECLARE_RTL_COND(rtl_csiar_cond)
5517 {
5518         void __iomem *ioaddr = tp->mmio_addr;
5519
5520         return RTL_R32(CSIAR) & CSIAR_FLAG;
5521 }
5522
5523 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5524 {
5525         void __iomem *ioaddr = tp->mmio_addr;
5526
5527         RTL_W32(CSIDR, value);
5528         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5529                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5530
5531         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5532 }
5533
5534 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5535 {
5536         void __iomem *ioaddr = tp->mmio_addr;
5537
5538         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5539                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5540
5541         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5542                 RTL_R32(CSIDR) : ~0;
5543 }
5544
5545 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5546 {
5547         void __iomem *ioaddr = tp->mmio_addr;
5548
5549         RTL_W32(CSIDR, value);
5550         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5551                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5552                 CSIAR_FUNC_NIC);
5553
5554         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5555 }
5556
5557 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5558 {
5559         void __iomem *ioaddr = tp->mmio_addr;
5560
5561         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5562                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5563
5564         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5565                 RTL_R32(CSIDR) : ~0;
5566 }
5567
5568 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5569 {
5570         void __iomem *ioaddr = tp->mmio_addr;
5571
5572         RTL_W32(CSIDR, value);
5573         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5574                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5575                 CSIAR_FUNC_NIC2);
5576
5577         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5578 }
5579
5580 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5581 {
5582         void __iomem *ioaddr = tp->mmio_addr;
5583
5584         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5585                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5586
5587         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5588                 RTL_R32(CSIDR) : ~0;
5589 }
5590
5591 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5592 {
5593         struct csi_ops *ops = &tp->csi_ops;
5594
5595         switch (tp->mac_version) {
5596         case RTL_GIGA_MAC_VER_01:
5597         case RTL_GIGA_MAC_VER_02:
5598         case RTL_GIGA_MAC_VER_03:
5599         case RTL_GIGA_MAC_VER_04:
5600         case RTL_GIGA_MAC_VER_05:
5601         case RTL_GIGA_MAC_VER_06:
5602         case RTL_GIGA_MAC_VER_10:
5603         case RTL_GIGA_MAC_VER_11:
5604         case RTL_GIGA_MAC_VER_12:
5605         case RTL_GIGA_MAC_VER_13:
5606         case RTL_GIGA_MAC_VER_14:
5607         case RTL_GIGA_MAC_VER_15:
5608         case RTL_GIGA_MAC_VER_16:
5609         case RTL_GIGA_MAC_VER_17:
5610                 ops->write      = NULL;
5611                 ops->read       = NULL;
5612                 break;
5613
5614         case RTL_GIGA_MAC_VER_37:
5615         case RTL_GIGA_MAC_VER_38:
5616                 ops->write      = r8402_csi_write;
5617                 ops->read       = r8402_csi_read;
5618                 break;
5619
5620         case RTL_GIGA_MAC_VER_44:
5621                 ops->write      = r8411_csi_write;
5622                 ops->read       = r8411_csi_read;
5623                 break;
5624
5625         default:
5626                 ops->write      = r8169_csi_write;
5627                 ops->read       = r8169_csi_read;
5628                 break;
5629         }
5630 }
5631
5632 struct ephy_info {
5633         unsigned int offset;
5634         u16 mask;
5635         u16 bits;
5636 };
5637
5638 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5639                           int len)
5640 {
5641         u16 w;
5642
5643         while (len-- > 0) {
5644                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5645                 rtl_ephy_write(tp, e->offset, w);
5646                 e++;
5647         }
5648 }
5649
5650 static void rtl_disable_clock_request(struct pci_dev *pdev)
5651 {
5652         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5653                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5654 }
5655
5656 static void rtl_enable_clock_request(struct pci_dev *pdev)
5657 {
5658         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5659                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5660 }
5661
5662 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5663 {
5664         void __iomem *ioaddr = tp->mmio_addr;
5665         u8 data;
5666
5667         data = RTL_R8(Config3);
5668
5669         if (enable)
5670                 data |= Rdy_to_L23;
5671         else
5672                 data &= ~Rdy_to_L23;
5673
5674         RTL_W8(Config3, data);
5675 }
5676
5677 #define R8168_CPCMD_QUIRK_MASK (\
5678         EnableBist | \
5679         Mac_dbgo_oe | \
5680         Force_half_dup | \
5681         Force_rxflow_en | \
5682         Force_txflow_en | \
5683         Cxpl_dbg_sel | \
5684         ASF | \
5685         PktCntrDisable | \
5686         Mac_dbgo_sel)
5687
5688 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5689 {
5690         void __iomem *ioaddr = tp->mmio_addr;
5691         struct pci_dev *pdev = tp->pci_dev;
5692
5693         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5694
5695         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5696
5697         if (tp->dev->mtu <= ETH_DATA_LEN) {
5698                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5699                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5700         }
5701 }
5702
5703 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5704 {
5705         void __iomem *ioaddr = tp->mmio_addr;
5706
5707         rtl_hw_start_8168bb(tp);
5708
5709         RTL_W8(MaxTxPacketSize, TxPacketMax);
5710
5711         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5712 }
5713
5714 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5715 {
5716         void __iomem *ioaddr = tp->mmio_addr;
5717         struct pci_dev *pdev = tp->pci_dev;
5718
5719         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5720
5721         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5722
5723         if (tp->dev->mtu <= ETH_DATA_LEN)
5724                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5725
5726         rtl_disable_clock_request(pdev);
5727
5728         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5729 }
5730
5731 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5732 {
5733         static const struct ephy_info e_info_8168cp[] = {
5734                 { 0x01, 0,      0x0001 },
5735                 { 0x02, 0x0800, 0x1000 },
5736                 { 0x03, 0,      0x0042 },
5737                 { 0x06, 0x0080, 0x0000 },
5738                 { 0x07, 0,      0x2000 }
5739         };
5740
5741         rtl_csi_access_enable_2(tp);
5742
5743         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5744
5745         __rtl_hw_start_8168cp(tp);
5746 }
5747
5748 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5749 {
5750         void __iomem *ioaddr = tp->mmio_addr;
5751         struct pci_dev *pdev = tp->pci_dev;
5752
5753         rtl_csi_access_enable_2(tp);
5754
5755         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5756
5757         if (tp->dev->mtu <= ETH_DATA_LEN)
5758                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5759
5760         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5761 }
5762
5763 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5764 {
5765         void __iomem *ioaddr = tp->mmio_addr;
5766         struct pci_dev *pdev = tp->pci_dev;
5767
5768         rtl_csi_access_enable_2(tp);
5769
5770         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5771
5772         /* Magic. */
5773         RTL_W8(DBG_REG, 0x20);
5774
5775         RTL_W8(MaxTxPacketSize, TxPacketMax);
5776
5777         if (tp->dev->mtu <= ETH_DATA_LEN)
5778                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5779
5780         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5781 }
5782
5783 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5784 {
5785         void __iomem *ioaddr = tp->mmio_addr;
5786         static const struct ephy_info e_info_8168c_1[] = {
5787                 { 0x02, 0x0800, 0x1000 },
5788                 { 0x03, 0,      0x0002 },
5789                 { 0x06, 0x0080, 0x0000 }
5790         };
5791
5792         rtl_csi_access_enable_2(tp);
5793
5794         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5795
5796         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5797
5798         __rtl_hw_start_8168cp(tp);
5799 }
5800
5801 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5802 {
5803         static const struct ephy_info e_info_8168c_2[] = {
5804                 { 0x01, 0,      0x0001 },
5805                 { 0x03, 0x0400, 0x0220 }
5806         };
5807
5808         rtl_csi_access_enable_2(tp);
5809
5810         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5811
5812         __rtl_hw_start_8168cp(tp);
5813 }
5814
5815 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5816 {
5817         rtl_hw_start_8168c_2(tp);
5818 }
5819
5820 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5821 {
5822         rtl_csi_access_enable_2(tp);
5823
5824         __rtl_hw_start_8168cp(tp);
5825 }
5826
5827 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5828 {
5829         void __iomem *ioaddr = tp->mmio_addr;
5830         struct pci_dev *pdev = tp->pci_dev;
5831
5832         rtl_csi_access_enable_2(tp);
5833
5834         rtl_disable_clock_request(pdev);
5835
5836         RTL_W8(MaxTxPacketSize, TxPacketMax);
5837
5838         if (tp->dev->mtu <= ETH_DATA_LEN)
5839                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5840
5841         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5842 }
5843
5844 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5845 {
5846         void __iomem *ioaddr = tp->mmio_addr;
5847         struct pci_dev *pdev = tp->pci_dev;
5848
5849         rtl_csi_access_enable_1(tp);
5850
5851         if (tp->dev->mtu <= ETH_DATA_LEN)
5852                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5853
5854         RTL_W8(MaxTxPacketSize, TxPacketMax);
5855
5856         rtl_disable_clock_request(pdev);
5857 }
5858
5859 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5860 {
5861         void __iomem *ioaddr = tp->mmio_addr;
5862         struct pci_dev *pdev = tp->pci_dev;
5863         static const struct ephy_info e_info_8168d_4[] = {
5864                 { 0x0b, ~0,     0x48 },
5865                 { 0x19, 0x20,   0x50 },
5866                 { 0x0c, ~0,     0x20 }
5867         };
5868         int i;
5869
5870         rtl_csi_access_enable_1(tp);
5871
5872         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5873
5874         RTL_W8(MaxTxPacketSize, TxPacketMax);
5875
5876         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5877                 const struct ephy_info *e = e_info_8168d_4 + i;
5878                 u16 w;
5879
5880                 w = rtl_ephy_read(tp, e->offset);
5881                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5882         }
5883
5884         rtl_enable_clock_request(pdev);
5885 }
5886
5887 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5888 {
5889         void __iomem *ioaddr = tp->mmio_addr;
5890         struct pci_dev *pdev = tp->pci_dev;
5891         static const struct ephy_info e_info_8168e_1[] = {
5892                 { 0x00, 0x0200, 0x0100 },
5893                 { 0x00, 0x0000, 0x0004 },
5894                 { 0x06, 0x0002, 0x0001 },
5895                 { 0x06, 0x0000, 0x0030 },
5896                 { 0x07, 0x0000, 0x2000 },
5897                 { 0x00, 0x0000, 0x0020 },
5898                 { 0x03, 0x5800, 0x2000 },
5899                 { 0x03, 0x0000, 0x0001 },
5900                 { 0x01, 0x0800, 0x1000 },
5901                 { 0x07, 0x0000, 0x4000 },
5902                 { 0x1e, 0x0000, 0x2000 },
5903                 { 0x19, 0xffff, 0xfe6c },
5904                 { 0x0a, 0x0000, 0x0040 }
5905         };
5906
5907         rtl_csi_access_enable_2(tp);
5908
5909         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5910
5911         if (tp->dev->mtu <= ETH_DATA_LEN)
5912                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5913
5914         RTL_W8(MaxTxPacketSize, TxPacketMax);
5915
5916         rtl_disable_clock_request(pdev);
5917
5918         /* Reset tx FIFO pointer */
5919         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5920         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5921
5922         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5923 }
5924
5925 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5926 {
5927         void __iomem *ioaddr = tp->mmio_addr;
5928         struct pci_dev *pdev = tp->pci_dev;
5929         static const struct ephy_info e_info_8168e_2[] = {
5930                 { 0x09, 0x0000, 0x0080 },
5931                 { 0x19, 0x0000, 0x0224 }
5932         };
5933
5934         rtl_csi_access_enable_1(tp);
5935
5936         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5937
5938         if (tp->dev->mtu <= ETH_DATA_LEN)
5939                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5940
5941         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5942         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5943         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5944         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5945         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5946         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5947         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5948         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5949
5950         RTL_W8(MaxTxPacketSize, EarlySize);
5951
5952         rtl_disable_clock_request(pdev);
5953
5954         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5955         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5956
5957         /* Adjust EEE LED frequency */
5958         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5959
5960         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5961         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5962         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5963 }
5964
5965 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5966 {
5967         void __iomem *ioaddr = tp->mmio_addr;
5968         struct pci_dev *pdev = tp->pci_dev;
5969
5970         rtl_csi_access_enable_2(tp);
5971
5972         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5973
5974         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5975         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5976         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5977         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5978         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5979         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5980         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5981         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5982         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5983         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5984
5985         RTL_W8(MaxTxPacketSize, EarlySize);
5986
5987         rtl_disable_clock_request(pdev);
5988
5989         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5990         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5991         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5992         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5993         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5994 }
5995
5996 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5997 {
5998         void __iomem *ioaddr = tp->mmio_addr;
5999         static const struct ephy_info e_info_8168f_1[] = {
6000                 { 0x06, 0x00c0, 0x0020 },
6001                 { 0x08, 0x0001, 0x0002 },
6002                 { 0x09, 0x0000, 0x0080 },
6003                 { 0x19, 0x0000, 0x0224 }
6004         };
6005
6006         rtl_hw_start_8168f(tp);
6007
6008         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6009
6010         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6011
6012         /* Adjust EEE LED frequency */
6013         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6014 }
6015
6016 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6017 {
6018         static const struct ephy_info e_info_8168f_1[] = {
6019                 { 0x06, 0x00c0, 0x0020 },
6020                 { 0x0f, 0xffff, 0x5200 },
6021                 { 0x1e, 0x0000, 0x4000 },
6022                 { 0x19, 0x0000, 0x0224 }
6023         };
6024
6025         rtl_hw_start_8168f(tp);
6026         rtl_pcie_state_l2l3_enable(tp, false);
6027
6028         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6029
6030         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6031 }
6032
6033 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6034 {
6035         void __iomem *ioaddr = tp->mmio_addr;
6036         struct pci_dev *pdev = tp->pci_dev;
6037
6038         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6039
6040         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6041         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6042         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6043         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6044
6045         rtl_csi_access_enable_1(tp);
6046
6047         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6048
6049         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6050         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6051         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6052
6053         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6054         RTL_W8(MaxTxPacketSize, EarlySize);
6055
6056         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6057         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6058
6059         /* Adjust EEE LED frequency */
6060         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6061
6062         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6063         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6064
6065         rtl_pcie_state_l2l3_enable(tp, false);
6066 }
6067
6068 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6069 {
6070         void __iomem *ioaddr = tp->mmio_addr;
6071         static const struct ephy_info e_info_8168g_1[] = {
6072                 { 0x00, 0x0000, 0x0008 },
6073                 { 0x0c, 0x37d0, 0x0820 },
6074                 { 0x1e, 0x0000, 0x0001 },
6075                 { 0x19, 0x8000, 0x0000 }
6076         };
6077
6078         rtl_hw_start_8168g(tp);
6079
6080         /* disable aspm and clock request before access ephy */
6081         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6082         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6083         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6084 }
6085
6086 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6087 {
6088         void __iomem *ioaddr = tp->mmio_addr;
6089         static const struct ephy_info e_info_8168g_2[] = {
6090                 { 0x00, 0x0000, 0x0008 },
6091                 { 0x0c, 0x3df0, 0x0200 },
6092                 { 0x19, 0xffff, 0xfc00 },
6093                 { 0x1e, 0xffff, 0x20eb }
6094         };
6095
6096         rtl_hw_start_8168g(tp);
6097
6098         /* disable aspm and clock request before access ephy */
6099         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6100         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6101         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6102 }
6103
6104 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6105 {
6106         void __iomem *ioaddr = tp->mmio_addr;
6107         static const struct ephy_info e_info_8411_2[] = {
6108                 { 0x00, 0x0000, 0x0008 },
6109                 { 0x0c, 0x3df0, 0x0200 },
6110                 { 0x0f, 0xffff, 0x5200 },
6111                 { 0x19, 0x0020, 0x0000 },
6112                 { 0x1e, 0x0000, 0x2000 }
6113         };
6114
6115         rtl_hw_start_8168g(tp);
6116
6117         /* disable aspm and clock request before access ephy */
6118         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6119         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6120         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6121 }
6122
6123 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6124 {
6125         void __iomem *ioaddr = tp->mmio_addr;
6126         struct pci_dev *pdev = tp->pci_dev;
6127         u16 rg_saw_cnt;
6128         u32 data;
6129         static const struct ephy_info e_info_8168h_1[] = {
6130                 { 0x1e, 0x0800, 0x0001 },
6131                 { 0x1d, 0x0000, 0x0800 },
6132                 { 0x05, 0xffff, 0x2089 },
6133                 { 0x06, 0xffff, 0x5881 },
6134                 { 0x04, 0xffff, 0x154a },
6135                 { 0x01, 0xffff, 0x068b }
6136         };
6137
6138         /* disable aspm and clock request before access ephy */
6139         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6140         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6141         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6142
6143         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6144
6145         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6146         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6147         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6148         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6149
6150         rtl_csi_access_enable_1(tp);
6151
6152         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6153
6154         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6155         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6156
6157         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6158
6159         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6160
6161         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6162
6163         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6164         RTL_W8(MaxTxPacketSize, EarlySize);
6165
6166         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6167         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6168
6169         /* Adjust EEE LED frequency */
6170         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6171
6172         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6173         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6174
6175         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6176
6177         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6178
6179         rtl_pcie_state_l2l3_enable(tp, false);
6180
6181         rtl_writephy(tp, 0x1f, 0x0c42);
6182         rg_saw_cnt = rtl_readphy(tp, 0x13);
6183         rtl_writephy(tp, 0x1f, 0x0000);
6184         if (rg_saw_cnt > 0) {
6185                 u16 sw_cnt_1ms_ini;
6186
6187                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6188                 sw_cnt_1ms_ini &= 0x0fff;
6189                 data = r8168_mac_ocp_read(tp, 0xd412);
6190                 data &= 0x0fff;
6191                 data |= sw_cnt_1ms_ini;
6192                 r8168_mac_ocp_write(tp, 0xd412, data);
6193         }
6194
6195         data = r8168_mac_ocp_read(tp, 0xe056);
6196         data &= 0xf0;
6197         data |= 0x07;
6198         r8168_mac_ocp_write(tp, 0xe056, data);
6199
6200         data = r8168_mac_ocp_read(tp, 0xe052);
6201         data &= 0x8008;
6202         data |= 0x6000;
6203         r8168_mac_ocp_write(tp, 0xe052, data);
6204
6205         data = r8168_mac_ocp_read(tp, 0xe0d6);
6206         data &= 0x01ff;
6207         data |= 0x017f;
6208         r8168_mac_ocp_write(tp, 0xe0d6, data);
6209
6210         data = r8168_mac_ocp_read(tp, 0xd420);
6211         data &= 0x0fff;
6212         data |= 0x047f;
6213         r8168_mac_ocp_write(tp, 0xd420, data);
6214
6215         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6216         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6217         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6218         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6219 }
6220
6221 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6222 {
6223         void __iomem *ioaddr = tp->mmio_addr;
6224         struct pci_dev *pdev = tp->pci_dev;
6225
6226         rtl8168ep_stop_cmac(tp);
6227
6228         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6229
6230         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6231         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6232         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6233         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6234
6235         rtl_csi_access_enable_1(tp);
6236
6237         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6238
6239         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6240         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6241
6242         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6243
6244         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6245
6246         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6247         RTL_W8(MaxTxPacketSize, EarlySize);
6248
6249         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6250         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6251
6252         /* Adjust EEE LED frequency */
6253         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6254
6255         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6256
6257         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6258
6259         rtl_pcie_state_l2l3_enable(tp, false);
6260 }
6261
6262 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6263 {
6264         void __iomem *ioaddr = tp->mmio_addr;
6265         static const struct ephy_info e_info_8168ep_1[] = {
6266                 { 0x00, 0xffff, 0x10ab },
6267                 { 0x06, 0xffff, 0xf030 },
6268                 { 0x08, 0xffff, 0x2006 },
6269                 { 0x0d, 0xffff, 0x1666 },
6270                 { 0x0c, 0x3ff0, 0x0000 }
6271         };
6272
6273         /* disable aspm and clock request before access ephy */
6274         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6275         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6276         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6277
6278         rtl_hw_start_8168ep(tp);
6279 }
6280
6281 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6282 {
6283         void __iomem *ioaddr = tp->mmio_addr;
6284         static const struct ephy_info e_info_8168ep_2[] = {
6285                 { 0x00, 0xffff, 0x10a3 },
6286                 { 0x19, 0xffff, 0xfc00 },
6287                 { 0x1e, 0xffff, 0x20ea }
6288         };
6289
6290         /* disable aspm and clock request before access ephy */
6291         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6292         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6293         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6294
6295         rtl_hw_start_8168ep(tp);
6296
6297         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6298         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6299 }
6300
6301 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6302 {
6303         void __iomem *ioaddr = tp->mmio_addr;
6304         u32 data;
6305         static const struct ephy_info e_info_8168ep_3[] = {
6306                 { 0x00, 0xffff, 0x10a3 },
6307                 { 0x19, 0xffff, 0x7c00 },
6308                 { 0x1e, 0xffff, 0x20eb },
6309                 { 0x0d, 0xffff, 0x1666 }
6310         };
6311
6312         /* disable aspm and clock request before access ephy */
6313         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6314         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6315         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6316
6317         rtl_hw_start_8168ep(tp);
6318
6319         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6320         RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6321
6322         data = r8168_mac_ocp_read(tp, 0xd3e2);
6323         data &= 0xf000;
6324         data |= 0x0271;
6325         r8168_mac_ocp_write(tp, 0xd3e2, data);
6326
6327         data = r8168_mac_ocp_read(tp, 0xd3e4);
6328         data &= 0xff00;
6329         r8168_mac_ocp_write(tp, 0xd3e4, data);
6330
6331         data = r8168_mac_ocp_read(tp, 0xe860);
6332         data |= 0x0080;
6333         r8168_mac_ocp_write(tp, 0xe860, data);
6334 }
6335
6336 static void rtl_hw_start_8168(struct net_device *dev)
6337 {
6338         struct rtl8169_private *tp = netdev_priv(dev);
6339         void __iomem *ioaddr = tp->mmio_addr;
6340
6341         RTL_W8(Cfg9346, Cfg9346_Unlock);
6342
6343         RTL_W8(MaxTxPacketSize, TxPacketMax);
6344
6345         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6346
6347         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6348
6349         RTL_W16(CPlusCmd, tp->cp_cmd);
6350
6351         RTL_W16(IntrMitigate, 0x5151);
6352
6353         /* Work around for RxFIFO overflow. */
6354         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6355                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6356                 tp->event_slow &= ~RxOverflow;
6357         }
6358
6359         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6360
6361         rtl_set_rx_tx_config_registers(tp);
6362
6363         RTL_R8(IntrMask);
6364
6365         switch (tp->mac_version) {
6366         case RTL_GIGA_MAC_VER_11:
6367                 rtl_hw_start_8168bb(tp);
6368                 break;
6369
6370         case RTL_GIGA_MAC_VER_12:
6371         case RTL_GIGA_MAC_VER_17:
6372                 rtl_hw_start_8168bef(tp);
6373                 break;
6374
6375         case RTL_GIGA_MAC_VER_18:
6376                 rtl_hw_start_8168cp_1(tp);
6377                 break;
6378
6379         case RTL_GIGA_MAC_VER_19:
6380                 rtl_hw_start_8168c_1(tp);
6381                 break;
6382
6383         case RTL_GIGA_MAC_VER_20:
6384                 rtl_hw_start_8168c_2(tp);
6385                 break;
6386
6387         case RTL_GIGA_MAC_VER_21:
6388                 rtl_hw_start_8168c_3(tp);
6389                 break;
6390
6391         case RTL_GIGA_MAC_VER_22:
6392                 rtl_hw_start_8168c_4(tp);
6393                 break;
6394
6395         case RTL_GIGA_MAC_VER_23:
6396                 rtl_hw_start_8168cp_2(tp);
6397                 break;
6398
6399         case RTL_GIGA_MAC_VER_24:
6400                 rtl_hw_start_8168cp_3(tp);
6401                 break;
6402
6403         case RTL_GIGA_MAC_VER_25:
6404         case RTL_GIGA_MAC_VER_26:
6405         case RTL_GIGA_MAC_VER_27:
6406                 rtl_hw_start_8168d(tp);
6407                 break;
6408
6409         case RTL_GIGA_MAC_VER_28:
6410                 rtl_hw_start_8168d_4(tp);
6411                 break;
6412
6413         case RTL_GIGA_MAC_VER_31:
6414                 rtl_hw_start_8168dp(tp);
6415                 break;
6416
6417         case RTL_GIGA_MAC_VER_32:
6418         case RTL_GIGA_MAC_VER_33:
6419                 rtl_hw_start_8168e_1(tp);
6420                 break;
6421         case RTL_GIGA_MAC_VER_34:
6422                 rtl_hw_start_8168e_2(tp);
6423                 break;
6424
6425         case RTL_GIGA_MAC_VER_35:
6426         case RTL_GIGA_MAC_VER_36:
6427                 rtl_hw_start_8168f_1(tp);
6428                 break;
6429
6430         case RTL_GIGA_MAC_VER_38:
6431                 rtl_hw_start_8411(tp);
6432                 break;
6433
6434         case RTL_GIGA_MAC_VER_40:
6435         case RTL_GIGA_MAC_VER_41:
6436                 rtl_hw_start_8168g_1(tp);
6437                 break;
6438         case RTL_GIGA_MAC_VER_42:
6439                 rtl_hw_start_8168g_2(tp);
6440                 break;
6441
6442         case RTL_GIGA_MAC_VER_44:
6443                 rtl_hw_start_8411_2(tp);
6444                 break;
6445
6446         case RTL_GIGA_MAC_VER_45:
6447         case RTL_GIGA_MAC_VER_46:
6448                 rtl_hw_start_8168h_1(tp);
6449                 break;
6450
6451         case RTL_GIGA_MAC_VER_49:
6452                 rtl_hw_start_8168ep_1(tp);
6453                 break;
6454
6455         case RTL_GIGA_MAC_VER_50:
6456                 rtl_hw_start_8168ep_2(tp);
6457                 break;
6458
6459         case RTL_GIGA_MAC_VER_51:
6460                 rtl_hw_start_8168ep_3(tp);
6461                 break;
6462
6463         default:
6464                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6465                         dev->name, tp->mac_version);
6466                 break;
6467         }
6468
6469         RTL_W8(Cfg9346, Cfg9346_Lock);
6470
6471         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6472
6473         rtl_set_rx_mode(dev);
6474
6475         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6476 }
6477
6478 #define R810X_CPCMD_QUIRK_MASK (\
6479         EnableBist | \
6480         Mac_dbgo_oe | \
6481         Force_half_dup | \
6482         Force_rxflow_en | \
6483         Force_txflow_en | \
6484         Cxpl_dbg_sel | \
6485         ASF | \
6486         PktCntrDisable | \
6487         Mac_dbgo_sel)
6488
6489 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6490 {
6491         void __iomem *ioaddr = tp->mmio_addr;
6492         struct pci_dev *pdev = tp->pci_dev;
6493         static const struct ephy_info e_info_8102e_1[] = {
6494                 { 0x01, 0, 0x6e65 },
6495                 { 0x02, 0, 0x091f },
6496                 { 0x03, 0, 0xc2f9 },
6497                 { 0x06, 0, 0xafb5 },
6498                 { 0x07, 0, 0x0e00 },
6499                 { 0x19, 0, 0xec80 },
6500                 { 0x01, 0, 0x2e65 },
6501                 { 0x01, 0, 0x6e65 }
6502         };
6503         u8 cfg1;
6504
6505         rtl_csi_access_enable_2(tp);
6506
6507         RTL_W8(DBG_REG, FIX_NAK_1);
6508
6509         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6510
6511         RTL_W8(Config1,
6512                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6513         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6514
6515         cfg1 = RTL_R8(Config1);
6516         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6517                 RTL_W8(Config1, cfg1 & ~LEDS0);
6518
6519         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6520 }
6521
6522 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6523 {
6524         void __iomem *ioaddr = tp->mmio_addr;
6525         struct pci_dev *pdev = tp->pci_dev;
6526
6527         rtl_csi_access_enable_2(tp);
6528
6529         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6530
6531         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6532         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6533 }
6534
6535 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6536 {
6537         rtl_hw_start_8102e_2(tp);
6538
6539         rtl_ephy_write(tp, 0x03, 0xc2f9);
6540 }
6541
6542 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6543 {
6544         void __iomem *ioaddr = tp->mmio_addr;
6545         static const struct ephy_info e_info_8105e_1[] = {
6546                 { 0x07, 0, 0x4000 },
6547                 { 0x19, 0, 0x0200 },
6548                 { 0x19, 0, 0x0020 },
6549                 { 0x1e, 0, 0x2000 },
6550                 { 0x03, 0, 0x0001 },
6551                 { 0x19, 0, 0x0100 },
6552                 { 0x19, 0, 0x0004 },
6553                 { 0x0a, 0, 0x0020 }
6554         };
6555
6556         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6557         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6558
6559         /* Disable Early Tally Counter */
6560         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6561
6562         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6563         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6564
6565         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6566
6567         rtl_pcie_state_l2l3_enable(tp, false);
6568 }
6569
6570 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6571 {
6572         rtl_hw_start_8105e_1(tp);
6573         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6574 }
6575
6576 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6577 {
6578         void __iomem *ioaddr = tp->mmio_addr;
6579         static const struct ephy_info e_info_8402[] = {
6580                 { 0x19, 0xffff, 0xff64 },
6581                 { 0x1e, 0, 0x4000 }
6582         };
6583
6584         rtl_csi_access_enable_2(tp);
6585
6586         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6587         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6588
6589         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6590         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6591
6592         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6593
6594         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6595
6596         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6597         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6598         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6599         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6600         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6601         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6602         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6603
6604         rtl_pcie_state_l2l3_enable(tp, false);
6605 }
6606
6607 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6608 {
6609         void __iomem *ioaddr = tp->mmio_addr;
6610
6611         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6612         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6613
6614         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6615         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6616         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6617
6618         rtl_pcie_state_l2l3_enable(tp, false);
6619 }
6620
6621 static void rtl_hw_start_8101(struct net_device *dev)
6622 {
6623         struct rtl8169_private *tp = netdev_priv(dev);
6624         void __iomem *ioaddr = tp->mmio_addr;
6625         struct pci_dev *pdev = tp->pci_dev;
6626
6627         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6628                 tp->event_slow &= ~RxFIFOOver;
6629
6630         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6631             tp->mac_version == RTL_GIGA_MAC_VER_16)
6632                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6633                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6634
6635         RTL_W8(Cfg9346, Cfg9346_Unlock);
6636
6637         RTL_W8(MaxTxPacketSize, TxPacketMax);
6638
6639         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6640
6641         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6642         RTL_W16(CPlusCmd, tp->cp_cmd);
6643
6644         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6645
6646         rtl_set_rx_tx_config_registers(tp);
6647
6648         switch (tp->mac_version) {
6649         case RTL_GIGA_MAC_VER_07:
6650                 rtl_hw_start_8102e_1(tp);
6651                 break;
6652
6653         case RTL_GIGA_MAC_VER_08:
6654                 rtl_hw_start_8102e_3(tp);
6655                 break;
6656
6657         case RTL_GIGA_MAC_VER_09:
6658                 rtl_hw_start_8102e_2(tp);
6659                 break;
6660
6661         case RTL_GIGA_MAC_VER_29:
6662                 rtl_hw_start_8105e_1(tp);
6663                 break;
6664         case RTL_GIGA_MAC_VER_30:
6665                 rtl_hw_start_8105e_2(tp);
6666                 break;
6667
6668         case RTL_GIGA_MAC_VER_37:
6669                 rtl_hw_start_8402(tp);
6670                 break;
6671
6672         case RTL_GIGA_MAC_VER_39:
6673                 rtl_hw_start_8106(tp);
6674                 break;
6675         case RTL_GIGA_MAC_VER_43:
6676                 rtl_hw_start_8168g_2(tp);
6677                 break;
6678         case RTL_GIGA_MAC_VER_47:
6679         case RTL_GIGA_MAC_VER_48:
6680                 rtl_hw_start_8168h_1(tp);
6681                 break;
6682         }
6683
6684         RTL_W8(Cfg9346, Cfg9346_Lock);
6685
6686         RTL_W16(IntrMitigate, 0x0000);
6687
6688         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6689
6690         rtl_set_rx_mode(dev);
6691
6692         RTL_R8(IntrMask);
6693
6694         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6695 }
6696
6697 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6698 {
6699         struct rtl8169_private *tp = netdev_priv(dev);
6700
6701         if (new_mtu < ETH_ZLEN ||
6702             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6703                 return -EINVAL;
6704
6705         if (new_mtu > ETH_DATA_LEN)
6706                 rtl_hw_jumbo_enable(tp);
6707         else
6708                 rtl_hw_jumbo_disable(tp);
6709
6710         dev->mtu = new_mtu;
6711         netdev_update_features(dev);
6712
6713         return 0;
6714 }
6715
6716 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6717 {
6718         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6719         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6720 }
6721
6722 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6723                                      void **data_buff, struct RxDesc *desc)
6724 {
6725         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6726                          DMA_FROM_DEVICE);
6727
6728         kfree(*data_buff);
6729         *data_buff = NULL;
6730         rtl8169_make_unusable_by_asic(desc);
6731 }
6732
6733 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6734 {
6735         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6736
6737         /* Force memory writes to complete before releasing descriptor */
6738         dma_wmb();
6739
6740         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6741 }
6742
6743 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6744                                        u32 rx_buf_sz)
6745 {
6746         desc->addr = cpu_to_le64(mapping);
6747         rtl8169_mark_to_asic(desc, rx_buf_sz);
6748 }
6749
6750 static inline void *rtl8169_align(void *data)
6751 {
6752         return (void *)ALIGN((long)data, 16);
6753 }
6754
6755 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6756                                              struct RxDesc *desc)
6757 {
6758         void *data;
6759         dma_addr_t mapping;
6760         struct device *d = &tp->pci_dev->dev;
6761         struct net_device *dev = tp->dev;
6762         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6763
6764         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6765         if (!data)
6766                 return NULL;
6767
6768         if (rtl8169_align(data) != data) {
6769                 kfree(data);
6770                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6771                 if (!data)
6772                         return NULL;
6773         }
6774
6775         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6776                                  DMA_FROM_DEVICE);
6777         if (unlikely(dma_mapping_error(d, mapping))) {
6778                 if (net_ratelimit())
6779                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6780                 goto err_out;
6781         }
6782
6783         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6784         return data;
6785
6786 err_out:
6787         kfree(data);
6788         return NULL;
6789 }
6790
6791 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6792 {
6793         unsigned int i;
6794
6795         for (i = 0; i < NUM_RX_DESC; i++) {
6796                 if (tp->Rx_databuff[i]) {
6797                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6798                                             tp->RxDescArray + i);
6799                 }
6800         }
6801 }
6802
6803 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6804 {
6805         desc->opts1 |= cpu_to_le32(RingEnd);
6806 }
6807
6808 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6809 {
6810         unsigned int i;
6811
6812         for (i = 0; i < NUM_RX_DESC; i++) {
6813                 void *data;
6814
6815                 if (tp->Rx_databuff[i])
6816                         continue;
6817
6818                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6819                 if (!data) {
6820                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6821                         goto err_out;
6822                 }
6823                 tp->Rx_databuff[i] = data;
6824         }
6825
6826         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6827         return 0;
6828
6829 err_out:
6830         rtl8169_rx_clear(tp);
6831         return -ENOMEM;
6832 }
6833
6834 static int rtl8169_init_ring(struct net_device *dev)
6835 {
6836         struct rtl8169_private *tp = netdev_priv(dev);
6837
6838         rtl8169_init_ring_indexes(tp);
6839
6840         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6841         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6842
6843         return rtl8169_rx_fill(tp);
6844 }
6845
6846 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6847                                  struct TxDesc *desc)
6848 {
6849         unsigned int len = tx_skb->len;
6850
6851         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6852
6853         desc->opts1 = 0x00;
6854         desc->opts2 = 0x00;
6855         desc->addr = 0x00;
6856         tx_skb->len = 0;
6857 }
6858
6859 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6860                                    unsigned int n)
6861 {
6862         unsigned int i;
6863
6864         for (i = 0; i < n; i++) {
6865                 unsigned int entry = (start + i) % NUM_TX_DESC;
6866                 struct ring_info *tx_skb = tp->tx_skb + entry;
6867                 unsigned int len = tx_skb->len;
6868
6869                 if (len) {
6870                         struct sk_buff *skb = tx_skb->skb;
6871
6872                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6873                                              tp->TxDescArray + entry);
6874                         if (skb) {
6875                                 tp->dev->stats.tx_dropped++;
6876                                 dev_kfree_skb_any(skb);
6877                                 tx_skb->skb = NULL;
6878                         }
6879                 }
6880         }
6881 }
6882
6883 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6884 {
6885         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6886         tp->cur_tx = tp->dirty_tx = 0;
6887 }
6888
6889 static void rtl_reset_work(struct rtl8169_private *tp)
6890 {
6891         struct net_device *dev = tp->dev;
6892         int i;
6893
6894         napi_disable(&tp->napi);
6895         netif_stop_queue(dev);
6896         synchronize_sched();
6897
6898         rtl8169_hw_reset(tp);
6899
6900         for (i = 0; i < NUM_RX_DESC; i++)
6901                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6902
6903         rtl8169_tx_clear(tp);
6904         rtl8169_init_ring_indexes(tp);
6905
6906         napi_enable(&tp->napi);
6907         rtl_hw_start(dev);
6908         netif_wake_queue(dev);
6909         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6910 }
6911
6912 static void rtl8169_tx_timeout(struct net_device *dev)
6913 {
6914         struct rtl8169_private *tp = netdev_priv(dev);
6915
6916         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6917 }
6918
6919 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6920                               u32 *opts)
6921 {
6922         struct skb_shared_info *info = skb_shinfo(skb);
6923         unsigned int cur_frag, entry;
6924         struct TxDesc *uninitialized_var(txd);
6925         struct device *d = &tp->pci_dev->dev;
6926
6927         entry = tp->cur_tx;
6928         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6929                 const skb_frag_t *frag = info->frags + cur_frag;
6930                 dma_addr_t mapping;
6931                 u32 status, len;
6932                 void *addr;
6933
6934                 entry = (entry + 1) % NUM_TX_DESC;
6935
6936                 txd = tp->TxDescArray + entry;
6937                 len = skb_frag_size(frag);
6938                 addr = skb_frag_address(frag);
6939                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6940                 if (unlikely(dma_mapping_error(d, mapping))) {
6941                         if (net_ratelimit())
6942                                 netif_err(tp, drv, tp->dev,
6943                                           "Failed to map TX fragments DMA!\n");
6944                         goto err_out;
6945                 }
6946
6947                 /* Anti gcc 2.95.3 bugware (sic) */
6948                 status = opts[0] | len |
6949                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6950
6951                 txd->opts1 = cpu_to_le32(status);
6952                 txd->opts2 = cpu_to_le32(opts[1]);
6953                 txd->addr = cpu_to_le64(mapping);
6954
6955                 tp->tx_skb[entry].len = len;
6956         }
6957
6958         if (cur_frag) {
6959                 tp->tx_skb[entry].skb = skb;
6960                 txd->opts1 |= cpu_to_le32(LastFrag);
6961         }
6962
6963         return cur_frag;
6964
6965 err_out:
6966         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6967         return -EIO;
6968 }
6969
6970 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6971 {
6972         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6973 }
6974
6975 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6976                                       struct net_device *dev);
6977 /* r8169_csum_workaround()
6978  * The hw limites the value the transport offset. When the offset is out of the
6979  * range, calculate the checksum by sw.
6980  */
6981 static void r8169_csum_workaround(struct rtl8169_private *tp,
6982                                   struct sk_buff *skb)
6983 {
6984         if (skb_shinfo(skb)->gso_size) {
6985                 netdev_features_t features = tp->dev->features;
6986                 struct sk_buff *segs, *nskb;
6987
6988                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6989                 segs = skb_gso_segment(skb, features);
6990                 if (IS_ERR(segs) || !segs)
6991                         goto drop;
6992
6993                 do {
6994                         nskb = segs;
6995                         segs = segs->next;
6996                         nskb->next = NULL;
6997                         rtl8169_start_xmit(nskb, tp->dev);
6998                 } while (segs);
6999
7000                 dev_consume_skb_any(skb);
7001         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7002                 if (skb_checksum_help(skb) < 0)
7003                         goto drop;
7004
7005                 rtl8169_start_xmit(skb, tp->dev);
7006         } else {
7007                 struct net_device_stats *stats;
7008
7009 drop:
7010                 stats = &tp->dev->stats;
7011                 stats->tx_dropped++;
7012                 dev_kfree_skb_any(skb);
7013         }
7014 }
7015
7016 /* msdn_giant_send_check()
7017  * According to the document of microsoft, the TCP Pseudo Header excludes the
7018  * packet length for IPv6 TCP large packets.
7019  */
7020 static int msdn_giant_send_check(struct sk_buff *skb)
7021 {
7022         const struct ipv6hdr *ipv6h;
7023         struct tcphdr *th;
7024         int ret;
7025
7026         ret = skb_cow_head(skb, 0);
7027         if (ret)
7028                 return ret;
7029
7030         ipv6h = ipv6_hdr(skb);
7031         th = tcp_hdr(skb);
7032
7033         th->check = 0;
7034         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7035
7036         return ret;
7037 }
7038
7039 static inline __be16 get_protocol(struct sk_buff *skb)
7040 {
7041         __be16 protocol;
7042
7043         if (skb->protocol == htons(ETH_P_8021Q))
7044                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7045         else
7046                 protocol = skb->protocol;
7047
7048         return protocol;
7049 }
7050
7051 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7052                                 struct sk_buff *skb, u32 *opts)
7053 {
7054         u32 mss = skb_shinfo(skb)->gso_size;
7055
7056         if (mss) {
7057                 opts[0] |= TD_LSO;
7058                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7059         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7060                 const struct iphdr *ip = ip_hdr(skb);
7061
7062                 if (ip->protocol == IPPROTO_TCP)
7063                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7064                 else if (ip->protocol == IPPROTO_UDP)
7065                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7066                 else
7067                         WARN_ON_ONCE(1);
7068         }
7069
7070         return true;
7071 }
7072
7073 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7074                                 struct sk_buff *skb, u32 *opts)
7075 {
7076         u32 transport_offset = (u32)skb_transport_offset(skb);
7077         u32 mss = skb_shinfo(skb)->gso_size;
7078
7079         if (mss) {
7080                 if (transport_offset > GTTCPHO_MAX) {
7081                         netif_warn(tp, tx_err, tp->dev,
7082                                    "Invalid transport offset 0x%x for TSO\n",
7083                                    transport_offset);
7084                         return false;
7085                 }
7086
7087                 switch (get_protocol(skb)) {
7088                 case htons(ETH_P_IP):
7089                         opts[0] |= TD1_GTSENV4;
7090                         break;
7091
7092                 case htons(ETH_P_IPV6):
7093                         if (msdn_giant_send_check(skb))
7094                                 return false;
7095
7096                         opts[0] |= TD1_GTSENV6;
7097                         break;
7098
7099                 default:
7100                         WARN_ON_ONCE(1);
7101                         break;
7102                 }
7103
7104                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7105                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7106         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7107                 u8 ip_protocol;
7108
7109                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7110                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7111
7112                 if (transport_offset > TCPHO_MAX) {
7113                         netif_warn(tp, tx_err, tp->dev,
7114                                    "Invalid transport offset 0x%x\n",
7115                                    transport_offset);
7116                         return false;
7117                 }
7118
7119                 switch (get_protocol(skb)) {
7120                 case htons(ETH_P_IP):
7121                         opts[1] |= TD1_IPv4_CS;
7122                         ip_protocol = ip_hdr(skb)->protocol;
7123                         break;
7124
7125                 case htons(ETH_P_IPV6):
7126                         opts[1] |= TD1_IPv6_CS;
7127                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7128                         break;
7129
7130                 default:
7131                         ip_protocol = IPPROTO_RAW;
7132                         break;
7133                 }
7134
7135                 if (ip_protocol == IPPROTO_TCP)
7136                         opts[1] |= TD1_TCP_CS;
7137                 else if (ip_protocol == IPPROTO_UDP)
7138                         opts[1] |= TD1_UDP_CS;
7139                 else
7140                         WARN_ON_ONCE(1);
7141
7142                 opts[1] |= transport_offset << TCPHO_SHIFT;
7143         } else {
7144                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7145                         return !eth_skb_pad(skb);
7146         }
7147
7148         return true;
7149 }
7150
7151 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7152                                       struct net_device *dev)
7153 {
7154         struct rtl8169_private *tp = netdev_priv(dev);
7155         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7156         struct TxDesc *txd = tp->TxDescArray + entry;
7157         void __iomem *ioaddr = tp->mmio_addr;
7158         struct device *d = &tp->pci_dev->dev;
7159         dma_addr_t mapping;
7160         u32 status, len;
7161         u32 opts[2];
7162         int frags;
7163
7164         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7165                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7166                 goto err_stop_0;
7167         }
7168
7169         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7170                 goto err_stop_0;
7171
7172         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7173         opts[0] = DescOwn;
7174
7175         if (!tp->tso_csum(tp, skb, opts)) {
7176                 r8169_csum_workaround(tp, skb);
7177                 return NETDEV_TX_OK;
7178         }
7179
7180         len = skb_headlen(skb);
7181         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7182         if (unlikely(dma_mapping_error(d, mapping))) {
7183                 if (net_ratelimit())
7184                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7185                 goto err_dma_0;
7186         }
7187
7188         tp->tx_skb[entry].len = len;
7189         txd->addr = cpu_to_le64(mapping);
7190
7191         frags = rtl8169_xmit_frags(tp, skb, opts);
7192         if (frags < 0)
7193                 goto err_dma_1;
7194         else if (frags)
7195                 opts[0] |= FirstFrag;
7196         else {
7197                 opts[0] |= FirstFrag | LastFrag;
7198                 tp->tx_skb[entry].skb = skb;
7199         }
7200
7201         txd->opts2 = cpu_to_le32(opts[1]);
7202
7203         skb_tx_timestamp(skb);
7204
7205         /* Force memory writes to complete before releasing descriptor */
7206         dma_wmb();
7207
7208         /* Anti gcc 2.95.3 bugware (sic) */
7209         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7210         txd->opts1 = cpu_to_le32(status);
7211
7212         /* Force all memory writes to complete before notifying device */
7213         wmb();
7214
7215         tp->cur_tx += frags + 1;
7216
7217         RTL_W8(TxPoll, NPQ);
7218
7219         mmiowb();
7220
7221         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7222                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7223                  * not miss a ring update when it notices a stopped queue.
7224                  */
7225                 smp_wmb();
7226                 netif_stop_queue(dev);
7227                 /* Sync with rtl_tx:
7228                  * - publish queue status and cur_tx ring index (write barrier)
7229                  * - refresh dirty_tx ring index (read barrier).
7230                  * May the current thread have a pessimistic view of the ring
7231                  * status and forget to wake up queue, a racing rtl_tx thread
7232                  * can't.
7233                  */
7234                 smp_mb();
7235                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7236                         netif_wake_queue(dev);
7237         }
7238
7239         return NETDEV_TX_OK;
7240
7241 err_dma_1:
7242         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7243 err_dma_0:
7244         dev_kfree_skb_any(skb);
7245         dev->stats.tx_dropped++;
7246         return NETDEV_TX_OK;
7247
7248 err_stop_0:
7249         netif_stop_queue(dev);
7250         dev->stats.tx_dropped++;
7251         return NETDEV_TX_BUSY;
7252 }
7253
7254 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7255 {
7256         struct rtl8169_private *tp = netdev_priv(dev);
7257         struct pci_dev *pdev = tp->pci_dev;
7258         u16 pci_status, pci_cmd;
7259
7260         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7261         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7262
7263         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7264                   pci_cmd, pci_status);
7265
7266         /*
7267          * The recovery sequence below admits a very elaborated explanation:
7268          * - it seems to work;
7269          * - I did not see what else could be done;
7270          * - it makes iop3xx happy.
7271          *
7272          * Feel free to adjust to your needs.
7273          */
7274         if (pdev->broken_parity_status)
7275                 pci_cmd &= ~PCI_COMMAND_PARITY;
7276         else
7277                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7278
7279         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7280
7281         pci_write_config_word(pdev, PCI_STATUS,
7282                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7283                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7284                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7285
7286         /* The infamous DAC f*ckup only happens at boot time */
7287         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7288                 void __iomem *ioaddr = tp->mmio_addr;
7289
7290                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7291                 tp->cp_cmd &= ~PCIDAC;
7292                 RTL_W16(CPlusCmd, tp->cp_cmd);
7293                 dev->features &= ~NETIF_F_HIGHDMA;
7294         }
7295
7296         rtl8169_hw_reset(tp);
7297
7298         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7299 }
7300
7301 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7302 {
7303         unsigned int dirty_tx, tx_left;
7304
7305         dirty_tx = tp->dirty_tx;
7306         smp_rmb();
7307         tx_left = tp->cur_tx - dirty_tx;
7308
7309         while (tx_left > 0) {
7310                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7311                 struct ring_info *tx_skb = tp->tx_skb + entry;
7312                 u32 status;
7313
7314                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7315                 if (status & DescOwn)
7316                         break;
7317
7318                 /* This barrier is needed to keep us from reading
7319                  * any other fields out of the Tx descriptor until
7320                  * we know the status of DescOwn
7321                  */
7322                 dma_rmb();
7323
7324                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7325                                      tp->TxDescArray + entry);
7326                 if (status & LastFrag) {
7327                         u64_stats_update_begin(&tp->tx_stats.syncp);
7328                         tp->tx_stats.packets++;
7329                         tp->tx_stats.bytes += tx_skb->skb->len;
7330                         u64_stats_update_end(&tp->tx_stats.syncp);
7331                         dev_kfree_skb_any(tx_skb->skb);
7332                         tx_skb->skb = NULL;
7333                 }
7334                 dirty_tx++;
7335                 tx_left--;
7336         }
7337
7338         if (tp->dirty_tx != dirty_tx) {
7339                 tp->dirty_tx = dirty_tx;
7340                 /* Sync with rtl8169_start_xmit:
7341                  * - publish dirty_tx ring index (write barrier)
7342                  * - refresh cur_tx ring index and queue status (read barrier)
7343                  * May the current thread miss the stopped queue condition,
7344                  * a racing xmit thread can only have a right view of the
7345                  * ring status.
7346                  */
7347                 smp_mb();
7348                 if (netif_queue_stopped(dev) &&
7349                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7350                         netif_wake_queue(dev);
7351                 }
7352                 /*
7353                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7354                  * too close. Let's kick an extra TxPoll request when a burst
7355                  * of start_xmit activity is detected (if it is not detected,
7356                  * it is slow enough). -- FR
7357                  */
7358                 if (tp->cur_tx != dirty_tx) {
7359                         void __iomem *ioaddr = tp->mmio_addr;
7360
7361                         RTL_W8(TxPoll, NPQ);
7362                 }
7363         }
7364 }
7365
7366 static inline int rtl8169_fragmented_frame(u32 status)
7367 {
7368         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7369 }
7370
7371 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7372 {
7373         u32 status = opts1 & RxProtoMask;
7374
7375         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7376             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7377                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7378         else
7379                 skb_checksum_none_assert(skb);
7380 }
7381
7382 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7383                                            struct rtl8169_private *tp,
7384                                            int pkt_size,
7385                                            dma_addr_t addr)
7386 {
7387         struct sk_buff *skb;
7388         struct device *d = &tp->pci_dev->dev;
7389
7390         data = rtl8169_align(data);
7391         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7392         prefetch(data);
7393         skb = napi_alloc_skb(&tp->napi, pkt_size);
7394         if (skb)
7395                 memcpy(skb->data, data, pkt_size);
7396         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7397
7398         return skb;
7399 }
7400
7401 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7402 {
7403         unsigned int cur_rx, rx_left;
7404         unsigned int count;
7405
7406         cur_rx = tp->cur_rx;
7407
7408         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7409                 unsigned int entry = cur_rx % NUM_RX_DESC;
7410                 struct RxDesc *desc = tp->RxDescArray + entry;
7411                 u32 status;
7412
7413                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7414                 if (status & DescOwn)
7415                         break;
7416
7417                 /* This barrier is needed to keep us from reading
7418                  * any other fields out of the Rx descriptor until
7419                  * we know the status of DescOwn
7420                  */
7421                 dma_rmb();
7422
7423                 if (unlikely(status & RxRES)) {
7424                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7425                                    status);
7426                         dev->stats.rx_errors++;
7427                         if (status & (RxRWT | RxRUNT))
7428                                 dev->stats.rx_length_errors++;
7429                         if (status & RxCRC)
7430                                 dev->stats.rx_crc_errors++;
7431                         if (status & RxFOVF) {
7432                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7433                                 dev->stats.rx_fifo_errors++;
7434                         }
7435                         if ((status & (RxRUNT | RxCRC)) &&
7436                             !(status & (RxRWT | RxFOVF)) &&
7437                             (dev->features & NETIF_F_RXALL))
7438                                 goto process_pkt;
7439                 } else {
7440                         struct sk_buff *skb;
7441                         dma_addr_t addr;
7442                         int pkt_size;
7443
7444 process_pkt:
7445                         addr = le64_to_cpu(desc->addr);
7446                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7447                                 pkt_size = (status & 0x00003fff) - 4;
7448                         else
7449                                 pkt_size = status & 0x00003fff;
7450
7451                         /*
7452                          * The driver does not support incoming fragmented
7453                          * frames. They are seen as a symptom of over-mtu
7454                          * sized frames.
7455                          */
7456                         if (unlikely(rtl8169_fragmented_frame(status))) {
7457                                 dev->stats.rx_dropped++;
7458                                 dev->stats.rx_length_errors++;
7459                                 goto release_descriptor;
7460                         }
7461
7462                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7463                                                   tp, pkt_size, addr);
7464                         if (!skb) {
7465                                 dev->stats.rx_dropped++;
7466                                 goto release_descriptor;
7467                         }
7468
7469                         rtl8169_rx_csum(skb, status);
7470                         skb_put(skb, pkt_size);
7471                         skb->protocol = eth_type_trans(skb, dev);
7472
7473                         rtl8169_rx_vlan_tag(desc, skb);
7474
7475                         napi_gro_receive(&tp->napi, skb);
7476
7477                         u64_stats_update_begin(&tp->rx_stats.syncp);
7478                         tp->rx_stats.packets++;
7479                         tp->rx_stats.bytes += pkt_size;
7480                         u64_stats_update_end(&tp->rx_stats.syncp);
7481
7482                         if (skb->pkt_type == PACKET_MULTICAST)
7483                                 dev->stats.multicast++;
7484                 }
7485 release_descriptor:
7486                 desc->opts2 = 0;
7487                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7488         }
7489
7490         count = cur_rx - tp->cur_rx;
7491         tp->cur_rx = cur_rx;
7492
7493         return count;
7494 }
7495
7496 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7497 {
7498         struct net_device *dev = dev_instance;
7499         struct rtl8169_private *tp = netdev_priv(dev);
7500         int handled = 0;
7501         u16 status;
7502
7503         status = rtl_get_events(tp);
7504         if (status && status != 0xffff) {
7505                 status &= RTL_EVENT_NAPI | tp->event_slow;
7506                 if (status) {
7507                         handled = 1;
7508
7509                         rtl_irq_disable(tp);
7510                         napi_schedule(&tp->napi);
7511                 }
7512         }
7513         return IRQ_RETVAL(handled);
7514 }
7515
7516 /*
7517  * Workqueue context.
7518  */
7519 static void rtl_slow_event_work(struct rtl8169_private *tp)
7520 {
7521         struct net_device *dev = tp->dev;
7522         u16 status;
7523
7524         status = rtl_get_events(tp) & tp->event_slow;
7525         rtl_ack_events(tp, status);
7526
7527         if (unlikely(status & RxFIFOOver)) {
7528                 switch (tp->mac_version) {
7529                 /* Work around for rx fifo overflow */
7530                 case RTL_GIGA_MAC_VER_11:
7531                         netif_stop_queue(dev);
7532                         /* XXX - Hack alert. See rtl_task(). */
7533                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7534                 default:
7535                         break;
7536                 }
7537         }
7538
7539         if (unlikely(status & SYSErr))
7540                 rtl8169_pcierr_interrupt(dev);
7541
7542         if (status & LinkChg)
7543                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7544
7545         rtl_irq_enable_all(tp);
7546 }
7547
7548 static void rtl_task(struct work_struct *work)
7549 {
7550         static const struct {
7551                 int bitnr;
7552                 void (*action)(struct rtl8169_private *);
7553         } rtl_work[] = {
7554                 /* XXX - keep rtl_slow_event_work() as first element. */
7555                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7556                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7557                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7558         };
7559         struct rtl8169_private *tp =
7560                 container_of(work, struct rtl8169_private, wk.work);
7561         struct net_device *dev = tp->dev;
7562         int i;
7563
7564         rtl_lock_work(tp);
7565
7566         if (!netif_running(dev) ||
7567             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7568                 goto out_unlock;
7569
7570         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7571                 bool pending;
7572
7573                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7574                 if (pending)
7575                         rtl_work[i].action(tp);
7576         }
7577
7578 out_unlock:
7579         rtl_unlock_work(tp);
7580 }
7581
7582 static int rtl8169_poll(struct napi_struct *napi, int budget)
7583 {
7584         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7585         struct net_device *dev = tp->dev;
7586         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7587         int work_done= 0;
7588         u16 status;
7589
7590         status = rtl_get_events(tp);
7591         rtl_ack_events(tp, status & ~tp->event_slow);
7592
7593         if (status & RTL_EVENT_NAPI_RX)
7594                 work_done = rtl_rx(dev, tp, (u32) budget);
7595
7596         if (status & RTL_EVENT_NAPI_TX)
7597                 rtl_tx(dev, tp);
7598
7599         if (status & tp->event_slow) {
7600                 enable_mask &= ~tp->event_slow;
7601
7602                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7603         }
7604
7605         if (work_done < budget) {
7606                 napi_complete(napi);
7607
7608                 rtl_irq_enable(tp, enable_mask);
7609                 mmiowb();
7610         }
7611
7612         return work_done;
7613 }
7614
7615 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7616 {
7617         struct rtl8169_private *tp = netdev_priv(dev);
7618
7619         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7620                 return;
7621
7622         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7623         RTL_W32(RxMissed, 0);
7624 }
7625
7626 static void rtl8169_down(struct net_device *dev)
7627 {
7628         struct rtl8169_private *tp = netdev_priv(dev);
7629         void __iomem *ioaddr = tp->mmio_addr;
7630
7631         del_timer_sync(&tp->timer);
7632
7633         napi_disable(&tp->napi);
7634         netif_stop_queue(dev);
7635
7636         rtl8169_hw_reset(tp);
7637         /*
7638          * At this point device interrupts can not be enabled in any function,
7639          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7640          * and napi is disabled (rtl8169_poll).
7641          */
7642         rtl8169_rx_missed(dev, ioaddr);
7643
7644         /* Give a racing hard_start_xmit a few cycles to complete. */
7645         synchronize_sched();
7646
7647         rtl8169_tx_clear(tp);
7648
7649         rtl8169_rx_clear(tp);
7650
7651         rtl_pll_power_down(tp);
7652 }
7653
7654 static int rtl8169_close(struct net_device *dev)
7655 {
7656         struct rtl8169_private *tp = netdev_priv(dev);
7657         struct pci_dev *pdev = tp->pci_dev;
7658
7659         pm_runtime_get_sync(&pdev->dev);
7660
7661         /* Update counters before going down */
7662         rtl8169_update_counters(dev);
7663
7664         rtl_lock_work(tp);
7665         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7666
7667         rtl8169_down(dev);
7668         rtl_unlock_work(tp);
7669
7670         cancel_work_sync(&tp->wk.work);
7671
7672         free_irq(pdev->irq, dev);
7673
7674         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7675                           tp->RxPhyAddr);
7676         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7677                           tp->TxPhyAddr);
7678         tp->TxDescArray = NULL;
7679         tp->RxDescArray = NULL;
7680
7681         pm_runtime_put_sync(&pdev->dev);
7682
7683         return 0;
7684 }
7685
7686 #ifdef CONFIG_NET_POLL_CONTROLLER
7687 static void rtl8169_netpoll(struct net_device *dev)
7688 {
7689         struct rtl8169_private *tp = netdev_priv(dev);
7690
7691         rtl8169_interrupt(tp->pci_dev->irq, dev);
7692 }
7693 #endif
7694
7695 static int rtl_open(struct net_device *dev)
7696 {
7697         struct rtl8169_private *tp = netdev_priv(dev);
7698         void __iomem *ioaddr = tp->mmio_addr;
7699         struct pci_dev *pdev = tp->pci_dev;
7700         int retval = -ENOMEM;
7701
7702         pm_runtime_get_sync(&pdev->dev);
7703
7704         /*
7705          * Rx and Tx descriptors needs 256 bytes alignment.
7706          * dma_alloc_coherent provides more.
7707          */
7708         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7709                                              &tp->TxPhyAddr, GFP_KERNEL);
7710         if (!tp->TxDescArray)
7711                 goto err_pm_runtime_put;
7712
7713         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7714                                              &tp->RxPhyAddr, GFP_KERNEL);
7715         if (!tp->RxDescArray)
7716                 goto err_free_tx_0;
7717
7718         retval = rtl8169_init_ring(dev);
7719         if (retval < 0)
7720                 goto err_free_rx_1;
7721
7722         INIT_WORK(&tp->wk.work, rtl_task);
7723
7724         smp_mb();
7725
7726         rtl_request_firmware(tp);
7727
7728         retval = request_irq(pdev->irq, rtl8169_interrupt,
7729                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7730                              dev->name, dev);
7731         if (retval < 0)
7732                 goto err_release_fw_2;
7733
7734         rtl_lock_work(tp);
7735
7736         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7737
7738         napi_enable(&tp->napi);
7739
7740         rtl8169_init_phy(dev, tp);
7741
7742         __rtl8169_set_features(dev, dev->features);
7743
7744         rtl_pll_power_up(tp);
7745
7746         rtl_hw_start(dev);
7747
7748         if (!rtl8169_init_counter_offsets(dev))
7749                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7750
7751         netif_start_queue(dev);
7752
7753         rtl_unlock_work(tp);
7754
7755         tp->saved_wolopts = 0;
7756         pm_runtime_put_noidle(&pdev->dev);
7757
7758         rtl8169_check_link_status(dev, tp, ioaddr);
7759 out:
7760         return retval;
7761
7762 err_release_fw_2:
7763         rtl_release_firmware(tp);
7764         rtl8169_rx_clear(tp);
7765 err_free_rx_1:
7766         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7767                           tp->RxPhyAddr);
7768         tp->RxDescArray = NULL;
7769 err_free_tx_0:
7770         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7771                           tp->TxPhyAddr);
7772         tp->TxDescArray = NULL;
7773 err_pm_runtime_put:
7774         pm_runtime_put_noidle(&pdev->dev);
7775         goto out;
7776 }
7777
7778 static struct rtnl_link_stats64 *
7779 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7780 {
7781         struct rtl8169_private *tp = netdev_priv(dev);
7782         void __iomem *ioaddr = tp->mmio_addr;
7783         unsigned int start;
7784
7785         if (netif_running(dev))
7786                 rtl8169_rx_missed(dev, ioaddr);
7787
7788         do {
7789                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7790                 stats->rx_packets = tp->rx_stats.packets;
7791                 stats->rx_bytes = tp->rx_stats.bytes;
7792         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7793
7794         do {
7795                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7796                 stats->tx_packets = tp->tx_stats.packets;
7797                 stats->tx_bytes = tp->tx_stats.bytes;
7798         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7799
7800         stats->rx_dropped       = dev->stats.rx_dropped;
7801         stats->tx_dropped       = dev->stats.tx_dropped;
7802         stats->rx_length_errors = dev->stats.rx_length_errors;
7803         stats->rx_errors        = dev->stats.rx_errors;
7804         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7805         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7806         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7807         stats->multicast        = dev->stats.multicast;
7808
7809         /*
7810          * Fetch additonal counter values missing in stats collected by driver
7811          * from tally counters.
7812          */
7813         rtl8169_update_counters(dev);
7814
7815         /*
7816          * Subtract values fetched during initalization.
7817          * See rtl8169_init_counter_offsets for a description why we do that.
7818          */
7819         stats->tx_errors = le64_to_cpu(tp->counters.tx_errors) -
7820                 le64_to_cpu(tp->tc_offset.tx_errors);
7821         stats->collisions = le32_to_cpu(tp->counters.tx_multi_collision) -
7822                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7823         stats->tx_aborted_errors = le16_to_cpu(tp->counters.tx_aborted) -
7824                 le16_to_cpu(tp->tc_offset.tx_aborted);
7825
7826         return stats;
7827 }
7828
7829 static void rtl8169_net_suspend(struct net_device *dev)
7830 {
7831         struct rtl8169_private *tp = netdev_priv(dev);
7832
7833         if (!netif_running(dev))
7834                 return;
7835
7836         netif_device_detach(dev);
7837         netif_stop_queue(dev);
7838
7839         rtl_lock_work(tp);
7840         napi_disable(&tp->napi);
7841         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7842         rtl_unlock_work(tp);
7843
7844         rtl_pll_power_down(tp);
7845 }
7846
7847 #ifdef CONFIG_PM
7848
7849 static int rtl8169_suspend(struct device *device)
7850 {
7851         struct pci_dev *pdev = to_pci_dev(device);
7852         struct net_device *dev = pci_get_drvdata(pdev);
7853
7854         rtl8169_net_suspend(dev);
7855
7856         return 0;
7857 }
7858
7859 static void __rtl8169_resume(struct net_device *dev)
7860 {
7861         struct rtl8169_private *tp = netdev_priv(dev);
7862
7863         netif_device_attach(dev);
7864
7865         rtl_pll_power_up(tp);
7866
7867         rtl_lock_work(tp);
7868         napi_enable(&tp->napi);
7869         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7870         rtl_unlock_work(tp);
7871
7872         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7873 }
7874
7875 static int rtl8169_resume(struct device *device)
7876 {
7877         struct pci_dev *pdev = to_pci_dev(device);
7878         struct net_device *dev = pci_get_drvdata(pdev);
7879         struct rtl8169_private *tp = netdev_priv(dev);
7880
7881         rtl8169_init_phy(dev, tp);
7882
7883         if (netif_running(dev))
7884                 __rtl8169_resume(dev);
7885
7886         return 0;
7887 }
7888
7889 static int rtl8169_runtime_suspend(struct device *device)
7890 {
7891         struct pci_dev *pdev = to_pci_dev(device);
7892         struct net_device *dev = pci_get_drvdata(pdev);
7893         struct rtl8169_private *tp = netdev_priv(dev);
7894
7895         if (!tp->TxDescArray)
7896                 return 0;
7897
7898         rtl_lock_work(tp);
7899         tp->saved_wolopts = __rtl8169_get_wol(tp);
7900         __rtl8169_set_wol(tp, WAKE_ANY);
7901         rtl_unlock_work(tp);
7902
7903         rtl8169_net_suspend(dev);
7904
7905         return 0;
7906 }
7907
7908 static int rtl8169_runtime_resume(struct device *device)
7909 {
7910         struct pci_dev *pdev = to_pci_dev(device);
7911         struct net_device *dev = pci_get_drvdata(pdev);
7912         struct rtl8169_private *tp = netdev_priv(dev);
7913
7914         if (!tp->TxDescArray)
7915                 return 0;
7916
7917         rtl_lock_work(tp);
7918         __rtl8169_set_wol(tp, tp->saved_wolopts);
7919         tp->saved_wolopts = 0;
7920         rtl_unlock_work(tp);
7921
7922         rtl8169_init_phy(dev, tp);
7923
7924         __rtl8169_resume(dev);
7925
7926         return 0;
7927 }
7928
7929 static int rtl8169_runtime_idle(struct device *device)
7930 {
7931         struct pci_dev *pdev = to_pci_dev(device);
7932         struct net_device *dev = pci_get_drvdata(pdev);
7933         struct rtl8169_private *tp = netdev_priv(dev);
7934
7935         return tp->TxDescArray ? -EBUSY : 0;
7936 }
7937
7938 static const struct dev_pm_ops rtl8169_pm_ops = {
7939         .suspend                = rtl8169_suspend,
7940         .resume                 = rtl8169_resume,
7941         .freeze                 = rtl8169_suspend,
7942         .thaw                   = rtl8169_resume,
7943         .poweroff               = rtl8169_suspend,
7944         .restore                = rtl8169_resume,
7945         .runtime_suspend        = rtl8169_runtime_suspend,
7946         .runtime_resume         = rtl8169_runtime_resume,
7947         .runtime_idle           = rtl8169_runtime_idle,
7948 };
7949
7950 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7951
7952 #else /* !CONFIG_PM */
7953
7954 #define RTL8169_PM_OPS  NULL
7955
7956 #endif /* !CONFIG_PM */
7957
7958 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7959 {
7960         void __iomem *ioaddr = tp->mmio_addr;
7961
7962         /* WoL fails with 8168b when the receiver is disabled. */
7963         switch (tp->mac_version) {
7964         case RTL_GIGA_MAC_VER_11:
7965         case RTL_GIGA_MAC_VER_12:
7966         case RTL_GIGA_MAC_VER_17:
7967                 pci_clear_master(tp->pci_dev);
7968
7969                 RTL_W8(ChipCmd, CmdRxEnb);
7970                 /* PCI commit */
7971                 RTL_R8(ChipCmd);
7972                 break;
7973         default:
7974                 break;
7975         }
7976 }
7977
7978 static void rtl_shutdown(struct pci_dev *pdev)
7979 {
7980         struct net_device *dev = pci_get_drvdata(pdev);
7981         struct rtl8169_private *tp = netdev_priv(dev);
7982         struct device *d = &pdev->dev;
7983
7984         pm_runtime_get_sync(d);
7985
7986         rtl8169_net_suspend(dev);
7987
7988         /* Restore original MAC address */
7989         rtl_rar_set(tp, dev->perm_addr);
7990
7991         rtl8169_hw_reset(tp);
7992
7993         if (system_state == SYSTEM_POWER_OFF) {
7994                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7995                         rtl_wol_suspend_quirk(tp);
7996                         rtl_wol_shutdown_quirk(tp);
7997                 }
7998
7999                 pci_wake_from_d3(pdev, true);
8000                 pci_set_power_state(pdev, PCI_D3hot);
8001         }
8002
8003         pm_runtime_put_noidle(d);
8004 }
8005
8006 static void rtl_remove_one(struct pci_dev *pdev)
8007 {
8008         struct net_device *dev = pci_get_drvdata(pdev);
8009         struct rtl8169_private *tp = netdev_priv(dev);
8010
8011         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8012              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8013              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8014              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8015              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8016              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8017             r8168_check_dash(tp)) {
8018                 rtl8168_driver_stop(tp);
8019         }
8020
8021         netif_napi_del(&tp->napi);
8022
8023         unregister_netdev(dev);
8024
8025         rtl_release_firmware(tp);
8026
8027         if (pci_dev_run_wake(pdev))
8028                 pm_runtime_get_noresume(&pdev->dev);
8029
8030         /* restore original MAC address */
8031         rtl_rar_set(tp, dev->perm_addr);
8032
8033         rtl_disable_msi(pdev, tp);
8034         rtl8169_release_board(pdev, dev, tp->mmio_addr);
8035 }
8036
8037 static const struct net_device_ops rtl_netdev_ops = {
8038         .ndo_open               = rtl_open,
8039         .ndo_stop               = rtl8169_close,
8040         .ndo_get_stats64        = rtl8169_get_stats64,
8041         .ndo_start_xmit         = rtl8169_start_xmit,
8042         .ndo_tx_timeout         = rtl8169_tx_timeout,
8043         .ndo_validate_addr      = eth_validate_addr,
8044         .ndo_change_mtu         = rtl8169_change_mtu,
8045         .ndo_fix_features       = rtl8169_fix_features,
8046         .ndo_set_features       = rtl8169_set_features,
8047         .ndo_set_mac_address    = rtl_set_mac_address,
8048         .ndo_do_ioctl           = rtl8169_ioctl,
8049         .ndo_set_rx_mode        = rtl_set_rx_mode,
8050 #ifdef CONFIG_NET_POLL_CONTROLLER
8051         .ndo_poll_controller    = rtl8169_netpoll,
8052 #endif
8053
8054 };
8055
8056 static const struct rtl_cfg_info {
8057         void (*hw_start)(struct net_device *);
8058         unsigned int region;
8059         unsigned int align;
8060         u16 event_slow;
8061         unsigned features;
8062         u8 default_ver;
8063 } rtl_cfg_infos [] = {
8064         [RTL_CFG_0] = {
8065                 .hw_start       = rtl_hw_start_8169,
8066                 .region         = 1,
8067                 .align          = 0,
8068                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8069                 .features       = RTL_FEATURE_GMII,
8070                 .default_ver    = RTL_GIGA_MAC_VER_01,
8071         },
8072         [RTL_CFG_1] = {
8073                 .hw_start       = rtl_hw_start_8168,
8074                 .region         = 2,
8075                 .align          = 8,
8076                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8077                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8078                 .default_ver    = RTL_GIGA_MAC_VER_11,
8079         },
8080         [RTL_CFG_2] = {
8081                 .hw_start       = rtl_hw_start_8101,
8082                 .region         = 2,
8083                 .align          = 8,
8084                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8085                                   PCSTimeout,
8086                 .features       = RTL_FEATURE_MSI,
8087                 .default_ver    = RTL_GIGA_MAC_VER_13,
8088         }
8089 };
8090
8091 /* Cfg9346_Unlock assumed. */
8092 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8093                             const struct rtl_cfg_info *cfg)
8094 {
8095         void __iomem *ioaddr = tp->mmio_addr;
8096         unsigned msi = 0;
8097         u8 cfg2;
8098
8099         cfg2 = RTL_R8(Config2) & ~MSIEnable;
8100         if (cfg->features & RTL_FEATURE_MSI) {
8101                 if (pci_enable_msi(tp->pci_dev)) {
8102                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8103                 } else {
8104                         cfg2 |= MSIEnable;
8105                         msi = RTL_FEATURE_MSI;
8106                 }
8107         }
8108         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8109                 RTL_W8(Config2, cfg2);
8110         return msi;
8111 }
8112
8113 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8114 {
8115         void __iomem *ioaddr = tp->mmio_addr;
8116
8117         return RTL_R8(MCU) & LINK_LIST_RDY;
8118 }
8119
8120 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8121 {
8122         void __iomem *ioaddr = tp->mmio_addr;
8123
8124         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8125 }
8126
8127 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8128 {
8129         void __iomem *ioaddr = tp->mmio_addr;
8130         u32 data;
8131
8132         tp->ocp_base = OCP_STD_PHY_BASE;
8133
8134         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8135
8136         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8137                 return;
8138
8139         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8140                 return;
8141
8142         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8143         msleep(1);
8144         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8145
8146         data = r8168_mac_ocp_read(tp, 0xe8de);
8147         data &= ~(1 << 14);
8148         r8168_mac_ocp_write(tp, 0xe8de, data);
8149
8150         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8151                 return;
8152
8153         data = r8168_mac_ocp_read(tp, 0xe8de);
8154         data |= (1 << 15);
8155         r8168_mac_ocp_write(tp, 0xe8de, data);
8156
8157         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8158                 return;
8159 }
8160
8161 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8162 {
8163         rtl8168ep_stop_cmac(tp);
8164         rtl_hw_init_8168g(tp);
8165 }
8166
8167 static void rtl_hw_initialize(struct rtl8169_private *tp)
8168 {
8169         switch (tp->mac_version) {
8170         case RTL_GIGA_MAC_VER_40:
8171         case RTL_GIGA_MAC_VER_41:
8172         case RTL_GIGA_MAC_VER_42:
8173         case RTL_GIGA_MAC_VER_43:
8174         case RTL_GIGA_MAC_VER_44:
8175         case RTL_GIGA_MAC_VER_45:
8176         case RTL_GIGA_MAC_VER_46:
8177         case RTL_GIGA_MAC_VER_47:
8178         case RTL_GIGA_MAC_VER_48:
8179                 rtl_hw_init_8168g(tp);
8180                 break;
8181         case RTL_GIGA_MAC_VER_49:
8182         case RTL_GIGA_MAC_VER_50:
8183         case RTL_GIGA_MAC_VER_51:
8184                 rtl_hw_init_8168ep(tp);
8185                 break;
8186         default:
8187                 break;
8188         }
8189 }
8190
8191 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8192 {
8193         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8194         const unsigned int region = cfg->region;
8195         struct rtl8169_private *tp;
8196         struct mii_if_info *mii;
8197         struct net_device *dev;
8198         void __iomem *ioaddr;
8199         int chipset, i;
8200         int rc;
8201
8202         if (netif_msg_drv(&debug)) {
8203                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8204                        MODULENAME, RTL8169_VERSION);
8205         }
8206
8207         dev = alloc_etherdev(sizeof (*tp));
8208         if (!dev) {
8209                 rc = -ENOMEM;
8210                 goto out;
8211         }
8212
8213         SET_NETDEV_DEV(dev, &pdev->dev);
8214         dev->netdev_ops = &rtl_netdev_ops;
8215         tp = netdev_priv(dev);
8216         tp->dev = dev;
8217         tp->pci_dev = pdev;
8218         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8219
8220         mii = &tp->mii;
8221         mii->dev = dev;
8222         mii->mdio_read = rtl_mdio_read;
8223         mii->mdio_write = rtl_mdio_write;
8224         mii->phy_id_mask = 0x1f;
8225         mii->reg_num_mask = 0x1f;
8226         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8227
8228         /* disable ASPM completely as that cause random device stop working
8229          * problems as well as full system hangs for some PCIe devices users */
8230         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8231                                      PCIE_LINK_STATE_CLKPM);
8232
8233         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8234         rc = pci_enable_device(pdev);
8235         if (rc < 0) {
8236                 netif_err(tp, probe, dev, "enable failure\n");
8237                 goto err_out_free_dev_1;
8238         }
8239
8240         if (pci_set_mwi(pdev) < 0)
8241                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8242
8243         /* make sure PCI base addr 1 is MMIO */
8244         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8245                 netif_err(tp, probe, dev,
8246                           "region #%d not an MMIO resource, aborting\n",
8247                           region);
8248                 rc = -ENODEV;
8249                 goto err_out_mwi_2;
8250         }
8251
8252         /* check for weird/broken PCI region reporting */
8253         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8254                 netif_err(tp, probe, dev,
8255                           "Invalid PCI region size(s), aborting\n");
8256                 rc = -ENODEV;
8257                 goto err_out_mwi_2;
8258         }
8259
8260         rc = pci_request_regions(pdev, MODULENAME);
8261         if (rc < 0) {
8262                 netif_err(tp, probe, dev, "could not request regions\n");
8263                 goto err_out_mwi_2;
8264         }
8265
8266         tp->cp_cmd = 0;
8267
8268         if ((sizeof(dma_addr_t) > 4) &&
8269             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8270                 tp->cp_cmd |= PCIDAC;
8271                 dev->features |= NETIF_F_HIGHDMA;
8272         } else {
8273                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8274                 if (rc < 0) {
8275                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8276                         goto err_out_free_res_3;
8277                 }
8278         }
8279
8280         /* ioremap MMIO region */
8281         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8282         if (!ioaddr) {
8283                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8284                 rc = -EIO;
8285                 goto err_out_free_res_3;
8286         }
8287         tp->mmio_addr = ioaddr;
8288
8289         if (!pci_is_pcie(pdev))
8290                 netif_info(tp, probe, dev, "not PCI Express\n");
8291
8292         /* Identify chip attached to board */
8293         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8294
8295         rtl_init_rxcfg(tp);
8296
8297         rtl_irq_disable(tp);
8298
8299         rtl_hw_initialize(tp);
8300
8301         rtl_hw_reset(tp);
8302
8303         rtl_ack_events(tp, 0xffff);
8304
8305         pci_set_master(pdev);
8306
8307         rtl_init_mdio_ops(tp);
8308         rtl_init_pll_power_ops(tp);
8309         rtl_init_jumbo_ops(tp);
8310         rtl_init_csi_ops(tp);
8311
8312         rtl8169_print_mac_version(tp);
8313
8314         chipset = tp->mac_version;
8315         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8316
8317         RTL_W8(Cfg9346, Cfg9346_Unlock);
8318         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8319         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8320         switch (tp->mac_version) {
8321         case RTL_GIGA_MAC_VER_34:
8322         case RTL_GIGA_MAC_VER_35:
8323         case RTL_GIGA_MAC_VER_36:
8324         case RTL_GIGA_MAC_VER_37:
8325         case RTL_GIGA_MAC_VER_38:
8326         case RTL_GIGA_MAC_VER_40:
8327         case RTL_GIGA_MAC_VER_41:
8328         case RTL_GIGA_MAC_VER_42:
8329         case RTL_GIGA_MAC_VER_43:
8330         case RTL_GIGA_MAC_VER_44:
8331         case RTL_GIGA_MAC_VER_45:
8332         case RTL_GIGA_MAC_VER_46:
8333         case RTL_GIGA_MAC_VER_47:
8334         case RTL_GIGA_MAC_VER_48:
8335         case RTL_GIGA_MAC_VER_49:
8336         case RTL_GIGA_MAC_VER_50:
8337         case RTL_GIGA_MAC_VER_51:
8338                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8339                         tp->features |= RTL_FEATURE_WOL;
8340                 if ((RTL_R8(Config3) & LinkUp) != 0)
8341                         tp->features |= RTL_FEATURE_WOL;
8342                 break;
8343         default:
8344                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8345                         tp->features |= RTL_FEATURE_WOL;
8346                 break;
8347         }
8348         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8349                 tp->features |= RTL_FEATURE_WOL;
8350         tp->features |= rtl_try_msi(tp, cfg);
8351         RTL_W8(Cfg9346, Cfg9346_Lock);
8352
8353         if (rtl_tbi_enabled(tp)) {
8354                 tp->set_speed = rtl8169_set_speed_tbi;
8355                 tp->get_settings = rtl8169_gset_tbi;
8356                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8357                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8358                 tp->link_ok = rtl8169_tbi_link_ok;
8359                 tp->do_ioctl = rtl_tbi_ioctl;
8360         } else {
8361                 tp->set_speed = rtl8169_set_speed_xmii;
8362                 tp->get_settings = rtl8169_gset_xmii;
8363                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8364                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8365                 tp->link_ok = rtl8169_xmii_link_ok;
8366                 tp->do_ioctl = rtl_xmii_ioctl;
8367         }
8368
8369         mutex_init(&tp->wk.mutex);
8370         u64_stats_init(&tp->rx_stats.syncp);
8371         u64_stats_init(&tp->tx_stats.syncp);
8372
8373         /* Get MAC address */
8374         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8375             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8376             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8377             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8378             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8379             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8380             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8381             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8382             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8383             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8384             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8385             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8386             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8387             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8388             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8389             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8390                 u16 mac_addr[3];
8391
8392                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8393                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8394
8395                 if (is_valid_ether_addr((u8 *)mac_addr))
8396                         rtl_rar_set(tp, (u8 *)mac_addr);
8397         }
8398         for (i = 0; i < ETH_ALEN; i++)
8399                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8400
8401         dev->ethtool_ops = &rtl8169_ethtool_ops;
8402         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8403
8404         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8405
8406         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8407          * properly for all devices */
8408         dev->features |= NETIF_F_RXCSUM |
8409                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8410
8411         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8412                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8413                 NETIF_F_HW_VLAN_CTAG_RX;
8414         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8415                 NETIF_F_HIGHDMA;
8416
8417         tp->cp_cmd |= RxChkSum | RxVlan;
8418
8419         /*
8420          * Pretend we are using VLANs; This bypasses a nasty bug where
8421          * Interrupts stop flowing on high load on 8110SCd controllers.
8422          */
8423         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8424                 /* Disallow toggling */
8425                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8426
8427         if (tp->txd_version == RTL_TD_0)
8428                 tp->tso_csum = rtl8169_tso_csum_v1;
8429         else if (tp->txd_version == RTL_TD_1) {
8430                 tp->tso_csum = rtl8169_tso_csum_v2;
8431                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8432         } else
8433                 WARN_ON_ONCE(1);
8434
8435         dev->hw_features |= NETIF_F_RXALL;
8436         dev->hw_features |= NETIF_F_RXFCS;
8437
8438         tp->hw_start = cfg->hw_start;
8439         tp->event_slow = cfg->event_slow;
8440
8441         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8442                 ~(RxBOVF | RxFOVF) : ~0;
8443
8444         init_timer(&tp->timer);
8445         tp->timer.data = (unsigned long) dev;
8446         tp->timer.function = rtl8169_phy_timer;
8447
8448         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8449
8450         rc = register_netdev(dev);
8451         if (rc < 0)
8452                 goto err_out_msi_4;
8453
8454         pci_set_drvdata(pdev, dev);
8455
8456         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8457                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8458                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8459         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8460                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8461                            "tx checksumming: %s]\n",
8462                            rtl_chip_infos[chipset].jumbo_max,
8463                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8464         }
8465
8466         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8467              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8468              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8469              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8470              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8471              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8472             r8168_check_dash(tp)) {
8473                 rtl8168_driver_start(tp);
8474         }
8475
8476         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8477
8478         if (pci_dev_run_wake(pdev))
8479                 pm_runtime_put_noidle(&pdev->dev);
8480
8481         netif_carrier_off(dev);
8482
8483 out:
8484         return rc;
8485
8486 err_out_msi_4:
8487         netif_napi_del(&tp->napi);
8488         rtl_disable_msi(pdev, tp);
8489         iounmap(ioaddr);
8490 err_out_free_res_3:
8491         pci_release_regions(pdev);
8492 err_out_mwi_2:
8493         pci_clear_mwi(pdev);
8494         pci_disable_device(pdev);
8495 err_out_free_dev_1:
8496         free_netdev(dev);
8497         goto out;
8498 }
8499
8500 static struct pci_driver rtl8169_pci_driver = {
8501         .name           = MODULENAME,
8502         .id_table       = rtl8169_pci_tbl,
8503         .probe          = rtl_init_one,
8504         .remove         = rtl_remove_one,
8505         .shutdown       = rtl_shutdown,
8506         .driver.pm      = RTL8169_PM_OPS,
8507 };
8508
8509 module_pci_driver(rtl8169_pci_driver);