2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
110 RTL_GIGA_MAC_VER_01 = 0,
161 RTL_GIGA_MAC_NONE = 0xff,
164 enum rtl_tx_desc_version {
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
175 #define _R(NAME,TD,FW,SZ,B) { \
183 static const struct {
185 enum rtl_tx_desc_version txd_version;
189 } rtl_chip_infos[] = {
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
347 static int rx_buf_sz = 16383;
354 MAC0 = 0, /* Ethernet hardware address. */
356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
371 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
375 #define RX128_INT_EN (1 << 15) /* 8111c and later */
376 #define RX_MULTI_EN (1 << 14) /* 8111c only */
377 #define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
380 #define RX_EARLY_OFF (1 << 11)
381 #define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
390 #define PME_SIGNAL (1 << 5) /* 8168c and later */
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
405 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
409 #define TxPacketMax (8064 >> 7)
410 #define EarlySize 0x27
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
419 FuncForceEvent = 0xfc,
422 enum rtl8110_registers {
428 enum rtl8168_8101_registers {
431 #define CSIAR_FLAG 0x80000000
432 #define CSIAR_WRITE_CMD 0x80000000
433 #define CSIAR_BYTE_ENABLE 0x0f
434 #define CSIAR_BYTE_ENABLE_SHIFT 12
435 #define CSIAR_ADDR_MASK 0x0fff
436 #define CSIAR_FUNC_CARD 0x00000000
437 #define CSIAR_FUNC_SDIO 0x00010000
438 #define CSIAR_FUNC_NIC 0x00020000
439 #define CSIAR_FUNC_NIC2 0x00010000
442 #define EPHYAR_FLAG 0x80000000
443 #define EPHYAR_WRITE_CMD 0x80000000
444 #define EPHYAR_REG_MASK 0x1f
445 #define EPHYAR_REG_SHIFT 16
446 #define EPHYAR_DATA_MASK 0xffff
448 #define PFM_EN (1 << 6)
449 #define TX_10M_PS_EN (1 << 7)
451 #define FIX_NAK_1 (1 << 4)
452 #define FIX_NAK_2 (1 << 3)
455 #define NOW_IS_OOB (1 << 7)
456 #define TX_EMPTY (1 << 5)
457 #define RX_EMPTY (1 << 4)
458 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
459 #define EN_NDP (1 << 3)
460 #define EN_OOB_RESET (1 << 2)
461 #define LINK_LIST_RDY (1 << 1)
463 #define EFUSEAR_FLAG 0x80000000
464 #define EFUSEAR_WRITE_CMD 0x80000000
465 #define EFUSEAR_READ_CMD 0x00000000
466 #define EFUSEAR_REG_MASK 0x03ff
467 #define EFUSEAR_REG_SHIFT 8
468 #define EFUSEAR_DATA_MASK 0xff
470 #define PFM_D3COLD_EN (1 << 6)
473 enum rtl8168_registers {
478 #define ERIAR_FLAG 0x80000000
479 #define ERIAR_WRITE_CMD 0x80000000
480 #define ERIAR_READ_CMD 0x00000000
481 #define ERIAR_ADDR_BYTE_ALIGN 4
482 #define ERIAR_TYPE_SHIFT 16
483 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_MASK_SHIFT 12
488 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495 #define OCPDR_WRITE_CMD 0x80000000
496 #define OCPDR_READ_CMD 0x00000000
497 #define OCPDR_REG_MASK 0x7f
498 #define OCPDR_GPHY_REG_SHIFT 16
499 #define OCPDR_DATA_MASK 0xffff
501 #define OCPAR_FLAG 0x80000000
502 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
503 #define OCPAR_GPHY_READ_CMD 0x0000f060
505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
507 #define TXPLA_RST (1 << 29)
508 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
509 #define PWM_EN (1 << 22)
510 #define RXDV_GATED_EN (1 << 19)
511 #define EARLY_TALLY_EN (1 << 16)
514 enum rtl_register_content {
515 /* InterruptStatusBits */
519 TxDescUnavail = 0x0080,
543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
550 Cfg9346_Unlock = 0xc0,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
558 AcceptAllPhys = 0x01,
559 #define RX_CONFIG_ACCEPT_MASK 0x3f
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
565 /* Config1 register p.24 */
568 Speed_down = (1 << 4),
572 PMEnable = (1 << 0), /* Power Management Enable */
574 /* Config2 register p. 25 */
575 ClkReqEn = (1 << 7), /* Clock Request Enable */
576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
590 /* Config5 register p.27 */
591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
595 LanWake = (1 << 1), /* LanWake enable/disable */
596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
597 ASPM_en = (1 << 0), /* ASPM enable */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
627 /* rtl8169_PHYstatus */
638 TBILinkOK = 0x02000000,
640 /* ResetCounterCommand */
643 /* DumpCounterCommand */
646 /* magic enable v2 */
647 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
651 /* First doubleword. */
652 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
653 RingEnd = (1 << 30), /* End of descriptor ring */
654 FirstFrag = (1 << 29), /* First segment of a packet */
655 LastFrag = (1 << 28), /* Final segment of a packet */
659 enum rtl_tx_desc_bit {
660 /* First doubleword. */
661 TD_LSO = (1 << 27), /* Large Send Offload */
662 #define TD_MSS_MAX 0x07ffu /* MSS value */
664 /* Second doubleword. */
665 TxVlanTag = (1 << 17), /* Add VLAN tag */
668 /* 8169, 8168b and 810x except 8102e. */
669 enum rtl_tx_desc_bit_0 {
670 /* First doubleword. */
671 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
672 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
673 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
674 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
677 /* 8102e, 8168c and beyond. */
678 enum rtl_tx_desc_bit_1 {
679 /* First doubleword. */
680 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
681 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
682 #define GTTCPHO_SHIFT 18
683 #define GTTCPHO_MAX 0x7fU
685 /* Second doubleword. */
686 #define TCPHO_SHIFT 18
687 #define TCPHO_MAX 0x3ffU
688 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
689 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
690 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
691 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
692 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
695 enum rtl_rx_desc_bit {
697 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
698 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
700 #define RxProtoUDP (PID1)
701 #define RxProtoTCP (PID0)
702 #define RxProtoIP (PID1 | PID0)
703 #define RxProtoMask RxProtoIP
705 IPFail = (1 << 16), /* IP checksum failed */
706 UDPFail = (1 << 15), /* UDP/IP checksum failed */
707 TCPFail = (1 << 14), /* TCP/IP checksum failed */
708 RxVlanTag = (1 << 16), /* VLAN tag available */
711 #define RsvdMask 0x3fffc000
728 u8 __pad[sizeof(void *) - sizeof(u32)];
732 RTL_FEATURE_WOL = (1 << 0),
733 RTL_FEATURE_MSI = (1 << 1),
734 RTL_FEATURE_GMII = (1 << 2),
737 struct rtl8169_counters {
744 __le32 tx_one_collision;
745 __le32 tx_multi_collision;
753 struct rtl8169_tc_offsets {
756 __le32 tx_multi_collision;
761 RTL_FLAG_TASK_ENABLED,
762 RTL_FLAG_TASK_SLOW_PENDING,
763 RTL_FLAG_TASK_RESET_PENDING,
764 RTL_FLAG_TASK_PHY_PENDING,
768 struct rtl8169_stats {
771 struct u64_stats_sync syncp;
774 struct rtl8169_private {
775 void __iomem *mmio_addr; /* memory map physical address */
776 struct pci_dev *pci_dev;
777 struct net_device *dev;
778 struct napi_struct napi;
782 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
783 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
785 struct rtl8169_stats rx_stats;
786 struct rtl8169_stats tx_stats;
787 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
788 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
789 dma_addr_t TxPhyAddr;
790 dma_addr_t RxPhyAddr;
791 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
792 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
793 struct timer_list timer;
799 void (*write)(struct rtl8169_private *, int, int);
800 int (*read)(struct rtl8169_private *, int);
803 struct pll_power_ops {
804 void (*down)(struct rtl8169_private *);
805 void (*up)(struct rtl8169_private *);
809 void (*enable)(struct rtl8169_private *);
810 void (*disable)(struct rtl8169_private *);
814 void (*write)(struct rtl8169_private *, int, int);
815 u32 (*read)(struct rtl8169_private *, int);
818 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
819 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
820 void (*phy_reset_enable)(struct rtl8169_private *tp);
821 void (*hw_start)(struct net_device *);
822 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
823 unsigned int (*link_ok)(void __iomem *);
824 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
825 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
828 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
830 struct work_struct work;
835 struct mii_if_info mii;
836 struct rtl8169_counters counters;
837 struct rtl8169_tc_offsets tc_offset;
842 const struct firmware *fw;
844 #define RTL_VER_SIZE 32
846 char version[RTL_VER_SIZE];
848 struct rtl_fw_phy_action {
853 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
858 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
859 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
860 module_param(use_dac, int, 0);
861 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
862 module_param_named(debug, debug.msg_enable, int, 0);
863 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
864 MODULE_LICENSE("GPL");
865 MODULE_VERSION(RTL8169_VERSION);
866 MODULE_FIRMWARE(FIRMWARE_8168D_1);
867 MODULE_FIRMWARE(FIRMWARE_8168D_2);
868 MODULE_FIRMWARE(FIRMWARE_8168E_1);
869 MODULE_FIRMWARE(FIRMWARE_8168E_2);
870 MODULE_FIRMWARE(FIRMWARE_8168E_3);
871 MODULE_FIRMWARE(FIRMWARE_8105E_1);
872 MODULE_FIRMWARE(FIRMWARE_8168F_1);
873 MODULE_FIRMWARE(FIRMWARE_8168F_2);
874 MODULE_FIRMWARE(FIRMWARE_8402_1);
875 MODULE_FIRMWARE(FIRMWARE_8411_1);
876 MODULE_FIRMWARE(FIRMWARE_8411_2);
877 MODULE_FIRMWARE(FIRMWARE_8106E_1);
878 MODULE_FIRMWARE(FIRMWARE_8106E_2);
879 MODULE_FIRMWARE(FIRMWARE_8168G_2);
880 MODULE_FIRMWARE(FIRMWARE_8168G_3);
881 MODULE_FIRMWARE(FIRMWARE_8168H_1);
882 MODULE_FIRMWARE(FIRMWARE_8168H_2);
883 MODULE_FIRMWARE(FIRMWARE_8107E_1);
884 MODULE_FIRMWARE(FIRMWARE_8107E_2);
886 static void rtl_lock_work(struct rtl8169_private *tp)
888 mutex_lock(&tp->wk.mutex);
891 static void rtl_unlock_work(struct rtl8169_private *tp)
893 mutex_unlock(&tp->wk.mutex);
896 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
898 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
899 PCI_EXP_DEVCTL_READRQ, force);
903 bool (*check)(struct rtl8169_private *);
907 static void rtl_udelay(unsigned int d)
912 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
913 void (*delay)(unsigned int), unsigned int d, int n,
918 for (i = 0; i < n; i++) {
920 if (c->check(tp) == high)
923 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
924 c->msg, !high, n, d);
928 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
929 const struct rtl_cond *c,
930 unsigned int d, int n)
932 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
935 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
936 const struct rtl_cond *c,
937 unsigned int d, int n)
939 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
942 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
943 const struct rtl_cond *c,
944 unsigned int d, int n)
946 return rtl_loop_wait(tp, c, msleep, d, n, true);
949 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
950 const struct rtl_cond *c,
951 unsigned int d, int n)
953 return rtl_loop_wait(tp, c, msleep, d, n, false);
956 #define DECLARE_RTL_COND(name) \
957 static bool name ## _check(struct rtl8169_private *); \
959 static const struct rtl_cond name = { \
960 .check = name ## _check, \
964 static bool name ## _check(struct rtl8169_private *tp)
966 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
968 if (reg & 0xffff0001) {
969 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
975 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
977 void __iomem *ioaddr = tp->mmio_addr;
979 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
982 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
984 void __iomem *ioaddr = tp->mmio_addr;
986 if (rtl_ocp_reg_failure(tp, reg))
989 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
991 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
994 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
996 void __iomem *ioaddr = tp->mmio_addr;
998 if (rtl_ocp_reg_failure(tp, reg))
1001 RTL_W32(GPHY_OCP, reg << 15);
1003 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1004 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1007 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1009 void __iomem *ioaddr = tp->mmio_addr;
1011 if (rtl_ocp_reg_failure(tp, reg))
1014 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1017 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1019 void __iomem *ioaddr = tp->mmio_addr;
1021 if (rtl_ocp_reg_failure(tp, reg))
1024 RTL_W32(OCPDR, reg << 15);
1026 return RTL_R32(OCPDR);
1029 #define OCP_STD_PHY_BASE 0xa400
1031 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1034 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1038 if (tp->ocp_base != OCP_STD_PHY_BASE)
1041 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1044 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1046 if (tp->ocp_base != OCP_STD_PHY_BASE)
1049 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1052 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1055 tp->ocp_base = value << 4;
1059 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1062 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1064 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1067 DECLARE_RTL_COND(rtl_phyar_cond)
1069 void __iomem *ioaddr = tp->mmio_addr;
1071 return RTL_R32(PHYAR) & 0x80000000;
1074 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1076 void __iomem *ioaddr = tp->mmio_addr;
1078 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1080 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1082 * According to hardware specs a 20us delay is required after write
1083 * complete indication, but before sending next command.
1088 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1090 void __iomem *ioaddr = tp->mmio_addr;
1093 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1095 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1096 RTL_R32(PHYAR) & 0xffff : ~0;
1099 * According to hardware specs a 20us delay is required after read
1100 * complete indication, but before sending next command.
1107 DECLARE_RTL_COND(rtl_ocpar_cond)
1109 void __iomem *ioaddr = tp->mmio_addr;
1111 return RTL_R32(OCPAR) & OCPAR_FLAG;
1114 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1116 void __iomem *ioaddr = tp->mmio_addr;
1118 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1119 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1120 RTL_W32(EPHY_RXER_NUM, 0);
1122 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1125 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1127 r8168dp_1_mdio_access(tp, reg,
1128 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1131 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1133 void __iomem *ioaddr = tp->mmio_addr;
1135 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1138 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1139 RTL_W32(EPHY_RXER_NUM, 0);
1141 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1142 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1145 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1147 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1149 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1152 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1154 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1157 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1159 void __iomem *ioaddr = tp->mmio_addr;
1161 r8168dp_2_mdio_start(ioaddr);
1163 r8169_mdio_write(tp, reg, value);
1165 r8168dp_2_mdio_stop(ioaddr);
1168 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1170 void __iomem *ioaddr = tp->mmio_addr;
1173 r8168dp_2_mdio_start(ioaddr);
1175 value = r8169_mdio_read(tp, reg);
1177 r8168dp_2_mdio_stop(ioaddr);
1182 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1184 tp->mdio_ops.write(tp, location, val);
1187 static int rtl_readphy(struct rtl8169_private *tp, int location)
1189 return tp->mdio_ops.read(tp, location);
1192 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1194 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1197 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1201 val = rtl_readphy(tp, reg_addr);
1202 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1205 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1208 struct rtl8169_private *tp = netdev_priv(dev);
1210 rtl_writephy(tp, location, val);
1213 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1215 struct rtl8169_private *tp = netdev_priv(dev);
1217 return rtl_readphy(tp, location);
1220 DECLARE_RTL_COND(rtl_ephyar_cond)
1222 void __iomem *ioaddr = tp->mmio_addr;
1224 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1227 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1229 void __iomem *ioaddr = tp->mmio_addr;
1231 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1232 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1239 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1241 void __iomem *ioaddr = tp->mmio_addr;
1243 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1245 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1246 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1249 DECLARE_RTL_COND(rtl_eriar_cond)
1251 void __iomem *ioaddr = tp->mmio_addr;
1253 return RTL_R32(ERIAR) & ERIAR_FLAG;
1256 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1259 void __iomem *ioaddr = tp->mmio_addr;
1261 BUG_ON((addr & 3) || (mask == 0));
1262 RTL_W32(ERIDR, val);
1263 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1265 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1268 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1270 void __iomem *ioaddr = tp->mmio_addr;
1272 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1274 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1275 RTL_R32(ERIDR) : ~0;
1278 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1283 val = rtl_eri_read(tp, addr, type);
1284 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1287 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1289 void __iomem *ioaddr = tp->mmio_addr;
1291 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1292 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1293 RTL_R32(OCPDR) : ~0;
1296 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298 return rtl_eri_read(tp, reg, ERIAR_OOB);
1301 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1303 switch (tp->mac_version) {
1304 case RTL_GIGA_MAC_VER_27:
1305 case RTL_GIGA_MAC_VER_28:
1306 case RTL_GIGA_MAC_VER_31:
1307 return r8168dp_ocp_read(tp, mask, reg);
1308 case RTL_GIGA_MAC_VER_49:
1309 case RTL_GIGA_MAC_VER_50:
1310 case RTL_GIGA_MAC_VER_51:
1311 return r8168ep_ocp_read(tp, mask, reg);
1318 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1321 void __iomem *ioaddr = tp->mmio_addr;
1323 RTL_W32(OCPDR, data);
1324 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1325 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1328 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1331 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1335 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1337 switch (tp->mac_version) {
1338 case RTL_GIGA_MAC_VER_27:
1339 case RTL_GIGA_MAC_VER_28:
1340 case RTL_GIGA_MAC_VER_31:
1341 r8168dp_ocp_write(tp, mask, reg, data);
1343 case RTL_GIGA_MAC_VER_49:
1344 case RTL_GIGA_MAC_VER_50:
1345 case RTL_GIGA_MAC_VER_51:
1346 r8168ep_ocp_write(tp, mask, reg, data);
1354 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1356 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1358 ocp_write(tp, 0x1, 0x30, 0x00000001);
1361 #define OOB_CMD_RESET 0x00
1362 #define OOB_CMD_DRIVER_START 0x05
1363 #define OOB_CMD_DRIVER_STOP 0x06
1365 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1367 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1370 DECLARE_RTL_COND(rtl_ocp_read_cond)
1374 reg = rtl8168_get_ocp_reg(tp);
1376 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1379 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1381 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1384 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1386 void __iomem *ioaddr = tp->mmio_addr;
1388 return RTL_R8(IBISR0) & 0x02;
1391 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1393 void __iomem *ioaddr = tp->mmio_addr;
1395 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1396 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1397 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1398 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1401 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1403 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1404 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1407 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1409 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1410 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1411 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1414 static void rtl8168_driver_start(struct rtl8169_private *tp)
1416 switch (tp->mac_version) {
1417 case RTL_GIGA_MAC_VER_27:
1418 case RTL_GIGA_MAC_VER_28:
1419 case RTL_GIGA_MAC_VER_31:
1420 rtl8168dp_driver_start(tp);
1422 case RTL_GIGA_MAC_VER_49:
1423 case RTL_GIGA_MAC_VER_50:
1424 case RTL_GIGA_MAC_VER_51:
1425 rtl8168ep_driver_start(tp);
1433 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1435 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1436 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1439 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1441 rtl8168ep_stop_cmac(tp);
1442 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1443 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1444 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1447 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1449 switch (tp->mac_version) {
1450 case RTL_GIGA_MAC_VER_27:
1451 case RTL_GIGA_MAC_VER_28:
1452 case RTL_GIGA_MAC_VER_31:
1453 rtl8168dp_driver_stop(tp);
1455 case RTL_GIGA_MAC_VER_49:
1456 case RTL_GIGA_MAC_VER_50:
1457 case RTL_GIGA_MAC_VER_51:
1458 rtl8168ep_driver_stop(tp);
1466 static int r8168dp_check_dash(struct rtl8169_private *tp)
1468 u16 reg = rtl8168_get_ocp_reg(tp);
1470 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1473 static int r8168ep_check_dash(struct rtl8169_private *tp)
1475 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1478 static int r8168_check_dash(struct rtl8169_private *tp)
1480 switch (tp->mac_version) {
1481 case RTL_GIGA_MAC_VER_27:
1482 case RTL_GIGA_MAC_VER_28:
1483 case RTL_GIGA_MAC_VER_31:
1484 return r8168dp_check_dash(tp);
1485 case RTL_GIGA_MAC_VER_49:
1486 case RTL_GIGA_MAC_VER_50:
1487 case RTL_GIGA_MAC_VER_51:
1488 return r8168ep_check_dash(tp);
1500 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1501 const struct exgmac_reg *r, int len)
1504 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1509 DECLARE_RTL_COND(rtl_efusear_cond)
1511 void __iomem *ioaddr = tp->mmio_addr;
1513 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1516 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1518 void __iomem *ioaddr = tp->mmio_addr;
1520 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1522 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1523 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1526 static u16 rtl_get_events(struct rtl8169_private *tp)
1528 void __iomem *ioaddr = tp->mmio_addr;
1530 return RTL_R16(IntrStatus);
1533 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1535 void __iomem *ioaddr = tp->mmio_addr;
1537 RTL_W16(IntrStatus, bits);
1541 static void rtl_irq_disable(struct rtl8169_private *tp)
1543 void __iomem *ioaddr = tp->mmio_addr;
1545 RTL_W16(IntrMask, 0);
1549 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1551 void __iomem *ioaddr = tp->mmio_addr;
1553 RTL_W16(IntrMask, bits);
1556 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1557 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1558 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1560 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1562 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1565 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1567 void __iomem *ioaddr = tp->mmio_addr;
1569 rtl_irq_disable(tp);
1570 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1574 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1576 void __iomem *ioaddr = tp->mmio_addr;
1578 return RTL_R32(TBICSR) & TBIReset;
1581 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1583 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1586 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1588 return RTL_R32(TBICSR) & TBILinkOk;
1591 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1593 return RTL_R8(PHYstatus) & LinkStatus;
1596 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1598 void __iomem *ioaddr = tp->mmio_addr;
1600 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1603 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1607 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1608 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1611 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1613 void __iomem *ioaddr = tp->mmio_addr;
1614 struct net_device *dev = tp->dev;
1616 if (!netif_running(dev))
1619 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1620 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1621 if (RTL_R8(PHYstatus) & _1000bpsF) {
1622 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1624 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1626 } else if (RTL_R8(PHYstatus) & _100bps) {
1627 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1629 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1632 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1634 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1637 /* Reset packet filter */
1638 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1640 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1642 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1643 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1644 if (RTL_R8(PHYstatus) & _1000bpsF) {
1645 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1647 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1650 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1652 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1655 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1656 if (RTL_R8(PHYstatus) & _10bps) {
1657 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1659 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1662 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1668 static void __rtl8169_check_link_status(struct net_device *dev,
1669 struct rtl8169_private *tp,
1670 void __iomem *ioaddr, bool pm)
1672 if (tp->link_ok(ioaddr)) {
1673 rtl_link_chg_patch(tp);
1674 /* This is to cancel a scheduled suspend if there's one. */
1676 pm_request_resume(&tp->pci_dev->dev);
1677 netif_carrier_on(dev);
1678 if (net_ratelimit())
1679 netif_info(tp, ifup, dev, "link up\n");
1681 netif_carrier_off(dev);
1682 netif_info(tp, ifdown, dev, "link down\n");
1684 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1688 static void rtl8169_check_link_status(struct net_device *dev,
1689 struct rtl8169_private *tp,
1690 void __iomem *ioaddr)
1692 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1695 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1699 void __iomem *ioaddr = tp->mmio_addr;
1703 options = RTL_R8(Config1);
1704 if (!(options & PMEnable))
1707 options = RTL_R8(Config3);
1708 if (options & LinkUp)
1709 wolopts |= WAKE_PHY;
1710 switch (tp->mac_version) {
1711 case RTL_GIGA_MAC_VER_34:
1712 case RTL_GIGA_MAC_VER_35:
1713 case RTL_GIGA_MAC_VER_36:
1714 case RTL_GIGA_MAC_VER_37:
1715 case RTL_GIGA_MAC_VER_38:
1716 case RTL_GIGA_MAC_VER_40:
1717 case RTL_GIGA_MAC_VER_41:
1718 case RTL_GIGA_MAC_VER_42:
1719 case RTL_GIGA_MAC_VER_43:
1720 case RTL_GIGA_MAC_VER_44:
1721 case RTL_GIGA_MAC_VER_45:
1722 case RTL_GIGA_MAC_VER_46:
1723 case RTL_GIGA_MAC_VER_47:
1724 case RTL_GIGA_MAC_VER_48:
1725 case RTL_GIGA_MAC_VER_49:
1726 case RTL_GIGA_MAC_VER_50:
1727 case RTL_GIGA_MAC_VER_51:
1728 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1729 wolopts |= WAKE_MAGIC;
1732 if (options & MagicPacket)
1733 wolopts |= WAKE_MAGIC;
1737 options = RTL_R8(Config5);
1739 wolopts |= WAKE_UCAST;
1741 wolopts |= WAKE_BCAST;
1743 wolopts |= WAKE_MCAST;
1748 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1750 struct rtl8169_private *tp = netdev_priv(dev);
1754 wol->supported = WAKE_ANY;
1755 wol->wolopts = __rtl8169_get_wol(tp);
1757 rtl_unlock_work(tp);
1760 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1762 void __iomem *ioaddr = tp->mmio_addr;
1763 unsigned int i, tmp;
1764 static const struct {
1769 { WAKE_PHY, Config3, LinkUp },
1770 { WAKE_UCAST, Config5, UWF },
1771 { WAKE_BCAST, Config5, BWF },
1772 { WAKE_MCAST, Config5, MWF },
1773 { WAKE_ANY, Config5, LanWake },
1774 { WAKE_MAGIC, Config3, MagicPacket }
1778 RTL_W8(Cfg9346, Cfg9346_Unlock);
1780 switch (tp->mac_version) {
1781 case RTL_GIGA_MAC_VER_34:
1782 case RTL_GIGA_MAC_VER_35:
1783 case RTL_GIGA_MAC_VER_36:
1784 case RTL_GIGA_MAC_VER_37:
1785 case RTL_GIGA_MAC_VER_38:
1786 case RTL_GIGA_MAC_VER_40:
1787 case RTL_GIGA_MAC_VER_41:
1788 case RTL_GIGA_MAC_VER_42:
1789 case RTL_GIGA_MAC_VER_43:
1790 case RTL_GIGA_MAC_VER_44:
1791 case RTL_GIGA_MAC_VER_45:
1792 case RTL_GIGA_MAC_VER_46:
1793 case RTL_GIGA_MAC_VER_47:
1794 case RTL_GIGA_MAC_VER_48:
1795 case RTL_GIGA_MAC_VER_49:
1796 case RTL_GIGA_MAC_VER_50:
1797 case RTL_GIGA_MAC_VER_51:
1798 tmp = ARRAY_SIZE(cfg) - 1;
1799 if (wolopts & WAKE_MAGIC)
1815 tmp = ARRAY_SIZE(cfg);
1819 for (i = 0; i < tmp; i++) {
1820 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1821 if (wolopts & cfg[i].opt)
1822 options |= cfg[i].mask;
1823 RTL_W8(cfg[i].reg, options);
1826 switch (tp->mac_version) {
1827 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1828 options = RTL_R8(Config1) & ~PMEnable;
1830 options |= PMEnable;
1831 RTL_W8(Config1, options);
1834 options = RTL_R8(Config2) & ~PME_SIGNAL;
1836 options |= PME_SIGNAL;
1837 RTL_W8(Config2, options);
1841 RTL_W8(Cfg9346, Cfg9346_Lock);
1844 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1846 struct rtl8169_private *tp = netdev_priv(dev);
1851 tp->features |= RTL_FEATURE_WOL;
1853 tp->features &= ~RTL_FEATURE_WOL;
1854 __rtl8169_set_wol(tp, wol->wolopts);
1856 rtl_unlock_work(tp);
1858 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1863 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1865 return rtl_chip_infos[tp->mac_version].fw_name;
1868 static void rtl8169_get_drvinfo(struct net_device *dev,
1869 struct ethtool_drvinfo *info)
1871 struct rtl8169_private *tp = netdev_priv(dev);
1872 struct rtl_fw *rtl_fw = tp->rtl_fw;
1874 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1875 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1876 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1877 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1878 if (!IS_ERR_OR_NULL(rtl_fw))
1879 strlcpy(info->fw_version, rtl_fw->version,
1880 sizeof(info->fw_version));
1883 static int rtl8169_get_regs_len(struct net_device *dev)
1885 return R8169_REGS_SIZE;
1888 static int rtl8169_set_speed_tbi(struct net_device *dev,
1889 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1891 struct rtl8169_private *tp = netdev_priv(dev);
1892 void __iomem *ioaddr = tp->mmio_addr;
1896 reg = RTL_R32(TBICSR);
1897 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1898 (duplex == DUPLEX_FULL)) {
1899 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1900 } else if (autoneg == AUTONEG_ENABLE)
1901 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1903 netif_warn(tp, link, dev,
1904 "incorrect speed setting refused in TBI mode\n");
1911 static int rtl8169_set_speed_xmii(struct net_device *dev,
1912 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1914 struct rtl8169_private *tp = netdev_priv(dev);
1915 int giga_ctrl, bmcr;
1918 rtl_writephy(tp, 0x1f, 0x0000);
1920 if (autoneg == AUTONEG_ENABLE) {
1923 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1924 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1925 ADVERTISE_100HALF | ADVERTISE_100FULL);
1927 if (adv & ADVERTISED_10baseT_Half)
1928 auto_nego |= ADVERTISE_10HALF;
1929 if (adv & ADVERTISED_10baseT_Full)
1930 auto_nego |= ADVERTISE_10FULL;
1931 if (adv & ADVERTISED_100baseT_Half)
1932 auto_nego |= ADVERTISE_100HALF;
1933 if (adv & ADVERTISED_100baseT_Full)
1934 auto_nego |= ADVERTISE_100FULL;
1936 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1938 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1939 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1941 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1942 if (tp->mii.supports_gmii) {
1943 if (adv & ADVERTISED_1000baseT_Half)
1944 giga_ctrl |= ADVERTISE_1000HALF;
1945 if (adv & ADVERTISED_1000baseT_Full)
1946 giga_ctrl |= ADVERTISE_1000FULL;
1947 } else if (adv & (ADVERTISED_1000baseT_Half |
1948 ADVERTISED_1000baseT_Full)) {
1949 netif_info(tp, link, dev,
1950 "PHY does not support 1000Mbps\n");
1954 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1956 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1957 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1961 if (speed == SPEED_10)
1963 else if (speed == SPEED_100)
1964 bmcr = BMCR_SPEED100;
1968 if (duplex == DUPLEX_FULL)
1969 bmcr |= BMCR_FULLDPLX;
1972 rtl_writephy(tp, MII_BMCR, bmcr);
1974 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1975 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1976 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1977 rtl_writephy(tp, 0x17, 0x2138);
1978 rtl_writephy(tp, 0x0e, 0x0260);
1980 rtl_writephy(tp, 0x17, 0x2108);
1981 rtl_writephy(tp, 0x0e, 0x0000);
1990 static int rtl8169_set_speed(struct net_device *dev,
1991 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1993 struct rtl8169_private *tp = netdev_priv(dev);
1996 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2000 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2001 (advertising & ADVERTISED_1000baseT_Full)) {
2002 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2008 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2010 struct rtl8169_private *tp = netdev_priv(dev);
2013 del_timer_sync(&tp->timer);
2016 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2017 cmd->duplex, cmd->advertising);
2018 rtl_unlock_work(tp);
2023 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2024 netdev_features_t features)
2026 struct rtl8169_private *tp = netdev_priv(dev);
2028 if (dev->mtu > TD_MSS_MAX)
2029 features &= ~NETIF_F_ALL_TSO;
2031 if (dev->mtu > JUMBO_1K &&
2032 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2033 features &= ~NETIF_F_IP_CSUM;
2038 static void __rtl8169_set_features(struct net_device *dev,
2039 netdev_features_t features)
2041 struct rtl8169_private *tp = netdev_priv(dev);
2042 void __iomem *ioaddr = tp->mmio_addr;
2045 rx_config = RTL_R32(RxConfig);
2046 if (features & NETIF_F_RXALL)
2047 rx_config |= (AcceptErr | AcceptRunt);
2049 rx_config &= ~(AcceptErr | AcceptRunt);
2051 RTL_W32(RxConfig, rx_config);
2053 if (features & NETIF_F_RXCSUM)
2054 tp->cp_cmd |= RxChkSum;
2056 tp->cp_cmd &= ~RxChkSum;
2058 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2059 tp->cp_cmd |= RxVlan;
2061 tp->cp_cmd &= ~RxVlan;
2063 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2065 RTL_W16(CPlusCmd, tp->cp_cmd);
2069 static int rtl8169_set_features(struct net_device *dev,
2070 netdev_features_t features)
2072 struct rtl8169_private *tp = netdev_priv(dev);
2074 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2077 if (features ^ dev->features)
2078 __rtl8169_set_features(dev, features);
2079 rtl_unlock_work(tp);
2085 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2087 return (skb_vlan_tag_present(skb)) ?
2088 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2091 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2093 u32 opts2 = le32_to_cpu(desc->opts2);
2095 if (opts2 & RxVlanTag)
2096 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2099 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2101 struct rtl8169_private *tp = netdev_priv(dev);
2102 void __iomem *ioaddr = tp->mmio_addr;
2106 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2107 cmd->port = PORT_FIBRE;
2108 cmd->transceiver = XCVR_INTERNAL;
2110 status = RTL_R32(TBICSR);
2111 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2112 cmd->autoneg = !!(status & TBINwEnable);
2114 ethtool_cmd_speed_set(cmd, SPEED_1000);
2115 cmd->duplex = DUPLEX_FULL; /* Always set */
2120 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2122 struct rtl8169_private *tp = netdev_priv(dev);
2124 return mii_ethtool_gset(&tp->mii, cmd);
2127 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2129 struct rtl8169_private *tp = netdev_priv(dev);
2133 rc = tp->get_settings(dev, cmd);
2134 rtl_unlock_work(tp);
2139 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2142 struct rtl8169_private *tp = netdev_priv(dev);
2143 u32 __iomem *data = tp->mmio_addr;
2148 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2149 memcpy_fromio(dw++, data++, 4);
2150 rtl_unlock_work(tp);
2153 static u32 rtl8169_get_msglevel(struct net_device *dev)
2155 struct rtl8169_private *tp = netdev_priv(dev);
2157 return tp->msg_enable;
2160 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2162 struct rtl8169_private *tp = netdev_priv(dev);
2164 tp->msg_enable = value;
2167 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2174 "tx_single_collisions",
2175 "tx_multi_collisions",
2183 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2187 return ARRAY_SIZE(rtl8169_gstrings);
2193 static struct rtl8169_counters *rtl8169_map_counters(struct net_device *dev,
2197 struct rtl8169_private *tp = netdev_priv(dev);
2198 void __iomem *ioaddr = tp->mmio_addr;
2199 struct device *d = &tp->pci_dev->dev;
2200 struct rtl8169_counters *counters;
2203 counters = dma_alloc_coherent(d, sizeof(*counters), paddr, GFP_KERNEL);
2205 RTL_W32(CounterAddrHigh, (u64)*paddr >> 32);
2206 cmd = (u64)*paddr & DMA_BIT_MASK(32);
2207 RTL_W32(CounterAddrLow, cmd);
2208 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2213 static void rtl8169_unmap_counters (struct net_device *dev,
2215 struct rtl8169_counters *counters)
2217 struct rtl8169_private *tp = netdev_priv(dev);
2218 void __iomem *ioaddr = tp->mmio_addr;
2219 struct device *d = &tp->pci_dev->dev;
2221 RTL_W32(CounterAddrLow, 0);
2222 RTL_W32(CounterAddrHigh, 0);
2224 dma_free_coherent(d, sizeof(*counters), counters, paddr);
2227 DECLARE_RTL_COND(rtl_reset_counters_cond)
2229 void __iomem *ioaddr = tp->mmio_addr;
2231 return RTL_R32(CounterAddrLow) & CounterReset;
2234 static bool rtl8169_reset_counters(struct net_device *dev)
2236 struct rtl8169_private *tp = netdev_priv(dev);
2237 struct rtl8169_counters *counters;
2242 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2245 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2248 counters = rtl8169_map_counters(dev, &paddr, CounterReset);
2252 if (!rtl_udelay_loop_wait_low(tp, &rtl_reset_counters_cond, 10, 1000))
2255 rtl8169_unmap_counters(dev, paddr, counters);
2260 DECLARE_RTL_COND(rtl_counters_cond)
2262 void __iomem *ioaddr = tp->mmio_addr;
2264 return RTL_R32(CounterAddrLow) & CounterDump;
2267 static bool rtl8169_update_counters(struct net_device *dev)
2269 struct rtl8169_private *tp = netdev_priv(dev);
2270 void __iomem *ioaddr = tp->mmio_addr;
2271 struct rtl8169_counters *counters;
2276 * Some chips are unable to dump tally counters when the receiver
2279 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2282 counters = rtl8169_map_counters(dev, &paddr, CounterDump);
2286 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2287 memcpy(&tp->counters, counters, sizeof(*counters));
2291 rtl8169_unmap_counters(dev, paddr, counters);
2296 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2298 struct rtl8169_private *tp = netdev_priv(dev);
2302 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2303 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2304 * reset by a power cycle, while the counter values collected by the
2305 * driver are reset at every driver unload/load cycle.
2307 * To make sure the HW values returned by @get_stats64 match the SW
2308 * values, we collect the initial values at first open(*) and use them
2309 * as offsets to normalize the values returned by @get_stats64.
2311 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2312 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2313 * set at open time by rtl_hw_start.
2316 if (tp->tc_offset.inited)
2319 /* If both, reset and update fail, propagate to caller. */
2320 if (rtl8169_reset_counters(dev))
2323 if (rtl8169_update_counters(dev))
2326 tp->tc_offset.tx_errors = tp->counters.tx_errors;
2327 tp->tc_offset.tx_multi_collision = tp->counters.tx_multi_collision;
2328 tp->tc_offset.tx_aborted = tp->counters.tx_aborted;
2329 tp->tc_offset.inited = true;
2334 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2335 struct ethtool_stats *stats, u64 *data)
2337 struct rtl8169_private *tp = netdev_priv(dev);
2341 rtl8169_update_counters(dev);
2343 data[0] = le64_to_cpu(tp->counters.tx_packets);
2344 data[1] = le64_to_cpu(tp->counters.rx_packets);
2345 data[2] = le64_to_cpu(tp->counters.tx_errors);
2346 data[3] = le32_to_cpu(tp->counters.rx_errors);
2347 data[4] = le16_to_cpu(tp->counters.rx_missed);
2348 data[5] = le16_to_cpu(tp->counters.align_errors);
2349 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2350 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2351 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2352 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2353 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2354 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2355 data[12] = le16_to_cpu(tp->counters.tx_underun);
2358 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2362 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2367 static const struct ethtool_ops rtl8169_ethtool_ops = {
2368 .get_drvinfo = rtl8169_get_drvinfo,
2369 .get_regs_len = rtl8169_get_regs_len,
2370 .get_link = ethtool_op_get_link,
2371 .get_settings = rtl8169_get_settings,
2372 .set_settings = rtl8169_set_settings,
2373 .get_msglevel = rtl8169_get_msglevel,
2374 .set_msglevel = rtl8169_set_msglevel,
2375 .get_regs = rtl8169_get_regs,
2376 .get_wol = rtl8169_get_wol,
2377 .set_wol = rtl8169_set_wol,
2378 .get_strings = rtl8169_get_strings,
2379 .get_sset_count = rtl8169_get_sset_count,
2380 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2381 .get_ts_info = ethtool_op_get_ts_info,
2384 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2385 struct net_device *dev, u8 default_version)
2387 void __iomem *ioaddr = tp->mmio_addr;
2389 * The driver currently handles the 8168Bf and the 8168Be identically
2390 * but they can be identified more specifically through the test below
2393 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2395 * Same thing for the 8101Eb and the 8101Ec:
2397 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2399 static const struct rtl_mac_info {
2404 /* 8168EP family. */
2405 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2406 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2407 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2410 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2411 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2414 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2415 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2416 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2417 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2420 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2421 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2422 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2425 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2426 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2427 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2428 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2431 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2432 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2433 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2435 /* 8168DP family. */
2436 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2437 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2438 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2441 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2442 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2443 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2444 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2445 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2446 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2447 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2448 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2449 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2452 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2453 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2454 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2455 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2458 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2459 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2460 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2461 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2462 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2463 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2464 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2465 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2466 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2467 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2468 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2469 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2470 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2471 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2472 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2473 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2474 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2475 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2476 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2477 /* FIXME: where did these entries come from ? -- FR */
2478 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2479 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2482 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2483 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2484 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2485 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2486 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2487 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2490 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2492 const struct rtl_mac_info *p = mac_info;
2495 reg = RTL_R32(TxConfig);
2496 while ((reg & p->mask) != p->val)
2498 tp->mac_version = p->mac_version;
2500 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2501 netif_notice(tp, probe, dev,
2502 "unknown MAC, using family default\n");
2503 tp->mac_version = default_version;
2504 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2505 tp->mac_version = tp->mii.supports_gmii ?
2506 RTL_GIGA_MAC_VER_42 :
2507 RTL_GIGA_MAC_VER_43;
2508 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2509 tp->mac_version = tp->mii.supports_gmii ?
2510 RTL_GIGA_MAC_VER_45 :
2511 RTL_GIGA_MAC_VER_47;
2512 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2513 tp->mac_version = tp->mii.supports_gmii ?
2514 RTL_GIGA_MAC_VER_46 :
2515 RTL_GIGA_MAC_VER_48;
2519 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2521 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2529 static void rtl_writephy_batch(struct rtl8169_private *tp,
2530 const struct phy_reg *regs, int len)
2533 rtl_writephy(tp, regs->reg, regs->val);
2538 #define PHY_READ 0x00000000
2539 #define PHY_DATA_OR 0x10000000
2540 #define PHY_DATA_AND 0x20000000
2541 #define PHY_BJMPN 0x30000000
2542 #define PHY_MDIO_CHG 0x40000000
2543 #define PHY_CLEAR_READCOUNT 0x70000000
2544 #define PHY_WRITE 0x80000000
2545 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2546 #define PHY_COMP_EQ_SKIPN 0xa0000000
2547 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2548 #define PHY_WRITE_PREVIOUS 0xc0000000
2549 #define PHY_SKIPN 0xd0000000
2550 #define PHY_DELAY_MS 0xe0000000
2554 char version[RTL_VER_SIZE];
2560 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2562 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2564 const struct firmware *fw = rtl_fw->fw;
2565 struct fw_info *fw_info = (struct fw_info *)fw->data;
2566 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2567 char *version = rtl_fw->version;
2570 if (fw->size < FW_OPCODE_SIZE)
2573 if (!fw_info->magic) {
2574 size_t i, size, start;
2577 if (fw->size < sizeof(*fw_info))
2580 for (i = 0; i < fw->size; i++)
2581 checksum += fw->data[i];
2585 start = le32_to_cpu(fw_info->fw_start);
2586 if (start > fw->size)
2589 size = le32_to_cpu(fw_info->fw_len);
2590 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2593 memcpy(version, fw_info->version, RTL_VER_SIZE);
2595 pa->code = (__le32 *)(fw->data + start);
2598 if (fw->size % FW_OPCODE_SIZE)
2601 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2603 pa->code = (__le32 *)fw->data;
2604 pa->size = fw->size / FW_OPCODE_SIZE;
2606 version[RTL_VER_SIZE - 1] = 0;
2613 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2614 struct rtl_fw_phy_action *pa)
2619 for (index = 0; index < pa->size; index++) {
2620 u32 action = le32_to_cpu(pa->code[index]);
2621 u32 regno = (action & 0x0fff0000) >> 16;
2623 switch(action & 0xf0000000) {
2628 case PHY_CLEAR_READCOUNT:
2630 case PHY_WRITE_PREVIOUS:
2635 if (regno > index) {
2636 netif_err(tp, ifup, tp->dev,
2637 "Out of range of firmware\n");
2641 case PHY_READCOUNT_EQ_SKIP:
2642 if (index + 2 >= pa->size) {
2643 netif_err(tp, ifup, tp->dev,
2644 "Out of range of firmware\n");
2648 case PHY_COMP_EQ_SKIPN:
2649 case PHY_COMP_NEQ_SKIPN:
2651 if (index + 1 + regno >= pa->size) {
2652 netif_err(tp, ifup, tp->dev,
2653 "Out of range of firmware\n");
2659 netif_err(tp, ifup, tp->dev,
2660 "Invalid action 0x%08x\n", action);
2669 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2671 struct net_device *dev = tp->dev;
2674 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2675 netif_err(tp, ifup, dev, "invalid firmware\n");
2679 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2685 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2687 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2688 struct mdio_ops org, *ops = &tp->mdio_ops;
2692 predata = count = 0;
2693 org.write = ops->write;
2694 org.read = ops->read;
2696 for (index = 0; index < pa->size; ) {
2697 u32 action = le32_to_cpu(pa->code[index]);
2698 u32 data = action & 0x0000ffff;
2699 u32 regno = (action & 0x0fff0000) >> 16;
2704 switch(action & 0xf0000000) {
2706 predata = rtl_readphy(tp, regno);
2723 ops->write = org.write;
2724 ops->read = org.read;
2725 } else if (data == 1) {
2726 ops->write = mac_mcu_write;
2727 ops->read = mac_mcu_read;
2732 case PHY_CLEAR_READCOUNT:
2737 rtl_writephy(tp, regno, data);
2740 case PHY_READCOUNT_EQ_SKIP:
2741 index += (count == data) ? 2 : 1;
2743 case PHY_COMP_EQ_SKIPN:
2744 if (predata == data)
2748 case PHY_COMP_NEQ_SKIPN:
2749 if (predata != data)
2753 case PHY_WRITE_PREVIOUS:
2754 rtl_writephy(tp, regno, predata);
2770 ops->write = org.write;
2771 ops->read = org.read;
2774 static void rtl_release_firmware(struct rtl8169_private *tp)
2776 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2777 release_firmware(tp->rtl_fw->fw);
2780 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2783 static void rtl_apply_firmware(struct rtl8169_private *tp)
2785 struct rtl_fw *rtl_fw = tp->rtl_fw;
2787 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2788 if (!IS_ERR_OR_NULL(rtl_fw))
2789 rtl_phy_write_fw(tp, rtl_fw);
2792 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2794 if (rtl_readphy(tp, reg) != val)
2795 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2797 rtl_apply_firmware(tp);
2800 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2802 static const struct phy_reg phy_reg_init[] = {
2864 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2867 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2869 static const struct phy_reg phy_reg_init[] = {
2875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2878 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2880 struct pci_dev *pdev = tp->pci_dev;
2882 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2883 (pdev->subsystem_device != 0xe000))
2886 rtl_writephy(tp, 0x1f, 0x0001);
2887 rtl_writephy(tp, 0x10, 0xf01b);
2888 rtl_writephy(tp, 0x1f, 0x0000);
2891 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2893 static const struct phy_reg phy_reg_init[] = {
2933 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2935 rtl8169scd_hw_phy_config_quirk(tp);
2938 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2940 static const struct phy_reg phy_reg_init[] = {
2988 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2991 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2993 static const struct phy_reg phy_reg_init[] = {
2998 rtl_writephy(tp, 0x1f, 0x0001);
2999 rtl_patchphy(tp, 0x16, 1 << 0);
3001 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3004 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3006 static const struct phy_reg phy_reg_init[] = {
3012 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3015 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3017 static const struct phy_reg phy_reg_init[] = {
3025 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3028 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3030 static const struct phy_reg phy_reg_init[] = {
3036 rtl_writephy(tp, 0x1f, 0x0000);
3037 rtl_patchphy(tp, 0x14, 1 << 5);
3038 rtl_patchphy(tp, 0x0d, 1 << 5);
3040 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3043 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3045 static const struct phy_reg phy_reg_init[] = {
3065 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3067 rtl_patchphy(tp, 0x14, 1 << 5);
3068 rtl_patchphy(tp, 0x0d, 1 << 5);
3069 rtl_writephy(tp, 0x1f, 0x0000);
3072 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3074 static const struct phy_reg phy_reg_init[] = {
3092 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3094 rtl_patchphy(tp, 0x16, 1 << 0);
3095 rtl_patchphy(tp, 0x14, 1 << 5);
3096 rtl_patchphy(tp, 0x0d, 1 << 5);
3097 rtl_writephy(tp, 0x1f, 0x0000);
3100 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3102 static const struct phy_reg phy_reg_init[] = {
3114 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3116 rtl_patchphy(tp, 0x16, 1 << 0);
3117 rtl_patchphy(tp, 0x14, 1 << 5);
3118 rtl_patchphy(tp, 0x0d, 1 << 5);
3119 rtl_writephy(tp, 0x1f, 0x0000);
3122 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3124 rtl8168c_3_hw_phy_config(tp);
3127 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3129 static const struct phy_reg phy_reg_init_0[] = {
3130 /* Channel Estimation */
3151 * Enhance line driver power
3160 * Can not link to 1Gbps with bad cable
3161 * Decrease SNR threshold form 21.07dB to 19.04dB
3170 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3174 * Fine Tune Switching regulator parameter
3176 rtl_writephy(tp, 0x1f, 0x0002);
3177 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3178 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3180 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3181 static const struct phy_reg phy_reg_init[] = {
3191 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3193 val = rtl_readphy(tp, 0x0d);
3195 if ((val & 0x00ff) != 0x006c) {
3196 static const u32 set[] = {
3197 0x0065, 0x0066, 0x0067, 0x0068,
3198 0x0069, 0x006a, 0x006b, 0x006c
3202 rtl_writephy(tp, 0x1f, 0x0002);
3205 for (i = 0; i < ARRAY_SIZE(set); i++)
3206 rtl_writephy(tp, 0x0d, val | set[i]);
3209 static const struct phy_reg phy_reg_init[] = {
3217 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3220 /* RSET couple improve */
3221 rtl_writephy(tp, 0x1f, 0x0002);
3222 rtl_patchphy(tp, 0x0d, 0x0300);
3223 rtl_patchphy(tp, 0x0f, 0x0010);
3225 /* Fine tune PLL performance */
3226 rtl_writephy(tp, 0x1f, 0x0002);
3227 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3228 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3230 rtl_writephy(tp, 0x1f, 0x0005);
3231 rtl_writephy(tp, 0x05, 0x001b);
3233 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3235 rtl_writephy(tp, 0x1f, 0x0000);
3238 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3240 static const struct phy_reg phy_reg_init_0[] = {
3241 /* Channel Estimation */
3262 * Enhance line driver power
3271 * Can not link to 1Gbps with bad cable
3272 * Decrease SNR threshold form 21.07dB to 19.04dB
3281 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3283 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3284 static const struct phy_reg phy_reg_init[] = {
3295 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3297 val = rtl_readphy(tp, 0x0d);
3298 if ((val & 0x00ff) != 0x006c) {
3299 static const u32 set[] = {
3300 0x0065, 0x0066, 0x0067, 0x0068,
3301 0x0069, 0x006a, 0x006b, 0x006c
3305 rtl_writephy(tp, 0x1f, 0x0002);
3308 for (i = 0; i < ARRAY_SIZE(set); i++)
3309 rtl_writephy(tp, 0x0d, val | set[i]);
3312 static const struct phy_reg phy_reg_init[] = {
3320 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3323 /* Fine tune PLL performance */
3324 rtl_writephy(tp, 0x1f, 0x0002);
3325 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3326 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3328 /* Switching regulator Slew rate */
3329 rtl_writephy(tp, 0x1f, 0x0002);
3330 rtl_patchphy(tp, 0x0f, 0x0017);
3332 rtl_writephy(tp, 0x1f, 0x0005);
3333 rtl_writephy(tp, 0x05, 0x001b);
3335 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3337 rtl_writephy(tp, 0x1f, 0x0000);
3340 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3342 static const struct phy_reg phy_reg_init[] = {
3398 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3401 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3403 static const struct phy_reg phy_reg_init[] = {
3413 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3414 rtl_patchphy(tp, 0x0d, 1 << 5);
3417 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3419 static const struct phy_reg phy_reg_init[] = {
3420 /* Enable Delay cap */
3426 /* Channel estimation fine tune */
3435 /* Update PFM & 10M TX idle timer */
3447 rtl_apply_firmware(tp);
3449 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3451 /* DCO enable for 10M IDLE Power */
3452 rtl_writephy(tp, 0x1f, 0x0007);
3453 rtl_writephy(tp, 0x1e, 0x0023);
3454 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3455 rtl_writephy(tp, 0x1f, 0x0000);
3457 /* For impedance matching */
3458 rtl_writephy(tp, 0x1f, 0x0002);
3459 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3460 rtl_writephy(tp, 0x1f, 0x0000);
3462 /* PHY auto speed down */
3463 rtl_writephy(tp, 0x1f, 0x0007);
3464 rtl_writephy(tp, 0x1e, 0x002d);
3465 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3466 rtl_writephy(tp, 0x1f, 0x0000);
3467 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3469 rtl_writephy(tp, 0x1f, 0x0005);
3470 rtl_writephy(tp, 0x05, 0x8b86);
3471 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3472 rtl_writephy(tp, 0x1f, 0x0000);
3474 rtl_writephy(tp, 0x1f, 0x0005);
3475 rtl_writephy(tp, 0x05, 0x8b85);
3476 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3477 rtl_writephy(tp, 0x1f, 0x0007);
3478 rtl_writephy(tp, 0x1e, 0x0020);
3479 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3480 rtl_writephy(tp, 0x1f, 0x0006);
3481 rtl_writephy(tp, 0x00, 0x5a00);
3482 rtl_writephy(tp, 0x1f, 0x0000);
3483 rtl_writephy(tp, 0x0d, 0x0007);
3484 rtl_writephy(tp, 0x0e, 0x003c);
3485 rtl_writephy(tp, 0x0d, 0x4007);
3486 rtl_writephy(tp, 0x0e, 0x0000);
3487 rtl_writephy(tp, 0x0d, 0x0000);
3490 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3493 addr[0] | (addr[1] << 8),
3494 addr[2] | (addr[3] << 8),
3495 addr[4] | (addr[5] << 8)
3497 const struct exgmac_reg e[] = {
3498 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3499 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3500 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3501 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3504 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3507 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3509 static const struct phy_reg phy_reg_init[] = {
3510 /* Enable Delay cap */
3519 /* Channel estimation fine tune */
3536 rtl_apply_firmware(tp);
3538 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3540 /* For 4-corner performance improve */
3541 rtl_writephy(tp, 0x1f, 0x0005);
3542 rtl_writephy(tp, 0x05, 0x8b80);
3543 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3544 rtl_writephy(tp, 0x1f, 0x0000);
3546 /* PHY auto speed down */
3547 rtl_writephy(tp, 0x1f, 0x0004);
3548 rtl_writephy(tp, 0x1f, 0x0007);
3549 rtl_writephy(tp, 0x1e, 0x002d);
3550 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3551 rtl_writephy(tp, 0x1f, 0x0002);
3552 rtl_writephy(tp, 0x1f, 0x0000);
3553 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3555 /* improve 10M EEE waveform */
3556 rtl_writephy(tp, 0x1f, 0x0005);
3557 rtl_writephy(tp, 0x05, 0x8b86);
3558 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3559 rtl_writephy(tp, 0x1f, 0x0000);
3561 /* Improve 2-pair detection performance */
3562 rtl_writephy(tp, 0x1f, 0x0005);
3563 rtl_writephy(tp, 0x05, 0x8b85);
3564 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3565 rtl_writephy(tp, 0x1f, 0x0000);
3568 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3569 rtl_writephy(tp, 0x1f, 0x0005);
3570 rtl_writephy(tp, 0x05, 0x8b85);
3571 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3572 rtl_writephy(tp, 0x1f, 0x0004);
3573 rtl_writephy(tp, 0x1f, 0x0007);
3574 rtl_writephy(tp, 0x1e, 0x0020);
3575 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3576 rtl_writephy(tp, 0x1f, 0x0002);
3577 rtl_writephy(tp, 0x1f, 0x0000);
3578 rtl_writephy(tp, 0x0d, 0x0007);
3579 rtl_writephy(tp, 0x0e, 0x003c);
3580 rtl_writephy(tp, 0x0d, 0x4007);
3581 rtl_writephy(tp, 0x0e, 0x0000);
3582 rtl_writephy(tp, 0x0d, 0x0000);
3585 rtl_writephy(tp, 0x1f, 0x0003);
3586 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3587 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3588 rtl_writephy(tp, 0x1f, 0x0000);
3590 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3591 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3594 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3596 /* For 4-corner performance improve */
3597 rtl_writephy(tp, 0x1f, 0x0005);
3598 rtl_writephy(tp, 0x05, 0x8b80);
3599 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3600 rtl_writephy(tp, 0x1f, 0x0000);
3602 /* PHY auto speed down */
3603 rtl_writephy(tp, 0x1f, 0x0007);
3604 rtl_writephy(tp, 0x1e, 0x002d);
3605 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3606 rtl_writephy(tp, 0x1f, 0x0000);
3607 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3609 /* Improve 10M EEE waveform */
3610 rtl_writephy(tp, 0x1f, 0x0005);
3611 rtl_writephy(tp, 0x05, 0x8b86);
3612 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3613 rtl_writephy(tp, 0x1f, 0x0000);
3616 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3618 static const struct phy_reg phy_reg_init[] = {
3619 /* Channel estimation fine tune */
3624 /* Modify green table for giga & fnet */
3641 /* Modify green table for 10M */
3647 /* Disable hiimpedance detection (RTCT) */
3653 rtl_apply_firmware(tp);
3655 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3657 rtl8168f_hw_phy_config(tp);
3659 /* Improve 2-pair detection performance */
3660 rtl_writephy(tp, 0x1f, 0x0005);
3661 rtl_writephy(tp, 0x05, 0x8b85);
3662 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3663 rtl_writephy(tp, 0x1f, 0x0000);
3666 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3668 rtl_apply_firmware(tp);
3670 rtl8168f_hw_phy_config(tp);
3673 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3675 static const struct phy_reg phy_reg_init[] = {
3676 /* Channel estimation fine tune */
3681 /* Modify green table for giga & fnet */
3698 /* Modify green table for 10M */
3704 /* Disable hiimpedance detection (RTCT) */
3711 rtl_apply_firmware(tp);
3713 rtl8168f_hw_phy_config(tp);
3715 /* Improve 2-pair detection performance */
3716 rtl_writephy(tp, 0x1f, 0x0005);
3717 rtl_writephy(tp, 0x05, 0x8b85);
3718 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3719 rtl_writephy(tp, 0x1f, 0x0000);
3721 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3723 /* Modify green table for giga */
3724 rtl_writephy(tp, 0x1f, 0x0005);
3725 rtl_writephy(tp, 0x05, 0x8b54);
3726 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3727 rtl_writephy(tp, 0x05, 0x8b5d);
3728 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3729 rtl_writephy(tp, 0x05, 0x8a7c);
3730 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3731 rtl_writephy(tp, 0x05, 0x8a7f);
3732 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3733 rtl_writephy(tp, 0x05, 0x8a82);
3734 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3735 rtl_writephy(tp, 0x05, 0x8a85);
3736 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3737 rtl_writephy(tp, 0x05, 0x8a88);
3738 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3739 rtl_writephy(tp, 0x1f, 0x0000);
3741 /* uc same-seed solution */
3742 rtl_writephy(tp, 0x1f, 0x0005);
3743 rtl_writephy(tp, 0x05, 0x8b85);
3744 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3745 rtl_writephy(tp, 0x1f, 0x0000);
3748 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3749 rtl_writephy(tp, 0x1f, 0x0005);
3750 rtl_writephy(tp, 0x05, 0x8b85);
3751 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3752 rtl_writephy(tp, 0x1f, 0x0004);
3753 rtl_writephy(tp, 0x1f, 0x0007);
3754 rtl_writephy(tp, 0x1e, 0x0020);
3755 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3756 rtl_writephy(tp, 0x1f, 0x0000);
3757 rtl_writephy(tp, 0x0d, 0x0007);
3758 rtl_writephy(tp, 0x0e, 0x003c);
3759 rtl_writephy(tp, 0x0d, 0x4007);
3760 rtl_writephy(tp, 0x0e, 0x0000);
3761 rtl_writephy(tp, 0x0d, 0x0000);
3764 rtl_writephy(tp, 0x1f, 0x0003);
3765 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3766 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3767 rtl_writephy(tp, 0x1f, 0x0000);
3770 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3772 rtl_apply_firmware(tp);
3774 rtl_writephy(tp, 0x1f, 0x0a46);
3775 if (rtl_readphy(tp, 0x10) & 0x0100) {
3776 rtl_writephy(tp, 0x1f, 0x0bcc);
3777 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3779 rtl_writephy(tp, 0x1f, 0x0bcc);
3780 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3783 rtl_writephy(tp, 0x1f, 0x0a46);
3784 if (rtl_readphy(tp, 0x13) & 0x0100) {
3785 rtl_writephy(tp, 0x1f, 0x0c41);
3786 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3788 rtl_writephy(tp, 0x1f, 0x0c41);
3789 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3792 /* Enable PHY auto speed down */
3793 rtl_writephy(tp, 0x1f, 0x0a44);
3794 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3796 rtl_writephy(tp, 0x1f, 0x0bcc);
3797 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3798 rtl_writephy(tp, 0x1f, 0x0a44);
3799 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3800 rtl_writephy(tp, 0x1f, 0x0a43);
3801 rtl_writephy(tp, 0x13, 0x8084);
3802 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3803 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3805 /* EEE auto-fallback function */
3806 rtl_writephy(tp, 0x1f, 0x0a4b);
3807 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3809 /* Enable UC LPF tune function */
3810 rtl_writephy(tp, 0x1f, 0x0a43);
3811 rtl_writephy(tp, 0x13, 0x8012);
3812 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3814 rtl_writephy(tp, 0x1f, 0x0c42);
3815 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3817 /* Improve SWR Efficiency */
3818 rtl_writephy(tp, 0x1f, 0x0bcd);
3819 rtl_writephy(tp, 0x14, 0x5065);
3820 rtl_writephy(tp, 0x14, 0xd065);
3821 rtl_writephy(tp, 0x1f, 0x0bc8);
3822 rtl_writephy(tp, 0x11, 0x5655);
3823 rtl_writephy(tp, 0x1f, 0x0bcd);
3824 rtl_writephy(tp, 0x14, 0x1065);
3825 rtl_writephy(tp, 0x14, 0x9065);
3826 rtl_writephy(tp, 0x14, 0x1065);
3828 /* Check ALDPS bit, disable it if enabled */
3829 rtl_writephy(tp, 0x1f, 0x0a43);
3830 if (rtl_readphy(tp, 0x10) & 0x0004)
3831 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3833 rtl_writephy(tp, 0x1f, 0x0000);
3836 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3838 rtl_apply_firmware(tp);
3841 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3846 rtl_apply_firmware(tp);
3848 /* CHN EST parameters adjust - giga master */
3849 rtl_writephy(tp, 0x1f, 0x0a43);
3850 rtl_writephy(tp, 0x13, 0x809b);
3851 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3852 rtl_writephy(tp, 0x13, 0x80a2);
3853 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3854 rtl_writephy(tp, 0x13, 0x80a4);
3855 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3856 rtl_writephy(tp, 0x13, 0x809c);
3857 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3858 rtl_writephy(tp, 0x1f, 0x0000);
3860 /* CHN EST parameters adjust - giga slave */
3861 rtl_writephy(tp, 0x1f, 0x0a43);
3862 rtl_writephy(tp, 0x13, 0x80ad);
3863 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3864 rtl_writephy(tp, 0x13, 0x80b4);
3865 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3866 rtl_writephy(tp, 0x13, 0x80ac);
3867 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3868 rtl_writephy(tp, 0x1f, 0x0000);
3870 /* CHN EST parameters adjust - fnet */
3871 rtl_writephy(tp, 0x1f, 0x0a43);
3872 rtl_writephy(tp, 0x13, 0x808e);
3873 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3874 rtl_writephy(tp, 0x13, 0x8090);
3875 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3876 rtl_writephy(tp, 0x13, 0x8092);
3877 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3878 rtl_writephy(tp, 0x1f, 0x0000);
3880 /* enable R-tune & PGA-retune function */
3882 rtl_writephy(tp, 0x1f, 0x0a46);
3883 data = rtl_readphy(tp, 0x13);
3886 dout_tapbin |= data;
3887 data = rtl_readphy(tp, 0x12);
3890 dout_tapbin |= data;
3891 dout_tapbin = ~(dout_tapbin^0x08);
3893 dout_tapbin &= 0xf000;
3894 rtl_writephy(tp, 0x1f, 0x0a43);
3895 rtl_writephy(tp, 0x13, 0x827a);
3896 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3897 rtl_writephy(tp, 0x13, 0x827b);
3898 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3899 rtl_writephy(tp, 0x13, 0x827c);
3900 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3901 rtl_writephy(tp, 0x13, 0x827d);
3902 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3904 rtl_writephy(tp, 0x1f, 0x0a43);
3905 rtl_writephy(tp, 0x13, 0x0811);
3906 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3907 rtl_writephy(tp, 0x1f, 0x0a42);
3908 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3909 rtl_writephy(tp, 0x1f, 0x0000);
3911 /* enable GPHY 10M */
3912 rtl_writephy(tp, 0x1f, 0x0a44);
3913 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3914 rtl_writephy(tp, 0x1f, 0x0000);
3916 /* SAR ADC performance */
3917 rtl_writephy(tp, 0x1f, 0x0bca);
3918 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3919 rtl_writephy(tp, 0x1f, 0x0000);
3921 rtl_writephy(tp, 0x1f, 0x0a43);
3922 rtl_writephy(tp, 0x13, 0x803f);
3923 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3924 rtl_writephy(tp, 0x13, 0x8047);
3925 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3926 rtl_writephy(tp, 0x13, 0x804f);
3927 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3928 rtl_writephy(tp, 0x13, 0x8057);
3929 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3930 rtl_writephy(tp, 0x13, 0x805f);
3931 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3932 rtl_writephy(tp, 0x13, 0x8067);
3933 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3934 rtl_writephy(tp, 0x13, 0x806f);
3935 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3936 rtl_writephy(tp, 0x1f, 0x0000);
3938 /* disable phy pfm mode */
3939 rtl_writephy(tp, 0x1f, 0x0a44);
3940 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3941 rtl_writephy(tp, 0x1f, 0x0000);
3943 /* Check ALDPS bit, disable it if enabled */
3944 rtl_writephy(tp, 0x1f, 0x0a43);
3945 if (rtl_readphy(tp, 0x10) & 0x0004)
3946 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3948 rtl_writephy(tp, 0x1f, 0x0000);
3951 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3953 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3957 rtl_apply_firmware(tp);
3959 /* CHIN EST parameter update */
3960 rtl_writephy(tp, 0x1f, 0x0a43);
3961 rtl_writephy(tp, 0x13, 0x808a);
3962 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3963 rtl_writephy(tp, 0x1f, 0x0000);
3965 /* enable R-tune & PGA-retune function */
3966 rtl_writephy(tp, 0x1f, 0x0a43);
3967 rtl_writephy(tp, 0x13, 0x0811);
3968 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3969 rtl_writephy(tp, 0x1f, 0x0a42);
3970 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3971 rtl_writephy(tp, 0x1f, 0x0000);
3973 /* enable GPHY 10M */
3974 rtl_writephy(tp, 0x1f, 0x0a44);
3975 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3976 rtl_writephy(tp, 0x1f, 0x0000);
3978 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3979 data = r8168_mac_ocp_read(tp, 0xdd02);
3980 ioffset_p3 = ((data & 0x80)>>7);
3983 data = r8168_mac_ocp_read(tp, 0xdd00);
3984 ioffset_p3 |= ((data & (0xe000))>>13);
3985 ioffset_p2 = ((data & (0x1e00))>>9);
3986 ioffset_p1 = ((data & (0x01e0))>>5);
3987 ioffset_p0 = ((data & 0x0010)>>4);
3989 ioffset_p0 |= (data & (0x07));
3990 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3992 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3993 (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3994 rtl_writephy(tp, 0x1f, 0x0bcf);
3995 rtl_writephy(tp, 0x16, data);
3996 rtl_writephy(tp, 0x1f, 0x0000);
3999 /* Modify rlen (TX LPF corner frequency) level */
4000 rtl_writephy(tp, 0x1f, 0x0bcd);
4001 data = rtl_readphy(tp, 0x16);
4006 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4007 rtl_writephy(tp, 0x17, data);
4008 rtl_writephy(tp, 0x1f, 0x0bcd);
4009 rtl_writephy(tp, 0x1f, 0x0000);
4011 /* disable phy pfm mode */
4012 rtl_writephy(tp, 0x1f, 0x0a44);
4013 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
4014 rtl_writephy(tp, 0x1f, 0x0000);
4016 /* Check ALDPS bit, disable it if enabled */
4017 rtl_writephy(tp, 0x1f, 0x0a43);
4018 if (rtl_readphy(tp, 0x10) & 0x0004)
4019 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4021 rtl_writephy(tp, 0x1f, 0x0000);
4024 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4026 /* Enable PHY auto speed down */
4027 rtl_writephy(tp, 0x1f, 0x0a44);
4028 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4029 rtl_writephy(tp, 0x1f, 0x0000);
4031 /* patch 10M & ALDPS */
4032 rtl_writephy(tp, 0x1f, 0x0bcc);
4033 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4034 rtl_writephy(tp, 0x1f, 0x0a44);
4035 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4036 rtl_writephy(tp, 0x1f, 0x0a43);
4037 rtl_writephy(tp, 0x13, 0x8084);
4038 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4039 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4040 rtl_writephy(tp, 0x1f, 0x0000);
4042 /* Enable EEE auto-fallback function */
4043 rtl_writephy(tp, 0x1f, 0x0a4b);
4044 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4045 rtl_writephy(tp, 0x1f, 0x0000);
4047 /* Enable UC LPF tune function */
4048 rtl_writephy(tp, 0x1f, 0x0a43);
4049 rtl_writephy(tp, 0x13, 0x8012);
4050 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4051 rtl_writephy(tp, 0x1f, 0x0000);
4053 /* set rg_sel_sdm_rate */
4054 rtl_writephy(tp, 0x1f, 0x0c42);
4055 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4056 rtl_writephy(tp, 0x1f, 0x0000);
4058 /* Check ALDPS bit, disable it if enabled */
4059 rtl_writephy(tp, 0x1f, 0x0a43);
4060 if (rtl_readphy(tp, 0x10) & 0x0004)
4061 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4063 rtl_writephy(tp, 0x1f, 0x0000);
4066 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4068 /* patch 10M & ALDPS */
4069 rtl_writephy(tp, 0x1f, 0x0bcc);
4070 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4071 rtl_writephy(tp, 0x1f, 0x0a44);
4072 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4073 rtl_writephy(tp, 0x1f, 0x0a43);
4074 rtl_writephy(tp, 0x13, 0x8084);
4075 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4076 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4077 rtl_writephy(tp, 0x1f, 0x0000);
4079 /* Enable UC LPF tune function */
4080 rtl_writephy(tp, 0x1f, 0x0a43);
4081 rtl_writephy(tp, 0x13, 0x8012);
4082 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4083 rtl_writephy(tp, 0x1f, 0x0000);
4085 /* Set rg_sel_sdm_rate */
4086 rtl_writephy(tp, 0x1f, 0x0c42);
4087 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4088 rtl_writephy(tp, 0x1f, 0x0000);
4090 /* Channel estimation parameters */
4091 rtl_writephy(tp, 0x1f, 0x0a43);
4092 rtl_writephy(tp, 0x13, 0x80f3);
4093 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4094 rtl_writephy(tp, 0x13, 0x80f0);
4095 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4096 rtl_writephy(tp, 0x13, 0x80ef);
4097 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4098 rtl_writephy(tp, 0x13, 0x80f6);
4099 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4100 rtl_writephy(tp, 0x13, 0x80ec);
4101 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4102 rtl_writephy(tp, 0x13, 0x80ed);
4103 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4104 rtl_writephy(tp, 0x13, 0x80f2);
4105 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4106 rtl_writephy(tp, 0x13, 0x80f4);
4107 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4108 rtl_writephy(tp, 0x1f, 0x0a43);
4109 rtl_writephy(tp, 0x13, 0x8110);
4110 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4111 rtl_writephy(tp, 0x13, 0x810f);
4112 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4113 rtl_writephy(tp, 0x13, 0x8111);
4114 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4115 rtl_writephy(tp, 0x13, 0x8113);
4116 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4117 rtl_writephy(tp, 0x13, 0x8115);
4118 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4119 rtl_writephy(tp, 0x13, 0x810e);
4120 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4121 rtl_writephy(tp, 0x13, 0x810c);
4122 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4123 rtl_writephy(tp, 0x13, 0x810b);
4124 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4125 rtl_writephy(tp, 0x1f, 0x0a43);
4126 rtl_writephy(tp, 0x13, 0x80d1);
4127 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4128 rtl_writephy(tp, 0x13, 0x80cd);
4129 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4130 rtl_writephy(tp, 0x13, 0x80d3);
4131 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4132 rtl_writephy(tp, 0x13, 0x80d5);
4133 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4134 rtl_writephy(tp, 0x13, 0x80d7);
4135 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4137 /* Force PWM-mode */
4138 rtl_writephy(tp, 0x1f, 0x0bcd);
4139 rtl_writephy(tp, 0x14, 0x5065);
4140 rtl_writephy(tp, 0x14, 0xd065);
4141 rtl_writephy(tp, 0x1f, 0x0bc8);
4142 rtl_writephy(tp, 0x12, 0x00ed);
4143 rtl_writephy(tp, 0x1f, 0x0bcd);
4144 rtl_writephy(tp, 0x14, 0x1065);
4145 rtl_writephy(tp, 0x14, 0x9065);
4146 rtl_writephy(tp, 0x14, 0x1065);
4147 rtl_writephy(tp, 0x1f, 0x0000);
4149 /* Check ALDPS bit, disable it if enabled */
4150 rtl_writephy(tp, 0x1f, 0x0a43);
4151 if (rtl_readphy(tp, 0x10) & 0x0004)
4152 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4154 rtl_writephy(tp, 0x1f, 0x0000);
4157 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4159 static const struct phy_reg phy_reg_init[] = {
4166 rtl_writephy(tp, 0x1f, 0x0000);
4167 rtl_patchphy(tp, 0x11, 1 << 12);
4168 rtl_patchphy(tp, 0x19, 1 << 13);
4169 rtl_patchphy(tp, 0x10, 1 << 15);
4171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4174 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4176 static const struct phy_reg phy_reg_init[] = {
4190 /* Disable ALDPS before ram code */
4191 rtl_writephy(tp, 0x1f, 0x0000);
4192 rtl_writephy(tp, 0x18, 0x0310);
4195 rtl_apply_firmware(tp);
4197 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4200 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4202 /* Disable ALDPS before setting firmware */
4203 rtl_writephy(tp, 0x1f, 0x0000);
4204 rtl_writephy(tp, 0x18, 0x0310);
4207 rtl_apply_firmware(tp);
4210 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4211 rtl_writephy(tp, 0x1f, 0x0004);
4212 rtl_writephy(tp, 0x10, 0x401f);
4213 rtl_writephy(tp, 0x19, 0x7030);
4214 rtl_writephy(tp, 0x1f, 0x0000);
4217 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4219 static const struct phy_reg phy_reg_init[] = {
4226 /* Disable ALDPS before ram code */
4227 rtl_writephy(tp, 0x1f, 0x0000);
4228 rtl_writephy(tp, 0x18, 0x0310);
4231 rtl_apply_firmware(tp);
4233 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4234 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4236 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4239 static void rtl_hw_phy_config(struct net_device *dev)
4241 struct rtl8169_private *tp = netdev_priv(dev);
4243 rtl8169_print_mac_version(tp);
4245 switch (tp->mac_version) {
4246 case RTL_GIGA_MAC_VER_01:
4248 case RTL_GIGA_MAC_VER_02:
4249 case RTL_GIGA_MAC_VER_03:
4250 rtl8169s_hw_phy_config(tp);
4252 case RTL_GIGA_MAC_VER_04:
4253 rtl8169sb_hw_phy_config(tp);
4255 case RTL_GIGA_MAC_VER_05:
4256 rtl8169scd_hw_phy_config(tp);
4258 case RTL_GIGA_MAC_VER_06:
4259 rtl8169sce_hw_phy_config(tp);
4261 case RTL_GIGA_MAC_VER_07:
4262 case RTL_GIGA_MAC_VER_08:
4263 case RTL_GIGA_MAC_VER_09:
4264 rtl8102e_hw_phy_config(tp);
4266 case RTL_GIGA_MAC_VER_11:
4267 rtl8168bb_hw_phy_config(tp);
4269 case RTL_GIGA_MAC_VER_12:
4270 rtl8168bef_hw_phy_config(tp);
4272 case RTL_GIGA_MAC_VER_17:
4273 rtl8168bef_hw_phy_config(tp);
4275 case RTL_GIGA_MAC_VER_18:
4276 rtl8168cp_1_hw_phy_config(tp);
4278 case RTL_GIGA_MAC_VER_19:
4279 rtl8168c_1_hw_phy_config(tp);
4281 case RTL_GIGA_MAC_VER_20:
4282 rtl8168c_2_hw_phy_config(tp);
4284 case RTL_GIGA_MAC_VER_21:
4285 rtl8168c_3_hw_phy_config(tp);
4287 case RTL_GIGA_MAC_VER_22:
4288 rtl8168c_4_hw_phy_config(tp);
4290 case RTL_GIGA_MAC_VER_23:
4291 case RTL_GIGA_MAC_VER_24:
4292 rtl8168cp_2_hw_phy_config(tp);
4294 case RTL_GIGA_MAC_VER_25:
4295 rtl8168d_1_hw_phy_config(tp);
4297 case RTL_GIGA_MAC_VER_26:
4298 rtl8168d_2_hw_phy_config(tp);
4300 case RTL_GIGA_MAC_VER_27:
4301 rtl8168d_3_hw_phy_config(tp);
4303 case RTL_GIGA_MAC_VER_28:
4304 rtl8168d_4_hw_phy_config(tp);
4306 case RTL_GIGA_MAC_VER_29:
4307 case RTL_GIGA_MAC_VER_30:
4308 rtl8105e_hw_phy_config(tp);
4310 case RTL_GIGA_MAC_VER_31:
4313 case RTL_GIGA_MAC_VER_32:
4314 case RTL_GIGA_MAC_VER_33:
4315 rtl8168e_1_hw_phy_config(tp);
4317 case RTL_GIGA_MAC_VER_34:
4318 rtl8168e_2_hw_phy_config(tp);
4320 case RTL_GIGA_MAC_VER_35:
4321 rtl8168f_1_hw_phy_config(tp);
4323 case RTL_GIGA_MAC_VER_36:
4324 rtl8168f_2_hw_phy_config(tp);
4327 case RTL_GIGA_MAC_VER_37:
4328 rtl8402_hw_phy_config(tp);
4331 case RTL_GIGA_MAC_VER_38:
4332 rtl8411_hw_phy_config(tp);
4335 case RTL_GIGA_MAC_VER_39:
4336 rtl8106e_hw_phy_config(tp);
4339 case RTL_GIGA_MAC_VER_40:
4340 rtl8168g_1_hw_phy_config(tp);
4342 case RTL_GIGA_MAC_VER_42:
4343 case RTL_GIGA_MAC_VER_43:
4344 case RTL_GIGA_MAC_VER_44:
4345 rtl8168g_2_hw_phy_config(tp);
4347 case RTL_GIGA_MAC_VER_45:
4348 case RTL_GIGA_MAC_VER_47:
4349 rtl8168h_1_hw_phy_config(tp);
4351 case RTL_GIGA_MAC_VER_46:
4352 case RTL_GIGA_MAC_VER_48:
4353 rtl8168h_2_hw_phy_config(tp);
4356 case RTL_GIGA_MAC_VER_49:
4357 rtl8168ep_1_hw_phy_config(tp);
4359 case RTL_GIGA_MAC_VER_50:
4360 case RTL_GIGA_MAC_VER_51:
4361 rtl8168ep_2_hw_phy_config(tp);
4364 case RTL_GIGA_MAC_VER_41:
4370 static void rtl_phy_work(struct rtl8169_private *tp)
4372 struct timer_list *timer = &tp->timer;
4373 void __iomem *ioaddr = tp->mmio_addr;
4374 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4376 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4378 if (tp->phy_reset_pending(tp)) {
4380 * A busy loop could burn quite a few cycles on nowadays CPU.
4381 * Let's delay the execution of the timer for a few ticks.
4387 if (tp->link_ok(ioaddr))
4390 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4392 tp->phy_reset_enable(tp);
4395 mod_timer(timer, jiffies + timeout);
4398 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4400 if (!test_and_set_bit(flag, tp->wk.flags))
4401 schedule_work(&tp->wk.work);
4404 static void rtl8169_phy_timer(unsigned long __opaque)
4406 struct net_device *dev = (struct net_device *)__opaque;
4407 struct rtl8169_private *tp = netdev_priv(dev);
4409 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4412 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4413 void __iomem *ioaddr)
4416 pci_release_regions(pdev);
4417 pci_clear_mwi(pdev);
4418 pci_disable_device(pdev);
4422 DECLARE_RTL_COND(rtl_phy_reset_cond)
4424 return tp->phy_reset_pending(tp);
4427 static void rtl8169_phy_reset(struct net_device *dev,
4428 struct rtl8169_private *tp)
4430 tp->phy_reset_enable(tp);
4431 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4434 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4436 void __iomem *ioaddr = tp->mmio_addr;
4438 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4439 (RTL_R8(PHYstatus) & TBI_Enable);
4442 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4444 void __iomem *ioaddr = tp->mmio_addr;
4446 rtl_hw_phy_config(dev);
4448 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4449 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4453 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4455 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4456 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4458 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4459 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4461 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4462 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4465 rtl8169_phy_reset(dev, tp);
4467 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4468 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4469 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4470 (tp->mii.supports_gmii ?
4471 ADVERTISED_1000baseT_Half |
4472 ADVERTISED_1000baseT_Full : 0));
4474 if (rtl_tbi_enabled(tp))
4475 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4478 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4480 void __iomem *ioaddr = tp->mmio_addr;
4484 RTL_W8(Cfg9346, Cfg9346_Unlock);
4486 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4489 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4492 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4493 rtl_rar_exgmac_set(tp, addr);
4495 RTL_W8(Cfg9346, Cfg9346_Lock);
4497 rtl_unlock_work(tp);
4500 static int rtl_set_mac_address(struct net_device *dev, void *p)
4502 struct rtl8169_private *tp = netdev_priv(dev);
4503 struct sockaddr *addr = p;
4505 if (!is_valid_ether_addr(addr->sa_data))
4506 return -EADDRNOTAVAIL;
4508 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4510 rtl_rar_set(tp, dev->dev_addr);
4515 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4517 struct rtl8169_private *tp = netdev_priv(dev);
4518 struct mii_ioctl_data *data = if_mii(ifr);
4520 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4523 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4524 struct mii_ioctl_data *data, int cmd)
4528 data->phy_id = 32; /* Internal PHY */
4532 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4536 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4542 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4547 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4549 if (tp->features & RTL_FEATURE_MSI) {
4550 pci_disable_msi(pdev);
4551 tp->features &= ~RTL_FEATURE_MSI;
4555 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4557 struct mdio_ops *ops = &tp->mdio_ops;
4559 switch (tp->mac_version) {
4560 case RTL_GIGA_MAC_VER_27:
4561 ops->write = r8168dp_1_mdio_write;
4562 ops->read = r8168dp_1_mdio_read;
4564 case RTL_GIGA_MAC_VER_28:
4565 case RTL_GIGA_MAC_VER_31:
4566 ops->write = r8168dp_2_mdio_write;
4567 ops->read = r8168dp_2_mdio_read;
4569 case RTL_GIGA_MAC_VER_40:
4570 case RTL_GIGA_MAC_VER_41:
4571 case RTL_GIGA_MAC_VER_42:
4572 case RTL_GIGA_MAC_VER_43:
4573 case RTL_GIGA_MAC_VER_44:
4574 case RTL_GIGA_MAC_VER_45:
4575 case RTL_GIGA_MAC_VER_46:
4576 case RTL_GIGA_MAC_VER_47:
4577 case RTL_GIGA_MAC_VER_48:
4578 case RTL_GIGA_MAC_VER_49:
4579 case RTL_GIGA_MAC_VER_50:
4580 case RTL_GIGA_MAC_VER_51:
4581 ops->write = r8168g_mdio_write;
4582 ops->read = r8168g_mdio_read;
4585 ops->write = r8169_mdio_write;
4586 ops->read = r8169_mdio_read;
4591 static void rtl_speed_down(struct rtl8169_private *tp)
4596 rtl_writephy(tp, 0x1f, 0x0000);
4597 lpa = rtl_readphy(tp, MII_LPA);
4599 if (lpa & (LPA_10HALF | LPA_10FULL))
4600 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4601 else if (lpa & (LPA_100HALF | LPA_100FULL))
4602 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4603 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4605 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4606 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4607 (tp->mii.supports_gmii ?
4608 ADVERTISED_1000baseT_Half |
4609 ADVERTISED_1000baseT_Full : 0);
4611 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4615 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4617 void __iomem *ioaddr = tp->mmio_addr;
4619 switch (tp->mac_version) {
4620 case RTL_GIGA_MAC_VER_25:
4621 case RTL_GIGA_MAC_VER_26:
4622 case RTL_GIGA_MAC_VER_29:
4623 case RTL_GIGA_MAC_VER_30:
4624 case RTL_GIGA_MAC_VER_32:
4625 case RTL_GIGA_MAC_VER_33:
4626 case RTL_GIGA_MAC_VER_34:
4627 case RTL_GIGA_MAC_VER_37:
4628 case RTL_GIGA_MAC_VER_38:
4629 case RTL_GIGA_MAC_VER_39:
4630 case RTL_GIGA_MAC_VER_40:
4631 case RTL_GIGA_MAC_VER_41:
4632 case RTL_GIGA_MAC_VER_42:
4633 case RTL_GIGA_MAC_VER_43:
4634 case RTL_GIGA_MAC_VER_44:
4635 case RTL_GIGA_MAC_VER_45:
4636 case RTL_GIGA_MAC_VER_46:
4637 case RTL_GIGA_MAC_VER_47:
4638 case RTL_GIGA_MAC_VER_48:
4639 case RTL_GIGA_MAC_VER_49:
4640 case RTL_GIGA_MAC_VER_50:
4641 case RTL_GIGA_MAC_VER_51:
4642 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4643 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4650 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4652 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4656 rtl_wol_suspend_quirk(tp);
4661 static void r810x_phy_power_down(struct rtl8169_private *tp)
4663 rtl_writephy(tp, 0x1f, 0x0000);
4664 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4667 static void r810x_phy_power_up(struct rtl8169_private *tp)
4669 rtl_writephy(tp, 0x1f, 0x0000);
4670 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4673 static void r810x_pll_power_down(struct rtl8169_private *tp)
4675 void __iomem *ioaddr = tp->mmio_addr;
4677 if (rtl_wol_pll_power_down(tp))
4680 r810x_phy_power_down(tp);
4682 switch (tp->mac_version) {
4683 case RTL_GIGA_MAC_VER_07:
4684 case RTL_GIGA_MAC_VER_08:
4685 case RTL_GIGA_MAC_VER_09:
4686 case RTL_GIGA_MAC_VER_10:
4687 case RTL_GIGA_MAC_VER_13:
4688 case RTL_GIGA_MAC_VER_16:
4691 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4696 static void r810x_pll_power_up(struct rtl8169_private *tp)
4698 void __iomem *ioaddr = tp->mmio_addr;
4700 r810x_phy_power_up(tp);
4702 switch (tp->mac_version) {
4703 case RTL_GIGA_MAC_VER_07:
4704 case RTL_GIGA_MAC_VER_08:
4705 case RTL_GIGA_MAC_VER_09:
4706 case RTL_GIGA_MAC_VER_10:
4707 case RTL_GIGA_MAC_VER_13:
4708 case RTL_GIGA_MAC_VER_16:
4710 case RTL_GIGA_MAC_VER_47:
4711 case RTL_GIGA_MAC_VER_48:
4712 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4715 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4720 static void r8168_phy_power_up(struct rtl8169_private *tp)
4722 rtl_writephy(tp, 0x1f, 0x0000);
4723 switch (tp->mac_version) {
4724 case RTL_GIGA_MAC_VER_11:
4725 case RTL_GIGA_MAC_VER_12:
4726 case RTL_GIGA_MAC_VER_17:
4727 case RTL_GIGA_MAC_VER_18:
4728 case RTL_GIGA_MAC_VER_19:
4729 case RTL_GIGA_MAC_VER_20:
4730 case RTL_GIGA_MAC_VER_21:
4731 case RTL_GIGA_MAC_VER_22:
4732 case RTL_GIGA_MAC_VER_23:
4733 case RTL_GIGA_MAC_VER_24:
4734 case RTL_GIGA_MAC_VER_25:
4735 case RTL_GIGA_MAC_VER_26:
4736 case RTL_GIGA_MAC_VER_27:
4737 case RTL_GIGA_MAC_VER_28:
4738 case RTL_GIGA_MAC_VER_31:
4739 rtl_writephy(tp, 0x0e, 0x0000);
4744 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4747 static void r8168_phy_power_down(struct rtl8169_private *tp)
4749 rtl_writephy(tp, 0x1f, 0x0000);
4750 switch (tp->mac_version) {
4751 case RTL_GIGA_MAC_VER_32:
4752 case RTL_GIGA_MAC_VER_33:
4753 case RTL_GIGA_MAC_VER_40:
4754 case RTL_GIGA_MAC_VER_41:
4755 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4758 case RTL_GIGA_MAC_VER_11:
4759 case RTL_GIGA_MAC_VER_12:
4760 case RTL_GIGA_MAC_VER_17:
4761 case RTL_GIGA_MAC_VER_18:
4762 case RTL_GIGA_MAC_VER_19:
4763 case RTL_GIGA_MAC_VER_20:
4764 case RTL_GIGA_MAC_VER_21:
4765 case RTL_GIGA_MAC_VER_22:
4766 case RTL_GIGA_MAC_VER_23:
4767 case RTL_GIGA_MAC_VER_24:
4768 case RTL_GIGA_MAC_VER_25:
4769 case RTL_GIGA_MAC_VER_26:
4770 case RTL_GIGA_MAC_VER_27:
4771 case RTL_GIGA_MAC_VER_28:
4772 case RTL_GIGA_MAC_VER_31:
4773 rtl_writephy(tp, 0x0e, 0x0200);
4775 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4780 static void r8168_pll_power_down(struct rtl8169_private *tp)
4782 void __iomem *ioaddr = tp->mmio_addr;
4784 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4785 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4786 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4787 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4788 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4789 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4790 r8168_check_dash(tp)) {
4794 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4795 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4796 (RTL_R16(CPlusCmd) & ASF)) {
4800 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4801 tp->mac_version == RTL_GIGA_MAC_VER_33)
4802 rtl_ephy_write(tp, 0x19, 0xff64);
4804 if (rtl_wol_pll_power_down(tp))
4807 r8168_phy_power_down(tp);
4809 switch (tp->mac_version) {
4810 case RTL_GIGA_MAC_VER_25:
4811 case RTL_GIGA_MAC_VER_26:
4812 case RTL_GIGA_MAC_VER_27:
4813 case RTL_GIGA_MAC_VER_28:
4814 case RTL_GIGA_MAC_VER_31:
4815 case RTL_GIGA_MAC_VER_32:
4816 case RTL_GIGA_MAC_VER_33:
4817 case RTL_GIGA_MAC_VER_44:
4818 case RTL_GIGA_MAC_VER_45:
4819 case RTL_GIGA_MAC_VER_46:
4820 case RTL_GIGA_MAC_VER_50:
4821 case RTL_GIGA_MAC_VER_51:
4822 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4824 case RTL_GIGA_MAC_VER_40:
4825 case RTL_GIGA_MAC_VER_41:
4826 case RTL_GIGA_MAC_VER_49:
4827 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4828 0xfc000000, ERIAR_EXGMAC);
4829 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4834 static void r8168_pll_power_up(struct rtl8169_private *tp)
4836 void __iomem *ioaddr = tp->mmio_addr;
4838 switch (tp->mac_version) {
4839 case RTL_GIGA_MAC_VER_25:
4840 case RTL_GIGA_MAC_VER_26:
4841 case RTL_GIGA_MAC_VER_27:
4842 case RTL_GIGA_MAC_VER_28:
4843 case RTL_GIGA_MAC_VER_31:
4844 case RTL_GIGA_MAC_VER_32:
4845 case RTL_GIGA_MAC_VER_33:
4846 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4848 case RTL_GIGA_MAC_VER_44:
4849 case RTL_GIGA_MAC_VER_45:
4850 case RTL_GIGA_MAC_VER_46:
4851 case RTL_GIGA_MAC_VER_50:
4852 case RTL_GIGA_MAC_VER_51:
4853 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4855 case RTL_GIGA_MAC_VER_40:
4856 case RTL_GIGA_MAC_VER_41:
4857 case RTL_GIGA_MAC_VER_49:
4858 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4859 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4860 0x00000000, ERIAR_EXGMAC);
4864 r8168_phy_power_up(tp);
4867 static void rtl_generic_op(struct rtl8169_private *tp,
4868 void (*op)(struct rtl8169_private *))
4874 static void rtl_pll_power_down(struct rtl8169_private *tp)
4876 rtl_generic_op(tp, tp->pll_power_ops.down);
4879 static void rtl_pll_power_up(struct rtl8169_private *tp)
4881 rtl_generic_op(tp, tp->pll_power_ops.up);
4884 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4886 struct pll_power_ops *ops = &tp->pll_power_ops;
4888 switch (tp->mac_version) {
4889 case RTL_GIGA_MAC_VER_07:
4890 case RTL_GIGA_MAC_VER_08:
4891 case RTL_GIGA_MAC_VER_09:
4892 case RTL_GIGA_MAC_VER_10:
4893 case RTL_GIGA_MAC_VER_16:
4894 case RTL_GIGA_MAC_VER_29:
4895 case RTL_GIGA_MAC_VER_30:
4896 case RTL_GIGA_MAC_VER_37:
4897 case RTL_GIGA_MAC_VER_39:
4898 case RTL_GIGA_MAC_VER_43:
4899 case RTL_GIGA_MAC_VER_47:
4900 case RTL_GIGA_MAC_VER_48:
4901 ops->down = r810x_pll_power_down;
4902 ops->up = r810x_pll_power_up;
4905 case RTL_GIGA_MAC_VER_11:
4906 case RTL_GIGA_MAC_VER_12:
4907 case RTL_GIGA_MAC_VER_17:
4908 case RTL_GIGA_MAC_VER_18:
4909 case RTL_GIGA_MAC_VER_19:
4910 case RTL_GIGA_MAC_VER_20:
4911 case RTL_GIGA_MAC_VER_21:
4912 case RTL_GIGA_MAC_VER_22:
4913 case RTL_GIGA_MAC_VER_23:
4914 case RTL_GIGA_MAC_VER_24:
4915 case RTL_GIGA_MAC_VER_25:
4916 case RTL_GIGA_MAC_VER_26:
4917 case RTL_GIGA_MAC_VER_27:
4918 case RTL_GIGA_MAC_VER_28:
4919 case RTL_GIGA_MAC_VER_31:
4920 case RTL_GIGA_MAC_VER_32:
4921 case RTL_GIGA_MAC_VER_33:
4922 case RTL_GIGA_MAC_VER_34:
4923 case RTL_GIGA_MAC_VER_35:
4924 case RTL_GIGA_MAC_VER_36:
4925 case RTL_GIGA_MAC_VER_38:
4926 case RTL_GIGA_MAC_VER_40:
4927 case RTL_GIGA_MAC_VER_41:
4928 case RTL_GIGA_MAC_VER_42:
4929 case RTL_GIGA_MAC_VER_44:
4930 case RTL_GIGA_MAC_VER_45:
4931 case RTL_GIGA_MAC_VER_46:
4932 case RTL_GIGA_MAC_VER_49:
4933 case RTL_GIGA_MAC_VER_50:
4934 case RTL_GIGA_MAC_VER_51:
4935 ops->down = r8168_pll_power_down;
4936 ops->up = r8168_pll_power_up;
4946 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4948 void __iomem *ioaddr = tp->mmio_addr;
4950 switch (tp->mac_version) {
4951 case RTL_GIGA_MAC_VER_01:
4952 case RTL_GIGA_MAC_VER_02:
4953 case RTL_GIGA_MAC_VER_03:
4954 case RTL_GIGA_MAC_VER_04:
4955 case RTL_GIGA_MAC_VER_05:
4956 case RTL_GIGA_MAC_VER_06:
4957 case RTL_GIGA_MAC_VER_10:
4958 case RTL_GIGA_MAC_VER_11:
4959 case RTL_GIGA_MAC_VER_12:
4960 case RTL_GIGA_MAC_VER_13:
4961 case RTL_GIGA_MAC_VER_14:
4962 case RTL_GIGA_MAC_VER_15:
4963 case RTL_GIGA_MAC_VER_16:
4964 case RTL_GIGA_MAC_VER_17:
4965 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4967 case RTL_GIGA_MAC_VER_18:
4968 case RTL_GIGA_MAC_VER_19:
4969 case RTL_GIGA_MAC_VER_20:
4970 case RTL_GIGA_MAC_VER_21:
4971 case RTL_GIGA_MAC_VER_22:
4972 case RTL_GIGA_MAC_VER_23:
4973 case RTL_GIGA_MAC_VER_24:
4974 case RTL_GIGA_MAC_VER_34:
4975 case RTL_GIGA_MAC_VER_35:
4976 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4978 case RTL_GIGA_MAC_VER_40:
4979 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4981 case RTL_GIGA_MAC_VER_41:
4982 case RTL_GIGA_MAC_VER_42:
4983 case RTL_GIGA_MAC_VER_43:
4984 case RTL_GIGA_MAC_VER_44:
4985 case RTL_GIGA_MAC_VER_45:
4986 case RTL_GIGA_MAC_VER_46:
4987 case RTL_GIGA_MAC_VER_47:
4988 case RTL_GIGA_MAC_VER_48:
4989 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4991 case RTL_GIGA_MAC_VER_49:
4992 case RTL_GIGA_MAC_VER_50:
4993 case RTL_GIGA_MAC_VER_51:
4994 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4997 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
5002 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5004 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5007 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5009 void __iomem *ioaddr = tp->mmio_addr;
5011 RTL_W8(Cfg9346, Cfg9346_Unlock);
5012 rtl_generic_op(tp, tp->jumbo_ops.enable);
5013 RTL_W8(Cfg9346, Cfg9346_Lock);
5016 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5018 void __iomem *ioaddr = tp->mmio_addr;
5020 RTL_W8(Cfg9346, Cfg9346_Unlock);
5021 rtl_generic_op(tp, tp->jumbo_ops.disable);
5022 RTL_W8(Cfg9346, Cfg9346_Lock);
5025 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5027 void __iomem *ioaddr = tp->mmio_addr;
5029 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5030 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5031 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5034 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5036 void __iomem *ioaddr = tp->mmio_addr;
5038 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5039 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5040 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5043 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5045 void __iomem *ioaddr = tp->mmio_addr;
5047 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5050 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5052 void __iomem *ioaddr = tp->mmio_addr;
5054 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5057 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5059 void __iomem *ioaddr = tp->mmio_addr;
5061 RTL_W8(MaxTxPacketSize, 0x3f);
5062 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5063 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5064 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5067 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5069 void __iomem *ioaddr = tp->mmio_addr;
5071 RTL_W8(MaxTxPacketSize, 0x0c);
5072 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5073 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5074 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5077 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5079 rtl_tx_performance_tweak(tp->pci_dev,
5080 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5083 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5085 rtl_tx_performance_tweak(tp->pci_dev,
5086 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5089 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5091 void __iomem *ioaddr = tp->mmio_addr;
5093 r8168b_0_hw_jumbo_enable(tp);
5095 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5098 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5100 void __iomem *ioaddr = tp->mmio_addr;
5102 r8168b_0_hw_jumbo_disable(tp);
5104 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5107 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5109 struct jumbo_ops *ops = &tp->jumbo_ops;
5111 switch (tp->mac_version) {
5112 case RTL_GIGA_MAC_VER_11:
5113 ops->disable = r8168b_0_hw_jumbo_disable;
5114 ops->enable = r8168b_0_hw_jumbo_enable;
5116 case RTL_GIGA_MAC_VER_12:
5117 case RTL_GIGA_MAC_VER_17:
5118 ops->disable = r8168b_1_hw_jumbo_disable;
5119 ops->enable = r8168b_1_hw_jumbo_enable;
5121 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5122 case RTL_GIGA_MAC_VER_19:
5123 case RTL_GIGA_MAC_VER_20:
5124 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5125 case RTL_GIGA_MAC_VER_22:
5126 case RTL_GIGA_MAC_VER_23:
5127 case RTL_GIGA_MAC_VER_24:
5128 case RTL_GIGA_MAC_VER_25:
5129 case RTL_GIGA_MAC_VER_26:
5130 ops->disable = r8168c_hw_jumbo_disable;
5131 ops->enable = r8168c_hw_jumbo_enable;
5133 case RTL_GIGA_MAC_VER_27:
5134 case RTL_GIGA_MAC_VER_28:
5135 ops->disable = r8168dp_hw_jumbo_disable;
5136 ops->enable = r8168dp_hw_jumbo_enable;
5138 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5139 case RTL_GIGA_MAC_VER_32:
5140 case RTL_GIGA_MAC_VER_33:
5141 case RTL_GIGA_MAC_VER_34:
5142 ops->disable = r8168e_hw_jumbo_disable;
5143 ops->enable = r8168e_hw_jumbo_enable;
5147 * No action needed for jumbo frames with 8169.
5148 * No jumbo for 810x at all.
5150 case RTL_GIGA_MAC_VER_40:
5151 case RTL_GIGA_MAC_VER_41:
5152 case RTL_GIGA_MAC_VER_42:
5153 case RTL_GIGA_MAC_VER_43:
5154 case RTL_GIGA_MAC_VER_44:
5155 case RTL_GIGA_MAC_VER_45:
5156 case RTL_GIGA_MAC_VER_46:
5157 case RTL_GIGA_MAC_VER_47:
5158 case RTL_GIGA_MAC_VER_48:
5159 case RTL_GIGA_MAC_VER_49:
5160 case RTL_GIGA_MAC_VER_50:
5161 case RTL_GIGA_MAC_VER_51:
5163 ops->disable = NULL;
5169 DECLARE_RTL_COND(rtl_chipcmd_cond)
5171 void __iomem *ioaddr = tp->mmio_addr;
5173 return RTL_R8(ChipCmd) & CmdReset;
5176 static void rtl_hw_reset(struct rtl8169_private *tp)
5178 void __iomem *ioaddr = tp->mmio_addr;
5180 RTL_W8(ChipCmd, CmdReset);
5182 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5185 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5187 struct rtl_fw *rtl_fw;
5191 name = rtl_lookup_firmware_name(tp);
5193 goto out_no_firmware;
5195 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5199 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5203 rc = rtl_check_firmware(tp, rtl_fw);
5205 goto err_release_firmware;
5207 tp->rtl_fw = rtl_fw;
5211 err_release_firmware:
5212 release_firmware(rtl_fw->fw);
5216 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5223 static void rtl_request_firmware(struct rtl8169_private *tp)
5225 if (IS_ERR(tp->rtl_fw))
5226 rtl_request_uncached_firmware(tp);
5229 static void rtl_rx_close(struct rtl8169_private *tp)
5231 void __iomem *ioaddr = tp->mmio_addr;
5233 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5236 DECLARE_RTL_COND(rtl_npq_cond)
5238 void __iomem *ioaddr = tp->mmio_addr;
5240 return RTL_R8(TxPoll) & NPQ;
5243 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5245 void __iomem *ioaddr = tp->mmio_addr;
5247 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5250 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5252 void __iomem *ioaddr = tp->mmio_addr;
5254 /* Disable interrupts */
5255 rtl8169_irq_mask_and_ack(tp);
5259 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5260 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5261 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5262 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5263 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5264 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5265 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5266 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5267 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5268 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5269 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5270 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5271 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5272 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5273 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5274 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5275 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5276 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5277 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5278 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5279 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5280 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5281 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5283 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5290 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5292 void __iomem *ioaddr = tp->mmio_addr;
5294 /* Set DMA burst size and Interframe Gap Time */
5295 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5296 (InterFrameGap << TxInterFrameGapShift));
5299 static void rtl_hw_start(struct net_device *dev)
5301 struct rtl8169_private *tp = netdev_priv(dev);
5305 rtl_irq_enable_all(tp);
5308 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5309 void __iomem *ioaddr)
5312 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5313 * register to be written before TxDescAddrLow to work.
5314 * Switching from MMIO to I/O access fixes the issue as well.
5316 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5317 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5318 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5319 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5322 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5326 cmd = RTL_R16(CPlusCmd);
5327 RTL_W16(CPlusCmd, cmd);
5331 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5333 /* Low hurts. Let's disable the filtering. */
5334 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5337 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5339 static const struct rtl_cfg2_info {
5344 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5345 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5346 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5347 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5349 const struct rtl_cfg2_info *p = cfg2_info;
5353 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5354 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5355 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5356 RTL_W32(0x7c, p->val);
5362 static void rtl_set_rx_mode(struct net_device *dev)
5364 struct rtl8169_private *tp = netdev_priv(dev);
5365 void __iomem *ioaddr = tp->mmio_addr;
5366 u32 mc_filter[2]; /* Multicast hash filter */
5370 if (dev->flags & IFF_PROMISC) {
5371 /* Unconditionally log net taps. */
5372 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5374 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5376 mc_filter[1] = mc_filter[0] = 0xffffffff;
5377 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5378 (dev->flags & IFF_ALLMULTI)) {
5379 /* Too many to filter perfectly -- accept all multicasts. */
5380 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5381 mc_filter[1] = mc_filter[0] = 0xffffffff;
5383 struct netdev_hw_addr *ha;
5385 rx_mode = AcceptBroadcast | AcceptMyPhys;
5386 mc_filter[1] = mc_filter[0] = 0;
5387 netdev_for_each_mc_addr(ha, dev) {
5388 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5389 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5390 rx_mode |= AcceptMulticast;
5394 if (dev->features & NETIF_F_RXALL)
5395 rx_mode |= (AcceptErr | AcceptRunt);
5397 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5399 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5400 u32 data = mc_filter[0];
5402 mc_filter[0] = swab32(mc_filter[1]);
5403 mc_filter[1] = swab32(data);
5406 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5407 mc_filter[1] = mc_filter[0] = 0xffffffff;
5409 RTL_W32(MAR0 + 4, mc_filter[1]);
5410 RTL_W32(MAR0 + 0, mc_filter[0]);
5412 RTL_W32(RxConfig, tmp);
5415 static void rtl_hw_start_8169(struct net_device *dev)
5417 struct rtl8169_private *tp = netdev_priv(dev);
5418 void __iomem *ioaddr = tp->mmio_addr;
5419 struct pci_dev *pdev = tp->pci_dev;
5421 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5422 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5423 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5426 RTL_W8(Cfg9346, Cfg9346_Unlock);
5427 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5428 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5429 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5430 tp->mac_version == RTL_GIGA_MAC_VER_04)
5431 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5435 RTL_W8(EarlyTxThres, NoEarlyTx);
5437 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5439 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5440 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5441 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5442 tp->mac_version == RTL_GIGA_MAC_VER_04)
5443 rtl_set_rx_tx_config_registers(tp);
5445 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5447 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5448 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5449 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5450 "Bit-3 and bit-14 MUST be 1\n");
5451 tp->cp_cmd |= (1 << 14);
5454 RTL_W16(CPlusCmd, tp->cp_cmd);
5456 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5459 * Undocumented corner. Supposedly:
5460 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5462 RTL_W16(IntrMitigate, 0x0000);
5464 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5466 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5467 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5468 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5469 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5470 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5471 rtl_set_rx_tx_config_registers(tp);
5474 RTL_W8(Cfg9346, Cfg9346_Lock);
5476 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5479 RTL_W32(RxMissed, 0);
5481 rtl_set_rx_mode(dev);
5483 /* no early-rx interrupts */
5484 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5487 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5489 if (tp->csi_ops.write)
5490 tp->csi_ops.write(tp, addr, value);
5493 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5495 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5498 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5502 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5503 rtl_csi_write(tp, 0x070c, csi | bits);
5506 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5508 rtl_csi_access_enable(tp, 0x17000000);
5511 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5513 rtl_csi_access_enable(tp, 0x27000000);
5516 DECLARE_RTL_COND(rtl_csiar_cond)
5518 void __iomem *ioaddr = tp->mmio_addr;
5520 return RTL_R32(CSIAR) & CSIAR_FLAG;
5523 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5525 void __iomem *ioaddr = tp->mmio_addr;
5527 RTL_W32(CSIDR, value);
5528 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5529 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5531 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5534 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5536 void __iomem *ioaddr = tp->mmio_addr;
5538 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5539 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5541 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5542 RTL_R32(CSIDR) : ~0;
5545 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5547 void __iomem *ioaddr = tp->mmio_addr;
5549 RTL_W32(CSIDR, value);
5550 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5551 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5554 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5557 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5559 void __iomem *ioaddr = tp->mmio_addr;
5561 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5562 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5564 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5565 RTL_R32(CSIDR) : ~0;
5568 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5570 void __iomem *ioaddr = tp->mmio_addr;
5572 RTL_W32(CSIDR, value);
5573 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5574 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5577 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5580 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5582 void __iomem *ioaddr = tp->mmio_addr;
5584 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5585 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5587 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5588 RTL_R32(CSIDR) : ~0;
5591 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5593 struct csi_ops *ops = &tp->csi_ops;
5595 switch (tp->mac_version) {
5596 case RTL_GIGA_MAC_VER_01:
5597 case RTL_GIGA_MAC_VER_02:
5598 case RTL_GIGA_MAC_VER_03:
5599 case RTL_GIGA_MAC_VER_04:
5600 case RTL_GIGA_MAC_VER_05:
5601 case RTL_GIGA_MAC_VER_06:
5602 case RTL_GIGA_MAC_VER_10:
5603 case RTL_GIGA_MAC_VER_11:
5604 case RTL_GIGA_MAC_VER_12:
5605 case RTL_GIGA_MAC_VER_13:
5606 case RTL_GIGA_MAC_VER_14:
5607 case RTL_GIGA_MAC_VER_15:
5608 case RTL_GIGA_MAC_VER_16:
5609 case RTL_GIGA_MAC_VER_17:
5614 case RTL_GIGA_MAC_VER_37:
5615 case RTL_GIGA_MAC_VER_38:
5616 ops->write = r8402_csi_write;
5617 ops->read = r8402_csi_read;
5620 case RTL_GIGA_MAC_VER_44:
5621 ops->write = r8411_csi_write;
5622 ops->read = r8411_csi_read;
5626 ops->write = r8169_csi_write;
5627 ops->read = r8169_csi_read;
5633 unsigned int offset;
5638 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5644 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5645 rtl_ephy_write(tp, e->offset, w);
5650 static void rtl_disable_clock_request(struct pci_dev *pdev)
5652 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5653 PCI_EXP_LNKCTL_CLKREQ_EN);
5656 static void rtl_enable_clock_request(struct pci_dev *pdev)
5658 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5659 PCI_EXP_LNKCTL_CLKREQ_EN);
5662 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5664 void __iomem *ioaddr = tp->mmio_addr;
5667 data = RTL_R8(Config3);
5672 data &= ~Rdy_to_L23;
5674 RTL_W8(Config3, data);
5677 #define R8168_CPCMD_QUIRK_MASK (\
5688 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5690 void __iomem *ioaddr = tp->mmio_addr;
5691 struct pci_dev *pdev = tp->pci_dev;
5693 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5695 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5697 if (tp->dev->mtu <= ETH_DATA_LEN) {
5698 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5699 PCI_EXP_DEVCTL_NOSNOOP_EN);
5703 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5705 void __iomem *ioaddr = tp->mmio_addr;
5707 rtl_hw_start_8168bb(tp);
5709 RTL_W8(MaxTxPacketSize, TxPacketMax);
5711 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5714 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5716 void __iomem *ioaddr = tp->mmio_addr;
5717 struct pci_dev *pdev = tp->pci_dev;
5719 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5721 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5723 if (tp->dev->mtu <= ETH_DATA_LEN)
5724 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5726 rtl_disable_clock_request(pdev);
5728 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5731 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5733 static const struct ephy_info e_info_8168cp[] = {
5734 { 0x01, 0, 0x0001 },
5735 { 0x02, 0x0800, 0x1000 },
5736 { 0x03, 0, 0x0042 },
5737 { 0x06, 0x0080, 0x0000 },
5741 rtl_csi_access_enable_2(tp);
5743 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5745 __rtl_hw_start_8168cp(tp);
5748 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5750 void __iomem *ioaddr = tp->mmio_addr;
5751 struct pci_dev *pdev = tp->pci_dev;
5753 rtl_csi_access_enable_2(tp);
5755 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5757 if (tp->dev->mtu <= ETH_DATA_LEN)
5758 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5760 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5763 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5765 void __iomem *ioaddr = tp->mmio_addr;
5766 struct pci_dev *pdev = tp->pci_dev;
5768 rtl_csi_access_enable_2(tp);
5770 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5773 RTL_W8(DBG_REG, 0x20);
5775 RTL_W8(MaxTxPacketSize, TxPacketMax);
5777 if (tp->dev->mtu <= ETH_DATA_LEN)
5778 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5780 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5783 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5785 void __iomem *ioaddr = tp->mmio_addr;
5786 static const struct ephy_info e_info_8168c_1[] = {
5787 { 0x02, 0x0800, 0x1000 },
5788 { 0x03, 0, 0x0002 },
5789 { 0x06, 0x0080, 0x0000 }
5792 rtl_csi_access_enable_2(tp);
5794 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5796 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5798 __rtl_hw_start_8168cp(tp);
5801 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5803 static const struct ephy_info e_info_8168c_2[] = {
5804 { 0x01, 0, 0x0001 },
5805 { 0x03, 0x0400, 0x0220 }
5808 rtl_csi_access_enable_2(tp);
5810 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5812 __rtl_hw_start_8168cp(tp);
5815 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5817 rtl_hw_start_8168c_2(tp);
5820 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5822 rtl_csi_access_enable_2(tp);
5824 __rtl_hw_start_8168cp(tp);
5827 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5829 void __iomem *ioaddr = tp->mmio_addr;
5830 struct pci_dev *pdev = tp->pci_dev;
5832 rtl_csi_access_enable_2(tp);
5834 rtl_disable_clock_request(pdev);
5836 RTL_W8(MaxTxPacketSize, TxPacketMax);
5838 if (tp->dev->mtu <= ETH_DATA_LEN)
5839 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5841 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5844 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5846 void __iomem *ioaddr = tp->mmio_addr;
5847 struct pci_dev *pdev = tp->pci_dev;
5849 rtl_csi_access_enable_1(tp);
5851 if (tp->dev->mtu <= ETH_DATA_LEN)
5852 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5854 RTL_W8(MaxTxPacketSize, TxPacketMax);
5856 rtl_disable_clock_request(pdev);
5859 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5861 void __iomem *ioaddr = tp->mmio_addr;
5862 struct pci_dev *pdev = tp->pci_dev;
5863 static const struct ephy_info e_info_8168d_4[] = {
5865 { 0x19, 0x20, 0x50 },
5870 rtl_csi_access_enable_1(tp);
5872 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5874 RTL_W8(MaxTxPacketSize, TxPacketMax);
5876 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5877 const struct ephy_info *e = e_info_8168d_4 + i;
5880 w = rtl_ephy_read(tp, e->offset);
5881 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5884 rtl_enable_clock_request(pdev);
5887 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5889 void __iomem *ioaddr = tp->mmio_addr;
5890 struct pci_dev *pdev = tp->pci_dev;
5891 static const struct ephy_info e_info_8168e_1[] = {
5892 { 0x00, 0x0200, 0x0100 },
5893 { 0x00, 0x0000, 0x0004 },
5894 { 0x06, 0x0002, 0x0001 },
5895 { 0x06, 0x0000, 0x0030 },
5896 { 0x07, 0x0000, 0x2000 },
5897 { 0x00, 0x0000, 0x0020 },
5898 { 0x03, 0x5800, 0x2000 },
5899 { 0x03, 0x0000, 0x0001 },
5900 { 0x01, 0x0800, 0x1000 },
5901 { 0x07, 0x0000, 0x4000 },
5902 { 0x1e, 0x0000, 0x2000 },
5903 { 0x19, 0xffff, 0xfe6c },
5904 { 0x0a, 0x0000, 0x0040 }
5907 rtl_csi_access_enable_2(tp);
5909 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5911 if (tp->dev->mtu <= ETH_DATA_LEN)
5912 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5914 RTL_W8(MaxTxPacketSize, TxPacketMax);
5916 rtl_disable_clock_request(pdev);
5918 /* Reset tx FIFO pointer */
5919 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5920 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5922 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5925 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5927 void __iomem *ioaddr = tp->mmio_addr;
5928 struct pci_dev *pdev = tp->pci_dev;
5929 static const struct ephy_info e_info_8168e_2[] = {
5930 { 0x09, 0x0000, 0x0080 },
5931 { 0x19, 0x0000, 0x0224 }
5934 rtl_csi_access_enable_1(tp);
5936 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5938 if (tp->dev->mtu <= ETH_DATA_LEN)
5939 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5941 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5942 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5943 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5944 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5945 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5946 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5947 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5948 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5950 RTL_W8(MaxTxPacketSize, EarlySize);
5952 rtl_disable_clock_request(pdev);
5954 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5955 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5957 /* Adjust EEE LED frequency */
5958 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5960 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5961 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5962 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5965 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5967 void __iomem *ioaddr = tp->mmio_addr;
5968 struct pci_dev *pdev = tp->pci_dev;
5970 rtl_csi_access_enable_2(tp);
5972 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5974 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5975 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5976 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5977 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5978 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5979 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5980 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5981 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5982 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5983 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5985 RTL_W8(MaxTxPacketSize, EarlySize);
5987 rtl_disable_clock_request(pdev);
5989 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5990 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5991 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5992 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5993 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5996 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5998 void __iomem *ioaddr = tp->mmio_addr;
5999 static const struct ephy_info e_info_8168f_1[] = {
6000 { 0x06, 0x00c0, 0x0020 },
6001 { 0x08, 0x0001, 0x0002 },
6002 { 0x09, 0x0000, 0x0080 },
6003 { 0x19, 0x0000, 0x0224 }
6006 rtl_hw_start_8168f(tp);
6008 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6010 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6012 /* Adjust EEE LED frequency */
6013 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6016 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6018 static const struct ephy_info e_info_8168f_1[] = {
6019 { 0x06, 0x00c0, 0x0020 },
6020 { 0x0f, 0xffff, 0x5200 },
6021 { 0x1e, 0x0000, 0x4000 },
6022 { 0x19, 0x0000, 0x0224 }
6025 rtl_hw_start_8168f(tp);
6026 rtl_pcie_state_l2l3_enable(tp, false);
6028 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6030 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6033 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6035 void __iomem *ioaddr = tp->mmio_addr;
6036 struct pci_dev *pdev = tp->pci_dev;
6038 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6040 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6041 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6042 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6043 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6045 rtl_csi_access_enable_1(tp);
6047 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6049 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6050 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6051 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6053 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6054 RTL_W8(MaxTxPacketSize, EarlySize);
6056 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6057 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6059 /* Adjust EEE LED frequency */
6060 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6062 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6063 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6065 rtl_pcie_state_l2l3_enable(tp, false);
6068 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6070 void __iomem *ioaddr = tp->mmio_addr;
6071 static const struct ephy_info e_info_8168g_1[] = {
6072 { 0x00, 0x0000, 0x0008 },
6073 { 0x0c, 0x37d0, 0x0820 },
6074 { 0x1e, 0x0000, 0x0001 },
6075 { 0x19, 0x8000, 0x0000 }
6078 rtl_hw_start_8168g(tp);
6080 /* disable aspm and clock request before access ephy */
6081 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6082 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6083 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6086 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6088 void __iomem *ioaddr = tp->mmio_addr;
6089 static const struct ephy_info e_info_8168g_2[] = {
6090 { 0x00, 0x0000, 0x0008 },
6091 { 0x0c, 0x3df0, 0x0200 },
6092 { 0x19, 0xffff, 0xfc00 },
6093 { 0x1e, 0xffff, 0x20eb }
6096 rtl_hw_start_8168g(tp);
6098 /* disable aspm and clock request before access ephy */
6099 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6100 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6101 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6104 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6106 void __iomem *ioaddr = tp->mmio_addr;
6107 static const struct ephy_info e_info_8411_2[] = {
6108 { 0x00, 0x0000, 0x0008 },
6109 { 0x0c, 0x3df0, 0x0200 },
6110 { 0x0f, 0xffff, 0x5200 },
6111 { 0x19, 0x0020, 0x0000 },
6112 { 0x1e, 0x0000, 0x2000 }
6115 rtl_hw_start_8168g(tp);
6117 /* disable aspm and clock request before access ephy */
6118 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6119 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6120 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6123 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6125 void __iomem *ioaddr = tp->mmio_addr;
6126 struct pci_dev *pdev = tp->pci_dev;
6129 static const struct ephy_info e_info_8168h_1[] = {
6130 { 0x1e, 0x0800, 0x0001 },
6131 { 0x1d, 0x0000, 0x0800 },
6132 { 0x05, 0xffff, 0x2089 },
6133 { 0x06, 0xffff, 0x5881 },
6134 { 0x04, 0xffff, 0x154a },
6135 { 0x01, 0xffff, 0x068b }
6138 /* disable aspm and clock request before access ephy */
6139 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6140 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6141 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6143 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6145 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6146 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6147 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6148 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6150 rtl_csi_access_enable_1(tp);
6152 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6154 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6155 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6157 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6159 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6161 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6163 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6164 RTL_W8(MaxTxPacketSize, EarlySize);
6166 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6167 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6169 /* Adjust EEE LED frequency */
6170 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6172 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6173 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6175 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6177 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6179 rtl_pcie_state_l2l3_enable(tp, false);
6181 rtl_writephy(tp, 0x1f, 0x0c42);
6182 rg_saw_cnt = rtl_readphy(tp, 0x13);
6183 rtl_writephy(tp, 0x1f, 0x0000);
6184 if (rg_saw_cnt > 0) {
6187 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6188 sw_cnt_1ms_ini &= 0x0fff;
6189 data = r8168_mac_ocp_read(tp, 0xd412);
6191 data |= sw_cnt_1ms_ini;
6192 r8168_mac_ocp_write(tp, 0xd412, data);
6195 data = r8168_mac_ocp_read(tp, 0xe056);
6198 r8168_mac_ocp_write(tp, 0xe056, data);
6200 data = r8168_mac_ocp_read(tp, 0xe052);
6203 r8168_mac_ocp_write(tp, 0xe052, data);
6205 data = r8168_mac_ocp_read(tp, 0xe0d6);
6208 r8168_mac_ocp_write(tp, 0xe0d6, data);
6210 data = r8168_mac_ocp_read(tp, 0xd420);
6213 r8168_mac_ocp_write(tp, 0xd420, data);
6215 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6216 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6217 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6218 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6221 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6223 void __iomem *ioaddr = tp->mmio_addr;
6224 struct pci_dev *pdev = tp->pci_dev;
6226 rtl8168ep_stop_cmac(tp);
6228 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6230 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6231 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6232 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6233 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6235 rtl_csi_access_enable_1(tp);
6237 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6239 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6240 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6242 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6244 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6246 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6247 RTL_W8(MaxTxPacketSize, EarlySize);
6249 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6250 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6252 /* Adjust EEE LED frequency */
6253 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6255 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6257 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6259 rtl_pcie_state_l2l3_enable(tp, false);
6262 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6264 void __iomem *ioaddr = tp->mmio_addr;
6265 static const struct ephy_info e_info_8168ep_1[] = {
6266 { 0x00, 0xffff, 0x10ab },
6267 { 0x06, 0xffff, 0xf030 },
6268 { 0x08, 0xffff, 0x2006 },
6269 { 0x0d, 0xffff, 0x1666 },
6270 { 0x0c, 0x3ff0, 0x0000 }
6273 /* disable aspm and clock request before access ephy */
6274 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6275 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6276 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6278 rtl_hw_start_8168ep(tp);
6281 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6283 void __iomem *ioaddr = tp->mmio_addr;
6284 static const struct ephy_info e_info_8168ep_2[] = {
6285 { 0x00, 0xffff, 0x10a3 },
6286 { 0x19, 0xffff, 0xfc00 },
6287 { 0x1e, 0xffff, 0x20ea }
6290 /* disable aspm and clock request before access ephy */
6291 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6292 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6293 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6295 rtl_hw_start_8168ep(tp);
6297 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6298 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6301 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6303 void __iomem *ioaddr = tp->mmio_addr;
6305 static const struct ephy_info e_info_8168ep_3[] = {
6306 { 0x00, 0xffff, 0x10a3 },
6307 { 0x19, 0xffff, 0x7c00 },
6308 { 0x1e, 0xffff, 0x20eb },
6309 { 0x0d, 0xffff, 0x1666 }
6312 /* disable aspm and clock request before access ephy */
6313 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6314 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6315 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6317 rtl_hw_start_8168ep(tp);
6319 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6320 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6322 data = r8168_mac_ocp_read(tp, 0xd3e2);
6325 r8168_mac_ocp_write(tp, 0xd3e2, data);
6327 data = r8168_mac_ocp_read(tp, 0xd3e4);
6329 r8168_mac_ocp_write(tp, 0xd3e4, data);
6331 data = r8168_mac_ocp_read(tp, 0xe860);
6333 r8168_mac_ocp_write(tp, 0xe860, data);
6336 static void rtl_hw_start_8168(struct net_device *dev)
6338 struct rtl8169_private *tp = netdev_priv(dev);
6339 void __iomem *ioaddr = tp->mmio_addr;
6341 RTL_W8(Cfg9346, Cfg9346_Unlock);
6343 RTL_W8(MaxTxPacketSize, TxPacketMax);
6345 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6347 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6349 RTL_W16(CPlusCmd, tp->cp_cmd);
6351 RTL_W16(IntrMitigate, 0x5151);
6353 /* Work around for RxFIFO overflow. */
6354 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6355 tp->event_slow |= RxFIFOOver | PCSTimeout;
6356 tp->event_slow &= ~RxOverflow;
6359 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6361 rtl_set_rx_tx_config_registers(tp);
6365 switch (tp->mac_version) {
6366 case RTL_GIGA_MAC_VER_11:
6367 rtl_hw_start_8168bb(tp);
6370 case RTL_GIGA_MAC_VER_12:
6371 case RTL_GIGA_MAC_VER_17:
6372 rtl_hw_start_8168bef(tp);
6375 case RTL_GIGA_MAC_VER_18:
6376 rtl_hw_start_8168cp_1(tp);
6379 case RTL_GIGA_MAC_VER_19:
6380 rtl_hw_start_8168c_1(tp);
6383 case RTL_GIGA_MAC_VER_20:
6384 rtl_hw_start_8168c_2(tp);
6387 case RTL_GIGA_MAC_VER_21:
6388 rtl_hw_start_8168c_3(tp);
6391 case RTL_GIGA_MAC_VER_22:
6392 rtl_hw_start_8168c_4(tp);
6395 case RTL_GIGA_MAC_VER_23:
6396 rtl_hw_start_8168cp_2(tp);
6399 case RTL_GIGA_MAC_VER_24:
6400 rtl_hw_start_8168cp_3(tp);
6403 case RTL_GIGA_MAC_VER_25:
6404 case RTL_GIGA_MAC_VER_26:
6405 case RTL_GIGA_MAC_VER_27:
6406 rtl_hw_start_8168d(tp);
6409 case RTL_GIGA_MAC_VER_28:
6410 rtl_hw_start_8168d_4(tp);
6413 case RTL_GIGA_MAC_VER_31:
6414 rtl_hw_start_8168dp(tp);
6417 case RTL_GIGA_MAC_VER_32:
6418 case RTL_GIGA_MAC_VER_33:
6419 rtl_hw_start_8168e_1(tp);
6421 case RTL_GIGA_MAC_VER_34:
6422 rtl_hw_start_8168e_2(tp);
6425 case RTL_GIGA_MAC_VER_35:
6426 case RTL_GIGA_MAC_VER_36:
6427 rtl_hw_start_8168f_1(tp);
6430 case RTL_GIGA_MAC_VER_38:
6431 rtl_hw_start_8411(tp);
6434 case RTL_GIGA_MAC_VER_40:
6435 case RTL_GIGA_MAC_VER_41:
6436 rtl_hw_start_8168g_1(tp);
6438 case RTL_GIGA_MAC_VER_42:
6439 rtl_hw_start_8168g_2(tp);
6442 case RTL_GIGA_MAC_VER_44:
6443 rtl_hw_start_8411_2(tp);
6446 case RTL_GIGA_MAC_VER_45:
6447 case RTL_GIGA_MAC_VER_46:
6448 rtl_hw_start_8168h_1(tp);
6451 case RTL_GIGA_MAC_VER_49:
6452 rtl_hw_start_8168ep_1(tp);
6455 case RTL_GIGA_MAC_VER_50:
6456 rtl_hw_start_8168ep_2(tp);
6459 case RTL_GIGA_MAC_VER_51:
6460 rtl_hw_start_8168ep_3(tp);
6464 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6465 dev->name, tp->mac_version);
6469 RTL_W8(Cfg9346, Cfg9346_Lock);
6471 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6473 rtl_set_rx_mode(dev);
6475 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6478 #define R810X_CPCMD_QUIRK_MASK (\
6489 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6491 void __iomem *ioaddr = tp->mmio_addr;
6492 struct pci_dev *pdev = tp->pci_dev;
6493 static const struct ephy_info e_info_8102e_1[] = {
6494 { 0x01, 0, 0x6e65 },
6495 { 0x02, 0, 0x091f },
6496 { 0x03, 0, 0xc2f9 },
6497 { 0x06, 0, 0xafb5 },
6498 { 0x07, 0, 0x0e00 },
6499 { 0x19, 0, 0xec80 },
6500 { 0x01, 0, 0x2e65 },
6505 rtl_csi_access_enable_2(tp);
6507 RTL_W8(DBG_REG, FIX_NAK_1);
6509 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6512 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6513 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6515 cfg1 = RTL_R8(Config1);
6516 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6517 RTL_W8(Config1, cfg1 & ~LEDS0);
6519 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6522 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6524 void __iomem *ioaddr = tp->mmio_addr;
6525 struct pci_dev *pdev = tp->pci_dev;
6527 rtl_csi_access_enable_2(tp);
6529 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6531 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6532 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6535 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6537 rtl_hw_start_8102e_2(tp);
6539 rtl_ephy_write(tp, 0x03, 0xc2f9);
6542 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6544 void __iomem *ioaddr = tp->mmio_addr;
6545 static const struct ephy_info e_info_8105e_1[] = {
6546 { 0x07, 0, 0x4000 },
6547 { 0x19, 0, 0x0200 },
6548 { 0x19, 0, 0x0020 },
6549 { 0x1e, 0, 0x2000 },
6550 { 0x03, 0, 0x0001 },
6551 { 0x19, 0, 0x0100 },
6552 { 0x19, 0, 0x0004 },
6556 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6557 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6559 /* Disable Early Tally Counter */
6560 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6562 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6563 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6565 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6567 rtl_pcie_state_l2l3_enable(tp, false);
6570 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6572 rtl_hw_start_8105e_1(tp);
6573 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6576 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6578 void __iomem *ioaddr = tp->mmio_addr;
6579 static const struct ephy_info e_info_8402[] = {
6580 { 0x19, 0xffff, 0xff64 },
6584 rtl_csi_access_enable_2(tp);
6586 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6587 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6589 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6590 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6592 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6594 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6596 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6597 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6598 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6599 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6600 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6601 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6602 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6604 rtl_pcie_state_l2l3_enable(tp, false);
6607 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6609 void __iomem *ioaddr = tp->mmio_addr;
6611 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6612 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6614 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6615 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6616 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6618 rtl_pcie_state_l2l3_enable(tp, false);
6621 static void rtl_hw_start_8101(struct net_device *dev)
6623 struct rtl8169_private *tp = netdev_priv(dev);
6624 void __iomem *ioaddr = tp->mmio_addr;
6625 struct pci_dev *pdev = tp->pci_dev;
6627 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6628 tp->event_slow &= ~RxFIFOOver;
6630 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6631 tp->mac_version == RTL_GIGA_MAC_VER_16)
6632 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6633 PCI_EXP_DEVCTL_NOSNOOP_EN);
6635 RTL_W8(Cfg9346, Cfg9346_Unlock);
6637 RTL_W8(MaxTxPacketSize, TxPacketMax);
6639 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6641 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6642 RTL_W16(CPlusCmd, tp->cp_cmd);
6644 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6646 rtl_set_rx_tx_config_registers(tp);
6648 switch (tp->mac_version) {
6649 case RTL_GIGA_MAC_VER_07:
6650 rtl_hw_start_8102e_1(tp);
6653 case RTL_GIGA_MAC_VER_08:
6654 rtl_hw_start_8102e_3(tp);
6657 case RTL_GIGA_MAC_VER_09:
6658 rtl_hw_start_8102e_2(tp);
6661 case RTL_GIGA_MAC_VER_29:
6662 rtl_hw_start_8105e_1(tp);
6664 case RTL_GIGA_MAC_VER_30:
6665 rtl_hw_start_8105e_2(tp);
6668 case RTL_GIGA_MAC_VER_37:
6669 rtl_hw_start_8402(tp);
6672 case RTL_GIGA_MAC_VER_39:
6673 rtl_hw_start_8106(tp);
6675 case RTL_GIGA_MAC_VER_43:
6676 rtl_hw_start_8168g_2(tp);
6678 case RTL_GIGA_MAC_VER_47:
6679 case RTL_GIGA_MAC_VER_48:
6680 rtl_hw_start_8168h_1(tp);
6684 RTL_W8(Cfg9346, Cfg9346_Lock);
6686 RTL_W16(IntrMitigate, 0x0000);
6688 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6690 rtl_set_rx_mode(dev);
6694 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6697 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6699 struct rtl8169_private *tp = netdev_priv(dev);
6701 if (new_mtu < ETH_ZLEN ||
6702 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6705 if (new_mtu > ETH_DATA_LEN)
6706 rtl_hw_jumbo_enable(tp);
6708 rtl_hw_jumbo_disable(tp);
6711 netdev_update_features(dev);
6716 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6718 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6719 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6722 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6723 void **data_buff, struct RxDesc *desc)
6725 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6730 rtl8169_make_unusable_by_asic(desc);
6733 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6735 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6737 /* Force memory writes to complete before releasing descriptor */
6740 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6743 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6746 desc->addr = cpu_to_le64(mapping);
6747 rtl8169_mark_to_asic(desc, rx_buf_sz);
6750 static inline void *rtl8169_align(void *data)
6752 return (void *)ALIGN((long)data, 16);
6755 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6756 struct RxDesc *desc)
6760 struct device *d = &tp->pci_dev->dev;
6761 struct net_device *dev = tp->dev;
6762 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6764 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6768 if (rtl8169_align(data) != data) {
6770 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6775 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6777 if (unlikely(dma_mapping_error(d, mapping))) {
6778 if (net_ratelimit())
6779 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6783 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6791 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6795 for (i = 0; i < NUM_RX_DESC; i++) {
6796 if (tp->Rx_databuff[i]) {
6797 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6798 tp->RxDescArray + i);
6803 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6805 desc->opts1 |= cpu_to_le32(RingEnd);
6808 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6812 for (i = 0; i < NUM_RX_DESC; i++) {
6815 if (tp->Rx_databuff[i])
6818 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6820 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6823 tp->Rx_databuff[i] = data;
6826 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6830 rtl8169_rx_clear(tp);
6834 static int rtl8169_init_ring(struct net_device *dev)
6836 struct rtl8169_private *tp = netdev_priv(dev);
6838 rtl8169_init_ring_indexes(tp);
6840 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6841 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6843 return rtl8169_rx_fill(tp);
6846 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6847 struct TxDesc *desc)
6849 unsigned int len = tx_skb->len;
6851 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6859 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6864 for (i = 0; i < n; i++) {
6865 unsigned int entry = (start + i) % NUM_TX_DESC;
6866 struct ring_info *tx_skb = tp->tx_skb + entry;
6867 unsigned int len = tx_skb->len;
6870 struct sk_buff *skb = tx_skb->skb;
6872 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6873 tp->TxDescArray + entry);
6875 tp->dev->stats.tx_dropped++;
6876 dev_kfree_skb_any(skb);
6883 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6885 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6886 tp->cur_tx = tp->dirty_tx = 0;
6889 static void rtl_reset_work(struct rtl8169_private *tp)
6891 struct net_device *dev = tp->dev;
6894 napi_disable(&tp->napi);
6895 netif_stop_queue(dev);
6896 synchronize_sched();
6898 rtl8169_hw_reset(tp);
6900 for (i = 0; i < NUM_RX_DESC; i++)
6901 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6903 rtl8169_tx_clear(tp);
6904 rtl8169_init_ring_indexes(tp);
6906 napi_enable(&tp->napi);
6908 netif_wake_queue(dev);
6909 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6912 static void rtl8169_tx_timeout(struct net_device *dev)
6914 struct rtl8169_private *tp = netdev_priv(dev);
6916 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6919 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6922 struct skb_shared_info *info = skb_shinfo(skb);
6923 unsigned int cur_frag, entry;
6924 struct TxDesc *uninitialized_var(txd);
6925 struct device *d = &tp->pci_dev->dev;
6928 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6929 const skb_frag_t *frag = info->frags + cur_frag;
6934 entry = (entry + 1) % NUM_TX_DESC;
6936 txd = tp->TxDescArray + entry;
6937 len = skb_frag_size(frag);
6938 addr = skb_frag_address(frag);
6939 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6940 if (unlikely(dma_mapping_error(d, mapping))) {
6941 if (net_ratelimit())
6942 netif_err(tp, drv, tp->dev,
6943 "Failed to map TX fragments DMA!\n");
6947 /* Anti gcc 2.95.3 bugware (sic) */
6948 status = opts[0] | len |
6949 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6951 txd->opts1 = cpu_to_le32(status);
6952 txd->opts2 = cpu_to_le32(opts[1]);
6953 txd->addr = cpu_to_le64(mapping);
6955 tp->tx_skb[entry].len = len;
6959 tp->tx_skb[entry].skb = skb;
6960 txd->opts1 |= cpu_to_le32(LastFrag);
6966 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6970 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6972 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6975 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6976 struct net_device *dev);
6977 /* r8169_csum_workaround()
6978 * The hw limites the value the transport offset. When the offset is out of the
6979 * range, calculate the checksum by sw.
6981 static void r8169_csum_workaround(struct rtl8169_private *tp,
6982 struct sk_buff *skb)
6984 if (skb_shinfo(skb)->gso_size) {
6985 netdev_features_t features = tp->dev->features;
6986 struct sk_buff *segs, *nskb;
6988 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6989 segs = skb_gso_segment(skb, features);
6990 if (IS_ERR(segs) || !segs)
6997 rtl8169_start_xmit(nskb, tp->dev);
7000 dev_consume_skb_any(skb);
7001 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7002 if (skb_checksum_help(skb) < 0)
7005 rtl8169_start_xmit(skb, tp->dev);
7007 struct net_device_stats *stats;
7010 stats = &tp->dev->stats;
7011 stats->tx_dropped++;
7012 dev_kfree_skb_any(skb);
7016 /* msdn_giant_send_check()
7017 * According to the document of microsoft, the TCP Pseudo Header excludes the
7018 * packet length for IPv6 TCP large packets.
7020 static int msdn_giant_send_check(struct sk_buff *skb)
7022 const struct ipv6hdr *ipv6h;
7026 ret = skb_cow_head(skb, 0);
7030 ipv6h = ipv6_hdr(skb);
7034 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7039 static inline __be16 get_protocol(struct sk_buff *skb)
7043 if (skb->protocol == htons(ETH_P_8021Q))
7044 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7046 protocol = skb->protocol;
7051 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7052 struct sk_buff *skb, u32 *opts)
7054 u32 mss = skb_shinfo(skb)->gso_size;
7058 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7059 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7060 const struct iphdr *ip = ip_hdr(skb);
7062 if (ip->protocol == IPPROTO_TCP)
7063 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7064 else if (ip->protocol == IPPROTO_UDP)
7065 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7073 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7074 struct sk_buff *skb, u32 *opts)
7076 u32 transport_offset = (u32)skb_transport_offset(skb);
7077 u32 mss = skb_shinfo(skb)->gso_size;
7080 if (transport_offset > GTTCPHO_MAX) {
7081 netif_warn(tp, tx_err, tp->dev,
7082 "Invalid transport offset 0x%x for TSO\n",
7087 switch (get_protocol(skb)) {
7088 case htons(ETH_P_IP):
7089 opts[0] |= TD1_GTSENV4;
7092 case htons(ETH_P_IPV6):
7093 if (msdn_giant_send_check(skb))
7096 opts[0] |= TD1_GTSENV6;
7104 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7105 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7106 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7109 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7110 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7112 if (transport_offset > TCPHO_MAX) {
7113 netif_warn(tp, tx_err, tp->dev,
7114 "Invalid transport offset 0x%x\n",
7119 switch (get_protocol(skb)) {
7120 case htons(ETH_P_IP):
7121 opts[1] |= TD1_IPv4_CS;
7122 ip_protocol = ip_hdr(skb)->protocol;
7125 case htons(ETH_P_IPV6):
7126 opts[1] |= TD1_IPv6_CS;
7127 ip_protocol = ipv6_hdr(skb)->nexthdr;
7131 ip_protocol = IPPROTO_RAW;
7135 if (ip_protocol == IPPROTO_TCP)
7136 opts[1] |= TD1_TCP_CS;
7137 else if (ip_protocol == IPPROTO_UDP)
7138 opts[1] |= TD1_UDP_CS;
7142 opts[1] |= transport_offset << TCPHO_SHIFT;
7144 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7145 return !eth_skb_pad(skb);
7151 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7152 struct net_device *dev)
7154 struct rtl8169_private *tp = netdev_priv(dev);
7155 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7156 struct TxDesc *txd = tp->TxDescArray + entry;
7157 void __iomem *ioaddr = tp->mmio_addr;
7158 struct device *d = &tp->pci_dev->dev;
7164 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7165 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7169 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7172 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7175 if (!tp->tso_csum(tp, skb, opts)) {
7176 r8169_csum_workaround(tp, skb);
7177 return NETDEV_TX_OK;
7180 len = skb_headlen(skb);
7181 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7182 if (unlikely(dma_mapping_error(d, mapping))) {
7183 if (net_ratelimit())
7184 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7188 tp->tx_skb[entry].len = len;
7189 txd->addr = cpu_to_le64(mapping);
7191 frags = rtl8169_xmit_frags(tp, skb, opts);
7195 opts[0] |= FirstFrag;
7197 opts[0] |= FirstFrag | LastFrag;
7198 tp->tx_skb[entry].skb = skb;
7201 txd->opts2 = cpu_to_le32(opts[1]);
7203 skb_tx_timestamp(skb);
7205 /* Force memory writes to complete before releasing descriptor */
7208 /* Anti gcc 2.95.3 bugware (sic) */
7209 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7210 txd->opts1 = cpu_to_le32(status);
7212 /* Force all memory writes to complete before notifying device */
7215 tp->cur_tx += frags + 1;
7217 RTL_W8(TxPoll, NPQ);
7221 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7222 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7223 * not miss a ring update when it notices a stopped queue.
7226 netif_stop_queue(dev);
7227 /* Sync with rtl_tx:
7228 * - publish queue status and cur_tx ring index (write barrier)
7229 * - refresh dirty_tx ring index (read barrier).
7230 * May the current thread have a pessimistic view of the ring
7231 * status and forget to wake up queue, a racing rtl_tx thread
7235 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7236 netif_wake_queue(dev);
7239 return NETDEV_TX_OK;
7242 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7244 dev_kfree_skb_any(skb);
7245 dev->stats.tx_dropped++;
7246 return NETDEV_TX_OK;
7249 netif_stop_queue(dev);
7250 dev->stats.tx_dropped++;
7251 return NETDEV_TX_BUSY;
7254 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7256 struct rtl8169_private *tp = netdev_priv(dev);
7257 struct pci_dev *pdev = tp->pci_dev;
7258 u16 pci_status, pci_cmd;
7260 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7261 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7263 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7264 pci_cmd, pci_status);
7267 * The recovery sequence below admits a very elaborated explanation:
7268 * - it seems to work;
7269 * - I did not see what else could be done;
7270 * - it makes iop3xx happy.
7272 * Feel free to adjust to your needs.
7274 if (pdev->broken_parity_status)
7275 pci_cmd &= ~PCI_COMMAND_PARITY;
7277 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7279 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7281 pci_write_config_word(pdev, PCI_STATUS,
7282 pci_status & (PCI_STATUS_DETECTED_PARITY |
7283 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7284 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7286 /* The infamous DAC f*ckup only happens at boot time */
7287 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7288 void __iomem *ioaddr = tp->mmio_addr;
7290 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7291 tp->cp_cmd &= ~PCIDAC;
7292 RTL_W16(CPlusCmd, tp->cp_cmd);
7293 dev->features &= ~NETIF_F_HIGHDMA;
7296 rtl8169_hw_reset(tp);
7298 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7301 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7303 unsigned int dirty_tx, tx_left;
7305 dirty_tx = tp->dirty_tx;
7307 tx_left = tp->cur_tx - dirty_tx;
7309 while (tx_left > 0) {
7310 unsigned int entry = dirty_tx % NUM_TX_DESC;
7311 struct ring_info *tx_skb = tp->tx_skb + entry;
7314 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7315 if (status & DescOwn)
7318 /* This barrier is needed to keep us from reading
7319 * any other fields out of the Tx descriptor until
7320 * we know the status of DescOwn
7324 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7325 tp->TxDescArray + entry);
7326 if (status & LastFrag) {
7327 u64_stats_update_begin(&tp->tx_stats.syncp);
7328 tp->tx_stats.packets++;
7329 tp->tx_stats.bytes += tx_skb->skb->len;
7330 u64_stats_update_end(&tp->tx_stats.syncp);
7331 dev_kfree_skb_any(tx_skb->skb);
7338 if (tp->dirty_tx != dirty_tx) {
7339 tp->dirty_tx = dirty_tx;
7340 /* Sync with rtl8169_start_xmit:
7341 * - publish dirty_tx ring index (write barrier)
7342 * - refresh cur_tx ring index and queue status (read barrier)
7343 * May the current thread miss the stopped queue condition,
7344 * a racing xmit thread can only have a right view of the
7348 if (netif_queue_stopped(dev) &&
7349 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7350 netif_wake_queue(dev);
7353 * 8168 hack: TxPoll requests are lost when the Tx packets are
7354 * too close. Let's kick an extra TxPoll request when a burst
7355 * of start_xmit activity is detected (if it is not detected,
7356 * it is slow enough). -- FR
7358 if (tp->cur_tx != dirty_tx) {
7359 void __iomem *ioaddr = tp->mmio_addr;
7361 RTL_W8(TxPoll, NPQ);
7366 static inline int rtl8169_fragmented_frame(u32 status)
7368 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7371 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7373 u32 status = opts1 & RxProtoMask;
7375 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7376 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7377 skb->ip_summed = CHECKSUM_UNNECESSARY;
7379 skb_checksum_none_assert(skb);
7382 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7383 struct rtl8169_private *tp,
7387 struct sk_buff *skb;
7388 struct device *d = &tp->pci_dev->dev;
7390 data = rtl8169_align(data);
7391 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7393 skb = napi_alloc_skb(&tp->napi, pkt_size);
7395 memcpy(skb->data, data, pkt_size);
7396 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7401 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7403 unsigned int cur_rx, rx_left;
7406 cur_rx = tp->cur_rx;
7408 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7409 unsigned int entry = cur_rx % NUM_RX_DESC;
7410 struct RxDesc *desc = tp->RxDescArray + entry;
7413 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7414 if (status & DescOwn)
7417 /* This barrier is needed to keep us from reading
7418 * any other fields out of the Rx descriptor until
7419 * we know the status of DescOwn
7423 if (unlikely(status & RxRES)) {
7424 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7426 dev->stats.rx_errors++;
7427 if (status & (RxRWT | RxRUNT))
7428 dev->stats.rx_length_errors++;
7430 dev->stats.rx_crc_errors++;
7431 if (status & RxFOVF) {
7432 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7433 dev->stats.rx_fifo_errors++;
7435 if ((status & (RxRUNT | RxCRC)) &&
7436 !(status & (RxRWT | RxFOVF)) &&
7437 (dev->features & NETIF_F_RXALL))
7440 struct sk_buff *skb;
7445 addr = le64_to_cpu(desc->addr);
7446 if (likely(!(dev->features & NETIF_F_RXFCS)))
7447 pkt_size = (status & 0x00003fff) - 4;
7449 pkt_size = status & 0x00003fff;
7452 * The driver does not support incoming fragmented
7453 * frames. They are seen as a symptom of over-mtu
7456 if (unlikely(rtl8169_fragmented_frame(status))) {
7457 dev->stats.rx_dropped++;
7458 dev->stats.rx_length_errors++;
7459 goto release_descriptor;
7462 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7463 tp, pkt_size, addr);
7465 dev->stats.rx_dropped++;
7466 goto release_descriptor;
7469 rtl8169_rx_csum(skb, status);
7470 skb_put(skb, pkt_size);
7471 skb->protocol = eth_type_trans(skb, dev);
7473 rtl8169_rx_vlan_tag(desc, skb);
7475 napi_gro_receive(&tp->napi, skb);
7477 u64_stats_update_begin(&tp->rx_stats.syncp);
7478 tp->rx_stats.packets++;
7479 tp->rx_stats.bytes += pkt_size;
7480 u64_stats_update_end(&tp->rx_stats.syncp);
7482 if (skb->pkt_type == PACKET_MULTICAST)
7483 dev->stats.multicast++;
7487 rtl8169_mark_to_asic(desc, rx_buf_sz);
7490 count = cur_rx - tp->cur_rx;
7491 tp->cur_rx = cur_rx;
7496 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7498 struct net_device *dev = dev_instance;
7499 struct rtl8169_private *tp = netdev_priv(dev);
7503 status = rtl_get_events(tp);
7504 if (status && status != 0xffff) {
7505 status &= RTL_EVENT_NAPI | tp->event_slow;
7509 rtl_irq_disable(tp);
7510 napi_schedule(&tp->napi);
7513 return IRQ_RETVAL(handled);
7517 * Workqueue context.
7519 static void rtl_slow_event_work(struct rtl8169_private *tp)
7521 struct net_device *dev = tp->dev;
7524 status = rtl_get_events(tp) & tp->event_slow;
7525 rtl_ack_events(tp, status);
7527 if (unlikely(status & RxFIFOOver)) {
7528 switch (tp->mac_version) {
7529 /* Work around for rx fifo overflow */
7530 case RTL_GIGA_MAC_VER_11:
7531 netif_stop_queue(dev);
7532 /* XXX - Hack alert. See rtl_task(). */
7533 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7539 if (unlikely(status & SYSErr))
7540 rtl8169_pcierr_interrupt(dev);
7542 if (status & LinkChg)
7543 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7545 rtl_irq_enable_all(tp);
7548 static void rtl_task(struct work_struct *work)
7550 static const struct {
7552 void (*action)(struct rtl8169_private *);
7554 /* XXX - keep rtl_slow_event_work() as first element. */
7555 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7556 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7557 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7559 struct rtl8169_private *tp =
7560 container_of(work, struct rtl8169_private, wk.work);
7561 struct net_device *dev = tp->dev;
7566 if (!netif_running(dev) ||
7567 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7570 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7573 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7575 rtl_work[i].action(tp);
7579 rtl_unlock_work(tp);
7582 static int rtl8169_poll(struct napi_struct *napi, int budget)
7584 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7585 struct net_device *dev = tp->dev;
7586 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7590 status = rtl_get_events(tp);
7591 rtl_ack_events(tp, status & ~tp->event_slow);
7593 if (status & RTL_EVENT_NAPI_RX)
7594 work_done = rtl_rx(dev, tp, (u32) budget);
7596 if (status & RTL_EVENT_NAPI_TX)
7599 if (status & tp->event_slow) {
7600 enable_mask &= ~tp->event_slow;
7602 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7605 if (work_done < budget) {
7606 napi_complete(napi);
7608 rtl_irq_enable(tp, enable_mask);
7615 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7617 struct rtl8169_private *tp = netdev_priv(dev);
7619 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7622 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7623 RTL_W32(RxMissed, 0);
7626 static void rtl8169_down(struct net_device *dev)
7628 struct rtl8169_private *tp = netdev_priv(dev);
7629 void __iomem *ioaddr = tp->mmio_addr;
7631 del_timer_sync(&tp->timer);
7633 napi_disable(&tp->napi);
7634 netif_stop_queue(dev);
7636 rtl8169_hw_reset(tp);
7638 * At this point device interrupts can not be enabled in any function,
7639 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7640 * and napi is disabled (rtl8169_poll).
7642 rtl8169_rx_missed(dev, ioaddr);
7644 /* Give a racing hard_start_xmit a few cycles to complete. */
7645 synchronize_sched();
7647 rtl8169_tx_clear(tp);
7649 rtl8169_rx_clear(tp);
7651 rtl_pll_power_down(tp);
7654 static int rtl8169_close(struct net_device *dev)
7656 struct rtl8169_private *tp = netdev_priv(dev);
7657 struct pci_dev *pdev = tp->pci_dev;
7659 pm_runtime_get_sync(&pdev->dev);
7661 /* Update counters before going down */
7662 rtl8169_update_counters(dev);
7665 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7668 rtl_unlock_work(tp);
7670 cancel_work_sync(&tp->wk.work);
7672 free_irq(pdev->irq, dev);
7674 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7676 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7678 tp->TxDescArray = NULL;
7679 tp->RxDescArray = NULL;
7681 pm_runtime_put_sync(&pdev->dev);
7686 #ifdef CONFIG_NET_POLL_CONTROLLER
7687 static void rtl8169_netpoll(struct net_device *dev)
7689 struct rtl8169_private *tp = netdev_priv(dev);
7691 rtl8169_interrupt(tp->pci_dev->irq, dev);
7695 static int rtl_open(struct net_device *dev)
7697 struct rtl8169_private *tp = netdev_priv(dev);
7698 void __iomem *ioaddr = tp->mmio_addr;
7699 struct pci_dev *pdev = tp->pci_dev;
7700 int retval = -ENOMEM;
7702 pm_runtime_get_sync(&pdev->dev);
7705 * Rx and Tx descriptors needs 256 bytes alignment.
7706 * dma_alloc_coherent provides more.
7708 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7709 &tp->TxPhyAddr, GFP_KERNEL);
7710 if (!tp->TxDescArray)
7711 goto err_pm_runtime_put;
7713 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7714 &tp->RxPhyAddr, GFP_KERNEL);
7715 if (!tp->RxDescArray)
7718 retval = rtl8169_init_ring(dev);
7722 INIT_WORK(&tp->wk.work, rtl_task);
7726 rtl_request_firmware(tp);
7728 retval = request_irq(pdev->irq, rtl8169_interrupt,
7729 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7732 goto err_release_fw_2;
7736 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7738 napi_enable(&tp->napi);
7740 rtl8169_init_phy(dev, tp);
7742 __rtl8169_set_features(dev, dev->features);
7744 rtl_pll_power_up(tp);
7748 if (!rtl8169_init_counter_offsets(dev))
7749 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7751 netif_start_queue(dev);
7753 rtl_unlock_work(tp);
7755 tp->saved_wolopts = 0;
7756 pm_runtime_put_noidle(&pdev->dev);
7758 rtl8169_check_link_status(dev, tp, ioaddr);
7763 rtl_release_firmware(tp);
7764 rtl8169_rx_clear(tp);
7766 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7768 tp->RxDescArray = NULL;
7770 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7772 tp->TxDescArray = NULL;
7774 pm_runtime_put_noidle(&pdev->dev);
7778 static struct rtnl_link_stats64 *
7779 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7781 struct rtl8169_private *tp = netdev_priv(dev);
7782 void __iomem *ioaddr = tp->mmio_addr;
7785 if (netif_running(dev))
7786 rtl8169_rx_missed(dev, ioaddr);
7789 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7790 stats->rx_packets = tp->rx_stats.packets;
7791 stats->rx_bytes = tp->rx_stats.bytes;
7792 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7795 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7796 stats->tx_packets = tp->tx_stats.packets;
7797 stats->tx_bytes = tp->tx_stats.bytes;
7798 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7800 stats->rx_dropped = dev->stats.rx_dropped;
7801 stats->tx_dropped = dev->stats.tx_dropped;
7802 stats->rx_length_errors = dev->stats.rx_length_errors;
7803 stats->rx_errors = dev->stats.rx_errors;
7804 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7805 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7806 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7807 stats->multicast = dev->stats.multicast;
7810 * Fetch additonal counter values missing in stats collected by driver
7811 * from tally counters.
7813 rtl8169_update_counters(dev);
7816 * Subtract values fetched during initalization.
7817 * See rtl8169_init_counter_offsets for a description why we do that.
7819 stats->tx_errors = le64_to_cpu(tp->counters.tx_errors) -
7820 le64_to_cpu(tp->tc_offset.tx_errors);
7821 stats->collisions = le32_to_cpu(tp->counters.tx_multi_collision) -
7822 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7823 stats->tx_aborted_errors = le16_to_cpu(tp->counters.tx_aborted) -
7824 le16_to_cpu(tp->tc_offset.tx_aborted);
7829 static void rtl8169_net_suspend(struct net_device *dev)
7831 struct rtl8169_private *tp = netdev_priv(dev);
7833 if (!netif_running(dev))
7836 netif_device_detach(dev);
7837 netif_stop_queue(dev);
7840 napi_disable(&tp->napi);
7841 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7842 rtl_unlock_work(tp);
7844 rtl_pll_power_down(tp);
7849 static int rtl8169_suspend(struct device *device)
7851 struct pci_dev *pdev = to_pci_dev(device);
7852 struct net_device *dev = pci_get_drvdata(pdev);
7854 rtl8169_net_suspend(dev);
7859 static void __rtl8169_resume(struct net_device *dev)
7861 struct rtl8169_private *tp = netdev_priv(dev);
7863 netif_device_attach(dev);
7865 rtl_pll_power_up(tp);
7868 napi_enable(&tp->napi);
7869 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7870 rtl_unlock_work(tp);
7872 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7875 static int rtl8169_resume(struct device *device)
7877 struct pci_dev *pdev = to_pci_dev(device);
7878 struct net_device *dev = pci_get_drvdata(pdev);
7879 struct rtl8169_private *tp = netdev_priv(dev);
7881 rtl8169_init_phy(dev, tp);
7883 if (netif_running(dev))
7884 __rtl8169_resume(dev);
7889 static int rtl8169_runtime_suspend(struct device *device)
7891 struct pci_dev *pdev = to_pci_dev(device);
7892 struct net_device *dev = pci_get_drvdata(pdev);
7893 struct rtl8169_private *tp = netdev_priv(dev);
7895 if (!tp->TxDescArray)
7899 tp->saved_wolopts = __rtl8169_get_wol(tp);
7900 __rtl8169_set_wol(tp, WAKE_ANY);
7901 rtl_unlock_work(tp);
7903 rtl8169_net_suspend(dev);
7908 static int rtl8169_runtime_resume(struct device *device)
7910 struct pci_dev *pdev = to_pci_dev(device);
7911 struct net_device *dev = pci_get_drvdata(pdev);
7912 struct rtl8169_private *tp = netdev_priv(dev);
7914 if (!tp->TxDescArray)
7918 __rtl8169_set_wol(tp, tp->saved_wolopts);
7919 tp->saved_wolopts = 0;
7920 rtl_unlock_work(tp);
7922 rtl8169_init_phy(dev, tp);
7924 __rtl8169_resume(dev);
7929 static int rtl8169_runtime_idle(struct device *device)
7931 struct pci_dev *pdev = to_pci_dev(device);
7932 struct net_device *dev = pci_get_drvdata(pdev);
7933 struct rtl8169_private *tp = netdev_priv(dev);
7935 return tp->TxDescArray ? -EBUSY : 0;
7938 static const struct dev_pm_ops rtl8169_pm_ops = {
7939 .suspend = rtl8169_suspend,
7940 .resume = rtl8169_resume,
7941 .freeze = rtl8169_suspend,
7942 .thaw = rtl8169_resume,
7943 .poweroff = rtl8169_suspend,
7944 .restore = rtl8169_resume,
7945 .runtime_suspend = rtl8169_runtime_suspend,
7946 .runtime_resume = rtl8169_runtime_resume,
7947 .runtime_idle = rtl8169_runtime_idle,
7950 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7952 #else /* !CONFIG_PM */
7954 #define RTL8169_PM_OPS NULL
7956 #endif /* !CONFIG_PM */
7958 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7960 void __iomem *ioaddr = tp->mmio_addr;
7962 /* WoL fails with 8168b when the receiver is disabled. */
7963 switch (tp->mac_version) {
7964 case RTL_GIGA_MAC_VER_11:
7965 case RTL_GIGA_MAC_VER_12:
7966 case RTL_GIGA_MAC_VER_17:
7967 pci_clear_master(tp->pci_dev);
7969 RTL_W8(ChipCmd, CmdRxEnb);
7978 static void rtl_shutdown(struct pci_dev *pdev)
7980 struct net_device *dev = pci_get_drvdata(pdev);
7981 struct rtl8169_private *tp = netdev_priv(dev);
7982 struct device *d = &pdev->dev;
7984 pm_runtime_get_sync(d);
7986 rtl8169_net_suspend(dev);
7988 /* Restore original MAC address */
7989 rtl_rar_set(tp, dev->perm_addr);
7991 rtl8169_hw_reset(tp);
7993 if (system_state == SYSTEM_POWER_OFF) {
7994 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7995 rtl_wol_suspend_quirk(tp);
7996 rtl_wol_shutdown_quirk(tp);
7999 pci_wake_from_d3(pdev, true);
8000 pci_set_power_state(pdev, PCI_D3hot);
8003 pm_runtime_put_noidle(d);
8006 static void rtl_remove_one(struct pci_dev *pdev)
8008 struct net_device *dev = pci_get_drvdata(pdev);
8009 struct rtl8169_private *tp = netdev_priv(dev);
8011 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8012 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8013 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8014 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8015 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8016 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8017 r8168_check_dash(tp)) {
8018 rtl8168_driver_stop(tp);
8021 netif_napi_del(&tp->napi);
8023 unregister_netdev(dev);
8025 rtl_release_firmware(tp);
8027 if (pci_dev_run_wake(pdev))
8028 pm_runtime_get_noresume(&pdev->dev);
8030 /* restore original MAC address */
8031 rtl_rar_set(tp, dev->perm_addr);
8033 rtl_disable_msi(pdev, tp);
8034 rtl8169_release_board(pdev, dev, tp->mmio_addr);
8037 static const struct net_device_ops rtl_netdev_ops = {
8038 .ndo_open = rtl_open,
8039 .ndo_stop = rtl8169_close,
8040 .ndo_get_stats64 = rtl8169_get_stats64,
8041 .ndo_start_xmit = rtl8169_start_xmit,
8042 .ndo_tx_timeout = rtl8169_tx_timeout,
8043 .ndo_validate_addr = eth_validate_addr,
8044 .ndo_change_mtu = rtl8169_change_mtu,
8045 .ndo_fix_features = rtl8169_fix_features,
8046 .ndo_set_features = rtl8169_set_features,
8047 .ndo_set_mac_address = rtl_set_mac_address,
8048 .ndo_do_ioctl = rtl8169_ioctl,
8049 .ndo_set_rx_mode = rtl_set_rx_mode,
8050 #ifdef CONFIG_NET_POLL_CONTROLLER
8051 .ndo_poll_controller = rtl8169_netpoll,
8056 static const struct rtl_cfg_info {
8057 void (*hw_start)(struct net_device *);
8058 unsigned int region;
8063 } rtl_cfg_infos [] = {
8065 .hw_start = rtl_hw_start_8169,
8068 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8069 .features = RTL_FEATURE_GMII,
8070 .default_ver = RTL_GIGA_MAC_VER_01,
8073 .hw_start = rtl_hw_start_8168,
8076 .event_slow = SYSErr | LinkChg | RxOverflow,
8077 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8078 .default_ver = RTL_GIGA_MAC_VER_11,
8081 .hw_start = rtl_hw_start_8101,
8084 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8086 .features = RTL_FEATURE_MSI,
8087 .default_ver = RTL_GIGA_MAC_VER_13,
8091 /* Cfg9346_Unlock assumed. */
8092 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8093 const struct rtl_cfg_info *cfg)
8095 void __iomem *ioaddr = tp->mmio_addr;
8099 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8100 if (cfg->features & RTL_FEATURE_MSI) {
8101 if (pci_enable_msi(tp->pci_dev)) {
8102 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8105 msi = RTL_FEATURE_MSI;
8108 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8109 RTL_W8(Config2, cfg2);
8113 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8115 void __iomem *ioaddr = tp->mmio_addr;
8117 return RTL_R8(MCU) & LINK_LIST_RDY;
8120 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8122 void __iomem *ioaddr = tp->mmio_addr;
8124 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8127 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8129 void __iomem *ioaddr = tp->mmio_addr;
8132 tp->ocp_base = OCP_STD_PHY_BASE;
8134 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8136 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8139 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8142 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8144 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8146 data = r8168_mac_ocp_read(tp, 0xe8de);
8148 r8168_mac_ocp_write(tp, 0xe8de, data);
8150 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8153 data = r8168_mac_ocp_read(tp, 0xe8de);
8155 r8168_mac_ocp_write(tp, 0xe8de, data);
8157 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8161 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8163 rtl8168ep_stop_cmac(tp);
8164 rtl_hw_init_8168g(tp);
8167 static void rtl_hw_initialize(struct rtl8169_private *tp)
8169 switch (tp->mac_version) {
8170 case RTL_GIGA_MAC_VER_40:
8171 case RTL_GIGA_MAC_VER_41:
8172 case RTL_GIGA_MAC_VER_42:
8173 case RTL_GIGA_MAC_VER_43:
8174 case RTL_GIGA_MAC_VER_44:
8175 case RTL_GIGA_MAC_VER_45:
8176 case RTL_GIGA_MAC_VER_46:
8177 case RTL_GIGA_MAC_VER_47:
8178 case RTL_GIGA_MAC_VER_48:
8179 rtl_hw_init_8168g(tp);
8181 case RTL_GIGA_MAC_VER_49:
8182 case RTL_GIGA_MAC_VER_50:
8183 case RTL_GIGA_MAC_VER_51:
8184 rtl_hw_init_8168ep(tp);
8191 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8193 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8194 const unsigned int region = cfg->region;
8195 struct rtl8169_private *tp;
8196 struct mii_if_info *mii;
8197 struct net_device *dev;
8198 void __iomem *ioaddr;
8202 if (netif_msg_drv(&debug)) {
8203 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8204 MODULENAME, RTL8169_VERSION);
8207 dev = alloc_etherdev(sizeof (*tp));
8213 SET_NETDEV_DEV(dev, &pdev->dev);
8214 dev->netdev_ops = &rtl_netdev_ops;
8215 tp = netdev_priv(dev);
8218 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8222 mii->mdio_read = rtl_mdio_read;
8223 mii->mdio_write = rtl_mdio_write;
8224 mii->phy_id_mask = 0x1f;
8225 mii->reg_num_mask = 0x1f;
8226 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8228 /* disable ASPM completely as that cause random device stop working
8229 * problems as well as full system hangs for some PCIe devices users */
8230 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8231 PCIE_LINK_STATE_CLKPM);
8233 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8234 rc = pci_enable_device(pdev);
8236 netif_err(tp, probe, dev, "enable failure\n");
8237 goto err_out_free_dev_1;
8240 if (pci_set_mwi(pdev) < 0)
8241 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8243 /* make sure PCI base addr 1 is MMIO */
8244 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8245 netif_err(tp, probe, dev,
8246 "region #%d not an MMIO resource, aborting\n",
8252 /* check for weird/broken PCI region reporting */
8253 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8254 netif_err(tp, probe, dev,
8255 "Invalid PCI region size(s), aborting\n");
8260 rc = pci_request_regions(pdev, MODULENAME);
8262 netif_err(tp, probe, dev, "could not request regions\n");
8268 if ((sizeof(dma_addr_t) > 4) &&
8269 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8270 tp->cp_cmd |= PCIDAC;
8271 dev->features |= NETIF_F_HIGHDMA;
8273 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8275 netif_err(tp, probe, dev, "DMA configuration failed\n");
8276 goto err_out_free_res_3;
8280 /* ioremap MMIO region */
8281 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8283 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8285 goto err_out_free_res_3;
8287 tp->mmio_addr = ioaddr;
8289 if (!pci_is_pcie(pdev))
8290 netif_info(tp, probe, dev, "not PCI Express\n");
8292 /* Identify chip attached to board */
8293 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8297 rtl_irq_disable(tp);
8299 rtl_hw_initialize(tp);
8303 rtl_ack_events(tp, 0xffff);
8305 pci_set_master(pdev);
8307 rtl_init_mdio_ops(tp);
8308 rtl_init_pll_power_ops(tp);
8309 rtl_init_jumbo_ops(tp);
8310 rtl_init_csi_ops(tp);
8312 rtl8169_print_mac_version(tp);
8314 chipset = tp->mac_version;
8315 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8317 RTL_W8(Cfg9346, Cfg9346_Unlock);
8318 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8319 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8320 switch (tp->mac_version) {
8321 case RTL_GIGA_MAC_VER_34:
8322 case RTL_GIGA_MAC_VER_35:
8323 case RTL_GIGA_MAC_VER_36:
8324 case RTL_GIGA_MAC_VER_37:
8325 case RTL_GIGA_MAC_VER_38:
8326 case RTL_GIGA_MAC_VER_40:
8327 case RTL_GIGA_MAC_VER_41:
8328 case RTL_GIGA_MAC_VER_42:
8329 case RTL_GIGA_MAC_VER_43:
8330 case RTL_GIGA_MAC_VER_44:
8331 case RTL_GIGA_MAC_VER_45:
8332 case RTL_GIGA_MAC_VER_46:
8333 case RTL_GIGA_MAC_VER_47:
8334 case RTL_GIGA_MAC_VER_48:
8335 case RTL_GIGA_MAC_VER_49:
8336 case RTL_GIGA_MAC_VER_50:
8337 case RTL_GIGA_MAC_VER_51:
8338 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8339 tp->features |= RTL_FEATURE_WOL;
8340 if ((RTL_R8(Config3) & LinkUp) != 0)
8341 tp->features |= RTL_FEATURE_WOL;
8344 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8345 tp->features |= RTL_FEATURE_WOL;
8348 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8349 tp->features |= RTL_FEATURE_WOL;
8350 tp->features |= rtl_try_msi(tp, cfg);
8351 RTL_W8(Cfg9346, Cfg9346_Lock);
8353 if (rtl_tbi_enabled(tp)) {
8354 tp->set_speed = rtl8169_set_speed_tbi;
8355 tp->get_settings = rtl8169_gset_tbi;
8356 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8357 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8358 tp->link_ok = rtl8169_tbi_link_ok;
8359 tp->do_ioctl = rtl_tbi_ioctl;
8361 tp->set_speed = rtl8169_set_speed_xmii;
8362 tp->get_settings = rtl8169_gset_xmii;
8363 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8364 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8365 tp->link_ok = rtl8169_xmii_link_ok;
8366 tp->do_ioctl = rtl_xmii_ioctl;
8369 mutex_init(&tp->wk.mutex);
8370 u64_stats_init(&tp->rx_stats.syncp);
8371 u64_stats_init(&tp->tx_stats.syncp);
8373 /* Get MAC address */
8374 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8375 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8376 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8377 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8378 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8379 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8380 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8381 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8382 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8383 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8384 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8385 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8386 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8387 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8388 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8389 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8392 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8393 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8395 if (is_valid_ether_addr((u8 *)mac_addr))
8396 rtl_rar_set(tp, (u8 *)mac_addr);
8398 for (i = 0; i < ETH_ALEN; i++)
8399 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8401 dev->ethtool_ops = &rtl8169_ethtool_ops;
8402 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8404 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8406 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8407 * properly for all devices */
8408 dev->features |= NETIF_F_RXCSUM |
8409 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8411 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8412 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8413 NETIF_F_HW_VLAN_CTAG_RX;
8414 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8417 tp->cp_cmd |= RxChkSum | RxVlan;
8420 * Pretend we are using VLANs; This bypasses a nasty bug where
8421 * Interrupts stop flowing on high load on 8110SCd controllers.
8423 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8424 /* Disallow toggling */
8425 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8427 if (tp->txd_version == RTL_TD_0)
8428 tp->tso_csum = rtl8169_tso_csum_v1;
8429 else if (tp->txd_version == RTL_TD_1) {
8430 tp->tso_csum = rtl8169_tso_csum_v2;
8431 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8435 dev->hw_features |= NETIF_F_RXALL;
8436 dev->hw_features |= NETIF_F_RXFCS;
8438 tp->hw_start = cfg->hw_start;
8439 tp->event_slow = cfg->event_slow;
8441 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8442 ~(RxBOVF | RxFOVF) : ~0;
8444 init_timer(&tp->timer);
8445 tp->timer.data = (unsigned long) dev;
8446 tp->timer.function = rtl8169_phy_timer;
8448 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8450 rc = register_netdev(dev);
8454 pci_set_drvdata(pdev, dev);
8456 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8457 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8458 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8459 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8460 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8461 "tx checksumming: %s]\n",
8462 rtl_chip_infos[chipset].jumbo_max,
8463 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8466 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8467 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8468 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8469 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8470 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8471 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8472 r8168_check_dash(tp)) {
8473 rtl8168_driver_start(tp);
8476 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8478 if (pci_dev_run_wake(pdev))
8479 pm_runtime_put_noidle(&pdev->dev);
8481 netif_carrier_off(dev);
8487 netif_napi_del(&tp->napi);
8488 rtl_disable_msi(pdev, tp);
8491 pci_release_regions(pdev);
8493 pci_clear_mwi(pdev);
8494 pci_disable_device(pdev);
8500 static struct pci_driver rtl8169_pci_driver = {
8502 .id_table = rtl8169_pci_tbl,
8503 .probe = rtl_init_one,
8504 .remove = rtl_remove_one,
8505 .shutdown = rtl_shutdown,
8506 .driver.pm = RTL8169_PM_OPS,
8509 module_pci_driver(rtl8169_pci_driver);