drivers/net/ethernet/renesas/sh_eth.c

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   6  *  Copyright (C) 2013 Cogent Embedded, Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *  You should have received a copy of the GNU General Public License along with
  17  *  this program; if not, write to the Free Software Foundation, Inc.,
  18  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  *  The full GNU General Public License is included in this distribution in
  21  *  the file called "COPYING".
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/mdio-bitbang.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44
  45 #include "sh_eth.h"
  46
  47 #define SH_ETH_DEF_MSG_ENABLE \
  48                 (NETIF_MSG_LINK | \
  49                 NETIF_MSG_TIMER | \
  50                 NETIF_MSG_RX_ERR| \
  51                 NETIF_MSG_TX_ERR)
  52
  53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  54         [EDSR]          = 0x0000,
  55         [EDMR]          = 0x0400,
  56         [EDTRR]         = 0x0408,
  57         [EDRRR]         = 0x0410,
  58         [EESR]          = 0x0428,
  59         [EESIPR]        = 0x0430,
  60         [TDLAR]         = 0x0010,
  61         [TDFAR]         = 0x0014,
  62         [TDFXR]         = 0x0018,
  63         [TDFFR]         = 0x001c,
  64         [RDLAR]         = 0x0030,
  65         [RDFAR]         = 0x0034,
  66         [RDFXR]         = 0x0038,
  67         [RDFFR]         = 0x003c,
  68         [TRSCER]        = 0x0438,
  69         [RMFCR]         = 0x0440,
  70         [TFTR]          = 0x0448,
  71         [FDR]           = 0x0450,
  72         [RMCR]          = 0x0458,
  73         [RPADIR]        = 0x0460,
  74         [FCFTR]         = 0x0468,
  75         [CSMR]          = 0x04E4,
  76
  77         [ECMR]          = 0x0500,
  78         [ECSR]          = 0x0510,
  79         [ECSIPR]        = 0x0518,
  80         [PIR]           = 0x0520,
  81         [PSR]           = 0x0528,
  82         [PIPR]          = 0x052c,
  83         [RFLR]          = 0x0508,
  84         [APR]           = 0x0554,
  85         [MPR]           = 0x0558,
  86         [PFTCR]         = 0x055c,
  87         [PFRCR]         = 0x0560,
  88         [TPAUSER]       = 0x0564,
  89         [GECMR]         = 0x05b0,
  90         [BCULR]         = 0x05b4,
  91         [MAHR]          = 0x05c0,
  92         [MALR]          = 0x05c8,
  93         [TROCR]         = 0x0700,
  94         [CDCR]          = 0x0708,
  95         [LCCR]          = 0x0710,
  96         [CEFCR]         = 0x0740,
  97         [FRECR]         = 0x0748,
  98         [TSFRCR]        = 0x0750,
  99         [TLFRCR]        = 0x0758,
 100         [RFCR]          = 0x0760,
 101         [CERCR]         = 0x0768,
 102         [CEECR]         = 0x0770,
 103         [MAFCR]         = 0x0778,
 104         [RMII_MII]      = 0x0790,
 105
 106         [ARSTR]         = 0x0000,
 107         [TSU_CTRST]     = 0x0004,
 108         [TSU_FWEN0]     = 0x0010,
 109         [TSU_FWEN1]     = 0x0014,
 110         [TSU_FCM]       = 0x0018,
 111         [TSU_BSYSL0]    = 0x0020,
 112         [TSU_BSYSL1]    = 0x0024,
 113         [TSU_PRISL0]    = 0x0028,
 114         [TSU_PRISL1]    = 0x002c,
 115         [TSU_FWSL0]     = 0x0030,
 116         [TSU_FWSL1]     = 0x0034,
 117         [TSU_FWSLC]     = 0x0038,
 118         [TSU_QTAG0]     = 0x0040,
 119         [TSU_QTAG1]     = 0x0044,
 120         [TSU_FWSR]      = 0x0050,
 121         [TSU_FWINMK]    = 0x0054,
 122         [TSU_ADQT0]     = 0x0048,
 123         [TSU_ADQT1]     = 0x004c,
 124         [TSU_VTAG0]     = 0x0058,
 125         [TSU_VTAG1]     = 0x005c,
 126         [TSU_ADSBSY]    = 0x0060,
 127         [TSU_TEN]       = 0x0064,
 128         [TSU_POST1]     = 0x0070,
 129         [TSU_POST2]     = 0x0074,
 130         [TSU_POST3]     = 0x0078,
 131         [TSU_POST4]     = 0x007c,
 132         [TSU_ADRH0]     = 0x0100,
 133         [TSU_ADRL0]     = 0x0104,
 134         [TSU_ADRH31]    = 0x01f8,
 135         [TSU_ADRL31]    = 0x01fc,
 136
 137         [TXNLCR0]       = 0x0080,
 138         [TXALCR0]       = 0x0084,
 139         [RXNLCR0]       = 0x0088,
 140         [RXALCR0]       = 0x008c,
 141         [FWNLCR0]       = 0x0090,
 142         [FWALCR0]       = 0x0094,
 143         [TXNLCR1]       = 0x00a0,
 144         [TXALCR1]       = 0x00a0,
 145         [RXNLCR1]       = 0x00a8,
 146         [RXALCR1]       = 0x00ac,
 147         [FWNLCR1]       = 0x00b0,
 148         [FWALCR1]       = 0x00b4,
 149 };
 150
 151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 152         [ECMR]          = 0x0300,
 153         [RFLR]          = 0x0308,
 154         [ECSR]          = 0x0310,
 155         [ECSIPR]        = 0x0318,
 156         [PIR]           = 0x0320,
 157         [PSR]           = 0x0328,
 158         [RDMLR]         = 0x0340,
 159         [IPGR]          = 0x0350,
 160         [APR]           = 0x0354,
 161         [MPR]           = 0x0358,
 162         [RFCF]          = 0x0360,
 163         [TPAUSER]       = 0x0364,
 164         [TPAUSECR]      = 0x0368,
 165         [MAHR]          = 0x03c0,
 166         [MALR]          = 0x03c8,
 167         [TROCR]         = 0x03d0,
 168         [CDCR]          = 0x03d4,
 169         [LCCR]          = 0x03d8,
 170         [CNDCR]         = 0x03dc,
 171         [CEFCR]         = 0x03e4,
 172         [FRECR]         = 0x03e8,
 173         [TSFRCR]        = 0x03ec,
 174         [TLFRCR]        = 0x03f0,
 175         [RFCR]          = 0x03f4,
 176         [MAFCR]         = 0x03f8,
 177
 178         [EDMR]          = 0x0200,
 179         [EDTRR]         = 0x0208,
 180         [EDRRR]         = 0x0210,
 181         [TDLAR]         = 0x0218,
 182         [RDLAR]         = 0x0220,
 183         [EESR]          = 0x0228,
 184         [EESIPR]        = 0x0230,
 185         [TRSCER]        = 0x0238,
 186         [RMFCR]         = 0x0240,
 187         [TFTR]          = 0x0248,
 188         [FDR]           = 0x0250,
 189         [RMCR]          = 0x0258,
 190         [TFUCR]         = 0x0264,
 191         [RFOCR]         = 0x0268,
 192         [FCFTR]         = 0x0270,
 193         [TRIMD]         = 0x027c,
 194 };
 195
 196 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 197         [ECMR]          = 0x0100,
 198         [RFLR]          = 0x0108,
 199         [ECSR]          = 0x0110,
 200         [ECSIPR]        = 0x0118,
 201         [PIR]           = 0x0120,
 202         [PSR]           = 0x0128,
 203         [RDMLR]         = 0x0140,
 204         [IPGR]          = 0x0150,
 205         [APR]           = 0x0154,
 206         [MPR]           = 0x0158,
 207         [TPAUSER]       = 0x0164,
 208         [RFCF]          = 0x0160,
 209         [TPAUSECR]      = 0x0168,
 210         [BCFRR]         = 0x016c,
 211         [MAHR]          = 0x01c0,
 212         [MALR]          = 0x01c8,
 213         [TROCR]         = 0x01d0,
 214         [CDCR]          = 0x01d4,
 215         [LCCR]          = 0x01d8,
 216         [CNDCR]         = 0x01dc,
 217         [CEFCR]         = 0x01e4,
 218         [FRECR]         = 0x01e8,
 219         [TSFRCR]        = 0x01ec,
 220         [TLFRCR]        = 0x01f0,
 221         [RFCR]          = 0x01f4,
 222         [MAFCR]         = 0x01f8,
 223         [RTRATE]        = 0x01fc,
 224
 225         [EDMR]          = 0x0000,
 226         [EDTRR]         = 0x0008,
 227         [EDRRR]         = 0x0010,
 228         [TDLAR]         = 0x0018,
 229         [RDLAR]         = 0x0020,
 230         [EESR]          = 0x0028,
 231         [EESIPR]        = 0x0030,
 232         [TRSCER]        = 0x0038,
 233         [RMFCR]         = 0x0040,
 234         [TFTR]          = 0x0048,
 235         [FDR]           = 0x0050,
 236         [RMCR]          = 0x0058,
 237         [TFUCR]         = 0x0064,
 238         [RFOCR]         = 0x0068,
 239         [FCFTR]         = 0x0070,
 240         [RPADIR]        = 0x0078,
 241         [TRIMD]         = 0x007c,
 242         [RBWAR]         = 0x00c8,
 243         [RDFAR]         = 0x00cc,
 244         [TBRAR]         = 0x00d4,
 245         [TDFAR]         = 0x00d8,
 246 };
 247
 248 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 249         [ECMR]          = 0x0160,
 250         [ECSR]          = 0x0164,
 251         [ECSIPR]        = 0x0168,
 252         [PIR]           = 0x016c,
 253         [MAHR]          = 0x0170,
 254         [MALR]          = 0x0174,
 255         [RFLR]          = 0x0178,
 256         [PSR]           = 0x017c,
 257         [TROCR]         = 0x0180,
 258         [CDCR]          = 0x0184,
 259         [LCCR]          = 0x0188,
 260         [CNDCR]         = 0x018c,
 261         [CEFCR]         = 0x0194,
 262         [FRECR]         = 0x0198,
 263         [TSFRCR]        = 0x019c,
 264         [TLFRCR]        = 0x01a0,
 265         [RFCR]          = 0x01a4,
 266         [MAFCR]         = 0x01a8,
 267         [IPGR]          = 0x01b4,
 268         [APR]           = 0x01b8,
 269         [MPR]           = 0x01bc,
 270         [TPAUSER]       = 0x01c4,
 271         [BCFR]          = 0x01cc,
 272
 273         [ARSTR]         = 0x0000,
 274         [TSU_CTRST]     = 0x0004,
 275         [TSU_FWEN0]     = 0x0010,
 276         [TSU_FWEN1]     = 0x0014,
 277         [TSU_FCM]       = 0x0018,
 278         [TSU_BSYSL0]    = 0x0020,
 279         [TSU_BSYSL1]    = 0x0024,
 280         [TSU_PRISL0]    = 0x0028,
 281         [TSU_PRISL1]    = 0x002c,
 282         [TSU_FWSL0]     = 0x0030,
 283         [TSU_FWSL1]     = 0x0034,
 284         [TSU_FWSLC]     = 0x0038,
 285         [TSU_QTAGM0]    = 0x0040,
 286         [TSU_QTAGM1]    = 0x0044,
 287         [TSU_ADQT0]     = 0x0048,
 288         [TSU_ADQT1]     = 0x004c,
 289         [TSU_FWSR]      = 0x0050,
 290         [TSU_FWINMK]    = 0x0054,
 291         [TSU_ADSBSY]    = 0x0060,
 292         [TSU_TEN]       = 0x0064,
 293         [TSU_POST1]     = 0x0070,
 294         [TSU_POST2]     = 0x0074,
 295         [TSU_POST3]     = 0x0078,
 296         [TSU_POST4]     = 0x007c,
 297
 298         [TXNLCR0]       = 0x0080,
 299         [TXALCR0]       = 0x0084,
 300         [RXNLCR0]       = 0x0088,
 301         [RXALCR0]       = 0x008c,
 302         [FWNLCR0]       = 0x0090,
 303         [FWALCR0]       = 0x0094,
 304         [TXNLCR1]       = 0x00a0,
 305         [TXALCR1]       = 0x00a0,
 306         [RXNLCR1]       = 0x00a8,
 307         [RXALCR1]       = 0x00ac,
 308         [FWNLCR1]       = 0x00b0,
 309         [FWALCR1]       = 0x00b4,
 310
 311         [TSU_ADRH0]     = 0x0100,
 312         [TSU_ADRL0]     = 0x0104,
 313         [TSU_ADRL31]    = 0x01fc,
 314 };
 315
 316 static int sh_eth_is_gether(struct sh_eth_private *mdp)
 317 {
 318         if (mdp->reg_offset == sh_eth_offset_gigabit)
 319                 return 1;
 320         else
 321                 return 0;
 322 }
 323
 324 static void __maybe_unused sh_eth_select_mii(struct net_device *ndev)
 325 {
 326         u32 value = 0x0;
 327         struct sh_eth_private *mdp = netdev_priv(ndev);
 328
 329         switch (mdp->phy_interface) {
 330         case PHY_INTERFACE_MODE_GMII:
 331                 value = 0x2;
 332                 break;
 333         case PHY_INTERFACE_MODE_MII:
 334                 value = 0x1;
 335                 break;
 336         case PHY_INTERFACE_MODE_RMII:
 337                 value = 0x0;
 338                 break;
 339         default:
 340                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 341                 value = 0x1;
 342                 break;
 343         }
 344
 345         sh_eth_write(ndev, value, RMII_MII);
 346 }
 347
 348 static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev)
 349 {
 350         struct sh_eth_private *mdp = netdev_priv(ndev);
 351
 352         if (mdp->duplex) /* Full */
 353                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 354         else            /* Half */
 355                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 356 }
 357
 358 /* There is CPU dependent code */
 359 #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
 360 static void sh_eth_set_rate(struct net_device *ndev)
 361 {
 362         struct sh_eth_private *mdp = netdev_priv(ndev);
 363
 364         switch (mdp->speed) {
 365         case 10: /* 10BASE */
 366                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 367                 break;
 368         case 100:/* 100BASE */
 369                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 370                 break;
 371         default:
 372                 break;
 373         }
 374 }
 375
 376 /* R8A7778/9 */
 377 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 378         .set_duplex     = sh_eth_set_duplex,
 379         .set_rate       = sh_eth_set_rate,
 380
 381         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 382         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 383         .eesipr_value   = 0x01ff009f,
 384
 385         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 386         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 387                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 388         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 389
 390         .apr            = 1,
 391         .mpr            = 1,
 392         .tpauser        = 1,
 393         .hw_swap        = 1,
 394 };
 395 #endif
 396
 397 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 398 {
 399         struct sh_eth_private *mdp = netdev_priv(ndev);
 400
 401         switch (mdp->speed) {
 402         case 10: /* 10BASE */
 403                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 404                 break;
 405         case 100:/* 100BASE */
 406                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 407                 break;
 408         default:
 409                 break;
 410         }
 411 }
 412
 413 /* SH7724 */
 414 static struct sh_eth_cpu_data sh7724_data = {
 415         .set_duplex     = sh_eth_set_duplex,
 416         .set_rate       = sh_eth_set_rate_sh7724,
 417
 418         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 419         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 420         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
 421
 422         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 423         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 424                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 425         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 426
 427         .apr            = 1,
 428         .mpr            = 1,
 429         .tpauser        = 1,
 430         .hw_swap        = 1,
 431         .rpadir         = 1,
 432         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 433 };
 434
 435 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 436 {
 437         struct sh_eth_private *mdp = netdev_priv(ndev);
 438
 439         switch (mdp->speed) {
 440         case 10: /* 10BASE */
 441                 sh_eth_write(ndev, 0, RTRATE);
 442                 break;
 443         case 100:/* 100BASE */
 444                 sh_eth_write(ndev, 1, RTRATE);
 445                 break;
 446         default:
 447                 break;
 448         }
 449 }
 450
 451 /* SH7757 */
 452 static struct sh_eth_cpu_data sh7757_data = {
 453         .set_duplex     = sh_eth_set_duplex,
 454         .set_rate       = sh_eth_set_rate_sh7757,
 455
 456         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 457         .rmcr_value     = 0x00000001,
 458
 459         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 460         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 461                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 462         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 463
 464         .irq_flags      = IRQF_SHARED,
 465         .apr            = 1,
 466         .mpr            = 1,
 467         .tpauser        = 1,
 468         .hw_swap        = 1,
 469         .no_ade         = 1,
 470         .rpadir         = 1,
 471         .rpadir_value   = 2 << 16,
 472 };
 473
 474 #define SH_GIGA_ETH_BASE        0xfee00000
 475 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 476 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 477 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 478 {
 479         int i;
 480         unsigned long mahr[2], malr[2];
 481
 482         /* save MAHR and MALR */
 483         for (i = 0; i < 2; i++) {
 484                 malr[i] = ioread32((void *)GIGA_MALR(i));
 485                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 486         }
 487
 488         /* reset device */
 489         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 490         mdelay(1);
 491
 492         /* restore MAHR and MALR */
 493         for (i = 0; i < 2; i++) {
 494                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 495                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 496         }
 497 }
 498
 499 static void sh_eth_set_rate_giga(struct net_device *ndev)
 500 {
 501         struct sh_eth_private *mdp = netdev_priv(ndev);
 502
 503         switch (mdp->speed) {
 504         case 10: /* 10BASE */
 505                 sh_eth_write(ndev, 0x00000000, GECMR);
 506                 break;
 507         case 100:/* 100BASE */
 508                 sh_eth_write(ndev, 0x00000010, GECMR);
 509                 break;
 510         case 1000: /* 1000BASE */
 511                 sh_eth_write(ndev, 0x00000020, GECMR);
 512                 break;
 513         default:
 514                 break;
 515         }
 516 }
 517
 518 /* SH7757(GETHERC) */
 519 static struct sh_eth_cpu_data sh7757_data_giga = {
 520         .chip_reset     = sh_eth_chip_reset_giga,
 521         .set_duplex     = sh_eth_set_duplex,
 522         .set_rate       = sh_eth_set_rate_giga,
 523
 524         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 525         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 526         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 527
 528         .tx_check       = EESR_TC1 | EESR_FTC,
 529         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 530                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 531                           EESR_ECI,
 532         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 533                           EESR_TFE,
 534         .fdr_value      = 0x0000072f,
 535         .rmcr_value     = 0x00000001,
 536
 537         .irq_flags      = IRQF_SHARED,
 538         .apr            = 1,
 539         .mpr            = 1,
 540         .tpauser        = 1,
 541         .bculr          = 1,
 542         .hw_swap        = 1,
 543         .rpadir         = 1,
 544         .rpadir_value   = 2 << 16,
 545         .no_trimd       = 1,
 546         .no_ade         = 1,
 547         .tsu            = 1,
 548 };
 549
 550 static void sh_eth_chip_reset(struct net_device *ndev)
 551 {
 552         struct sh_eth_private *mdp = netdev_priv(ndev);
 553
 554         /* reset device */
 555         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 556         mdelay(1);
 557 }
 558
 559 static void sh_eth_set_rate_gether(struct net_device *ndev)
 560 {
 561         struct sh_eth_private *mdp = netdev_priv(ndev);
 562
 563         switch (mdp->speed) {
 564         case 10: /* 10BASE */
 565                 sh_eth_write(ndev, GECMR_10, GECMR);
 566                 break;
 567         case 100:/* 100BASE */
 568                 sh_eth_write(ndev, GECMR_100, GECMR);
 569                 break;
 570         case 1000: /* 1000BASE */
 571                 sh_eth_write(ndev, GECMR_1000, GECMR);
 572                 break;
 573         default:
 574                 break;
 575         }
 576 }
 577
 578 /* SH7734 */
 579 static struct sh_eth_cpu_data sh7734_data = {
 580         .chip_reset     = sh_eth_chip_reset,
 581         .set_duplex     = sh_eth_set_duplex,
 582         .set_rate       = sh_eth_set_rate_gether,
 583
 584         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 585         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 586         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 587
 588         .tx_check       = EESR_TC1 | EESR_FTC,
 589         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 590                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 591                           EESR_ECI,
 592         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 593                           EESR_TFE,
 594
 595         .apr            = 1,
 596         .mpr            = 1,
 597         .tpauser        = 1,
 598         .bculr          = 1,
 599         .hw_swap        = 1,
 600         .no_trimd       = 1,
 601         .no_ade         = 1,
 602         .tsu            = 1,
 603         .hw_crc         = 1,
 604         .select_mii     = 1,
 605 };
 606
 607 /* SH7763 */
 608 static struct sh_eth_cpu_data sh7763_data = {
 609         .chip_reset     = sh_eth_chip_reset,
 610         .set_duplex     = sh_eth_set_duplex,
 611         .set_rate       = sh_eth_set_rate_gether,
 612
 613         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 614         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 615         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 616
 617         .tx_check       = EESR_TC1 | EESR_FTC,
 618         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 619                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 620                           EESR_ECI,
 621         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 622                           EESR_TFE,
 623
 624         .apr            = 1,
 625         .mpr            = 1,
 626         .tpauser        = 1,
 627         .bculr          = 1,
 628         .hw_swap        = 1,
 629         .no_trimd       = 1,
 630         .no_ade         = 1,
 631         .tsu            = 1,
 632         .irq_flags      = IRQF_SHARED,
 633 };
 634
 635 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 636 {
 637         struct sh_eth_private *mdp = netdev_priv(ndev);
 638
 639         /* reset device */
 640         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 641         mdelay(1);
 642
 643         sh_eth_select_mii(ndev);
 644 }
 645
 646 /* R8A7740 */
 647 static struct sh_eth_cpu_data r8a7740_data = {
 648         .chip_reset     = sh_eth_chip_reset_r8a7740,
 649         .set_duplex     = sh_eth_set_duplex,
 650         .set_rate       = sh_eth_set_rate_gether,
 651
 652         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 653         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 654         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 655
 656         .tx_check       = EESR_TC1 | EESR_FTC,
 657         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 658                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 659                           EESR_ECI,
 660         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 661                           EESR_TFE,
 662
 663         .apr            = 1,
 664         .mpr            = 1,
 665         .tpauser        = 1,
 666         .bculr          = 1,
 667         .hw_swap        = 1,
 668         .no_trimd       = 1,
 669         .no_ade         = 1,
 670         .tsu            = 1,
 671         .select_mii     = 1,
 672 };
 673
 674 static struct sh_eth_cpu_data sh7619_data = {
 675         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 676
 677         .apr            = 1,
 678         .mpr            = 1,
 679         .tpauser        = 1,
 680         .hw_swap        = 1,
 681 };
 682
 683 static struct sh_eth_cpu_data sh771x_data = {
 684         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 685         .tsu            = 1,
 686 };
 687
 688 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 689 {
 690         if (!cd->ecsr_value)
 691                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 692
 693         if (!cd->ecsipr_value)
 694                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 695
 696         if (!cd->fcftr_value)
 697                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
 698                                   DEFAULT_FIFO_F_D_RFD;
 699
 700         if (!cd->fdr_value)
 701                 cd->fdr_value = DEFAULT_FDR_INIT;
 702
 703         if (!cd->rmcr_value)
 704                 cd->rmcr_value = DEFAULT_RMCR_VALUE;
 705
 706         if (!cd->tx_check)
 707                 cd->tx_check = DEFAULT_TX_CHECK;
 708
 709         if (!cd->eesr_err_check)
 710                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 711
 712         if (!cd->tx_error_check)
 713                 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
 714 }
 715
 716 static int sh_eth_check_reset(struct net_device *ndev)
 717 {
 718         int ret = 0;
 719         int cnt = 100;
 720
 721         while (cnt > 0) {
 722                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 723                         break;
 724                 mdelay(1);
 725                 cnt--;
 726         }
 727         if (cnt < 0) {
 728                 pr_err("Device reset fail\n");
 729                 ret = -ETIMEDOUT;
 730         }
 731         return ret;
 732 }
 733
 734 static int sh_eth_reset(struct net_device *ndev)
 735 {
 736         struct sh_eth_private *mdp = netdev_priv(ndev);
 737         int ret = 0;
 738
 739         if (sh_eth_is_gether(mdp)) {
 740                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 741                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 742                              EDMR);
 743
 744                 ret = sh_eth_check_reset(ndev);
 745                 if (ret)
 746                         goto out;
 747
 748                 /* Table Init */
 749                 sh_eth_write(ndev, 0x0, TDLAR);
 750                 sh_eth_write(ndev, 0x0, TDFAR);
 751                 sh_eth_write(ndev, 0x0, TDFXR);
 752                 sh_eth_write(ndev, 0x0, TDFFR);
 753                 sh_eth_write(ndev, 0x0, RDLAR);
 754                 sh_eth_write(ndev, 0x0, RDFAR);
 755                 sh_eth_write(ndev, 0x0, RDFXR);
 756                 sh_eth_write(ndev, 0x0, RDFFR);
 757
 758                 /* Reset HW CRC register */
 759                 if (mdp->cd->hw_crc)
 760                         sh_eth_write(ndev, 0x0, CSMR);
 761
 762                 /* Select MII mode */
 763                 if (mdp->cd->select_mii)
 764                         sh_eth_select_mii(ndev);
 765         } else {
 766                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 767                              EDMR);
 768                 mdelay(3);
 769                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 770                              EDMR);
 771         }
 772
 773 out:
 774         return ret;
 775 }
 776
 777 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 778 static void sh_eth_set_receive_align(struct sk_buff *skb)
 779 {
 780         int reserve;
 781
 782         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 783         if (reserve)
 784                 skb_reserve(skb, reserve);
 785 }
 786 #else
 787 static void sh_eth_set_receive_align(struct sk_buff *skb)
 788 {
 789         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 790 }
 791 #endif
 792
 793
 794 /* CPU <-> EDMAC endian convert */
 795 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 796 {
 797         switch (mdp->edmac_endian) {
 798         case EDMAC_LITTLE_ENDIAN:
 799                 return cpu_to_le32(x);
 800         case EDMAC_BIG_ENDIAN:
 801                 return cpu_to_be32(x);
 802         }
 803         return x;
 804 }
 805
 806 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 807 {
 808         switch (mdp->edmac_endian) {
 809         case EDMAC_LITTLE_ENDIAN:
 810                 return le32_to_cpu(x);
 811         case EDMAC_BIG_ENDIAN:
 812                 return be32_to_cpu(x);
 813         }
 814         return x;
 815 }
 816
 817 /*
 818  * Program the hardware MAC address from dev->dev_addr.
 819  */
 820 static void update_mac_address(struct net_device *ndev)
 821 {
 822         sh_eth_write(ndev,
 823                 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 824                 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 825         sh_eth_write(ndev,
 826                 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 827 }
 828
 829 /*
 830  * Get MAC address from SuperH MAC address register
 831  *
 832  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 833  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 834  * When you want use this device, you must set MAC address in bootloader.
 835  *
 836  */
 837 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 838 {
 839         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 840                 memcpy(ndev->dev_addr, mac, 6);
 841         } else {
 842                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 843                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 844                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 845                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 846                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 847                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 848         }
 849 }
 850
 851 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 852 {
 853         if (sh_eth_is_gether(mdp))
 854                 return EDTRR_TRNS_GETHER;
 855         else
 856                 return EDTRR_TRNS_ETHER;
 857 }
 858
 859 struct bb_info {
 860         void (*set_gate)(void *addr);
 861         struct mdiobb_ctrl ctrl;
 862         void *addr;
 863         u32 mmd_msk;/* MMD */
 864         u32 mdo_msk;
 865         u32 mdi_msk;
 866         u32 mdc_msk;
 867 };
 868
 869 /* PHY bit set */
 870 static void bb_set(void *addr, u32 msk)
 871 {
 872         iowrite32(ioread32(addr) | msk, addr);
 873 }
 874
 875 /* PHY bit clear */
 876 static void bb_clr(void *addr, u32 msk)
 877 {
 878         iowrite32((ioread32(addr) & ~msk), addr);
 879 }
 880
 881 /* PHY bit read */
 882 static int bb_read(void *addr, u32 msk)
 883 {
 884         return (ioread32(addr) & msk) != 0;
 885 }
 886
 887 /* Data I/O pin control */
 888 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 889 {
 890         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 891
 892         if (bitbang->set_gate)
 893                 bitbang->set_gate(bitbang->addr);
 894
 895         if (bit)
 896                 bb_set(bitbang->addr, bitbang->mmd_msk);
 897         else
 898                 bb_clr(bitbang->addr, bitbang->mmd_msk);
 899 }
 900
 901 /* Set bit data*/
 902 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
 903 {
 904         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 905
 906         if (bitbang->set_gate)
 907                 bitbang->set_gate(bitbang->addr);
 908
 909         if (bit)
 910                 bb_set(bitbang->addr, bitbang->mdo_msk);
 911         else
 912                 bb_clr(bitbang->addr, bitbang->mdo_msk);
 913 }
 914
 915 /* Get bit data*/
 916 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
 917 {
 918         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 919
 920         if (bitbang->set_gate)
 921                 bitbang->set_gate(bitbang->addr);
 922
 923         return bb_read(bitbang->addr, bitbang->mdi_msk);
 924 }
 925
 926 /* MDC pin control */
 927 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 928 {
 929         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 930
 931         if (bitbang->set_gate)
 932                 bitbang->set_gate(bitbang->addr);
 933
 934         if (bit)
 935                 bb_set(bitbang->addr, bitbang->mdc_msk);
 936         else
 937                 bb_clr(bitbang->addr, bitbang->mdc_msk);
 938 }
 939
 940 /* mdio bus control struct */
 941 static struct mdiobb_ops bb_ops = {
 942         .owner = THIS_MODULE,
 943         .set_mdc = sh_mdc_ctrl,
 944         .set_mdio_dir = sh_mmd_ctrl,
 945         .set_mdio_data = sh_set_mdio,
 946         .get_mdio_data = sh_get_mdio,
 947 };
 948
 949 /* free skb and descriptor buffer */
 950 static void sh_eth_ring_free(struct net_device *ndev)
 951 {
 952         struct sh_eth_private *mdp = netdev_priv(ndev);
 953         int i;
 954
 955         /* Free Rx skb ringbuffer */
 956         if (mdp->rx_skbuff) {
 957                 for (i = 0; i < mdp->num_rx_ring; i++) {
 958                         if (mdp->rx_skbuff[i])
 959                                 dev_kfree_skb(mdp->rx_skbuff[i]);
 960                 }
 961         }
 962         kfree(mdp->rx_skbuff);
 963         mdp->rx_skbuff = NULL;
 964
 965         /* Free Tx skb ringbuffer */
 966         if (mdp->tx_skbuff) {
 967                 for (i = 0; i < mdp->num_tx_ring; i++) {
 968                         if (mdp->tx_skbuff[i])
 969                                 dev_kfree_skb(mdp->tx_skbuff[i]);
 970                 }
 971         }
 972         kfree(mdp->tx_skbuff);
 973         mdp->tx_skbuff = NULL;
 974 }
 975
 976 /* format skb and descriptor buffer */
 977 static void sh_eth_ring_format(struct net_device *ndev)
 978 {
 979         struct sh_eth_private *mdp = netdev_priv(ndev);
 980         int i;
 981         struct sk_buff *skb;
 982         struct sh_eth_rxdesc *rxdesc = NULL;
 983         struct sh_eth_txdesc *txdesc = NULL;
 984         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
 985         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
 986
 987         mdp->cur_rx = mdp->cur_tx = 0;
 988         mdp->dirty_rx = mdp->dirty_tx = 0;
 989
 990         memset(mdp->rx_ring, 0, rx_ringsize);
 991
 992         /* build Rx ring buffer */
 993         for (i = 0; i < mdp->num_rx_ring; i++) {
 994                 /* skb */
 995                 mdp->rx_skbuff[i] = NULL;
 996                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
 997                 mdp->rx_skbuff[i] = skb;
 998                 if (skb == NULL)
 999                         break;
1000                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1001                                 DMA_FROM_DEVICE);
1002                 sh_eth_set_receive_align(skb);
1003
1004                 /* RX descriptor */
1005                 rxdesc = &mdp->rx_ring[i];
1006                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1007                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1008
1009                 /* The size of the buffer is 16 byte boundary. */
1010                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1011                 /* Rx descriptor address set */
1012                 if (i == 0) {
1013                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1014                         if (sh_eth_is_gether(mdp))
1015                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1016                 }
1017         }
1018
1019         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1020
1021         /* Mark the last entry as wrapping the ring. */
1022         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1023
1024         memset(mdp->tx_ring, 0, tx_ringsize);
1025
1026         /* build Tx ring buffer */
1027         for (i = 0; i < mdp->num_tx_ring; i++) {
1028                 mdp->tx_skbuff[i] = NULL;
1029                 txdesc = &mdp->tx_ring[i];
1030                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1031                 txdesc->buffer_length = 0;
1032                 if (i == 0) {
1033                         /* Tx descriptor address set */
1034                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1035                         if (sh_eth_is_gether(mdp))
1036                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1037                 }
1038         }
1039
1040         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1041 }
1042
1043 /* Get skb and descriptor buffer */
1044 static int sh_eth_ring_init(struct net_device *ndev)
1045 {
1046         struct sh_eth_private *mdp = netdev_priv(ndev);
1047         int rx_ringsize, tx_ringsize, ret = 0;
1048
1049         /*
1050          * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1051          * card needs room to do 8 byte alignment, +2 so we can reserve
1052          * the first 2 bytes, and +16 gets room for the status word from the
1053          * card.
1054          */
1055         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1056                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1057         if (mdp->cd->rpadir)
1058                 mdp->rx_buf_sz += NET_IP_ALIGN;
1059
1060         /* Allocate RX and TX skb rings */
1061         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1062                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1063         if (!mdp->rx_skbuff) {
1064                 ret = -ENOMEM;
1065                 return ret;
1066         }
1067
1068         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1069                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1070         if (!mdp->tx_skbuff) {
1071                 ret = -ENOMEM;
1072                 goto skb_ring_free;
1073         }
1074
1075         /* Allocate all Rx descriptors. */
1076         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1077         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1078                                           GFP_KERNEL);
1079         if (!mdp->rx_ring) {
1080                 ret = -ENOMEM;
1081                 goto desc_ring_free;
1082         }
1083
1084         mdp->dirty_rx = 0;
1085
1086         /* Allocate all Tx descriptors. */
1087         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1088         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1089                                           GFP_KERNEL);
1090         if (!mdp->tx_ring) {
1091                 ret = -ENOMEM;
1092                 goto desc_ring_free;
1093         }
1094         return ret;
1095
1096 desc_ring_free:
1097         /* free DMA buffer */
1098         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1099
1100 skb_ring_free:
1101         /* Free Rx and Tx skb ring buffer */
1102         sh_eth_ring_free(ndev);
1103         mdp->tx_ring = NULL;
1104         mdp->rx_ring = NULL;
1105
1106         return ret;
1107 }
1108
1109 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1110 {
1111         int ringsize;
1112
1113         if (mdp->rx_ring) {
1114                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1115                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1116                                   mdp->rx_desc_dma);
1117                 mdp->rx_ring = NULL;
1118         }
1119
1120         if (mdp->tx_ring) {
1121                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1122                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1123                                   mdp->tx_desc_dma);
1124                 mdp->tx_ring = NULL;
1125         }
1126 }
1127
1128 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1129 {
1130         int ret = 0;
1131         struct sh_eth_private *mdp = netdev_priv(ndev);
1132         u32 val;
1133
1134         /* Soft Reset */
1135         ret = sh_eth_reset(ndev);
1136         if (ret)
1137                 goto out;
1138
1139         /* Descriptor format */
1140         sh_eth_ring_format(ndev);
1141         if (mdp->cd->rpadir)
1142                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1143
1144         /* all sh_eth int mask */
1145         sh_eth_write(ndev, 0, EESIPR);
1146
1147 #if defined(__LITTLE_ENDIAN)
1148         if (mdp->cd->hw_swap)
1149                 sh_eth_write(ndev, EDMR_EL, EDMR);
1150         else
1151 #endif
1152                 sh_eth_write(ndev, 0, EDMR);
1153
1154         /* FIFO size set */
1155         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1156         sh_eth_write(ndev, 0, TFTR);
1157
1158         /* Frame recv control */
1159         sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1160
1161         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1162
1163         if (mdp->cd->bculr)
1164                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1165
1166         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1167
1168         if (!mdp->cd->no_trimd)
1169                 sh_eth_write(ndev, 0, TRIMD);
1170
1171         /* Recv frame limit set register */
1172         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1173                      RFLR);
1174
1175         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1176         if (start)
1177                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1178
1179         /* PAUSE Prohibition */
1180         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1181                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1182
1183         sh_eth_write(ndev, val, ECMR);
1184
1185         if (mdp->cd->set_rate)
1186                 mdp->cd->set_rate(ndev);
1187
1188         /* E-MAC Status Register clear */
1189         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1190
1191         /* E-MAC Interrupt Enable register */
1192         if (start)
1193                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1194
1195         /* Set MAC address */
1196         update_mac_address(ndev);
1197
1198         /* mask reset */
1199         if (mdp->cd->apr)
1200                 sh_eth_write(ndev, APR_AP, APR);
1201         if (mdp->cd->mpr)
1202                 sh_eth_write(ndev, MPR_MP, MPR);
1203         if (mdp->cd->tpauser)
1204                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1205
1206         if (start) {
1207                 /* Setting the Rx mode will start the Rx process. */
1208                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1209
1210                 netif_start_queue(ndev);
1211         }
1212
1213 out:
1214         return ret;
1215 }
1216
1217 /* free Tx skb function */
1218 static int sh_eth_txfree(struct net_device *ndev)
1219 {
1220         struct sh_eth_private *mdp = netdev_priv(ndev);
1221         struct sh_eth_txdesc *txdesc;
1222         int freeNum = 0;
1223         int entry = 0;
1224
1225         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1226                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1227                 txdesc = &mdp->tx_ring[entry];
1228                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1229                         break;
1230                 /* Free the original skb. */
1231                 if (mdp->tx_skbuff[entry]) {
1232                         dma_unmap_single(&ndev->dev, txdesc->addr,
1233                                          txdesc->buffer_length, DMA_TO_DEVICE);
1234                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1235                         mdp->tx_skbuff[entry] = NULL;
1236                         freeNum++;
1237                 }
1238                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1239                 if (entry >= mdp->num_tx_ring - 1)
1240                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1241
1242                 ndev->stats.tx_packets++;
1243                 ndev->stats.tx_bytes += txdesc->buffer_length;
1244         }
1245         return freeNum;
1246 }
1247
1248 /* Packet receive function */
1249 static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
1250 {
1251         struct sh_eth_private *mdp = netdev_priv(ndev);
1252         struct sh_eth_rxdesc *rxdesc;
1253
1254         int entry = mdp->cur_rx % mdp->num_rx_ring;
1255         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1256         struct sk_buff *skb;
1257         u16 pkt_len = 0;
1258         u32 desc_status;
1259
1260         rxdesc = &mdp->rx_ring[entry];
1261         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1262                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1263                 pkt_len = rxdesc->frame_length;
1264
1265 #if defined(CONFIG_ARCH_R8A7740)
1266                 desc_status >>= 16;
1267 #endif
1268
1269                 if (--boguscnt < 0)
1270                         break;
1271
1272                 if (!(desc_status & RDFEND))
1273                         ndev->stats.rx_length_errors++;
1274
1275                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1276                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1277                         ndev->stats.rx_errors++;
1278                         if (desc_status & RD_RFS1)
1279                                 ndev->stats.rx_crc_errors++;
1280                         if (desc_status & RD_RFS2)
1281                                 ndev->stats.rx_frame_errors++;
1282                         if (desc_status & RD_RFS3)
1283                                 ndev->stats.rx_length_errors++;
1284                         if (desc_status & RD_RFS4)
1285                                 ndev->stats.rx_length_errors++;
1286                         if (desc_status & RD_RFS6)
1287                                 ndev->stats.rx_missed_errors++;
1288                         if (desc_status & RD_RFS10)
1289                                 ndev->stats.rx_over_errors++;
1290                 } else {
1291                         if (!mdp->cd->hw_swap)
1292                                 sh_eth_soft_swap(
1293                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1294                                         pkt_len + 2);
1295                         skb = mdp->rx_skbuff[entry];
1296                         mdp->rx_skbuff[entry] = NULL;
1297                         if (mdp->cd->rpadir)
1298                                 skb_reserve(skb, NET_IP_ALIGN);
1299                         skb_put(skb, pkt_len);
1300                         skb->protocol = eth_type_trans(skb, ndev);
1301                         netif_rx(skb);
1302                         ndev->stats.rx_packets++;
1303                         ndev->stats.rx_bytes += pkt_len;
1304                 }
1305                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1306                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1307                 rxdesc = &mdp->rx_ring[entry];
1308         }
1309
1310         /* Refill the Rx ring buffers. */
1311         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1312                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1313                 rxdesc = &mdp->rx_ring[entry];
1314                 /* The size of the buffer is 16 byte boundary. */
1315                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1316
1317                 if (mdp->rx_skbuff[entry] == NULL) {
1318                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1319                         mdp->rx_skbuff[entry] = skb;
1320                         if (skb == NULL)
1321                                 break;  /* Better luck next round. */
1322                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1323                                         DMA_FROM_DEVICE);
1324                         sh_eth_set_receive_align(skb);
1325
1326                         skb_checksum_none_assert(skb);
1327                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1328                 }
1329                 if (entry >= mdp->num_rx_ring - 1)
1330                         rxdesc->status |=
1331                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1332                 else
1333                         rxdesc->status |=
1334                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1335         }
1336
1337         /* Restart Rx engine if stopped. */
1338         /* If we don't need to check status, don't. -KDU */
1339         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1340                 /* fix the values for the next receiving if RDE is set */
1341                 if (intr_status & EESR_RDE)
1342                         mdp->cur_rx = mdp->dirty_rx =
1343                                 (sh_eth_read(ndev, RDFAR) -
1344                                  sh_eth_read(ndev, RDLAR)) >> 4;
1345                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1346         }
1347
1348         return 0;
1349 }
1350
1351 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1352 {
1353         /* disable tx and rx */
1354         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1355                 ~(ECMR_RE | ECMR_TE), ECMR);
1356 }
1357
1358 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1359 {
1360         /* enable tx and rx */
1361         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1362                 (ECMR_RE | ECMR_TE), ECMR);
1363 }
1364
1365 /* error control function */
1366 static void sh_eth_error(struct net_device *ndev, int intr_status)
1367 {
1368         struct sh_eth_private *mdp = netdev_priv(ndev);
1369         u32 felic_stat;
1370         u32 link_stat;
1371         u32 mask;
1372
1373         if (intr_status & EESR_ECI) {
1374                 felic_stat = sh_eth_read(ndev, ECSR);
1375                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1376                 if (felic_stat & ECSR_ICD)
1377                         ndev->stats.tx_carrier_errors++;
1378                 if (felic_stat & ECSR_LCHNG) {
1379                         /* Link Changed */
1380                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1381                                 goto ignore_link;
1382                         } else {
1383                                 link_stat = (sh_eth_read(ndev, PSR));
1384                                 if (mdp->ether_link_active_low)
1385                                         link_stat = ~link_stat;
1386                         }
1387                         if (!(link_stat & PHY_ST_LINK))
1388                                 sh_eth_rcv_snd_disable(ndev);
1389                         else {
1390                                 /* Link Up */
1391                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1392                                           ~DMAC_M_ECI, EESIPR);
1393                                 /*clear int */
1394                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1395                                           ECSR);
1396                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1397                                           DMAC_M_ECI, EESIPR);
1398                                 /* enable tx and rx */
1399                                 sh_eth_rcv_snd_enable(ndev);
1400                         }
1401                 }
1402         }
1403
1404 ignore_link:
1405         if (intr_status & EESR_TWB) {
1406                 /* Write buck end. unused write back interrupt */
1407                 if (intr_status & EESR_TABT)    /* Transmit Abort int */
1408                         ndev->stats.tx_aborted_errors++;
1409                         if (netif_msg_tx_err(mdp))
1410                                 dev_err(&ndev->dev, "Transmit Abort\n");
1411         }
1412
1413         if (intr_status & EESR_RABT) {
1414                 /* Receive Abort int */
1415                 if (intr_status & EESR_RFRMER) {
1416                         /* Receive Frame Overflow int */
1417                         ndev->stats.rx_frame_errors++;
1418                         if (netif_msg_rx_err(mdp))
1419                                 dev_err(&ndev->dev, "Receive Abort\n");
1420                 }
1421         }
1422
1423         if (intr_status & EESR_TDE) {
1424                 /* Transmit Descriptor Empty int */
1425                 ndev->stats.tx_fifo_errors++;
1426                 if (netif_msg_tx_err(mdp))
1427                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1428         }
1429
1430         if (intr_status & EESR_TFE) {
1431                 /* FIFO under flow */
1432                 ndev->stats.tx_fifo_errors++;
1433                 if (netif_msg_tx_err(mdp))
1434                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1435         }
1436
1437         if (intr_status & EESR_RDE) {
1438                 /* Receive Descriptor Empty int */
1439                 ndev->stats.rx_over_errors++;
1440
1441                 if (netif_msg_rx_err(mdp))
1442                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1443         }
1444
1445         if (intr_status & EESR_RFE) {
1446                 /* Receive FIFO Overflow int */
1447                 ndev->stats.rx_fifo_errors++;
1448                 if (netif_msg_rx_err(mdp))
1449                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1450         }
1451
1452         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1453                 /* Address Error */
1454                 ndev->stats.tx_fifo_errors++;
1455                 if (netif_msg_tx_err(mdp))
1456                         dev_err(&ndev->dev, "Address Error\n");
1457         }
1458
1459         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1460         if (mdp->cd->no_ade)
1461                 mask &= ~EESR_ADE;
1462         if (intr_status & mask) {
1463                 /* Tx error */
1464                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1465                 /* dmesg */
1466                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1467                                 intr_status, mdp->cur_tx);
1468                 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1469                                 mdp->dirty_tx, (u32) ndev->state, edtrr);
1470                 /* dirty buffer free */
1471                 sh_eth_txfree(ndev);
1472
1473                 /* SH7712 BUG */
1474                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1475                         /* tx dma start */
1476                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1477                 }
1478                 /* wakeup */
1479                 netif_wake_queue(ndev);
1480         }
1481 }
1482
1483 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1484 {
1485         struct net_device *ndev = netdev;
1486         struct sh_eth_private *mdp = netdev_priv(ndev);
1487         struct sh_eth_cpu_data *cd = mdp->cd;
1488         irqreturn_t ret = IRQ_NONE;
1489         unsigned long intr_status;
1490
1491         spin_lock(&mdp->lock);
1492
1493         /* Get interrupt status */
1494         intr_status = sh_eth_read(ndev, EESR);
1495         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1496          * enabled since it's the one that  comes thru regardless of the mask,
1497          * and we need to fully handle it in sh_eth_error() in order to quench
1498          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1499          */
1500         intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
1501         /* Clear interrupt */
1502         if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1503                         EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1504                         cd->tx_check | cd->eesr_err_check)) {
1505                 sh_eth_write(ndev, intr_status, EESR);
1506                 ret = IRQ_HANDLED;
1507         } else
1508                 goto other_irq;
1509
1510         if (intr_status & (EESR_FRC | /* Frame recv*/
1511                         EESR_RMAF | /* Multi cast address recv*/
1512                         EESR_RRF  | /* Bit frame recv */
1513                         EESR_RTLF | /* Long frame recv*/
1514                         EESR_RTSF | /* short frame recv */
1515                         EESR_PRE  | /* PHY-LSI recv error */
1516                         EESR_CERF)){ /* recv frame CRC error */
1517                 sh_eth_rx(ndev, intr_status);
1518         }
1519
1520         /* Tx Check */
1521         if (intr_status & cd->tx_check) {
1522                 sh_eth_txfree(ndev);
1523                 netif_wake_queue(ndev);
1524         }
1525
1526         if (intr_status & cd->eesr_err_check)
1527                 sh_eth_error(ndev, intr_status);
1528
1529 other_irq:
1530         spin_unlock(&mdp->lock);
1531
1532         return ret;
1533 }
1534
1535 /* PHY state control function */
1536 static void sh_eth_adjust_link(struct net_device *ndev)
1537 {
1538         struct sh_eth_private *mdp = netdev_priv(ndev);
1539         struct phy_device *phydev = mdp->phydev;
1540         int new_state = 0;
1541
1542         if (phydev->link) {
1543                 if (phydev->duplex != mdp->duplex) {
1544                         new_state = 1;
1545                         mdp->duplex = phydev->duplex;
1546                         if (mdp->cd->set_duplex)
1547                                 mdp->cd->set_duplex(ndev);
1548                 }
1549
1550                 if (phydev->speed != mdp->speed) {
1551                         new_state = 1;
1552                         mdp->speed = phydev->speed;
1553                         if (mdp->cd->set_rate)
1554                                 mdp->cd->set_rate(ndev);
1555                 }
1556                 if (!mdp->link) {
1557                         sh_eth_write(ndev,
1558                                 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1559                         new_state = 1;
1560                         mdp->link = phydev->link;
1561                         if (mdp->cd->no_psr || mdp->no_ether_link)
1562                                 sh_eth_rcv_snd_enable(ndev);
1563                 }
1564         } else if (mdp->link) {
1565                 new_state = 1;
1566                 mdp->link = 0;
1567                 mdp->speed = 0;
1568                 mdp->duplex = -1;
1569                 if (mdp->cd->no_psr || mdp->no_ether_link)
1570                         sh_eth_rcv_snd_disable(ndev);
1571         }
1572
1573         if (new_state && netif_msg_link(mdp))
1574                 phy_print_status(phydev);
1575 }
1576
1577 /* PHY init function */
1578 static int sh_eth_phy_init(struct net_device *ndev)
1579 {
1580         struct sh_eth_private *mdp = netdev_priv(ndev);
1581         char phy_id[MII_BUS_ID_SIZE + 3];
1582         struct phy_device *phydev = NULL;
1583
1584         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1585                 mdp->mii_bus->id , mdp->phy_id);
1586
1587         mdp->link = 0;
1588         mdp->speed = 0;
1589         mdp->duplex = -1;
1590
1591         /* Try connect to PHY */
1592         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1593                              mdp->phy_interface);
1594         if (IS_ERR(phydev)) {
1595                 dev_err(&ndev->dev, "phy_connect failed\n");
1596                 return PTR_ERR(phydev);
1597         }
1598
1599         dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1600                 phydev->addr, phydev->drv->name);
1601
1602         mdp->phydev = phydev;
1603
1604         return 0;
1605 }
1606
1607 /* PHY control start function */
1608 static int sh_eth_phy_start(struct net_device *ndev)
1609 {
1610         struct sh_eth_private *mdp = netdev_priv(ndev);
1611         int ret;
1612
1613         ret = sh_eth_phy_init(ndev);
1614         if (ret)
1615                 return ret;
1616
1617         /* reset phy - this also wakes it from PDOWN */
1618         phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1619         phy_start(mdp->phydev);
1620
1621         return 0;
1622 }
1623
1624 static int sh_eth_get_settings(struct net_device *ndev,
1625                         struct ethtool_cmd *ecmd)
1626 {
1627         struct sh_eth_private *mdp = netdev_priv(ndev);
1628         unsigned long flags;
1629         int ret;
1630
1631         spin_lock_irqsave(&mdp->lock, flags);
1632         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1633         spin_unlock_irqrestore(&mdp->lock, flags);
1634
1635         return ret;
1636 }
1637
1638 static int sh_eth_set_settings(struct net_device *ndev,
1639                 struct ethtool_cmd *ecmd)
1640 {
1641         struct sh_eth_private *mdp = netdev_priv(ndev);
1642         unsigned long flags;
1643         int ret;
1644
1645         spin_lock_irqsave(&mdp->lock, flags);
1646
1647         /* disable tx and rx */
1648         sh_eth_rcv_snd_disable(ndev);
1649
1650         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1651         if (ret)
1652                 goto error_exit;
1653
1654         if (ecmd->duplex == DUPLEX_FULL)
1655                 mdp->duplex = 1;
1656         else
1657                 mdp->duplex = 0;
1658
1659         if (mdp->cd->set_duplex)
1660                 mdp->cd->set_duplex(ndev);
1661
1662 error_exit:
1663         mdelay(1);
1664
1665         /* enable tx and rx */
1666         sh_eth_rcv_snd_enable(ndev);
1667
1668         spin_unlock_irqrestore(&mdp->lock, flags);
1669
1670         return ret;
1671 }
1672
1673 static int sh_eth_nway_reset(struct net_device *ndev)
1674 {
1675         struct sh_eth_private *mdp = netdev_priv(ndev);
1676         unsigned long flags;
1677         int ret;
1678
1679         spin_lock_irqsave(&mdp->lock, flags);
1680         ret = phy_start_aneg(mdp->phydev);
1681         spin_unlock_irqrestore(&mdp->lock, flags);
1682
1683         return ret;
1684 }
1685
1686 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1687 {
1688         struct sh_eth_private *mdp = netdev_priv(ndev);
1689         return mdp->msg_enable;
1690 }
1691
1692 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1693 {
1694         struct sh_eth_private *mdp = netdev_priv(ndev);
1695         mdp->msg_enable = value;
1696 }
1697
1698 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1699         "rx_current", "tx_current",
1700         "rx_dirty", "tx_dirty",
1701 };
1702 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1703
1704 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1705 {
1706         switch (sset) {
1707         case ETH_SS_STATS:
1708                 return SH_ETH_STATS_LEN;
1709         default:
1710                 return -EOPNOTSUPP;
1711         }
1712 }
1713
1714 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1715                         struct ethtool_stats *stats, u64 *data)
1716 {
1717         struct sh_eth_private *mdp = netdev_priv(ndev);
1718         int i = 0;
1719
1720         /* device-specific stats */
1721         data[i++] = mdp->cur_rx;
1722         data[i++] = mdp->cur_tx;
1723         data[i++] = mdp->dirty_rx;
1724         data[i++] = mdp->dirty_tx;
1725 }
1726
1727 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1728 {
1729         switch (stringset) {
1730         case ETH_SS_STATS:
1731                 memcpy(data, *sh_eth_gstrings_stats,
1732                                         sizeof(sh_eth_gstrings_stats));
1733                 break;
1734         }
1735 }
1736
1737 static void sh_eth_get_ringparam(struct net_device *ndev,
1738                                  struct ethtool_ringparam *ring)
1739 {
1740         struct sh_eth_private *mdp = netdev_priv(ndev);
1741
1742         ring->rx_max_pending = RX_RING_MAX;
1743         ring->tx_max_pending = TX_RING_MAX;
1744         ring->rx_pending = mdp->num_rx_ring;
1745         ring->tx_pending = mdp->num_tx_ring;
1746 }
1747
1748 static int sh_eth_set_ringparam(struct net_device *ndev,
1749                                 struct ethtool_ringparam *ring)
1750 {
1751         struct sh_eth_private *mdp = netdev_priv(ndev);
1752         int ret;
1753
1754         if (ring->tx_pending > TX_RING_MAX ||
1755             ring->rx_pending > RX_RING_MAX ||
1756             ring->tx_pending < TX_RING_MIN ||
1757             ring->rx_pending < RX_RING_MIN)
1758                 return -EINVAL;
1759         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1760                 return -EINVAL;
1761
1762         if (netif_running(ndev)) {
1763                 netif_tx_disable(ndev);
1764                 /* Disable interrupts by clearing the interrupt mask. */
1765                 sh_eth_write(ndev, 0x0000, EESIPR);
1766                 /* Stop the chip's Tx and Rx processes. */
1767                 sh_eth_write(ndev, 0, EDTRR);
1768                 sh_eth_write(ndev, 0, EDRRR);
1769                 synchronize_irq(ndev->irq);
1770         }
1771
1772         /* Free all the skbuffs in the Rx queue. */
1773         sh_eth_ring_free(ndev);
1774         /* Free DMA buffer */
1775         sh_eth_free_dma_buffer(mdp);
1776
1777         /* Set new parameters */
1778         mdp->num_rx_ring = ring->rx_pending;
1779         mdp->num_tx_ring = ring->tx_pending;
1780
1781         ret = sh_eth_ring_init(ndev);
1782         if (ret < 0) {
1783                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1784                 return ret;
1785         }
1786         ret = sh_eth_dev_init(ndev, false);
1787         if (ret < 0) {
1788                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1789                 return ret;
1790         }
1791
1792         if (netif_running(ndev)) {
1793                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1794                 /* Setting the Rx mode will start the Rx process. */
1795                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1796                 netif_wake_queue(ndev);
1797         }
1798
1799         return 0;
1800 }
1801
1802 static const struct ethtool_ops sh_eth_ethtool_ops = {
1803         .get_settings   = sh_eth_get_settings,
1804         .set_settings   = sh_eth_set_settings,
1805         .nway_reset     = sh_eth_nway_reset,
1806         .get_msglevel   = sh_eth_get_msglevel,
1807         .set_msglevel   = sh_eth_set_msglevel,
1808         .get_link       = ethtool_op_get_link,
1809         .get_strings    = sh_eth_get_strings,
1810         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
1811         .get_sset_count     = sh_eth_get_sset_count,
1812         .get_ringparam  = sh_eth_get_ringparam,
1813         .set_ringparam  = sh_eth_set_ringparam,
1814 };
1815
1816 /* network device open function */
1817 static int sh_eth_open(struct net_device *ndev)
1818 {
1819         int ret = 0;
1820         struct sh_eth_private *mdp = netdev_priv(ndev);
1821
1822         pm_runtime_get_sync(&mdp->pdev->dev);
1823
1824         ret = request_irq(ndev->irq, sh_eth_interrupt,
1825                           mdp->cd->irq_flags, ndev->name, ndev);
1826         if (ret) {
1827                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1828                 return ret;
1829         }
1830
1831         /* Descriptor set */
1832         ret = sh_eth_ring_init(ndev);
1833         if (ret)
1834                 goto out_free_irq;
1835
1836         /* device init */
1837         ret = sh_eth_dev_init(ndev, true);
1838         if (ret)
1839                 goto out_free_irq;
1840
1841         /* PHY control start*/
1842         ret = sh_eth_phy_start(ndev);
1843         if (ret)
1844                 goto out_free_irq;
1845
1846         return ret;
1847
1848 out_free_irq:
1849         free_irq(ndev->irq, ndev);
1850         pm_runtime_put_sync(&mdp->pdev->dev);
1851         return ret;
1852 }
1853
1854 /* Timeout function */
1855 static void sh_eth_tx_timeout(struct net_device *ndev)
1856 {
1857         struct sh_eth_private *mdp = netdev_priv(ndev);
1858         struct sh_eth_rxdesc *rxdesc;
1859         int i;
1860
1861         netif_stop_queue(ndev);
1862
1863         if (netif_msg_timer(mdp))
1864                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1865                " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1866
1867         /* tx_errors count up */
1868         ndev->stats.tx_errors++;
1869
1870         /* Free all the skbuffs in the Rx queue. */
1871         for (i = 0; i < mdp->num_rx_ring; i++) {
1872                 rxdesc = &mdp->rx_ring[i];
1873                 rxdesc->status = 0;
1874                 rxdesc->addr = 0xBADF00D0;
1875                 if (mdp->rx_skbuff[i])
1876                         dev_kfree_skb(mdp->rx_skbuff[i]);
1877                 mdp->rx_skbuff[i] = NULL;
1878         }
1879         for (i = 0; i < mdp->num_tx_ring; i++) {
1880                 if (mdp->tx_skbuff[i])
1881                         dev_kfree_skb(mdp->tx_skbuff[i]);
1882                 mdp->tx_skbuff[i] = NULL;
1883         }
1884
1885         /* device init */
1886         sh_eth_dev_init(ndev, true);
1887 }
1888
1889 /* Packet transmit function */
1890 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1891 {
1892         struct sh_eth_private *mdp = netdev_priv(ndev);
1893         struct sh_eth_txdesc *txdesc;
1894         u32 entry;
1895         unsigned long flags;
1896
1897         spin_lock_irqsave(&mdp->lock, flags);
1898         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1899                 if (!sh_eth_txfree(ndev)) {
1900                         if (netif_msg_tx_queued(mdp))
1901                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1902                         netif_stop_queue(ndev);
1903                         spin_unlock_irqrestore(&mdp->lock, flags);
1904                         return NETDEV_TX_BUSY;
1905                 }
1906         }
1907         spin_unlock_irqrestore(&mdp->lock, flags);
1908
1909         entry = mdp->cur_tx % mdp->num_tx_ring;
1910         mdp->tx_skbuff[entry] = skb;
1911         txdesc = &mdp->tx_ring[entry];
1912         /* soft swap. */
1913         if (!mdp->cd->hw_swap)
1914                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1915                                  skb->len + 2);
1916         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1917                                       DMA_TO_DEVICE);
1918         if (skb->len < ETHERSMALL)
1919                 txdesc->buffer_length = ETHERSMALL;
1920         else
1921                 txdesc->buffer_length = skb->len;
1922
1923         if (entry >= mdp->num_tx_ring - 1)
1924                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1925         else
1926                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1927
1928         mdp->cur_tx++;
1929
1930         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1931                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1932
1933         return NETDEV_TX_OK;
1934 }
1935
1936 /* device close function */
1937 static int sh_eth_close(struct net_device *ndev)
1938 {
1939         struct sh_eth_private *mdp = netdev_priv(ndev);
1940
1941         netif_stop_queue(ndev);
1942
1943         /* Disable interrupts by clearing the interrupt mask. */
1944         sh_eth_write(ndev, 0x0000, EESIPR);
1945
1946         /* Stop the chip's Tx and Rx processes. */
1947         sh_eth_write(ndev, 0, EDTRR);
1948         sh_eth_write(ndev, 0, EDRRR);
1949
1950         /* PHY Disconnect */
1951         if (mdp->phydev) {
1952                 phy_stop(mdp->phydev);
1953                 phy_disconnect(mdp->phydev);
1954         }
1955
1956         free_irq(ndev->irq, ndev);
1957
1958         /* Free all the skbuffs in the Rx queue. */
1959         sh_eth_ring_free(ndev);
1960
1961         /* free DMA buffer */
1962         sh_eth_free_dma_buffer(mdp);
1963
1964         pm_runtime_put_sync(&mdp->pdev->dev);
1965
1966         return 0;
1967 }
1968
1969 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1970 {
1971         struct sh_eth_private *mdp = netdev_priv(ndev);
1972
1973         pm_runtime_get_sync(&mdp->pdev->dev);
1974
1975         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1976         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
1977         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
1978         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
1979         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1980         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
1981         if (sh_eth_is_gether(mdp)) {
1982                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1983                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
1984                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1985                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
1986         } else {
1987                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1988                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
1989         }
1990         pm_runtime_put_sync(&mdp->pdev->dev);
1991
1992         return &ndev->stats;
1993 }
1994
1995 /* ioctl to device function */
1996 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1997                                 int cmd)
1998 {
1999         struct sh_eth_private *mdp = netdev_priv(ndev);
2000         struct phy_device *phydev = mdp->phydev;
2001
2002         if (!netif_running(ndev))
2003                 return -EINVAL;
2004
2005         if (!phydev)
2006                 return -ENODEV;
2007
2008         return phy_mii_ioctl(phydev, rq, cmd);
2009 }
2010
2011 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2012 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2013                                             int entry)
2014 {
2015         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2016 }
2017
2018 static u32 sh_eth_tsu_get_post_mask(int entry)
2019 {
2020         return 0x0f << (28 - ((entry % 8) * 4));
2021 }
2022
2023 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2024 {
2025         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2026 }
2027
2028 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2029                                              int entry)
2030 {
2031         struct sh_eth_private *mdp = netdev_priv(ndev);
2032         u32 tmp;
2033         void *reg_offset;
2034
2035         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2036         tmp = ioread32(reg_offset);
2037         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2038 }
2039
2040 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2041                                               int entry)
2042 {
2043         struct sh_eth_private *mdp = netdev_priv(ndev);
2044         u32 post_mask, ref_mask, tmp;
2045         void *reg_offset;
2046
2047         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2048         post_mask = sh_eth_tsu_get_post_mask(entry);
2049         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2050
2051         tmp = ioread32(reg_offset);
2052         iowrite32(tmp & ~post_mask, reg_offset);
2053
2054         /* If other port enables, the function returns "true" */
2055         return tmp & ref_mask;
2056 }
2057
2058 static int sh_eth_tsu_busy(struct net_device *ndev)
2059 {
2060         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2061         struct sh_eth_private *mdp = netdev_priv(ndev);
2062
2063         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2064                 udelay(10);
2065                 timeout--;
2066                 if (timeout <= 0) {
2067                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2068                         return -ETIMEDOUT;
2069                 }
2070         }
2071
2072         return 0;
2073 }
2074
2075 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2076                                   const u8 *addr)
2077 {
2078         u32 val;
2079
2080         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2081         iowrite32(val, reg);
2082         if (sh_eth_tsu_busy(ndev) < 0)
2083                 return -EBUSY;
2084
2085         val = addr[4] << 8 | addr[5];
2086         iowrite32(val, reg + 4);
2087         if (sh_eth_tsu_busy(ndev) < 0)
2088                 return -EBUSY;
2089
2090         return 0;
2091 }
2092
2093 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2094 {
2095         u32 val;
2096
2097         val = ioread32(reg);
2098         addr[0] = (val >> 24) & 0xff;
2099         addr[1] = (val >> 16) & 0xff;
2100         addr[2] = (val >> 8) & 0xff;
2101         addr[3] = val & 0xff;
2102         val = ioread32(reg + 4);
2103         addr[4] = (val >> 8) & 0xff;
2104         addr[5] = val & 0xff;
2105 }
2106
2107
2108 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2109 {
2110         struct sh_eth_private *mdp = netdev_priv(ndev);
2111         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2112         int i;
2113         u8 c_addr[ETH_ALEN];
2114
2115         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2116                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2117                 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2118                         return i;
2119         }
2120
2121         return -ENOENT;
2122 }
2123
2124 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2125 {
2126         u8 blank[ETH_ALEN];
2127         int entry;
2128
2129         memset(blank, 0, sizeof(blank));
2130         entry = sh_eth_tsu_find_entry(ndev, blank);
2131         return (entry < 0) ? -ENOMEM : entry;
2132 }
2133
2134 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2135                                               int entry)
2136 {
2137         struct sh_eth_private *mdp = netdev_priv(ndev);
2138         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2139         int ret;
2140         u8 blank[ETH_ALEN];
2141
2142         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2143                          ~(1 << (31 - entry)), TSU_TEN);
2144
2145         memset(blank, 0, sizeof(blank));
2146         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2147         if (ret < 0)
2148                 return ret;
2149         return 0;
2150 }
2151
2152 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2153 {
2154         struct sh_eth_private *mdp = netdev_priv(ndev);
2155         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2156         int i, ret;
2157
2158         if (!mdp->cd->tsu)
2159                 return 0;
2160
2161         i = sh_eth_tsu_find_entry(ndev, addr);
2162         if (i < 0) {
2163                 /* No entry found, create one */
2164                 i = sh_eth_tsu_find_empty(ndev);
2165                 if (i < 0)
2166                         return -ENOMEM;
2167                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2168                 if (ret < 0)
2169                         return ret;
2170
2171                 /* Enable the entry */
2172                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2173                                  (1 << (31 - i)), TSU_TEN);
2174         }
2175
2176         /* Entry found or created, enable POST */
2177         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2178
2179         return 0;
2180 }
2181
2182 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2183 {
2184         struct sh_eth_private *mdp = netdev_priv(ndev);
2185         int i, ret;
2186
2187         if (!mdp->cd->tsu)
2188                 return 0;
2189
2190         i = sh_eth_tsu_find_entry(ndev, addr);
2191         if (i) {
2192                 /* Entry found */
2193                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2194                         goto done;
2195
2196                 /* Disable the entry if both ports was disabled */
2197                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2198                 if (ret < 0)
2199                         return ret;
2200         }
2201 done:
2202         return 0;
2203 }
2204
2205 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2206 {
2207         struct sh_eth_private *mdp = netdev_priv(ndev);
2208         int i, ret;
2209
2210         if (unlikely(!mdp->cd->tsu))
2211                 return 0;
2212
2213         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2214                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2215                         continue;
2216
2217                 /* Disable the entry if both ports was disabled */
2218                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2219                 if (ret < 0)
2220                         return ret;
2221         }
2222
2223         return 0;
2224 }
2225
2226 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2227 {
2228         struct sh_eth_private *mdp = netdev_priv(ndev);
2229         u8 addr[ETH_ALEN];
2230         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2231         int i;
2232
2233         if (unlikely(!mdp->cd->tsu))
2234                 return;
2235
2236         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2237                 sh_eth_tsu_read_entry(reg_offset, addr);
2238                 if (is_multicast_ether_addr(addr))
2239                         sh_eth_tsu_del_entry(ndev, addr);
2240         }
2241 }
2242
2243 /* Multicast reception directions set */
2244 static void sh_eth_set_multicast_list(struct net_device *ndev)
2245 {
2246         struct sh_eth_private *mdp = netdev_priv(ndev);
2247         u32 ecmr_bits;
2248         int mcast_all = 0;
2249         unsigned long flags;
2250
2251         spin_lock_irqsave(&mdp->lock, flags);
2252         /*
2253          * Initial condition is MCT = 1, PRM = 0.
2254          * Depending on ndev->flags, set PRM or clear MCT
2255          */
2256         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2257
2258         if (!(ndev->flags & IFF_MULTICAST)) {
2259                 sh_eth_tsu_purge_mcast(ndev);
2260                 mcast_all = 1;
2261         }
2262         if (ndev->flags & IFF_ALLMULTI) {
2263                 sh_eth_tsu_purge_mcast(ndev);
2264                 ecmr_bits &= ~ECMR_MCT;
2265                 mcast_all = 1;
2266         }
2267
2268         if (ndev->flags & IFF_PROMISC) {
2269                 sh_eth_tsu_purge_all(ndev);
2270                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2271         } else if (mdp->cd->tsu) {
2272                 struct netdev_hw_addr *ha;
2273                 netdev_for_each_mc_addr(ha, ndev) {
2274                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2275                                 continue;
2276
2277                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2278                                 if (!mcast_all) {
2279                                         sh_eth_tsu_purge_mcast(ndev);
2280                                         ecmr_bits &= ~ECMR_MCT;
2281                                         mcast_all = 1;
2282                                 }
2283                         }
2284                 }
2285         } else {
2286                 /* Normal, unicast/broadcast-only mode. */
2287                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2288         }
2289
2290         /* update the ethernet mode */
2291         sh_eth_write(ndev, ecmr_bits, ECMR);
2292
2293         spin_unlock_irqrestore(&mdp->lock, flags);
2294 }
2295
2296 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2297 {
2298         if (!mdp->port)
2299                 return TSU_VTAG0;
2300         else
2301                 return TSU_VTAG1;
2302 }
2303
2304 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2305                                   __be16 proto, u16 vid)
2306 {
2307         struct sh_eth_private *mdp = netdev_priv(ndev);
2308         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2309
2310         if (unlikely(!mdp->cd->tsu))
2311                 return -EPERM;
2312
2313         /* No filtering if vid = 0 */
2314         if (!vid)
2315                 return 0;
2316
2317         mdp->vlan_num_ids++;
2318
2319         /*
2320          * The controller has one VLAN tag HW filter. So, if the filter is
2321          * already enabled, the driver disables it and the filte
2322          */
2323         if (mdp->vlan_num_ids > 1) {
2324                 /* disable VLAN filter */
2325                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2326                 return 0;
2327         }
2328
2329         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2330                          vtag_reg_index);
2331
2332         return 0;
2333 }
2334
2335 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2336                                    __be16 proto, u16 vid)
2337 {
2338         struct sh_eth_private *mdp = netdev_priv(ndev);
2339         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2340
2341         if (unlikely(!mdp->cd->tsu))
2342                 return -EPERM;
2343
2344         /* No filtering if vid = 0 */
2345         if (!vid)
2346                 return 0;
2347
2348         mdp->vlan_num_ids--;
2349         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2350
2351         return 0;
2352 }
2353
2354 /* SuperH's TSU register init function */
2355 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2356 {
2357         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2358         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2359         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2360         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2361         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2362         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2363         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2364         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2365         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2366         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2367         if (sh_eth_is_gether(mdp)) {
2368                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2369                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2370         } else {
2371                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2372                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2373         }
2374         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2375         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2376         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2377         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2378         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2379         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2380         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2381 }
2382
2383 /* MDIO bus release function */
2384 static int sh_mdio_release(struct net_device *ndev)
2385 {
2386         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2387
2388         /* unregister mdio bus */
2389         mdiobus_unregister(bus);
2390
2391         /* remove mdio bus info from net_device */
2392         dev_set_drvdata(&ndev->dev, NULL);
2393
2394         /* free bitbang info */
2395         free_mdio_bitbang(bus);
2396
2397         return 0;
2398 }
2399
2400 /* MDIO bus init function */
2401 static int sh_mdio_init(struct net_device *ndev, int id,
2402                         struct sh_eth_plat_data *pd)
2403 {
2404         int ret, i;
2405         struct bb_info *bitbang;
2406         struct sh_eth_private *mdp = netdev_priv(ndev);
2407
2408         /* create bit control struct for PHY */
2409         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2410                                GFP_KERNEL);
2411         if (!bitbang) {
2412                 ret = -ENOMEM;
2413                 goto out;
2414         }
2415
2416         /* bitbang init */
2417         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2418         bitbang->set_gate = pd->set_mdio_gate;
2419         bitbang->mdi_msk = PIR_MDI;
2420         bitbang->mdo_msk = PIR_MDO;
2421         bitbang->mmd_msk = PIR_MMD;
2422         bitbang->mdc_msk = PIR_MDC;
2423         bitbang->ctrl.ops = &bb_ops;
2424
2425         /* MII controller setting */
2426         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2427         if (!mdp->mii_bus) {
2428                 ret = -ENOMEM;
2429                 goto out;
2430         }
2431
2432         /* Hook up MII support for ethtool */
2433         mdp->mii_bus->name = "sh_mii";
2434         mdp->mii_bus->parent = &ndev->dev;
2435         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2436                 mdp->pdev->name, id);
2437
2438         /* PHY IRQ */
2439         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2440                                          sizeof(int) * PHY_MAX_ADDR,
2441                                          GFP_KERNEL);
2442         if (!mdp->mii_bus->irq) {
2443                 ret = -ENOMEM;
2444                 goto out_free_bus;
2445         }
2446
2447         for (i = 0; i < PHY_MAX_ADDR; i++)
2448                 mdp->mii_bus->irq[i] = PHY_POLL;
2449
2450         /* register mdio bus */
2451         ret = mdiobus_register(mdp->mii_bus);
2452         if (ret)
2453                 goto out_free_bus;
2454
2455         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2456
2457         return 0;
2458
2459 out_free_bus:
2460         free_mdio_bitbang(mdp->mii_bus);
2461
2462 out:
2463         return ret;
2464 }
2465
2466 static const u16 *sh_eth_get_register_offset(int register_type)
2467 {
2468         const u16 *reg_offset = NULL;
2469
2470         switch (register_type) {
2471         case SH_ETH_REG_GIGABIT:
2472                 reg_offset = sh_eth_offset_gigabit;
2473                 break;
2474         case SH_ETH_REG_FAST_RCAR:
2475                 reg_offset = sh_eth_offset_fast_rcar;
2476                 break;
2477         case SH_ETH_REG_FAST_SH4:
2478                 reg_offset = sh_eth_offset_fast_sh4;
2479                 break;
2480         case SH_ETH_REG_FAST_SH3_SH2:
2481                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2482                 break;
2483         default:
2484                 pr_err("Unknown register type (%d)\n", register_type);
2485                 break;
2486         }
2487
2488         return reg_offset;
2489 }
2490
2491 static struct net_device_ops sh_eth_netdev_ops = {
2492         .ndo_open               = sh_eth_open,
2493         .ndo_stop               = sh_eth_close,
2494         .ndo_start_xmit         = sh_eth_start_xmit,
2495         .ndo_get_stats          = sh_eth_get_stats,
2496         .ndo_tx_timeout         = sh_eth_tx_timeout,
2497         .ndo_do_ioctl           = sh_eth_do_ioctl,
2498         .ndo_validate_addr      = eth_validate_addr,
2499         .ndo_set_mac_address    = eth_mac_addr,
2500         .ndo_change_mtu         = eth_change_mtu,
2501 };
2502
2503 static int sh_eth_drv_probe(struct platform_device *pdev)
2504 {
2505         int ret, devno = 0;
2506         struct resource *res;
2507         struct net_device *ndev = NULL;
2508         struct sh_eth_private *mdp = NULL;
2509         struct sh_eth_plat_data *pd = pdev->dev.platform_data;
2510         const struct platform_device_id *id = platform_get_device_id(pdev);
2511
2512         /* get base addr */
2513         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2514         if (unlikely(res == NULL)) {
2515                 dev_err(&pdev->dev, "invalid resource\n");
2516                 ret = -EINVAL;
2517                 goto out;
2518         }
2519
2520         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2521         if (!ndev) {
2522                 ret = -ENOMEM;
2523                 goto out;
2524         }
2525
2526         /* The sh Ether-specific entries in the device structure. */
2527         ndev->base_addr = res->start;
2528         devno = pdev->id;
2529         if (devno < 0)
2530                 devno = 0;
2531
2532         ndev->dma = -1;
2533         ret = platform_get_irq(pdev, 0);
2534         if (ret < 0) {
2535                 ret = -ENODEV;
2536                 goto out_release;
2537         }
2538         ndev->irq = ret;
2539
2540         SET_NETDEV_DEV(ndev, &pdev->dev);
2541
2542         /* Fill in the fields of the device structure with ethernet values. */
2543         ether_setup(ndev);
2544
2545         mdp = netdev_priv(ndev);
2546         mdp->num_tx_ring = TX_RING_SIZE;
2547         mdp->num_rx_ring = RX_RING_SIZE;
2548         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2549         if (IS_ERR(mdp->addr)) {
2550                 ret = PTR_ERR(mdp->addr);
2551                 goto out_release;
2552         }
2553
2554         spin_lock_init(&mdp->lock);
2555         mdp->pdev = pdev;
2556         pm_runtime_enable(&pdev->dev);
2557         pm_runtime_resume(&pdev->dev);
2558
2559         /* get PHY ID */
2560         mdp->phy_id = pd->phy;
2561         mdp->phy_interface = pd->phy_interface;
2562         /* EDMAC endian */
2563         mdp->edmac_endian = pd->edmac_endian;
2564         mdp->no_ether_link = pd->no_ether_link;
2565         mdp->ether_link_active_low = pd->ether_link_active_low;
2566         mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2567
2568         /* set cpu data */
2569         mdp->cd = &sh_eth_my_cpu_data;
2570         if (id->driver_data)
2571                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2572         sh_eth_set_default_cpu_data(mdp->cd);
2573
2574         /* set function */
2575         if (mdp->cd->tsu) {
2576                 sh_eth_netdev_ops.ndo_set_rx_mode = sh_eth_set_multicast_list;
2577                 sh_eth_netdev_ops.ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid;
2578                 sh_eth_netdev_ops.ndo_vlan_rx_kill_vid =
2579                         sh_eth_vlan_rx_kill_vid;
2580         }
2581
2582         ndev->netdev_ops = &sh_eth_netdev_ops;
2583         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2584         ndev->watchdog_timeo = TX_TIMEOUT;
2585
2586         /* debug message level */
2587         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2588
2589         /* read and set MAC address */
2590         read_mac_address(ndev, pd->mac_addr);
2591         if (!is_valid_ether_addr(ndev->dev_addr)) {
2592                 dev_warn(&pdev->dev,
2593                          "no valid MAC address supplied, using a random one.\n");
2594                 eth_hw_addr_random(ndev);
2595         }
2596
2597         /* ioremap the TSU registers */
2598         if (mdp->cd->tsu) {
2599                 struct resource *rtsu;
2600                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2601                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2602                 if (IS_ERR(mdp->tsu_addr)) {
2603                         ret = PTR_ERR(mdp->tsu_addr);
2604                         goto out_release;
2605                 }
2606                 mdp->port = devno % 2;
2607                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2608         }
2609
2610         /* initialize first or needed device */
2611         if (!devno || pd->needs_init) {
2612                 if (mdp->cd->chip_reset)
2613                         mdp->cd->chip_reset(ndev);
2614
2615                 if (mdp->cd->tsu) {
2616                         /* TSU init (Init only)*/
2617                         sh_eth_tsu_init(mdp);
2618                 }
2619         }
2620
2621         /* network device register */
2622         ret = register_netdev(ndev);
2623         if (ret)
2624                 goto out_release;
2625
2626         /* mdio bus init */
2627         ret = sh_mdio_init(ndev, pdev->id, pd);
2628         if (ret)
2629                 goto out_unregister;
2630
2631         /* print device information */
2632         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2633                (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2634
2635         platform_set_drvdata(pdev, ndev);
2636
2637         return ret;
2638
2639 out_unregister:
2640         unregister_netdev(ndev);
2641
2642 out_release:
2643         /* net_dev free */
2644         if (ndev)
2645                 free_netdev(ndev);
2646
2647 out:
2648         return ret;
2649 }
2650
2651 static int sh_eth_drv_remove(struct platform_device *pdev)
2652 {
2653         struct net_device *ndev = platform_get_drvdata(pdev);
2654
2655         sh_mdio_release(ndev);
2656         unregister_netdev(ndev);
2657         pm_runtime_disable(&pdev->dev);
2658         free_netdev(ndev);
2659
2660         return 0;
2661 }
2662
2663 #ifdef CONFIG_PM
2664 static int sh_eth_runtime_nop(struct device *dev)
2665 {
2666         /*
2667          * Runtime PM callback shared between ->runtime_suspend()
2668          * and ->runtime_resume(). Simply returns success.
2669          *
2670          * This driver re-initializes all registers after
2671          * pm_runtime_get_sync() anyway so there is no need
2672          * to save and restore registers here.
2673          */
2674         return 0;
2675 }
2676
2677 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2678         .runtime_suspend = sh_eth_runtime_nop,
2679         .runtime_resume = sh_eth_runtime_nop,
2680 };
2681 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2682 #else
2683 #define SH_ETH_PM_OPS NULL
2684 #endif
2685
2686 static struct platform_device_id sh_eth_id_table[] = {
2687         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2688         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2689         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2690         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2691         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2692         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2693         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2694         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2695         { CARDNAME },
2696         { }
2697 };
2698 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2699
2700 static struct platform_driver sh_eth_driver = {
2701         .probe = sh_eth_drv_probe,
2702         .remove = sh_eth_drv_remove,
2703         .id_table = sh_eth_id_table,
2704         .driver = {
2705                    .name = CARDNAME,
2706                    .pm = SH_ETH_PM_OPS,
2707         },
2708 };
2709
2710 module_platform_driver(sh_eth_driver);
2711
2712 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2713 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2714 MODULE_LICENSE("GPL v2");