drivers/net/ethernet/renesas/sh_eth.c

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2013 Renesas Solutions Corp.
   6  *  Copyright (C) 2013 Cogent Embedded, Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms and conditions of the GNU General Public License,
  10  *  version 2, as published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  *  more details.
  16  *  You should have received a copy of the GNU General Public License along with
  17  *  this program; if not, write to the Free Software Foundation, Inc.,
  18  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  *  The full GNU General Public License is included in this distribution in
  21  *  the file called "COPYING".
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/mdio-bitbang.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/phy.h>
  36 #include <linux/cache.h>
  37 #include <linux/io.h>
  38 #include <linux/pm_runtime.h>
  39 #include <linux/slab.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/clk.h>
  43 #include <linux/sh_eth.h>
  44
  45 #include "sh_eth.h"
  46
  47 #define SH_ETH_DEF_MSG_ENABLE \
  48                 (NETIF_MSG_LINK | \
  49                 NETIF_MSG_TIMER | \
  50                 NETIF_MSG_RX_ERR| \
  51                 NETIF_MSG_TX_ERR)
  52
  53 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  54         [EDSR]          = 0x0000,
  55         [EDMR]          = 0x0400,
  56         [EDTRR]         = 0x0408,
  57         [EDRRR]         = 0x0410,
  58         [EESR]          = 0x0428,
  59         [EESIPR]        = 0x0430,
  60         [TDLAR]         = 0x0010,
  61         [TDFAR]         = 0x0014,
  62         [TDFXR]         = 0x0018,
  63         [TDFFR]         = 0x001c,
  64         [RDLAR]         = 0x0030,
  65         [RDFAR]         = 0x0034,
  66         [RDFXR]         = 0x0038,
  67         [RDFFR]         = 0x003c,
  68         [TRSCER]        = 0x0438,
  69         [RMFCR]         = 0x0440,
  70         [TFTR]          = 0x0448,
  71         [FDR]           = 0x0450,
  72         [RMCR]          = 0x0458,
  73         [RPADIR]        = 0x0460,
  74         [FCFTR]         = 0x0468,
  75         [CSMR]          = 0x04E4,
  76
  77         [ECMR]          = 0x0500,
  78         [ECSR]          = 0x0510,
  79         [ECSIPR]        = 0x0518,
  80         [PIR]           = 0x0520,
  81         [PSR]           = 0x0528,
  82         [PIPR]          = 0x052c,
  83         [RFLR]          = 0x0508,
  84         [APR]           = 0x0554,
  85         [MPR]           = 0x0558,
  86         [PFTCR]         = 0x055c,
  87         [PFRCR]         = 0x0560,
  88         [TPAUSER]       = 0x0564,
  89         [GECMR]         = 0x05b0,
  90         [BCULR]         = 0x05b4,
  91         [MAHR]          = 0x05c0,
  92         [MALR]          = 0x05c8,
  93         [TROCR]         = 0x0700,
  94         [CDCR]          = 0x0708,
  95         [LCCR]          = 0x0710,
  96         [CEFCR]         = 0x0740,
  97         [FRECR]         = 0x0748,
  98         [TSFRCR]        = 0x0750,
  99         [TLFRCR]        = 0x0758,
 100         [RFCR]          = 0x0760,
 101         [CERCR]         = 0x0768,
 102         [CEECR]         = 0x0770,
 103         [MAFCR]         = 0x0778,
 104         [RMII_MII]      = 0x0790,
 105
 106         [ARSTR]         = 0x0000,
 107         [TSU_CTRST]     = 0x0004,
 108         [TSU_FWEN0]     = 0x0010,
 109         [TSU_FWEN1]     = 0x0014,
 110         [TSU_FCM]       = 0x0018,
 111         [TSU_BSYSL0]    = 0x0020,
 112         [TSU_BSYSL1]    = 0x0024,
 113         [TSU_PRISL0]    = 0x0028,
 114         [TSU_PRISL1]    = 0x002c,
 115         [TSU_FWSL0]     = 0x0030,
 116         [TSU_FWSL1]     = 0x0034,
 117         [TSU_FWSLC]     = 0x0038,
 118         [TSU_QTAG0]     = 0x0040,
 119         [TSU_QTAG1]     = 0x0044,
 120         [TSU_FWSR]      = 0x0050,
 121         [TSU_FWINMK]    = 0x0054,
 122         [TSU_ADQT0]     = 0x0048,
 123         [TSU_ADQT1]     = 0x004c,
 124         [TSU_VTAG0]     = 0x0058,
 125         [TSU_VTAG1]     = 0x005c,
 126         [TSU_ADSBSY]    = 0x0060,
 127         [TSU_TEN]       = 0x0064,
 128         [TSU_POST1]     = 0x0070,
 129         [TSU_POST2]     = 0x0074,
 130         [TSU_POST3]     = 0x0078,
 131         [TSU_POST4]     = 0x007c,
 132         [TSU_ADRH0]     = 0x0100,
 133         [TSU_ADRL0]     = 0x0104,
 134         [TSU_ADRH31]    = 0x01f8,
 135         [TSU_ADRL31]    = 0x01fc,
 136
 137         [TXNLCR0]       = 0x0080,
 138         [TXALCR0]       = 0x0084,
 139         [RXNLCR0]       = 0x0088,
 140         [RXALCR0]       = 0x008c,
 141         [FWNLCR0]       = 0x0090,
 142         [FWALCR0]       = 0x0094,
 143         [TXNLCR1]       = 0x00a0,
 144         [TXALCR1]       = 0x00a0,
 145         [RXNLCR1]       = 0x00a8,
 146         [RXALCR1]       = 0x00ac,
 147         [FWNLCR1]       = 0x00b0,
 148         [FWALCR1]       = 0x00b4,
 149 };
 150
 151 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 152         [ECMR]          = 0x0300,
 153         [RFLR]          = 0x0308,
 154         [ECSR]          = 0x0310,
 155         [ECSIPR]        = 0x0318,
 156         [PIR]           = 0x0320,
 157         [PSR]           = 0x0328,
 158         [RDMLR]         = 0x0340,
 159         [IPGR]          = 0x0350,
 160         [APR]           = 0x0354,
 161         [MPR]           = 0x0358,
 162         [RFCF]          = 0x0360,
 163         [TPAUSER]       = 0x0364,
 164         [TPAUSECR]      = 0x0368,
 165         [MAHR]          = 0x03c0,
 166         [MALR]          = 0x03c8,
 167         [TROCR]         = 0x03d0,
 168         [CDCR]          = 0x03d4,
 169         [LCCR]          = 0x03d8,
 170         [CNDCR]         = 0x03dc,
 171         [CEFCR]         = 0x03e4,
 172         [FRECR]         = 0x03e8,
 173         [TSFRCR]        = 0x03ec,
 174         [TLFRCR]        = 0x03f0,
 175         [RFCR]          = 0x03f4,
 176         [MAFCR]         = 0x03f8,
 177
 178         [EDMR]          = 0x0200,
 179         [EDTRR]         = 0x0208,
 180         [EDRRR]         = 0x0210,
 181         [TDLAR]         = 0x0218,
 182         [RDLAR]         = 0x0220,
 183         [EESR]          = 0x0228,
 184         [EESIPR]        = 0x0230,
 185         [TRSCER]        = 0x0238,
 186         [RMFCR]         = 0x0240,
 187         [TFTR]          = 0x0248,
 188         [FDR]           = 0x0250,
 189         [RMCR]          = 0x0258,
 190         [TFUCR]         = 0x0264,
 191         [RFOCR]         = 0x0268,
 192         [FCFTR]         = 0x0270,
 193         [TRIMD]         = 0x027c,
 194 };
 195
 196 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 197         [ECMR]          = 0x0100,
 198         [RFLR]          = 0x0108,
 199         [ECSR]          = 0x0110,
 200         [ECSIPR]        = 0x0118,
 201         [PIR]           = 0x0120,
 202         [PSR]           = 0x0128,
 203         [RDMLR]         = 0x0140,
 204         [IPGR]          = 0x0150,
 205         [APR]           = 0x0154,
 206         [MPR]           = 0x0158,
 207         [TPAUSER]       = 0x0164,
 208         [RFCF]          = 0x0160,
 209         [TPAUSECR]      = 0x0168,
 210         [BCFRR]         = 0x016c,
 211         [MAHR]          = 0x01c0,
 212         [MALR]          = 0x01c8,
 213         [TROCR]         = 0x01d0,
 214         [CDCR]          = 0x01d4,
 215         [LCCR]          = 0x01d8,
 216         [CNDCR]         = 0x01dc,
 217         [CEFCR]         = 0x01e4,
 218         [FRECR]         = 0x01e8,
 219         [TSFRCR]        = 0x01ec,
 220         [TLFRCR]        = 0x01f0,
 221         [RFCR]          = 0x01f4,
 222         [MAFCR]         = 0x01f8,
 223         [RTRATE]        = 0x01fc,
 224
 225         [EDMR]          = 0x0000,
 226         [EDTRR]         = 0x0008,
 227         [EDRRR]         = 0x0010,
 228         [TDLAR]         = 0x0018,
 229         [RDLAR]         = 0x0020,
 230         [EESR]          = 0x0028,
 231         [EESIPR]        = 0x0030,
 232         [TRSCER]        = 0x0038,
 233         [RMFCR]         = 0x0040,
 234         [TFTR]          = 0x0048,
 235         [FDR]           = 0x0050,
 236         [RMCR]          = 0x0058,
 237         [TFUCR]         = 0x0064,
 238         [RFOCR]         = 0x0068,
 239         [FCFTR]         = 0x0070,
 240         [RPADIR]        = 0x0078,
 241         [TRIMD]         = 0x007c,
 242         [RBWAR]         = 0x00c8,
 243         [RDFAR]         = 0x00cc,
 244         [TBRAR]         = 0x00d4,
 245         [TDFAR]         = 0x00d8,
 246 };
 247
 248 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 249         [ECMR]          = 0x0160,
 250         [ECSR]          = 0x0164,
 251         [ECSIPR]        = 0x0168,
 252         [PIR]           = 0x016c,
 253         [MAHR]          = 0x0170,
 254         [MALR]          = 0x0174,
 255         [RFLR]          = 0x0178,
 256         [PSR]           = 0x017c,
 257         [TROCR]         = 0x0180,
 258         [CDCR]          = 0x0184,
 259         [LCCR]          = 0x0188,
 260         [CNDCR]         = 0x018c,
 261         [CEFCR]         = 0x0194,
 262         [FRECR]         = 0x0198,
 263         [TSFRCR]        = 0x019c,
 264         [TLFRCR]        = 0x01a0,
 265         [RFCR]          = 0x01a4,
 266         [MAFCR]         = 0x01a8,
 267         [IPGR]          = 0x01b4,
 268         [APR]           = 0x01b8,
 269         [MPR]           = 0x01bc,
 270         [TPAUSER]       = 0x01c4,
 271         [BCFR]          = 0x01cc,
 272
 273         [ARSTR]         = 0x0000,
 274         [TSU_CTRST]     = 0x0004,
 275         [TSU_FWEN0]     = 0x0010,
 276         [TSU_FWEN1]     = 0x0014,
 277         [TSU_FCM]       = 0x0018,
 278         [TSU_BSYSL0]    = 0x0020,
 279         [TSU_BSYSL1]    = 0x0024,
 280         [TSU_PRISL0]    = 0x0028,
 281         [TSU_PRISL1]    = 0x002c,
 282         [TSU_FWSL0]     = 0x0030,
 283         [TSU_FWSL1]     = 0x0034,
 284         [TSU_FWSLC]     = 0x0038,
 285         [TSU_QTAGM0]    = 0x0040,
 286         [TSU_QTAGM1]    = 0x0044,
 287         [TSU_ADQT0]     = 0x0048,
 288         [TSU_ADQT1]     = 0x004c,
 289         [TSU_FWSR]      = 0x0050,
 290         [TSU_FWINMK]    = 0x0054,
 291         [TSU_ADSBSY]    = 0x0060,
 292         [TSU_TEN]       = 0x0064,
 293         [TSU_POST1]     = 0x0070,
 294         [TSU_POST2]     = 0x0074,
 295         [TSU_POST3]     = 0x0078,
 296         [TSU_POST4]     = 0x007c,
 297
 298         [TXNLCR0]       = 0x0080,
 299         [TXALCR0]       = 0x0084,
 300         [RXNLCR0]       = 0x0088,
 301         [RXALCR0]       = 0x008c,
 302         [FWNLCR0]       = 0x0090,
 303         [FWALCR0]       = 0x0094,
 304         [TXNLCR1]       = 0x00a0,
 305         [TXALCR1]       = 0x00a0,
 306         [RXNLCR1]       = 0x00a8,
 307         [RXALCR1]       = 0x00ac,
 308         [FWNLCR1]       = 0x00b0,
 309         [FWALCR1]       = 0x00b4,
 310
 311         [TSU_ADRH0]     = 0x0100,
 312         [TSU_ADRL0]     = 0x0104,
 313         [TSU_ADRL31]    = 0x01fc,
 314 };
 315
 316 static int sh_eth_is_gether(struct sh_eth_private *mdp)
 317 {
 318         if (mdp->reg_offset == sh_eth_offset_gigabit)
 319                 return 1;
 320         else
 321                 return 0;
 322 }
 323
 324 static void __maybe_unused sh_eth_select_mii(struct net_device *ndev)
 325 {
 326         u32 value = 0x0;
 327         struct sh_eth_private *mdp = netdev_priv(ndev);
 328
 329         switch (mdp->phy_interface) {
 330         case PHY_INTERFACE_MODE_GMII:
 331                 value = 0x2;
 332                 break;
 333         case PHY_INTERFACE_MODE_MII:
 334                 value = 0x1;
 335                 break;
 336         case PHY_INTERFACE_MODE_RMII:
 337                 value = 0x0;
 338                 break;
 339         default:
 340                 pr_warn("PHY interface mode was not setup. Set to MII.\n");
 341                 value = 0x1;
 342                 break;
 343         }
 344
 345         sh_eth_write(ndev, value, RMII_MII);
 346 }
 347
 348 static void __maybe_unused sh_eth_set_duplex(struct net_device *ndev)
 349 {
 350         struct sh_eth_private *mdp = netdev_priv(ndev);
 351
 352         if (mdp->duplex) /* Full */
 353                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 354         else            /* Half */
 355                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 356 }
 357
 358 /* There is CPU dependent code */
 359 #if defined(CONFIG_ARCH_R8A7778) || defined(CONFIG_ARCH_R8A7779)
 360 static void sh_eth_set_rate(struct net_device *ndev)
 361 {
 362         struct sh_eth_private *mdp = netdev_priv(ndev);
 363
 364         switch (mdp->speed) {
 365         case 10: /* 10BASE */
 366                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 367                 break;
 368         case 100:/* 100BASE */
 369                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 370                 break;
 371         default:
 372                 break;
 373         }
 374 }
 375
 376 /* R8A7778/9 */
 377 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 378         .set_duplex     = sh_eth_set_duplex,
 379         .set_rate       = sh_eth_set_rate,
 380
 381         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 382         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 383         .eesipr_value   = 0x01ff009f,
 384
 385         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 386         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 387                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 388         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 389
 390         .apr            = 1,
 391         .mpr            = 1,
 392         .tpauser        = 1,
 393         .hw_swap        = 1,
 394 };
 395 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
 396
 397 static void sh_eth_set_rate(struct net_device *ndev)
 398 {
 399         struct sh_eth_private *mdp = netdev_priv(ndev);
 400
 401         switch (mdp->speed) {
 402         case 10: /* 10BASE */
 403                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 404                 break;
 405         case 100:/* 100BASE */
 406                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 407                 break;
 408         default:
 409                 break;
 410         }
 411 }
 412
 413 /* SH7724 */
 414 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 415         .set_duplex     = sh_eth_set_duplex,
 416         .set_rate       = sh_eth_set_rate,
 417
 418         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 419         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 420         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
 421
 422         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 423         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 424                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 425         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 426
 427         .apr            = 1,
 428         .mpr            = 1,
 429         .tpauser        = 1,
 430         .hw_swap        = 1,
 431         .rpadir         = 1,
 432         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 433 };
 434 #endif
 435
 436 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 437 {
 438         struct sh_eth_private *mdp = netdev_priv(ndev);
 439
 440         switch (mdp->speed) {
 441         case 10: /* 10BASE */
 442                 sh_eth_write(ndev, 0, RTRATE);
 443                 break;
 444         case 100:/* 100BASE */
 445                 sh_eth_write(ndev, 1, RTRATE);
 446                 break;
 447         default:
 448                 break;
 449         }
 450 }
 451
 452 /* SH7757 */
 453 static struct sh_eth_cpu_data sh7757_data = {
 454         .set_duplex     = sh_eth_set_duplex,
 455         .set_rate       = sh_eth_set_rate_sh7757,
 456
 457         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 458         .rmcr_value     = 0x00000001,
 459
 460         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 461         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
 462                           EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
 463         .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
 464
 465         .irq_flags      = IRQF_SHARED,
 466         .apr            = 1,
 467         .mpr            = 1,
 468         .tpauser        = 1,
 469         .hw_swap        = 1,
 470         .no_ade         = 1,
 471         .rpadir         = 1,
 472         .rpadir_value   = 2 << 16,
 473 };
 474
 475 #define SH_GIGA_ETH_BASE        0xfee00000
 476 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 477 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 478 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 479 {
 480         int i;
 481         unsigned long mahr[2], malr[2];
 482
 483         /* save MAHR and MALR */
 484         for (i = 0; i < 2; i++) {
 485                 malr[i] = ioread32((void *)GIGA_MALR(i));
 486                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 487         }
 488
 489         /* reset device */
 490         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 491         mdelay(1);
 492
 493         /* restore MAHR and MALR */
 494         for (i = 0; i < 2; i++) {
 495                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 496                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 497         }
 498 }
 499
 500 static void sh_eth_set_rate_giga(struct net_device *ndev)
 501 {
 502         struct sh_eth_private *mdp = netdev_priv(ndev);
 503
 504         switch (mdp->speed) {
 505         case 10: /* 10BASE */
 506                 sh_eth_write(ndev, 0x00000000, GECMR);
 507                 break;
 508         case 100:/* 100BASE */
 509                 sh_eth_write(ndev, 0x00000010, GECMR);
 510                 break;
 511         case 1000: /* 1000BASE */
 512                 sh_eth_write(ndev, 0x00000020, GECMR);
 513                 break;
 514         default:
 515                 break;
 516         }
 517 }
 518
 519 /* SH7757(GETHERC) */
 520 static struct sh_eth_cpu_data sh7757_data_giga = {
 521         .chip_reset     = sh_eth_chip_reset_giga,
 522         .set_duplex     = sh_eth_set_duplex,
 523         .set_rate       = sh_eth_set_rate_giga,
 524
 525         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 526         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 527         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 528
 529         .tx_check       = EESR_TC1 | EESR_FTC,
 530         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 531                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 532                           EESR_ECI,
 533         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 534                           EESR_TFE,
 535         .fdr_value      = 0x0000072f,
 536         .rmcr_value     = 0x00000001,
 537
 538         .irq_flags      = IRQF_SHARED,
 539         .apr            = 1,
 540         .mpr            = 1,
 541         .tpauser        = 1,
 542         .bculr          = 1,
 543         .hw_swap        = 1,
 544         .rpadir         = 1,
 545         .rpadir_value   = 2 << 16,
 546         .no_trimd       = 1,
 547         .no_ade         = 1,
 548         .tsu            = 1,
 549 };
 550
 551 static void sh_eth_chip_reset(struct net_device *ndev)
 552 {
 553         struct sh_eth_private *mdp = netdev_priv(ndev);
 554
 555         /* reset device */
 556         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 557         mdelay(1);
 558 }
 559
 560 static void sh_eth_set_rate_gether(struct net_device *ndev)
 561 {
 562         struct sh_eth_private *mdp = netdev_priv(ndev);
 563
 564         switch (mdp->speed) {
 565         case 10: /* 10BASE */
 566                 sh_eth_write(ndev, GECMR_10, GECMR);
 567                 break;
 568         case 100:/* 100BASE */
 569                 sh_eth_write(ndev, GECMR_100, GECMR);
 570                 break;
 571         case 1000: /* 1000BASE */
 572                 sh_eth_write(ndev, GECMR_1000, GECMR);
 573                 break;
 574         default:
 575                 break;
 576         }
 577 }
 578
 579 /* SH7734 */
 580 static struct sh_eth_cpu_data sh7734_data = {
 581         .chip_reset     = sh_eth_chip_reset,
 582         .set_duplex     = sh_eth_set_duplex,
 583         .set_rate       = sh_eth_set_rate_gether,
 584
 585         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 586         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 587         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 588
 589         .tx_check       = EESR_TC1 | EESR_FTC,
 590         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 591                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 592                           EESR_ECI,
 593         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 594                           EESR_TFE,
 595
 596         .apr            = 1,
 597         .mpr            = 1,
 598         .tpauser        = 1,
 599         .bculr          = 1,
 600         .hw_swap        = 1,
 601         .no_trimd       = 1,
 602         .no_ade         = 1,
 603         .tsu            = 1,
 604         .hw_crc         = 1,
 605         .select_mii     = 1,
 606 };
 607
 608 /* SH7763 */
 609 static struct sh_eth_cpu_data sh7763_data = {
 610         .chip_reset     = sh_eth_chip_reset,
 611         .set_duplex     = sh_eth_set_duplex,
 612         .set_rate       = sh_eth_set_rate_gether,
 613
 614         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 615         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 616         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 617
 618         .tx_check       = EESR_TC1 | EESR_FTC,
 619         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 620                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 621                           EESR_ECI,
 622         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 623                           EESR_TFE,
 624
 625         .apr            = 1,
 626         .mpr            = 1,
 627         .tpauser        = 1,
 628         .bculr          = 1,
 629         .hw_swap        = 1,
 630         .no_trimd       = 1,
 631         .no_ade         = 1,
 632         .tsu            = 1,
 633         .irq_flags      = IRQF_SHARED,
 634 };
 635
 636 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 637 {
 638         struct sh_eth_private *mdp = netdev_priv(ndev);
 639
 640         /* reset device */
 641         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 642         mdelay(1);
 643
 644         sh_eth_select_mii(ndev);
 645 }
 646
 647 /* R8A7740 */
 648 static struct sh_eth_cpu_data r8a7740_data = {
 649         .chip_reset     = sh_eth_chip_reset_r8a7740,
 650         .set_duplex     = sh_eth_set_duplex,
 651         .set_rate       = sh_eth_set_rate_gether,
 652
 653         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 654         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 655         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 656
 657         .tx_check       = EESR_TC1 | EESR_FTC,
 658         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
 659                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
 660                           EESR_ECI,
 661         .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
 662                           EESR_TFE,
 663
 664         .apr            = 1,
 665         .mpr            = 1,
 666         .tpauser        = 1,
 667         .bculr          = 1,
 668         .hw_swap        = 1,
 669         .no_trimd       = 1,
 670         .no_ade         = 1,
 671         .tsu            = 1,
 672         .select_mii     = 1,
 673 };
 674
 675 static struct sh_eth_cpu_data sh7619_data = {
 676         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 677
 678         .apr            = 1,
 679         .mpr            = 1,
 680         .tpauser        = 1,
 681         .hw_swap        = 1,
 682 };
 683
 684 static struct sh_eth_cpu_data sh771x_data = {
 685         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 686         .tsu            = 1,
 687 };
 688
 689 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 690 {
 691         if (!cd->ecsr_value)
 692                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 693
 694         if (!cd->ecsipr_value)
 695                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 696
 697         if (!cd->fcftr_value)
 698                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
 699                                   DEFAULT_FIFO_F_D_RFD;
 700
 701         if (!cd->fdr_value)
 702                 cd->fdr_value = DEFAULT_FDR_INIT;
 703
 704         if (!cd->rmcr_value)
 705                 cd->rmcr_value = DEFAULT_RMCR_VALUE;
 706
 707         if (!cd->tx_check)
 708                 cd->tx_check = DEFAULT_TX_CHECK;
 709
 710         if (!cd->eesr_err_check)
 711                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 712
 713         if (!cd->tx_error_check)
 714                 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
 715 }
 716
 717 static int sh_eth_check_reset(struct net_device *ndev)
 718 {
 719         int ret = 0;
 720         int cnt = 100;
 721
 722         while (cnt > 0) {
 723                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 724                         break;
 725                 mdelay(1);
 726                 cnt--;
 727         }
 728         if (cnt < 0) {
 729                 pr_err("Device reset fail\n");
 730                 ret = -ETIMEDOUT;
 731         }
 732         return ret;
 733 }
 734
 735 static int sh_eth_reset(struct net_device *ndev)
 736 {
 737         struct sh_eth_private *mdp = netdev_priv(ndev);
 738         int ret = 0;
 739
 740         if (sh_eth_is_gether(mdp)) {
 741                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 742                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 743                              EDMR);
 744
 745                 ret = sh_eth_check_reset(ndev);
 746                 if (ret)
 747                         goto out;
 748
 749                 /* Table Init */
 750                 sh_eth_write(ndev, 0x0, TDLAR);
 751                 sh_eth_write(ndev, 0x0, TDFAR);
 752                 sh_eth_write(ndev, 0x0, TDFXR);
 753                 sh_eth_write(ndev, 0x0, TDFFR);
 754                 sh_eth_write(ndev, 0x0, RDLAR);
 755                 sh_eth_write(ndev, 0x0, RDFAR);
 756                 sh_eth_write(ndev, 0x0, RDFXR);
 757                 sh_eth_write(ndev, 0x0, RDFFR);
 758
 759                 /* Reset HW CRC register */
 760                 if (mdp->cd->hw_crc)
 761                         sh_eth_write(ndev, 0x0, CSMR);
 762
 763                 /* Select MII mode */
 764                 if (mdp->cd->select_mii)
 765                         sh_eth_select_mii(ndev);
 766         } else {
 767                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 768                              EDMR);
 769                 mdelay(3);
 770                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 771                              EDMR);
 772         }
 773
 774 out:
 775         return ret;
 776 }
 777
 778 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 779 static void sh_eth_set_receive_align(struct sk_buff *skb)
 780 {
 781         int reserve;
 782
 783         reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
 784         if (reserve)
 785                 skb_reserve(skb, reserve);
 786 }
 787 #else
 788 static void sh_eth_set_receive_align(struct sk_buff *skb)
 789 {
 790         skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
 791 }
 792 #endif
 793
 794
 795 /* CPU <-> EDMAC endian convert */
 796 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 797 {
 798         switch (mdp->edmac_endian) {
 799         case EDMAC_LITTLE_ENDIAN:
 800                 return cpu_to_le32(x);
 801         case EDMAC_BIG_ENDIAN:
 802                 return cpu_to_be32(x);
 803         }
 804         return x;
 805 }
 806
 807 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 808 {
 809         switch (mdp->edmac_endian) {
 810         case EDMAC_LITTLE_ENDIAN:
 811                 return le32_to_cpu(x);
 812         case EDMAC_BIG_ENDIAN:
 813                 return be32_to_cpu(x);
 814         }
 815         return x;
 816 }
 817
 818 /*
 819  * Program the hardware MAC address from dev->dev_addr.
 820  */
 821 static void update_mac_address(struct net_device *ndev)
 822 {
 823         sh_eth_write(ndev,
 824                 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 825                 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 826         sh_eth_write(ndev,
 827                 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 828 }
 829
 830 /*
 831  * Get MAC address from SuperH MAC address register
 832  *
 833  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 834  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 835  * When you want use this device, you must set MAC address in bootloader.
 836  *
 837  */
 838 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 839 {
 840         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 841                 memcpy(ndev->dev_addr, mac, 6);
 842         } else {
 843                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 844                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 845                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 846                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 847                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 848                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 849         }
 850 }
 851
 852 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
 853 {
 854         if (sh_eth_is_gether(mdp))
 855                 return EDTRR_TRNS_GETHER;
 856         else
 857                 return EDTRR_TRNS_ETHER;
 858 }
 859
 860 struct bb_info {
 861         void (*set_gate)(void *addr);
 862         struct mdiobb_ctrl ctrl;
 863         void *addr;
 864         u32 mmd_msk;/* MMD */
 865         u32 mdo_msk;
 866         u32 mdi_msk;
 867         u32 mdc_msk;
 868 };
 869
 870 /* PHY bit set */
 871 static void bb_set(void *addr, u32 msk)
 872 {
 873         iowrite32(ioread32(addr) | msk, addr);
 874 }
 875
 876 /* PHY bit clear */
 877 static void bb_clr(void *addr, u32 msk)
 878 {
 879         iowrite32((ioread32(addr) & ~msk), addr);
 880 }
 881
 882 /* PHY bit read */
 883 static int bb_read(void *addr, u32 msk)
 884 {
 885         return (ioread32(addr) & msk) != 0;
 886 }
 887
 888 /* Data I/O pin control */
 889 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 890 {
 891         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 892
 893         if (bitbang->set_gate)
 894                 bitbang->set_gate(bitbang->addr);
 895
 896         if (bit)
 897                 bb_set(bitbang->addr, bitbang->mmd_msk);
 898         else
 899                 bb_clr(bitbang->addr, bitbang->mmd_msk);
 900 }
 901
 902 /* Set bit data*/
 903 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
 904 {
 905         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 906
 907         if (bitbang->set_gate)
 908                 bitbang->set_gate(bitbang->addr);
 909
 910         if (bit)
 911                 bb_set(bitbang->addr, bitbang->mdo_msk);
 912         else
 913                 bb_clr(bitbang->addr, bitbang->mdo_msk);
 914 }
 915
 916 /* Get bit data*/
 917 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
 918 {
 919         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 920
 921         if (bitbang->set_gate)
 922                 bitbang->set_gate(bitbang->addr);
 923
 924         return bb_read(bitbang->addr, bitbang->mdi_msk);
 925 }
 926
 927 /* MDC pin control */
 928 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
 929 {
 930         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
 931
 932         if (bitbang->set_gate)
 933                 bitbang->set_gate(bitbang->addr);
 934
 935         if (bit)
 936                 bb_set(bitbang->addr, bitbang->mdc_msk);
 937         else
 938                 bb_clr(bitbang->addr, bitbang->mdc_msk);
 939 }
 940
 941 /* mdio bus control struct */
 942 static struct mdiobb_ops bb_ops = {
 943         .owner = THIS_MODULE,
 944         .set_mdc = sh_mdc_ctrl,
 945         .set_mdio_dir = sh_mmd_ctrl,
 946         .set_mdio_data = sh_set_mdio,
 947         .get_mdio_data = sh_get_mdio,
 948 };
 949
 950 /* free skb and descriptor buffer */
 951 static void sh_eth_ring_free(struct net_device *ndev)
 952 {
 953         struct sh_eth_private *mdp = netdev_priv(ndev);
 954         int i;
 955
 956         /* Free Rx skb ringbuffer */
 957         if (mdp->rx_skbuff) {
 958                 for (i = 0; i < mdp->num_rx_ring; i++) {
 959                         if (mdp->rx_skbuff[i])
 960                                 dev_kfree_skb(mdp->rx_skbuff[i]);
 961                 }
 962         }
 963         kfree(mdp->rx_skbuff);
 964         mdp->rx_skbuff = NULL;
 965
 966         /* Free Tx skb ringbuffer */
 967         if (mdp->tx_skbuff) {
 968                 for (i = 0; i < mdp->num_tx_ring; i++) {
 969                         if (mdp->tx_skbuff[i])
 970                                 dev_kfree_skb(mdp->tx_skbuff[i]);
 971                 }
 972         }
 973         kfree(mdp->tx_skbuff);
 974         mdp->tx_skbuff = NULL;
 975 }
 976
 977 /* format skb and descriptor buffer */
 978 static void sh_eth_ring_format(struct net_device *ndev)
 979 {
 980         struct sh_eth_private *mdp = netdev_priv(ndev);
 981         int i;
 982         struct sk_buff *skb;
 983         struct sh_eth_rxdesc *rxdesc = NULL;
 984         struct sh_eth_txdesc *txdesc = NULL;
 985         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
 986         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
 987
 988         mdp->cur_rx = mdp->cur_tx = 0;
 989         mdp->dirty_rx = mdp->dirty_tx = 0;
 990
 991         memset(mdp->rx_ring, 0, rx_ringsize);
 992
 993         /* build Rx ring buffer */
 994         for (i = 0; i < mdp->num_rx_ring; i++) {
 995                 /* skb */
 996                 mdp->rx_skbuff[i] = NULL;
 997                 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
 998                 mdp->rx_skbuff[i] = skb;
 999                 if (skb == NULL)
1000                         break;
1001                 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1002                                 DMA_FROM_DEVICE);
1003                 sh_eth_set_receive_align(skb);
1004
1005                 /* RX descriptor */
1006                 rxdesc = &mdp->rx_ring[i];
1007                 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1008                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1009
1010                 /* The size of the buffer is 16 byte boundary. */
1011                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1012                 /* Rx descriptor address set */
1013                 if (i == 0) {
1014                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1015                         if (sh_eth_is_gether(mdp))
1016                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1017                 }
1018         }
1019
1020         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1021
1022         /* Mark the last entry as wrapping the ring. */
1023         rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1024
1025         memset(mdp->tx_ring, 0, tx_ringsize);
1026
1027         /* build Tx ring buffer */
1028         for (i = 0; i < mdp->num_tx_ring; i++) {
1029                 mdp->tx_skbuff[i] = NULL;
1030                 txdesc = &mdp->tx_ring[i];
1031                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1032                 txdesc->buffer_length = 0;
1033                 if (i == 0) {
1034                         /* Tx descriptor address set */
1035                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1036                         if (sh_eth_is_gether(mdp))
1037                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1038                 }
1039         }
1040
1041         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1042 }
1043
1044 /* Get skb and descriptor buffer */
1045 static int sh_eth_ring_init(struct net_device *ndev)
1046 {
1047         struct sh_eth_private *mdp = netdev_priv(ndev);
1048         int rx_ringsize, tx_ringsize, ret = 0;
1049
1050         /*
1051          * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1052          * card needs room to do 8 byte alignment, +2 so we can reserve
1053          * the first 2 bytes, and +16 gets room for the status word from the
1054          * card.
1055          */
1056         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1057                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1058         if (mdp->cd->rpadir)
1059                 mdp->rx_buf_sz += NET_IP_ALIGN;
1060
1061         /* Allocate RX and TX skb rings */
1062         mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1063                                        sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1064         if (!mdp->rx_skbuff) {
1065                 ret = -ENOMEM;
1066                 return ret;
1067         }
1068
1069         mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1070                                        sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1071         if (!mdp->tx_skbuff) {
1072                 ret = -ENOMEM;
1073                 goto skb_ring_free;
1074         }
1075
1076         /* Allocate all Rx descriptors. */
1077         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1078         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1079                                           GFP_KERNEL);
1080         if (!mdp->rx_ring) {
1081                 ret = -ENOMEM;
1082                 goto desc_ring_free;
1083         }
1084
1085         mdp->dirty_rx = 0;
1086
1087         /* Allocate all Tx descriptors. */
1088         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1089         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1090                                           GFP_KERNEL);
1091         if (!mdp->tx_ring) {
1092                 ret = -ENOMEM;
1093                 goto desc_ring_free;
1094         }
1095         return ret;
1096
1097 desc_ring_free:
1098         /* free DMA buffer */
1099         dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1100
1101 skb_ring_free:
1102         /* Free Rx and Tx skb ring buffer */
1103         sh_eth_ring_free(ndev);
1104         mdp->tx_ring = NULL;
1105         mdp->rx_ring = NULL;
1106
1107         return ret;
1108 }
1109
1110 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1111 {
1112         int ringsize;
1113
1114         if (mdp->rx_ring) {
1115                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1116                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1117                                   mdp->rx_desc_dma);
1118                 mdp->rx_ring = NULL;
1119         }
1120
1121         if (mdp->tx_ring) {
1122                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1123                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1124                                   mdp->tx_desc_dma);
1125                 mdp->tx_ring = NULL;
1126         }
1127 }
1128
1129 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1130 {
1131         int ret = 0;
1132         struct sh_eth_private *mdp = netdev_priv(ndev);
1133         u32 val;
1134
1135         /* Soft Reset */
1136         ret = sh_eth_reset(ndev);
1137         if (ret)
1138                 goto out;
1139
1140         /* Descriptor format */
1141         sh_eth_ring_format(ndev);
1142         if (mdp->cd->rpadir)
1143                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1144
1145         /* all sh_eth int mask */
1146         sh_eth_write(ndev, 0, EESIPR);
1147
1148 #if defined(__LITTLE_ENDIAN)
1149         if (mdp->cd->hw_swap)
1150                 sh_eth_write(ndev, EDMR_EL, EDMR);
1151         else
1152 #endif
1153                 sh_eth_write(ndev, 0, EDMR);
1154
1155         /* FIFO size set */
1156         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1157         sh_eth_write(ndev, 0, TFTR);
1158
1159         /* Frame recv control */
1160         sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
1161
1162         sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
1163
1164         if (mdp->cd->bculr)
1165                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1166
1167         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1168
1169         if (!mdp->cd->no_trimd)
1170                 sh_eth_write(ndev, 0, TRIMD);
1171
1172         /* Recv frame limit set register */
1173         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1174                      RFLR);
1175
1176         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1177         if (start)
1178                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1179
1180         /* PAUSE Prohibition */
1181         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1182                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1183
1184         sh_eth_write(ndev, val, ECMR);
1185
1186         if (mdp->cd->set_rate)
1187                 mdp->cd->set_rate(ndev);
1188
1189         /* E-MAC Status Register clear */
1190         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1191
1192         /* E-MAC Interrupt Enable register */
1193         if (start)
1194                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1195
1196         /* Set MAC address */
1197         update_mac_address(ndev);
1198
1199         /* mask reset */
1200         if (mdp->cd->apr)
1201                 sh_eth_write(ndev, APR_AP, APR);
1202         if (mdp->cd->mpr)
1203                 sh_eth_write(ndev, MPR_MP, MPR);
1204         if (mdp->cd->tpauser)
1205                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1206
1207         if (start) {
1208                 /* Setting the Rx mode will start the Rx process. */
1209                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1210
1211                 netif_start_queue(ndev);
1212         }
1213
1214 out:
1215         return ret;
1216 }
1217
1218 /* free Tx skb function */
1219 static int sh_eth_txfree(struct net_device *ndev)
1220 {
1221         struct sh_eth_private *mdp = netdev_priv(ndev);
1222         struct sh_eth_txdesc *txdesc;
1223         int freeNum = 0;
1224         int entry = 0;
1225
1226         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1227                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1228                 txdesc = &mdp->tx_ring[entry];
1229                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1230                         break;
1231                 /* Free the original skb. */
1232                 if (mdp->tx_skbuff[entry]) {
1233                         dma_unmap_single(&ndev->dev, txdesc->addr,
1234                                          txdesc->buffer_length, DMA_TO_DEVICE);
1235                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1236                         mdp->tx_skbuff[entry] = NULL;
1237                         freeNum++;
1238                 }
1239                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1240                 if (entry >= mdp->num_tx_ring - 1)
1241                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1242
1243                 ndev->stats.tx_packets++;
1244                 ndev->stats.tx_bytes += txdesc->buffer_length;
1245         }
1246         return freeNum;
1247 }
1248
1249 /* Packet receive function */
1250 static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
1251 {
1252         struct sh_eth_private *mdp = netdev_priv(ndev);
1253         struct sh_eth_rxdesc *rxdesc;
1254
1255         int entry = mdp->cur_rx % mdp->num_rx_ring;
1256         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1257         struct sk_buff *skb;
1258         u16 pkt_len = 0;
1259         u32 desc_status;
1260
1261         rxdesc = &mdp->rx_ring[entry];
1262         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1263                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1264                 pkt_len = rxdesc->frame_length;
1265
1266 #if defined(CONFIG_ARCH_R8A7740)
1267                 desc_status >>= 16;
1268 #endif
1269
1270                 if (--boguscnt < 0)
1271                         break;
1272
1273                 if (!(desc_status & RDFEND))
1274                         ndev->stats.rx_length_errors++;
1275
1276                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1277                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1278                         ndev->stats.rx_errors++;
1279                         if (desc_status & RD_RFS1)
1280                                 ndev->stats.rx_crc_errors++;
1281                         if (desc_status & RD_RFS2)
1282                                 ndev->stats.rx_frame_errors++;
1283                         if (desc_status & RD_RFS3)
1284                                 ndev->stats.rx_length_errors++;
1285                         if (desc_status & RD_RFS4)
1286                                 ndev->stats.rx_length_errors++;
1287                         if (desc_status & RD_RFS6)
1288                                 ndev->stats.rx_missed_errors++;
1289                         if (desc_status & RD_RFS10)
1290                                 ndev->stats.rx_over_errors++;
1291                 } else {
1292                         if (!mdp->cd->hw_swap)
1293                                 sh_eth_soft_swap(
1294                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1295                                         pkt_len + 2);
1296                         skb = mdp->rx_skbuff[entry];
1297                         mdp->rx_skbuff[entry] = NULL;
1298                         if (mdp->cd->rpadir)
1299                                 skb_reserve(skb, NET_IP_ALIGN);
1300                         skb_put(skb, pkt_len);
1301                         skb->protocol = eth_type_trans(skb, ndev);
1302                         netif_rx(skb);
1303                         ndev->stats.rx_packets++;
1304                         ndev->stats.rx_bytes += pkt_len;
1305                 }
1306                 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
1307                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1308                 rxdesc = &mdp->rx_ring[entry];
1309         }
1310
1311         /* Refill the Rx ring buffers. */
1312         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1313                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1314                 rxdesc = &mdp->rx_ring[entry];
1315                 /* The size of the buffer is 16 byte boundary. */
1316                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1317
1318                 if (mdp->rx_skbuff[entry] == NULL) {
1319                         skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz);
1320                         mdp->rx_skbuff[entry] = skb;
1321                         if (skb == NULL)
1322                                 break;  /* Better luck next round. */
1323                         dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz,
1324                                         DMA_FROM_DEVICE);
1325                         sh_eth_set_receive_align(skb);
1326
1327                         skb_checksum_none_assert(skb);
1328                         rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
1329                 }
1330                 if (entry >= mdp->num_rx_ring - 1)
1331                         rxdesc->status |=
1332                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1333                 else
1334                         rxdesc->status |=
1335                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1336         }
1337
1338         /* Restart Rx engine if stopped. */
1339         /* If we don't need to check status, don't. -KDU */
1340         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1341                 /* fix the values for the next receiving if RDE is set */
1342                 if (intr_status & EESR_RDE)
1343                         mdp->cur_rx = mdp->dirty_rx =
1344                                 (sh_eth_read(ndev, RDFAR) -
1345                                  sh_eth_read(ndev, RDLAR)) >> 4;
1346                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1347         }
1348
1349         return 0;
1350 }
1351
1352 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1353 {
1354         /* disable tx and rx */
1355         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1356                 ~(ECMR_RE | ECMR_TE), ECMR);
1357 }
1358
1359 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1360 {
1361         /* enable tx and rx */
1362         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1363                 (ECMR_RE | ECMR_TE), ECMR);
1364 }
1365
1366 /* error control function */
1367 static void sh_eth_error(struct net_device *ndev, int intr_status)
1368 {
1369         struct sh_eth_private *mdp = netdev_priv(ndev);
1370         u32 felic_stat;
1371         u32 link_stat;
1372         u32 mask;
1373
1374         if (intr_status & EESR_ECI) {
1375                 felic_stat = sh_eth_read(ndev, ECSR);
1376                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1377                 if (felic_stat & ECSR_ICD)
1378                         ndev->stats.tx_carrier_errors++;
1379                 if (felic_stat & ECSR_LCHNG) {
1380                         /* Link Changed */
1381                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1382                                 goto ignore_link;
1383                         } else {
1384                                 link_stat = (sh_eth_read(ndev, PSR));
1385                                 if (mdp->ether_link_active_low)
1386                                         link_stat = ~link_stat;
1387                         }
1388                         if (!(link_stat & PHY_ST_LINK))
1389                                 sh_eth_rcv_snd_disable(ndev);
1390                         else {
1391                                 /* Link Up */
1392                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1393                                           ~DMAC_M_ECI, EESIPR);
1394                                 /*clear int */
1395                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1396                                           ECSR);
1397                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1398                                           DMAC_M_ECI, EESIPR);
1399                                 /* enable tx and rx */
1400                                 sh_eth_rcv_snd_enable(ndev);
1401                         }
1402                 }
1403         }
1404
1405 ignore_link:
1406         if (intr_status & EESR_TWB) {
1407                 /* Write buck end. unused write back interrupt */
1408                 if (intr_status & EESR_TABT)    /* Transmit Abort int */
1409                         ndev->stats.tx_aborted_errors++;
1410                         if (netif_msg_tx_err(mdp))
1411                                 dev_err(&ndev->dev, "Transmit Abort\n");
1412         }
1413
1414         if (intr_status & EESR_RABT) {
1415                 /* Receive Abort int */
1416                 if (intr_status & EESR_RFRMER) {
1417                         /* Receive Frame Overflow int */
1418                         ndev->stats.rx_frame_errors++;
1419                         if (netif_msg_rx_err(mdp))
1420                                 dev_err(&ndev->dev, "Receive Abort\n");
1421                 }
1422         }
1423
1424         if (intr_status & EESR_TDE) {
1425                 /* Transmit Descriptor Empty int */
1426                 ndev->stats.tx_fifo_errors++;
1427                 if (netif_msg_tx_err(mdp))
1428                         dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1429         }
1430
1431         if (intr_status & EESR_TFE) {
1432                 /* FIFO under flow */
1433                 ndev->stats.tx_fifo_errors++;
1434                 if (netif_msg_tx_err(mdp))
1435                         dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
1436         }
1437
1438         if (intr_status & EESR_RDE) {
1439                 /* Receive Descriptor Empty int */
1440                 ndev->stats.rx_over_errors++;
1441
1442                 if (netif_msg_rx_err(mdp))
1443                         dev_err(&ndev->dev, "Receive Descriptor Empty\n");
1444         }
1445
1446         if (intr_status & EESR_RFE) {
1447                 /* Receive FIFO Overflow int */
1448                 ndev->stats.rx_fifo_errors++;
1449                 if (netif_msg_rx_err(mdp))
1450                         dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1451         }
1452
1453         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1454                 /* Address Error */
1455                 ndev->stats.tx_fifo_errors++;
1456                 if (netif_msg_tx_err(mdp))
1457                         dev_err(&ndev->dev, "Address Error\n");
1458         }
1459
1460         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1461         if (mdp->cd->no_ade)
1462                 mask &= ~EESR_ADE;
1463         if (intr_status & mask) {
1464                 /* Tx error */
1465                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1466                 /* dmesg */
1467                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1468                                 intr_status, mdp->cur_tx);
1469                 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1470                                 mdp->dirty_tx, (u32) ndev->state, edtrr);
1471                 /* dirty buffer free */
1472                 sh_eth_txfree(ndev);
1473
1474                 /* SH7712 BUG */
1475                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1476                         /* tx dma start */
1477                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1478                 }
1479                 /* wakeup */
1480                 netif_wake_queue(ndev);
1481         }
1482 }
1483
1484 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1485 {
1486         struct net_device *ndev = netdev;
1487         struct sh_eth_private *mdp = netdev_priv(ndev);
1488         struct sh_eth_cpu_data *cd = mdp->cd;
1489         irqreturn_t ret = IRQ_NONE;
1490         unsigned long intr_status;
1491
1492         spin_lock(&mdp->lock);
1493
1494         /* Get interrupt status */
1495         intr_status = sh_eth_read(ndev, EESR);
1496         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1497          * enabled since it's the one that  comes thru regardless of the mask,
1498          * and we need to fully handle it in sh_eth_error() in order to quench
1499          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1500          */
1501         intr_status &= sh_eth_read(ndev, EESIPR) | DMAC_M_ECI;
1502         /* Clear interrupt */
1503         if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1504                         EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
1505                         cd->tx_check | cd->eesr_err_check)) {
1506                 sh_eth_write(ndev, intr_status, EESR);
1507                 ret = IRQ_HANDLED;
1508         } else
1509                 goto other_irq;
1510
1511         if (intr_status & (EESR_FRC | /* Frame recv*/
1512                         EESR_RMAF | /* Multi cast address recv*/
1513                         EESR_RRF  | /* Bit frame recv */
1514                         EESR_RTLF | /* Long frame recv*/
1515                         EESR_RTSF | /* short frame recv */
1516                         EESR_PRE  | /* PHY-LSI recv error */
1517                         EESR_CERF)){ /* recv frame CRC error */
1518                 sh_eth_rx(ndev, intr_status);
1519         }
1520
1521         /* Tx Check */
1522         if (intr_status & cd->tx_check) {
1523                 sh_eth_txfree(ndev);
1524                 netif_wake_queue(ndev);
1525         }
1526
1527         if (intr_status & cd->eesr_err_check)
1528                 sh_eth_error(ndev, intr_status);
1529
1530 other_irq:
1531         spin_unlock(&mdp->lock);
1532
1533         return ret;
1534 }
1535
1536 /* PHY state control function */
1537 static void sh_eth_adjust_link(struct net_device *ndev)
1538 {
1539         struct sh_eth_private *mdp = netdev_priv(ndev);
1540         struct phy_device *phydev = mdp->phydev;
1541         int new_state = 0;
1542
1543         if (phydev->link) {
1544                 if (phydev->duplex != mdp->duplex) {
1545                         new_state = 1;
1546                         mdp->duplex = phydev->duplex;
1547                         if (mdp->cd->set_duplex)
1548                                 mdp->cd->set_duplex(ndev);
1549                 }
1550
1551                 if (phydev->speed != mdp->speed) {
1552                         new_state = 1;
1553                         mdp->speed = phydev->speed;
1554                         if (mdp->cd->set_rate)
1555                                 mdp->cd->set_rate(ndev);
1556                 }
1557                 if (!mdp->link) {
1558                         sh_eth_write(ndev,
1559                                 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
1560                         new_state = 1;
1561                         mdp->link = phydev->link;
1562                         if (mdp->cd->no_psr || mdp->no_ether_link)
1563                                 sh_eth_rcv_snd_enable(ndev);
1564                 }
1565         } else if (mdp->link) {
1566                 new_state = 1;
1567                 mdp->link = 0;
1568                 mdp->speed = 0;
1569                 mdp->duplex = -1;
1570                 if (mdp->cd->no_psr || mdp->no_ether_link)
1571                         sh_eth_rcv_snd_disable(ndev);
1572         }
1573
1574         if (new_state && netif_msg_link(mdp))
1575                 phy_print_status(phydev);
1576 }
1577
1578 /* PHY init function */
1579 static int sh_eth_phy_init(struct net_device *ndev)
1580 {
1581         struct sh_eth_private *mdp = netdev_priv(ndev);
1582         char phy_id[MII_BUS_ID_SIZE + 3];
1583         struct phy_device *phydev = NULL;
1584
1585         snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1586                 mdp->mii_bus->id , mdp->phy_id);
1587
1588         mdp->link = 0;
1589         mdp->speed = 0;
1590         mdp->duplex = -1;
1591
1592         /* Try connect to PHY */
1593         phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1594                              mdp->phy_interface);
1595         if (IS_ERR(phydev)) {
1596                 dev_err(&ndev->dev, "phy_connect failed\n");
1597                 return PTR_ERR(phydev);
1598         }
1599
1600         dev_info(&ndev->dev, "attached phy %i to driver %s\n",
1601                 phydev->addr, phydev->drv->name);
1602
1603         mdp->phydev = phydev;
1604
1605         return 0;
1606 }
1607
1608 /* PHY control start function */
1609 static int sh_eth_phy_start(struct net_device *ndev)
1610 {
1611         struct sh_eth_private *mdp = netdev_priv(ndev);
1612         int ret;
1613
1614         ret = sh_eth_phy_init(ndev);
1615         if (ret)
1616                 return ret;
1617
1618         /* reset phy - this also wakes it from PDOWN */
1619         phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1620         phy_start(mdp->phydev);
1621
1622         return 0;
1623 }
1624
1625 static int sh_eth_get_settings(struct net_device *ndev,
1626                         struct ethtool_cmd *ecmd)
1627 {
1628         struct sh_eth_private *mdp = netdev_priv(ndev);
1629         unsigned long flags;
1630         int ret;
1631
1632         spin_lock_irqsave(&mdp->lock, flags);
1633         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1634         spin_unlock_irqrestore(&mdp->lock, flags);
1635
1636         return ret;
1637 }
1638
1639 static int sh_eth_set_settings(struct net_device *ndev,
1640                 struct ethtool_cmd *ecmd)
1641 {
1642         struct sh_eth_private *mdp = netdev_priv(ndev);
1643         unsigned long flags;
1644         int ret;
1645
1646         spin_lock_irqsave(&mdp->lock, flags);
1647
1648         /* disable tx and rx */
1649         sh_eth_rcv_snd_disable(ndev);
1650
1651         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1652         if (ret)
1653                 goto error_exit;
1654
1655         if (ecmd->duplex == DUPLEX_FULL)
1656                 mdp->duplex = 1;
1657         else
1658                 mdp->duplex = 0;
1659
1660         if (mdp->cd->set_duplex)
1661                 mdp->cd->set_duplex(ndev);
1662
1663 error_exit:
1664         mdelay(1);
1665
1666         /* enable tx and rx */
1667         sh_eth_rcv_snd_enable(ndev);
1668
1669         spin_unlock_irqrestore(&mdp->lock, flags);
1670
1671         return ret;
1672 }
1673
1674 static int sh_eth_nway_reset(struct net_device *ndev)
1675 {
1676         struct sh_eth_private *mdp = netdev_priv(ndev);
1677         unsigned long flags;
1678         int ret;
1679
1680         spin_lock_irqsave(&mdp->lock, flags);
1681         ret = phy_start_aneg(mdp->phydev);
1682         spin_unlock_irqrestore(&mdp->lock, flags);
1683
1684         return ret;
1685 }
1686
1687 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1688 {
1689         struct sh_eth_private *mdp = netdev_priv(ndev);
1690         return mdp->msg_enable;
1691 }
1692
1693 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1694 {
1695         struct sh_eth_private *mdp = netdev_priv(ndev);
1696         mdp->msg_enable = value;
1697 }
1698
1699 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1700         "rx_current", "tx_current",
1701         "rx_dirty", "tx_dirty",
1702 };
1703 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
1704
1705 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1706 {
1707         switch (sset) {
1708         case ETH_SS_STATS:
1709                 return SH_ETH_STATS_LEN;
1710         default:
1711                 return -EOPNOTSUPP;
1712         }
1713 }
1714
1715 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1716                         struct ethtool_stats *stats, u64 *data)
1717 {
1718         struct sh_eth_private *mdp = netdev_priv(ndev);
1719         int i = 0;
1720
1721         /* device-specific stats */
1722         data[i++] = mdp->cur_rx;
1723         data[i++] = mdp->cur_tx;
1724         data[i++] = mdp->dirty_rx;
1725         data[i++] = mdp->dirty_tx;
1726 }
1727
1728 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1729 {
1730         switch (stringset) {
1731         case ETH_SS_STATS:
1732                 memcpy(data, *sh_eth_gstrings_stats,
1733                                         sizeof(sh_eth_gstrings_stats));
1734                 break;
1735         }
1736 }
1737
1738 static void sh_eth_get_ringparam(struct net_device *ndev,
1739                                  struct ethtool_ringparam *ring)
1740 {
1741         struct sh_eth_private *mdp = netdev_priv(ndev);
1742
1743         ring->rx_max_pending = RX_RING_MAX;
1744         ring->tx_max_pending = TX_RING_MAX;
1745         ring->rx_pending = mdp->num_rx_ring;
1746         ring->tx_pending = mdp->num_tx_ring;
1747 }
1748
1749 static int sh_eth_set_ringparam(struct net_device *ndev,
1750                                 struct ethtool_ringparam *ring)
1751 {
1752         struct sh_eth_private *mdp = netdev_priv(ndev);
1753         int ret;
1754
1755         if (ring->tx_pending > TX_RING_MAX ||
1756             ring->rx_pending > RX_RING_MAX ||
1757             ring->tx_pending < TX_RING_MIN ||
1758             ring->rx_pending < RX_RING_MIN)
1759                 return -EINVAL;
1760         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1761                 return -EINVAL;
1762
1763         if (netif_running(ndev)) {
1764                 netif_tx_disable(ndev);
1765                 /* Disable interrupts by clearing the interrupt mask. */
1766                 sh_eth_write(ndev, 0x0000, EESIPR);
1767                 /* Stop the chip's Tx and Rx processes. */
1768                 sh_eth_write(ndev, 0, EDTRR);
1769                 sh_eth_write(ndev, 0, EDRRR);
1770                 synchronize_irq(ndev->irq);
1771         }
1772
1773         /* Free all the skbuffs in the Rx queue. */
1774         sh_eth_ring_free(ndev);
1775         /* Free DMA buffer */
1776         sh_eth_free_dma_buffer(mdp);
1777
1778         /* Set new parameters */
1779         mdp->num_rx_ring = ring->rx_pending;
1780         mdp->num_tx_ring = ring->tx_pending;
1781
1782         ret = sh_eth_ring_init(ndev);
1783         if (ret < 0) {
1784                 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__);
1785                 return ret;
1786         }
1787         ret = sh_eth_dev_init(ndev, false);
1788         if (ret < 0) {
1789                 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__);
1790                 return ret;
1791         }
1792
1793         if (netif_running(ndev)) {
1794                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1795                 /* Setting the Rx mode will start the Rx process. */
1796                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1797                 netif_wake_queue(ndev);
1798         }
1799
1800         return 0;
1801 }
1802
1803 static const struct ethtool_ops sh_eth_ethtool_ops = {
1804         .get_settings   = sh_eth_get_settings,
1805         .set_settings   = sh_eth_set_settings,
1806         .nway_reset     = sh_eth_nway_reset,
1807         .get_msglevel   = sh_eth_get_msglevel,
1808         .set_msglevel   = sh_eth_set_msglevel,
1809         .get_link       = ethtool_op_get_link,
1810         .get_strings    = sh_eth_get_strings,
1811         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
1812         .get_sset_count     = sh_eth_get_sset_count,
1813         .get_ringparam  = sh_eth_get_ringparam,
1814         .set_ringparam  = sh_eth_set_ringparam,
1815 };
1816
1817 /* network device open function */
1818 static int sh_eth_open(struct net_device *ndev)
1819 {
1820         int ret = 0;
1821         struct sh_eth_private *mdp = netdev_priv(ndev);
1822
1823         pm_runtime_get_sync(&mdp->pdev->dev);
1824
1825         ret = request_irq(ndev->irq, sh_eth_interrupt,
1826                           mdp->cd->irq_flags, ndev->name, ndev);
1827         if (ret) {
1828                 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1829                 return ret;
1830         }
1831
1832         /* Descriptor set */
1833         ret = sh_eth_ring_init(ndev);
1834         if (ret)
1835                 goto out_free_irq;
1836
1837         /* device init */
1838         ret = sh_eth_dev_init(ndev, true);
1839         if (ret)
1840                 goto out_free_irq;
1841
1842         /* PHY control start*/
1843         ret = sh_eth_phy_start(ndev);
1844         if (ret)
1845                 goto out_free_irq;
1846
1847         return ret;
1848
1849 out_free_irq:
1850         free_irq(ndev->irq, ndev);
1851         pm_runtime_put_sync(&mdp->pdev->dev);
1852         return ret;
1853 }
1854
1855 /* Timeout function */
1856 static void sh_eth_tx_timeout(struct net_device *ndev)
1857 {
1858         struct sh_eth_private *mdp = netdev_priv(ndev);
1859         struct sh_eth_rxdesc *rxdesc;
1860         int i;
1861
1862         netif_stop_queue(ndev);
1863
1864         if (netif_msg_timer(mdp))
1865                 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
1866                " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
1867
1868         /* tx_errors count up */
1869         ndev->stats.tx_errors++;
1870
1871         /* Free all the skbuffs in the Rx queue. */
1872         for (i = 0; i < mdp->num_rx_ring; i++) {
1873                 rxdesc = &mdp->rx_ring[i];
1874                 rxdesc->status = 0;
1875                 rxdesc->addr = 0xBADF00D0;
1876                 if (mdp->rx_skbuff[i])
1877                         dev_kfree_skb(mdp->rx_skbuff[i]);
1878                 mdp->rx_skbuff[i] = NULL;
1879         }
1880         for (i = 0; i < mdp->num_tx_ring; i++) {
1881                 if (mdp->tx_skbuff[i])
1882                         dev_kfree_skb(mdp->tx_skbuff[i]);
1883                 mdp->tx_skbuff[i] = NULL;
1884         }
1885
1886         /* device init */
1887         sh_eth_dev_init(ndev, true);
1888 }
1889
1890 /* Packet transmit function */
1891 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1892 {
1893         struct sh_eth_private *mdp = netdev_priv(ndev);
1894         struct sh_eth_txdesc *txdesc;
1895         u32 entry;
1896         unsigned long flags;
1897
1898         spin_lock_irqsave(&mdp->lock, flags);
1899         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
1900                 if (!sh_eth_txfree(ndev)) {
1901                         if (netif_msg_tx_queued(mdp))
1902                                 dev_warn(&ndev->dev, "TxFD exhausted.\n");
1903                         netif_stop_queue(ndev);
1904                         spin_unlock_irqrestore(&mdp->lock, flags);
1905                         return NETDEV_TX_BUSY;
1906                 }
1907         }
1908         spin_unlock_irqrestore(&mdp->lock, flags);
1909
1910         entry = mdp->cur_tx % mdp->num_tx_ring;
1911         mdp->tx_skbuff[entry] = skb;
1912         txdesc = &mdp->tx_ring[entry];
1913         /* soft swap. */
1914         if (!mdp->cd->hw_swap)
1915                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1916                                  skb->len + 2);
1917         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
1918                                       DMA_TO_DEVICE);
1919         if (skb->len < ETHERSMALL)
1920                 txdesc->buffer_length = ETHERSMALL;
1921         else
1922                 txdesc->buffer_length = skb->len;
1923
1924         if (entry >= mdp->num_tx_ring - 1)
1925                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1926         else
1927                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1928
1929         mdp->cur_tx++;
1930
1931         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1932                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1933
1934         return NETDEV_TX_OK;
1935 }
1936
1937 /* device close function */
1938 static int sh_eth_close(struct net_device *ndev)
1939 {
1940         struct sh_eth_private *mdp = netdev_priv(ndev);
1941
1942         netif_stop_queue(ndev);
1943
1944         /* Disable interrupts by clearing the interrupt mask. */
1945         sh_eth_write(ndev, 0x0000, EESIPR);
1946
1947         /* Stop the chip's Tx and Rx processes. */
1948         sh_eth_write(ndev, 0, EDTRR);
1949         sh_eth_write(ndev, 0, EDRRR);
1950
1951         /* PHY Disconnect */
1952         if (mdp->phydev) {
1953                 phy_stop(mdp->phydev);
1954                 phy_disconnect(mdp->phydev);
1955         }
1956
1957         free_irq(ndev->irq, ndev);
1958
1959         /* Free all the skbuffs in the Rx queue. */
1960         sh_eth_ring_free(ndev);
1961
1962         /* free DMA buffer */
1963         sh_eth_free_dma_buffer(mdp);
1964
1965         pm_runtime_put_sync(&mdp->pdev->dev);
1966
1967         return 0;
1968 }
1969
1970 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1971 {
1972         struct sh_eth_private *mdp = netdev_priv(ndev);
1973
1974         pm_runtime_get_sync(&mdp->pdev->dev);
1975
1976         ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1977         sh_eth_write(ndev, 0, TROCR);   /* (write clear) */
1978         ndev->stats.collisions += sh_eth_read(ndev, CDCR);
1979         sh_eth_write(ndev, 0, CDCR);    /* (write clear) */
1980         ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1981         sh_eth_write(ndev, 0, LCCR);    /* (write clear) */
1982         if (sh_eth_is_gether(mdp)) {
1983                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1984                 sh_eth_write(ndev, 0, CERCR);   /* (write clear) */
1985                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1986                 sh_eth_write(ndev, 0, CEECR);   /* (write clear) */
1987         } else {
1988                 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1989                 sh_eth_write(ndev, 0, CNDCR);   /* (write clear) */
1990         }
1991         pm_runtime_put_sync(&mdp->pdev->dev);
1992
1993         return &ndev->stats;
1994 }
1995
1996 /* ioctl to device function */
1997 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1998                                 int cmd)
1999 {
2000         struct sh_eth_private *mdp = netdev_priv(ndev);
2001         struct phy_device *phydev = mdp->phydev;
2002
2003         if (!netif_running(ndev))
2004                 return -EINVAL;
2005
2006         if (!phydev)
2007                 return -ENODEV;
2008
2009         return phy_mii_ioctl(phydev, rq, cmd);
2010 }
2011
2012 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2013 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2014                                             int entry)
2015 {
2016         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2017 }
2018
2019 static u32 sh_eth_tsu_get_post_mask(int entry)
2020 {
2021         return 0x0f << (28 - ((entry % 8) * 4));
2022 }
2023
2024 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2025 {
2026         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2027 }
2028
2029 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2030                                              int entry)
2031 {
2032         struct sh_eth_private *mdp = netdev_priv(ndev);
2033         u32 tmp;
2034         void *reg_offset;
2035
2036         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2037         tmp = ioread32(reg_offset);
2038         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2039 }
2040
2041 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2042                                               int entry)
2043 {
2044         struct sh_eth_private *mdp = netdev_priv(ndev);
2045         u32 post_mask, ref_mask, tmp;
2046         void *reg_offset;
2047
2048         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2049         post_mask = sh_eth_tsu_get_post_mask(entry);
2050         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2051
2052         tmp = ioread32(reg_offset);
2053         iowrite32(tmp & ~post_mask, reg_offset);
2054
2055         /* If other port enables, the function returns "true" */
2056         return tmp & ref_mask;
2057 }
2058
2059 static int sh_eth_tsu_busy(struct net_device *ndev)
2060 {
2061         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2062         struct sh_eth_private *mdp = netdev_priv(ndev);
2063
2064         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2065                 udelay(10);
2066                 timeout--;
2067                 if (timeout <= 0) {
2068                         dev_err(&ndev->dev, "%s: timeout\n", __func__);
2069                         return -ETIMEDOUT;
2070                 }
2071         }
2072
2073         return 0;
2074 }
2075
2076 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2077                                   const u8 *addr)
2078 {
2079         u32 val;
2080
2081         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2082         iowrite32(val, reg);
2083         if (sh_eth_tsu_busy(ndev) < 0)
2084                 return -EBUSY;
2085
2086         val = addr[4] << 8 | addr[5];
2087         iowrite32(val, reg + 4);
2088         if (sh_eth_tsu_busy(ndev) < 0)
2089                 return -EBUSY;
2090
2091         return 0;
2092 }
2093
2094 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2095 {
2096         u32 val;
2097
2098         val = ioread32(reg);
2099         addr[0] = (val >> 24) & 0xff;
2100         addr[1] = (val >> 16) & 0xff;
2101         addr[2] = (val >> 8) & 0xff;
2102         addr[3] = val & 0xff;
2103         val = ioread32(reg + 4);
2104         addr[4] = (val >> 8) & 0xff;
2105         addr[5] = val & 0xff;
2106 }
2107
2108
2109 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2110 {
2111         struct sh_eth_private *mdp = netdev_priv(ndev);
2112         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2113         int i;
2114         u8 c_addr[ETH_ALEN];
2115
2116         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2117                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2118                 if (memcmp(addr, c_addr, ETH_ALEN) == 0)
2119                         return i;
2120         }
2121
2122         return -ENOENT;
2123 }
2124
2125 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2126 {
2127         u8 blank[ETH_ALEN];
2128         int entry;
2129
2130         memset(blank, 0, sizeof(blank));
2131         entry = sh_eth_tsu_find_entry(ndev, blank);
2132         return (entry < 0) ? -ENOMEM : entry;
2133 }
2134
2135 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2136                                               int entry)
2137 {
2138         struct sh_eth_private *mdp = netdev_priv(ndev);
2139         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2140         int ret;
2141         u8 blank[ETH_ALEN];
2142
2143         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2144                          ~(1 << (31 - entry)), TSU_TEN);
2145
2146         memset(blank, 0, sizeof(blank));
2147         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2148         if (ret < 0)
2149                 return ret;
2150         return 0;
2151 }
2152
2153 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2154 {
2155         struct sh_eth_private *mdp = netdev_priv(ndev);
2156         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2157         int i, ret;
2158
2159         if (!mdp->cd->tsu)
2160                 return 0;
2161
2162         i = sh_eth_tsu_find_entry(ndev, addr);
2163         if (i < 0) {
2164                 /* No entry found, create one */
2165                 i = sh_eth_tsu_find_empty(ndev);
2166                 if (i < 0)
2167                         return -ENOMEM;
2168                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2169                 if (ret < 0)
2170                         return ret;
2171
2172                 /* Enable the entry */
2173                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2174                                  (1 << (31 - i)), TSU_TEN);
2175         }
2176
2177         /* Entry found or created, enable POST */
2178         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2179
2180         return 0;
2181 }
2182
2183 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2184 {
2185         struct sh_eth_private *mdp = netdev_priv(ndev);
2186         int i, ret;
2187
2188         if (!mdp->cd->tsu)
2189                 return 0;
2190
2191         i = sh_eth_tsu_find_entry(ndev, addr);
2192         if (i) {
2193                 /* Entry found */
2194                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2195                         goto done;
2196
2197                 /* Disable the entry if both ports was disabled */
2198                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2199                 if (ret < 0)
2200                         return ret;
2201         }
2202 done:
2203         return 0;
2204 }
2205
2206 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2207 {
2208         struct sh_eth_private *mdp = netdev_priv(ndev);
2209         int i, ret;
2210
2211         if (unlikely(!mdp->cd->tsu))
2212                 return 0;
2213
2214         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2215                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2216                         continue;
2217
2218                 /* Disable the entry if both ports was disabled */
2219                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2220                 if (ret < 0)
2221                         return ret;
2222         }
2223
2224         return 0;
2225 }
2226
2227 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2228 {
2229         struct sh_eth_private *mdp = netdev_priv(ndev);
2230         u8 addr[ETH_ALEN];
2231         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2232         int i;
2233
2234         if (unlikely(!mdp->cd->tsu))
2235                 return;
2236
2237         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2238                 sh_eth_tsu_read_entry(reg_offset, addr);
2239                 if (is_multicast_ether_addr(addr))
2240                         sh_eth_tsu_del_entry(ndev, addr);
2241         }
2242 }
2243
2244 /* Multicast reception directions set */
2245 static void sh_eth_set_multicast_list(struct net_device *ndev)
2246 {
2247         struct sh_eth_private *mdp = netdev_priv(ndev);
2248         u32 ecmr_bits;
2249         int mcast_all = 0;
2250         unsigned long flags;
2251
2252         spin_lock_irqsave(&mdp->lock, flags);
2253         /*
2254          * Initial condition is MCT = 1, PRM = 0.
2255          * Depending on ndev->flags, set PRM or clear MCT
2256          */
2257         ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
2258
2259         if (!(ndev->flags & IFF_MULTICAST)) {
2260                 sh_eth_tsu_purge_mcast(ndev);
2261                 mcast_all = 1;
2262         }
2263         if (ndev->flags & IFF_ALLMULTI) {
2264                 sh_eth_tsu_purge_mcast(ndev);
2265                 ecmr_bits &= ~ECMR_MCT;
2266                 mcast_all = 1;
2267         }
2268
2269         if (ndev->flags & IFF_PROMISC) {
2270                 sh_eth_tsu_purge_all(ndev);
2271                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2272         } else if (mdp->cd->tsu) {
2273                 struct netdev_hw_addr *ha;
2274                 netdev_for_each_mc_addr(ha, ndev) {
2275                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2276                                 continue;
2277
2278                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2279                                 if (!mcast_all) {
2280                                         sh_eth_tsu_purge_mcast(ndev);
2281                                         ecmr_bits &= ~ECMR_MCT;
2282                                         mcast_all = 1;
2283                                 }
2284                         }
2285                 }
2286         } else {
2287                 /* Normal, unicast/broadcast-only mode. */
2288                 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
2289         }
2290
2291         /* update the ethernet mode */
2292         sh_eth_write(ndev, ecmr_bits, ECMR);
2293
2294         spin_unlock_irqrestore(&mdp->lock, flags);
2295 }
2296
2297 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2298 {
2299         if (!mdp->port)
2300                 return TSU_VTAG0;
2301         else
2302                 return TSU_VTAG1;
2303 }
2304
2305 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2306                                   __be16 proto, u16 vid)
2307 {
2308         struct sh_eth_private *mdp = netdev_priv(ndev);
2309         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2310
2311         if (unlikely(!mdp->cd->tsu))
2312                 return -EPERM;
2313
2314         /* No filtering if vid = 0 */
2315         if (!vid)
2316                 return 0;
2317
2318         mdp->vlan_num_ids++;
2319
2320         /*
2321          * The controller has one VLAN tag HW filter. So, if the filter is
2322          * already enabled, the driver disables it and the filte
2323          */
2324         if (mdp->vlan_num_ids > 1) {
2325                 /* disable VLAN filter */
2326                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2327                 return 0;
2328         }
2329
2330         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2331                          vtag_reg_index);
2332
2333         return 0;
2334 }
2335
2336 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2337                                    __be16 proto, u16 vid)
2338 {
2339         struct sh_eth_private *mdp = netdev_priv(ndev);
2340         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2341
2342         if (unlikely(!mdp->cd->tsu))
2343                 return -EPERM;
2344
2345         /* No filtering if vid = 0 */
2346         if (!vid)
2347                 return 0;
2348
2349         mdp->vlan_num_ids--;
2350         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2351
2352         return 0;
2353 }
2354
2355 /* SuperH's TSU register init function */
2356 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2357 {
2358         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2359         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2360         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2361         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2362         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2363         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2364         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2365         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2366         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2367         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2368         if (sh_eth_is_gether(mdp)) {
2369                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2370                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2371         } else {
2372                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2373                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2374         }
2375         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2376         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2377         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2378         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2379         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2380         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2381         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2382 }
2383
2384 /* MDIO bus release function */
2385 static int sh_mdio_release(struct net_device *ndev)
2386 {
2387         struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
2388
2389         /* unregister mdio bus */
2390         mdiobus_unregister(bus);
2391
2392         /* remove mdio bus info from net_device */
2393         dev_set_drvdata(&ndev->dev, NULL);
2394
2395         /* free bitbang info */
2396         free_mdio_bitbang(bus);
2397
2398         return 0;
2399 }
2400
2401 /* MDIO bus init function */
2402 static int sh_mdio_init(struct net_device *ndev, int id,
2403                         struct sh_eth_plat_data *pd)
2404 {
2405         int ret, i;
2406         struct bb_info *bitbang;
2407         struct sh_eth_private *mdp = netdev_priv(ndev);
2408
2409         /* create bit control struct for PHY */
2410         bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info),
2411                                GFP_KERNEL);
2412         if (!bitbang) {
2413                 ret = -ENOMEM;
2414                 goto out;
2415         }
2416
2417         /* bitbang init */
2418         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2419         bitbang->set_gate = pd->set_mdio_gate;
2420         bitbang->mdi_msk = PIR_MDI;
2421         bitbang->mdo_msk = PIR_MDO;
2422         bitbang->mmd_msk = PIR_MMD;
2423         bitbang->mdc_msk = PIR_MDC;
2424         bitbang->ctrl.ops = &bb_ops;
2425
2426         /* MII controller setting */
2427         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2428         if (!mdp->mii_bus) {
2429                 ret = -ENOMEM;
2430                 goto out;
2431         }
2432
2433         /* Hook up MII support for ethtool */
2434         mdp->mii_bus->name = "sh_mii";
2435         mdp->mii_bus->parent = &ndev->dev;
2436         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2437                 mdp->pdev->name, id);
2438
2439         /* PHY IRQ */
2440         mdp->mii_bus->irq = devm_kzalloc(&ndev->dev,
2441                                          sizeof(int) * PHY_MAX_ADDR,
2442                                          GFP_KERNEL);
2443         if (!mdp->mii_bus->irq) {
2444                 ret = -ENOMEM;
2445                 goto out_free_bus;
2446         }
2447
2448         for (i = 0; i < PHY_MAX_ADDR; i++)
2449                 mdp->mii_bus->irq[i] = PHY_POLL;
2450
2451         /* register mdio bus */
2452         ret = mdiobus_register(mdp->mii_bus);
2453         if (ret)
2454                 goto out_free_bus;
2455
2456         dev_set_drvdata(&ndev->dev, mdp->mii_bus);
2457
2458         return 0;
2459
2460 out_free_bus:
2461         free_mdio_bitbang(mdp->mii_bus);
2462
2463 out:
2464         return ret;
2465 }
2466
2467 static const u16 *sh_eth_get_register_offset(int register_type)
2468 {
2469         const u16 *reg_offset = NULL;
2470
2471         switch (register_type) {
2472         case SH_ETH_REG_GIGABIT:
2473                 reg_offset = sh_eth_offset_gigabit;
2474                 break;
2475         case SH_ETH_REG_FAST_RCAR:
2476                 reg_offset = sh_eth_offset_fast_rcar;
2477                 break;
2478         case SH_ETH_REG_FAST_SH4:
2479                 reg_offset = sh_eth_offset_fast_sh4;
2480                 break;
2481         case SH_ETH_REG_FAST_SH3_SH2:
2482                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2483                 break;
2484         default:
2485                 pr_err("Unknown register type (%d)\n", register_type);
2486                 break;
2487         }
2488
2489         return reg_offset;
2490 }
2491
2492 static struct net_device_ops sh_eth_netdev_ops = {
2493         .ndo_open               = sh_eth_open,
2494         .ndo_stop               = sh_eth_close,
2495         .ndo_start_xmit         = sh_eth_start_xmit,
2496         .ndo_get_stats          = sh_eth_get_stats,
2497         .ndo_tx_timeout         = sh_eth_tx_timeout,
2498         .ndo_do_ioctl           = sh_eth_do_ioctl,
2499         .ndo_validate_addr      = eth_validate_addr,
2500         .ndo_set_mac_address    = eth_mac_addr,
2501         .ndo_change_mtu         = eth_change_mtu,
2502 };
2503
2504 static int sh_eth_drv_probe(struct platform_device *pdev)
2505 {
2506         int ret, devno = 0;
2507         struct resource *res;
2508         struct net_device *ndev = NULL;
2509         struct sh_eth_private *mdp = NULL;
2510         struct sh_eth_plat_data *pd = pdev->dev.platform_data;
2511         const struct platform_device_id *id = platform_get_device_id(pdev);
2512
2513         /* get base addr */
2514         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2515         if (unlikely(res == NULL)) {
2516                 dev_err(&pdev->dev, "invalid resource\n");
2517                 ret = -EINVAL;
2518                 goto out;
2519         }
2520
2521         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2522         if (!ndev) {
2523                 ret = -ENOMEM;
2524                 goto out;
2525         }
2526
2527         /* The sh Ether-specific entries in the device structure. */
2528         ndev->base_addr = res->start;
2529         devno = pdev->id;
2530         if (devno < 0)
2531                 devno = 0;
2532
2533         ndev->dma = -1;
2534         ret = platform_get_irq(pdev, 0);
2535         if (ret < 0) {
2536                 ret = -ENODEV;
2537                 goto out_release;
2538         }
2539         ndev->irq = ret;
2540
2541         SET_NETDEV_DEV(ndev, &pdev->dev);
2542
2543         /* Fill in the fields of the device structure with ethernet values. */
2544         ether_setup(ndev);
2545
2546         mdp = netdev_priv(ndev);
2547         mdp->num_tx_ring = TX_RING_SIZE;
2548         mdp->num_rx_ring = RX_RING_SIZE;
2549         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2550         if (IS_ERR(mdp->addr)) {
2551                 ret = PTR_ERR(mdp->addr);
2552                 goto out_release;
2553         }
2554
2555         spin_lock_init(&mdp->lock);
2556         mdp->pdev = pdev;
2557         pm_runtime_enable(&pdev->dev);
2558         pm_runtime_resume(&pdev->dev);
2559
2560         /* get PHY ID */
2561         mdp->phy_id = pd->phy;
2562         mdp->phy_interface = pd->phy_interface;
2563         /* EDMAC endian */
2564         mdp->edmac_endian = pd->edmac_endian;
2565         mdp->no_ether_link = pd->no_ether_link;
2566         mdp->ether_link_active_low = pd->ether_link_active_low;
2567         mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
2568
2569         /* set cpu data */
2570         mdp->cd = &sh_eth_my_cpu_data;
2571         if (id->driver_data)
2572                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2573         sh_eth_set_default_cpu_data(mdp->cd);
2574
2575         /* set function */
2576         if (mdp->cd->tsu) {
2577                 sh_eth_netdev_ops.ndo_set_rx_mode = sh_eth_set_multicast_list;
2578                 sh_eth_netdev_ops.ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid;
2579                 sh_eth_netdev_ops.ndo_vlan_rx_kill_vid =
2580                         sh_eth_vlan_rx_kill_vid;
2581         }
2582
2583         ndev->netdev_ops = &sh_eth_netdev_ops;
2584         SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
2585         ndev->watchdog_timeo = TX_TIMEOUT;
2586
2587         /* debug message level */
2588         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2589
2590         /* read and set MAC address */
2591         read_mac_address(ndev, pd->mac_addr);
2592         if (!is_valid_ether_addr(ndev->dev_addr)) {
2593                 dev_warn(&pdev->dev,
2594                          "no valid MAC address supplied, using a random one.\n");
2595                 eth_hw_addr_random(ndev);
2596         }
2597
2598         /* ioremap the TSU registers */
2599         if (mdp->cd->tsu) {
2600                 struct resource *rtsu;
2601                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2602                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2603                 if (IS_ERR(mdp->tsu_addr)) {
2604                         ret = PTR_ERR(mdp->tsu_addr);
2605                         goto out_release;
2606                 }
2607                 mdp->port = devno % 2;
2608                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2609         }
2610
2611         /* initialize first or needed device */
2612         if (!devno || pd->needs_init) {
2613                 if (mdp->cd->chip_reset)
2614                         mdp->cd->chip_reset(ndev);
2615
2616                 if (mdp->cd->tsu) {
2617                         /* TSU init (Init only)*/
2618                         sh_eth_tsu_init(mdp);
2619                 }
2620         }
2621
2622         /* network device register */
2623         ret = register_netdev(ndev);
2624         if (ret)
2625                 goto out_release;
2626
2627         /* mdio bus init */
2628         ret = sh_mdio_init(ndev, pdev->id, pd);
2629         if (ret)
2630                 goto out_unregister;
2631
2632         /* print device information */
2633         pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
2634                (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2635
2636         platform_set_drvdata(pdev, ndev);
2637
2638         return ret;
2639
2640 out_unregister:
2641         unregister_netdev(ndev);
2642
2643 out_release:
2644         /* net_dev free */
2645         if (ndev)
2646                 free_netdev(ndev);
2647
2648 out:
2649         return ret;
2650 }
2651
2652 static int sh_eth_drv_remove(struct platform_device *pdev)
2653 {
2654         struct net_device *ndev = platform_get_drvdata(pdev);
2655
2656         sh_mdio_release(ndev);
2657         unregister_netdev(ndev);
2658         pm_runtime_disable(&pdev->dev);
2659         free_netdev(ndev);
2660
2661         return 0;
2662 }
2663
2664 #ifdef CONFIG_PM
2665 static int sh_eth_runtime_nop(struct device *dev)
2666 {
2667         /*
2668          * Runtime PM callback shared between ->runtime_suspend()
2669          * and ->runtime_resume(). Simply returns success.
2670          *
2671          * This driver re-initializes all registers after
2672          * pm_runtime_get_sync() anyway so there is no need
2673          * to save and restore registers here.
2674          */
2675         return 0;
2676 }
2677
2678 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2679         .runtime_suspend = sh_eth_runtime_nop,
2680         .runtime_resume = sh_eth_runtime_nop,
2681 };
2682 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2683 #else
2684 #define SH_ETH_PM_OPS NULL
2685 #endif
2686
2687 static struct platform_device_id sh_eth_id_table[] = {
2688         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2689         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2690         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2691         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2692         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2693         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2694         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2695         { CARDNAME },
2696         { }
2697 };
2698 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
2699
2700 static struct platform_driver sh_eth_driver = {
2701         .probe = sh_eth_drv_probe,
2702         .remove = sh_eth_drv_remove,
2703         .id_table = sh_eth_id_table,
2704         .driver = {
2705                    .name = CARDNAME,
2706                    .pm = SH_ETH_PM_OPS,
2707         },
2708 };
2709
2710 module_platform_driver(sh_eth_driver);
2711
2712 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
2713 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
2714 MODULE_LICENSE("GPL v2");