1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2011 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
14 #include <linux/net_tstamp.h>
15 #include <linux/i2c-algo-bit.h>
16 #include "net_driver.h"
21 * Falcon hardware control
25 EFX_REV_FALCON_A0 = 0,
26 EFX_REV_FALCON_A1 = 1,
27 EFX_REV_FALCON_B0 = 2,
31 static inline int efx_nic_rev(struct efx_nic *efx)
33 return efx->type->revision;
36 extern u32 efx_farch_fpga_ver(struct efx_nic *efx);
38 /* NIC has two interlinked PCI functions for the same port. */
39 static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
41 return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
44 /* Read the current event from the event queue */
45 static inline efx_qword_t *efx_event(struct efx_channel *channel,
48 return ((efx_qword_t *) (channel->eventq.buf.addr)) +
49 (index & channel->eventq_mask);
52 /* See if an event is present
54 * We check both the high and low dword of the event for all ones. We
55 * wrote all ones when we cleared the event, and no valid event can
56 * have all ones in either its high or low dwords. This approach is
57 * robust against reordering.
59 * Note that using a single 64-bit comparison is incorrect; even
60 * though the CPU read will be atomic, the DMA write may not be.
62 static inline int efx_event_present(efx_qword_t *event)
64 return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
65 EFX_DWORD_IS_ALL_ONES(event->dword[1]));
68 /* Returns a pointer to the specified transmit descriptor in the TX
69 * descriptor queue belonging to the specified channel.
71 static inline efx_qword_t *
72 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
74 return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
77 /* Decide whether to push a TX descriptor to the NIC vs merely writing
78 * the doorbell. This can reduce latency when we are adding a single
79 * descriptor to an empty queue, but is otherwise pointless. Further,
80 * Falcon and Siena have hardware bugs (SF bug 33851) that may be
81 * triggered if we don't check this.
83 static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
84 unsigned int write_count)
86 unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
88 if (empty_read_count == 0)
91 tx_queue->empty_read_count = 0;
92 return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0
93 && tx_queue->write_count - write_count == 1;
96 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
97 static inline efx_qword_t *
98 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
100 return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
105 PHY_TYPE_TXC43128 = 1,
106 PHY_TYPE_88E1111 = 2,
107 PHY_TYPE_SFX7101 = 3,
108 PHY_TYPE_QT2022C2 = 4,
110 PHY_TYPE_SFT9001A = 8,
111 PHY_TYPE_QT2025C = 9,
112 PHY_TYPE_SFT9001B = 10,
115 #define FALCON_XMAC_LOOPBACKS \
116 ((1 << LOOPBACK_XGMII) | \
117 (1 << LOOPBACK_XGXS) | \
118 (1 << LOOPBACK_XAUI))
120 #define FALCON_GMAC_LOOPBACKS \
123 /* Alignment of PCIe DMA boundaries (4KB) */
124 #define EFX_PAGE_SIZE 4096
125 /* Size and alignment of buffer table entries (same) */
126 #define EFX_BUF_SIZE EFX_PAGE_SIZE
129 * struct falcon_board_type - board operations and type information
130 * @id: Board type id, as found in NVRAM
131 * @init: Allocate resources and initialise peripheral hardware
132 * @init_phy: Do board-specific PHY initialisation
133 * @fini: Shut down hardware and free resources
134 * @set_id_led: Set state of identifying LED or revert to automatic function
135 * @monitor: Board-specific health check function
137 struct falcon_board_type {
139 int (*init) (struct efx_nic *nic);
140 void (*init_phy) (struct efx_nic *efx);
141 void (*fini) (struct efx_nic *nic);
142 void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
143 int (*monitor) (struct efx_nic *nic);
147 * struct falcon_board - board information
148 * @type: Type of board
149 * @major: Major rev. ('A', 'B' ...)
150 * @minor: Minor rev. (0, 1, ...)
151 * @i2c_adap: I2C adapter for on-board peripherals
152 * @i2c_data: Data for bit-banging algorithm
153 * @hwmon_client: I2C client for hardware monitor
154 * @ioexp_client: I2C client for power/port control
156 struct falcon_board {
157 const struct falcon_board_type *type;
160 struct i2c_adapter i2c_adap;
161 struct i2c_algo_bit_data i2c_data;
162 struct i2c_client *hwmon_client, *ioexp_client;
166 * struct falcon_spi_device - a Falcon SPI (Serial Peripheral Interface) device
167 * @device_id: Controller's id for the device
168 * @size: Size (in bytes)
169 * @addr_len: Number of address bytes in read/write commands
170 * @munge_address: Flag whether addresses should be munged.
171 * Some devices with 9-bit addresses (e.g. AT25040A EEPROM)
172 * use bit 3 of the command byte as address bit A8, rather
173 * than having a two-byte address. If this flag is set, then
174 * commands should be munged in this way.
175 * @erase_command: Erase command (or 0 if sector erase not needed).
176 * @erase_size: Erase sector size (in bytes)
177 * Erase commands affect sectors with this size and alignment.
178 * This must be a power of two.
179 * @block_size: Write block size (in bytes).
180 * Write commands are limited to blocks with this size and alignment.
182 struct falcon_spi_device {
185 unsigned int addr_len;
186 unsigned int munge_address:1;
188 unsigned int erase_size;
189 unsigned int block_size;
192 static inline bool falcon_spi_present(const struct falcon_spi_device *spi)
194 return spi->size != 0;
198 * struct falcon_nic_data - Falcon NIC state
199 * @pci_dev2: Secondary function of Falcon A
200 * @board: Board state and functions
201 * @stats_disable_count: Nest count for disabling statistics fetches
202 * @stats_pending: Is there a pending DMA of MAC statistics.
203 * @stats_timer: A timer for regularly fetching MAC statistics.
204 * @stats_dma_done: Pointer to the flag which indicates DMA completion.
205 * @spi_flash: SPI flash device
206 * @spi_eeprom: SPI EEPROM device
207 * @spi_lock: SPI bus lock
208 * @mdio_lock: MDIO bus lock
209 * @xmac_poll_required: XMAC link state needs polling
211 struct falcon_nic_data {
212 struct pci_dev *pci_dev2;
213 struct falcon_board board;
214 unsigned int stats_disable_count;
216 struct timer_list stats_timer;
218 struct falcon_spi_device spi_flash;
219 struct falcon_spi_device spi_eeprom;
220 struct mutex spi_lock;
221 struct mutex mdio_lock;
222 bool xmac_poll_required;
225 static inline struct falcon_board *falcon_board(struct efx_nic *efx)
227 struct falcon_nic_data *data = efx->nic_data;
232 * struct siena_nic_data - Siena NIC state
233 * @wol_filter_id: Wake-on-LAN packet filter id
235 struct siena_nic_data {
240 * On the SFC9000 family each port is associated with 1 PCI physical
241 * function (PF) handled by sfc and a configurable number of virtual
242 * functions (VFs) that may be handled by some other driver, often in
243 * a VM guest. The queue pointer registers are mapped in both PF and
244 * VF BARs such that an 8K region provides access to a single RX, TX
245 * and event queue (collectively a Virtual Interface, VI or VNIC).
247 * The PF has access to all 1024 VIs while VFs are mapped to VIs
248 * according to VI_BASE and VI_SCALE: VF i has access to VIs numbered
249 * in range [VI_BASE + i << VI_SCALE, VI_BASE + i + 1 << VI_SCALE).
250 * The number of VIs and the VI_SCALE value are configurable but must
251 * be established at boot time by firmware.
254 /* Maximum VI_SCALE parameter supported by Siena */
255 #define EFX_VI_SCALE_MAX 6
256 /* Base VI to use for SR-IOV. Must be aligned to (1 << EFX_VI_SCALE_MAX),
257 * so this is the smallest allowed value. */
258 #define EFX_VI_BASE 128U
259 /* Maximum number of VFs allowed */
260 #define EFX_VF_COUNT_MAX 127
261 /* Limit EVQs on VFs to be only 8k to reduce buffer table reservation */
262 #define EFX_MAX_VF_EVQ_SIZE 8192UL
263 /* The number of buffer table entries reserved for each VI on a VF */
264 #define EFX_VF_BUFTBL_PER_VI \
265 ((EFX_MAX_VF_EVQ_SIZE + 2 * EFX_MAX_DMAQ_SIZE) * \
266 sizeof(efx_qword_t) / EFX_BUF_SIZE)
268 #ifdef CONFIG_SFC_SRIOV
270 static inline bool efx_sriov_wanted(struct efx_nic *efx)
272 return efx->vf_count != 0;
274 static inline bool efx_sriov_enabled(struct efx_nic *efx)
276 return efx->vf_init_count != 0;
278 static inline unsigned int efx_vf_size(struct efx_nic *efx)
280 return 1 << efx->vi_scale;
283 extern int efx_init_sriov(void);
284 extern void efx_sriov_probe(struct efx_nic *efx);
285 extern int efx_sriov_init(struct efx_nic *efx);
286 extern void efx_sriov_mac_address_changed(struct efx_nic *efx);
287 extern void efx_sriov_tx_flush_done(struct efx_nic *efx, efx_qword_t *event);
288 extern void efx_sriov_rx_flush_done(struct efx_nic *efx, efx_qword_t *event);
289 extern void efx_sriov_event(struct efx_channel *channel, efx_qword_t *event);
290 extern void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq);
291 extern void efx_sriov_flr(struct efx_nic *efx, unsigned flr);
292 extern void efx_sriov_reset(struct efx_nic *efx);
293 extern void efx_sriov_fini(struct efx_nic *efx);
294 extern void efx_fini_sriov(void);
298 static inline bool efx_sriov_wanted(struct efx_nic *efx) { return false; }
299 static inline bool efx_sriov_enabled(struct efx_nic *efx) { return false; }
300 static inline unsigned int efx_vf_size(struct efx_nic *efx) { return 0; }
302 static inline int efx_init_sriov(void) { return 0; }
303 static inline void efx_sriov_probe(struct efx_nic *efx) {}
304 static inline int efx_sriov_init(struct efx_nic *efx) { return -EOPNOTSUPP; }
305 static inline void efx_sriov_mac_address_changed(struct efx_nic *efx) {}
306 static inline void efx_sriov_tx_flush_done(struct efx_nic *efx,
307 efx_qword_t *event) {}
308 static inline void efx_sriov_rx_flush_done(struct efx_nic *efx,
309 efx_qword_t *event) {}
310 static inline void efx_sriov_event(struct efx_channel *channel,
311 efx_qword_t *event) {}
312 static inline void efx_sriov_desc_fetch_err(struct efx_nic *efx, unsigned dmaq) {}
313 static inline void efx_sriov_flr(struct efx_nic *efx, unsigned flr) {}
314 static inline void efx_sriov_reset(struct efx_nic *efx) {}
315 static inline void efx_sriov_fini(struct efx_nic *efx) {}
316 static inline void efx_fini_sriov(void) {}
320 extern int efx_sriov_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
321 extern int efx_sriov_set_vf_vlan(struct net_device *dev, int vf,
323 extern int efx_sriov_get_vf_config(struct net_device *dev, int vf,
324 struct ifla_vf_info *ivf);
325 extern int efx_sriov_set_vf_spoofchk(struct net_device *net_dev, int vf,
328 struct ethtool_ts_info;
329 extern void efx_ptp_probe(struct efx_nic *efx);
330 extern int efx_ptp_ioctl(struct efx_nic *efx, struct ifreq *ifr, int cmd);
331 extern void efx_ptp_get_ts_info(struct efx_nic *efx,
332 struct ethtool_ts_info *ts_info);
333 extern bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
334 extern int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb);
335 extern void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev);
337 extern const struct efx_nic_type falcon_a1_nic_type;
338 extern const struct efx_nic_type falcon_b0_nic_type;
339 extern const struct efx_nic_type siena_a0_nic_type;
341 /**************************************************************************
345 **************************************************************************
348 extern int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
351 static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
353 return tx_queue->efx->type->tx_probe(tx_queue);
355 static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
357 tx_queue->efx->type->tx_init(tx_queue);
359 static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
361 tx_queue->efx->type->tx_remove(tx_queue);
363 static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
365 tx_queue->efx->type->tx_write(tx_queue);
369 static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
371 return rx_queue->efx->type->rx_probe(rx_queue);
373 static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
375 rx_queue->efx->type->rx_init(rx_queue);
377 static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
379 rx_queue->efx->type->rx_remove(rx_queue);
381 static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
383 rx_queue->efx->type->rx_write(rx_queue);
385 static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
387 rx_queue->efx->type->rx_defer_refill(rx_queue);
390 /* Event data path */
391 static inline int efx_nic_probe_eventq(struct efx_channel *channel)
393 return channel->efx->type->ev_probe(channel);
395 static inline void efx_nic_init_eventq(struct efx_channel *channel)
397 channel->efx->type->ev_init(channel);
399 static inline void efx_nic_fini_eventq(struct efx_channel *channel)
401 channel->efx->type->ev_fini(channel);
403 static inline void efx_nic_remove_eventq(struct efx_channel *channel)
405 channel->efx->type->ev_remove(channel);
408 efx_nic_process_eventq(struct efx_channel *channel, int quota)
410 return channel->efx->type->ev_process(channel, quota);
412 static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
414 channel->efx->type->ev_read_ack(channel);
416 extern void efx_nic_event_test_start(struct efx_channel *channel);
418 /* Falcon/Siena queue operations */
419 extern int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
420 extern void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
421 extern void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
422 extern void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
423 extern void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
424 extern int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
425 extern void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
426 extern void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
427 extern void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
428 extern void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
429 extern void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
430 extern int efx_farch_ev_probe(struct efx_channel *channel);
431 extern void efx_farch_ev_init(struct efx_channel *channel);
432 extern void efx_farch_ev_fini(struct efx_channel *channel);
433 extern void efx_farch_ev_remove(struct efx_channel *channel);
434 extern int efx_farch_ev_process(struct efx_channel *channel, int quota);
435 extern void efx_farch_ev_read_ack(struct efx_channel *channel);
436 extern void efx_farch_ev_test_generate(struct efx_channel *channel);
438 /* Falcon/Siena filter operations */
439 extern int efx_farch_filter_table_probe(struct efx_nic *efx);
440 extern void efx_farch_filter_table_restore(struct efx_nic *efx);
441 extern void efx_farch_filter_table_remove(struct efx_nic *efx);
442 extern void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);
443 extern s32 efx_farch_filter_insert(struct efx_nic *efx,
444 struct efx_filter_spec *spec, bool replace);
445 extern int efx_farch_filter_remove_safe(struct efx_nic *efx,
446 enum efx_filter_priority priority,
448 extern int efx_farch_filter_get_safe(struct efx_nic *efx,
449 enum efx_filter_priority priority,
450 u32 filter_id, struct efx_filter_spec *);
451 extern void efx_farch_filter_clear_rx(struct efx_nic *efx,
452 enum efx_filter_priority priority);
453 extern u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
454 enum efx_filter_priority priority);
455 extern u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);
456 extern s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
457 enum efx_filter_priority priority,
459 #ifdef CONFIG_RFS_ACCEL
460 extern s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
461 struct efx_filter_spec *spec);
462 extern bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
465 extern void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);
467 extern bool efx_nic_event_present(struct efx_channel *channel);
469 /* Some statistics are computed as A - B where A and B each increase
470 * linearly with some hardware counter(s) and the counters are read
471 * asynchronously. If the counters contributing to B are always read
472 * after those contributing to A, the computed value may be lower than
473 * the true value by some variable amount, and may decrease between
474 * subsequent computations.
476 * We should never allow statistics to decrease or to exceed the true
477 * value. Since the computed value will never be greater than the
478 * true value, we can achieve this by only storing the computed value
481 static inline void efx_update_diff_stat(u64 *stat, u64 diff)
483 if ((s64)(diff - *stat) > 0)
488 extern int efx_nic_init_interrupt(struct efx_nic *efx);
489 extern void efx_nic_irq_test_start(struct efx_nic *efx);
490 extern void efx_nic_fini_interrupt(struct efx_nic *efx);
492 /* Falcon/Siena interrupts */
493 extern void efx_farch_irq_enable_master(struct efx_nic *efx);
494 extern void efx_farch_irq_test_generate(struct efx_nic *efx);
495 extern void efx_farch_irq_disable_master(struct efx_nic *efx);
496 extern irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
497 extern irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
498 extern irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
500 static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
502 return ACCESS_ONCE(channel->event_test_cpu);
504 static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
506 return ACCESS_ONCE(efx->last_irq_cpu);
509 /* Global Resources */
510 extern int efx_nic_flush_queues(struct efx_nic *efx);
511 extern void siena_prepare_flush(struct efx_nic *efx);
512 extern int efx_farch_fini_dmaq(struct efx_nic *efx);
513 extern void siena_finish_flush(struct efx_nic *efx);
514 extern void falcon_start_nic_stats(struct efx_nic *efx);
515 extern void falcon_stop_nic_stats(struct efx_nic *efx);
516 extern int falcon_reset_xaui(struct efx_nic *efx);
517 extern void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
518 extern void efx_farch_init_common(struct efx_nic *efx);
519 static inline void efx_nic_push_rx_indir_table(struct efx_nic *efx)
521 efx->type->rx_push_indir_table(efx);
523 extern void efx_farch_rx_push_indir_table(struct efx_nic *efx);
525 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
526 unsigned int len, gfp_t gfp_flags);
527 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
530 struct efx_farch_register_test {
534 extern int efx_farch_test_registers(struct efx_nic *efx,
535 const struct efx_farch_register_test *regs,
538 extern size_t efx_nic_get_regs_len(struct efx_nic *efx);
539 extern void efx_nic_get_regs(struct efx_nic *efx, void *buf);
541 #define EFX_MAX_FLUSH_TIME 5000
543 extern void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
546 #endif /* EFX_NIC_H */