drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c

   1 /**
   2  * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
   3  *
   4  * Copyright (C) 2014 Chen-Zhi (Roger Chen)
   5  *
   6  * Chen-Zhi (Roger Chen)  <roger.chen@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/stmmac.h>
  20 #include <linux/bitops.h>
  21 #include <linux/clk.h>
  22 #include <linux/phy.h>
  23 #include <linux/of_net.h>
  24 #include <linux/gpio.h>
  25 #include <linux/module.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/delay.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include "stmmac_platform.h"
  36
  37 struct rk_priv_data;
  38 struct rk_gmac_ops {
  39         void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
  40                              int tx_delay, int rx_delay);
  41         void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
  42         void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  43         void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
  44 };
  45
  46 struct rk_priv_data {
  47         struct platform_device *pdev;
  48         int phy_iface;
  49         struct regulator *regulator;
  50         bool suspended;
  51         const struct rk_gmac_ops *ops;
  52
  53         bool clk_enabled;
  54         bool clock_input;
  55
  56         struct clk *clk_mac;
  57         struct clk *gmac_clkin;
  58         struct clk *mac_clk_rx;
  59         struct clk *mac_clk_tx;
  60         struct clk *clk_mac_ref;
  61         struct clk *clk_mac_refout;
  62         struct clk *aclk_mac;
  63         struct clk *pclk_mac;
  64
  65         int tx_delay;
  66         int rx_delay;
  67
  68         struct regmap *grf;
  69 };
  70
  71 #define HIWORD_UPDATE(val, mask, shift) \
  72                 ((val) << (shift) | (mask) << ((shift) + 16))
  73
  74 #define GRF_BIT(nr)     (BIT(nr) | BIT(nr+16))
  75 #define GRF_CLR_BIT(nr) (BIT(nr+16))
  76
  77 #define DELAY_ENABLE(soc, tx, rx) \
  78         (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
  79          ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
  80
  81 #define RK3228_GRF_MAC_CON0     0x0900
  82 #define RK3228_GRF_MAC_CON1     0x0904
  83
  84 /* RK3228_GRF_MAC_CON0 */
  85 #define RK3228_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
  86 #define RK3228_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
  87
  88 /* RK3228_GRF_MAC_CON1 */
  89 #define RK3228_GMAC_PHY_INTF_SEL_RGMII  \
  90                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
  91 #define RK3228_GMAC_PHY_INTF_SEL_RMII   \
  92                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
  93 #define RK3228_GMAC_FLOW_CTRL           GRF_BIT(3)
  94 #define RK3228_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
  95 #define RK3228_GMAC_SPEED_10M           GRF_CLR_BIT(2)
  96 #define RK3228_GMAC_SPEED_100M          GRF_BIT(2)
  97 #define RK3228_GMAC_RMII_CLK_25M        GRF_BIT(7)
  98 #define RK3228_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
  99 #define RK3228_GMAC_CLK_125M            (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
 100 #define RK3228_GMAC_CLK_25M             (GRF_BIT(8) | GRF_BIT(9))
 101 #define RK3228_GMAC_CLK_2_5M            (GRF_CLR_BIT(8) | GRF_BIT(9))
 102 #define RK3228_GMAC_RMII_MODE           GRF_BIT(10)
 103 #define RK3228_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(10)
 104 #define RK3228_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 105 #define RK3228_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 106 #define RK3228_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 107 #define RK3228_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(1)
 108
 109 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
 110                                 int tx_delay, int rx_delay)
 111 {
 112         struct device *dev = &bsp_priv->pdev->dev;
 113
 114         if (IS_ERR(bsp_priv->grf)) {
 115                 dev_err(dev, "Missing rockchip,grf property\n");
 116                 return;
 117         }
 118
 119         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 120                      RK3228_GMAC_PHY_INTF_SEL_RGMII |
 121                      RK3228_GMAC_RMII_MODE_CLR |
 122                      DELAY_ENABLE(RK3228, tx_delay, rx_delay));
 123
 124         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
 125                      RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
 126                      RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
 127 }
 128
 129 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
 130 {
 131         struct device *dev = &bsp_priv->pdev->dev;
 132
 133         if (IS_ERR(bsp_priv->grf)) {
 134                 dev_err(dev, "Missing rockchip,grf property\n");
 135                 return;
 136         }
 137
 138         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 139                      RK3228_GMAC_PHY_INTF_SEL_RMII |
 140                      RK3228_GMAC_RMII_MODE);
 141
 142         /* set MAC to RMII mode */
 143         regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
 144 }
 145
 146 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 147 {
 148         struct device *dev = &bsp_priv->pdev->dev;
 149
 150         if (IS_ERR(bsp_priv->grf)) {
 151                 dev_err(dev, "Missing rockchip,grf property\n");
 152                 return;
 153         }
 154
 155         if (speed == 10)
 156                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 157                              RK3228_GMAC_CLK_2_5M);
 158         else if (speed == 100)
 159                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 160                              RK3228_GMAC_CLK_25M);
 161         else if (speed == 1000)
 162                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 163                              RK3228_GMAC_CLK_125M);
 164         else
 165                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 166 }
 167
 168 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 169 {
 170         struct device *dev = &bsp_priv->pdev->dev;
 171
 172         if (IS_ERR(bsp_priv->grf)) {
 173                 dev_err(dev, "Missing rockchip,grf property\n");
 174                 return;
 175         }
 176
 177         if (speed == 10)
 178                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 179                              RK3228_GMAC_RMII_CLK_2_5M |
 180                              RK3228_GMAC_SPEED_10M);
 181         else if (speed == 100)
 182                 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
 183                              RK3228_GMAC_RMII_CLK_25M |
 184                              RK3228_GMAC_SPEED_100M);
 185         else
 186                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 187 }
 188
 189 static const struct rk_gmac_ops rk3228_ops = {
 190         .set_to_rgmii = rk3228_set_to_rgmii,
 191         .set_to_rmii = rk3228_set_to_rmii,
 192         .set_rgmii_speed = rk3228_set_rgmii_speed,
 193         .set_rmii_speed = rk3228_set_rmii_speed,
 194 };
 195
 196 #define RK3288_GRF_SOC_CON1     0x0248
 197 #define RK3288_GRF_SOC_CON3     0x0250
 198
 199 /*RK3288_GRF_SOC_CON1*/
 200 #define RK3288_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(6) | GRF_CLR_BIT(7) | \
 201                                          GRF_CLR_BIT(8))
 202 #define RK3288_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
 203                                          GRF_BIT(8))
 204 #define RK3288_GMAC_FLOW_CTRL           GRF_BIT(9)
 205 #define RK3288_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(9)
 206 #define RK3288_GMAC_SPEED_10M           GRF_CLR_BIT(10)
 207 #define RK3288_GMAC_SPEED_100M          GRF_BIT(10)
 208 #define RK3288_GMAC_RMII_CLK_25M        GRF_BIT(11)
 209 #define RK3288_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(11)
 210 #define RK3288_GMAC_CLK_125M            (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
 211 #define RK3288_GMAC_CLK_25M             (GRF_BIT(12) | GRF_BIT(13))
 212 #define RK3288_GMAC_CLK_2_5M            (GRF_CLR_BIT(12) | GRF_BIT(13))
 213 #define RK3288_GMAC_RMII_MODE           GRF_BIT(14)
 214 #define RK3288_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(14)
 215
 216 /*RK3288_GRF_SOC_CON3*/
 217 #define RK3288_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(14)
 218 #define RK3288_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(14)
 219 #define RK3288_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 220 #define RK3288_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 221 #define RK3288_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 222 #define RK3288_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 223
 224 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
 225                                 int tx_delay, int rx_delay)
 226 {
 227         struct device *dev = &bsp_priv->pdev->dev;
 228
 229         if (IS_ERR(bsp_priv->grf)) {
 230                 dev_err(dev, "Missing rockchip,grf property\n");
 231                 return;
 232         }
 233
 234         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 235                      RK3288_GMAC_PHY_INTF_SEL_RGMII |
 236                      RK3288_GMAC_RMII_MODE_CLR);
 237         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
 238                      DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
 239                      RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
 240                      RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
 241 }
 242
 243 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
 244 {
 245         struct device *dev = &bsp_priv->pdev->dev;
 246
 247         if (IS_ERR(bsp_priv->grf)) {
 248                 dev_err(dev, "Missing rockchip,grf property\n");
 249                 return;
 250         }
 251
 252         regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 253                      RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
 254 }
 255
 256 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 257 {
 258         struct device *dev = &bsp_priv->pdev->dev;
 259
 260         if (IS_ERR(bsp_priv->grf)) {
 261                 dev_err(dev, "Missing rockchip,grf property\n");
 262                 return;
 263         }
 264
 265         if (speed == 10)
 266                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 267                              RK3288_GMAC_CLK_2_5M);
 268         else if (speed == 100)
 269                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 270                              RK3288_GMAC_CLK_25M);
 271         else if (speed == 1000)
 272                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 273                              RK3288_GMAC_CLK_125M);
 274         else
 275                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 276 }
 277
 278 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 279 {
 280         struct device *dev = &bsp_priv->pdev->dev;
 281
 282         if (IS_ERR(bsp_priv->grf)) {
 283                 dev_err(dev, "Missing rockchip,grf property\n");
 284                 return;
 285         }
 286
 287         if (speed == 10) {
 288                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 289                              RK3288_GMAC_RMII_CLK_2_5M |
 290                              RK3288_GMAC_SPEED_10M);
 291         } else if (speed == 100) {
 292                 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
 293                              RK3288_GMAC_RMII_CLK_25M |
 294                              RK3288_GMAC_SPEED_100M);
 295         } else {
 296                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 297         }
 298 }
 299
 300 static const struct rk_gmac_ops rk3288_ops = {
 301         .set_to_rgmii = rk3288_set_to_rgmii,
 302         .set_to_rmii = rk3288_set_to_rmii,
 303         .set_rgmii_speed = rk3288_set_rgmii_speed,
 304         .set_rmii_speed = rk3288_set_rmii_speed,
 305 };
 306
 307 #define RK3328_GRF_MAC_CON0     0x0900
 308 #define RK3328_GRF_MAC_CON1     0x0904
 309
 310 /* RK3328_GRF_MAC_CON0 */
 311 #define RK3328_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 7)
 312 #define RK3328_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 313
 314 /* RK3328_GRF_MAC_CON1 */
 315 #define RK3328_GMAC_PHY_INTF_SEL_RGMII  \
 316                 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
 317 #define RK3328_GMAC_PHY_INTF_SEL_RMII   \
 318                 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
 319 #define RK3328_GMAC_FLOW_CTRL           GRF_BIT(3)
 320 #define RK3328_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(3)
 321 #define RK3328_GMAC_SPEED_10M           GRF_CLR_BIT(2)
 322 #define RK3328_GMAC_SPEED_100M          GRF_BIT(2)
 323 #define RK3328_GMAC_RMII_CLK_25M        GRF_BIT(7)
 324 #define RK3328_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(7)
 325 #define RK3328_GMAC_CLK_125M            (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
 326 #define RK3328_GMAC_CLK_25M             (GRF_BIT(11) | GRF_BIT(12))
 327 #define RK3328_GMAC_CLK_2_5M            (GRF_CLR_BIT(11) | GRF_BIT(12))
 328 #define RK3328_GMAC_RMII_MODE           GRF_BIT(9)
 329 #define RK3328_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(9)
 330 #define RK3328_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(0)
 331 #define RK3328_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 332 #define RK3328_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(1)
 333 #define RK3328_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(0)
 334
 335 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
 336                                 int tx_delay, int rx_delay)
 337 {
 338         struct device *dev = &bsp_priv->pdev->dev;
 339
 340         if (IS_ERR(bsp_priv->grf)) {
 341                 dev_err(dev, "Missing rockchip,grf property\n");
 342                 return;
 343         }
 344
 345         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 346                      RK3328_GMAC_PHY_INTF_SEL_RGMII |
 347                      RK3328_GMAC_RMII_MODE_CLR |
 348                      RK3328_GMAC_RXCLK_DLY_ENABLE |
 349                      RK3328_GMAC_TXCLK_DLY_ENABLE);
 350
 351         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
 352                      RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
 353                      RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
 354 }
 355
 356 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
 357 {
 358         struct device *dev = &bsp_priv->pdev->dev;
 359
 360         if (IS_ERR(bsp_priv->grf)) {
 361                 dev_err(dev, "Missing rockchip,grf property\n");
 362                 return;
 363         }
 364
 365         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 366                      RK3328_GMAC_PHY_INTF_SEL_RMII |
 367                      RK3328_GMAC_RMII_MODE);
 368
 369         /* set MAC to RMII mode */
 370         regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, GRF_BIT(11));
 371 }
 372
 373 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 374 {
 375         struct device *dev = &bsp_priv->pdev->dev;
 376
 377         if (IS_ERR(bsp_priv->grf)) {
 378                 dev_err(dev, "Missing rockchip,grf property\n");
 379                 return;
 380         }
 381
 382         if (speed == 10)
 383                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 384                              RK3328_GMAC_CLK_2_5M);
 385         else if (speed == 100)
 386                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 387                              RK3328_GMAC_CLK_25M);
 388         else if (speed == 1000)
 389                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 390                              RK3328_GMAC_CLK_125M);
 391         else
 392                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 393 }
 394
 395 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 396 {
 397         struct device *dev = &bsp_priv->pdev->dev;
 398
 399         if (IS_ERR(bsp_priv->grf)) {
 400                 dev_err(dev, "Missing rockchip,grf property\n");
 401                 return;
 402         }
 403
 404         if (speed == 10)
 405                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 406                              RK3328_GMAC_RMII_CLK_2_5M |
 407                              RK3328_GMAC_SPEED_10M);
 408         else if (speed == 100)
 409                 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
 410                              RK3328_GMAC_RMII_CLK_25M |
 411                              RK3328_GMAC_SPEED_100M);
 412         else
 413                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 414 }
 415
 416 static const struct rk_gmac_ops rk3328_ops = {
 417         .set_to_rgmii = rk3328_set_to_rgmii,
 418         .set_to_rmii = rk3328_set_to_rmii,
 419         .set_rgmii_speed = rk3328_set_rgmii_speed,
 420         .set_rmii_speed = rk3328_set_rmii_speed,
 421 };
 422
 423 #define RK3366_GRF_SOC_CON6     0x0418
 424 #define RK3366_GRF_SOC_CON7     0x041c
 425
 426 /* RK3366_GRF_SOC_CON6 */
 427 #define RK3366_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 428                                          GRF_CLR_BIT(11))
 429 #define RK3366_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 430                                          GRF_BIT(11))
 431 #define RK3366_GMAC_FLOW_CTRL           GRF_BIT(8)
 432 #define RK3366_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 433 #define RK3366_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 434 #define RK3366_GMAC_SPEED_100M          GRF_BIT(7)
 435 #define RK3366_GMAC_RMII_CLK_25M        GRF_BIT(3)
 436 #define RK3366_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 437 #define RK3366_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 438 #define RK3366_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 439 #define RK3366_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 440 #define RK3366_GMAC_RMII_MODE           GRF_BIT(6)
 441 #define RK3366_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 442
 443 /* RK3366_GRF_SOC_CON7 */
 444 #define RK3366_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 445 #define RK3366_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 446 #define RK3366_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 447 #define RK3366_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 448 #define RK3366_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 449 #define RK3366_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 450
 451 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
 452                                 int tx_delay, int rx_delay)
 453 {
 454         struct device *dev = &bsp_priv->pdev->dev;
 455
 456         if (IS_ERR(bsp_priv->grf)) {
 457                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 458                 return;
 459         }
 460
 461         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 462                      RK3366_GMAC_PHY_INTF_SEL_RGMII |
 463                      RK3366_GMAC_RMII_MODE_CLR);
 464         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
 465                      DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
 466                      RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
 467                      RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
 468 }
 469
 470 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
 471 {
 472         struct device *dev = &bsp_priv->pdev->dev;
 473
 474         if (IS_ERR(bsp_priv->grf)) {
 475                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 476                 return;
 477         }
 478
 479         regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 480                      RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
 481 }
 482
 483 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 484 {
 485         struct device *dev = &bsp_priv->pdev->dev;
 486
 487         if (IS_ERR(bsp_priv->grf)) {
 488                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 489                 return;
 490         }
 491
 492         if (speed == 10)
 493                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 494                              RK3366_GMAC_CLK_2_5M);
 495         else if (speed == 100)
 496                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 497                              RK3366_GMAC_CLK_25M);
 498         else if (speed == 1000)
 499                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 500                              RK3366_GMAC_CLK_125M);
 501         else
 502                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 503 }
 504
 505 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 506 {
 507         struct device *dev = &bsp_priv->pdev->dev;
 508
 509         if (IS_ERR(bsp_priv->grf)) {
 510                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 511                 return;
 512         }
 513
 514         if (speed == 10) {
 515                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 516                              RK3366_GMAC_RMII_CLK_2_5M |
 517                              RK3366_GMAC_SPEED_10M);
 518         } else if (speed == 100) {
 519                 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
 520                              RK3366_GMAC_RMII_CLK_25M |
 521                              RK3366_GMAC_SPEED_100M);
 522         } else {
 523                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 524         }
 525 }
 526
 527 static const struct rk_gmac_ops rk3366_ops = {
 528         .set_to_rgmii = rk3366_set_to_rgmii,
 529         .set_to_rmii = rk3366_set_to_rmii,
 530         .set_rgmii_speed = rk3366_set_rgmii_speed,
 531         .set_rmii_speed = rk3366_set_rmii_speed,
 532 };
 533
 534 #define RK3368_GRF_SOC_CON15    0x043c
 535 #define RK3368_GRF_SOC_CON16    0x0440
 536
 537 /* RK3368_GRF_SOC_CON15 */
 538 #define RK3368_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 539                                          GRF_CLR_BIT(11))
 540 #define RK3368_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 541                                          GRF_BIT(11))
 542 #define RK3368_GMAC_FLOW_CTRL           GRF_BIT(8)
 543 #define RK3368_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 544 #define RK3368_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 545 #define RK3368_GMAC_SPEED_100M          GRF_BIT(7)
 546 #define RK3368_GMAC_RMII_CLK_25M        GRF_BIT(3)
 547 #define RK3368_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 548 #define RK3368_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 549 #define RK3368_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 550 #define RK3368_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 551 #define RK3368_GMAC_RMII_MODE           GRF_BIT(6)
 552 #define RK3368_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 553
 554 /* RK3368_GRF_SOC_CON16 */
 555 #define RK3368_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 556 #define RK3368_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 557 #define RK3368_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 558 #define RK3368_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 559 #define RK3368_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 560 #define RK3368_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 561
 562 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
 563                                 int tx_delay, int rx_delay)
 564 {
 565         struct device *dev = &bsp_priv->pdev->dev;
 566
 567         if (IS_ERR(bsp_priv->grf)) {
 568                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 569                 return;
 570         }
 571
 572         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 573                      RK3368_GMAC_PHY_INTF_SEL_RGMII |
 574                      RK3368_GMAC_RMII_MODE_CLR);
 575         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
 576                      DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
 577                      RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
 578                      RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
 579 }
 580
 581 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
 582 {
 583         struct device *dev = &bsp_priv->pdev->dev;
 584
 585         if (IS_ERR(bsp_priv->grf)) {
 586                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 587                 return;
 588         }
 589
 590         regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 591                      RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
 592 }
 593
 594 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 595 {
 596         struct device *dev = &bsp_priv->pdev->dev;
 597
 598         if (IS_ERR(bsp_priv->grf)) {
 599                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 600                 return;
 601         }
 602
 603         if (speed == 10)
 604                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 605                              RK3368_GMAC_CLK_2_5M);
 606         else if (speed == 100)
 607                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 608                              RK3368_GMAC_CLK_25M);
 609         else if (speed == 1000)
 610                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 611                              RK3368_GMAC_CLK_125M);
 612         else
 613                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 614 }
 615
 616 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 617 {
 618         struct device *dev = &bsp_priv->pdev->dev;
 619
 620         if (IS_ERR(bsp_priv->grf)) {
 621                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 622                 return;
 623         }
 624
 625         if (speed == 10) {
 626                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 627                              RK3368_GMAC_RMII_CLK_2_5M |
 628                              RK3368_GMAC_SPEED_10M);
 629         } else if (speed == 100) {
 630                 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
 631                              RK3368_GMAC_RMII_CLK_25M |
 632                              RK3368_GMAC_SPEED_100M);
 633         } else {
 634                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 635         }
 636 }
 637
 638 static const struct rk_gmac_ops rk3368_ops = {
 639         .set_to_rgmii = rk3368_set_to_rgmii,
 640         .set_to_rmii = rk3368_set_to_rmii,
 641         .set_rgmii_speed = rk3368_set_rgmii_speed,
 642         .set_rmii_speed = rk3368_set_rmii_speed,
 643 };
 644
 645 #define RK3399_GRF_SOC_CON5     0xc214
 646 #define RK3399_GRF_SOC_CON6     0xc218
 647
 648 /* RK3399_GRF_SOC_CON5 */
 649 #define RK3399_GMAC_PHY_INTF_SEL_RGMII  (GRF_BIT(9) | GRF_CLR_BIT(10) | \
 650                                          GRF_CLR_BIT(11))
 651 #define RK3399_GMAC_PHY_INTF_SEL_RMII   (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
 652                                          GRF_BIT(11))
 653 #define RK3399_GMAC_FLOW_CTRL           GRF_BIT(8)
 654 #define RK3399_GMAC_FLOW_CTRL_CLR       GRF_CLR_BIT(8)
 655 #define RK3399_GMAC_SPEED_10M           GRF_CLR_BIT(7)
 656 #define RK3399_GMAC_SPEED_100M          GRF_BIT(7)
 657 #define RK3399_GMAC_RMII_CLK_25M        GRF_BIT(3)
 658 #define RK3399_GMAC_RMII_CLK_2_5M       GRF_CLR_BIT(3)
 659 #define RK3399_GMAC_CLK_125M            (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
 660 #define RK3399_GMAC_CLK_25M             (GRF_BIT(4) | GRF_BIT(5))
 661 #define RK3399_GMAC_CLK_2_5M            (GRF_CLR_BIT(4) | GRF_BIT(5))
 662 #define RK3399_GMAC_RMII_MODE           GRF_BIT(6)
 663 #define RK3399_GMAC_RMII_MODE_CLR       GRF_CLR_BIT(6)
 664
 665 /* RK3399_GRF_SOC_CON6 */
 666 #define RK3399_GMAC_TXCLK_DLY_ENABLE    GRF_BIT(7)
 667 #define RK3399_GMAC_TXCLK_DLY_DISABLE   GRF_CLR_BIT(7)
 668 #define RK3399_GMAC_RXCLK_DLY_ENABLE    GRF_BIT(15)
 669 #define RK3399_GMAC_RXCLK_DLY_DISABLE   GRF_CLR_BIT(15)
 670 #define RK3399_GMAC_CLK_RX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 8)
 671 #define RK3399_GMAC_CLK_TX_DL_CFG(val)  HIWORD_UPDATE(val, 0x7F, 0)
 672
 673 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
 674                                 int tx_delay, int rx_delay)
 675 {
 676         struct device *dev = &bsp_priv->pdev->dev;
 677
 678         if (IS_ERR(bsp_priv->grf)) {
 679                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 680                 return;
 681         }
 682
 683         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 684                      RK3399_GMAC_PHY_INTF_SEL_RGMII |
 685                      RK3399_GMAC_RMII_MODE_CLR);
 686         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
 687                      DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
 688                      RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
 689                      RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
 690 }
 691
 692 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
 693 {
 694         struct device *dev = &bsp_priv->pdev->dev;
 695
 696         if (IS_ERR(bsp_priv->grf)) {
 697                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 698                 return;
 699         }
 700
 701         regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 702                      RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
 703 }
 704
 705 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
 706 {
 707         struct device *dev = &bsp_priv->pdev->dev;
 708
 709         if (IS_ERR(bsp_priv->grf)) {
 710                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 711                 return;
 712         }
 713
 714         if (speed == 10)
 715                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 716                              RK3399_GMAC_CLK_2_5M);
 717         else if (speed == 100)
 718                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 719                              RK3399_GMAC_CLK_25M);
 720         else if (speed == 1000)
 721                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 722                              RK3399_GMAC_CLK_125M);
 723         else
 724                 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
 725 }
 726
 727 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
 728 {
 729         struct device *dev = &bsp_priv->pdev->dev;
 730
 731         if (IS_ERR(bsp_priv->grf)) {
 732                 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
 733                 return;
 734         }
 735
 736         if (speed == 10) {
 737                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 738                              RK3399_GMAC_RMII_CLK_2_5M |
 739                              RK3399_GMAC_SPEED_10M);
 740         } else if (speed == 100) {
 741                 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
 742                              RK3399_GMAC_RMII_CLK_25M |
 743                              RK3399_GMAC_SPEED_100M);
 744         } else {
 745                 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
 746         }
 747 }
 748
 749 static const struct rk_gmac_ops rk3399_ops = {
 750         .set_to_rgmii = rk3399_set_to_rgmii,
 751         .set_to_rmii = rk3399_set_to_rmii,
 752         .set_rgmii_speed = rk3399_set_rgmii_speed,
 753         .set_rmii_speed = rk3399_set_rmii_speed,
 754 };
 755
 756 static int gmac_clk_init(struct rk_priv_data *bsp_priv)
 757 {
 758         struct device *dev = &bsp_priv->pdev->dev;
 759
 760         bsp_priv->clk_enabled = false;
 761
 762         bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
 763         if (IS_ERR(bsp_priv->mac_clk_rx))
 764                 dev_err(dev, "cannot get clock %s\n",
 765                         "mac_clk_rx");
 766
 767         bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
 768         if (IS_ERR(bsp_priv->mac_clk_tx))
 769                 dev_err(dev, "cannot get clock %s\n",
 770                         "mac_clk_tx");
 771
 772         bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
 773         if (IS_ERR(bsp_priv->aclk_mac))
 774                 dev_err(dev, "cannot get clock %s\n",
 775                         "aclk_mac");
 776
 777         bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
 778         if (IS_ERR(bsp_priv->pclk_mac))
 779                 dev_err(dev, "cannot get clock %s\n",
 780                         "pclk_mac");
 781
 782         bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
 783         if (IS_ERR(bsp_priv->clk_mac))
 784                 dev_err(dev, "cannot get clock %s\n",
 785                         "stmmaceth");
 786
 787         if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
 788                 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
 789                 if (IS_ERR(bsp_priv->clk_mac_ref))
 790                         dev_err(dev, "cannot get clock %s\n",
 791                                 "clk_mac_ref");
 792
 793                 if (!bsp_priv->clock_input) {
 794                         bsp_priv->clk_mac_refout =
 795                                 devm_clk_get(dev, "clk_mac_refout");
 796                         if (IS_ERR(bsp_priv->clk_mac_refout))
 797                                 dev_err(dev, "cannot get clock %s\n",
 798                                         "clk_mac_refout");
 799                 }
 800         }
 801
 802         if (bsp_priv->clock_input) {
 803                 dev_info(dev, "clock input from PHY\n");
 804         } else {
 805                 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
 806                         clk_set_rate(bsp_priv->clk_mac, 50000000);
 807         }
 808
 809         return 0;
 810 }
 811
 812 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 813 {
 814         int phy_iface = bsp_priv->phy_iface;
 815
 816         if (enable) {
 817                 if (!bsp_priv->clk_enabled) {
 818                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 819                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 820                                         clk_prepare_enable(
 821                                                 bsp_priv->mac_clk_rx);
 822
 823                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 824                                         clk_prepare_enable(
 825                                                 bsp_priv->clk_mac_ref);
 826
 827                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 828                                         clk_prepare_enable(
 829                                                 bsp_priv->clk_mac_refout);
 830                         }
 831
 832                         if (!IS_ERR(bsp_priv->aclk_mac))
 833                                 clk_prepare_enable(bsp_priv->aclk_mac);
 834
 835                         if (!IS_ERR(bsp_priv->pclk_mac))
 836                                 clk_prepare_enable(bsp_priv->pclk_mac);
 837
 838                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 839                                 clk_prepare_enable(bsp_priv->mac_clk_tx);
 840
 841                         /**
 842                          * if (!IS_ERR(bsp_priv->clk_mac))
 843                          *      clk_prepare_enable(bsp_priv->clk_mac);
 844                          */
 845                         mdelay(5);
 846                         bsp_priv->clk_enabled = true;
 847                 }
 848         } else {
 849                 if (bsp_priv->clk_enabled) {
 850                         if (phy_iface == PHY_INTERFACE_MODE_RMII) {
 851                                 if (!IS_ERR(bsp_priv->mac_clk_rx))
 852                                         clk_disable_unprepare(
 853                                                 bsp_priv->mac_clk_rx);
 854
 855                                 if (!IS_ERR(bsp_priv->clk_mac_ref))
 856                                         clk_disable_unprepare(
 857                                                 bsp_priv->clk_mac_ref);
 858
 859                                 if (!IS_ERR(bsp_priv->clk_mac_refout))
 860                                         clk_disable_unprepare(
 861                                                 bsp_priv->clk_mac_refout);
 862                         }
 863
 864                         if (!IS_ERR(bsp_priv->aclk_mac))
 865                                 clk_disable_unprepare(bsp_priv->aclk_mac);
 866
 867                         if (!IS_ERR(bsp_priv->pclk_mac))
 868                                 clk_disable_unprepare(bsp_priv->pclk_mac);
 869
 870                         if (!IS_ERR(bsp_priv->mac_clk_tx))
 871                                 clk_disable_unprepare(bsp_priv->mac_clk_tx);
 872                         /**
 873                          * if (!IS_ERR(bsp_priv->clk_mac))
 874                          *      clk_disable_unprepare(bsp_priv->clk_mac);
 875                          */
 876                         bsp_priv->clk_enabled = false;
 877                 }
 878         }
 879
 880         return 0;
 881 }
 882
 883 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
 884 {
 885         struct regulator *ldo = bsp_priv->regulator;
 886         int ret;
 887         struct device *dev = &bsp_priv->pdev->dev;
 888
 889         if (!ldo) {
 890                 dev_err(dev, "no regulator found\n");
 891                 return -1;
 892         }
 893
 894         if (enable) {
 895                 ret = regulator_enable(ldo);
 896                 if (ret)
 897                         dev_err(dev, "fail to enable phy-supply\n");
 898         } else {
 899                 ret = regulator_disable(ldo);
 900                 if (ret)
 901                         dev_err(dev, "fail to disable phy-supply\n");
 902         }
 903
 904         return 0;
 905 }
 906
 907 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
 908                                           const struct rk_gmac_ops *ops)
 909 {
 910         struct rk_priv_data *bsp_priv;
 911         struct device *dev = &pdev->dev;
 912         int ret;
 913         const char *strings = NULL;
 914         int value;
 915
 916         bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
 917         if (!bsp_priv)
 918                 return ERR_PTR(-ENOMEM);
 919
 920         bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
 921         bsp_priv->ops = ops;
 922
 923         bsp_priv->regulator = devm_regulator_get_optional(dev, "phy");
 924         if (IS_ERR(bsp_priv->regulator)) {
 925                 if (PTR_ERR(bsp_priv->regulator) == -EPROBE_DEFER) {
 926                         dev_err(dev, "phy regulator is not available yet, deferred probing\n");
 927                         return ERR_PTR(-EPROBE_DEFER);
 928                 }
 929                 dev_err(dev, "no regulator found\n");
 930                 bsp_priv->regulator = NULL;
 931         }
 932
 933         ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
 934         if (ret) {
 935                 dev_err(dev, "Can not read property: clock_in_out.\n");
 936                 bsp_priv->clock_input = true;
 937         } else {
 938                 dev_info(dev, "clock input or output? (%s).\n",
 939                          strings);
 940                 if (!strcmp(strings, "input"))
 941                         bsp_priv->clock_input = true;
 942                 else
 943                         bsp_priv->clock_input = false;
 944         }
 945
 946         ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
 947         if (ret) {
 948                 bsp_priv->tx_delay = 0x30;
 949                 dev_err(dev, "Can not read property: tx_delay.");
 950                 dev_err(dev, "set tx_delay to 0x%x\n",
 951                         bsp_priv->tx_delay);
 952         } else {
 953                 dev_info(dev, "TX delay(0x%x).\n", value);
 954                 bsp_priv->tx_delay = value;
 955         }
 956
 957         ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
 958         if (ret) {
 959                 bsp_priv->rx_delay = 0x10;
 960                 dev_err(dev, "Can not read property: rx_delay.");
 961                 dev_err(dev, "set rx_delay to 0x%x\n",
 962                         bsp_priv->rx_delay);
 963         } else {
 964                 dev_info(dev, "RX delay(0x%x).\n", value);
 965                 bsp_priv->rx_delay = value;
 966         }
 967
 968         bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
 969                                                         "rockchip,grf");
 970         bsp_priv->pdev = pdev;
 971
 972         gmac_clk_init(bsp_priv);
 973
 974         return bsp_priv;
 975 }
 976
 977 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
 978 {
 979         int ret;
 980         struct device *dev = &bsp_priv->pdev->dev;
 981
 982         ret = gmac_clk_enable(bsp_priv, true);
 983         if (ret)
 984                 return ret;
 985
 986         /*rmii or rgmii*/
 987         switch (bsp_priv->phy_iface) {
 988         case PHY_INTERFACE_MODE_RGMII:
 989                 dev_info(dev, "init for RGMII\n");
 990                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
 991                                             bsp_priv->rx_delay);
 992                 break;
 993         case PHY_INTERFACE_MODE_RGMII_ID:
 994                 dev_info(dev, "init for RGMII_ID\n");
 995                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
 996                 break;
 997         case PHY_INTERFACE_MODE_RGMII_RXID:
 998                 dev_info(dev, "init for RGMII_RXID\n");
 999                 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1000                 break;
1001         case PHY_INTERFACE_MODE_RGMII_TXID:
1002                 dev_info(dev, "init for RGMII_TXID\n");
1003                 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1004                 break;
1005         case PHY_INTERFACE_MODE_RMII:
1006                 dev_info(dev, "init for RMII\n");
1007                 bsp_priv->ops->set_to_rmii(bsp_priv);
1008                 break;
1009         default:
1010                 dev_err(dev, "NO interface defined!\n");
1011         }
1012
1013         ret = phy_power_on(bsp_priv, true);
1014         if (ret)
1015                 return ret;
1016
1017         pm_runtime_enable(dev);
1018         pm_runtime_get_sync(dev);
1019
1020         return 0;
1021 }
1022
1023 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1024 {
1025         struct device *dev = &gmac->pdev->dev;
1026
1027         pm_runtime_put_sync(dev);
1028         pm_runtime_disable(dev);
1029
1030         phy_power_on(gmac, false);
1031         gmac_clk_enable(gmac, false);
1032 }
1033
1034 static void rk_fix_speed(void *priv, unsigned int speed)
1035 {
1036         struct rk_priv_data *bsp_priv = priv;
1037         struct device *dev = &bsp_priv->pdev->dev;
1038
1039         switch (bsp_priv->phy_iface) {
1040         case PHY_INTERFACE_MODE_RGMII:
1041         case PHY_INTERFACE_MODE_RGMII_ID:
1042         case PHY_INTERFACE_MODE_RGMII_RXID:
1043         case PHY_INTERFACE_MODE_RGMII_TXID:
1044                 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1045                 break;
1046         case PHY_INTERFACE_MODE_RMII:
1047                 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1048                 break;
1049         default:
1050                 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1051         }
1052 }
1053
1054 static int rk_gmac_probe(struct platform_device *pdev)
1055 {
1056         struct plat_stmmacenet_data *plat_dat;
1057         struct stmmac_resources stmmac_res;
1058         const struct rk_gmac_ops *data;
1059         int ret;
1060
1061         data = of_device_get_match_data(&pdev->dev);
1062         if (!data) {
1063                 dev_err(&pdev->dev, "no of match data provided\n");
1064                 return -EINVAL;
1065         }
1066
1067         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1068         if (ret)
1069                 return ret;
1070
1071         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1072         if (IS_ERR(plat_dat))
1073                 return PTR_ERR(plat_dat);
1074
1075         plat_dat->has_gmac = true;
1076         plat_dat->fix_mac_speed = rk_fix_speed;
1077
1078         plat_dat->bsp_priv = rk_gmac_setup(pdev, data);
1079         if (IS_ERR(plat_dat->bsp_priv)) {
1080                 ret = PTR_ERR(plat_dat->bsp_priv);
1081                 goto err_remove_config_dt;
1082         }
1083
1084         ret = rk_gmac_powerup(plat_dat->bsp_priv);
1085         if (ret)
1086                 goto err_remove_config_dt;
1087
1088         ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1089         if (ret)
1090                 goto err_gmac_powerdown;
1091
1092         return 0;
1093
1094 err_gmac_powerdown:
1095         rk_gmac_powerdown(plat_dat->bsp_priv);
1096 err_remove_config_dt:
1097         stmmac_remove_config_dt(pdev, plat_dat);
1098
1099         return ret;
1100 }
1101
1102 static int rk_gmac_remove(struct platform_device *pdev)
1103 {
1104         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1105         int ret = stmmac_dvr_remove(&pdev->dev);
1106
1107         rk_gmac_powerdown(bsp_priv);
1108
1109         return ret;
1110 }
1111
1112 #ifdef CONFIG_PM_SLEEP
1113 static int rk_gmac_suspend(struct device *dev)
1114 {
1115         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1116         int ret = stmmac_suspend(dev);
1117
1118         /* Keep the PHY up if we use Wake-on-Lan. */
1119         if (!device_may_wakeup(dev)) {
1120                 rk_gmac_powerdown(bsp_priv);
1121                 bsp_priv->suspended = true;
1122         }
1123
1124         return ret;
1125 }
1126
1127 static int rk_gmac_resume(struct device *dev)
1128 {
1129         struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1130
1131         /* The PHY was up for Wake-on-Lan. */
1132         if (bsp_priv->suspended) {
1133                 rk_gmac_powerup(bsp_priv);
1134                 bsp_priv->suspended = false;
1135         }
1136
1137         return stmmac_resume(dev);
1138 }
1139 #endif /* CONFIG_PM_SLEEP */
1140
1141 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1142
1143 static const struct of_device_id rk_gmac_dwmac_match[] = {
1144         { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1145         { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1146         { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1147         { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1148         { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1149         { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1150         { }
1151 };
1152 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1153
1154 static struct platform_driver rk_gmac_dwmac_driver = {
1155         .probe  = rk_gmac_probe,
1156         .remove = rk_gmac_remove,
1157         .driver = {
1158                 .name           = "rk_gmac-dwmac",
1159                 .pm             = &rk_gmac_pm_ops,
1160                 .of_match_table = rk_gmac_dwmac_match,
1161         },
1162 };
1163 module_platform_driver(rk_gmac_dwmac_driver);
1164
1165 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1166 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1167 MODULE_LICENSE("GPL");