2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
20 #include <asm/errno.h>
21 #include <linux/compiler.h>
25 DECLARE_GLOBAL_DATA_PTR;
28 * Timeout the transfer after 5 mS. This is usually a bit more, since
29 * the code in the tightloops this timeout is used in adds some overhead.
31 #define FEC_XFER_TIMEOUT 5000
34 #error "CONFIG_MII has to be defined!"
37 #ifndef CONFIG_FEC_XCV_TYPE
38 #define CONFIG_FEC_XCV_TYPE MII100
42 * The i.MX28 operates with packets in big endian. We need to swap them before
43 * sending and after receiving.
46 #define CONFIG_FEC_MXC_SWAP_PACKET
49 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
51 /* Check various alignment issues at compile time */
52 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
53 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
56 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
57 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
58 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
64 uint8_t data[1500]; /**< actual data */
65 int length; /**< actual length */
66 int used; /**< buffer in use or not */
67 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
72 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
73 static void swap_packet(uint32_t *packet, int length)
77 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
78 packet[i] = __swab32(packet[i]);
83 * MII-interface related functions
85 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
88 uint32_t reg; /* convenient holder for the PHY register */
89 uint32_t phy; /* convenient holder for the PHY */
94 * reading from any PHY's register is done by properly
95 * programming the FEC's MII data register.
97 writel(FEC_IEVENT_MII, ð->ievent);
98 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
99 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
101 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
102 phy | reg, ð->mii_data);
105 * wait for the related interrupt
107 start = get_timer(0);
108 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
109 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
110 if (readl(ð->ievent) & FEC_IEVENT_MII)
112 printf("Read MDIO failed...\n");
118 * clear mii interrupt bit
120 writel(FEC_IEVENT_MII, ð->ievent);
123 * it's now safe to read the PHY's register
125 val = (unsigned short)readl(ð->mii_data);
126 debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr,
131 static void fec_mii_setspeed(struct ethernet_regs *eth)
134 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
135 * and do not drop the Preamble.
137 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
139 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
142 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
143 uint8_t regAddr, uint16_t data)
145 uint32_t reg; /* convenient holder for the PHY register */
146 uint32_t phy; /* convenient holder for the PHY */
149 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
150 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
152 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
153 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
156 * wait for the MII interrupt
158 start = get_timer(0);
159 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
160 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
161 if (readl(ð->ievent) & FEC_IEVENT_MII)
163 printf("Write MDIO failed...\n");
169 * clear MII interrupt bit
171 writel(FEC_IEVENT_MII, ð->ievent);
172 debug("%s: phy: %02x reg:%02x val:%#06x\n", __func__, phyAddr,
178 int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
180 return fec_mdio_read(bus->priv, phyAddr, regAddr);
183 int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
186 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
189 #ifndef CONFIG_PHYLIB
190 static int miiphy_restart_aneg(struct eth_device *dev)
193 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
194 struct fec_priv *fec = (struct fec_priv *)dev->priv;
195 struct ethernet_regs *eth = fec->bus->priv;
198 * Wake up from sleep if necessary
199 * Reset PHY, then delay 300ns
202 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
204 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
208 * Set the auto-negotiation advertisement register bits
210 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
211 LPA_100FULL | LPA_100HALF | LPA_10FULL |
212 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
213 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
214 BMCR_ANENABLE | BMCR_ANRESTART);
216 if (fec->mii_postcall)
217 ret = fec->mii_postcall(fec->phy_id);
223 static int miiphy_wait_aneg(struct eth_device *dev)
227 struct fec_priv *fec = (struct fec_priv *)dev->priv;
228 struct ethernet_regs *eth = fec->bus->priv;
231 * Wait for AN completion
233 start = get_timer(0);
235 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
236 printf("%s: Autonegotiation timeout\n", dev->name);
240 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
242 printf("%s: Autonegotiation failed. status: %d\n",
246 } while (!(status & BMSR_LSTATUS));
252 static inline void fec_rx_task_enable(struct fec_priv *fec)
254 writel(1 << 24, &fec->eth->r_des_active);
257 static inline void fec_rx_task_disable(struct fec_priv *fec)
261 static inline void fec_tx_task_enable(struct fec_priv *fec)
263 writel(1 << 24, &fec->eth->x_des_active);
266 static inline void fec_tx_task_disable(struct fec_priv *fec)
271 * Initialize receive task's buffer descriptors
272 * @param[in] fec all we know about the device yet
273 * @param[in] count receive buffer count to be allocated
274 * @param[in] dsize desired size of each receive buffer
275 * @return 0 on success
277 * For this task we need additional memory for the data buffers. And each
278 * data buffer requires some alignment. Thy must be aligned to a specific
281 static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
287 * Allocate memory for the buffers. This allocation respects the
290 size = roundup(dsize, ARCH_DMA_MINALIGN);
291 for (i = 0; i < count; i++) {
292 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
294 uint8_t *data = memalign(ARCH_DMA_MINALIGN,
297 printf("%s: error allocating rxbuf %d\n",
301 writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
302 } /* needs allocation */
303 writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
304 writew(0, &fec->rbd_base[i].data_length);
307 /* Mark the last RBD to close the ring. */
308 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
314 for (; i >= 0; i--) {
315 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
316 free((void *)data_ptr);
323 * Initialize transmit task's buffer descriptors
324 * @param[in] fec all we know about the device yet
326 * Transmit buffers are created externally. We only have to init the BDs here.\n
327 * Note: There is a race condition in the hardware. When only one BD is in
328 * use it must be marked with the WRAP bit to use it for every transmitt.
329 * This bit in combination with the READY bit results into double transmit
330 * of each data buffer. It seems the state machine checks READY earlier then
331 * resetting it after the first transfer.
332 * Using two BDs solves this issue.
334 static void fec_tbd_init(struct fec_priv *fec)
336 unsigned addr = (unsigned)fec->tbd_base;
337 unsigned size = roundup(2 * sizeof(struct fec_bd),
339 writew(0x0000, &fec->tbd_base[0].status);
340 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
342 flush_dcache_range(addr, addr + size);
346 * Mark the given read buffer descriptor as free
347 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
348 * @param[in] pRbd buffer descriptor to mark free again
350 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
352 unsigned short flags = FEC_RBD_EMPTY;
354 flags |= FEC_RBD_WRAP;
355 writew(flags, &pRbd->status);
356 writew(0, &pRbd->data_length);
359 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
362 imx_get_mac_from_fuse(dev_id, mac);
363 return !is_valid_ether_addr(mac);
366 static int fec_set_hwaddr(struct eth_device *dev)
368 uchar *mac = dev->enetaddr;
369 struct fec_priv *fec = (struct fec_priv *)dev->priv;
371 writel(0, &fec->eth->iaddr1);
372 writel(0, &fec->eth->iaddr2);
373 writel(0, &fec->eth->gaddr1);
374 writel(0, &fec->eth->gaddr2);
377 * Set physical address
379 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
381 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
387 * Do initial configuration of the FEC registers
389 static void fec_reg_setup(struct fec_priv *fec)
394 * Set interrupt mask register
396 writel(0x00000000, &fec->eth->imask);
399 * Clear FEC-Lite interrupt event register(IEVENT)
401 writel(0xffffffff, &fec->eth->ievent);
405 * Set FEC-Lite receive control register(R_CNTRL):
408 /* Start with frame length = 1518, common for all modes. */
409 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
410 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
411 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
412 if (fec->xcv_type == RGMII)
413 rcntrl |= FEC_RCNTRL_RGMII;
414 else if (fec->xcv_type == RMII)
415 rcntrl |= FEC_RCNTRL_RMII;
417 writel(rcntrl, &fec->eth->r_cntrl);
421 * Start the FEC engine
422 * @param[in] dev Our device to handle
424 static int fec_open(struct eth_device *edev)
426 struct fec_priv *fec = edev->priv;
431 debug("fec_open: fec_open(dev)\n");
432 /* full-duplex, heartbeat disabled */
433 writel(1 << 2, &fec->eth->x_cntrl);
436 /* Invalidate all descriptors */
437 for (i = 0; i < FEC_RBD_NUM - 1; i++)
438 fec_rbd_clean(0, &fec->rbd_base[i]);
439 fec_rbd_clean(1, &fec->rbd_base[i]);
441 /* Flush the descriptors into RAM */
442 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
444 addr = (uint32_t)fec->rbd_base;
445 flush_dcache_range(addr, addr + size);
447 #ifdef FEC_QUIRK_ENET_MAC
448 /* Enable ENET HW endian SWAP */
449 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
451 /* Enable ENET store and forward mode */
452 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
456 * Enable FEC-Lite controller
458 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
460 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
463 * setup the MII gasket for RMII mode
466 /* disable the gasket */
467 writew(0, &fec->eth->miigsk_enr);
469 /* wait for the gasket to be disabled */
470 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
473 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
474 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
476 /* re-enable the gasket */
477 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
479 /* wait until MII gasket is ready */
481 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
482 if (--max_loops <= 0) {
483 printf("WAIT for MII Gasket ready timed out\n");
491 /* Start up the PHY */
492 int ret = phy_startup(fec->phydev);
495 printf("Could not initialize PHY %s\n",
496 fec->phydev->dev->name);
499 speed = fec->phydev->speed;
502 miiphy_wait_aneg(edev);
503 speed = miiphy_speed(edev->name, fec->phy_id);
504 miiphy_duplex(edev->name, fec->phy_id);
507 #ifdef FEC_QUIRK_ENET_MAC
509 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
510 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
512 if (speed == _1000BASET)
513 ecr |= FEC_ECNTRL_SPEED;
514 else if (speed != _100BASET)
515 rcr |= FEC_RCNTRL_RMII_10T;
516 writel(ecr, &fec->eth->ecntrl);
517 writel(rcr, &fec->eth->r_cntrl);
519 #elif defined(CONFIG_MX28)
521 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
523 if (speed == _10BASET)
524 rcr |= FEC_RCNTRL_RMII_10T;
525 writel(rcr, &fec->eth->r_cntrl);
528 debug("%s:Speed=%i\n", __func__, speed);
531 * Enable SmartDMA receive task
533 fec_rx_task_enable(fec);
539 static int fec_init(struct eth_device *dev, bd_t* bd)
541 struct fec_priv *fec = dev->priv;
542 uint32_t *mib_ptr = (uint32_t *)&fec->eth->rmon_t_drop;
546 /* Initialize MAC address */
550 * Allocate transmit descriptors, there are two in total. This
551 * allocation respects cache alignment.
553 if (!fec->tbd_base) {
554 size = roundup(2 * sizeof(struct fec_bd),
556 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
557 if (!fec->tbd_base) {
561 memset(fec->tbd_base, 0, size);
566 * Allocate receive descriptors. This allocation respects cache
569 if (!fec->rbd_base) {
570 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
572 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
573 if (!fec->rbd_base) {
577 memset(fec->rbd_base, 0, size);
579 * Initialize RxBD ring
581 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
585 flush_dcache_range((unsigned)fec->rbd_base,
586 (unsigned)fec->rbd_base + size);
591 if (fec->xcv_type != SEVENWIRE)
592 fec_mii_setspeed(fec->bus->priv);
595 * Set Opcode/Pause Duration Register
597 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
598 writel(0x2, &fec->eth->x_wmrk);
600 * Set multicast address filter
602 writel(0x00000000, &fec->eth->gaddr1);
603 writel(0x00000000, &fec->eth->gaddr2);
607 for (i = 0; i <= 0xfc >> 2; i++)
608 writel(0, &mib_ptr[i]);
610 /* FIFO receive start register */
611 writel(0x520, &fec->eth->r_fstart);
613 /* size and address of each buffer */
614 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
615 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
616 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
618 #ifndef CONFIG_PHYLIB
619 if (fec->xcv_type != SEVENWIRE)
620 miiphy_restart_aneg(dev);
634 * Halt the FEC engine
635 * @param[in] dev Our device to handle
637 static void fec_halt(struct eth_device *dev)
639 struct fec_priv *fec = (struct fec_priv *)dev->priv;
643 * issue graceful stop command to the FEC transmitter if necessary
645 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
648 debug("eth_halt: wait for stop regs\n");
650 * wait for graceful stop to register
652 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
656 * Disable SmartDMA tasks
658 fec_tx_task_disable(fec);
659 fec_rx_task_disable(fec);
662 * Disable the Ethernet Controller
663 * Note: this will also reset the BD index counter!
665 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
669 debug("eth_halt: done\n");
674 * @param[in] dev Our ethernet device to handle
675 * @param[in] packet Pointer to the data to be transmitted
676 * @param[in] length Data count in bytes
677 * @return 0 on success
679 static int fec_send(struct eth_device *dev, void *packet, int length)
684 int timeout = FEC_XFER_TIMEOUT;
688 * This routine transmits one frame. This routine only accepts
689 * 6-byte Ethernet addresses.
691 struct fec_priv *fec = dev->priv;
694 * Check for valid length of data.
696 if ((length > 1500) || (length <= 0)) {
697 printf("Payload (%d) too large\n", length);
702 * Setup the transmit buffer. We are always using the first buffer for
703 * transmission, the second will be empty and only used to stop the DMA
704 * engine. We also flush the packet to RAM here to avoid cache trouble.
706 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
707 swap_packet((uint32_t *)packet, length);
710 addr = (uint32_t)packet;
711 end = roundup(addr + length, ARCH_DMA_MINALIGN);
712 addr &= ~(ARCH_DMA_MINALIGN - 1);
713 flush_dcache_range(addr, end);
715 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
716 writel((unsigned long)packet,
717 &fec->tbd_base[fec->tbd_index].data_pointer);
720 * update BD's status now
722 * - is always the last in a chain (means no chain)
723 * - should transmit the CRC
724 * - might be the last BD in the list, so the address counter should
725 * wrap (-> keep the WRAP flag)
727 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
728 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
729 writew(status, &fec->tbd_base[fec->tbd_index].status);
732 * Flush data cache. This code flushes both TX descriptors to RAM.
733 * After this code, the descriptors will be safely in RAM and we
736 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
737 addr = (uint32_t)fec->tbd_base;
738 flush_dcache_range(addr, addr + size);
741 * Below we read the DMA descriptor's last four bytes back from the
742 * DRAM. This is important in order to make sure that all WRITE
743 * operations on the bus that were triggered by previous cache FLUSH
746 * Otherwise, on MX28, it is possible to observe a corruption of the
747 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
748 * for the bus structure of MX28. The scenario is as follows:
750 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
751 * to DRAM due to flush_dcache_range()
752 * 2) ARM core writes the FEC registers via AHB_ARB2
753 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
755 * Note that 2) does sometimes finish before 1) due to reordering of
756 * WRITE accesses on the AHB bus, therefore triggering 3) before the
757 * DMA descriptor is fully written into DRAM. This results in occasional
758 * corruption of the DMA descriptor.
760 readl(addr + size - 4);
763 * Enable SmartDMA transmit task
765 fec_tx_task_enable(fec);
768 * Wait until frame is sent. On each turn of the wait cycle, we must
769 * invalidate data cache to see what's really in RAM. Also, we need
773 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
780 invalidate_dcache_range(addr, addr + size);
781 if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
784 debug("fec_send: status 0x%x index %d ret %i\n",
785 readw(&fec->tbd_base[fec->tbd_index].status),
786 fec->tbd_index, ret);
787 /* for next transmission use the other buffer */
797 * Pull one frame from the card
798 * @param[in] dev Our ethernet device to handle
799 * @return Length of packet read
801 static int fec_recv(struct eth_device *dev)
803 struct fec_priv *fec = (struct fec_priv *)dev->priv;
804 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
805 unsigned long ievent;
806 int frame_length, len = 0;
809 uint32_t addr, size, end;
813 * Check if any critical events have happened
815 ievent = readl(&fec->eth->ievent);
817 writel(ievent, &fec->eth->ievent);
820 debug("fec_recv: ievent 0x%lx\n", ievent);
821 if (ievent & FEC_IEVENT_BABR) {
823 fec_init(dev, fec->bd);
824 printf("some error: 0x%08lx\n", ievent);
827 if (ievent & FEC_IEVENT_HBERR) {
828 /* Heartbeat error */
829 writel(0x00000001 | readl(&fec->eth->x_cntrl),
832 if (ievent & FEC_IEVENT_GRA) {
833 /* Graceful stop complete */
834 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
836 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
838 fec_init(dev, fec->bd);
843 * Read the buffer status. Before the status can be read, the data cache
844 * must be invalidated, because the data in RAM might have been changed
845 * by DMA. The descriptors are properly aligned to cachelines so there's
846 * no need to worry they'd overlap.
848 * WARNING: By invalidating the descriptor here, we also invalidate
849 * the descriptors surrounding this one. Therefore we can NOT change the
850 * contents of this descriptor nor the surrounding ones. The problem is
851 * that in order to mark the descriptor as processed, we need to change
852 * the descriptor. The solution is to mark the whole cache line when all
853 * descriptors in the cache line are processed.
855 addr = (uint32_t)rbd;
856 addr &= ~(ARCH_DMA_MINALIGN - 1);
857 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
858 invalidate_dcache_range(addr, addr + size);
860 bd_status = readw(&rbd->status);
861 if (!(bd_status & FEC_RBD_EMPTY)) {
862 debug("fec_recv: status 0x%04x len %u\n", bd_status,
863 readw(&rbd->data_length) - 4);
864 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
865 ((readw(&rbd->data_length) - 4) > 14)) {
867 * Get buffer address and size
869 frame = (struct nbuf *)readl(&rbd->data_pointer);
870 frame_length = readw(&rbd->data_length) - 4;
873 * Invalidate data cache over the buffer
875 addr = (uint32_t)frame;
876 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
877 addr &= ~(ARCH_DMA_MINALIGN - 1);
878 invalidate_dcache_range(addr, end);
881 * Fill the buffer and pass it to upper layers
883 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
884 swap_packet((uint32_t *)frame->data, frame_length);
886 memcpy((void *)NetRxPackets[rx_idx], frame->data, frame_length);
887 NetReceive(NetRxPackets[rx_idx], frame_length);
888 rx_idx = (rx_idx + 1) % PKTBUFSRX;
891 if (bd_status & FEC_RBD_ERR)
892 printf("error frame: 0x%08lx 0x%08x\n",
893 (ulong)rbd->data_pointer,
898 * Free the current buffer, restart the engine and move forward
899 * to the next buffer. Here we check if the whole cacheline of
900 * descriptors was already processed and if so, we mark it free
903 size = RXDESC_PER_CACHELINE - 1;
904 if ((fec->rbd_index & size) == size) {
905 i = fec->rbd_index - size;
906 addr = (uint32_t)&fec->rbd_base[i];
907 for (; i <= fec->rbd_index ; i++) {
908 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
911 flush_dcache_range(addr,
912 addr + ARCH_DMA_MINALIGN);
915 fec_rx_task_enable(fec);
916 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
917 debug("fec_recv: stop\n");
923 static void fec_set_dev_name(char *dest, int dev_id)
925 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
929 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
930 struct mii_dev *bus, struct phy_device *phydev)
932 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
933 struct mii_dev *bus, int phy_id)
936 struct eth_device *edev;
937 struct fec_priv *fec;
938 unsigned char ethaddr[6];
942 /* create and fill edev struct */
943 edev = calloc(sizeof(struct eth_device), 1);
945 puts("fec_mxc: not enough malloc memory for eth_device\n");
950 fec = calloc(sizeof(struct fec_priv), 1);
952 puts("fec_mxc: not enough malloc memory for fec_priv\n");
958 edev->init = fec_init;
959 edev->send = fec_send;
960 edev->recv = fec_recv;
961 edev->halt = fec_halt;
962 edev->write_hwaddr = fec_set_hwaddr;
964 fec->eth = (struct ethernet_regs *)base_addr;
967 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
970 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
971 start = get_timer(0);
972 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
973 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
974 printf("FEC MXC: Timeout reseting chip\n");
981 fec_set_dev_name(edev->name, dev_id);
982 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
984 fec_mii_setspeed(bus->priv);
986 fec->phydev = phydev;
987 phy_connect_dev(phydev, edev);
991 fec->phy_id = phy_id;
995 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
997 debug("got MAC address from fuse: %pM\n", ethaddr);
999 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
1000 memcpy(edev->enetaddr, ethaddr, 6);
1011 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
1013 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1014 struct mii_dev *bus;
1019 printf("mdio_alloc failed\n");
1022 bus->read = fec_phy_read;
1023 bus->write = fec_phy_write;
1025 fec_set_dev_name(bus->name, dev_id);
1027 ret = mdio_register(bus);
1029 printf("mdio_register failed\n");
1033 fec_mii_setspeed(eth);
1037 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1040 struct mii_dev *bus = NULL;
1041 #ifdef CONFIG_PHYLIB
1042 struct phy_device *phydev = NULL;
1048 * The i.MX28 has two ethernet interfaces, but they are not equal.
1049 * Only the first one can access the MDIO bus.
1051 base_mii = MXS_ENET0_BASE;
1055 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1056 bus = fec_get_miibus(base_mii, dev_id);
1059 #ifdef CONFIG_PHYLIB
1060 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1065 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1067 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1070 #ifdef CONFIG_PHYLIB
1078 #ifdef CONFIG_FEC_MXC_PHYADDR
1079 int fecmxc_initialize(bd_t *bd)
1081 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1086 #ifndef CONFIG_PHYLIB
1087 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1089 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1090 fec->mii_postcall = cb;