1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
38 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
40 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
49 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
50 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
51 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
52 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
53 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
54 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
55 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
56 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
59 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
60 * @hw: pointer to hardware structure
62 * Starts the hardware by filling the bus info structure and media type, clears
63 * all on chip counters, initializes receive address registers, multicast
64 * table, VLAN filter table, calls routine to set up link and flow control
65 * settings, and leaves transmit and receive units disabled and uninitialized
67 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
71 /* Set the media type */
72 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
74 /* Identify the PHY */
75 hw->phy.ops.identify(hw);
77 /* Clear the VLAN filter table */
78 hw->mac.ops.clear_vfta(hw);
80 /* Clear statistics registers */
81 hw->mac.ops.clear_hw_cntrs(hw);
83 /* Set No Snoop Disable */
84 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
85 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
86 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
87 IXGBE_WRITE_FLUSH(hw);
89 /* Setup flow control */
90 ixgbe_setup_fc(hw, 0);
92 /* Clear adapter stopped flag */
93 hw->adapter_stopped = false;
99 * ixgbe_start_hw_gen2 - Init sequence for common device family
100 * @hw: pointer to hw structure
102 * Performs the init sequence common to the second generation
104 * Devices in the second generation:
108 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
113 /* Clear the rate limiters */
114 for (i = 0; i < hw->mac.max_tx_queues; i++) {
115 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
116 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
118 IXGBE_WRITE_FLUSH(hw);
120 /* Disable relaxed ordering */
121 for (i = 0; i < hw->mac.max_tx_queues; i++) {
122 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
123 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
124 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
127 for (i = 0; i < hw->mac.max_rx_queues; i++) {
128 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
129 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
130 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
131 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
138 * ixgbe_init_hw_generic - Generic hardware initialization
139 * @hw: pointer to hardware structure
141 * Initialize the hardware by resetting the hardware, filling the bus info
142 * structure and media type, clears all on chip counters, initializes receive
143 * address registers, multicast table, VLAN filter table, calls routine to set
144 * up link and flow control settings, and leaves transmit and receive units
145 * disabled and uninitialized
147 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
151 /* Reset the hardware */
152 status = hw->mac.ops.reset_hw(hw);
156 status = hw->mac.ops.start_hw(hw);
163 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
164 * @hw: pointer to hardware structure
166 * Clears all hardware statistics counters by reading them from the hardware
167 * Statistics counters are clear on read.
169 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
173 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
174 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
175 IXGBE_READ_REG(hw, IXGBE_ERRBC);
176 IXGBE_READ_REG(hw, IXGBE_MSPDC);
177 for (i = 0; i < 8; i++)
178 IXGBE_READ_REG(hw, IXGBE_MPC(i));
180 IXGBE_READ_REG(hw, IXGBE_MLFC);
181 IXGBE_READ_REG(hw, IXGBE_MRFC);
182 IXGBE_READ_REG(hw, IXGBE_RLEC);
183 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
184 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
185 if (hw->mac.type >= ixgbe_mac_82599EB) {
186 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
187 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
189 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
190 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
193 for (i = 0; i < 8; i++) {
194 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
195 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
196 if (hw->mac.type >= ixgbe_mac_82599EB) {
197 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
198 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
200 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
201 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
204 if (hw->mac.type >= ixgbe_mac_82599EB)
205 for (i = 0; i < 8; i++)
206 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
207 IXGBE_READ_REG(hw, IXGBE_PRC64);
208 IXGBE_READ_REG(hw, IXGBE_PRC127);
209 IXGBE_READ_REG(hw, IXGBE_PRC255);
210 IXGBE_READ_REG(hw, IXGBE_PRC511);
211 IXGBE_READ_REG(hw, IXGBE_PRC1023);
212 IXGBE_READ_REG(hw, IXGBE_PRC1522);
213 IXGBE_READ_REG(hw, IXGBE_GPRC);
214 IXGBE_READ_REG(hw, IXGBE_BPRC);
215 IXGBE_READ_REG(hw, IXGBE_MPRC);
216 IXGBE_READ_REG(hw, IXGBE_GPTC);
217 IXGBE_READ_REG(hw, IXGBE_GORCL);
218 IXGBE_READ_REG(hw, IXGBE_GORCH);
219 IXGBE_READ_REG(hw, IXGBE_GOTCL);
220 IXGBE_READ_REG(hw, IXGBE_GOTCH);
221 for (i = 0; i < 8; i++)
222 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
223 IXGBE_READ_REG(hw, IXGBE_RUC);
224 IXGBE_READ_REG(hw, IXGBE_RFC);
225 IXGBE_READ_REG(hw, IXGBE_ROC);
226 IXGBE_READ_REG(hw, IXGBE_RJC);
227 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
228 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
229 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
230 IXGBE_READ_REG(hw, IXGBE_TORL);
231 IXGBE_READ_REG(hw, IXGBE_TORH);
232 IXGBE_READ_REG(hw, IXGBE_TPR);
233 IXGBE_READ_REG(hw, IXGBE_TPT);
234 IXGBE_READ_REG(hw, IXGBE_PTC64);
235 IXGBE_READ_REG(hw, IXGBE_PTC127);
236 IXGBE_READ_REG(hw, IXGBE_PTC255);
237 IXGBE_READ_REG(hw, IXGBE_PTC511);
238 IXGBE_READ_REG(hw, IXGBE_PTC1023);
239 IXGBE_READ_REG(hw, IXGBE_PTC1522);
240 IXGBE_READ_REG(hw, IXGBE_MPTC);
241 IXGBE_READ_REG(hw, IXGBE_BPTC);
242 for (i = 0; i < 16; i++) {
243 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
244 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
245 if (hw->mac.type >= ixgbe_mac_82599EB) {
246 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
247 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
248 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
249 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
250 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
252 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
253 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
257 if (hw->mac.type == ixgbe_mac_X540) {
259 hw->phy.ops.identify(hw);
260 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECL, &i);
261 hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECH, &i);
262 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECL, &i);
263 hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECH, &i);
270 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
271 * @hw: pointer to hardware structure
272 * @pba_num: stores the part number string from the EEPROM
273 * @pba_num_size: part number string buffer length
275 * Reads the part number string from the EEPROM.
277 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
286 if (pba_num == NULL) {
287 hw_dbg(hw, "PBA string buffer was null\n");
288 return IXGBE_ERR_INVALID_ARGUMENT;
291 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
293 hw_dbg(hw, "NVM Read Error\n");
297 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
299 hw_dbg(hw, "NVM Read Error\n");
304 * if data is not ptr guard the PBA must be in legacy format which
305 * means pba_ptr is actually our second data word for the PBA number
306 * and we can decode it into an ascii string
308 if (data != IXGBE_PBANUM_PTR_GUARD) {
309 hw_dbg(hw, "NVM PBA number is not stored as string\n");
311 /* we will need 11 characters to store the PBA */
312 if (pba_num_size < 11) {
313 hw_dbg(hw, "PBA string buffer too small\n");
314 return IXGBE_ERR_NO_SPACE;
317 /* extract hex string from data and pba_ptr */
318 pba_num[0] = (data >> 12) & 0xF;
319 pba_num[1] = (data >> 8) & 0xF;
320 pba_num[2] = (data >> 4) & 0xF;
321 pba_num[3] = data & 0xF;
322 pba_num[4] = (pba_ptr >> 12) & 0xF;
323 pba_num[5] = (pba_ptr >> 8) & 0xF;
326 pba_num[8] = (pba_ptr >> 4) & 0xF;
327 pba_num[9] = pba_ptr & 0xF;
329 /* put a null character on the end of our string */
332 /* switch all the data but the '-' to hex char */
333 for (offset = 0; offset < 10; offset++) {
334 if (pba_num[offset] < 0xA)
335 pba_num[offset] += '0';
336 else if (pba_num[offset] < 0x10)
337 pba_num[offset] += 'A' - 0xA;
343 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
345 hw_dbg(hw, "NVM Read Error\n");
349 if (length == 0xFFFF || length == 0) {
350 hw_dbg(hw, "NVM PBA number section invalid length\n");
351 return IXGBE_ERR_PBA_SECTION;
354 /* check if pba_num buffer is big enough */
355 if (pba_num_size < (((u32)length * 2) - 1)) {
356 hw_dbg(hw, "PBA string buffer too small\n");
357 return IXGBE_ERR_NO_SPACE;
360 /* trim pba length from start of string */
364 for (offset = 0; offset < length; offset++) {
365 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
367 hw_dbg(hw, "NVM Read Error\n");
370 pba_num[offset * 2] = (u8)(data >> 8);
371 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
373 pba_num[offset * 2] = '\0';
379 * ixgbe_get_mac_addr_generic - Generic get MAC address
380 * @hw: pointer to hardware structure
381 * @mac_addr: Adapter MAC address
383 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
384 * A reset of the adapter must be performed prior to calling this function
385 * in order for the MAC address to have been loaded from the EEPROM into RAR0
387 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
393 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
394 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
396 for (i = 0; i < 4; i++)
397 mac_addr[i] = (u8)(rar_low >> (i*8));
399 for (i = 0; i < 2; i++)
400 mac_addr[i+4] = (u8)(rar_high >> (i*8));
406 * ixgbe_get_bus_info_generic - Generic set PCI bus info
407 * @hw: pointer to hardware structure
409 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
411 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
413 struct ixgbe_adapter *adapter = hw->back;
414 struct ixgbe_mac_info *mac = &hw->mac;
417 hw->bus.type = ixgbe_bus_type_pci_express;
419 /* Get the negotiated link width and speed from PCI config space */
420 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
423 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
424 case IXGBE_PCI_LINK_WIDTH_1:
425 hw->bus.width = ixgbe_bus_width_pcie_x1;
427 case IXGBE_PCI_LINK_WIDTH_2:
428 hw->bus.width = ixgbe_bus_width_pcie_x2;
430 case IXGBE_PCI_LINK_WIDTH_4:
431 hw->bus.width = ixgbe_bus_width_pcie_x4;
433 case IXGBE_PCI_LINK_WIDTH_8:
434 hw->bus.width = ixgbe_bus_width_pcie_x8;
437 hw->bus.width = ixgbe_bus_width_unknown;
441 switch (link_status & IXGBE_PCI_LINK_SPEED) {
442 case IXGBE_PCI_LINK_SPEED_2500:
443 hw->bus.speed = ixgbe_bus_speed_2500;
445 case IXGBE_PCI_LINK_SPEED_5000:
446 hw->bus.speed = ixgbe_bus_speed_5000;
449 hw->bus.speed = ixgbe_bus_speed_unknown;
453 mac->ops.set_lan_id(hw);
459 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
460 * @hw: pointer to the HW structure
462 * Determines the LAN function id by reading memory-mapped registers
463 * and swaps the port value if requested.
465 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
467 struct ixgbe_bus_info *bus = &hw->bus;
470 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
471 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
472 bus->lan_id = bus->func;
474 /* check for a port swap */
475 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
476 if (reg & IXGBE_FACTPS_LFS)
481 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
482 * @hw: pointer to hardware structure
484 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
485 * disables transmit and receive units. The adapter_stopped flag is used by
486 * the shared code and drivers to determine if the adapter is in a stopped
487 * state and should not touch the hardware.
489 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
491 u32 number_of_queues;
496 * Set the adapter_stopped flag so other driver functions stop touching
499 hw->adapter_stopped = true;
501 /* Disable the receive unit */
502 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
503 reg_val &= ~(IXGBE_RXCTRL_RXEN);
504 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
505 IXGBE_WRITE_FLUSH(hw);
508 /* Clear interrupt mask to stop from interrupts being generated */
509 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
511 /* Clear any pending interrupts */
512 IXGBE_READ_REG(hw, IXGBE_EICR);
514 /* Disable the transmit unit. Each queue must be disabled. */
515 number_of_queues = hw->mac.max_tx_queues;
516 for (i = 0; i < number_of_queues; i++) {
517 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
518 if (reg_val & IXGBE_TXDCTL_ENABLE) {
519 reg_val &= ~IXGBE_TXDCTL_ENABLE;
520 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
525 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
526 * access and verify no pending requests
528 ixgbe_disable_pcie_master(hw);
534 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
535 * @hw: pointer to hardware structure
536 * @index: led number to turn on
538 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
540 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
542 /* To turn on the LED, set mode to ON. */
543 led_reg &= ~IXGBE_LED_MODE_MASK(index);
544 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
545 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
546 IXGBE_WRITE_FLUSH(hw);
552 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
553 * @hw: pointer to hardware structure
554 * @index: led number to turn off
556 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
558 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
560 /* To turn off the LED, set mode to OFF. */
561 led_reg &= ~IXGBE_LED_MODE_MASK(index);
562 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
563 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
564 IXGBE_WRITE_FLUSH(hw);
570 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
571 * @hw: pointer to hardware structure
573 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
574 * ixgbe_hw struct in order to set up EEPROM access.
576 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
578 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
582 if (eeprom->type == ixgbe_eeprom_uninitialized) {
583 eeprom->type = ixgbe_eeprom_none;
584 /* Set default semaphore delay to 10ms which is a well
586 eeprom->semaphore_delay = 10;
589 * Check for EEPROM present first.
590 * If not present leave as none
592 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
593 if (eec & IXGBE_EEC_PRES) {
594 eeprom->type = ixgbe_eeprom_spi;
597 * SPI EEPROM is assumed here. This code would need to
598 * change if a future EEPROM is not SPI.
600 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
601 IXGBE_EEC_SIZE_SHIFT);
602 eeprom->word_size = 1 << (eeprom_size +
603 IXGBE_EEPROM_WORD_SIZE_SHIFT);
606 if (eec & IXGBE_EEC_ADDR_SIZE)
607 eeprom->address_bits = 16;
609 eeprom->address_bits = 8;
610 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
611 "%d\n", eeprom->type, eeprom->word_size,
612 eeprom->address_bits);
619 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
620 * @hw: pointer to hardware structure
621 * @offset: offset within the EEPROM to be written to
622 * @data: 16 bit word to be written to the EEPROM
624 * If ixgbe_eeprom_update_checksum is not called after this function, the
625 * EEPROM will most likely contain an invalid checksum.
627 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
630 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
632 hw->eeprom.ops.init_params(hw);
634 if (offset >= hw->eeprom.word_size) {
635 status = IXGBE_ERR_EEPROM;
639 /* Prepare the EEPROM for writing */
640 status = ixgbe_acquire_eeprom(hw);
643 if (ixgbe_ready_eeprom(hw) != 0) {
644 ixgbe_release_eeprom(hw);
645 status = IXGBE_ERR_EEPROM;
650 ixgbe_standby_eeprom(hw);
652 /* Send the WRITE ENABLE command (8 bit opcode ) */
653 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
654 IXGBE_EEPROM_OPCODE_BITS);
656 ixgbe_standby_eeprom(hw);
659 * Some SPI eeproms use the 8th address bit embedded in the
662 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
663 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
665 /* Send the Write command (8-bit opcode + addr) */
666 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
667 IXGBE_EEPROM_OPCODE_BITS);
668 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
669 hw->eeprom.address_bits);
672 data = (data >> 8) | (data << 8);
673 ixgbe_shift_out_eeprom_bits(hw, data, 16);
674 ixgbe_standby_eeprom(hw);
676 /* Done with writing - release the EEPROM */
677 ixgbe_release_eeprom(hw);
685 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
686 * @hw: pointer to hardware structure
687 * @offset: offset within the EEPROM to be read
688 * @data: read 16 bit value from EEPROM
690 * Reads 16 bit value from EEPROM through bit-bang method
692 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
697 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
699 hw->eeprom.ops.init_params(hw);
701 if (offset >= hw->eeprom.word_size) {
702 status = IXGBE_ERR_EEPROM;
706 /* Prepare the EEPROM for reading */
707 status = ixgbe_acquire_eeprom(hw);
710 if (ixgbe_ready_eeprom(hw) != 0) {
711 ixgbe_release_eeprom(hw);
712 status = IXGBE_ERR_EEPROM;
717 ixgbe_standby_eeprom(hw);
720 * Some SPI eeproms use the 8th address bit embedded in the
723 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
724 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
726 /* Send the READ command (opcode + addr) */
727 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
728 IXGBE_EEPROM_OPCODE_BITS);
729 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
730 hw->eeprom.address_bits);
733 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
734 *data = (word_in >> 8) | (word_in << 8);
736 /* End this read operation */
737 ixgbe_release_eeprom(hw);
745 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
746 * @hw: pointer to hardware structure
747 * @offset: offset of word in the EEPROM to read
748 * @data: word read from the EEPROM
750 * Reads a 16 bit word from the EEPROM using the EERD register.
752 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
757 hw->eeprom.ops.init_params(hw);
759 if (offset >= hw->eeprom.word_size) {
760 status = IXGBE_ERR_EEPROM;
764 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
765 IXGBE_EEPROM_RW_REG_START;
767 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
768 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
771 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
772 IXGBE_EEPROM_RW_REG_DATA);
774 hw_dbg(hw, "Eeprom read timed out\n");
781 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
782 * @hw: pointer to hardware structure
783 * @ee_reg: EEPROM flag for polling
785 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
786 * read or write is done respectively.
788 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
792 s32 status = IXGBE_ERR_EEPROM;
794 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
795 if (ee_reg == IXGBE_NVM_POLL_READ)
796 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
798 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
800 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
810 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
811 * @hw: pointer to hardware structure
813 * Prepares EEPROM for access using bit-bang method. This function should
814 * be called before issuing a command to the EEPROM.
816 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
822 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
823 status = IXGBE_ERR_SWFW_SYNC;
826 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
828 /* Request EEPROM Access */
829 eec |= IXGBE_EEC_REQ;
830 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
832 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
833 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
834 if (eec & IXGBE_EEC_GNT)
839 /* Release if grant not acquired */
840 if (!(eec & IXGBE_EEC_GNT)) {
841 eec &= ~IXGBE_EEC_REQ;
842 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
843 hw_dbg(hw, "Could not acquire EEPROM grant\n");
845 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
846 status = IXGBE_ERR_EEPROM;
849 /* Setup EEPROM for Read/Write */
851 /* Clear CS and SK */
852 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
853 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
854 IXGBE_WRITE_FLUSH(hw);
862 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
863 * @hw: pointer to hardware structure
865 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
867 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
869 s32 status = IXGBE_ERR_EEPROM;
874 /* Get SMBI software semaphore between device drivers first */
875 for (i = 0; i < timeout; i++) {
877 * If the SMBI bit is 0 when we read it, then the bit will be
878 * set and we have the semaphore
880 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
881 if (!(swsm & IXGBE_SWSM_SMBI)) {
888 /* Now get the semaphore between SW/FW through the SWESMBI bit */
890 for (i = 0; i < timeout; i++) {
891 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
893 /* Set the SW EEPROM semaphore bit to request access */
894 swsm |= IXGBE_SWSM_SWESMBI;
895 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
898 * If we set the bit successfully then we got the
901 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
902 if (swsm & IXGBE_SWSM_SWESMBI)
909 * Release semaphores and return error if SW EEPROM semaphore
910 * was not granted because we don't have access to the EEPROM
913 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
915 ixgbe_release_eeprom_semaphore(hw);
916 status = IXGBE_ERR_EEPROM;
919 hw_dbg(hw, "Software semaphore SMBI between device drivers "
927 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
928 * @hw: pointer to hardware structure
930 * This function clears hardware semaphore bits.
932 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
936 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
938 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
939 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
940 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
941 IXGBE_WRITE_FLUSH(hw);
945 * ixgbe_ready_eeprom - Polls for EEPROM ready
946 * @hw: pointer to hardware structure
948 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
955 * Read "Status Register" repeatedly until the LSB is cleared. The
956 * EEPROM will signal that the command has been completed by clearing
957 * bit 0 of the internal status register. If it's not cleared within
958 * 5 milliseconds, then error out.
960 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
961 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
962 IXGBE_EEPROM_OPCODE_BITS);
963 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
964 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
968 ixgbe_standby_eeprom(hw);
972 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
973 * devices (and only 0-5mSec on 5V devices)
975 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
976 hw_dbg(hw, "SPI EEPROM Status error\n");
977 status = IXGBE_ERR_EEPROM;
984 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
985 * @hw: pointer to hardware structure
987 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
991 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
993 /* Toggle CS to flush commands */
995 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
996 IXGBE_WRITE_FLUSH(hw);
998 eec &= ~IXGBE_EEC_CS;
999 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1000 IXGBE_WRITE_FLUSH(hw);
1005 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1006 * @hw: pointer to hardware structure
1007 * @data: data to send to the EEPROM
1008 * @count: number of bits to shift out
1010 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1017 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1020 * Mask is used to shift "count" bits of "data" out to the EEPROM
1021 * one bit at a time. Determine the starting bit based on count
1023 mask = 0x01 << (count - 1);
1025 for (i = 0; i < count; i++) {
1027 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1028 * "1", and then raising and then lowering the clock (the SK
1029 * bit controls the clock input to the EEPROM). A "0" is
1030 * shifted out to the EEPROM by setting "DI" to "0" and then
1031 * raising and then lowering the clock.
1034 eec |= IXGBE_EEC_DI;
1036 eec &= ~IXGBE_EEC_DI;
1038 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1039 IXGBE_WRITE_FLUSH(hw);
1043 ixgbe_raise_eeprom_clk(hw, &eec);
1044 ixgbe_lower_eeprom_clk(hw, &eec);
1047 * Shift mask to signify next bit of data to shift in to the
1053 /* We leave the "DI" bit set to "0" when we leave this routine. */
1054 eec &= ~IXGBE_EEC_DI;
1055 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1056 IXGBE_WRITE_FLUSH(hw);
1060 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1061 * @hw: pointer to hardware structure
1063 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1070 * In order to read a register from the EEPROM, we need to shift
1071 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1072 * the clock input to the EEPROM (setting the SK bit), and then reading
1073 * the value of the "DO" bit. During this "shifting in" process the
1074 * "DI" bit should always be clear.
1076 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1078 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1080 for (i = 0; i < count; i++) {
1082 ixgbe_raise_eeprom_clk(hw, &eec);
1084 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1086 eec &= ~(IXGBE_EEC_DI);
1087 if (eec & IXGBE_EEC_DO)
1090 ixgbe_lower_eeprom_clk(hw, &eec);
1097 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1098 * @hw: pointer to hardware structure
1099 * @eec: EEC register's current value
1101 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1104 * Raise the clock input to the EEPROM
1105 * (setting the SK bit), then delay
1107 *eec = *eec | IXGBE_EEC_SK;
1108 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1109 IXGBE_WRITE_FLUSH(hw);
1114 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1115 * @hw: pointer to hardware structure
1116 * @eecd: EECD's current value
1118 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1121 * Lower the clock input to the EEPROM (clearing the SK bit), then
1124 *eec = *eec & ~IXGBE_EEC_SK;
1125 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1126 IXGBE_WRITE_FLUSH(hw);
1131 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1132 * @hw: pointer to hardware structure
1134 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1138 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1140 eec |= IXGBE_EEC_CS; /* Pull CS high */
1141 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1143 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1144 IXGBE_WRITE_FLUSH(hw);
1148 /* Stop requesting EEPROM access */
1149 eec &= ~IXGBE_EEC_REQ;
1150 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1152 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1154 /* Delay before attempt to obtain semaphore again to allow FW access */
1155 msleep(hw->eeprom.semaphore_delay);
1159 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1160 * @hw: pointer to hardware structure
1162 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1171 /* Include 0x0-0x3F in the checksum */
1172 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1173 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1174 hw_dbg(hw, "EEPROM read failed\n");
1180 /* Include all data from pointers except for the fw pointer */
1181 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1182 hw->eeprom.ops.read(hw, i, &pointer);
1184 /* Make sure the pointer seems valid */
1185 if (pointer != 0xFFFF && pointer != 0) {
1186 hw->eeprom.ops.read(hw, pointer, &length);
1188 if (length != 0xFFFF && length != 0) {
1189 for (j = pointer+1; j <= pointer+length; j++) {
1190 hw->eeprom.ops.read(hw, j, &word);
1197 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1203 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1204 * @hw: pointer to hardware structure
1205 * @checksum_val: calculated checksum
1207 * Performs checksum calculation and validates the EEPROM checksum. If the
1208 * caller does not need checksum_val, the value can be NULL.
1210 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1215 u16 read_checksum = 0;
1218 * Read the first word from the EEPROM. If this times out or fails, do
1219 * not continue or we could be in for a very long wait while every
1222 status = hw->eeprom.ops.read(hw, 0, &checksum);
1225 checksum = hw->eeprom.ops.calc_checksum(hw);
1227 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1230 * Verify read checksum from EEPROM is the same as
1231 * calculated checksum
1233 if (read_checksum != checksum)
1234 status = IXGBE_ERR_EEPROM_CHECKSUM;
1236 /* If the user cares, return the calculated checksum */
1238 *checksum_val = checksum;
1240 hw_dbg(hw, "EEPROM read failed\n");
1247 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1248 * @hw: pointer to hardware structure
1250 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1256 * Read the first word from the EEPROM. If this times out or fails, do
1257 * not continue or we could be in for a very long wait while every
1260 status = hw->eeprom.ops.read(hw, 0, &checksum);
1263 checksum = hw->eeprom.ops.calc_checksum(hw);
1264 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1267 hw_dbg(hw, "EEPROM read failed\n");
1274 * ixgbe_validate_mac_addr - Validate MAC address
1275 * @mac_addr: pointer to MAC address.
1277 * Tests a MAC address to ensure it is a valid Individual Address
1279 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1283 /* Make sure it is not a multicast address */
1284 if (IXGBE_IS_MULTICAST(mac_addr))
1285 status = IXGBE_ERR_INVALID_MAC_ADDR;
1286 /* Not a broadcast address */
1287 else if (IXGBE_IS_BROADCAST(mac_addr))
1288 status = IXGBE_ERR_INVALID_MAC_ADDR;
1289 /* Reject the zero address */
1290 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1291 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
1292 status = IXGBE_ERR_INVALID_MAC_ADDR;
1298 * ixgbe_set_rar_generic - Set Rx address register
1299 * @hw: pointer to hardware structure
1300 * @index: Receive address register to write
1301 * @addr: Address to put into receive address register
1302 * @vmdq: VMDq "set" or "pool" index
1303 * @enable_addr: set flag that address is active
1305 * Puts an ethernet address into a receive address register.
1307 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1310 u32 rar_low, rar_high;
1311 u32 rar_entries = hw->mac.num_rar_entries;
1313 /* Make sure we are using a valid rar index range */
1314 if (index >= rar_entries) {
1315 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1316 return IXGBE_ERR_INVALID_ARGUMENT;
1319 /* setup VMDq pool selection before this RAR gets enabled */
1320 hw->mac.ops.set_vmdq(hw, index, vmdq);
1323 * HW expects these in little endian so we reverse the byte
1324 * order from network order (big endian) to little endian
1326 rar_low = ((u32)addr[0] |
1327 ((u32)addr[1] << 8) |
1328 ((u32)addr[2] << 16) |
1329 ((u32)addr[3] << 24));
1331 * Some parts put the VMDq setting in the extra RAH bits,
1332 * so save everything except the lower 16 bits that hold part
1333 * of the address and the address valid bit.
1335 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1336 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1337 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1339 if (enable_addr != 0)
1340 rar_high |= IXGBE_RAH_AV;
1342 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1343 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1349 * ixgbe_clear_rar_generic - Remove Rx address register
1350 * @hw: pointer to hardware structure
1351 * @index: Receive address register to write
1353 * Clears an ethernet address from a receive address register.
1355 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1358 u32 rar_entries = hw->mac.num_rar_entries;
1360 /* Make sure we are using a valid rar index range */
1361 if (index >= rar_entries) {
1362 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1363 return IXGBE_ERR_INVALID_ARGUMENT;
1367 * Some parts put the VMDq setting in the extra RAH bits,
1368 * so save everything except the lower 16 bits that hold part
1369 * of the address and the address valid bit.
1371 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1372 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1374 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1375 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1377 /* clear VMDq pool/queue selection for this RAR */
1378 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1384 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1385 * @hw: pointer to hardware structure
1387 * Places the MAC address in receive address register 0 and clears the rest
1388 * of the receive address registers. Clears the multicast table. Assumes
1389 * the receiver is in reset when the routine is called.
1391 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1394 u32 rar_entries = hw->mac.num_rar_entries;
1397 * If the current mac address is valid, assume it is a software override
1398 * to the permanent address.
1399 * Otherwise, use the permanent address from the eeprom.
1401 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1402 IXGBE_ERR_INVALID_MAC_ADDR) {
1403 /* Get the MAC address from the RAR0 for later reference */
1404 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1406 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1408 /* Setup the receive address. */
1409 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1410 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1412 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1414 /* clear VMDq pool/queue selection for RAR 0 */
1415 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1417 hw->addr_ctrl.overflow_promisc = 0;
1419 hw->addr_ctrl.rar_used_count = 1;
1421 /* Zero out the other receive addresses. */
1422 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1423 for (i = 1; i < rar_entries; i++) {
1424 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1425 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1429 hw->addr_ctrl.mta_in_use = 0;
1430 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1432 hw_dbg(hw, " Clearing MTA\n");
1433 for (i = 0; i < hw->mac.mcft_size; i++)
1434 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1436 if (hw->mac.ops.init_uta_tables)
1437 hw->mac.ops.init_uta_tables(hw);
1443 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1444 * @hw: pointer to hardware structure
1445 * @mc_addr: the multicast address
1447 * Extracts the 12 bits, from a multicast address, to determine which
1448 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1449 * incoming rx multicast addresses, to determine the bit-vector to check in
1450 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1451 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1452 * to mc_filter_type.
1454 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1458 switch (hw->mac.mc_filter_type) {
1459 case 0: /* use bits [47:36] of the address */
1460 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1462 case 1: /* use bits [46:35] of the address */
1463 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1465 case 2: /* use bits [45:34] of the address */
1466 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1468 case 3: /* use bits [43:32] of the address */
1469 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1471 default: /* Invalid mc_filter_type */
1472 hw_dbg(hw, "MC filter type param set incorrectly\n");
1476 /* vector can only be 12-bits or boundary will be exceeded */
1482 * ixgbe_set_mta - Set bit-vector in multicast table
1483 * @hw: pointer to hardware structure
1484 * @hash_value: Multicast address hash value
1486 * Sets the bit-vector in the multicast table.
1488 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1494 hw->addr_ctrl.mta_in_use++;
1496 vector = ixgbe_mta_vector(hw, mc_addr);
1497 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1500 * The MTA is a register array of 128 32-bit registers. It is treated
1501 * like an array of 4096 bits. We want to set bit
1502 * BitArray[vector_value]. So we figure out what register the bit is
1503 * in, read it, OR in the new bit, then write back the new value. The
1504 * register is determined by the upper 7 bits of the vector value and
1505 * the bit within that register are determined by the lower 5 bits of
1508 vector_reg = (vector >> 5) & 0x7F;
1509 vector_bit = vector & 0x1F;
1510 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
1514 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1515 * @hw: pointer to hardware structure
1516 * @netdev: pointer to net device structure
1518 * The given list replaces any existing list. Clears the MC addrs from receive
1519 * address registers and the multicast table. Uses unused receive address
1520 * registers for the first multicast addresses, and hashes the rest into the
1523 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1524 struct net_device *netdev)
1526 struct netdev_hw_addr *ha;
1530 * Set the new number of MC addresses that we are being requested to
1533 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
1534 hw->addr_ctrl.mta_in_use = 0;
1536 /* Clear mta_shadow */
1537 hw_dbg(hw, " Clearing MTA\n");
1538 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
1540 /* Update mta shadow */
1541 netdev_for_each_mc_addr(ha, netdev) {
1542 hw_dbg(hw, " Adding the multicast addresses:\n");
1543 ixgbe_set_mta(hw, ha->addr);
1547 for (i = 0; i < hw->mac.mcft_size; i++)
1548 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1549 hw->mac.mta_shadow[i]);
1551 if (hw->addr_ctrl.mta_in_use > 0)
1552 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1553 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1555 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
1560 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1561 * @hw: pointer to hardware structure
1563 * Enables multicast address in RAR and the use of the multicast hash table.
1565 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1567 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1569 if (a->mta_in_use > 0)
1570 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1571 hw->mac.mc_filter_type);
1577 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1578 * @hw: pointer to hardware structure
1580 * Disables multicast address in RAR and the use of the multicast hash table.
1582 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1584 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1586 if (a->mta_in_use > 0)
1587 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1593 * ixgbe_fc_enable_generic - Enable flow control
1594 * @hw: pointer to hardware structure
1595 * @packetbuf_num: packet buffer number (0-7)
1597 * Enable flow control according to the current settings.
1599 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1602 u32 mflcn_reg, fccfg_reg;
1608 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1611 #endif /* CONFIG_DCB */
1612 /* Negotiate the fc mode to use */
1613 ret_val = ixgbe_fc_autoneg(hw);
1614 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
1617 /* Disable any previous flow control settings */
1618 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1619 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1621 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1622 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1625 * The possible values of fc.current_mode are:
1626 * 0: Flow control is completely disabled
1627 * 1: Rx flow control is enabled (we can receive pause frames,
1628 * but not send pause frames).
1629 * 2: Tx flow control is enabled (we can send pause frames but
1630 * we do not support receiving pause frames).
1631 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1633 * 4: Priority Flow Control is enabled.
1637 switch (hw->fc.current_mode) {
1640 * Flow control is disabled by software override or autoneg.
1641 * The code below will actually disable it in the HW.
1644 case ixgbe_fc_rx_pause:
1646 * Rx Flow control is enabled and Tx Flow control is
1647 * disabled by software override. Since there really
1648 * isn't a way to advertise that we are capable of RX
1649 * Pause ONLY, we will advertise that we support both
1650 * symmetric and asymmetric Rx PAUSE. Later, we will
1651 * disable the adapter's ability to send PAUSE frames.
1653 mflcn_reg |= IXGBE_MFLCN_RFCE;
1655 case ixgbe_fc_tx_pause:
1657 * Tx Flow control is enabled, and Rx Flow control is
1658 * disabled by software override.
1660 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1663 /* Flow control (both Rx and Tx) is enabled by SW override. */
1664 mflcn_reg |= IXGBE_MFLCN_RFCE;
1665 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1671 #endif /* CONFIG_DCB */
1673 hw_dbg(hw, "Flow control param set incorrectly\n");
1674 ret_val = IXGBE_ERR_CONFIG;
1679 /* Set 802.3x based flow control settings. */
1680 mflcn_reg |= IXGBE_MFLCN_DPF;
1681 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1682 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1684 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1685 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
1687 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
1688 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
1690 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1691 fcrth |= IXGBE_FCRTH_FCEN;
1692 if (hw->fc.send_xon)
1693 fcrtl |= IXGBE_FCRTL_XONE;
1696 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
1697 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
1699 /* Configure pause time (2 TCs per register) */
1700 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
1701 if ((packetbuf_num & 1) == 0)
1702 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1704 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1705 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1707 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1714 * ixgbe_fc_autoneg - Configure flow control
1715 * @hw: pointer to hardware structure
1717 * Compares our advertised flow control capabilities to those advertised by
1718 * our link partner, and determines the proper flow control mode to use.
1720 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1722 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
1723 ixgbe_link_speed speed;
1726 if (hw->fc.disable_fc_autoneg)
1730 * AN should have completed when the cable was plugged in.
1731 * Look for reasons to bail out. Bail out if:
1732 * - FC autoneg is disabled, or if
1735 * Since we're being called from an LSC, link is already known to be up.
1736 * So use link_up_wait_to_complete=false.
1738 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1740 ret_val = IXGBE_ERR_FLOW_CONTROL;
1744 switch (hw->phy.media_type) {
1745 /* Autoneg flow control on fiber adapters */
1746 case ixgbe_media_type_fiber:
1747 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
1748 ret_val = ixgbe_fc_autoneg_fiber(hw);
1751 /* Autoneg flow control on backplane adapters */
1752 case ixgbe_media_type_backplane:
1753 ret_val = ixgbe_fc_autoneg_backplane(hw);
1756 /* Autoneg flow control on copper adapters */
1757 case ixgbe_media_type_copper:
1758 if (ixgbe_device_supports_autoneg_fc(hw) == 0)
1759 ret_val = ixgbe_fc_autoneg_copper(hw);
1768 hw->fc.fc_was_autonegged = true;
1770 hw->fc.fc_was_autonegged = false;
1771 hw->fc.current_mode = hw->fc.requested_mode;
1777 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1778 * @hw: pointer to hardware structure
1780 * Enable flow control according on 1 gig fiber.
1782 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
1784 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1788 * On multispeed fiber at 1g, bail out if
1789 * - link is up but AN did not complete, or if
1790 * - link is up and AN completed but timed out
1793 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1794 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1795 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1796 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
1800 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1801 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1803 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
1804 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
1805 IXGBE_PCS1GANA_ASM_PAUSE,
1806 IXGBE_PCS1GANA_SYM_PAUSE,
1807 IXGBE_PCS1GANA_ASM_PAUSE);
1814 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1815 * @hw: pointer to hardware structure
1817 * Enable flow control according to IEEE clause 37.
1819 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
1821 u32 links2, anlp1_reg, autoc_reg, links;
1825 * On backplane, bail out if
1826 * - backplane autoneg was not completed, or if
1827 * - we are 82599 and link partner is not AN enabled
1829 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
1830 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
1831 hw->fc.fc_was_autonegged = false;
1832 hw->fc.current_mode = hw->fc.requested_mode;
1833 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
1837 if (hw->mac.type == ixgbe_mac_82599EB) {
1838 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1839 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1840 hw->fc.fc_was_autonegged = false;
1841 hw->fc.current_mode = hw->fc.requested_mode;
1842 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
1847 * Read the 10g AN autoc and LP ability registers and resolve
1848 * local flow control settings accordingly
1850 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1851 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1853 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
1854 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
1855 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
1862 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1863 * @hw: pointer to hardware structure
1865 * Enable flow control according to IEEE clause 37.
1867 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
1869 u16 technology_ability_reg = 0;
1870 u16 lp_technology_ability_reg = 0;
1872 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1874 &technology_ability_reg);
1875 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
1877 &lp_technology_ability_reg);
1879 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1880 (u32)lp_technology_ability_reg,
1881 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
1882 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
1886 * ixgbe_negotiate_fc - Negotiate flow control
1887 * @hw: pointer to hardware structure
1888 * @adv_reg: flow control advertised settings
1889 * @lp_reg: link partner's flow control settings
1890 * @adv_sym: symmetric pause bit in advertisement
1891 * @adv_asm: asymmetric pause bit in advertisement
1892 * @lp_sym: symmetric pause bit in link partner advertisement
1893 * @lp_asm: asymmetric pause bit in link partner advertisement
1895 * Find the intersection between advertised settings and link partner's
1896 * advertised settings
1898 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1899 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
1901 if ((!(adv_reg)) || (!(lp_reg)))
1902 return IXGBE_ERR_FC_NOT_NEGOTIATED;
1904 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
1906 * Now we need to check if the user selected Rx ONLY
1907 * of pause frames. In this case, we had to advertise
1908 * FULL flow control because we could not advertise RX
1909 * ONLY. Hence, we must now check to see if we need to
1910 * turn OFF the TRANSMISSION of PAUSE frames.
1912 if (hw->fc.requested_mode == ixgbe_fc_full) {
1913 hw->fc.current_mode = ixgbe_fc_full;
1914 hw_dbg(hw, "Flow Control = FULL.\n");
1916 hw->fc.current_mode = ixgbe_fc_rx_pause;
1917 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
1919 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1920 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1921 hw->fc.current_mode = ixgbe_fc_tx_pause;
1922 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1923 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1924 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1925 hw->fc.current_mode = ixgbe_fc_rx_pause;
1926 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1928 hw->fc.current_mode = ixgbe_fc_none;
1929 hw_dbg(hw, "Flow Control = NONE.\n");
1935 * ixgbe_setup_fc - Set up flow control
1936 * @hw: pointer to hardware structure
1938 * Called at init time to set up flow control.
1940 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1943 u32 reg = 0, reg_bp = 0;
1947 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1948 hw->fc.current_mode = hw->fc.requested_mode;
1952 #endif /* CONFIG_DCB */
1953 /* Validate the packetbuf configuration */
1954 if (packetbuf_num < 0 || packetbuf_num > 7) {
1955 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1956 "is 0-7\n", packetbuf_num);
1957 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1962 * Validate the water mark configuration. Zero water marks are invalid
1963 * because it causes the controller to just blast out fc packets.
1965 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1966 hw_dbg(hw, "Invalid water mark configuration\n");
1967 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1972 * Validate the requested mode. Strict IEEE mode does not allow
1973 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1975 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1976 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1978 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1983 * 10gig parts do not have a word in the EEPROM to determine the
1984 * default flow control setting, so we explicitly set it to full.
1986 if (hw->fc.requested_mode == ixgbe_fc_default)
1987 hw->fc.requested_mode = ixgbe_fc_full;
1990 * Set up the 1G and 10G flow control advertisement registers so the
1991 * HW will be able to do fc autoneg once the cable is plugged in. If
1992 * we link at 10G, the 1G advertisement is harmless and vice versa.
1995 switch (hw->phy.media_type) {
1996 case ixgbe_media_type_fiber:
1997 case ixgbe_media_type_backplane:
1998 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1999 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2002 case ixgbe_media_type_copper:
2003 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2004 MDIO_MMD_AN, ®_cu);
2012 * The possible values of fc.requested_mode are:
2013 * 0: Flow control is completely disabled
2014 * 1: Rx flow control is enabled (we can receive pause frames,
2015 * but not send pause frames).
2016 * 2: Tx flow control is enabled (we can send pause frames but
2017 * we do not support receiving pause frames).
2018 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2020 * 4: Priority Flow Control is enabled.
2024 switch (hw->fc.requested_mode) {
2026 /* Flow control completely disabled by software override. */
2027 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2028 if (hw->phy.media_type == ixgbe_media_type_backplane)
2029 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
2030 IXGBE_AUTOC_ASM_PAUSE);
2031 else if (hw->phy.media_type == ixgbe_media_type_copper)
2032 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2034 case ixgbe_fc_rx_pause:
2036 * Rx Flow control is enabled and Tx Flow control is
2037 * disabled by software override. Since there really
2038 * isn't a way to advertise that we are capable of RX
2039 * Pause ONLY, we will advertise that we support both
2040 * symmetric and asymmetric Rx PAUSE. Later, we will
2041 * disable the adapter's ability to send PAUSE frames.
2043 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2044 if (hw->phy.media_type == ixgbe_media_type_backplane)
2045 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2046 IXGBE_AUTOC_ASM_PAUSE);
2047 else if (hw->phy.media_type == ixgbe_media_type_copper)
2048 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2050 case ixgbe_fc_tx_pause:
2052 * Tx Flow control is enabled, and Rx Flow control is
2053 * disabled by software override.
2055 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2056 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
2057 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2058 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
2059 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
2060 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
2061 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
2062 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
2066 /* Flow control (both Rx and Tx) is enabled by SW override. */
2067 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2068 if (hw->phy.media_type == ixgbe_media_type_backplane)
2069 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2070 IXGBE_AUTOC_ASM_PAUSE);
2071 else if (hw->phy.media_type == ixgbe_media_type_copper)
2072 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2078 #endif /* CONFIG_DCB */
2080 hw_dbg(hw, "Flow control param set incorrectly\n");
2081 ret_val = IXGBE_ERR_CONFIG;
2086 if (hw->mac.type != ixgbe_mac_X540) {
2088 * Enable auto-negotiation between the MAC & PHY;
2089 * the MAC will advertise clause 37 flow control.
2091 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2092 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
2094 /* Disable AN timeout */
2095 if (hw->fc.strict_ieee)
2096 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2098 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2099 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2103 * AUTOC restart handles negotiation of 1G and 10G on backplane
2104 * and copper. There is no need to set the PCS1GCTL register.
2107 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2108 reg_bp |= IXGBE_AUTOC_AN_RESTART;
2109 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
2110 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
2111 (ixgbe_device_supports_autoneg_fc(hw) == 0)) {
2112 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
2113 MDIO_MMD_AN, reg_cu);
2116 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2122 * ixgbe_disable_pcie_master - Disable PCI-express master access
2123 * @hw: pointer to hardware structure
2125 * Disables PCI-Express master access and verifies there are no pending
2126 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2127 * bit hasn't caused the master requests to be disabled, else 0
2128 * is returned signifying master requests disabled.
2130 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2132 struct ixgbe_adapter *adapter = hw->back;
2135 u32 number_of_queues;
2139 /* Just jump out if bus mastering is already disabled */
2140 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2143 /* Disable the receive unit by stopping each queue */
2144 number_of_queues = hw->mac.max_rx_queues;
2145 for (i = 0; i < number_of_queues; i++) {
2146 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2147 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2148 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2149 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2153 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2154 reg_val |= IXGBE_CTRL_GIO_DIS;
2155 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2157 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2158 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2159 goto check_device_status;
2163 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2164 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2167 * Before proceeding, make sure that the PCIe block does not have
2168 * transactions pending.
2170 check_device_status:
2171 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2172 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2174 if (!(dev_status & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2179 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2180 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2185 * Two consecutive resets are required via CTRL.RST per datasheet
2186 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2187 * of this need. The first reset prevents new master requests from
2188 * being issued by our device. We then must wait 1usec for any
2189 * remaining completions from the PCIe bus to trickle in, and then reset
2190 * again to clear out any effects they may have had on our device.
2192 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2200 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2201 * @hw: pointer to hardware structure
2202 * @mask: Mask to specify which semaphore to acquire
2204 * Acquires the SWFW semaphore through the GSSR register for the specified
2205 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2207 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2211 u32 fwmask = mask << 5;
2216 * SW EEPROM semaphore bit is used for access to all
2217 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2219 if (ixgbe_get_eeprom_semaphore(hw))
2220 return IXGBE_ERR_SWFW_SYNC;
2222 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2223 if (!(gssr & (fwmask | swmask)))
2227 * Firmware currently using resource (fwmask) or other software
2228 * thread currently using resource (swmask)
2230 ixgbe_release_eeprom_semaphore(hw);
2236 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
2237 return IXGBE_ERR_SWFW_SYNC;
2241 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2243 ixgbe_release_eeprom_semaphore(hw);
2248 * ixgbe_release_swfw_sync - Release SWFW semaphore
2249 * @hw: pointer to hardware structure
2250 * @mask: Mask to specify which semaphore to release
2252 * Releases the SWFW semaphore through the GSSR register for the specified
2253 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2255 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2260 ixgbe_get_eeprom_semaphore(hw);
2262 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2264 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2266 ixgbe_release_eeprom_semaphore(hw);
2270 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2271 * @hw: pointer to hardware structure
2272 * @regval: register value to write to RXCTRL
2274 * Enables the Rx DMA unit
2276 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2278 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2284 * ixgbe_blink_led_start_generic - Blink LED based on index.
2285 * @hw: pointer to hardware structure
2286 * @index: led number to blink
2288 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2290 ixgbe_link_speed speed = 0;
2292 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2293 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2296 * Link must be up to auto-blink the LEDs;
2297 * Force it if link is down.
2299 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2302 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2303 autoc_reg |= IXGBE_AUTOC_FLU;
2304 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2308 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2309 led_reg |= IXGBE_LED_BLINK(index);
2310 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2311 IXGBE_WRITE_FLUSH(hw);
2317 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2318 * @hw: pointer to hardware structure
2319 * @index: led number to stop blinking
2321 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2323 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2324 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2326 autoc_reg &= ~IXGBE_AUTOC_FLU;
2327 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2328 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2330 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2331 led_reg &= ~IXGBE_LED_BLINK(index);
2332 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2333 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2334 IXGBE_WRITE_FLUSH(hw);
2340 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2341 * @hw: pointer to hardware structure
2342 * @san_mac_offset: SAN MAC address offset
2344 * This function will read the EEPROM location for the SAN MAC address
2345 * pointer, and returns the value at that location. This is used in both
2346 * get and set mac_addr routines.
2348 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2349 u16 *san_mac_offset)
2352 * First read the EEPROM pointer to see if the MAC addresses are
2355 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2361 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2362 * @hw: pointer to hardware structure
2363 * @san_mac_addr: SAN MAC address
2365 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2366 * per-port, so set_lan_id() must be called before reading the addresses.
2367 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2368 * upon for non-SFP connections, so we must call it here.
2370 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2372 u16 san_mac_data, san_mac_offset;
2376 * First read the EEPROM pointer to see if the MAC addresses are
2377 * available. If they're not, no point in calling set_lan_id() here.
2379 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2381 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2383 * No addresses available in this EEPROM. It's not an
2384 * error though, so just wipe the local address and return.
2386 for (i = 0; i < 6; i++)
2387 san_mac_addr[i] = 0xFF;
2389 goto san_mac_addr_out;
2392 /* make sure we know which port we need to program */
2393 hw->mac.ops.set_lan_id(hw);
2394 /* apply the port offset to the address offset */
2395 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2396 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2397 for (i = 0; i < 3; i++) {
2398 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2399 san_mac_addr[i * 2] = (u8)(san_mac_data);
2400 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2409 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2410 * @hw: pointer to hardware structure
2412 * Read PCIe configuration space, and get the MSI-X vector count from
2413 * the capabilities table.
2415 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2417 struct ixgbe_adapter *adapter = hw->back;
2419 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2421 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2423 /* MSI-X count is zero-based in HW, so increment to give proper value */
2430 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2431 * @hw: pointer to hardware struct
2432 * @rar: receive address register index to disassociate
2433 * @vmdq: VMDq pool index to remove from the rar
2435 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2437 u32 mpsar_lo, mpsar_hi;
2438 u32 rar_entries = hw->mac.num_rar_entries;
2440 /* Make sure we are using a valid rar index range */
2441 if (rar >= rar_entries) {
2442 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2443 return IXGBE_ERR_INVALID_ARGUMENT;
2446 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2447 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2449 if (!mpsar_lo && !mpsar_hi)
2452 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2454 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2458 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2461 } else if (vmdq < 32) {
2462 mpsar_lo &= ~(1 << vmdq);
2463 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2465 mpsar_hi &= ~(1 << (vmdq - 32));
2466 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2469 /* was that the last pool using this rar? */
2470 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2471 hw->mac.ops.clear_rar(hw, rar);
2477 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2478 * @hw: pointer to hardware struct
2479 * @rar: receive address register index to associate with a VMDq index
2480 * @vmdq: VMDq pool index
2482 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2485 u32 rar_entries = hw->mac.num_rar_entries;
2487 /* Make sure we are using a valid rar index range */
2488 if (rar >= rar_entries) {
2489 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2490 return IXGBE_ERR_INVALID_ARGUMENT;
2494 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2496 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2498 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2499 mpsar |= 1 << (vmdq - 32);
2500 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2506 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2507 * @hw: pointer to hardware structure
2509 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2513 for (i = 0; i < 128; i++)
2514 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2520 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2521 * @hw: pointer to hardware structure
2522 * @vlan: VLAN id to write to VLAN filter
2524 * return the VLVF index where this VLAN id should be placed
2527 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2530 u32 first_empty_slot = 0;
2533 /* short cut the special case */
2538 * Search for the vlan id in the VLVF entries. Save off the first empty
2539 * slot found along the way
2541 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2542 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2543 if (!bits && !(first_empty_slot))
2544 first_empty_slot = regindex;
2545 else if ((bits & 0x0FFF) == vlan)
2550 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2551 * in the VLVF. Else use the first empty VLVF register for this
2554 if (regindex >= IXGBE_VLVF_ENTRIES) {
2555 if (first_empty_slot)
2556 regindex = first_empty_slot;
2558 hw_dbg(hw, "No space in VLVF.\n");
2559 regindex = IXGBE_ERR_NO_SPACE;
2567 * ixgbe_set_vfta_generic - Set VLAN filter table
2568 * @hw: pointer to hardware structure
2569 * @vlan: VLAN id to write to VLAN filter
2570 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2571 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2573 * Turn on/off specified VLAN in the VLAN filter table.
2575 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2584 bool vfta_changed = false;
2587 return IXGBE_ERR_PARAM;
2590 * this is a 2 part operation - first the VFTA, then the
2591 * VLVF and VLVFB if VT Mode is set
2592 * We don't write the VFTA until we know the VLVF part succeeded.
2596 * The VFTA is a bitstring made up of 128 32-bit registers
2597 * that enable the particular VLAN id, much like the MTA:
2598 * bits[11-5]: which register
2599 * bits[4-0]: which bit in the register
2601 regindex = (vlan >> 5) & 0x7F;
2602 bitindex = vlan & 0x1F;
2603 targetbit = (1 << bitindex);
2604 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2607 if (!(vfta & targetbit)) {
2609 vfta_changed = true;
2612 if ((vfta & targetbit)) {
2614 vfta_changed = true;
2621 * make sure the vlan is in VLVF
2622 * set the vind bit in the matching VLVFB
2624 * clear the pool bit and possibly the vind
2626 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2627 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2630 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2635 /* set the pool bit */
2637 bits = IXGBE_READ_REG(hw,
2638 IXGBE_VLVFB(vlvf_index*2));
2639 bits |= (1 << vind);
2641 IXGBE_VLVFB(vlvf_index*2),
2644 bits = IXGBE_READ_REG(hw,
2645 IXGBE_VLVFB((vlvf_index*2)+1));
2646 bits |= (1 << (vind-32));
2648 IXGBE_VLVFB((vlvf_index*2)+1),
2652 /* clear the pool bit */
2654 bits = IXGBE_READ_REG(hw,
2655 IXGBE_VLVFB(vlvf_index*2));
2656 bits &= ~(1 << vind);
2658 IXGBE_VLVFB(vlvf_index*2),
2660 bits |= IXGBE_READ_REG(hw,
2661 IXGBE_VLVFB((vlvf_index*2)+1));
2663 bits = IXGBE_READ_REG(hw,
2664 IXGBE_VLVFB((vlvf_index*2)+1));
2665 bits &= ~(1 << (vind-32));
2667 IXGBE_VLVFB((vlvf_index*2)+1),
2669 bits |= IXGBE_READ_REG(hw,
2670 IXGBE_VLVFB(vlvf_index*2));
2675 * If there are still bits set in the VLVFB registers
2676 * for the VLAN ID indicated we need to see if the
2677 * caller is requesting that we clear the VFTA entry bit.
2678 * If the caller has requested that we clear the VFTA
2679 * entry bit but there are still pools/VFs using this VLAN
2680 * ID entry then ignore the request. We're not worried
2681 * about the case where we're turning the VFTA VLAN ID
2682 * entry bit on, only when requested to turn it off as
2683 * there may be multiple pools and/or VFs using the
2684 * VLAN ID entry. In that case we cannot clear the
2685 * VFTA bit until all pools/VFs using that VLAN ID have also
2686 * been cleared. This will be indicated by "bits" being
2690 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
2691 (IXGBE_VLVF_VIEN | vlan));
2693 /* someone wants to clear the vfta entry
2694 * but some pools/VFs are still using it.
2696 vfta_changed = false;
2700 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
2704 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
2710 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2711 * @hw: pointer to hardware structure
2713 * Clears the VLAN filer table, and the VMDq index associated with the filter
2715 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2719 for (offset = 0; offset < hw->mac.vft_size; offset++)
2720 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2722 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2723 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2724 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2725 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2732 * ixgbe_check_mac_link_generic - Determine link and speed status
2733 * @hw: pointer to hardware structure
2734 * @speed: pointer to link speed
2735 * @link_up: true when link is up
2736 * @link_up_wait_to_complete: bool used to wait for link up or not
2738 * Reads the links register to determine if link is up and the current speed
2740 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
2741 bool *link_up, bool link_up_wait_to_complete)
2743 u32 links_reg, links_orig;
2746 /* clear the old state */
2747 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
2749 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2751 if (links_orig != links_reg) {
2752 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
2753 links_orig, links_reg);
2756 if (link_up_wait_to_complete) {
2757 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2758 if (links_reg & IXGBE_LINKS_UP) {
2765 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2768 if (links_reg & IXGBE_LINKS_UP)
2774 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2775 IXGBE_LINKS_SPEED_10G_82599)
2776 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2777 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2778 IXGBE_LINKS_SPEED_1G_82599)
2779 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2780 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2781 IXGBE_LINKS_SPEED_100_82599)
2782 *speed = IXGBE_LINK_SPEED_100_FULL;
2784 *speed = IXGBE_LINK_SPEED_UNKNOWN;
2786 /* if link is down, zero out the current_mode */
2787 if (*link_up == false) {
2788 hw->fc.current_mode = ixgbe_fc_none;
2789 hw->fc.fc_was_autonegged = false;
2796 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
2798 * @hw: pointer to hardware structure
2799 * @wwnn_prefix: the alternative WWNN prefix
2800 * @wwpn_prefix: the alternative WWPN prefix
2802 * This function will read the EEPROM from the alternative SAN MAC address
2803 * block to check the support for the alternative WWNN/WWPN prefix support.
2805 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2809 u16 alt_san_mac_blk_offset;
2811 /* clear output first */
2812 *wwnn_prefix = 0xFFFF;
2813 *wwpn_prefix = 0xFFFF;
2815 /* check if alternative SAN MAC is supported */
2816 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2817 &alt_san_mac_blk_offset);
2819 if ((alt_san_mac_blk_offset == 0) ||
2820 (alt_san_mac_blk_offset == 0xFFFF))
2821 goto wwn_prefix_out;
2823 /* check capability in alternative san mac address block */
2824 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2825 hw->eeprom.ops.read(hw, offset, &caps);
2826 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2827 goto wwn_prefix_out;
2829 /* get the corresponding prefix for WWNN/WWPN */
2830 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2831 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2833 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2834 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2841 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
2843 * @hw: pointer to hardware structure
2845 * There are several phys that do not support autoneg flow control. This
2846 * function check the device id to see if the associated phy supports
2847 * autoneg flow control.
2849 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
2852 switch (hw->device_id) {
2853 case IXGBE_DEV_ID_X540T:
2855 case IXGBE_DEV_ID_82599_T3_LOM:
2858 return IXGBE_ERR_FC_NOT_SUPPORTED;
2863 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2864 * @hw: pointer to hardware structure
2865 * @enable: enable or disable switch for anti-spoofing
2866 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
2869 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
2872 int pf_target_reg = pf >> 3;
2873 int pf_target_shift = pf % 8;
2876 if (hw->mac.type == ixgbe_mac_82598EB)
2880 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
2883 * PFVFSPOOF register array is size 8 with 8 bits assigned to
2884 * MAC anti-spoof enables in each register array element.
2886 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
2887 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
2889 /* If not enabling anti-spoofing then done */
2894 * The PF should be allowed to spoof so that it can support
2895 * emulation mode NICs. Reset the bit assigned to the PF
2897 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
2898 pfvfspoof ^= (1 << pf_target_shift);
2899 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
2903 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
2904 * @hw: pointer to hardware structure
2905 * @enable: enable or disable switch for VLAN anti-spoofing
2906 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
2909 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
2911 int vf_target_reg = vf >> 3;
2912 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
2915 if (hw->mac.type == ixgbe_mac_82598EB)
2918 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2920 pfvfspoof |= (1 << vf_target_shift);
2922 pfvfspoof &= ~(1 << vf_target_shift);
2923 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);