2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
36 #define MASK(n) ((1ULL<<(n))-1)
37 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
38 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
39 #define MS_WIN(addr) (addr & 0x0ffc0000)
41 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
43 #define CRB_BLK(off) ((off >> 20) & 0x3f)
44 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
45 #define CRB_WINDOW_2M (0x130060)
46 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
47 #define CRB_INDIRECT_2M (0x1e0000UL)
50 static inline u64 readq(void __iomem *addr)
52 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
57 static inline void writeq(u64 val, void __iomem *addr)
59 writel(((u32) (val)), (addr));
60 writel(((u32) (val >> 32)), (addr + 4));
64 #define ADDR_IN_RANGE(addr, low, high) \
65 (((addr) < (high)) && ((addr) >= (low)))
67 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
68 ((adapter)->ahw.pci_base0 + (off))
69 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
70 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
71 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
72 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
74 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
77 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
78 return PCI_OFFSET_FIRST_RANGE(adapter, off);
80 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
81 return PCI_OFFSET_SECOND_RANGE(adapter, off);
83 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
84 return PCI_OFFSET_THIRD_RANGE(adapter, off);
89 static crb_128M_2M_block_map_t
90 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
91 {{{0, 0, 0, 0} } }, /* 0: PCI */
92 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
93 {1, 0x0110000, 0x0120000, 0x130000},
94 {1, 0x0120000, 0x0122000, 0x124000},
95 {1, 0x0130000, 0x0132000, 0x126000},
96 {1, 0x0140000, 0x0142000, 0x128000},
97 {1, 0x0150000, 0x0152000, 0x12a000},
98 {1, 0x0160000, 0x0170000, 0x110000},
99 {1, 0x0170000, 0x0172000, 0x12e000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {1, 0x01e0000, 0x01e0800, 0x122000},
107 {0, 0x0000000, 0x0000000, 0x000000} } },
108 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
109 {{{0, 0, 0, 0} } }, /* 3: */
110 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
111 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
112 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
113 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
114 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {1, 0x08f0000, 0x08f2000, 0x172000} } },
130 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {1, 0x09f0000, 0x09f2000, 0x176000} } },
146 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
162 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
178 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
179 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
180 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
181 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
182 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
183 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
184 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
185 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
186 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
187 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
188 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
189 {{{0, 0, 0, 0} } }, /* 23: */
190 {{{0, 0, 0, 0} } }, /* 24: */
191 {{{0, 0, 0, 0} } }, /* 25: */
192 {{{0, 0, 0, 0} } }, /* 26: */
193 {{{0, 0, 0, 0} } }, /* 27: */
194 {{{0, 0, 0, 0} } }, /* 28: */
195 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
196 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
197 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
198 {{{0} } }, /* 32: PCI */
199 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
200 {1, 0x2110000, 0x2120000, 0x130000},
201 {1, 0x2120000, 0x2122000, 0x124000},
202 {1, 0x2130000, 0x2132000, 0x126000},
203 {1, 0x2140000, 0x2142000, 0x128000},
204 {1, 0x2150000, 0x2152000, 0x12a000},
205 {1, 0x2160000, 0x2170000, 0x110000},
206 {1, 0x2170000, 0x2172000, 0x12e000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000} } },
215 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
221 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
222 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
223 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
224 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
225 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
226 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
227 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
228 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
229 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
230 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
231 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
232 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
234 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
235 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
236 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
237 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
238 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
239 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
240 {{{0} } }, /* 59: I2C0 */
241 {{{0} } }, /* 60: I2C1 */
242 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
243 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
244 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
248 * top 12 bits of crb internal address (hub, agent)
250 static unsigned crb_hub_agt[64] =
253 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
254 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
258 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
259 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
265 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
266 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
268 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
281 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
283 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
285 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
286 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
292 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
301 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
302 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
303 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
308 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
310 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
311 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
314 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
318 /* PCI Windowing for DDR regions. */
320 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
322 #define NETXEN_PCIE_SEM_TIMEOUT 10000
325 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
327 int done = 0, timeout = 0;
330 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
333 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
339 NXWR32(adapter, id_reg, adapter->portnum);
345 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
348 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
351 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
355 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
361 /* Disable an XG interface */
362 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
365 u32 port = adapter->physical_port;
367 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
370 if (port > NETXEN_NIU_MAX_XG_PORTS)
375 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
380 #define NETXEN_UNICAST_ADDR(port, index) \
381 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
382 #define NETXEN_MCAST_ADDR(port, index) \
383 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
384 #define MAC_HI(addr) \
385 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
386 #define MAC_LO(addr) \
387 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
389 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
392 u32 port = adapter->physical_port;
394 if (port > NETXEN_NIU_MAX_XG_PORTS)
397 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
398 if (mode == NETXEN_NIU_PROMISC_MODE)
399 reg = (reg | 0x2000UL);
401 reg = (reg & ~0x2000UL);
403 if (mode == NETXEN_NIU_ALLMULTI_MODE)
404 reg = (reg | 0x1000UL);
406 reg = (reg & ~0x1000UL);
408 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
413 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
418 u8 phy = adapter->physical_port;
420 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
423 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
424 mac_hi = addr[2] | ((u32)addr[3] << 8) |
425 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
427 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
428 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
430 /* write twice to flush */
431 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
433 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
440 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
443 u16 port = adapter->physical_port;
444 u8 *addr = adapter->netdev->dev_addr;
446 if (adapter->mc_enabled)
449 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
450 val |= (1UL << (28+port));
451 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
453 /* add broadcast addr to filter */
455 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
456 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
458 /* add station addr to filter */
460 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
462 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
464 adapter->mc_enabled = 1;
469 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
472 u16 port = adapter->physical_port;
473 u8 *addr = adapter->netdev->dev_addr;
475 if (!adapter->mc_enabled)
478 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
479 val &= ~(1UL << (28+port));
480 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
485 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
487 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
488 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
490 adapter->mc_enabled = 0;
495 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
499 u16 port = adapter->physical_port;
504 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
505 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
510 void netxen_p2_nic_set_multi(struct net_device *netdev)
512 struct netxen_adapter *adapter = netdev_priv(netdev);
513 struct dev_mc_list *mc_ptr;
517 memset(null_addr, 0, 6);
519 if (netdev->flags & IFF_PROMISC) {
521 adapter->set_promisc(adapter,
522 NETXEN_NIU_PROMISC_MODE);
524 /* Full promiscuous mode */
525 netxen_nic_disable_mcast_filter(adapter);
530 if (netdev->mc_count == 0) {
531 adapter->set_promisc(adapter,
532 NETXEN_NIU_NON_PROMISC_MODE);
533 netxen_nic_disable_mcast_filter(adapter);
537 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
538 if (netdev->flags & IFF_ALLMULTI ||
539 netdev->mc_count > adapter->max_mc_count) {
540 netxen_nic_disable_mcast_filter(adapter);
544 netxen_nic_enable_mcast_filter(adapter);
546 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
547 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
549 if (index != netdev->mc_count)
550 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
551 netxen_nic_driver_name, netdev->name);
553 /* Clear out remaining addresses */
554 for (; index < adapter->max_mc_count; index++)
555 netxen_nic_set_mcast_addr(adapter, index, null_addr);
559 netxen_send_cmd_descs(struct netxen_adapter *adapter,
560 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
562 u32 i, producer, consumer;
563 struct netxen_cmd_buffer *pbuf;
564 struct cmd_desc_type0 *cmd_desc;
565 struct nx_host_tx_ring *tx_ring;
569 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
572 tx_ring = adapter->tx_ring;
573 __netif_tx_lock_bh(tx_ring->txq);
575 producer = tx_ring->producer;
576 consumer = tx_ring->sw_consumer;
578 if (nr_desc >= netxen_tx_avail(tx_ring)) {
579 netif_tx_stop_queue(tx_ring->txq);
580 __netif_tx_unlock_bh(tx_ring->txq);
585 cmd_desc = &cmd_desc_arr[i];
587 pbuf = &tx_ring->cmd_buf_arr[producer];
589 pbuf->frag_count = 0;
591 memcpy(&tx_ring->desc_head[producer],
592 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
594 producer = get_next_index(producer, tx_ring->num_desc);
597 } while (i != nr_desc);
599 tx_ring->producer = producer;
601 netxen_nic_update_cmd_producer(adapter, tx_ring);
603 __netif_tx_unlock_bh(tx_ring->txq);
609 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
612 nx_mac_req_t *mac_req;
615 memset(&req, 0, sizeof(nx_nic_req_t));
616 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
618 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
619 req.req_hdr = cpu_to_le64(word);
621 mac_req = (nx_mac_req_t *)&req.words[0];
623 memcpy(mac_req->mac_addr, addr, 6);
625 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
628 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
629 u8 *addr, struct list_head *del_list)
631 struct list_head *head;
634 /* look up if already exists */
635 list_for_each(head, del_list) {
636 cur = list_entry(head, nx_mac_list_t, list);
638 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
639 list_move_tail(head, &adapter->mac_list);
644 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
646 printk(KERN_ERR "%s: failed to add mac address filter\n",
647 adapter->netdev->name);
650 memcpy(cur->mac_addr, addr, ETH_ALEN);
651 list_add_tail(&cur->list, &adapter->mac_list);
652 return nx_p3_sre_macaddr_change(adapter,
653 cur->mac_addr, NETXEN_MAC_ADD);
656 void netxen_p3_nic_set_multi(struct net_device *netdev)
658 struct netxen_adapter *adapter = netdev_priv(netdev);
659 struct dev_mc_list *mc_ptr;
660 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
661 u32 mode = VPORT_MISS_MODE_DROP;
663 struct list_head *head;
666 list_splice_tail_init(&adapter->mac_list, &del_list);
668 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
669 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
671 if (netdev->flags & IFF_PROMISC) {
672 mode = VPORT_MISS_MODE_ACCEPT_ALL;
676 if ((netdev->flags & IFF_ALLMULTI) ||
677 (netdev->mc_count > adapter->max_mc_count)) {
678 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
682 if (netdev->mc_count > 0) {
683 for (mc_ptr = netdev->mc_list; mc_ptr;
684 mc_ptr = mc_ptr->next) {
685 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
690 adapter->set_promisc(adapter, mode);
692 while (!list_empty(head)) {
693 cur = list_entry(head->next, nx_mac_list_t, list);
695 nx_p3_sre_macaddr_change(adapter,
696 cur->mac_addr, NETXEN_MAC_DEL);
697 list_del(&cur->list);
702 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
707 memset(&req, 0, sizeof(nx_nic_req_t));
709 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
711 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
712 ((u64)adapter->portnum << 16);
713 req.req_hdr = cpu_to_le64(word);
715 req.words[0] = cpu_to_le64(mode);
717 return netxen_send_cmd_descs(adapter,
718 (struct cmd_desc_type0 *)&req, 1);
721 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
724 struct list_head *head = &adapter->mac_list;
726 while (!list_empty(head)) {
727 cur = list_entry(head->next, nx_mac_list_t, list);
728 nx_p3_sre_macaddr_change(adapter,
729 cur->mac_addr, NETXEN_MAC_DEL);
730 list_del(&cur->list);
735 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
737 /* assuming caller has already copied new addr to netdev */
738 netxen_p3_nic_set_multi(adapter->netdev);
742 #define NETXEN_CONFIG_INTR_COALESCE 3
745 * Send the interrupt coalescing parameter set by ethtool to the card.
747 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
753 memset(&req, 0, sizeof(nx_nic_req_t));
755 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
757 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
758 req.req_hdr = cpu_to_le64(word);
760 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
762 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
764 printk(KERN_ERR "ERROR. Could not send "
765 "interrupt coalescing parameters\n");
771 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
777 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
780 memset(&req, 0, sizeof(nx_nic_req_t));
782 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
784 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
785 req.req_hdr = cpu_to_le64(word);
787 req.words[0] = cpu_to_le64(enable);
789 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
791 printk(KERN_ERR "ERROR. Could not send "
792 "configure hw lro request\n");
795 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
800 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
806 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
809 memset(&req, 0, sizeof(nx_nic_req_t));
811 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
813 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
814 ((u64)adapter->portnum << 16);
815 req.req_hdr = cpu_to_le64(word);
817 req.words[0] = cpu_to_le64(enable);
819 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
821 printk(KERN_ERR "ERROR. Could not send "
822 "configure bridge mode request\n");
825 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
831 #define RSS_HASHTYPE_IP_TCP 0x3
833 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
839 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
840 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
841 0x255b0ec26d5a56daULL };
844 memset(&req, 0, sizeof(nx_nic_req_t));
845 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
847 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
848 req.req_hdr = cpu_to_le64(word);
852 * bits 3-0: hash_method
853 * 5-4: hash_type_ipv4
854 * 7-6: hash_type_ipv6
856 * 9: use indirection table
858 * 63-48: indirection table mask
860 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
861 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
862 ((u64)(enable & 0x1) << 8) |
864 req.words[0] = cpu_to_le64(word);
865 for (i = 0; i < 5; i++)
866 req.words[i+1] = cpu_to_le64(key[i]);
869 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
871 printk(KERN_ERR "%s: could not configure RSS\n",
872 adapter->netdev->name);
878 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
884 memset(&req, 0, sizeof(nx_nic_req_t));
885 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
887 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
888 req.req_hdr = cpu_to_le64(word);
890 req.words[0] = cpu_to_le64(cmd);
891 req.words[1] = cpu_to_le64(ip);
893 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
895 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
896 adapter->netdev->name,
897 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
902 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
908 memset(&req, 0, sizeof(nx_nic_req_t));
909 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
911 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
912 req.req_hdr = cpu_to_le64(word);
913 req.words[0] = cpu_to_le64(enable | (enable << 8));
915 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
917 printk(KERN_ERR "%s: could not configure link notification\n",
918 adapter->netdev->name);
924 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
930 memset(&req, 0, sizeof(nx_nic_req_t));
931 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
933 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
934 ((u64)adapter->portnum << 16) |
935 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
937 req.req_hdr = cpu_to_le64(word);
939 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
941 printk(KERN_ERR "%s: could not cleanup lro flows\n",
942 adapter->netdev->name);
948 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
949 * @returns 0 on success, negative on failure
952 #define MTU_FUDGE_FACTOR 100
954 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
956 struct netxen_adapter *adapter = netdev_priv(netdev);
960 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
961 max_mtu = P3_MAX_MTU;
963 max_mtu = P2_MAX_MTU;
966 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
967 netdev->name, max_mtu);
971 if (adapter->set_mtu)
972 rc = adapter->set_mtu(adapter, mtu);
980 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
981 int size, __le32 * buf)
988 for (i = 0; i < size / sizeof(u32); i++) {
989 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
991 *ptr32 = cpu_to_le32(v);
995 if ((char *)buf + size > (char *)ptr32) {
997 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
999 local = cpu_to_le32(v);
1000 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1006 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1008 __le32 *pmac = (__le32 *) mac;
1011 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1013 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1016 if (*mac == cpu_to_le64(~0ULL)) {
1018 offset = NX_OLD_MAC_ADDR_OFFSET +
1019 (adapter->portnum * sizeof(u64));
1021 if (netxen_get_flash_block(adapter,
1022 offset, sizeof(u64), pmac) == -1)
1025 if (*mac == cpu_to_le64(~0ULL))
1031 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1033 uint32_t crbaddr, mac_hi, mac_lo;
1034 int pci_func = adapter->ahw.pci_func;
1036 crbaddr = CRB_MAC_BLOCK_START +
1037 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1039 mac_lo = NXRD32(adapter, crbaddr);
1040 mac_hi = NXRD32(adapter, crbaddr+4);
1043 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1045 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1051 * Changes the CRB window to the specified window.
1054 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
1056 void __iomem *offset;
1059 uint8_t func = adapter->ahw.pci_func;
1061 if (adapter->curr_window == wndw)
1064 * Move the CRB window.
1065 * We need to write to the "direct access" region of PCI
1066 * to avoid a race condition where the window register has
1067 * not been successfully written across CRB before the target
1068 * register address is received by PCI. The direct region bypasses
1071 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1072 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1075 wndw = NETXEN_WINDOW_ONE;
1077 writel(wndw, offset);
1079 /* MUST make sure window is set before we forge on... */
1080 while ((tmp = readl(offset)) != wndw) {
1081 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
1082 "registered properly: 0x%08x.\n",
1083 netxen_nic_driver_name, __func__, tmp);
1090 if (wndw == NETXEN_WINDOW_ONE)
1091 adapter->curr_window = 1;
1093 adapter->curr_window = 0;
1097 * Return -1 if off is not valid,
1098 * 1 if window access is needed. 'off' is set to offset from
1099 * CRB space in 128M pci map
1100 * 0 if no window access is needed. 'off' is set to 2M addr
1101 * In: 'off' is offset from base in 128M pci map
1104 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
1106 crb_128M_2M_sub_block_map_t *m;
1109 if (*off >= NETXEN_CRB_MAX)
1112 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
1113 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
1114 (ulong)adapter->ahw.pci_base0;
1118 if (*off < NETXEN_PCI_CRBSPACE)
1121 *off -= NETXEN_PCI_CRBSPACE;
1126 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
1128 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
1129 *off = *off + m->start_2M - m->start_128M +
1130 (ulong)adapter->ahw.pci_base0;
1135 * Not in direct map, use crb window
1141 * In: 'off' is offset from CRB space in 128M pci map
1142 * Out: 'off' is 2M pci map addr
1143 * side effect: lock crb window
1146 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
1150 adapter->crb_win = CRB_HI(*off);
1151 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
1153 * Read back value to make sure write has gone through before trying
1156 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
1157 if (win_read != adapter->crb_win) {
1158 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
1159 "Read crbwin (0x%x), off=0x%lx\n",
1160 __func__, adapter->crb_win, win_read, *off);
1162 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1163 (ulong)adapter->ahw.pci_base0;
1167 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1169 unsigned long flags;
1172 if (ADDR_IN_WINDOW1(off))
1173 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1175 addr = pci_base_offset(adapter, off);
1179 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1180 read_lock(&adapter->adapter_lock);
1182 read_unlock(&adapter->adapter_lock);
1183 } else { /* Window 0 */
1184 write_lock_irqsave(&adapter->adapter_lock, flags);
1185 addr = pci_base_offset(adapter, off);
1186 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1188 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1189 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1196 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1198 unsigned long flags;
1202 if (ADDR_IN_WINDOW1(off))
1203 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1205 addr = pci_base_offset(adapter, off);
1209 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1210 read_lock(&adapter->adapter_lock);
1212 read_unlock(&adapter->adapter_lock);
1213 } else { /* Window 0 */
1214 write_lock_irqsave(&adapter->adapter_lock, flags);
1215 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1217 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1218 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1225 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1227 unsigned long flags;
1230 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1233 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1240 write_lock_irqsave(&adapter->adapter_lock, flags);
1241 crb_win_lock(adapter);
1242 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1243 writel(data, (void __iomem *)off);
1244 crb_win_unlock(adapter);
1245 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1247 writel(data, (void __iomem *)off);
1254 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1256 unsigned long flags;
1260 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1263 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1270 write_lock_irqsave(&adapter->adapter_lock, flags);
1271 crb_win_lock(adapter);
1272 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1273 data = readl((void __iomem *)off);
1274 crb_win_unlock(adapter);
1275 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1277 data = readl((void __iomem *)off);
1282 static int netxen_pci_set_window_warning_count;
1284 static unsigned long
1285 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1286 unsigned long long addr)
1288 void __iomem *offset;
1290 unsigned long long qdr_max;
1291 uint8_t func = adapter->ahw.pci_func;
1293 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1294 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1296 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1299 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1300 /* DDR network side */
1301 addr -= NETXEN_ADDR_DDR_NET;
1302 window = (addr >> 25) & 0x3ff;
1303 if (adapter->ahw.ddr_mn_window != window) {
1304 adapter->ahw.ddr_mn_window = window;
1305 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1306 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1307 writel(window, offset);
1308 /* MUST make sure window is set before we forge on... */
1311 addr -= (window * NETXEN_WINDOW_ONE);
1312 addr += NETXEN_PCI_DDR_NET;
1313 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1314 addr -= NETXEN_ADDR_OCM0;
1315 addr += NETXEN_PCI_OCM0;
1316 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1317 addr -= NETXEN_ADDR_OCM1;
1318 addr += NETXEN_PCI_OCM1;
1319 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1320 /* QDR network side */
1321 addr -= NETXEN_ADDR_QDR_NET;
1322 window = (addr >> 22) & 0x3f;
1323 if (adapter->ahw.qdr_sn_window != window) {
1324 adapter->ahw.qdr_sn_window = window;
1325 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1326 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1327 writel((window << 22), offset);
1328 /* MUST make sure window is set before we forge on... */
1331 addr -= (window * 0x400000);
1332 addr += NETXEN_PCI_QDR_NET;
1335 * peg gdb frequently accesses memory that doesn't exist,
1336 * this limits the chit chat so debugging isn't slowed down.
1338 if ((netxen_pci_set_window_warning_count++ < 8)
1339 || (netxen_pci_set_window_warning_count % 64 == 0))
1340 printk("%s: Warning:netxen_nic_pci_set_window()"
1341 " Unknown address range!\n",
1342 netxen_nic_driver_name);
1348 /* window 1 registers only */
1349 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1350 void __iomem *addr, u32 data)
1352 read_lock(&adapter->adapter_lock);
1354 read_unlock(&adapter->adapter_lock);
1357 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1362 read_lock(&adapter->adapter_lock);
1364 read_unlock(&adapter->adapter_lock);
1369 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1370 void __iomem *addr, u32 data)
1375 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1382 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1386 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1387 if (offset < NETXEN_CRB_PCIX_HOST2 &&
1388 offset > NETXEN_CRB_PCIX_HOST)
1389 return PCI_OFFSET_SECOND_RANGE(adapter, offset);
1390 return NETXEN_CRB_NORMALIZE(adapter, offset);
1393 BUG_ON(netxen_nic_pci_get_crb_addr_2M(adapter, &off));
1394 return (void __iomem *)off;
1397 static unsigned long
1398 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1399 unsigned long long addr)
1404 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1405 /* DDR network side */
1406 window = MN_WIN(addr);
1407 adapter->ahw.ddr_mn_window = window;
1408 NXWR32(adapter, adapter->ahw.mn_win_crb, window);
1409 win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
1410 if ((win_read << 17) != window) {
1411 printk(KERN_INFO "Written MNwin (0x%x) != "
1412 "Read MNwin (0x%x)\n", window, win_read);
1414 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1415 } else if (ADDR_IN_RANGE(addr,
1416 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1417 if ((addr & 0x00ff800) == 0xff800) {
1418 printk("%s: QM access not handled.\n", __func__);
1422 window = OCM_WIN(addr);
1423 adapter->ahw.ddr_mn_window = window;
1424 NXWR32(adapter, adapter->ahw.mn_win_crb, window);
1425 win_read = NXRD32(adapter, adapter->ahw.mn_win_crb);
1426 if ((win_read >> 7) != window) {
1427 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1428 "Read OCMwin (0x%x)\n",
1429 __func__, window, win_read);
1431 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1433 } else if (ADDR_IN_RANGE(addr,
1434 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1435 /* QDR network side */
1436 window = MS_WIN(addr);
1437 adapter->ahw.qdr_sn_window = window;
1438 NXWR32(adapter, adapter->ahw.ms_win_crb, window);
1439 win_read = NXRD32(adapter, adapter->ahw.ms_win_crb);
1440 if (win_read != window) {
1441 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1442 "Read MSwin (0x%x)\n",
1443 __func__, window, win_read);
1445 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1449 * peg gdb frequently accesses memory that doesn't exist,
1450 * this limits the chit chat so debugging isn't slowed down.
1452 if ((netxen_pci_set_window_warning_count++ < 8)
1453 || (netxen_pci_set_window_warning_count%64 == 0)) {
1454 printk("%s: Warning:%s Unknown address range!\n",
1455 __func__, netxen_nic_driver_name);
1462 #define MAX_CTL_CHECK 1000
1465 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1466 u64 off, void *data, int size)
1468 unsigned long flags;
1469 int i, j, ret = 0, loop, sz[2], off0;
1471 uint64_t off8, tmpw, word[2] = {0, 0};
1472 void __iomem *mem_crb;
1477 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1478 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1479 mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
1483 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1484 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1491 off8 = off & 0xfffffff8;
1493 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1494 sz[1] = size - sz[0];
1495 loop = ((off0 + size - 1) >> 3) + 1;
1497 if ((size != 8) || (off0 != 0)) {
1498 for (i = 0; i < loop; i++) {
1499 if (adapter->pci_mem_read(adapter,
1500 off8 + (i << 3), &word[i], 8))
1507 tmpw = *((uint8_t *)data);
1510 tmpw = *((uint16_t *)data);
1513 tmpw = *((uint32_t *)data);
1517 tmpw = *((uint64_t *)data);
1520 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1521 word[0] |= tmpw << (off0 * 8);
1524 word[1] &= ~(~0ULL << (sz[1] * 8));
1525 word[1] |= tmpw >> (sz[0] * 8);
1528 write_lock_irqsave(&adapter->adapter_lock, flags);
1529 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1531 for (i = 0; i < loop; i++) {
1532 writel((uint32_t)(off8 + (i << 3)),
1533 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1535 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1536 writel(word[i] & 0xffffffff,
1537 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1538 writel((word[i] >> 32) & 0xffffffff,
1539 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1540 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1541 (mem_crb+MIU_TEST_AGT_CTRL));
1542 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1543 (mem_crb+MIU_TEST_AGT_CTRL));
1545 for (j = 0; j < MAX_CTL_CHECK; j++) {
1547 (mem_crb+MIU_TEST_AGT_CTRL));
1548 if ((temp & MIU_TA_CTL_BUSY) == 0)
1552 if (j >= MAX_CTL_CHECK) {
1553 if (printk_ratelimit())
1554 dev_err(&adapter->pdev->dev,
1555 "failed to write through agent\n");
1561 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1562 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1567 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1568 u64 off, void *data, int size)
1570 unsigned long flags;
1571 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1573 uint64_t off8, val, word[2] = {0, 0};
1574 void __iomem *mem_crb;
1579 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1580 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1581 mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET);
1585 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1586 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1593 off8 = off & 0xfffffff8;
1594 off0[0] = off & 0x7;
1596 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1597 sz[1] = size - sz[0];
1598 loop = ((off0[0] + size - 1) >> 3) + 1;
1600 write_lock_irqsave(&adapter->adapter_lock, flags);
1601 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1603 for (i = 0; i < loop; i++) {
1604 writel((uint32_t)(off8 + (i << 3)),
1605 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1607 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1608 writel(MIU_TA_CTL_ENABLE,
1609 (mem_crb+MIU_TEST_AGT_CTRL));
1610 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1611 (mem_crb+MIU_TEST_AGT_CTRL));
1613 for (j = 0; j < MAX_CTL_CHECK; j++) {
1615 (mem_crb+MIU_TEST_AGT_CTRL));
1616 if ((temp & MIU_TA_CTL_BUSY) == 0)
1620 if (j >= MAX_CTL_CHECK) {
1621 if (printk_ratelimit())
1622 dev_err(&adapter->pdev->dev,
1623 "failed to read through agent\n");
1627 start = off0[i] >> 2;
1628 end = (off0[i] + sz[i] - 1) >> 2;
1629 for (k = start; k <= end; k++) {
1630 word[i] |= ((uint64_t) readl(
1632 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1636 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1637 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1639 if (j >= MAX_CTL_CHECK)
1645 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1646 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1651 *(uint8_t *)data = val;
1654 *(uint16_t *)data = val;
1657 *(uint32_t *)data = val;
1660 *(uint64_t *)data = val;
1667 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1668 u64 off, void *data, int size)
1670 int i, j, ret = 0, loop, sz[2], off0;
1672 uint64_t off8, tmpw, word[2] = {0, 0};
1673 void __iomem *mem_crb;
1678 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1679 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1680 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
1684 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1685 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
1692 off8 = off & 0xfffffff8;
1694 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1695 sz[1] = size - sz[0];
1696 loop = ((off0 + size - 1) >> 3) + 1;
1698 if ((size != 8) || (off0 != 0)) {
1699 for (i = 0; i < loop; i++) {
1700 if (adapter->pci_mem_read(adapter,
1701 off8 + (i << 3), &word[i], 8))
1708 tmpw = *((uint8_t *)data);
1711 tmpw = *((uint16_t *)data);
1714 tmpw = *((uint32_t *)data);
1718 tmpw = *((uint64_t *)data);
1722 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1723 word[0] |= tmpw << (off0 * 8);
1726 word[1] &= ~(~0ULL << (sz[1] * 8));
1727 word[1] |= tmpw >> (sz[0] * 8);
1731 * don't lock here - write_wx gets the lock if each time
1732 * write_lock_irqsave(&adapter->adapter_lock, flags);
1733 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1736 for (i = 0; i < loop; i++) {
1737 writel(off8 + (i << 3), mem_crb+MIU_TEST_AGT_ADDR_LO);
1738 writel(0, mem_crb+MIU_TEST_AGT_ADDR_HI);
1739 writel(word[i] & 0xffffffff, mem_crb+MIU_TEST_AGT_WRDATA_LO);
1740 writel((word[i] >> 32) & 0xffffffff,
1741 mem_crb+MIU_TEST_AGT_WRDATA_HI);
1742 writel((MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE),
1743 mem_crb+MIU_TEST_AGT_CTRL);
1744 writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE,
1745 mem_crb+MIU_TEST_AGT_CTRL);
1747 for (j = 0; j < MAX_CTL_CHECK; j++) {
1748 temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
1749 if ((temp & MIU_TA_CTL_BUSY) == 0)
1753 if (j >= MAX_CTL_CHECK) {
1754 if (printk_ratelimit())
1755 dev_err(&adapter->pdev->dev,
1756 "failed to write through agent\n");
1763 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1764 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1770 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1771 u64 off, void *data, int size)
1773 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1775 uint64_t off8, val, word[2] = {0, 0};
1776 void __iomem *mem_crb;
1781 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1782 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1783 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET);
1787 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1788 mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET);
1795 off8 = off & 0xfffffff8;
1796 off0[0] = off & 0x7;
1798 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1799 sz[1] = size - sz[0];
1800 loop = ((off0[0] + size - 1) >> 3) + 1;
1803 * don't lock here - write_wx gets the lock if each time
1804 * write_lock_irqsave(&adapter->adapter_lock, flags);
1805 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1808 for (i = 0; i < loop; i++) {
1809 writel(off8 + (i << 3), mem_crb + MIU_TEST_AGT_ADDR_LO);
1810 writel(0, mem_crb + MIU_TEST_AGT_ADDR_HI);
1811 writel(MIU_TA_CTL_ENABLE, mem_crb + MIU_TEST_AGT_CTRL);
1812 writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE,
1813 mem_crb + MIU_TEST_AGT_CTRL);
1815 for (j = 0; j < MAX_CTL_CHECK; j++) {
1816 temp = readl(mem_crb + MIU_TEST_AGT_CTRL);
1817 if ((temp & MIU_TA_CTL_BUSY) == 0)
1821 if (j >= MAX_CTL_CHECK) {
1822 if (printk_ratelimit())
1823 dev_err(&adapter->pdev->dev,
1824 "failed to read through agent\n");
1828 start = off0[i] >> 2;
1829 end = (off0[i] + sz[i] - 1) >> 2;
1830 for (k = start; k <= end; k++) {
1831 temp = readl(mem_crb + MIU_TEST_AGT_RDDATA(k));
1832 word[i] |= ((uint64_t)temp << (32 * k));
1837 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1838 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1841 if (j >= MAX_CTL_CHECK)
1847 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1848 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1853 *(uint8_t *)data = val;
1856 *(uint16_t *)data = val;
1859 *(uint32_t *)data = val;
1862 *(uint64_t *)data = val;
1869 netxen_setup_hwops(struct netxen_adapter *adapter)
1871 adapter->init_port = netxen_niu_xg_init_port;
1872 adapter->stop_port = netxen_niu_disable_xg_port;
1874 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1875 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1876 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1877 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1878 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1879 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1880 adapter->io_read = netxen_nic_io_read_128M,
1881 adapter->io_write = netxen_nic_io_write_128M,
1883 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1884 adapter->set_multi = netxen_p2_nic_set_multi;
1885 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1886 adapter->set_promisc = netxen_p2_nic_set_promisc;
1889 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1890 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1891 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1892 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1893 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1894 adapter->io_read = netxen_nic_io_read_2M,
1895 adapter->io_write = netxen_nic_io_write_2M,
1897 adapter->set_mtu = nx_fw_cmd_set_mtu;
1898 adapter->set_promisc = netxen_p3_nic_set_promisc;
1899 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1900 adapter->set_multi = netxen_p3_nic_set_multi;
1902 adapter->phy_read = nx_fw_cmd_query_phy;
1903 adapter->phy_write = nx_fw_cmd_set_phy;
1907 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1909 int offset, board_type, magic, header_version;
1910 struct pci_dev *pdev = adapter->pdev;
1912 offset = NX_FW_MAGIC_OFFSET;
1913 if (netxen_rom_fast_read(adapter, offset, &magic))
1916 offset = NX_HDR_VERSION_OFFSET;
1917 if (netxen_rom_fast_read(adapter, offset, &header_version))
1920 if (magic != NETXEN_BDINFO_MAGIC ||
1921 header_version != NETXEN_BDINFO_VERSION) {
1923 "invalid board config, magic=%08x, version=%08x\n",
1924 magic, header_version);
1928 offset = NX_BRDTYPE_OFFSET;
1929 if (netxen_rom_fast_read(adapter, offset, &board_type))
1932 adapter->ahw.board_type = board_type;
1934 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1935 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1936 if ((gpio & 0x8000) == 0)
1937 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1940 switch (board_type) {
1941 case NETXEN_BRDTYPE_P2_SB35_4G:
1942 adapter->ahw.port_type = NETXEN_NIC_GBE;
1944 case NETXEN_BRDTYPE_P2_SB31_10G:
1945 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1946 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1947 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1948 case NETXEN_BRDTYPE_P3_HMEZ:
1949 case NETXEN_BRDTYPE_P3_XG_LOM:
1950 case NETXEN_BRDTYPE_P3_10G_CX4:
1951 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1952 case NETXEN_BRDTYPE_P3_IMEZ:
1953 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1954 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1955 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1956 case NETXEN_BRDTYPE_P3_10G_XFP:
1957 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1958 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1960 case NETXEN_BRDTYPE_P1_BD:
1961 case NETXEN_BRDTYPE_P1_SB:
1962 case NETXEN_BRDTYPE_P1_SMAX:
1963 case NETXEN_BRDTYPE_P1_SOCK:
1964 case NETXEN_BRDTYPE_P3_REF_QG:
1965 case NETXEN_BRDTYPE_P3_4_GB:
1966 case NETXEN_BRDTYPE_P3_4_GB_MM:
1967 adapter->ahw.port_type = NETXEN_NIC_GBE;
1969 case NETXEN_BRDTYPE_P3_10G_TP:
1970 adapter->ahw.port_type = (adapter->portnum < 2) ?
1971 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1974 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1975 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1982 /* NIU access sections */
1984 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1986 new_mtu += MTU_FUDGE_FACTOR;
1987 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1992 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1994 new_mtu += MTU_FUDGE_FACTOR;
1995 if (adapter->physical_port == 0)
1996 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1998 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2002 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2008 if (!netif_carrier_ok(adapter->netdev)) {
2009 adapter->link_speed = 0;
2010 adapter->link_duplex = -1;
2011 adapter->link_autoneg = AUTONEG_ENABLE;
2015 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2016 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2017 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2018 adapter->link_speed = SPEED_1000;
2019 adapter->link_duplex = DUPLEX_FULL;
2020 adapter->link_autoneg = AUTONEG_DISABLE;
2024 if (adapter->phy_read
2025 && adapter->phy_read(adapter,
2026 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2028 if (netxen_get_phy_link(status)) {
2029 switch (netxen_get_phy_speed(status)) {
2031 adapter->link_speed = SPEED_10;
2034 adapter->link_speed = SPEED_100;
2037 adapter->link_speed = SPEED_1000;
2040 adapter->link_speed = 0;
2043 switch (netxen_get_phy_duplex(status)) {
2045 adapter->link_duplex = DUPLEX_HALF;
2048 adapter->link_duplex = DUPLEX_FULL;
2051 adapter->link_duplex = -1;
2054 if (adapter->phy_read
2055 && adapter->phy_read(adapter,
2056 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2058 adapter->link_autoneg = autoneg;
2063 adapter->link_speed = 0;
2064 adapter->link_duplex = -1;
2070 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2074 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2077 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2078 if (wol_cfg & (1UL << adapter->portnum)) {
2079 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2080 if (wol_cfg & (1 << adapter->portnum))