drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/pci.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/delay.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_ether.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/ip.h>
  22 #include <linux/in.h>
  23 #include <linux/ipv6.h>
  24 #include <linux/log2.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/crc32.h>
  27 #include <linux/list.h>
  28 #include <linux/slab.h>
  29
  30 #include <linux/io.h>
  31
  32 #ifdef CONFIG_SPARC64
  33 #include <linux/of_device.h>
  34 #endif
  35
  36 #include "niu.h"
  37
  38 #define DRV_MODULE_NAME         "niu"
  39 #define DRV_MODULE_VERSION      "1.0"
  40 #define DRV_MODULE_RELDATE      "Nov 14, 2008"
  41
  42 static char version[] __devinitdata =
  43         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  44
  45 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  46 MODULE_DESCRIPTION("NIU ethernet driver");
  47 MODULE_LICENSE("GPL");
  48 MODULE_VERSION(DRV_MODULE_VERSION);
  49
  50 #ifndef readq
  51 static u64 readq(void __iomem *reg)
  52 {
  53         return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
  54 }
  55
  56 static void writeq(u64 val, void __iomem *reg)
  57 {
  58         writel(val & 0xffffffff, reg);
  59         writel(val >> 32, reg + 0x4UL);
  60 }
  61 #endif
  62
  63 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
  64         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  65         {}
  66 };
  67
  68 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  69
  70 #define NIU_TX_TIMEOUT                  (5 * HZ)
  71
  72 #define nr64(reg)               readq(np->regs + (reg))
  73 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  74
  75 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  76 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  77
  78 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  79 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  80
  81 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  82 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  83
  84 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  85 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  86
  87 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  88
  89 static int niu_debug;
  90 static int debug = -1;
  91 module_param(debug, int, 0);
  92 MODULE_PARM_DESC(debug, "NIU debug level");
  93
  94 #define niu_lock_parent(np, flags) \
  95         spin_lock_irqsave(&np->parent->lock, flags)
  96 #define niu_unlock_parent(np, flags) \
  97         spin_unlock_irqrestore(&np->parent->lock, flags)
  98
  99 static int serdes_init_10g_serdes(struct niu *np);
 100
 101 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 102                                      u64 bits, int limit, int delay)
 103 {
 104         while (--limit >= 0) {
 105                 u64 val = nr64_mac(reg);
 106
 107                 if (!(val & bits))
 108                         break;
 109                 udelay(delay);
 110         }
 111         if (limit < 0)
 112                 return -ENODEV;
 113         return 0;
 114 }
 115
 116 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 117                                         u64 bits, int limit, int delay,
 118                                         const char *reg_name)
 119 {
 120         int err;
 121
 122         nw64_mac(reg, bits);
 123         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 124         if (err)
 125                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 126                            (unsigned long long)bits, reg_name,
 127                            (unsigned long long)nr64_mac(reg));
 128         return err;
 129 }
 130
 131 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 132 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 133         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 134 })
 135
 136 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 137                                      u64 bits, int limit, int delay)
 138 {
 139         while (--limit >= 0) {
 140                 u64 val = nr64_ipp(reg);
 141
 142                 if (!(val & bits))
 143                         break;
 144                 udelay(delay);
 145         }
 146         if (limit < 0)
 147                 return -ENODEV;
 148         return 0;
 149 }
 150
 151 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 152                                         u64 bits, int limit, int delay,
 153                                         const char *reg_name)
 154 {
 155         int err;
 156         u64 val;
 157
 158         val = nr64_ipp(reg);
 159         val |= bits;
 160         nw64_ipp(reg, val);
 161
 162         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 163         if (err)
 164                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 165                            (unsigned long long)bits, reg_name,
 166                            (unsigned long long)nr64_ipp(reg));
 167         return err;
 168 }
 169
 170 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 171 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 172         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 173 })
 174
 175 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 176                                  u64 bits, int limit, int delay)
 177 {
 178         while (--limit >= 0) {
 179                 u64 val = nr64(reg);
 180
 181                 if (!(val & bits))
 182                         break;
 183                 udelay(delay);
 184         }
 185         if (limit < 0)
 186                 return -ENODEV;
 187         return 0;
 188 }
 189
 190 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 191 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 192         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 193 })
 194
 195 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 196                                     u64 bits, int limit, int delay,
 197                                     const char *reg_name)
 198 {
 199         int err;
 200
 201         nw64(reg, bits);
 202         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 203         if (err)
 204                 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
 205                            (unsigned long long)bits, reg_name,
 206                            (unsigned long long)nr64(reg));
 207         return err;
 208 }
 209
 210 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 211 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 212         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 213 })
 214
 215 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 216 {
 217         u64 val = (u64) lp->timer;
 218
 219         if (on)
 220                 val |= LDG_IMGMT_ARM;
 221
 222         nw64(LDG_IMGMT(lp->ldg_num), val);
 223 }
 224
 225 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 226 {
 227         unsigned long mask_reg, bits;
 228         u64 val;
 229
 230         if (ldn < 0 || ldn > LDN_MAX)
 231                 return -EINVAL;
 232
 233         if (ldn < 64) {
 234                 mask_reg = LD_IM0(ldn);
 235                 bits = LD_IM0_MASK;
 236         } else {
 237                 mask_reg = LD_IM1(ldn - 64);
 238                 bits = LD_IM1_MASK;
 239         }
 240
 241         val = nr64(mask_reg);
 242         if (on)
 243                 val &= ~bits;
 244         else
 245                 val |= bits;
 246         nw64(mask_reg, val);
 247
 248         return 0;
 249 }
 250
 251 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 252 {
 253         struct niu_parent *parent = np->parent;
 254         int i;
 255
 256         for (i = 0; i <= LDN_MAX; i++) {
 257                 int err;
 258
 259                 if (parent->ldg_map[i] != lp->ldg_num)
 260                         continue;
 261
 262                 err = niu_ldn_irq_enable(np, i, on);
 263                 if (err)
 264                         return err;
 265         }
 266         return 0;
 267 }
 268
 269 static int niu_enable_interrupts(struct niu *np, int on)
 270 {
 271         int i;
 272
 273         for (i = 0; i < np->num_ldg; i++) {
 274                 struct niu_ldg *lp = &np->ldg[i];
 275                 int err;
 276
 277                 err = niu_enable_ldn_in_ldg(np, lp, on);
 278                 if (err)
 279                         return err;
 280         }
 281         for (i = 0; i < np->num_ldg; i++)
 282                 niu_ldg_rearm(np, &np->ldg[i], on);
 283
 284         return 0;
 285 }
 286
 287 static u32 phy_encode(u32 type, int port)
 288 {
 289         return (type << (port * 2));
 290 }
 291
 292 static u32 phy_decode(u32 val, int port)
 293 {
 294         return (val >> (port * 2)) & PORT_TYPE_MASK;
 295 }
 296
 297 static int mdio_wait(struct niu *np)
 298 {
 299         int limit = 1000;
 300         u64 val;
 301
 302         while (--limit > 0) {
 303                 val = nr64(MIF_FRAME_OUTPUT);
 304                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 305                         return val & MIF_FRAME_OUTPUT_DATA;
 306
 307                 udelay(10);
 308         }
 309
 310         return -ENODEV;
 311 }
 312
 313 static int mdio_read(struct niu *np, int port, int dev, int reg)
 314 {
 315         int err;
 316
 317         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 318         err = mdio_wait(np);
 319         if (err < 0)
 320                 return err;
 321
 322         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 323         return mdio_wait(np);
 324 }
 325
 326 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 327 {
 328         int err;
 329
 330         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 331         err = mdio_wait(np);
 332         if (err < 0)
 333                 return err;
 334
 335         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 336         err = mdio_wait(np);
 337         if (err < 0)
 338                 return err;
 339
 340         return 0;
 341 }
 342
 343 static int mii_read(struct niu *np, int port, int reg)
 344 {
 345         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 346         return mdio_wait(np);
 347 }
 348
 349 static int mii_write(struct niu *np, int port, int reg, int data)
 350 {
 351         int err;
 352
 353         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 354         err = mdio_wait(np);
 355         if (err < 0)
 356                 return err;
 357
 358         return 0;
 359 }
 360
 361 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 362 {
 363         int err;
 364
 365         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 366                          ESR2_TI_PLL_TX_CFG_L(channel),
 367                          val & 0xffff);
 368         if (!err)
 369                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 370                                  ESR2_TI_PLL_TX_CFG_H(channel),
 371                                  val >> 16);
 372         return err;
 373 }
 374
 375 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 376 {
 377         int err;
 378
 379         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 380                          ESR2_TI_PLL_RX_CFG_L(channel),
 381                          val & 0xffff);
 382         if (!err)
 383                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 384                                  ESR2_TI_PLL_RX_CFG_H(channel),
 385                                  val >> 16);
 386         return err;
 387 }
 388
 389 /* Mode is always 10G fiber.  */
 390 static int serdes_init_niu_10g_fiber(struct niu *np)
 391 {
 392         struct niu_link_config *lp = &np->link_config;
 393         u32 tx_cfg, rx_cfg;
 394         unsigned long i;
 395
 396         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 397         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 398                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 399                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 400
 401         if (lp->loopback_mode == LOOPBACK_PHY) {
 402                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 403
 404                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 405                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 406
 407                 tx_cfg |= PLL_TX_CFG_ENTEST;
 408                 rx_cfg |= PLL_RX_CFG_ENTEST;
 409         }
 410
 411         /* Initialize all 4 lanes of the SERDES.  */
 412         for (i = 0; i < 4; i++) {
 413                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 414                 if (err)
 415                         return err;
 416         }
 417
 418         for (i = 0; i < 4; i++) {
 419                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 420                 if (err)
 421                         return err;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int serdes_init_niu_1g_serdes(struct niu *np)
 428 {
 429         struct niu_link_config *lp = &np->link_config;
 430         u16 pll_cfg, pll_sts;
 431         int max_retry = 100;
 432         u64 uninitialized_var(sig), mask, val;
 433         u32 tx_cfg, rx_cfg;
 434         unsigned long i;
 435         int err;
 436
 437         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
 438                   PLL_TX_CFG_RATE_HALF);
 439         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 440                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 441                   PLL_RX_CFG_RATE_HALF);
 442
 443         if (np->port == 0)
 444                 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
 445
 446         if (lp->loopback_mode == LOOPBACK_PHY) {
 447                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 448
 449                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 450                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 451
 452                 tx_cfg |= PLL_TX_CFG_ENTEST;
 453                 rx_cfg |= PLL_RX_CFG_ENTEST;
 454         }
 455
 456         /* Initialize PLL for 1G */
 457         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
 458
 459         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 460                          ESR2_TI_PLL_CFG_L, pll_cfg);
 461         if (err) {
 462                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 463                            np->port, __func__);
 464                 return err;
 465         }
 466
 467         pll_sts = PLL_CFG_ENPLL;
 468
 469         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 470                          ESR2_TI_PLL_STS_L, pll_sts);
 471         if (err) {
 472                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 473                            np->port, __func__);
 474                 return err;
 475         }
 476
 477         udelay(200);
 478
 479         /* Initialize all 4 lanes of the SERDES.  */
 480         for (i = 0; i < 4; i++) {
 481                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 482                 if (err)
 483                         return err;
 484         }
 485
 486         for (i = 0; i < 4; i++) {
 487                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 488                 if (err)
 489                         return err;
 490         }
 491
 492         switch (np->port) {
 493         case 0:
 494                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 495                 mask = val;
 496                 break;
 497
 498         case 1:
 499                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 500                 mask = val;
 501                 break;
 502
 503         default:
 504                 return -EINVAL;
 505         }
 506
 507         while (max_retry--) {
 508                 sig = nr64(ESR_INT_SIGNALS);
 509                 if ((sig & mask) == val)
 510                         break;
 511
 512                 mdelay(500);
 513         }
 514
 515         if ((sig & mask) != val) {
 516                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 517                            np->port, (int)(sig & mask), (int)val);
 518                 return -ENODEV;
 519         }
 520
 521         return 0;
 522 }
 523
 524 static int serdes_init_niu_10g_serdes(struct niu *np)
 525 {
 526         struct niu_link_config *lp = &np->link_config;
 527         u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
 528         int max_retry = 100;
 529         u64 uninitialized_var(sig), mask, val;
 530         unsigned long i;
 531         int err;
 532
 533         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 534         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 535                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 536                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 537
 538         if (lp->loopback_mode == LOOPBACK_PHY) {
 539                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 540
 541                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 542                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 543
 544                 tx_cfg |= PLL_TX_CFG_ENTEST;
 545                 rx_cfg |= PLL_RX_CFG_ENTEST;
 546         }
 547
 548         /* Initialize PLL for 10G */
 549         pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
 550
 551         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 552                          ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
 553         if (err) {
 554                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
 555                            np->port, __func__);
 556                 return err;
 557         }
 558
 559         pll_sts = PLL_CFG_ENPLL;
 560
 561         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 562                          ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
 563         if (err) {
 564                 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
 565                            np->port, __func__);
 566                 return err;
 567         }
 568
 569         udelay(200);
 570
 571         /* Initialize all 4 lanes of the SERDES.  */
 572         for (i = 0; i < 4; i++) {
 573                 err = esr2_set_tx_cfg(np, i, tx_cfg);
 574                 if (err)
 575                         return err;
 576         }
 577
 578         for (i = 0; i < 4; i++) {
 579                 err = esr2_set_rx_cfg(np, i, rx_cfg);
 580                 if (err)
 581                         return err;
 582         }
 583
 584         /* check if serdes is ready */
 585
 586         switch (np->port) {
 587         case 0:
 588                 mask = ESR_INT_SIGNALS_P0_BITS;
 589                 val = (ESR_INT_SRDY0_P0 |
 590                        ESR_INT_DET0_P0 |
 591                        ESR_INT_XSRDY_P0 |
 592                        ESR_INT_XDP_P0_CH3 |
 593                        ESR_INT_XDP_P0_CH2 |
 594                        ESR_INT_XDP_P0_CH1 |
 595                        ESR_INT_XDP_P0_CH0);
 596                 break;
 597
 598         case 1:
 599                 mask = ESR_INT_SIGNALS_P1_BITS;
 600                 val = (ESR_INT_SRDY0_P1 |
 601                        ESR_INT_DET0_P1 |
 602                        ESR_INT_XSRDY_P1 |
 603                        ESR_INT_XDP_P1_CH3 |
 604                        ESR_INT_XDP_P1_CH2 |
 605                        ESR_INT_XDP_P1_CH1 |
 606                        ESR_INT_XDP_P1_CH0);
 607                 break;
 608
 609         default:
 610                 return -EINVAL;
 611         }
 612
 613         while (max_retry--) {
 614                 sig = nr64(ESR_INT_SIGNALS);
 615                 if ((sig & mask) == val)
 616                         break;
 617
 618                 mdelay(500);
 619         }
 620
 621         if ((sig & mask) != val) {
 622                 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
 623                         np->port, (int)(sig & mask), (int)val);
 624
 625                 /* 10G failed, try initializing at 1G */
 626                 err = serdes_init_niu_1g_serdes(np);
 627                 if (!err) {
 628                         np->flags &= ~NIU_FLAGS_10G;
 629                         np->mac_xcvr = MAC_XCVR_PCS;
 630                 }  else {
 631                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
 632                                    np->port);
 633                         return -ENODEV;
 634                 }
 635         }
 636         return 0;
 637 }
 638
 639 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 640 {
 641         int err;
 642
 643         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 644         if (err >= 0) {
 645                 *val = (err & 0xffff);
 646                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 647                                 ESR_RXTX_CTRL_H(chan));
 648                 if (err >= 0)
 649                         *val |= ((err & 0xffff) << 16);
 650                 err = 0;
 651         }
 652         return err;
 653 }
 654
 655 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 656 {
 657         int err;
 658
 659         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 660                         ESR_GLUE_CTRL0_L(chan));
 661         if (err >= 0) {
 662                 *val = (err & 0xffff);
 663                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 664                                 ESR_GLUE_CTRL0_H(chan));
 665                 if (err >= 0) {
 666                         *val |= ((err & 0xffff) << 16);
 667                         err = 0;
 668                 }
 669         }
 670         return err;
 671 }
 672
 673 static int esr_read_reset(struct niu *np, u32 *val)
 674 {
 675         int err;
 676
 677         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 678                         ESR_RXTX_RESET_CTRL_L);
 679         if (err >= 0) {
 680                 *val = (err & 0xffff);
 681                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 682                                 ESR_RXTX_RESET_CTRL_H);
 683                 if (err >= 0) {
 684                         *val |= ((err & 0xffff) << 16);
 685                         err = 0;
 686                 }
 687         }
 688         return err;
 689 }
 690
 691 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 692 {
 693         int err;
 694
 695         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 696                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 697         if (!err)
 698                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 699                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 700         return err;
 701 }
 702
 703 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 704 {
 705         int err;
 706
 707         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 708                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 709         if (!err)
 710                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 711                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 712         return err;
 713 }
 714
 715 static int esr_reset(struct niu *np)
 716 {
 717         u32 uninitialized_var(reset);
 718         int err;
 719
 720         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 721                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 722         if (err)
 723                 return err;
 724         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 725                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 726         if (err)
 727                 return err;
 728         udelay(200);
 729
 730         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 731                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 732         if (err)
 733                 return err;
 734         udelay(200);
 735
 736         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 737                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 738         if (err)
 739                 return err;
 740         udelay(200);
 741
 742         err = esr_read_reset(np, &reset);
 743         if (err)
 744                 return err;
 745         if (reset != 0) {
 746                 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
 747                            np->port, reset);
 748                 return -ENODEV;
 749         }
 750
 751         return 0;
 752 }
 753
 754 static int serdes_init_10g(struct niu *np)
 755 {
 756         struct niu_link_config *lp = &np->link_config;
 757         unsigned long ctrl_reg, test_cfg_reg, i;
 758         u64 ctrl_val, test_cfg_val, sig, mask, val;
 759         int err;
 760
 761         switch (np->port) {
 762         case 0:
 763                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 764                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 765                 break;
 766         case 1:
 767                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 768                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 769                 break;
 770
 771         default:
 772                 return -EINVAL;
 773         }
 774         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 775                     ENET_SERDES_CTRL_SDET_1 |
 776                     ENET_SERDES_CTRL_SDET_2 |
 777                     ENET_SERDES_CTRL_SDET_3 |
 778                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 779                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 780                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 781                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 782                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 783                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 784                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 785                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 786         test_cfg_val = 0;
 787
 788         if (lp->loopback_mode == LOOPBACK_PHY) {
 789                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 790                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 791                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 792                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 793                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 794                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 795                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 796                                   ENET_SERDES_TEST_MD_3_SHIFT));
 797         }
 798
 799         nw64(ctrl_reg, ctrl_val);
 800         nw64(test_cfg_reg, test_cfg_val);
 801
 802         /* Initialize all 4 lanes of the SERDES.  */
 803         for (i = 0; i < 4; i++) {
 804                 u32 rxtx_ctrl, glue0;
 805
 806                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 807                 if (err)
 808                         return err;
 809                 err = esr_read_glue0(np, i, &glue0);
 810                 if (err)
 811                         return err;
 812
 813                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 814                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 815                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 816
 817                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 818                            ESR_GLUE_CTRL0_THCNT |
 819                            ESR_GLUE_CTRL0_BLTIME);
 820                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 821                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 822                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 823                           (BLTIME_300_CYCLES <<
 824                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 825
 826                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 827                 if (err)
 828                         return err;
 829                 err = esr_write_glue0(np, i, glue0);
 830                 if (err)
 831                         return err;
 832         }
 833
 834         err = esr_reset(np);
 835         if (err)
 836                 return err;
 837
 838         sig = nr64(ESR_INT_SIGNALS);
 839         switch (np->port) {
 840         case 0:
 841                 mask = ESR_INT_SIGNALS_P0_BITS;
 842                 val = (ESR_INT_SRDY0_P0 |
 843                        ESR_INT_DET0_P0 |
 844                        ESR_INT_XSRDY_P0 |
 845                        ESR_INT_XDP_P0_CH3 |
 846                        ESR_INT_XDP_P0_CH2 |
 847                        ESR_INT_XDP_P0_CH1 |
 848                        ESR_INT_XDP_P0_CH0);
 849                 break;
 850
 851         case 1:
 852                 mask = ESR_INT_SIGNALS_P1_BITS;
 853                 val = (ESR_INT_SRDY0_P1 |
 854                        ESR_INT_DET0_P1 |
 855                        ESR_INT_XSRDY_P1 |
 856                        ESR_INT_XDP_P1_CH3 |
 857                        ESR_INT_XDP_P1_CH2 |
 858                        ESR_INT_XDP_P1_CH1 |
 859                        ESR_INT_XDP_P1_CH0);
 860                 break;
 861
 862         default:
 863                 return -EINVAL;
 864         }
 865
 866         if ((sig & mask) != val) {
 867                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 868                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 869                         return 0;
 870                 }
 871                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
 872                            np->port, (int)(sig & mask), (int)val);
 873                 return -ENODEV;
 874         }
 875         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 876                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 877         return 0;
 878 }
 879
 880 static int serdes_init_1g(struct niu *np)
 881 {
 882         u64 val;
 883
 884         val = nr64(ENET_SERDES_1_PLL_CFG);
 885         val &= ~ENET_SERDES_PLL_FBDIV2;
 886         switch (np->port) {
 887         case 0:
 888                 val |= ENET_SERDES_PLL_HRATE0;
 889                 break;
 890         case 1:
 891                 val |= ENET_SERDES_PLL_HRATE1;
 892                 break;
 893         case 2:
 894                 val |= ENET_SERDES_PLL_HRATE2;
 895                 break;
 896         case 3:
 897                 val |= ENET_SERDES_PLL_HRATE3;
 898                 break;
 899         default:
 900                 return -EINVAL;
 901         }
 902         nw64(ENET_SERDES_1_PLL_CFG, val);
 903
 904         return 0;
 905 }
 906
 907 static int serdes_init_1g_serdes(struct niu *np)
 908 {
 909         struct niu_link_config *lp = &np->link_config;
 910         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 911         u64 ctrl_val, test_cfg_val, sig, mask, val;
 912         int err;
 913         u64 reset_val, val_rd;
 914
 915         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 916                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 917                 ENET_SERDES_PLL_FBDIV0;
 918         switch (np->port) {
 919         case 0:
 920                 reset_val =  ENET_SERDES_RESET_0;
 921                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 922                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 923                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 924                 break;
 925         case 1:
 926                 reset_val =  ENET_SERDES_RESET_1;
 927                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 928                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 929                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 930                 break;
 931
 932         default:
 933                 return -EINVAL;
 934         }
 935         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 936                     ENET_SERDES_CTRL_SDET_1 |
 937                     ENET_SERDES_CTRL_SDET_2 |
 938                     ENET_SERDES_CTRL_SDET_3 |
 939                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 940                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 941                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 942                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 943                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 944                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 945                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 946                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 947         test_cfg_val = 0;
 948
 949         if (lp->loopback_mode == LOOPBACK_PHY) {
 950                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 951                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 952                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 953                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 954                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 955                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 956                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 957                                   ENET_SERDES_TEST_MD_3_SHIFT));
 958         }
 959
 960         nw64(ENET_SERDES_RESET, reset_val);
 961         mdelay(20);
 962         val_rd = nr64(ENET_SERDES_RESET);
 963         val_rd &= ~reset_val;
 964         nw64(pll_cfg, val);
 965         nw64(ctrl_reg, ctrl_val);
 966         nw64(test_cfg_reg, test_cfg_val);
 967         nw64(ENET_SERDES_RESET, val_rd);
 968         mdelay(2000);
 969
 970         /* Initialize all 4 lanes of the SERDES.  */
 971         for (i = 0; i < 4; i++) {
 972                 u32 rxtx_ctrl, glue0;
 973
 974                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 975                 if (err)
 976                         return err;
 977                 err = esr_read_glue0(np, i, &glue0);
 978                 if (err)
 979                         return err;
 980
 981                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 982                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 983                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 984
 985                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 986                            ESR_GLUE_CTRL0_THCNT |
 987                            ESR_GLUE_CTRL0_BLTIME);
 988                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 989                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 990                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 991                           (BLTIME_300_CYCLES <<
 992                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 993
 994                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 995                 if (err)
 996                         return err;
 997                 err = esr_write_glue0(np, i, glue0);
 998                 if (err)
 999                         return err;
1000         }
1001
1002
1003         sig = nr64(ESR_INT_SIGNALS);
1004         switch (np->port) {
1005         case 0:
1006                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1007                 mask = val;
1008                 break;
1009
1010         case 1:
1011                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1012                 mask = val;
1013                 break;
1014
1015         default:
1016                 return -EINVAL;
1017         }
1018
1019         if ((sig & mask) != val) {
1020                 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1021                            np->port, (int)(sig & mask), (int)val);
1022                 return -ENODEV;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1029 {
1030         struct niu_link_config *lp = &np->link_config;
1031         int link_up;
1032         u64 val;
1033         u16 current_speed;
1034         unsigned long flags;
1035         u8 current_duplex;
1036
1037         link_up = 0;
1038         current_speed = SPEED_INVALID;
1039         current_duplex = DUPLEX_INVALID;
1040
1041         spin_lock_irqsave(&np->lock, flags);
1042
1043         val = nr64_pcs(PCS_MII_STAT);
1044
1045         if (val & PCS_MII_STAT_LINK_STATUS) {
1046                 link_up = 1;
1047                 current_speed = SPEED_1000;
1048                 current_duplex = DUPLEX_FULL;
1049         }
1050
1051         lp->active_speed = current_speed;
1052         lp->active_duplex = current_duplex;
1053         spin_unlock_irqrestore(&np->lock, flags);
1054
1055         *link_up_p = link_up;
1056         return 0;
1057 }
1058
1059 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1060 {
1061         unsigned long flags;
1062         struct niu_link_config *lp = &np->link_config;
1063         int link_up = 0;
1064         int link_ok = 1;
1065         u64 val, val2;
1066         u16 current_speed;
1067         u8 current_duplex;
1068
1069         if (!(np->flags & NIU_FLAGS_10G))
1070                 return link_status_1g_serdes(np, link_up_p);
1071
1072         current_speed = SPEED_INVALID;
1073         current_duplex = DUPLEX_INVALID;
1074         spin_lock_irqsave(&np->lock, flags);
1075
1076         val = nr64_xpcs(XPCS_STATUS(0));
1077         val2 = nr64_mac(XMAC_INTER2);
1078         if (val2 & 0x01000000)
1079                 link_ok = 0;
1080
1081         if ((val & 0x1000ULL) && link_ok) {
1082                 link_up = 1;
1083                 current_speed = SPEED_10000;
1084                 current_duplex = DUPLEX_FULL;
1085         }
1086         lp->active_speed = current_speed;
1087         lp->active_duplex = current_duplex;
1088         spin_unlock_irqrestore(&np->lock, flags);
1089         *link_up_p = link_up;
1090         return 0;
1091 }
1092
1093 static int link_status_mii(struct niu *np, int *link_up_p)
1094 {
1095         struct niu_link_config *lp = &np->link_config;
1096         int err;
1097         int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1098         int supported, advertising, active_speed, active_duplex;
1099
1100         err = mii_read(np, np->phy_addr, MII_BMCR);
1101         if (unlikely(err < 0))
1102                 return err;
1103         bmcr = err;
1104
1105         err = mii_read(np, np->phy_addr, MII_BMSR);
1106         if (unlikely(err < 0))
1107                 return err;
1108         bmsr = err;
1109
1110         err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1111         if (unlikely(err < 0))
1112                 return err;
1113         advert = err;
1114
1115         err = mii_read(np, np->phy_addr, MII_LPA);
1116         if (unlikely(err < 0))
1117                 return err;
1118         lpa = err;
1119
1120         if (likely(bmsr & BMSR_ESTATEN)) {
1121                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1122                 if (unlikely(err < 0))
1123                         return err;
1124                 estatus = err;
1125
1126                 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1127                 if (unlikely(err < 0))
1128                         return err;
1129                 ctrl1000 = err;
1130
1131                 err = mii_read(np, np->phy_addr, MII_STAT1000);
1132                 if (unlikely(err < 0))
1133                         return err;
1134                 stat1000 = err;
1135         } else
1136                 estatus = ctrl1000 = stat1000 = 0;
1137
1138         supported = 0;
1139         if (bmsr & BMSR_ANEGCAPABLE)
1140                 supported |= SUPPORTED_Autoneg;
1141         if (bmsr & BMSR_10HALF)
1142                 supported |= SUPPORTED_10baseT_Half;
1143         if (bmsr & BMSR_10FULL)
1144                 supported |= SUPPORTED_10baseT_Full;
1145         if (bmsr & BMSR_100HALF)
1146                 supported |= SUPPORTED_100baseT_Half;
1147         if (bmsr & BMSR_100FULL)
1148                 supported |= SUPPORTED_100baseT_Full;
1149         if (estatus & ESTATUS_1000_THALF)
1150                 supported |= SUPPORTED_1000baseT_Half;
1151         if (estatus & ESTATUS_1000_TFULL)
1152                 supported |= SUPPORTED_1000baseT_Full;
1153         lp->supported = supported;
1154
1155         advertising = 0;
1156         if (advert & ADVERTISE_10HALF)
1157                 advertising |= ADVERTISED_10baseT_Half;
1158         if (advert & ADVERTISE_10FULL)
1159                 advertising |= ADVERTISED_10baseT_Full;
1160         if (advert & ADVERTISE_100HALF)
1161                 advertising |= ADVERTISED_100baseT_Half;
1162         if (advert & ADVERTISE_100FULL)
1163                 advertising |= ADVERTISED_100baseT_Full;
1164         if (ctrl1000 & ADVERTISE_1000HALF)
1165                 advertising |= ADVERTISED_1000baseT_Half;
1166         if (ctrl1000 & ADVERTISE_1000FULL)
1167                 advertising |= ADVERTISED_1000baseT_Full;
1168
1169         if (bmcr & BMCR_ANENABLE) {
1170                 int neg, neg1000;
1171
1172                 lp->active_autoneg = 1;
1173                 advertising |= ADVERTISED_Autoneg;
1174
1175                 neg = advert & lpa;
1176                 neg1000 = (ctrl1000 << 2) & stat1000;
1177
1178                 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1179                         active_speed = SPEED_1000;
1180                 else if (neg & LPA_100)
1181                         active_speed = SPEED_100;
1182                 else if (neg & (LPA_10HALF | LPA_10FULL))
1183                         active_speed = SPEED_10;
1184                 else
1185                         active_speed = SPEED_INVALID;
1186
1187                 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1188                         active_duplex = DUPLEX_FULL;
1189                 else if (active_speed != SPEED_INVALID)
1190                         active_duplex = DUPLEX_HALF;
1191                 else
1192                         active_duplex = DUPLEX_INVALID;
1193         } else {
1194                 lp->active_autoneg = 0;
1195
1196                 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1197                         active_speed = SPEED_1000;
1198                 else if (bmcr & BMCR_SPEED100)
1199                         active_speed = SPEED_100;
1200                 else
1201                         active_speed = SPEED_10;
1202
1203                 if (bmcr & BMCR_FULLDPLX)
1204                         active_duplex = DUPLEX_FULL;
1205                 else
1206                         active_duplex = DUPLEX_HALF;
1207         }
1208
1209         lp->active_advertising = advertising;
1210         lp->active_speed = active_speed;
1211         lp->active_duplex = active_duplex;
1212         *link_up_p = !!(bmsr & BMSR_LSTATUS);
1213
1214         return 0;
1215 }
1216
1217 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1218 {
1219         struct niu_link_config *lp = &np->link_config;
1220         u16 current_speed, bmsr;
1221         unsigned long flags;
1222         u8 current_duplex;
1223         int err, link_up;
1224
1225         link_up = 0;
1226         current_speed = SPEED_INVALID;
1227         current_duplex = DUPLEX_INVALID;
1228
1229         spin_lock_irqsave(&np->lock, flags);
1230
1231         err = -EINVAL;
1232
1233         err = mii_read(np, np->phy_addr, MII_BMSR);
1234         if (err < 0)
1235                 goto out;
1236
1237         bmsr = err;
1238         if (bmsr & BMSR_LSTATUS) {
1239                 u16 adv, lpa, common, estat;
1240
1241                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1242                 if (err < 0)
1243                         goto out;
1244                 adv = err;
1245
1246                 err = mii_read(np, np->phy_addr, MII_LPA);
1247                 if (err < 0)
1248                         goto out;
1249                 lpa = err;
1250
1251                 common = adv & lpa;
1252
1253                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1254                 if (err < 0)
1255                         goto out;
1256                 estat = err;
1257                 link_up = 1;
1258                 current_speed = SPEED_1000;
1259                 current_duplex = DUPLEX_FULL;
1260
1261         }
1262         lp->active_speed = current_speed;
1263         lp->active_duplex = current_duplex;
1264         err = 0;
1265
1266 out:
1267         spin_unlock_irqrestore(&np->lock, flags);
1268
1269         *link_up_p = link_up;
1270         return err;
1271 }
1272
1273 static int link_status_1g(struct niu *np, int *link_up_p)
1274 {
1275         struct niu_link_config *lp = &np->link_config;
1276         unsigned long flags;
1277         int err;
1278
1279         spin_lock_irqsave(&np->lock, flags);
1280
1281         err = link_status_mii(np, link_up_p);
1282         lp->supported |= SUPPORTED_TP;
1283         lp->active_advertising |= ADVERTISED_TP;
1284
1285         spin_unlock_irqrestore(&np->lock, flags);
1286         return err;
1287 }
1288
1289 static int bcm8704_reset(struct niu *np)
1290 {
1291         int err, limit;
1292
1293         err = mdio_read(np, np->phy_addr,
1294                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1295         if (err < 0 || err == 0xffff)
1296                 return err;
1297         err |= BMCR_RESET;
1298         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1299                          MII_BMCR, err);
1300         if (err)
1301                 return err;
1302
1303         limit = 1000;
1304         while (--limit >= 0) {
1305                 err = mdio_read(np, np->phy_addr,
1306                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1307                 if (err < 0)
1308                         return err;
1309                 if (!(err & BMCR_RESET))
1310                         break;
1311         }
1312         if (limit < 0) {
1313                 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1314                            np->port, (err & 0xffff));
1315                 return -ENODEV;
1316         }
1317         return 0;
1318 }
1319
1320 /* When written, certain PHY registers need to be read back twice
1321  * in order for the bits to settle properly.
1322  */
1323 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1324 {
1325         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326         if (err < 0)
1327                 return err;
1328         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1329         if (err < 0)
1330                 return err;
1331         return 0;
1332 }
1333
1334 static int bcm8706_init_user_dev3(struct niu *np)
1335 {
1336         int err;
1337
1338
1339         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1340                         BCM8704_USER_OPT_DIGITAL_CTRL);
1341         if (err < 0)
1342                 return err;
1343         err &= ~USER_ODIG_CTRL_GPIOS;
1344         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1345         err |=  USER_ODIG_CTRL_RESV2;
1346         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1347                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1348         if (err)
1349                 return err;
1350
1351         mdelay(1000);
1352
1353         return 0;
1354 }
1355
1356 static int bcm8704_init_user_dev3(struct niu *np)
1357 {
1358         int err;
1359
1360         err = mdio_write(np, np->phy_addr,
1361                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1362                          (USER_CONTROL_OPTXRST_LVL |
1363                           USER_CONTROL_OPBIASFLT_LVL |
1364                           USER_CONTROL_OBTMPFLT_LVL |
1365                           USER_CONTROL_OPPRFLT_LVL |
1366                           USER_CONTROL_OPTXFLT_LVL |
1367                           USER_CONTROL_OPRXLOS_LVL |
1368                           USER_CONTROL_OPRXFLT_LVL |
1369                           USER_CONTROL_OPTXON_LVL |
1370                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1371         if (err)
1372                 return err;
1373
1374         err = mdio_write(np, np->phy_addr,
1375                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1376                          (USER_PMD_TX_CTL_XFP_CLKEN |
1377                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1378                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1379                           USER_PMD_TX_CTL_TSCK_LPWREN));
1380         if (err)
1381                 return err;
1382
1383         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1384         if (err)
1385                 return err;
1386         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1387         if (err)
1388                 return err;
1389
1390         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1391                         BCM8704_USER_OPT_DIGITAL_CTRL);
1392         if (err < 0)
1393                 return err;
1394         err &= ~USER_ODIG_CTRL_GPIOS;
1395         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1396         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1397                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1398         if (err)
1399                 return err;
1400
1401         mdelay(1000);
1402
1403         return 0;
1404 }
1405
1406 static int mrvl88x2011_act_led(struct niu *np, int val)
1407 {
1408         int     err;
1409
1410         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1411                 MRVL88X2011_LED_8_TO_11_CTL);
1412         if (err < 0)
1413                 return err;
1414
1415         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1416         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1417
1418         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1419                           MRVL88X2011_LED_8_TO_11_CTL, err);
1420 }
1421
1422 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1423 {
1424         int     err;
1425
1426         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1427                         MRVL88X2011_LED_BLINK_CTL);
1428         if (err >= 0) {
1429                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1430                 err |= (rate << 4);
1431
1432                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1433                                  MRVL88X2011_LED_BLINK_CTL, err);
1434         }
1435
1436         return err;
1437 }
1438
1439 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1440 {
1441         int     err;
1442
1443         /* Set LED functions */
1444         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1445         if (err)
1446                 return err;
1447
1448         /* led activity */
1449         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1450         if (err)
1451                 return err;
1452
1453         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1454                         MRVL88X2011_GENERAL_CTL);
1455         if (err < 0)
1456                 return err;
1457
1458         err |= MRVL88X2011_ENA_XFPREFCLK;
1459
1460         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1461                          MRVL88X2011_GENERAL_CTL, err);
1462         if (err < 0)
1463                 return err;
1464
1465         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1466                         MRVL88X2011_PMA_PMD_CTL_1);
1467         if (err < 0)
1468                 return err;
1469
1470         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1471                 err |= MRVL88X2011_LOOPBACK;
1472         else
1473                 err &= ~MRVL88X2011_LOOPBACK;
1474
1475         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1476                          MRVL88X2011_PMA_PMD_CTL_1, err);
1477         if (err < 0)
1478                 return err;
1479
1480         /* Enable PMD  */
1481         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1482                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1483 }
1484
1485
1486 static int xcvr_diag_bcm870x(struct niu *np)
1487 {
1488         u16 analog_stat0, tx_alarm_status;
1489         int err = 0;
1490
1491 #if 1
1492         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1493                         MII_STAT1000);
1494         if (err < 0)
1495                 return err;
1496         pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1497
1498         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1499         if (err < 0)
1500                 return err;
1501         pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1502
1503         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1504                         MII_NWAYTEST);
1505         if (err < 0)
1506                 return err;
1507         pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1508 #endif
1509
1510         /* XXX dig this out it might not be so useful XXX */
1511         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1512                         BCM8704_USER_ANALOG_STATUS0);
1513         if (err < 0)
1514                 return err;
1515         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1516                         BCM8704_USER_ANALOG_STATUS0);
1517         if (err < 0)
1518                 return err;
1519         analog_stat0 = err;
1520
1521         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1522                         BCM8704_USER_TX_ALARM_STATUS);
1523         if (err < 0)
1524                 return err;
1525         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1526                         BCM8704_USER_TX_ALARM_STATUS);
1527         if (err < 0)
1528                 return err;
1529         tx_alarm_status = err;
1530
1531         if (analog_stat0 != 0x03fc) {
1532                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1533                         pr_info("Port %u cable not connected or bad cable\n",
1534                                 np->port);
1535                 } else if (analog_stat0 == 0x639c) {
1536                         pr_info("Port %u optical module is bad or missing\n",
1537                                 np->port);
1538                 }
1539         }
1540
1541         return 0;
1542 }
1543
1544 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1545 {
1546         struct niu_link_config *lp = &np->link_config;
1547         int err;
1548
1549         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1550                         MII_BMCR);
1551         if (err < 0)
1552                 return err;
1553
1554         err &= ~BMCR_LOOPBACK;
1555
1556         if (lp->loopback_mode == LOOPBACK_MAC)
1557                 err |= BMCR_LOOPBACK;
1558
1559         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1560                          MII_BMCR, err);
1561         if (err)
1562                 return err;
1563
1564         return 0;
1565 }
1566
1567 static int xcvr_init_10g_bcm8706(struct niu *np)
1568 {
1569         int err = 0;
1570         u64 val;
1571
1572         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1573             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1574                         return err;
1575
1576         val = nr64_mac(XMAC_CONFIG);
1577         val &= ~XMAC_CONFIG_LED_POLARITY;
1578         val |= XMAC_CONFIG_FORCE_LED_ON;
1579         nw64_mac(XMAC_CONFIG, val);
1580
1581         val = nr64(MIF_CONFIG);
1582         val |= MIF_CONFIG_INDIRECT_MODE;
1583         nw64(MIF_CONFIG, val);
1584
1585         err = bcm8704_reset(np);
1586         if (err)
1587                 return err;
1588
1589         err = xcvr_10g_set_lb_bcm870x(np);
1590         if (err)
1591                 return err;
1592
1593         err = bcm8706_init_user_dev3(np);
1594         if (err)
1595                 return err;
1596
1597         err = xcvr_diag_bcm870x(np);
1598         if (err)
1599                 return err;
1600
1601         return 0;
1602 }
1603
1604 static int xcvr_init_10g_bcm8704(struct niu *np)
1605 {
1606         int err;
1607
1608         err = bcm8704_reset(np);
1609         if (err)
1610                 return err;
1611
1612         err = bcm8704_init_user_dev3(np);
1613         if (err)
1614                 return err;
1615
1616         err = xcvr_10g_set_lb_bcm870x(np);
1617         if (err)
1618                 return err;
1619
1620         err =  xcvr_diag_bcm870x(np);
1621         if (err)
1622                 return err;
1623
1624         return 0;
1625 }
1626
1627 static int xcvr_init_10g(struct niu *np)
1628 {
1629         int phy_id, err;
1630         u64 val;
1631
1632         val = nr64_mac(XMAC_CONFIG);
1633         val &= ~XMAC_CONFIG_LED_POLARITY;
1634         val |= XMAC_CONFIG_FORCE_LED_ON;
1635         nw64_mac(XMAC_CONFIG, val);
1636
1637         /* XXX shared resource, lock parent XXX */
1638         val = nr64(MIF_CONFIG);
1639         val |= MIF_CONFIG_INDIRECT_MODE;
1640         nw64(MIF_CONFIG, val);
1641
1642         phy_id = phy_decode(np->parent->port_phy, np->port);
1643         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1644
1645         /* handle different phy types */
1646         switch (phy_id & NIU_PHY_ID_MASK) {
1647         case NIU_PHY_ID_MRVL88X2011:
1648                 err = xcvr_init_10g_mrvl88x2011(np);
1649                 break;
1650
1651         default: /* bcom 8704 */
1652                 err = xcvr_init_10g_bcm8704(np);
1653                 break;
1654         }
1655
1656         return 0;
1657 }
1658
1659 static int mii_reset(struct niu *np)
1660 {
1661         int limit, err;
1662
1663         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1664         if (err)
1665                 return err;
1666
1667         limit = 1000;
1668         while (--limit >= 0) {
1669                 udelay(500);
1670                 err = mii_read(np, np->phy_addr, MII_BMCR);
1671                 if (err < 0)
1672                         return err;
1673                 if (!(err & BMCR_RESET))
1674                         break;
1675         }
1676         if (limit < 0) {
1677                 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1678                            np->port, err);
1679                 return -ENODEV;
1680         }
1681
1682         return 0;
1683 }
1684
1685 static int xcvr_init_1g_rgmii(struct niu *np)
1686 {
1687         int err;
1688         u64 val;
1689         u16 bmcr, bmsr, estat;
1690
1691         val = nr64(MIF_CONFIG);
1692         val &= ~MIF_CONFIG_INDIRECT_MODE;
1693         nw64(MIF_CONFIG, val);
1694
1695         err = mii_reset(np);
1696         if (err)
1697                 return err;
1698
1699         err = mii_read(np, np->phy_addr, MII_BMSR);
1700         if (err < 0)
1701                 return err;
1702         bmsr = err;
1703
1704         estat = 0;
1705         if (bmsr & BMSR_ESTATEN) {
1706                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1707                 if (err < 0)
1708                         return err;
1709                 estat = err;
1710         }
1711
1712         bmcr = 0;
1713         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1714         if (err)
1715                 return err;
1716
1717         if (bmsr & BMSR_ESTATEN) {
1718                 u16 ctrl1000 = 0;
1719
1720                 if (estat & ESTATUS_1000_TFULL)
1721                         ctrl1000 |= ADVERTISE_1000FULL;
1722                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1723                 if (err)
1724                         return err;
1725         }
1726
1727         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1728
1729         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1730         if (err)
1731                 return err;
1732
1733         err = mii_read(np, np->phy_addr, MII_BMCR);
1734         if (err < 0)
1735                 return err;
1736         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1737
1738         err = mii_read(np, np->phy_addr, MII_BMSR);
1739         if (err < 0)
1740                 return err;
1741
1742         return 0;
1743 }
1744
1745 static int mii_init_common(struct niu *np)
1746 {
1747         struct niu_link_config *lp = &np->link_config;
1748         u16 bmcr, bmsr, adv, estat;
1749         int err;
1750
1751         err = mii_reset(np);
1752         if (err)
1753                 return err;
1754
1755         err = mii_read(np, np->phy_addr, MII_BMSR);
1756         if (err < 0)
1757                 return err;
1758         bmsr = err;
1759
1760         estat = 0;
1761         if (bmsr & BMSR_ESTATEN) {
1762                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1763                 if (err < 0)
1764                         return err;
1765                 estat = err;
1766         }
1767
1768         bmcr = 0;
1769         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1770         if (err)
1771                 return err;
1772
1773         if (lp->loopback_mode == LOOPBACK_MAC) {
1774                 bmcr |= BMCR_LOOPBACK;
1775                 if (lp->active_speed == SPEED_1000)
1776                         bmcr |= BMCR_SPEED1000;
1777                 if (lp->active_duplex == DUPLEX_FULL)
1778                         bmcr |= BMCR_FULLDPLX;
1779         }
1780
1781         if (lp->loopback_mode == LOOPBACK_PHY) {
1782                 u16 aux;
1783
1784                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1785                        BCM5464R_AUX_CTL_WRITE_1);
1786                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1787                 if (err)
1788                         return err;
1789         }
1790
1791         if (lp->autoneg) {
1792                 u16 ctrl1000;
1793
1794                 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1795                 if ((bmsr & BMSR_10HALF) &&
1796                         (lp->advertising & ADVERTISED_10baseT_Half))
1797                         adv |= ADVERTISE_10HALF;
1798                 if ((bmsr & BMSR_10FULL) &&
1799                         (lp->advertising & ADVERTISED_10baseT_Full))
1800                         adv |= ADVERTISE_10FULL;
1801                 if ((bmsr & BMSR_100HALF) &&
1802                         (lp->advertising & ADVERTISED_100baseT_Half))
1803                         adv |= ADVERTISE_100HALF;
1804                 if ((bmsr & BMSR_100FULL) &&
1805                         (lp->advertising & ADVERTISED_100baseT_Full))
1806                         adv |= ADVERTISE_100FULL;
1807                 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1808                 if (err)
1809                         return err;
1810
1811                 if (likely(bmsr & BMSR_ESTATEN)) {
1812                         ctrl1000 = 0;
1813                         if ((estat & ESTATUS_1000_THALF) &&
1814                                 (lp->advertising & ADVERTISED_1000baseT_Half))
1815                                 ctrl1000 |= ADVERTISE_1000HALF;
1816                         if ((estat & ESTATUS_1000_TFULL) &&
1817                                 (lp->advertising & ADVERTISED_1000baseT_Full))
1818                                 ctrl1000 |= ADVERTISE_1000FULL;
1819                         err = mii_write(np, np->phy_addr,
1820                                         MII_CTRL1000, ctrl1000);
1821                         if (err)
1822                                 return err;
1823                 }
1824
1825                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1826         } else {
1827                 /* !lp->autoneg */
1828                 int fulldpx;
1829
1830                 if (lp->duplex == DUPLEX_FULL) {
1831                         bmcr |= BMCR_FULLDPLX;
1832                         fulldpx = 1;
1833                 } else if (lp->duplex == DUPLEX_HALF)
1834                         fulldpx = 0;
1835                 else
1836                         return -EINVAL;
1837
1838                 if (lp->speed == SPEED_1000) {
1839                         /* if X-full requested while not supported, or
1840                            X-half requested while not supported... */
1841                         if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1842                                 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1843                                 return -EINVAL;
1844                         bmcr |= BMCR_SPEED1000;
1845                 } else if (lp->speed == SPEED_100) {
1846                         if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1847                                 (!fulldpx && !(bmsr & BMSR_100HALF)))
1848                                 return -EINVAL;
1849                         bmcr |= BMCR_SPEED100;
1850                 } else if (lp->speed == SPEED_10) {
1851                         if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1852                                 (!fulldpx && !(bmsr & BMSR_10HALF)))
1853                                 return -EINVAL;
1854                 } else
1855                         return -EINVAL;
1856         }
1857
1858         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1859         if (err)
1860                 return err;
1861
1862 #if 0
1863         err = mii_read(np, np->phy_addr, MII_BMCR);
1864         if (err < 0)
1865                 return err;
1866         bmcr = err;
1867
1868         err = mii_read(np, np->phy_addr, MII_BMSR);
1869         if (err < 0)
1870                 return err;
1871         bmsr = err;
1872
1873         pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1874                 np->port, bmcr, bmsr);
1875 #endif
1876
1877         return 0;
1878 }
1879
1880 static int xcvr_init_1g(struct niu *np)
1881 {
1882         u64 val;
1883
1884         /* XXX shared resource, lock parent XXX */
1885         val = nr64(MIF_CONFIG);
1886         val &= ~MIF_CONFIG_INDIRECT_MODE;
1887         nw64(MIF_CONFIG, val);
1888
1889         return mii_init_common(np);
1890 }
1891
1892 static int niu_xcvr_init(struct niu *np)
1893 {
1894         const struct niu_phy_ops *ops = np->phy_ops;
1895         int err;
1896
1897         err = 0;
1898         if (ops->xcvr_init)
1899                 err = ops->xcvr_init(np);
1900
1901         return err;
1902 }
1903
1904 static int niu_serdes_init(struct niu *np)
1905 {
1906         const struct niu_phy_ops *ops = np->phy_ops;
1907         int err;
1908
1909         err = 0;
1910         if (ops->serdes_init)
1911                 err = ops->serdes_init(np);
1912
1913         return err;
1914 }
1915
1916 static void niu_init_xif(struct niu *);
1917 static void niu_handle_led(struct niu *, int status);
1918
1919 static int niu_link_status_common(struct niu *np, int link_up)
1920 {
1921         struct niu_link_config *lp = &np->link_config;
1922         struct net_device *dev = np->dev;
1923         unsigned long flags;
1924
1925         if (!netif_carrier_ok(dev) && link_up) {
1926                 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1927                            lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1928                            lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1929                            lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1930                            "10Mbit/sec",
1931                            lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1932
1933                 spin_lock_irqsave(&np->lock, flags);
1934                 niu_init_xif(np);
1935                 niu_handle_led(np, 1);
1936                 spin_unlock_irqrestore(&np->lock, flags);
1937
1938                 netif_carrier_on(dev);
1939         } else if (netif_carrier_ok(dev) && !link_up) {
1940                 netif_warn(np, link, dev, "Link is down\n");
1941                 spin_lock_irqsave(&np->lock, flags);
1942                 niu_handle_led(np, 0);
1943                 spin_unlock_irqrestore(&np->lock, flags);
1944                 netif_carrier_off(dev);
1945         }
1946
1947         return 0;
1948 }
1949
1950 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1951 {
1952         int err, link_up, pma_status, pcs_status;
1953
1954         link_up = 0;
1955
1956         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1957                         MRVL88X2011_10G_PMD_STATUS_2);
1958         if (err < 0)
1959                 goto out;
1960
1961         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1962         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1963                         MRVL88X2011_PMA_PMD_STATUS_1);
1964         if (err < 0)
1965                 goto out;
1966
1967         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1968
1969         /* Check PMC Register : 3.0001.2 == 1: read twice */
1970         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1971                         MRVL88X2011_PMA_PMD_STATUS_1);
1972         if (err < 0)
1973                 goto out;
1974
1975         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1976                         MRVL88X2011_PMA_PMD_STATUS_1);
1977         if (err < 0)
1978                 goto out;
1979
1980         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1981
1982         /* Check XGXS Register : 4.0018.[0-3,12] */
1983         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1984                         MRVL88X2011_10G_XGXS_LANE_STAT);
1985         if (err < 0)
1986                 goto out;
1987
1988         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1989                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1990                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1991                     0x800))
1992                 link_up = (pma_status && pcs_status) ? 1 : 0;
1993
1994         np->link_config.active_speed = SPEED_10000;
1995         np->link_config.active_duplex = DUPLEX_FULL;
1996         err = 0;
1997 out:
1998         mrvl88x2011_act_led(np, (link_up ?
1999                                  MRVL88X2011_LED_CTL_PCS_ACT :
2000                                  MRVL88X2011_LED_CTL_OFF));
2001
2002         *link_up_p = link_up;
2003         return err;
2004 }
2005
2006 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2007 {
2008         int err, link_up;
2009         link_up = 0;
2010
2011         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2012                         BCM8704_PMD_RCV_SIGDET);
2013         if (err < 0 || err == 0xffff)
2014                 goto out;
2015         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2016                 err = 0;
2017                 goto out;
2018         }
2019
2020         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2021                         BCM8704_PCS_10G_R_STATUS);
2022         if (err < 0)
2023                 goto out;
2024
2025         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2026                 err = 0;
2027                 goto out;
2028         }
2029
2030         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2031                         BCM8704_PHYXS_XGXS_LANE_STAT);
2032         if (err < 0)
2033                 goto out;
2034         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2035                     PHYXS_XGXS_LANE_STAT_MAGIC |
2036                     PHYXS_XGXS_LANE_STAT_PATTEST |
2037                     PHYXS_XGXS_LANE_STAT_LANE3 |
2038                     PHYXS_XGXS_LANE_STAT_LANE2 |
2039                     PHYXS_XGXS_LANE_STAT_LANE1 |
2040                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2041                 err = 0;
2042                 np->link_config.active_speed = SPEED_INVALID;
2043                 np->link_config.active_duplex = DUPLEX_INVALID;
2044                 goto out;
2045         }
2046
2047         link_up = 1;
2048         np->link_config.active_speed = SPEED_10000;
2049         np->link_config.active_duplex = DUPLEX_FULL;
2050         err = 0;
2051
2052 out:
2053         *link_up_p = link_up;
2054         return err;
2055 }
2056
2057 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2058 {
2059         int err, link_up;
2060
2061         link_up = 0;
2062
2063         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2064                         BCM8704_PMD_RCV_SIGDET);
2065         if (err < 0)
2066                 goto out;
2067         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2068                 err = 0;
2069                 goto out;
2070         }
2071
2072         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2073                         BCM8704_PCS_10G_R_STATUS);
2074         if (err < 0)
2075                 goto out;
2076         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2077                 err = 0;
2078                 goto out;
2079         }
2080
2081         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2082                         BCM8704_PHYXS_XGXS_LANE_STAT);
2083         if (err < 0)
2084                 goto out;
2085
2086         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2087                     PHYXS_XGXS_LANE_STAT_MAGIC |
2088                     PHYXS_XGXS_LANE_STAT_LANE3 |
2089                     PHYXS_XGXS_LANE_STAT_LANE2 |
2090                     PHYXS_XGXS_LANE_STAT_LANE1 |
2091                     PHYXS_XGXS_LANE_STAT_LANE0)) {
2092                 err = 0;
2093                 goto out;
2094         }
2095
2096         link_up = 1;
2097         np->link_config.active_speed = SPEED_10000;
2098         np->link_config.active_duplex = DUPLEX_FULL;
2099         err = 0;
2100
2101 out:
2102         *link_up_p = link_up;
2103         return err;
2104 }
2105
2106 static int link_status_10g(struct niu *np, int *link_up_p)
2107 {
2108         unsigned long flags;
2109         int err = -EINVAL;
2110
2111         spin_lock_irqsave(&np->lock, flags);
2112
2113         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2114                 int phy_id;
2115
2116                 phy_id = phy_decode(np->parent->port_phy, np->port);
2117                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2118
2119                 /* handle different phy types */
2120                 switch (phy_id & NIU_PHY_ID_MASK) {
2121                 case NIU_PHY_ID_MRVL88X2011:
2122                         err = link_status_10g_mrvl(np, link_up_p);
2123                         break;
2124
2125                 default: /* bcom 8704 */
2126                         err = link_status_10g_bcom(np, link_up_p);
2127                         break;
2128                 }
2129         }
2130
2131         spin_unlock_irqrestore(&np->lock, flags);
2132
2133         return err;
2134 }
2135
2136 static int niu_10g_phy_present(struct niu *np)
2137 {
2138         u64 sig, mask, val;
2139
2140         sig = nr64(ESR_INT_SIGNALS);
2141         switch (np->port) {
2142         case 0:
2143                 mask = ESR_INT_SIGNALS_P0_BITS;
2144                 val = (ESR_INT_SRDY0_P0 |
2145                        ESR_INT_DET0_P0 |
2146                        ESR_INT_XSRDY_P0 |
2147                        ESR_INT_XDP_P0_CH3 |
2148                        ESR_INT_XDP_P0_CH2 |
2149                        ESR_INT_XDP_P0_CH1 |
2150                        ESR_INT_XDP_P0_CH0);
2151                 break;
2152
2153         case 1:
2154                 mask = ESR_INT_SIGNALS_P1_BITS;
2155                 val = (ESR_INT_SRDY0_P1 |
2156                        ESR_INT_DET0_P1 |
2157                        ESR_INT_XSRDY_P1 |
2158                        ESR_INT_XDP_P1_CH3 |
2159                        ESR_INT_XDP_P1_CH2 |
2160                        ESR_INT_XDP_P1_CH1 |
2161                        ESR_INT_XDP_P1_CH0);
2162                 break;
2163
2164         default:
2165                 return 0;
2166         }
2167
2168         if ((sig & mask) != val)
2169                 return 0;
2170         return 1;
2171 }
2172
2173 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2174 {
2175         unsigned long flags;
2176         int err = 0;
2177         int phy_present;
2178         int phy_present_prev;
2179
2180         spin_lock_irqsave(&np->lock, flags);
2181
2182         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2183                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2184                         1 : 0;
2185                 phy_present = niu_10g_phy_present(np);
2186                 if (phy_present != phy_present_prev) {
2187                         /* state change */
2188                         if (phy_present) {
2189                                 /* A NEM was just plugged in */
2190                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2191                                 if (np->phy_ops->xcvr_init)
2192                                         err = np->phy_ops->xcvr_init(np);
2193                                 if (err) {
2194                                         err = mdio_read(np, np->phy_addr,
2195                                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2196                                         if (err == 0xffff) {
2197                                                 /* No mdio, back-to-back XAUI */
2198                                                 goto out;
2199                                         }
2200                                         /* debounce */
2201                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202                                 }
2203                         } else {
2204                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2205                                 *link_up_p = 0;
2206                                 netif_warn(np, link, np->dev,
2207                                            "Hotplug PHY Removed\n");
2208                         }
2209                 }
2210 out:
2211                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2212                         err = link_status_10g_bcm8706(np, link_up_p);
2213                         if (err == 0xffff) {
2214                                 /* No mdio, back-to-back XAUI: it is C10NEM */
2215                                 *link_up_p = 1;
2216                                 np->link_config.active_speed = SPEED_10000;
2217                                 np->link_config.active_duplex = DUPLEX_FULL;
2218                         }
2219                 }
2220         }
2221
2222         spin_unlock_irqrestore(&np->lock, flags);
2223
2224         return 0;
2225 }
2226
2227 static int niu_link_status(struct niu *np, int *link_up_p)
2228 {
2229         const struct niu_phy_ops *ops = np->phy_ops;
2230         int err;
2231
2232         err = 0;
2233         if (ops->link_status)
2234                 err = ops->link_status(np, link_up_p);
2235
2236         return err;
2237 }
2238
2239 static void niu_timer(unsigned long __opaque)
2240 {
2241         struct niu *np = (struct niu *) __opaque;
2242         unsigned long off;
2243         int err, link_up;
2244
2245         err = niu_link_status(np, &link_up);
2246         if (!err)
2247                 niu_link_status_common(np, link_up);
2248
2249         if (netif_carrier_ok(np->dev))
2250                 off = 5 * HZ;
2251         else
2252                 off = 1 * HZ;
2253         np->timer.expires = jiffies + off;
2254
2255         add_timer(&np->timer);
2256 }
2257
2258 static const struct niu_phy_ops phy_ops_10g_serdes = {
2259         .serdes_init            = serdes_init_10g_serdes,
2260         .link_status            = link_status_10g_serdes,
2261 };
2262
2263 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2264         .serdes_init            = serdes_init_niu_10g_serdes,
2265         .link_status            = link_status_10g_serdes,
2266 };
2267
2268 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2269         .serdes_init            = serdes_init_niu_1g_serdes,
2270         .link_status            = link_status_1g_serdes,
2271 };
2272
2273 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2274         .xcvr_init              = xcvr_init_1g_rgmii,
2275         .link_status            = link_status_1g_rgmii,
2276 };
2277
2278 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2279         .serdes_init            = serdes_init_niu_10g_fiber,
2280         .xcvr_init              = xcvr_init_10g,
2281         .link_status            = link_status_10g,
2282 };
2283
2284 static const struct niu_phy_ops phy_ops_10g_fiber = {
2285         .serdes_init            = serdes_init_10g,
2286         .xcvr_init              = xcvr_init_10g,
2287         .link_status            = link_status_10g,
2288 };
2289
2290 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2291         .serdes_init            = serdes_init_10g,
2292         .xcvr_init              = xcvr_init_10g_bcm8706,
2293         .link_status            = link_status_10g_hotplug,
2294 };
2295
2296 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2297         .serdes_init            = serdes_init_niu_10g_fiber,
2298         .xcvr_init              = xcvr_init_10g_bcm8706,
2299         .link_status            = link_status_10g_hotplug,
2300 };
2301
2302 static const struct niu_phy_ops phy_ops_10g_copper = {
2303         .serdes_init            = serdes_init_10g,
2304         .link_status            = link_status_10g, /* XXX */
2305 };
2306
2307 static const struct niu_phy_ops phy_ops_1g_fiber = {
2308         .serdes_init            = serdes_init_1g,
2309         .xcvr_init              = xcvr_init_1g,
2310         .link_status            = link_status_1g,
2311 };
2312
2313 static const struct niu_phy_ops phy_ops_1g_copper = {
2314         .xcvr_init              = xcvr_init_1g,
2315         .link_status            = link_status_1g,
2316 };
2317
2318 struct niu_phy_template {
2319         const struct niu_phy_ops        *ops;
2320         u32                             phy_addr_base;
2321 };
2322
2323 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2324         .ops            = &phy_ops_10g_fiber_niu,
2325         .phy_addr_base  = 16,
2326 };
2327
2328 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2329         .ops            = &phy_ops_10g_serdes_niu,
2330         .phy_addr_base  = 0,
2331 };
2332
2333 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2334         .ops            = &phy_ops_1g_serdes_niu,
2335         .phy_addr_base  = 0,
2336 };
2337
2338 static const struct niu_phy_template phy_template_10g_fiber = {
2339         .ops            = &phy_ops_10g_fiber,
2340         .phy_addr_base  = 8,
2341 };
2342
2343 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2344         .ops            = &phy_ops_10g_fiber_hotplug,
2345         .phy_addr_base  = 8,
2346 };
2347
2348 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2349         .ops            = &phy_ops_niu_10g_hotplug,
2350         .phy_addr_base  = 8,
2351 };
2352
2353 static const struct niu_phy_template phy_template_10g_copper = {
2354         .ops            = &phy_ops_10g_copper,
2355         .phy_addr_base  = 10,
2356 };
2357
2358 static const struct niu_phy_template phy_template_1g_fiber = {
2359         .ops            = &phy_ops_1g_fiber,
2360         .phy_addr_base  = 0,
2361 };
2362
2363 static const struct niu_phy_template phy_template_1g_copper = {
2364         .ops            = &phy_ops_1g_copper,
2365         .phy_addr_base  = 0,
2366 };
2367
2368 static const struct niu_phy_template phy_template_1g_rgmii = {
2369         .ops            = &phy_ops_1g_rgmii,
2370         .phy_addr_base  = 0,
2371 };
2372
2373 static const struct niu_phy_template phy_template_10g_serdes = {
2374         .ops            = &phy_ops_10g_serdes,
2375         .phy_addr_base  = 0,
2376 };
2377
2378 static int niu_atca_port_num[4] = {
2379         0, 0,  11, 10
2380 };
2381
2382 static int serdes_init_10g_serdes(struct niu *np)
2383 {
2384         struct niu_link_config *lp = &np->link_config;
2385         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2386         u64 ctrl_val, test_cfg_val, sig, mask, val;
2387         u64 reset_val;
2388
2389         switch (np->port) {
2390         case 0:
2391                 reset_val =  ENET_SERDES_RESET_0;
2392                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2393                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2394                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2395                 break;
2396         case 1:
2397                 reset_val =  ENET_SERDES_RESET_1;
2398                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2399                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2400                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2401                 break;
2402
2403         default:
2404                 return -EINVAL;
2405         }
2406         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2407                     ENET_SERDES_CTRL_SDET_1 |
2408                     ENET_SERDES_CTRL_SDET_2 |
2409                     ENET_SERDES_CTRL_SDET_3 |
2410                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2411                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2412                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2413                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2414                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2415                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2416                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2417                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2418         test_cfg_val = 0;
2419
2420         if (lp->loopback_mode == LOOPBACK_PHY) {
2421                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2422                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2423                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2424                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2425                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2426                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2427                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2428                                   ENET_SERDES_TEST_MD_3_SHIFT));
2429         }
2430
2431         esr_reset(np);
2432         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2433         nw64(ctrl_reg, ctrl_val);
2434         nw64(test_cfg_reg, test_cfg_val);
2435
2436         /* Initialize all 4 lanes of the SERDES.  */
2437         for (i = 0; i < 4; i++) {
2438                 u32 rxtx_ctrl, glue0;
2439                 int err;
2440
2441                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2442                 if (err)
2443                         return err;
2444                 err = esr_read_glue0(np, i, &glue0);
2445                 if (err)
2446                         return err;
2447
2448                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2449                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2450                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2451
2452                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2453                            ESR_GLUE_CTRL0_THCNT |
2454                            ESR_GLUE_CTRL0_BLTIME);
2455                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2456                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2457                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2458                           (BLTIME_300_CYCLES <<
2459                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2460
2461                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2462                 if (err)
2463                         return err;
2464                 err = esr_write_glue0(np, i, glue0);
2465                 if (err)
2466                         return err;
2467         }
2468
2469
2470         sig = nr64(ESR_INT_SIGNALS);
2471         switch (np->port) {
2472         case 0:
2473                 mask = ESR_INT_SIGNALS_P0_BITS;
2474                 val = (ESR_INT_SRDY0_P0 |
2475                        ESR_INT_DET0_P0 |
2476                        ESR_INT_XSRDY_P0 |
2477                        ESR_INT_XDP_P0_CH3 |
2478                        ESR_INT_XDP_P0_CH2 |
2479                        ESR_INT_XDP_P0_CH1 |
2480                        ESR_INT_XDP_P0_CH0);
2481                 break;
2482
2483         case 1:
2484                 mask = ESR_INT_SIGNALS_P1_BITS;
2485                 val = (ESR_INT_SRDY0_P1 |
2486                        ESR_INT_DET0_P1 |
2487                        ESR_INT_XSRDY_P1 |
2488                        ESR_INT_XDP_P1_CH3 |
2489                        ESR_INT_XDP_P1_CH2 |
2490                        ESR_INT_XDP_P1_CH1 |
2491                        ESR_INT_XDP_P1_CH0);
2492                 break;
2493
2494         default:
2495                 return -EINVAL;
2496         }
2497
2498         if ((sig & mask) != val) {
2499                 int err;
2500                 err = serdes_init_1g_serdes(np);
2501                 if (!err) {
2502                         np->flags &= ~NIU_FLAGS_10G;
2503                         np->mac_xcvr = MAC_XCVR_PCS;
2504                 }  else {
2505                         netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2506                                    np->port);
2507                         return -ENODEV;
2508                 }
2509         }
2510
2511         return 0;
2512 }
2513
2514 static int niu_determine_phy_disposition(struct niu *np)
2515 {
2516         struct niu_parent *parent = np->parent;
2517         u8 plat_type = parent->plat_type;
2518         const struct niu_phy_template *tp;
2519         u32 phy_addr_off = 0;
2520
2521         if (plat_type == PLAT_TYPE_NIU) {
2522                 switch (np->flags &
2523                         (NIU_FLAGS_10G |
2524                          NIU_FLAGS_FIBER |
2525                          NIU_FLAGS_XCVR_SERDES)) {
2526                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2527                         /* 10G Serdes */
2528                         tp = &phy_template_niu_10g_serdes;
2529                         break;
2530                 case NIU_FLAGS_XCVR_SERDES:
2531                         /* 1G Serdes */
2532                         tp = &phy_template_niu_1g_serdes;
2533                         break;
2534                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2535                         /* 10G Fiber */
2536                 default:
2537                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2538                                 tp = &phy_template_niu_10g_hotplug;
2539                                 if (np->port == 0)
2540                                         phy_addr_off = 8;
2541                                 if (np->port == 1)
2542                                         phy_addr_off = 12;
2543                         } else {
2544                                 tp = &phy_template_niu_10g_fiber;
2545                                 phy_addr_off += np->port;
2546                         }
2547                         break;
2548                 }
2549         } else {
2550                 switch (np->flags &
2551                         (NIU_FLAGS_10G |
2552                          NIU_FLAGS_FIBER |
2553                          NIU_FLAGS_XCVR_SERDES)) {
2554                 case 0:
2555                         /* 1G copper */
2556                         tp = &phy_template_1g_copper;
2557                         if (plat_type == PLAT_TYPE_VF_P0)
2558                                 phy_addr_off = 10;
2559                         else if (plat_type == PLAT_TYPE_VF_P1)
2560                                 phy_addr_off = 26;
2561
2562                         phy_addr_off += (np->port ^ 0x3);
2563                         break;
2564
2565                 case NIU_FLAGS_10G:
2566                         /* 10G copper */
2567                         tp = &phy_template_10g_copper;
2568                         break;
2569
2570                 case NIU_FLAGS_FIBER:
2571                         /* 1G fiber */
2572                         tp = &phy_template_1g_fiber;
2573                         break;
2574
2575                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2576                         /* 10G fiber */
2577                         tp = &phy_template_10g_fiber;
2578                         if (plat_type == PLAT_TYPE_VF_P0 ||
2579                             plat_type == PLAT_TYPE_VF_P1)
2580                                 phy_addr_off = 8;
2581                         phy_addr_off += np->port;
2582                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2583                                 tp = &phy_template_10g_fiber_hotplug;
2584                                 if (np->port == 0)
2585                                         phy_addr_off = 8;
2586                                 if (np->port == 1)
2587                                         phy_addr_off = 12;
2588                         }
2589                         break;
2590
2591                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2592                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2593                 case NIU_FLAGS_XCVR_SERDES:
2594                         switch(np->port) {
2595                         case 0:
2596                         case 1:
2597                                 tp = &phy_template_10g_serdes;
2598                                 break;
2599                         case 2:
2600                         case 3:
2601                                 tp = &phy_template_1g_rgmii;
2602                                 break;
2603                         default:
2604                                 return -EINVAL;
2605                                 break;
2606                         }
2607                         phy_addr_off = niu_atca_port_num[np->port];
2608                         break;
2609
2610                 default:
2611                         return -EINVAL;
2612                 }
2613         }
2614
2615         np->phy_ops = tp->ops;
2616         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2617
2618         return 0;
2619 }
2620
2621 static int niu_init_link(struct niu *np)
2622 {
2623         struct niu_parent *parent = np->parent;
2624         int err, ignore;
2625
2626         if (parent->plat_type == PLAT_TYPE_NIU) {
2627                 err = niu_xcvr_init(np);
2628                 if (err)
2629                         return err;
2630                 msleep(200);
2631         }
2632         err = niu_serdes_init(np);
2633         if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2634                 return err;
2635         msleep(200);
2636         err = niu_xcvr_init(np);
2637         if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2638                 niu_link_status(np, &ignore);
2639         return 0;
2640 }
2641
2642 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2643 {
2644         u16 reg0 = addr[4] << 8 | addr[5];
2645         u16 reg1 = addr[2] << 8 | addr[3];
2646         u16 reg2 = addr[0] << 8 | addr[1];
2647
2648         if (np->flags & NIU_FLAGS_XMAC) {
2649                 nw64_mac(XMAC_ADDR0, reg0);
2650                 nw64_mac(XMAC_ADDR1, reg1);
2651                 nw64_mac(XMAC_ADDR2, reg2);
2652         } else {
2653                 nw64_mac(BMAC_ADDR0, reg0);
2654                 nw64_mac(BMAC_ADDR1, reg1);
2655                 nw64_mac(BMAC_ADDR2, reg2);
2656         }
2657 }
2658
2659 static int niu_num_alt_addr(struct niu *np)
2660 {
2661         if (np->flags & NIU_FLAGS_XMAC)
2662                 return XMAC_NUM_ALT_ADDR;
2663         else
2664                 return BMAC_NUM_ALT_ADDR;
2665 }
2666
2667 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2668 {
2669         u16 reg0 = addr[4] << 8 | addr[5];
2670         u16 reg1 = addr[2] << 8 | addr[3];
2671         u16 reg2 = addr[0] << 8 | addr[1];
2672
2673         if (index >= niu_num_alt_addr(np))
2674                 return -EINVAL;
2675
2676         if (np->flags & NIU_FLAGS_XMAC) {
2677                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2678                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2679                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2680         } else {
2681                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2682                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2683                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2684         }
2685
2686         return 0;
2687 }
2688
2689 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2690 {
2691         unsigned long reg;
2692         u64 val, mask;
2693
2694         if (index >= niu_num_alt_addr(np))
2695                 return -EINVAL;
2696
2697         if (np->flags & NIU_FLAGS_XMAC) {
2698                 reg = XMAC_ADDR_CMPEN;
2699                 mask = 1 << index;
2700         } else {
2701                 reg = BMAC_ADDR_CMPEN;
2702                 mask = 1 << (index + 1);
2703         }
2704
2705         val = nr64_mac(reg);
2706         if (on)
2707                 val |= mask;
2708         else
2709                 val &= ~mask;
2710         nw64_mac(reg, val);
2711
2712         return 0;
2713 }
2714
2715 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2716                                    int num, int mac_pref)
2717 {
2718         u64 val = nr64_mac(reg);
2719         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2720         val |= num;
2721         if (mac_pref)
2722                 val |= HOST_INFO_MPR;
2723         nw64_mac(reg, val);
2724 }
2725
2726 static int __set_rdc_table_num(struct niu *np,
2727                                int xmac_index, int bmac_index,
2728                                int rdc_table_num, int mac_pref)
2729 {
2730         unsigned long reg;
2731
2732         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2733                 return -EINVAL;
2734         if (np->flags & NIU_FLAGS_XMAC)
2735                 reg = XMAC_HOST_INFO(xmac_index);
2736         else
2737                 reg = BMAC_HOST_INFO(bmac_index);
2738         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2739         return 0;
2740 }
2741
2742 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2743                                          int mac_pref)
2744 {
2745         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2746 }
2747
2748 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2749                                            int mac_pref)
2750 {
2751         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2752 }
2753
2754 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2755                                      int table_num, int mac_pref)
2756 {
2757         if (idx >= niu_num_alt_addr(np))
2758                 return -EINVAL;
2759         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2760 }
2761
2762 static u64 vlan_entry_set_parity(u64 reg_val)
2763 {
2764         u64 port01_mask;
2765         u64 port23_mask;
2766
2767         port01_mask = 0x00ff;
2768         port23_mask = 0xff00;
2769
2770         if (hweight64(reg_val & port01_mask) & 1)
2771                 reg_val |= ENET_VLAN_TBL_PARITY0;
2772         else
2773                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2774
2775         if (hweight64(reg_val & port23_mask) & 1)
2776                 reg_val |= ENET_VLAN_TBL_PARITY1;
2777         else
2778                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2779
2780         return reg_val;
2781 }
2782
2783 static void vlan_tbl_write(struct niu *np, unsigned long index,
2784                            int port, int vpr, int rdc_table)
2785 {
2786         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2787
2788         reg_val &= ~((ENET_VLAN_TBL_VPR |
2789                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2790                      ENET_VLAN_TBL_SHIFT(port));
2791         if (vpr)
2792                 reg_val |= (ENET_VLAN_TBL_VPR <<
2793                             ENET_VLAN_TBL_SHIFT(port));
2794         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2795
2796         reg_val = vlan_entry_set_parity(reg_val);
2797
2798         nw64(ENET_VLAN_TBL(index), reg_val);
2799 }
2800
2801 static void vlan_tbl_clear(struct niu *np)
2802 {
2803         int i;
2804
2805         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2806                 nw64(ENET_VLAN_TBL(i), 0);
2807 }
2808
2809 static int tcam_wait_bit(struct niu *np, u64 bit)
2810 {
2811         int limit = 1000;
2812
2813         while (--limit > 0) {
2814                 if (nr64(TCAM_CTL) & bit)
2815                         break;
2816                 udelay(1);
2817         }
2818         if (limit <= 0)
2819                 return -ENODEV;
2820
2821         return 0;
2822 }
2823
2824 static int tcam_flush(struct niu *np, int index)
2825 {
2826         nw64(TCAM_KEY_0, 0x00);
2827         nw64(TCAM_KEY_MASK_0, 0xff);
2828         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2829
2830         return tcam_wait_bit(np, TCAM_CTL_STAT);
2831 }
2832
2833 #if 0
2834 static int tcam_read(struct niu *np, int index,
2835                      u64 *key, u64 *mask)
2836 {
2837         int err;
2838
2839         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2840         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2841         if (!err) {
2842                 key[0] = nr64(TCAM_KEY_0);
2843                 key[1] = nr64(TCAM_KEY_1);
2844                 key[2] = nr64(TCAM_KEY_2);
2845                 key[3] = nr64(TCAM_KEY_3);
2846                 mask[0] = nr64(TCAM_KEY_MASK_0);
2847                 mask[1] = nr64(TCAM_KEY_MASK_1);
2848                 mask[2] = nr64(TCAM_KEY_MASK_2);
2849                 mask[3] = nr64(TCAM_KEY_MASK_3);
2850         }
2851         return err;
2852 }
2853 #endif
2854
2855 static int tcam_write(struct niu *np, int index,
2856                       u64 *key, u64 *mask)
2857 {
2858         nw64(TCAM_KEY_0, key[0]);
2859         nw64(TCAM_KEY_1, key[1]);
2860         nw64(TCAM_KEY_2, key[2]);
2861         nw64(TCAM_KEY_3, key[3]);
2862         nw64(TCAM_KEY_MASK_0, mask[0]);
2863         nw64(TCAM_KEY_MASK_1, mask[1]);
2864         nw64(TCAM_KEY_MASK_2, mask[2]);
2865         nw64(TCAM_KEY_MASK_3, mask[3]);
2866         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2867
2868         return tcam_wait_bit(np, TCAM_CTL_STAT);
2869 }
2870
2871 #if 0
2872 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2873 {
2874         int err;
2875
2876         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2877         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2878         if (!err)
2879                 *data = nr64(TCAM_KEY_1);
2880
2881         return err;
2882 }
2883 #endif
2884
2885 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2886 {
2887         nw64(TCAM_KEY_1, assoc_data);
2888         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2889
2890         return tcam_wait_bit(np, TCAM_CTL_STAT);
2891 }
2892
2893 static void tcam_enable(struct niu *np, int on)
2894 {
2895         u64 val = nr64(FFLP_CFG_1);
2896
2897         if (on)
2898                 val &= ~FFLP_CFG_1_TCAM_DIS;
2899         else
2900                 val |= FFLP_CFG_1_TCAM_DIS;
2901         nw64(FFLP_CFG_1, val);
2902 }
2903
2904 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2905 {
2906         u64 val = nr64(FFLP_CFG_1);
2907
2908         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2909                  FFLP_CFG_1_CAMLAT |
2910                  FFLP_CFG_1_CAMRATIO);
2911         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2912         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2913         nw64(FFLP_CFG_1, val);
2914
2915         val = nr64(FFLP_CFG_1);
2916         val |= FFLP_CFG_1_FFLPINITDONE;
2917         nw64(FFLP_CFG_1, val);
2918 }
2919
2920 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2921                                       int on)
2922 {
2923         unsigned long reg;
2924         u64 val;
2925
2926         if (class < CLASS_CODE_ETHERTYPE1 ||
2927             class > CLASS_CODE_ETHERTYPE2)
2928                 return -EINVAL;
2929
2930         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2931         val = nr64(reg);
2932         if (on)
2933                 val |= L2_CLS_VLD;
2934         else
2935                 val &= ~L2_CLS_VLD;
2936         nw64(reg, val);
2937
2938         return 0;
2939 }
2940
2941 #if 0
2942 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2943                                    u64 ether_type)
2944 {
2945         unsigned long reg;
2946         u64 val;
2947
2948         if (class < CLASS_CODE_ETHERTYPE1 ||
2949             class > CLASS_CODE_ETHERTYPE2 ||
2950             (ether_type & ~(u64)0xffff) != 0)
2951                 return -EINVAL;
2952
2953         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2954         val = nr64(reg);
2955         val &= ~L2_CLS_ETYPE;
2956         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2957         nw64(reg, val);
2958
2959         return 0;
2960 }
2961 #endif
2962
2963 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2964                                      int on)
2965 {
2966         unsigned long reg;
2967         u64 val;
2968
2969         if (class < CLASS_CODE_USER_PROG1 ||
2970             class > CLASS_CODE_USER_PROG4)
2971                 return -EINVAL;
2972
2973         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2974         val = nr64(reg);
2975         if (on)
2976                 val |= L3_CLS_VALID;
2977         else
2978                 val &= ~L3_CLS_VALID;
2979         nw64(reg, val);
2980
2981         return 0;
2982 }
2983
2984 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2985                                   int ipv6, u64 protocol_id,
2986                                   u64 tos_mask, u64 tos_val)
2987 {
2988         unsigned long reg;
2989         u64 val;
2990
2991         if (class < CLASS_CODE_USER_PROG1 ||
2992             class > CLASS_CODE_USER_PROG4 ||
2993             (protocol_id & ~(u64)0xff) != 0 ||
2994             (tos_mask & ~(u64)0xff) != 0 ||
2995             (tos_val & ~(u64)0xff) != 0)
2996                 return -EINVAL;
2997
2998         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2999         val = nr64(reg);
3000         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
3001                  L3_CLS_TOSMASK | L3_CLS_TOS);
3002         if (ipv6)
3003                 val |= L3_CLS_IPVER;
3004         val |= (protocol_id << L3_CLS_PID_SHIFT);
3005         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3006         val |= (tos_val << L3_CLS_TOS_SHIFT);
3007         nw64(reg, val);
3008
3009         return 0;
3010 }
3011
3012 static int tcam_early_init(struct niu *np)
3013 {
3014         unsigned long i;
3015         int err;
3016
3017         tcam_enable(np, 0);
3018         tcam_set_lat_and_ratio(np,
3019                                DEFAULT_TCAM_LATENCY,
3020                                DEFAULT_TCAM_ACCESS_RATIO);
3021         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3022                 err = tcam_user_eth_class_enable(np, i, 0);
3023                 if (err)
3024                         return err;
3025         }
3026         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3027                 err = tcam_user_ip_class_enable(np, i, 0);
3028                 if (err)
3029                         return err;
3030         }
3031
3032         return 0;
3033 }
3034
3035 static int tcam_flush_all(struct niu *np)
3036 {
3037         unsigned long i;
3038
3039         for (i = 0; i < np->parent->tcam_num_entries; i++) {
3040                 int err = tcam_flush(np, i);
3041                 if (err)
3042                         return err;
3043         }
3044         return 0;
3045 }
3046
3047 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3048 {
3049         return ((u64)index | (num_entries == 1 ?
3050                               HASH_TBL_ADDR_AUTOINC : 0));
3051 }
3052
3053 #if 0
3054 static int hash_read(struct niu *np, unsigned long partition,
3055                      unsigned long index, unsigned long num_entries,
3056                      u64 *data)
3057 {
3058         u64 val = hash_addr_regval(index, num_entries);
3059         unsigned long i;
3060
3061         if (partition >= FCRAM_NUM_PARTITIONS ||
3062             index + num_entries > FCRAM_SIZE)
3063                 return -EINVAL;
3064
3065         nw64(HASH_TBL_ADDR(partition), val);
3066         for (i = 0; i < num_entries; i++)
3067                 data[i] = nr64(HASH_TBL_DATA(partition));
3068
3069         return 0;
3070 }
3071 #endif
3072
3073 static int hash_write(struct niu *np, unsigned long partition,
3074                       unsigned long index, unsigned long num_entries,
3075                       u64 *data)
3076 {
3077         u64 val = hash_addr_regval(index, num_entries);
3078         unsigned long i;
3079
3080         if (partition >= FCRAM_NUM_PARTITIONS ||
3081             index + (num_entries * 8) > FCRAM_SIZE)
3082                 return -EINVAL;
3083
3084         nw64(HASH_TBL_ADDR(partition), val);
3085         for (i = 0; i < num_entries; i++)
3086                 nw64(HASH_TBL_DATA(partition), data[i]);
3087
3088         return 0;
3089 }
3090
3091 static void fflp_reset(struct niu *np)
3092 {
3093         u64 val;
3094
3095         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3096         udelay(10);
3097         nw64(FFLP_CFG_1, 0);
3098
3099         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3100         nw64(FFLP_CFG_1, val);
3101 }
3102
3103 static void fflp_set_timings(struct niu *np)
3104 {
3105         u64 val = nr64(FFLP_CFG_1);
3106
3107         val &= ~FFLP_CFG_1_FFLPINITDONE;
3108         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3109         nw64(FFLP_CFG_1, val);
3110
3111         val = nr64(FFLP_CFG_1);
3112         val |= FFLP_CFG_1_FFLPINITDONE;
3113         nw64(FFLP_CFG_1, val);
3114
3115         val = nr64(FCRAM_REF_TMR);
3116         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3117         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3118         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3119         nw64(FCRAM_REF_TMR, val);
3120 }
3121
3122 static int fflp_set_partition(struct niu *np, u64 partition,
3123                               u64 mask, u64 base, int enable)
3124 {
3125         unsigned long reg;
3126         u64 val;
3127
3128         if (partition >= FCRAM_NUM_PARTITIONS ||
3129             (mask & ~(u64)0x1f) != 0 ||
3130             (base & ~(u64)0x1f) != 0)
3131                 return -EINVAL;
3132
3133         reg = FLW_PRT_SEL(partition);
3134
3135         val = nr64(reg);
3136         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3137         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3138         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3139         if (enable)
3140                 val |= FLW_PRT_SEL_EXT;
3141         nw64(reg, val);
3142
3143         return 0;
3144 }
3145
3146 static int fflp_disable_all_partitions(struct niu *np)
3147 {
3148         unsigned long i;
3149
3150         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3151                 int err = fflp_set_partition(np, 0, 0, 0, 0);
3152                 if (err)
3153                         return err;
3154         }
3155         return 0;
3156 }
3157
3158 static void fflp_llcsnap_enable(struct niu *np, int on)
3159 {
3160         u64 val = nr64(FFLP_CFG_1);
3161
3162         if (on)
3163                 val |= FFLP_CFG_1_LLCSNAP;
3164         else
3165                 val &= ~FFLP_CFG_1_LLCSNAP;
3166         nw64(FFLP_CFG_1, val);
3167 }
3168
3169 static void fflp_errors_enable(struct niu *np, int on)
3170 {
3171         u64 val = nr64(FFLP_CFG_1);
3172
3173         if (on)
3174                 val &= ~FFLP_CFG_1_ERRORDIS;
3175         else
3176                 val |= FFLP_CFG_1_ERRORDIS;
3177         nw64(FFLP_CFG_1, val);
3178 }
3179
3180 static int fflp_hash_clear(struct niu *np)
3181 {
3182         struct fcram_hash_ipv4 ent;
3183         unsigned long i;
3184
3185         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
3186         memset(&ent, 0, sizeof(ent));
3187         ent.header = HASH_HEADER_EXT;
3188
3189         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3190                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3191                 if (err)
3192                         return err;
3193         }
3194         return 0;
3195 }
3196
3197 static int fflp_early_init(struct niu *np)
3198 {
3199         struct niu_parent *parent;
3200         unsigned long flags;
3201         int err;
3202
3203         niu_lock_parent(np, flags);
3204
3205         parent = np->parent;
3206         err = 0;
3207         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3208                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3209                         fflp_reset(np);
3210                         fflp_set_timings(np);
3211                         err = fflp_disable_all_partitions(np);
3212                         if (err) {
3213                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3214                                              "fflp_disable_all_partitions failed, err=%d\n",
3215                                              err);
3216                                 goto out;
3217                         }
3218                 }
3219
3220                 err = tcam_early_init(np);
3221                 if (err) {
3222                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3223                                      "tcam_early_init failed, err=%d\n", err);
3224                         goto out;
3225                 }
3226                 fflp_llcsnap_enable(np, 1);
3227                 fflp_errors_enable(np, 0);
3228                 nw64(H1POLY, 0);
3229                 nw64(H2POLY, 0);
3230
3231                 err = tcam_flush_all(np);
3232                 if (err) {
3233                         netif_printk(np, probe, KERN_DEBUG, np->dev,
3234                                      "tcam_flush_all failed, err=%d\n", err);
3235                         goto out;
3236                 }
3237                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3238                         err = fflp_hash_clear(np);
3239                         if (err) {
3240                                 netif_printk(np, probe, KERN_DEBUG, np->dev,
3241                                              "fflp_hash_clear failed, err=%d\n",
3242                                              err);
3243                                 goto out;
3244                         }
3245                 }
3246
3247                 vlan_tbl_clear(np);
3248
3249                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3250         }
3251 out:
3252         niu_unlock_parent(np, flags);
3253         return err;
3254 }
3255
3256 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3257 {
3258         if (class_code < CLASS_CODE_USER_PROG1 ||
3259             class_code > CLASS_CODE_SCTP_IPV6)
3260                 return -EINVAL;
3261
3262         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3263         return 0;
3264 }
3265
3266 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3267 {
3268         if (class_code < CLASS_CODE_USER_PROG1 ||
3269             class_code > CLASS_CODE_SCTP_IPV6)
3270                 return -EINVAL;
3271
3272         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3273         return 0;
3274 }
3275
3276 /* Entries for the ports are interleaved in the TCAM */
3277 static u16 tcam_get_index(struct niu *np, u16 idx)
3278 {
3279         /* One entry reserved for IP fragment rule */
3280         if (idx >= (np->clas.tcam_sz - 1))
3281                 idx = 0;
3282         return (np->clas.tcam_top + ((idx+1) * np->parent->num_ports));
3283 }
3284
3285 static u16 tcam_get_size(struct niu *np)
3286 {
3287         /* One entry reserved for IP fragment rule */
3288         return np->clas.tcam_sz - 1;
3289 }
3290
3291 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3292 {
3293         /* One entry reserved for IP fragment rule */
3294         return np->clas.tcam_valid_entries - 1;
3295 }
3296
3297 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3298                               u32 offset, u32 size)
3299 {
3300         int i = skb_shinfo(skb)->nr_frags;
3301         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3302
3303         frag->page = page;
3304         frag->page_offset = offset;
3305         frag->size = size;
3306
3307         skb->len += size;
3308         skb->data_len += size;
3309         skb->truesize += size;
3310
3311         skb_shinfo(skb)->nr_frags = i + 1;
3312 }
3313
3314 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3315 {
3316         a >>= PAGE_SHIFT;
3317         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3318
3319         return (a & (MAX_RBR_RING_SIZE - 1));
3320 }
3321
3322 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3323                                     struct page ***link)
3324 {
3325         unsigned int h = niu_hash_rxaddr(rp, addr);
3326         struct page *p, **pp;
3327
3328         addr &= PAGE_MASK;
3329         pp = &rp->rxhash[h];
3330         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3331                 if (p->index == addr) {
3332                         *link = pp;
3333                         break;
3334                 }
3335         }
3336
3337         return p;
3338 }
3339
3340 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3341 {
3342         unsigned int h = niu_hash_rxaddr(rp, base);
3343
3344         page->index = base;
3345         page->mapping = (struct address_space *) rp->rxhash[h];
3346         rp->rxhash[h] = page;
3347 }
3348
3349 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3350                             gfp_t mask, int start_index)
3351 {
3352         struct page *page;
3353         u64 addr;
3354         int i;
3355
3356         page = alloc_page(mask);
3357         if (!page)
3358                 return -ENOMEM;
3359
3360         addr = np->ops->map_page(np->device, page, 0,
3361                                  PAGE_SIZE, DMA_FROM_DEVICE);
3362
3363         niu_hash_page(rp, page, addr);
3364         if (rp->rbr_blocks_per_page > 1)
3365                 atomic_add(rp->rbr_blocks_per_page - 1,
3366                            &compound_head(page)->_count);
3367
3368         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3369                 __le32 *rbr = &rp->rbr[start_index + i];
3370
3371                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3372                 addr += rp->rbr_block_size;
3373         }
3374
3375         return 0;
3376 }
3377
3378 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3379 {
3380         int index = rp->rbr_index;
3381
3382         rp->rbr_pending++;
3383         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3384                 int err = niu_rbr_add_page(np, rp, mask, index);
3385
3386                 if (unlikely(err)) {
3387                         rp->rbr_pending--;
3388                         return;
3389                 }
3390
3391                 rp->rbr_index += rp->rbr_blocks_per_page;
3392                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3393                 if (rp->rbr_index == rp->rbr_table_size)
3394                         rp->rbr_index = 0;
3395
3396                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3397                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3398                         rp->rbr_pending = 0;
3399                 }
3400         }
3401 }
3402
3403 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3404 {
3405         unsigned int index = rp->rcr_index;
3406         int num_rcr = 0;
3407
3408         rp->rx_dropped++;
3409         while (1) {
3410                 struct page *page, **link;
3411                 u64 addr, val;
3412                 u32 rcr_size;
3413
3414                 num_rcr++;
3415
3416                 val = le64_to_cpup(&rp->rcr[index]);
3417                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3418                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3419                 page = niu_find_rxpage(rp, addr, &link);
3420
3421                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3422                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3423                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3424                         *link = (struct page *) page->mapping;
3425                         np->ops->unmap_page(np->device, page->index,
3426                                             PAGE_SIZE, DMA_FROM_DEVICE);
3427                         page->index = 0;
3428                         page->mapping = NULL;
3429                         __free_page(page);
3430                         rp->rbr_refill_pending++;
3431                 }
3432
3433                 index = NEXT_RCR(rp, index);
3434                 if (!(val & RCR_ENTRY_MULTI))
3435                         break;
3436
3437         }
3438         rp->rcr_index = index;
3439
3440         return num_rcr;
3441 }
3442
3443 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3444                               struct rx_ring_info *rp)
3445 {
3446         unsigned int index = rp->rcr_index;
3447         struct sk_buff *skb;
3448         int len, num_rcr;
3449
3450         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3451         if (unlikely(!skb))
3452                 return niu_rx_pkt_ignore(np, rp);
3453
3454         num_rcr = 0;
3455         while (1) {
3456                 struct page *page, **link;
3457                 u32 rcr_size, append_size;
3458                 u64 addr, val, off;
3459
3460                 num_rcr++;
3461
3462                 val = le64_to_cpup(&rp->rcr[index]);
3463
3464                 len = (val & RCR_ENTRY_L2_LEN) >>
3465                         RCR_ENTRY_L2_LEN_SHIFT;
3466                 len -= ETH_FCS_LEN;
3467
3468                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3469                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3470                 page = niu_find_rxpage(rp, addr, &link);
3471
3472                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3473                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3474
3475                 off = addr & ~PAGE_MASK;
3476                 append_size = rcr_size;
3477                 if (num_rcr == 1) {
3478                         int ptype;
3479
3480                         off += 2;
3481                         append_size -= 2;
3482
3483                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3484                         if ((ptype == RCR_PKT_TYPE_TCP ||
3485                              ptype == RCR_PKT_TYPE_UDP) &&
3486                             !(val & (RCR_ENTRY_NOPORT |
3487                                      RCR_ENTRY_ERROR)))
3488                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3489                         else
3490                                 skb->ip_summed = CHECKSUM_NONE;
3491                 }
3492                 if (!(val & RCR_ENTRY_MULTI))
3493                         append_size = len - skb->len;
3494
3495                 niu_rx_skb_append(skb, page, off, append_size);
3496                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3497                         *link = (struct page *) page->mapping;
3498                         np->ops->unmap_page(np->device, page->index,
3499                                             PAGE_SIZE, DMA_FROM_DEVICE);
3500                         page->index = 0;
3501                         page->mapping = NULL;
3502                         rp->rbr_refill_pending++;
3503                 } else
3504                         get_page(page);
3505
3506                 index = NEXT_RCR(rp, index);
3507                 if (!(val & RCR_ENTRY_MULTI))
3508                         break;
3509
3510         }
3511         rp->rcr_index = index;
3512
3513         skb_reserve(skb, NET_IP_ALIGN);
3514         __pskb_pull_tail(skb, min(len, VLAN_ETH_HLEN));
3515
3516         rp->rx_packets++;
3517         rp->rx_bytes += skb->len;
3518
3519         skb->protocol = eth_type_trans(skb, np->dev);
3520         skb_record_rx_queue(skb, rp->rx_channel);
3521         napi_gro_receive(napi, skb);
3522
3523         return num_rcr;
3524 }
3525
3526 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3527 {
3528         int blocks_per_page = rp->rbr_blocks_per_page;
3529         int err, index = rp->rbr_index;
3530
3531         err = 0;
3532         while (index < (rp->rbr_table_size - blocks_per_page)) {
3533                 err = niu_rbr_add_page(np, rp, mask, index);
3534                 if (err)
3535                         break;
3536
3537                 index += blocks_per_page;
3538         }
3539
3540         rp->rbr_index = index;
3541         return err;
3542 }
3543
3544 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3545 {
3546         int i;
3547
3548         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3549                 struct page *page;
3550
3551                 page = rp->rxhash[i];
3552                 while (page) {
3553                         struct page *next = (struct page *) page->mapping;
3554                         u64 base = page->index;
3555
3556                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3557                                             DMA_FROM_DEVICE);
3558                         page->index = 0;
3559                         page->mapping = NULL;
3560
3561                         __free_page(page);
3562
3563                         page = next;
3564                 }
3565         }
3566
3567         for (i = 0; i < rp->rbr_table_size; i++)
3568                 rp->rbr[i] = cpu_to_le32(0);
3569         rp->rbr_index = 0;
3570 }
3571
3572 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3573 {
3574         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3575         struct sk_buff *skb = tb->skb;
3576         struct tx_pkt_hdr *tp;
3577         u64 tx_flags;
3578         int i, len;
3579
3580         tp = (struct tx_pkt_hdr *) skb->data;
3581         tx_flags = le64_to_cpup(&tp->flags);
3582
3583         rp->tx_packets++;
3584         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3585                          ((tx_flags & TXHDR_PAD) / 2));
3586
3587         len = skb_headlen(skb);
3588         np->ops->unmap_single(np->device, tb->mapping,
3589                               len, DMA_TO_DEVICE);
3590
3591         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3592                 rp->mark_pending--;
3593
3594         tb->skb = NULL;
3595         do {
3596                 idx = NEXT_TX(rp, idx);
3597                 len -= MAX_TX_DESC_LEN;
3598         } while (len > 0);
3599
3600         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3601                 tb = &rp->tx_buffs[idx];
3602                 BUG_ON(tb->skb != NULL);
3603                 np->ops->unmap_page(np->device, tb->mapping,
3604                                     skb_shinfo(skb)->frags[i].size,
3605                                     DMA_TO_DEVICE);
3606                 idx = NEXT_TX(rp, idx);
3607         }
3608
3609         dev_kfree_skb(skb);
3610
3611         return idx;
3612 }
3613
3614 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3615
3616 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3617 {
3618         struct netdev_queue *txq;
3619         u16 pkt_cnt, tmp;
3620         int cons, index;
3621         u64 cs;
3622
3623         index = (rp - np->tx_rings);
3624         txq = netdev_get_tx_queue(np->dev, index);
3625
3626         cs = rp->tx_cs;
3627         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3628                 goto out;
3629
3630         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3631         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3632                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3633
3634         rp->last_pkt_cnt = tmp;
3635
3636         cons = rp->cons;
3637
3638         netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3639                      "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3640
3641         while (pkt_cnt--)
3642                 cons = release_tx_packet(np, rp, cons);
3643
3644         rp->cons = cons;
3645         smp_mb();
3646
3647 out:
3648         if (unlikely(netif_tx_queue_stopped(txq) &&
3649                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3650                 __netif_tx_lock(txq, smp_processor_id());
3651                 if (netif_tx_queue_stopped(txq) &&
3652                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3653                         netif_tx_wake_queue(txq);
3654                 __netif_tx_unlock(txq);
3655         }
3656 }
3657
3658 static inline void niu_sync_rx_discard_stats(struct niu *np,
3659                                              struct rx_ring_info *rp,
3660                                              const int limit)
3661 {
3662         /* This elaborate scheme is needed for reading the RX discard
3663          * counters, as they are only 16-bit and can overflow quickly,
3664          * and because the overflow indication bit is not usable as
3665          * the counter value does not wrap, but remains at max value
3666          * 0xFFFF.
3667          *
3668          * In theory and in practice counters can be lost in between
3669          * reading nr64() and clearing the counter nw64().  For this
3670          * reason, the number of counter clearings nw64() is
3671          * limited/reduced though the limit parameter.
3672          */
3673         int rx_channel = rp->rx_channel;
3674         u32 misc, wred;
3675
3676         /* RXMISC (Receive Miscellaneous Discard Count), covers the
3677          * following discard events: IPP (Input Port Process),
3678          * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3679          * Block Ring) prefetch buffer is empty.
3680          */
3681         misc = nr64(RXMISC(rx_channel));
3682         if (unlikely((misc & RXMISC_COUNT) > limit)) {
3683                 nw64(RXMISC(rx_channel), 0);
3684                 rp->rx_errors += misc & RXMISC_COUNT;
3685
3686                 if (unlikely(misc & RXMISC_OFLOW))
3687                         dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3688                                 rx_channel);
3689
3690                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3691                              "rx-%d: MISC drop=%u over=%u\n",
3692                              rx_channel, misc, misc-limit);
3693         }
3694
3695         /* WRED (Weighted Random Early Discard) by hardware */
3696         wred = nr64(RED_DIS_CNT(rx_channel));
3697         if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3698                 nw64(RED_DIS_CNT(rx_channel), 0);
3699                 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3700
3701                 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3702                         dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3703
3704                 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3705                              "rx-%d: WRED drop=%u over=%u\n",
3706                              rx_channel, wred, wred-limit);
3707         }
3708 }
3709
3710 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3711                        struct rx_ring_info *rp, int budget)
3712 {
3713         int qlen, rcr_done = 0, work_done = 0;
3714         struct rxdma_mailbox *mbox = rp->mbox;
3715         u64 stat;
3716
3717 #if 1
3718         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3719         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3720 #else
3721         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3722         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3723 #endif
3724         mbox->rx_dma_ctl_stat = 0;
3725         mbox->rcrstat_a = 0;
3726
3727         netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3728                      "%s(chan[%d]), stat[%llx] qlen=%d\n",
3729                      __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3730
3731         rcr_done = work_done = 0;
3732         qlen = min(qlen, budget);
3733         while (work_done < qlen) {
3734                 rcr_done += niu_process_rx_pkt(napi, np, rp);
3735                 work_done++;
3736         }
3737
3738         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3739                 unsigned int i;
3740
3741                 for (i = 0; i < rp->rbr_refill_pending; i++)
3742                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3743                 rp->rbr_refill_pending = 0;
3744         }
3745
3746         stat = (RX_DMA_CTL_STAT_MEX |
3747                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3748                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3749
3750         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3751
3752         /* Only sync discards stats when qlen indicate potential for drops */
3753         if (qlen > 10)
3754                 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3755
3756         return work_done;
3757 }
3758
3759 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3760 {
3761         u64 v0 = lp->v0;
3762         u32 tx_vec = (v0 >> 32);
3763         u32 rx_vec = (v0 & 0xffffffff);
3764         int i, work_done = 0;
3765
3766         netif_printk(np, intr, KERN_DEBUG, np->dev,
3767                      "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3768
3769         for (i = 0; i < np->num_tx_rings; i++) {
3770                 struct tx_ring_info *rp = &np->tx_rings[i];
3771                 if (tx_vec & (1 << rp->tx_channel))
3772                         niu_tx_work(np, rp);
3773                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3774         }
3775
3776         for (i = 0; i < np->num_rx_rings; i++) {
3777                 struct rx_ring_info *rp = &np->rx_rings[i];
3778
3779                 if (rx_vec & (1 << rp->rx_channel)) {
3780                         int this_work_done;
3781
3782                         this_work_done = niu_rx_work(&lp->napi, np, rp,
3783                                                      budget);
3784
3785                         budget -= this_work_done;
3786                         work_done += this_work_done;
3787                 }
3788                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3789         }
3790
3791         return work_done;
3792 }
3793
3794 static int niu_poll(struct napi_struct *napi, int budget)
3795 {
3796         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3797         struct niu *np = lp->np;
3798         int work_done;
3799
3800         work_done = niu_poll_core(np, lp, budget);
3801
3802         if (work_done < budget) {
3803                 napi_complete(napi);
3804                 niu_ldg_rearm(np, lp, 1);
3805         }
3806         return work_done;
3807 }
3808
3809 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3810                                   u64 stat)
3811 {
3812         netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3813
3814         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3815                 pr_cont("RBR_TMOUT ");
3816         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3817                 pr_cont("RSP_CNT ");
3818         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3819                 pr_cont("BYTE_EN_BUS ");
3820         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3821                 pr_cont("RSP_DAT ");
3822         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3823                 pr_cont("RCR_ACK ");
3824         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3825                 pr_cont("RCR_SHA_PAR ");
3826         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3827                 pr_cont("RBR_PRE_PAR ");
3828         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3829                 pr_cont("CONFIG ");
3830         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3831                 pr_cont("RCRINCON ");
3832         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3833                 pr_cont("RCRFULL ");
3834         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3835                 pr_cont("RBRFULL ");
3836         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3837                 pr_cont("RBRLOGPAGE ");
3838         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3839                 pr_cont("CFIGLOGPAGE ");
3840         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3841                 pr_cont("DC_FIDO ");
3842
3843         pr_cont(")\n");
3844 }
3845
3846 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3847 {
3848         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3849         int err = 0;
3850
3851
3852         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3853                     RX_DMA_CTL_STAT_PORT_FATAL))
3854                 err = -EINVAL;
3855
3856         if (err) {
3857                 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3858                            rp->rx_channel,
3859                            (unsigned long long) stat);
3860
3861                 niu_log_rxchan_errors(np, rp, stat);
3862         }
3863
3864         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3865              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3866
3867         return err;
3868 }
3869
3870 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3871                                   u64 cs)
3872 {
3873         netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3874
3875         if (cs & TX_CS_MBOX_ERR)
3876                 pr_cont("MBOX ");
3877         if (cs & TX_CS_PKT_SIZE_ERR)
3878                 pr_cont("PKT_SIZE ");
3879         if (cs & TX_CS_TX_RING_OFLOW)
3880                 pr_cont("TX_RING_OFLOW ");
3881         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3882                 pr_cont("PREF_BUF_PAR ");
3883         if (cs & TX_CS_NACK_PREF)
3884                 pr_cont("NACK_PREF ");
3885         if (cs & TX_CS_NACK_PKT_RD)
3886                 pr_cont("NACK_PKT_RD ");
3887         if (cs & TX_CS_CONF_PART_ERR)
3888                 pr_cont("CONF_PART ");
3889         if (cs & TX_CS_PKT_PRT_ERR)
3890                 pr_cont("PKT_PTR ");
3891
3892         pr_cont(")\n");
3893 }
3894
3895 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3896 {
3897         u64 cs, logh, logl;
3898
3899         cs = nr64(TX_CS(rp->tx_channel));
3900         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3901         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3902
3903         netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3904                    rp->tx_channel,
3905                    (unsigned long long)cs,
3906                    (unsigned long long)logh,
3907                    (unsigned long long)logl);
3908
3909         niu_log_txchan_errors(np, rp, cs);
3910
3911         return -ENODEV;
3912 }
3913
3914 static int niu_mif_interrupt(struct niu *np)
3915 {
3916         u64 mif_status = nr64(MIF_STATUS);
3917         int phy_mdint = 0;
3918
3919         if (np->flags & NIU_FLAGS_XMAC) {
3920                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3921
3922                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3923                         phy_mdint = 1;
3924         }
3925
3926         netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3927                    (unsigned long long)mif_status, phy_mdint);
3928
3929         return -ENODEV;
3930 }
3931
3932 static void niu_xmac_interrupt(struct niu *np)
3933 {
3934         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3935         u64 val;
3936
3937         val = nr64_mac(XTXMAC_STATUS);
3938         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3939                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3940         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3941                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3942         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3943                 mp->tx_fifo_errors++;
3944         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3945                 mp->tx_overflow_errors++;
3946         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3947                 mp->tx_max_pkt_size_errors++;
3948         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3949                 mp->tx_underflow_errors++;
3950
3951         val = nr64_mac(XRXMAC_STATUS);
3952         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3953                 mp->rx_local_faults++;
3954         if (val & XRXMAC_STATUS_RFLT_DET)
3955                 mp->rx_remote_faults++;
3956         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3957                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3958         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3959                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3960         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3961                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3962         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3963                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3964         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3965                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3966         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3967                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3968         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3969                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3970         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3971                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3972         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3973                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3974         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3975                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3976         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3977                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3978         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3979                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3980         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3981                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3982         if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3983                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3984         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3985                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3986         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3987                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3988         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3989                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3990         if (val & XRXMAC_STATUS_RXUFLOW)
3991                 mp->rx_underflows++;
3992         if (val & XRXMAC_STATUS_RXOFLOW)
3993                 mp->rx_overflows++;
3994
3995         val = nr64_mac(XMAC_FC_STAT);
3996         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3997                 mp->pause_off_state++;
3998         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3999                 mp->pause_on_state++;
4000         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4001                 mp->pause_received++;
4002 }
4003
4004 static void niu_bmac_interrupt(struct niu *np)
4005 {
4006         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4007         u64 val;
4008
4009         val = nr64_mac(BTXMAC_STATUS);
4010         if (val & BTXMAC_STATUS_UNDERRUN)
4011                 mp->tx_underflow_errors++;
4012         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4013                 mp->tx_max_pkt_size_errors++;
4014         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4015                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4016         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4017                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4018
4019         val = nr64_mac(BRXMAC_STATUS);
4020         if (val & BRXMAC_STATUS_OVERFLOW)
4021                 mp->rx_overflows++;
4022         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4023                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4024         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4025                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4026         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4027                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4028         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4029                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4030
4031         val = nr64_mac(BMAC_CTRL_STATUS);
4032         if (val & BMAC_CTRL_STATUS_NOPAUSE)
4033                 mp->pause_off_state++;
4034         if (val & BMAC_CTRL_STATUS_PAUSE)
4035                 mp->pause_on_state++;
4036         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4037                 mp->pause_received++;
4038 }
4039
4040 static int niu_mac_interrupt(struct niu *np)
4041 {
4042         if (np->flags & NIU_FLAGS_XMAC)
4043                 niu_xmac_interrupt(np);
4044         else
4045                 niu_bmac_interrupt(np);
4046
4047         return 0;
4048 }
4049
4050 static void niu_log_device_error(struct niu *np, u64 stat)
4051 {
4052         netdev_err(np->dev, "Core device errors ( ");
4053
4054         if (stat & SYS_ERR_MASK_META2)
4055                 pr_cont("META2 ");
4056         if (stat & SYS_ERR_MASK_META1)
4057                 pr_cont("META1 ");
4058         if (stat & SYS_ERR_MASK_PEU)
4059                 pr_cont("PEU ");
4060         if (stat & SYS_ERR_MASK_TXC)
4061                 pr_cont("TXC ");
4062         if (stat & SYS_ERR_MASK_RDMC)
4063                 pr_cont("RDMC ");
4064         if (stat & SYS_ERR_MASK_TDMC)
4065                 pr_cont("TDMC ");
4066         if (stat & SYS_ERR_MASK_ZCP)
4067                 pr_cont("ZCP ");
4068         if (stat & SYS_ERR_MASK_FFLP)
4069                 pr_cont("FFLP ");
4070         if (stat & SYS_ERR_MASK_IPP)
4071                 pr_cont("IPP ");
4072         if (stat & SYS_ERR_MASK_MAC)
4073                 pr_cont("MAC ");
4074         if (stat & SYS_ERR_MASK_SMX)
4075                 pr_cont("SMX ");
4076
4077         pr_cont(")\n");
4078 }
4079
4080 static int niu_device_error(struct niu *np)
4081 {
4082         u64 stat = nr64(SYS_ERR_STAT);
4083
4084         netdev_err(np->dev, "Core device error, stat[%llx]\n",
4085                    (unsigned long long)stat);
4086
4087         niu_log_device_error(np, stat);
4088
4089         return -ENODEV;
4090 }
4091
4092 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4093                               u64 v0, u64 v1, u64 v2)
4094 {
4095
4096         int i, err = 0;
4097
4098         lp->v0 = v0;
4099         lp->v1 = v1;
4100         lp->v2 = v2;
4101
4102         if (v1 & 0x00000000ffffffffULL) {
4103                 u32 rx_vec = (v1 & 0xffffffff);
4104
4105                 for (i = 0; i < np->num_rx_rings; i++) {
4106                         struct rx_ring_info *rp = &np->rx_rings[i];
4107
4108                         if (rx_vec & (1 << rp->rx_channel)) {
4109                                 int r = niu_rx_error(np, rp);
4110                                 if (r) {
4111                                         err = r;
4112                                 } else {
4113                                         if (!v0)
4114                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4115                                                      RX_DMA_CTL_STAT_MEX);
4116                                 }
4117                         }
4118                 }
4119         }
4120         if (v1 & 0x7fffffff00000000ULL) {
4121                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4122
4123                 for (i = 0; i < np->num_tx_rings; i++) {
4124                         struct tx_ring_info *rp = &np->tx_rings[i];
4125
4126                         if (tx_vec & (1 << rp->tx_channel)) {
4127                                 int r = niu_tx_error(np, rp);
4128                                 if (r)
4129                                         err = r;
4130                         }
4131                 }
4132         }
4133         if ((v0 | v1) & 0x8000000000000000ULL) {
4134                 int r = niu_mif_interrupt(np);
4135                 if (r)
4136                         err = r;
4137         }
4138         if (v2) {
4139                 if (v2 & 0x01ef) {
4140                         int r = niu_mac_interrupt(np);
4141                         if (r)
4142                                 err = r;
4143                 }
4144                 if (v2 & 0x0210) {
4145                         int r = niu_device_error(np);
4146                         if (r)
4147                                 err = r;
4148                 }
4149         }
4150
4151         if (err)
4152                 niu_enable_interrupts(np, 0);
4153
4154         return err;
4155 }
4156
4157 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4158                             int ldn)
4159 {
4160         struct rxdma_mailbox *mbox = rp->mbox;
4161         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4162
4163         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4164                       RX_DMA_CTL_STAT_RCRTO);
4165         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4166
4167         netif_printk(np, intr, KERN_DEBUG, np->dev,
4168                      "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4169 }
4170
4171 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4172                             int ldn)
4173 {
4174         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4175
4176         netif_printk(np, intr, KERN_DEBUG, np->dev,
4177                      "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4178 }
4179
4180 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4181 {
4182         struct niu_parent *parent = np->parent;
4183         u32 rx_vec, tx_vec;
4184         int i;
4185
4186         tx_vec = (v0 >> 32);
4187         rx_vec = (v0 & 0xffffffff);
4188
4189         for (i = 0; i < np->num_rx_rings; i++) {
4190                 struct rx_ring_info *rp = &np->rx_rings[i];
4191                 int ldn = LDN_RXDMA(rp->rx_channel);
4192
4193                 if (parent->ldg_map[ldn] != ldg)
4194                         continue;
4195
4196                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4197                 if (rx_vec & (1 << rp->rx_channel))
4198                         niu_rxchan_intr(np, rp, ldn);
4199         }
4200
4201         for (i = 0; i < np->num_tx_rings; i++) {
4202                 struct tx_ring_info *rp = &np->tx_rings[i];
4203                 int ldn = LDN_TXDMA(rp->tx_channel);
4204
4205                 if (parent->ldg_map[ldn] != ldg)
4206                         continue;
4207
4208                 nw64(LD_IM0(ldn), LD_IM0_MASK);
4209                 if (tx_vec & (1 << rp->tx_channel))
4210                         niu_txchan_intr(np, rp, ldn);
4211         }
4212 }
4213
4214 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4215                               u64 v0, u64 v1, u64 v2)
4216 {
4217         if (likely(napi_schedule_prep(&lp->napi))) {
4218                 lp->v0 = v0;
4219                 lp->v1 = v1;
4220                 lp->v2 = v2;
4221                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4222                 __napi_schedule(&lp->napi);
4223         }
4224 }
4225
4226 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4227 {
4228         struct niu_ldg *lp = dev_id;
4229         struct niu *np = lp->np;
4230         int ldg = lp->ldg_num;
4231         unsigned long flags;
4232         u64 v0, v1, v2;
4233
4234         if (netif_msg_intr(np))
4235                 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4236                        __func__, lp, ldg);
4237
4238         spin_lock_irqsave(&np->lock, flags);
4239
4240         v0 = nr64(LDSV0(ldg));
4241         v1 = nr64(LDSV1(ldg));
4242         v2 = nr64(LDSV2(ldg));
4243
4244         if (netif_msg_intr(np))
4245                 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4246                        (unsigned long long) v0,
4247                        (unsigned long long) v1,
4248                        (unsigned long long) v2);
4249
4250         if (unlikely(!v0 && !v1 && !v2)) {
4251                 spin_unlock_irqrestore(&np->lock, flags);
4252                 return IRQ_NONE;
4253         }
4254
4255         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4256                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4257                 if (err)
4258                         goto out;
4259         }
4260         if (likely(v0 & ~((u64)1 << LDN_MIF)))
4261                 niu_schedule_napi(np, lp, v0, v1, v2);
4262         else
4263                 niu_ldg_rearm(np, lp, 1);
4264 out:
4265         spin_unlock_irqrestore(&np->lock, flags);
4266
4267         return IRQ_HANDLED;
4268 }
4269
4270 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4271 {
4272         if (rp->mbox) {
4273                 np->ops->free_coherent(np->device,
4274                                        sizeof(struct rxdma_mailbox),
4275                                        rp->mbox, rp->mbox_dma);
4276                 rp->mbox = NULL;
4277         }
4278         if (rp->rcr) {
4279                 np->ops->free_coherent(np->device,
4280                                        MAX_RCR_RING_SIZE * sizeof(__le64),
4281                                        rp->rcr, rp->rcr_dma);
4282                 rp->rcr = NULL;
4283                 rp->rcr_table_size = 0;
4284                 rp->rcr_index = 0;
4285         }
4286         if (rp->rbr) {
4287                 niu_rbr_free(np, rp);
4288
4289                 np->ops->free_coherent(np->device,
4290                                        MAX_RBR_RING_SIZE * sizeof(__le32),
4291                                        rp->rbr, rp->rbr_dma);
4292                 rp->rbr = NULL;
4293                 rp->rbr_table_size = 0;
4294                 rp->rbr_index = 0;
4295         }
4296         kfree(rp->rxhash);
4297         rp->rxhash = NULL;
4298 }
4299
4300 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4301 {
4302         if (rp->mbox) {
4303                 np->ops->free_coherent(np->device,
4304                                        sizeof(struct txdma_mailbox),
4305                                        rp->mbox, rp->mbox_dma);
4306                 rp->mbox = NULL;
4307         }
4308         if (rp->descr) {
4309                 int i;
4310
4311                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4312                         if (rp->tx_buffs[i].skb)
4313                                 (void) release_tx_packet(np, rp, i);
4314                 }
4315
4316                 np->ops->free_coherent(np->device,
4317                                        MAX_TX_RING_SIZE * sizeof(__le64),
4318                                        rp->descr, rp->descr_dma);
4319                 rp->descr = NULL;
4320                 rp->pending = 0;
4321                 rp->prod = 0;
4322                 rp->cons = 0;
4323                 rp->wrap_bit = 0;
4324         }
4325 }
4326
4327 static void niu_free_channels(struct niu *np)
4328 {
4329         int i;
4330
4331         if (np->rx_rings) {
4332                 for (i = 0; i < np->num_rx_rings; i++) {
4333                         struct rx_ring_info *rp = &np->rx_rings[i];
4334
4335                         niu_free_rx_ring_info(np, rp);
4336                 }
4337                 kfree(np->rx_rings);
4338                 np->rx_rings = NULL;
4339                 np->num_rx_rings = 0;
4340         }
4341
4342         if (np->tx_rings) {
4343                 for (i = 0; i < np->num_tx_rings; i++) {
4344                         struct tx_ring_info *rp = &np->tx_rings[i];
4345
4346                         niu_free_tx_ring_info(np, rp);
4347                 }
4348                 kfree(np->tx_rings);
4349                 np->tx_rings = NULL;
4350                 np->num_tx_rings = 0;
4351         }
4352 }
4353
4354 static int niu_alloc_rx_ring_info(struct niu *np,
4355                                   struct rx_ring_info *rp)
4356 {
4357         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4358
4359         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4360                              GFP_KERNEL);
4361         if (!rp->rxhash)
4362                 return -ENOMEM;
4363
4364         rp->mbox = np->ops->alloc_coherent(np->device,
4365                                            sizeof(struct rxdma_mailbox),
4366                                            &rp->mbox_dma, GFP_KERNEL);
4367         if (!rp->mbox)
4368                 return -ENOMEM;
4369         if ((unsigned long)rp->mbox & (64UL - 1)) {
4370                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4371                            rp->mbox);
4372                 return -EINVAL;
4373         }
4374
4375         rp->rcr = np->ops->alloc_coherent(np->device,
4376                                           MAX_RCR_RING_SIZE * sizeof(__le64),
4377                                           &rp->rcr_dma, GFP_KERNEL);
4378         if (!rp->rcr)
4379                 return -ENOMEM;
4380         if ((unsigned long)rp->rcr & (64UL - 1)) {
4381                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4382                            rp->rcr);
4383                 return -EINVAL;
4384         }
4385         rp->rcr_table_size = MAX_RCR_RING_SIZE;
4386         rp->rcr_index = 0;
4387
4388         rp->rbr = np->ops->alloc_coherent(np->device,
4389                                           MAX_RBR_RING_SIZE * sizeof(__le32),
4390                                           &rp->rbr_dma, GFP_KERNEL);
4391         if (!rp->rbr)
4392                 return -ENOMEM;
4393         if ((unsigned long)rp->rbr & (64UL - 1)) {
4394                 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4395                            rp->rbr);
4396                 return -EINVAL;
4397         }
4398         rp->rbr_table_size = MAX_RBR_RING_SIZE;
4399         rp->rbr_index = 0;
4400         rp->rbr_pending = 0;
4401
4402         return 0;
4403 }
4404
4405 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4406 {
4407         int mtu = np->dev->mtu;
4408
4409         /* These values are recommended by the HW designers for fair
4410          * utilization of DRR amongst the rings.
4411          */
4412         rp->max_burst = mtu + 32;
4413         if (rp->max_burst > 4096)
4414                 rp->max_burst = 4096;
4415 }
4416
4417 static int niu_alloc_tx_ring_info(struct niu *np,
4418                                   struct tx_ring_info *rp)
4419 {
4420         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4421
4422         rp->mbox = np->ops->alloc_coherent(np->device,
4423                                            sizeof(struct txdma_mailbox),
4424                                            &rp->mbox_dma, GFP_KERNEL);
4425         if (!rp->mbox)
4426                 return -ENOMEM;
4427         if ((unsigned long)rp->mbox & (64UL - 1)) {
4428                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4429                            rp->mbox);
4430                 return -EINVAL;
4431         }
4432
4433         rp->descr = np->ops->alloc_coherent(np->device,
4434                                             MAX_TX_RING_SIZE * sizeof(__le64),
4435                                             &rp->descr_dma, GFP_KERNEL);
4436         if (!rp->descr)
4437                 return -ENOMEM;
4438         if ((unsigned long)rp->descr & (64UL - 1)) {
4439                 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4440                            rp->descr);
4441                 return -EINVAL;
4442         }
4443
4444         rp->pending = MAX_TX_RING_SIZE;
4445         rp->prod = 0;
4446         rp->cons = 0;
4447         rp->wrap_bit = 0;
4448
4449         /* XXX make these configurable... XXX */
4450         rp->mark_freq = rp->pending / 4;
4451
4452         niu_set_max_burst(np, rp);
4453
4454         return 0;
4455 }
4456
4457 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4458 {
4459         u16 bss;
4460
4461         bss = min(PAGE_SHIFT, 15);
4462
4463         rp->rbr_block_size = 1 << bss;
4464         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4465
4466         rp->rbr_sizes[0] = 256;
4467         rp->rbr_sizes[1] = 1024;
4468         if (np->dev->mtu > ETH_DATA_LEN) {
4469                 switch (PAGE_SIZE) {
4470                 case 4 * 1024:
4471                         rp->rbr_sizes[2] = 4096;
4472                         break;
4473
4474                 default:
4475                         rp->rbr_sizes[2] = 8192;
4476                         break;
4477                 }
4478         } else {
4479                 rp->rbr_sizes[2] = 2048;
4480         }
4481         rp->rbr_sizes[3] = rp->rbr_block_size;
4482 }
4483
4484 static int niu_alloc_channels(struct niu *np)
4485 {
4486         struct niu_parent *parent = np->parent;
4487         int first_rx_channel, first_tx_channel;
4488         int i, port, err;
4489
4490         port = np->port;
4491         first_rx_channel = first_tx_channel = 0;
4492         for (i = 0; i < port; i++) {
4493                 first_rx_channel += parent->rxchan_per_port[i];
4494                 first_tx_channel += parent->txchan_per_port[i];
4495         }
4496
4497         np->num_rx_rings = parent->rxchan_per_port[port];
4498         np->num_tx_rings = parent->txchan_per_port[port];
4499
4500         np->dev->real_num_tx_queues = np->num_tx_rings;
4501
4502         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4503                                GFP_KERNEL);
4504         err = -ENOMEM;
4505         if (!np->rx_rings)
4506                 goto out_err;
4507
4508         for (i = 0; i < np->num_rx_rings; i++) {
4509                 struct rx_ring_info *rp = &np->rx_rings[i];
4510
4511                 rp->np = np;
4512                 rp->rx_channel = first_rx_channel + i;
4513
4514                 err = niu_alloc_rx_ring_info(np, rp);
4515                 if (err)
4516                         goto out_err;
4517
4518                 niu_size_rbr(np, rp);
4519
4520                 /* XXX better defaults, configurable, etc... XXX */
4521                 rp->nonsyn_window = 64;
4522                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4523                 rp->syn_window = 64;
4524                 rp->syn_threshold = rp->rcr_table_size - 64;
4525                 rp->rcr_pkt_threshold = 16;
4526                 rp->rcr_timeout = 8;
4527                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4528                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4529                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4530
4531                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4532                 if (err)
4533                         return err;
4534         }
4535
4536         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4537                                GFP_KERNEL);
4538         err = -ENOMEM;
4539         if (!np->tx_rings)
4540                 goto out_err;
4541
4542         for (i = 0; i < np->num_tx_rings; i++) {
4543                 struct tx_ring_info *rp = &np->tx_rings[i];
4544
4545                 rp->np = np;
4546                 rp->tx_channel = first_tx_channel + i;
4547
4548                 err = niu_alloc_tx_ring_info(np, rp);
4549                 if (err)
4550                         goto out_err;
4551         }
4552
4553         return 0;
4554
4555 out_err:
4556         niu_free_channels(np);
4557         return err;
4558 }
4559
4560 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4561 {
4562         int limit = 1000;
4563
4564         while (--limit > 0) {
4565                 u64 val = nr64(TX_CS(channel));
4566                 if (val & TX_CS_SNG_STATE)
4567                         return 0;
4568         }
4569         return -ENODEV;
4570 }
4571
4572 static int niu_tx_channel_stop(struct niu *np, int channel)
4573 {
4574         u64 val = nr64(TX_CS(channel));
4575
4576         val |= TX_CS_STOP_N_GO;
4577         nw64(TX_CS(channel), val);
4578
4579         return niu_tx_cs_sng_poll(np, channel);
4580 }
4581
4582 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4583 {
4584         int limit = 1000;
4585
4586         while (--limit > 0) {
4587                 u64 val = nr64(TX_CS(channel));
4588                 if (!(val & TX_CS_RST))
4589                         return 0;
4590         }
4591         return -ENODEV;
4592 }
4593
4594 static int niu_tx_channel_reset(struct niu *np, int channel)
4595 {
4596         u64 val = nr64(TX_CS(channel));
4597         int err;
4598
4599         val |= TX_CS_RST;
4600         nw64(TX_CS(channel), val);
4601
4602         err = niu_tx_cs_reset_poll(np, channel);
4603         if (!err)
4604                 nw64(TX_RING_KICK(channel), 0);
4605
4606         return err;
4607 }
4608
4609 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4610 {
4611         u64 val;
4612
4613         nw64(TX_LOG_MASK1(channel), 0);
4614         nw64(TX_LOG_VAL1(channel), 0);
4615         nw64(TX_LOG_MASK2(channel), 0);
4616         nw64(TX_LOG_VAL2(channel), 0);
4617         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4618         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4619         nw64(TX_LOG_PAGE_HDL(channel), 0);
4620
4621         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4622         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4623         nw64(TX_LOG_PAGE_VLD(channel), val);
4624
4625         /* XXX TXDMA 32bit mode? XXX */
4626
4627         return 0;
4628 }
4629
4630 static void niu_txc_enable_port(struct niu *np, int on)
4631 {
4632         unsigned long flags;
4633         u64 val, mask;
4634
4635         niu_lock_parent(np, flags);
4636         val = nr64(TXC_CONTROL);
4637         mask = (u64)1 << np->port;
4638         if (on) {
4639                 val |= TXC_CONTROL_ENABLE | mask;
4640         } else {
4641                 val &= ~mask;
4642                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4643                         val &= ~TXC_CONTROL_ENABLE;
4644         }
4645         nw64(TXC_CONTROL, val);
4646         niu_unlock_parent(np, flags);
4647 }
4648
4649 static void niu_txc_set_imask(struct niu *np, u64 imask)
4650 {
4651         unsigned long flags;
4652         u64 val;
4653
4654         niu_lock_parent(np, flags);
4655         val = nr64(TXC_INT_MASK);
4656         val &= ~TXC_INT_MASK_VAL(np->port);
4657         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4658         niu_unlock_parent(np, flags);
4659 }
4660
4661 static void niu_txc_port_dma_enable(struct niu *np, int on)
4662 {
4663         u64 val = 0;
4664
4665         if (on) {
4666                 int i;
4667
4668                 for (i = 0; i < np->num_tx_rings; i++)
4669                         val |= (1 << np->tx_rings[i].tx_channel);
4670         }
4671         nw64(TXC_PORT_DMA(np->port), val);
4672 }
4673
4674 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4675 {
4676         int err, channel = rp->tx_channel;
4677         u64 val, ring_len;
4678
4679         err = niu_tx_channel_stop(np, channel);
4680         if (err)
4681                 return err;
4682
4683         err = niu_tx_channel_reset(np, channel);
4684         if (err)
4685                 return err;
4686
4687         err = niu_tx_channel_lpage_init(np, channel);
4688         if (err)
4689                 return err;
4690
4691         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4692         nw64(TX_ENT_MSK(channel), 0);
4693
4694         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4695                               TX_RNG_CFIG_STADDR)) {
4696                 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4697                            channel, (unsigned long long)rp->descr_dma);
4698                 return -EINVAL;
4699         }
4700
4701         /* The length field in TX_RNG_CFIG is measured in 64-byte
4702          * blocks.  rp->pending is the number of TX descriptors in
4703          * our ring, 8 bytes each, thus we divide by 8 bytes more
4704          * to get the proper value the chip wants.
4705          */
4706         ring_len = (rp->pending / 8);
4707
4708         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4709                rp->descr_dma);
4710         nw64(TX_RNG_CFIG(channel), val);
4711
4712         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4713             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4714                 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4715                             channel, (unsigned long long)rp->mbox_dma);
4716                 return -EINVAL;
4717         }
4718         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4719         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4720
4721         nw64(TX_CS(channel), 0);
4722
4723         rp->last_pkt_cnt = 0;
4724
4725         return 0;
4726 }
4727
4728 static void niu_init_rdc_groups(struct niu *np)
4729 {
4730         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4731         int i, first_table_num = tp->first_table_num;
4732
4733         for (i = 0; i < tp->num_tables; i++) {
4734                 struct rdc_table *tbl = &tp->tables[i];
4735                 int this_table = first_table_num + i;
4736                 int slot;
4737
4738                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4739                         nw64(RDC_TBL(this_table, slot),
4740                              tbl->rxdma_channel[slot]);
4741         }
4742
4743         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4744 }
4745
4746 static void niu_init_drr_weight(struct niu *np)
4747 {
4748         int type = phy_decode(np->parent->port_phy, np->port);
4749         u64 val;
4750
4751         switch (type) {
4752         case PORT_TYPE_10G:
4753                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4754                 break;
4755
4756         case PORT_TYPE_1G:
4757         default:
4758                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4759                 break;
4760         }
4761         nw64(PT_DRR_WT(np->port), val);
4762 }
4763
4764 static int niu_init_hostinfo(struct niu *np)
4765 {
4766         struct niu_parent *parent = np->parent;
4767         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4768         int i, err, num_alt = niu_num_alt_addr(np);
4769         int first_rdc_table = tp->first_table_num;
4770
4771         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4772         if (err)
4773                 return err;
4774
4775         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4776         if (err)
4777                 return err;
4778
4779         for (i = 0; i < num_alt; i++) {
4780                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4781                 if (err)
4782                         return err;
4783         }
4784
4785         return 0;
4786 }
4787
4788 static int niu_rx_channel_reset(struct niu *np, int channel)
4789 {
4790         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4791                                       RXDMA_CFIG1_RST, 1000, 10,
4792                                       "RXDMA_CFIG1");
4793 }
4794
4795 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4796 {
4797         u64 val;
4798
4799         nw64(RX_LOG_MASK1(channel), 0);
4800         nw64(RX_LOG_VAL1(channel), 0);
4801         nw64(RX_LOG_MASK2(channel), 0);
4802         nw64(RX_LOG_VAL2(channel), 0);
4803         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4804         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4805         nw64(RX_LOG_PAGE_HDL(channel), 0);
4806
4807         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4808         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4809         nw64(RX_LOG_PAGE_VLD(channel), val);
4810
4811         return 0;
4812 }
4813
4814 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4815 {
4816         u64 val;
4817
4818         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4819                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4820                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4821                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4822         nw64(RDC_RED_PARA(rp->rx_channel), val);
4823 }
4824
4825 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4826 {
4827         u64 val = 0;
4828
4829         *ret = 0;
4830         switch (rp->rbr_block_size) {
4831         case 4 * 1024:
4832                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4833                 break;
4834         case 8 * 1024:
4835                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4836                 break;
4837         case 16 * 1024:
4838                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4839                 break;
4840         case 32 * 1024:
4841                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4842                 break;
4843         default:
4844                 return -EINVAL;
4845         }
4846         val |= RBR_CFIG_B_VLD2;
4847         switch (rp->rbr_sizes[2]) {
4848         case 2 * 1024:
4849                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4850                 break;
4851         case 4 * 1024:
4852                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4853                 break;
4854         case 8 * 1024:
4855                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4856                 break;
4857         case 16 * 1024:
4858                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4859                 break;
4860
4861         default:
4862                 return -EINVAL;
4863         }
4864         val |= RBR_CFIG_B_VLD1;
4865         switch (rp->rbr_sizes[1]) {
4866         case 1 * 1024:
4867                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4868                 break;
4869         case 2 * 1024:
4870                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4871                 break;
4872         case 4 * 1024:
4873                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4874                 break;
4875         case 8 * 1024:
4876                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4877                 break;
4878
4879         default:
4880                 return -EINVAL;
4881         }
4882         val |= RBR_CFIG_B_VLD0;
4883         switch (rp->rbr_sizes[0]) {
4884         case 256:
4885                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4886                 break;
4887         case 512:
4888                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4889                 break;
4890         case 1 * 1024:
4891                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4892                 break;
4893         case 2 * 1024:
4894                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4895                 break;
4896
4897         default:
4898                 return -EINVAL;
4899         }
4900
4901         *ret = val;
4902         return 0;
4903 }
4904
4905 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4906 {
4907         u64 val = nr64(RXDMA_CFIG1(channel));
4908         int limit;
4909
4910         if (on)
4911                 val |= RXDMA_CFIG1_EN;
4912         else
4913                 val &= ~RXDMA_CFIG1_EN;
4914         nw64(RXDMA_CFIG1(channel), val);
4915
4916         limit = 1000;
4917         while (--limit > 0) {
4918                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4919                         break;
4920                 udelay(10);
4921         }
4922         if (limit <= 0)
4923                 return -ENODEV;
4924         return 0;
4925 }
4926
4927 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4928 {
4929         int err, channel = rp->rx_channel;
4930         u64 val;
4931
4932         err = niu_rx_channel_reset(np, channel);
4933         if (err)
4934                 return err;
4935
4936         err = niu_rx_channel_lpage_init(np, channel);
4937         if (err)
4938                 return err;
4939
4940         niu_rx_channel_wred_init(np, rp);
4941
4942         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4943         nw64(RX_DMA_CTL_STAT(channel),
4944              (RX_DMA_CTL_STAT_MEX |
4945               RX_DMA_CTL_STAT_RCRTHRES |
4946               RX_DMA_CTL_STAT_RCRTO |
4947               RX_DMA_CTL_STAT_RBR_EMPTY));
4948         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4949         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4950         nw64(RBR_CFIG_A(channel),
4951              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4952              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4953         err = niu_compute_rbr_cfig_b(rp, &val);
4954         if (err)
4955                 return err;
4956         nw64(RBR_CFIG_B(channel), val);
4957         nw64(RCRCFIG_A(channel),
4958              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4959              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4960         nw64(RCRCFIG_B(channel),
4961              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4962              RCRCFIG_B_ENTOUT |
4963              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4964
4965         err = niu_enable_rx_channel(np, channel, 1);
4966         if (err)
4967                 return err;
4968
4969         nw64(RBR_KICK(channel), rp->rbr_index);
4970
4971         val = nr64(RX_DMA_CTL_STAT(channel));
4972         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4973         nw64(RX_DMA_CTL_STAT(channel), val);
4974
4975         return 0;
4976 }
4977
4978 static int niu_init_rx_channels(struct niu *np)
4979 {
4980         unsigned long flags;
4981         u64 seed = jiffies_64;
4982         int err, i;
4983
4984         niu_lock_parent(np, flags);
4985         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4986         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4987         niu_unlock_parent(np, flags);
4988
4989         /* XXX RXDMA 32bit mode? XXX */
4990
4991         niu_init_rdc_groups(np);
4992         niu_init_drr_weight(np);
4993
4994         err = niu_init_hostinfo(np);
4995         if (err)
4996                 return err;
4997
4998         for (i = 0; i < np->num_rx_rings; i++) {
4999                 struct rx_ring_info *rp = &np->rx_rings[i];
5000
5001                 err = niu_init_one_rx_channel(np, rp);
5002                 if (err)
5003                         return err;
5004         }
5005
5006         return 0;
5007 }
5008
5009 static int niu_set_ip_frag_rule(struct niu *np)
5010 {
5011         struct niu_parent *parent = np->parent;
5012         struct niu_classifier *cp = &np->clas;
5013         struct niu_tcam_entry *tp;
5014         int index, err;
5015
5016         index = cp->tcam_top;
5017         tp = &parent->tcam[index];
5018
5019         /* Note that the noport bit is the same in both ipv4 and
5020          * ipv6 format TCAM entries.
5021          */
5022         memset(tp, 0, sizeof(*tp));
5023         tp->key[1] = TCAM_V4KEY1_NOPORT;
5024         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5025         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5026                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5027         err = tcam_write(np, index, tp->key, tp->key_mask);
5028         if (err)
5029                 return err;
5030         err = tcam_assoc_write(np, index, tp->assoc_data);
5031         if (err)
5032                 return err;
5033         tp->valid = 1;
5034         cp->tcam_valid_entries++;
5035
5036         return 0;
5037 }
5038
5039 static int niu_init_classifier_hw(struct niu *np)
5040 {
5041         struct niu_parent *parent = np->parent;
5042         struct niu_classifier *cp = &np->clas;
5043         int i, err;
5044
5045         nw64(H1POLY, cp->h1_init);
5046         nw64(H2POLY, cp->h2_init);
5047
5048         err = niu_init_hostinfo(np);
5049         if (err)
5050                 return err;
5051
5052         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5053                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5054
5055                 vlan_tbl_write(np, i, np->port,
5056                                vp->vlan_pref, vp->rdc_num);
5057         }
5058
5059         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5060                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5061
5062                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5063                                                 ap->rdc_num, ap->mac_pref);
5064                 if (err)
5065                         return err;
5066         }
5067
5068         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5069                 int index = i - CLASS_CODE_USER_PROG1;
5070
5071                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5072                 if (err)
5073                         return err;
5074                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5075                 if (err)
5076                         return err;
5077         }
5078
5079         err = niu_set_ip_frag_rule(np);
5080         if (err)
5081                 return err;
5082
5083         tcam_enable(np, 1);
5084
5085         return 0;
5086 }
5087
5088 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5089 {
5090         nw64(ZCP_RAM_DATA0, data[0]);
5091         nw64(ZCP_RAM_DATA1, data[1]);
5092         nw64(ZCP_RAM_DATA2, data[2]);
5093         nw64(ZCP_RAM_DATA3, data[3]);
5094         nw64(ZCP_RAM_DATA4, data[4]);
5095         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5096         nw64(ZCP_RAM_ACC,
5097              (ZCP_RAM_ACC_WRITE |
5098               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5099               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5100
5101         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5102                                    1000, 100);
5103 }
5104
5105 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5106 {
5107         int err;
5108
5109         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5110                                   1000, 100);
5111         if (err) {
5112                 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5113                            (unsigned long long)nr64(ZCP_RAM_ACC));
5114                 return err;
5115         }
5116
5117         nw64(ZCP_RAM_ACC,
5118              (ZCP_RAM_ACC_READ |
5119               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5120               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5121
5122         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5123                                   1000, 100);
5124         if (err) {
5125                 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5126                            (unsigned long long)nr64(ZCP_RAM_ACC));
5127                 return err;
5128         }
5129
5130         data[0] = nr64(ZCP_RAM_DATA0);
5131         data[1] = nr64(ZCP_RAM_DATA1);
5132         data[2] = nr64(ZCP_RAM_DATA2);
5133         data[3] = nr64(ZCP_RAM_DATA3);
5134         data[4] = nr64(ZCP_RAM_DATA4);
5135
5136         return 0;
5137 }
5138
5139 static void niu_zcp_cfifo_reset(struct niu *np)
5140 {
5141         u64 val = nr64(RESET_CFIFO);
5142
5143         val |= RESET_CFIFO_RST(np->port);
5144         nw64(RESET_CFIFO, val);
5145         udelay(10);
5146
5147         val &= ~RESET_CFIFO_RST(np->port);
5148         nw64(RESET_CFIFO, val);
5149 }
5150
5151 static int niu_init_zcp(struct niu *np)
5152 {
5153         u64 data[5], rbuf[5];
5154         int i, max, err;
5155
5156         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5157                 if (np->port == 0 || np->port == 1)
5158                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
5159                 else
5160                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
5161         } else
5162                 max = NIU_CFIFO_ENTRIES;
5163
5164         data[0] = 0;
5165         data[1] = 0;
5166         data[2] = 0;
5167         data[3] = 0;
5168         data[4] = 0;
5169
5170         for (i = 0; i < max; i++) {
5171                 err = niu_zcp_write(np, i, data);
5172                 if (err)
5173                         return err;
5174                 err = niu_zcp_read(np, i, rbuf);
5175                 if (err)
5176                         return err;
5177         }
5178
5179         niu_zcp_cfifo_reset(np);
5180         nw64(CFIFO_ECC(np->port), 0);
5181         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5182         (void) nr64(ZCP_INT_STAT);
5183         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5184
5185         return 0;
5186 }
5187
5188 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5189 {
5190         u64 val = nr64_ipp(IPP_CFIG);
5191
5192         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5193         nw64_ipp(IPP_DFIFO_WR_PTR, index);
5194         nw64_ipp(IPP_DFIFO_WR0, data[0]);
5195         nw64_ipp(IPP_DFIFO_WR1, data[1]);
5196         nw64_ipp(IPP_DFIFO_WR2, data[2]);
5197         nw64_ipp(IPP_DFIFO_WR3, data[3]);
5198         nw64_ipp(IPP_DFIFO_WR4, data[4]);
5199         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5200 }
5201
5202 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5203 {
5204         nw64_ipp(IPP_DFIFO_RD_PTR, index);
5205         data[0] = nr64_ipp(IPP_DFIFO_RD0);
5206         data[1] = nr64_ipp(IPP_DFIFO_RD1);
5207         data[2] = nr64_ipp(IPP_DFIFO_RD2);
5208         data[3] = nr64_ipp(IPP_DFIFO_RD3);
5209         data[4] = nr64_ipp(IPP_DFIFO_RD4);
5210 }
5211
5212 static int niu_ipp_reset(struct niu *np)
5213 {
5214         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5215                                           1000, 100, "IPP_CFIG");
5216 }
5217
5218 static int niu_init_ipp(struct niu *np)
5219 {
5220         u64 data[5], rbuf[5], val;
5221         int i, max, err;
5222
5223         if (np->parent->plat_type != PLAT_TYPE_NIU) {
5224                 if (np->port == 0 || np->port == 1)
5225                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
5226                 else
5227                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
5228         } else
5229                 max = NIU_DFIFO_ENTRIES;
5230
5231         data[0] = 0;
5232         data[1] = 0;
5233         data[2] = 0;
5234         data[3] = 0;
5235         data[4] = 0;
5236
5237         for (i = 0; i < max; i++) {
5238                 niu_ipp_write(np, i, data);
5239                 niu_ipp_read(np, i, rbuf);
5240         }
5241
5242         (void) nr64_ipp(IPP_INT_STAT);
5243         (void) nr64_ipp(IPP_INT_STAT);
5244
5245         err = niu_ipp_reset(np);
5246         if (err)
5247                 return err;
5248
5249         (void) nr64_ipp(IPP_PKT_DIS);
5250         (void) nr64_ipp(IPP_BAD_CS_CNT);
5251         (void) nr64_ipp(IPP_ECC);
5252
5253         (void) nr64_ipp(IPP_INT_STAT);
5254
5255         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5256
5257         val = nr64_ipp(IPP_CFIG);
5258         val &= ~IPP_CFIG_IP_MAX_PKT;
5259         val |= (IPP_CFIG_IPP_ENABLE |
5260                 IPP_CFIG_DFIFO_ECC_EN |
5261                 IPP_CFIG_DROP_BAD_CRC |
5262                 IPP_CFIG_CKSUM_EN |
5263                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5264         nw64_ipp(IPP_CFIG, val);
5265
5266         return 0;
5267 }
5268
5269 static void niu_handle_led(struct niu *np, int status)
5270 {
5271         u64 val;
5272         val = nr64_mac(XMAC_CONFIG);
5273
5274         if ((np->flags & NIU_FLAGS_10G) != 0 &&
5275             (np->flags & NIU_FLAGS_FIBER) != 0) {
5276                 if (status) {
5277                         val |= XMAC_CONFIG_LED_POLARITY;
5278                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
5279                 } else {
5280                         val |= XMAC_CONFIG_FORCE_LED_ON;
5281                         val &= ~XMAC_CONFIG_LED_POLARITY;
5282                 }
5283         }
5284
5285         nw64_mac(XMAC_CONFIG, val);
5286 }
5287
5288 static void niu_init_xif_xmac(struct niu *np)
5289 {
5290         struct niu_link_config *lp = &np->link_config;
5291         u64 val;
5292
5293         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5294                 val = nr64(MIF_CONFIG);
5295                 val |= MIF_CONFIG_ATCA_GE;
5296                 nw64(MIF_CONFIG, val);
5297         }
5298
5299         val = nr64_mac(XMAC_CONFIG);
5300         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5301
5302         val |= XMAC_CONFIG_TX_OUTPUT_EN;
5303
5304         if (lp->loopback_mode == LOOPBACK_MAC) {
5305                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5306                 val |= XMAC_CONFIG_LOOPBACK;
5307         } else {
5308                 val &= ~XMAC_CONFIG_LOOPBACK;
5309         }
5310
5311         if (np->flags & NIU_FLAGS_10G) {
5312                 val &= ~XMAC_CONFIG_LFS_DISABLE;
5313         } else {
5314                 val |= XMAC_CONFIG_LFS_DISABLE;
5315                 if (!(np->flags & NIU_FLAGS_FIBER) &&
5316                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
5317                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
5318                 else
5319                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5320         }
5321
5322         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5323
5324         if (lp->active_speed == SPEED_100)
5325                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5326         else
5327                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5328
5329         nw64_mac(XMAC_CONFIG, val);
5330
5331         val = nr64_mac(XMAC_CONFIG);
5332         val &= ~XMAC_CONFIG_MODE_MASK;
5333         if (np->flags & NIU_FLAGS_10G) {
5334                 val |= XMAC_CONFIG_MODE_XGMII;
5335         } else {
5336                 if (lp->active_speed == SPEED_1000)
5337                         val |= XMAC_CONFIG_MODE_GMII;
5338                 else
5339                         val |= XMAC_CONFIG_MODE_MII;
5340         }
5341
5342         nw64_mac(XMAC_CONFIG, val);
5343 }
5344
5345 static void niu_init_xif_bmac(struct niu *np)
5346 {
5347         struct niu_link_config *lp = &np->link_config;
5348         u64 val;
5349
5350         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5351
5352         if (lp->loopback_mode == LOOPBACK_MAC)
5353                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5354         else
5355                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5356
5357         if (lp->active_speed == SPEED_1000)
5358                 val |= BMAC_XIF_CONFIG_GMII_MODE;
5359         else
5360                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5361
5362         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5363                  BMAC_XIF_CONFIG_LED_POLARITY);
5364
5365         if (!(np->flags & NIU_FLAGS_10G) &&
5366             !(np->flags & NIU_FLAGS_FIBER) &&
5367             lp->active_speed == SPEED_100)
5368                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5369         else
5370                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5371
5372         nw64_mac(BMAC_XIF_CONFIG, val);
5373 }
5374
5375 static void niu_init_xif(struct niu *np)
5376 {
5377         if (np->flags & NIU_FLAGS_XMAC)
5378                 niu_init_xif_xmac(np);
5379         else
5380                 niu_init_xif_bmac(np);
5381 }
5382
5383 static void niu_pcs_mii_reset(struct niu *np)
5384 {
5385         int limit = 1000;
5386         u64 val = nr64_pcs(PCS_MII_CTL);
5387         val |= PCS_MII_CTL_RST;
5388         nw64_pcs(PCS_MII_CTL, val);
5389         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5390                 udelay(100);
5391                 val = nr64_pcs(PCS_MII_CTL);
5392         }
5393 }
5394
5395 static void niu_xpcs_reset(struct niu *np)
5396 {
5397         int limit = 1000;
5398         u64 val = nr64_xpcs(XPCS_CONTROL1);
5399         val |= XPCS_CONTROL1_RESET;
5400         nw64_xpcs(XPCS_CONTROL1, val);
5401         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5402                 udelay(100);
5403                 val = nr64_xpcs(XPCS_CONTROL1);
5404         }
5405 }
5406
5407 static int niu_init_pcs(struct niu *np)
5408 {
5409         struct niu_link_config *lp = &np->link_config;
5410         u64 val;
5411
5412         switch (np->flags & (NIU_FLAGS_10G |
5413                              NIU_FLAGS_FIBER |
5414                              NIU_FLAGS_XCVR_SERDES)) {
5415         case NIU_FLAGS_FIBER:
5416                 /* 1G fiber */
5417                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5418                 nw64_pcs(PCS_DPATH_MODE, 0);
5419                 niu_pcs_mii_reset(np);
5420                 break;
5421
5422         case NIU_FLAGS_10G:
5423         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5424         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5425                 /* 10G SERDES */
5426                 if (!(np->flags & NIU_FLAGS_XMAC))
5427                         return -EINVAL;
5428
5429                 /* 10G copper or fiber */
5430                 val = nr64_mac(XMAC_CONFIG);
5431                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5432                 nw64_mac(XMAC_CONFIG, val);
5433
5434                 niu_xpcs_reset(np);
5435
5436                 val = nr64_xpcs(XPCS_CONTROL1);
5437                 if (lp->loopback_mode == LOOPBACK_PHY)
5438                         val |= XPCS_CONTROL1_LOOPBACK;
5439                 else
5440                         val &= ~XPCS_CONTROL1_LOOPBACK;
5441                 nw64_xpcs(XPCS_CONTROL1, val);
5442
5443                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5444                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5445                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5446                 break;
5447
5448
5449         case NIU_FLAGS_XCVR_SERDES:
5450                 /* 1G SERDES */
5451                 niu_pcs_mii_reset(np);
5452                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5453                 nw64_pcs(PCS_DPATH_MODE, 0);
5454                 break;
5455
5456         case 0:
5457                 /* 1G copper */
5458         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5459                 /* 1G RGMII FIBER */
5460                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5461                 niu_pcs_mii_reset(np);
5462                 break;
5463
5464         default:
5465                 return -EINVAL;
5466         }
5467
5468         return 0;
5469 }
5470
5471 static int niu_reset_tx_xmac(struct niu *np)
5472 {
5473         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5474                                           (XTXMAC_SW_RST_REG_RS |
5475                                            XTXMAC_SW_RST_SOFT_RST),
5476                                           1000, 100, "XTXMAC_SW_RST");
5477 }
5478
5479 static int niu_reset_tx_bmac(struct niu *np)
5480 {
5481         int limit;
5482
5483         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5484         limit = 1000;
5485         while (--limit >= 0) {
5486                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5487                         break;
5488                 udelay(100);
5489         }
5490         if (limit < 0) {
5491                 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5492                         np->port,
5493                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5494                 return -ENODEV;
5495         }
5496
5497         return 0;
5498 }
5499
5500 static int niu_reset_tx_mac(struct niu *np)
5501 {
5502         if (np->flags & NIU_FLAGS_XMAC)
5503                 return niu_reset_tx_xmac(np);
5504         else
5505                 return niu_reset_tx_bmac(np);
5506 }
5507
5508 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5509 {
5510         u64 val;
5511
5512         val = nr64_mac(XMAC_MIN);
5513         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5514                  XMAC_MIN_RX_MIN_PKT_SIZE);
5515         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5516         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5517         nw64_mac(XMAC_MIN, val);
5518
5519         nw64_mac(XMAC_MAX, max);
5520
5521         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5522
5523         val = nr64_mac(XMAC_IPG);
5524         if (np->flags & NIU_FLAGS_10G) {
5525                 val &= ~XMAC_IPG_IPG_XGMII;
5526                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5527         } else {
5528                 val &= ~XMAC_IPG_IPG_MII_GMII;
5529                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5530         }
5531         nw64_mac(XMAC_IPG, val);
5532
5533         val = nr64_mac(XMAC_CONFIG);
5534         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5535                  XMAC_CONFIG_STRETCH_MODE |
5536                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5537                  XMAC_CONFIG_TX_ENABLE);
5538         nw64_mac(XMAC_CONFIG, val);
5539
5540         nw64_mac(TXMAC_FRM_CNT, 0);
5541         nw64_mac(TXMAC_BYTE_CNT, 0);
5542 }
5543
5544 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5545 {
5546         u64 val;
5547
5548         nw64_mac(BMAC_MIN_FRAME, min);
5549         nw64_mac(BMAC_MAX_FRAME, max);
5550
5551         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5552         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5553         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5554
5555         val = nr64_mac(BTXMAC_CONFIG);
5556         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5557                  BTXMAC_CONFIG_ENABLE);
5558         nw64_mac(BTXMAC_CONFIG, val);
5559 }
5560
5561 static void niu_init_tx_mac(struct niu *np)
5562 {
5563         u64 min, max;
5564
5565         min = 64;
5566         if (np->dev->mtu > ETH_DATA_LEN)
5567                 max = 9216;
5568         else
5569                 max = 1522;
5570
5571         /* The XMAC_MIN register only accepts values for TX min which
5572          * have the low 3 bits cleared.
5573          */
5574         BUG_ON(min & 0x7);
5575
5576         if (np->flags & NIU_FLAGS_XMAC)
5577                 niu_init_tx_xmac(np, min, max);
5578         else
5579                 niu_init_tx_bmac(np, min, max);
5580 }
5581
5582 static int niu_reset_rx_xmac(struct niu *np)
5583 {
5584         int limit;
5585
5586         nw64_mac(XRXMAC_SW_RST,
5587                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5588         limit = 1000;
5589         while (--limit >= 0) {
5590                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5591                                                  XRXMAC_SW_RST_SOFT_RST)))
5592                         break;
5593                 udelay(100);
5594         }
5595         if (limit < 0) {
5596                 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5597                         np->port,
5598                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5599                 return -ENODEV;
5600         }
5601
5602         return 0;
5603 }
5604
5605 static int niu_reset_rx_bmac(struct niu *np)
5606 {
5607         int limit;
5608
5609         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5610         limit = 1000;
5611         while (--limit >= 0) {
5612                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5613                         break;
5614                 udelay(100);
5615         }
5616         if (limit < 0) {
5617                 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5618                         np->port,
5619                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5620                 return -ENODEV;
5621         }
5622
5623         return 0;
5624 }
5625
5626 static int niu_reset_rx_mac(struct niu *np)
5627 {
5628         if (np->flags & NIU_FLAGS_XMAC)
5629                 return niu_reset_rx_xmac(np);
5630         else
5631                 return niu_reset_rx_bmac(np);
5632 }
5633
5634 static void niu_init_rx_xmac(struct niu *np)
5635 {
5636         struct niu_parent *parent = np->parent;
5637         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5638         int first_rdc_table = tp->first_table_num;
5639         unsigned long i;
5640         u64 val;
5641
5642         nw64_mac(XMAC_ADD_FILT0, 0);
5643         nw64_mac(XMAC_ADD_FILT1, 0);
5644         nw64_mac(XMAC_ADD_FILT2, 0);
5645         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5646         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5647         for (i = 0; i < MAC_NUM_HASH; i++)
5648                 nw64_mac(XMAC_HASH_TBL(i), 0);
5649         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5650         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5651         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5652
5653         val = nr64_mac(XMAC_CONFIG);
5654         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5655                  XMAC_CONFIG_PROMISCUOUS |
5656                  XMAC_CONFIG_PROMISC_GROUP |
5657                  XMAC_CONFIG_ERR_CHK_DIS |
5658                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5659                  XMAC_CONFIG_RESERVED_MULTICAST |
5660                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5661                  XMAC_CONFIG_ADDR_FILTER_EN |
5662                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5663                  XMAC_CONFIG_STRIP_CRC |
5664                  XMAC_CONFIG_PASS_FLOW_CTRL |
5665                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5666         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5667         nw64_mac(XMAC_CONFIG, val);
5668
5669         nw64_mac(RXMAC_BT_CNT, 0);
5670         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5671         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5672         nw64_mac(RXMAC_FRAG_CNT, 0);
5673         nw64_mac(RXMAC_HIST_CNT1, 0);
5674         nw64_mac(RXMAC_HIST_CNT2, 0);
5675         nw64_mac(RXMAC_HIST_CNT3, 0);
5676         nw64_mac(RXMAC_HIST_CNT4, 0);
5677         nw64_mac(RXMAC_HIST_CNT5, 0);
5678         nw64_mac(RXMAC_HIST_CNT6, 0);
5679         nw64_mac(RXMAC_HIST_CNT7, 0);
5680         nw64_mac(RXMAC_MPSZER_CNT, 0);
5681         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5682         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5683         nw64_mac(LINK_FAULT_CNT, 0);
5684 }
5685
5686 static void niu_init_rx_bmac(struct niu *np)
5687 {
5688         struct niu_parent *parent = np->parent;
5689         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5690         int first_rdc_table = tp->first_table_num;
5691         unsigned long i;
5692         u64 val;
5693
5694         nw64_mac(BMAC_ADD_FILT0, 0);
5695         nw64_mac(BMAC_ADD_FILT1, 0);
5696         nw64_mac(BMAC_ADD_FILT2, 0);
5697         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5698         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5699         for (i = 0; i < MAC_NUM_HASH; i++)
5700                 nw64_mac(BMAC_HASH_TBL(i), 0);
5701         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5702         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5703         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5704
5705         val = nr64_mac(BRXMAC_CONFIG);
5706         val &= ~(BRXMAC_CONFIG_ENABLE |
5707                  BRXMAC_CONFIG_STRIP_PAD |
5708                  BRXMAC_CONFIG_STRIP_FCS |
5709                  BRXMAC_CONFIG_PROMISC |
5710                  BRXMAC_CONFIG_PROMISC_GRP |
5711                  BRXMAC_CONFIG_ADDR_FILT_EN |
5712                  BRXMAC_CONFIG_DISCARD_DIS);
5713         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5714         nw64_mac(BRXMAC_CONFIG, val);
5715
5716         val = nr64_mac(BMAC_ADDR_CMPEN);
5717         val |= BMAC_ADDR_CMPEN_EN0;
5718         nw64_mac(BMAC_ADDR_CMPEN, val);
5719 }
5720
5721 static void niu_init_rx_mac(struct niu *np)
5722 {
5723         niu_set_primary_mac(np, np->dev->dev_addr);
5724
5725         if (np->flags & NIU_FLAGS_XMAC)
5726                 niu_init_rx_xmac(np);
5727         else
5728                 niu_init_rx_bmac(np);
5729 }
5730
5731 static void niu_enable_tx_xmac(struct niu *np, int on)
5732 {
5733         u64 val = nr64_mac(XMAC_CONFIG);
5734
5735         if (on)
5736                 val |= XMAC_CONFIG_TX_ENABLE;
5737         else
5738                 val &= ~XMAC_CONFIG_TX_ENABLE;
5739         nw64_mac(XMAC_CONFIG, val);
5740 }
5741
5742 static void niu_enable_tx_bmac(struct niu *np, int on)
5743 {
5744         u64 val = nr64_mac(BTXMAC_CONFIG);
5745
5746         if (on)
5747                 val |= BTXMAC_CONFIG_ENABLE;
5748         else
5749                 val &= ~BTXMAC_CONFIG_ENABLE;
5750         nw64_mac(BTXMAC_CONFIG, val);
5751 }
5752
5753 static void niu_enable_tx_mac(struct niu *np, int on)
5754 {
5755         if (np->flags & NIU_FLAGS_XMAC)
5756                 niu_enable_tx_xmac(np, on);
5757         else
5758                 niu_enable_tx_bmac(np, on);
5759 }
5760
5761 static void niu_enable_rx_xmac(struct niu *np, int on)
5762 {
5763         u64 val = nr64_mac(XMAC_CONFIG);
5764
5765         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5766                  XMAC_CONFIG_PROMISCUOUS);
5767
5768         if (np->flags & NIU_FLAGS_MCAST)
5769                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5770         if (np->flags & NIU_FLAGS_PROMISC)
5771                 val |= XMAC_CONFIG_PROMISCUOUS;
5772
5773         if (on)
5774                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5775         else
5776                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5777         nw64_mac(XMAC_CONFIG, val);
5778 }
5779
5780 static void niu_enable_rx_bmac(struct niu *np, int on)
5781 {
5782         u64 val = nr64_mac(BRXMAC_CONFIG);
5783
5784         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5785                  BRXMAC_CONFIG_PROMISC);
5786
5787         if (np->flags & NIU_FLAGS_MCAST)
5788                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5789         if (np->flags & NIU_FLAGS_PROMISC)
5790                 val |= BRXMAC_CONFIG_PROMISC;
5791
5792         if (on)
5793                 val |= BRXMAC_CONFIG_ENABLE;
5794         else
5795                 val &= ~BRXMAC_CONFIG_ENABLE;
5796         nw64_mac(BRXMAC_CONFIG, val);
5797 }
5798
5799 static void niu_enable_rx_mac(struct niu *np, int on)
5800 {
5801         if (np->flags & NIU_FLAGS_XMAC)
5802                 niu_enable_rx_xmac(np, on);
5803         else
5804                 niu_enable_rx_bmac(np, on);
5805 }
5806
5807 static int niu_init_mac(struct niu *np)
5808 {
5809         int err;
5810
5811         niu_init_xif(np);
5812         err = niu_init_pcs(np);
5813         if (err)
5814                 return err;
5815
5816         err = niu_reset_tx_mac(np);
5817         if (err)
5818                 return err;
5819         niu_init_tx_mac(np);
5820         err = niu_reset_rx_mac(np);
5821         if (err)
5822                 return err;
5823         niu_init_rx_mac(np);
5824
5825         /* This looks hookey but the RX MAC reset we just did will
5826          * undo some of the state we setup in niu_init_tx_mac() so we
5827          * have to call it again.  In particular, the RX MAC reset will
5828          * set the XMAC_MAX register back to it's default value.
5829          */
5830         niu_init_tx_mac(np);
5831         niu_enable_tx_mac(np, 1);
5832
5833         niu_enable_rx_mac(np, 1);
5834
5835         return 0;
5836 }
5837
5838 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5839 {
5840         (void) niu_tx_channel_stop(np, rp->tx_channel);
5841 }
5842
5843 static void niu_stop_tx_channels(struct niu *np)
5844 {
5845         int i;
5846
5847         for (i = 0; i < np->num_tx_rings; i++) {
5848                 struct tx_ring_info *rp = &np->tx_rings[i];
5849
5850                 niu_stop_one_tx_channel(np, rp);
5851         }
5852 }
5853
5854 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5855 {
5856         (void) niu_tx_channel_reset(np, rp->tx_channel);
5857 }
5858
5859 static void niu_reset_tx_channels(struct niu *np)
5860 {
5861         int i;
5862
5863         for (i = 0; i < np->num_tx_rings; i++) {
5864                 struct tx_ring_info *rp = &np->tx_rings[i];
5865
5866                 niu_reset_one_tx_channel(np, rp);
5867         }
5868 }
5869
5870 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5871 {
5872         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5873 }
5874
5875 static void niu_stop_rx_channels(struct niu *np)
5876 {
5877         int i;
5878
5879         for (i = 0; i < np->num_rx_rings; i++) {
5880                 struct rx_ring_info *rp = &np->rx_rings[i];
5881
5882                 niu_stop_one_rx_channel(np, rp);
5883         }
5884 }
5885
5886 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5887 {
5888         int channel = rp->rx_channel;
5889
5890         (void) niu_rx_channel_reset(np, channel);
5891         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5892         nw64(RX_DMA_CTL_STAT(channel), 0);
5893         (void) niu_enable_rx_channel(np, channel, 0);
5894 }
5895
5896 static void niu_reset_rx_channels(struct niu *np)
5897 {
5898         int i;
5899
5900         for (i = 0; i < np->num_rx_rings; i++) {
5901                 struct rx_ring_info *rp = &np->rx_rings[i];
5902
5903                 niu_reset_one_rx_channel(np, rp);
5904         }
5905 }
5906
5907 static void niu_disable_ipp(struct niu *np)
5908 {
5909         u64 rd, wr, val;
5910         int limit;
5911
5912         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5913         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5914         limit = 100;
5915         while (--limit >= 0 && (rd != wr)) {
5916                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5917                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5918         }
5919         if (limit < 0 &&
5920             (rd != 0 && wr != 1)) {
5921                 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5922                            (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5923                            (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5924         }
5925
5926         val = nr64_ipp(IPP_CFIG);
5927         val &= ~(IPP_CFIG_IPP_ENABLE |
5928                  IPP_CFIG_DFIFO_ECC_EN |
5929                  IPP_CFIG_DROP_BAD_CRC |
5930                  IPP_CFIG_CKSUM_EN);
5931         nw64_ipp(IPP_CFIG, val);
5932
5933         (void) niu_ipp_reset(np);
5934 }
5935
5936 static int niu_init_hw(struct niu *np)
5937 {
5938         int i, err;
5939
5940         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5941         niu_txc_enable_port(np, 1);
5942         niu_txc_port_dma_enable(np, 1);
5943         niu_txc_set_imask(np, 0);
5944
5945         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5946         for (i = 0; i < np->num_tx_rings; i++) {
5947                 struct tx_ring_info *rp = &np->tx_rings[i];
5948
5949                 err = niu_init_one_tx_channel(np, rp);
5950                 if (err)
5951                         return err;
5952         }
5953
5954         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5955         err = niu_init_rx_channels(np);
5956         if (err)
5957                 goto out_uninit_tx_channels;
5958
5959         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5960         err = niu_init_classifier_hw(np);
5961         if (err)
5962                 goto out_uninit_rx_channels;
5963
5964         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5965         err = niu_init_zcp(np);
5966         if (err)
5967                 goto out_uninit_rx_channels;
5968
5969         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5970         err = niu_init_ipp(np);
5971         if (err)
5972                 goto out_uninit_rx_channels;
5973
5974         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5975         err = niu_init_mac(np);
5976         if (err)
5977                 goto out_uninit_ipp;
5978
5979         return 0;
5980
5981 out_uninit_ipp:
5982         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5983         niu_disable_ipp(np);
5984
5985 out_uninit_rx_channels:
5986         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5987         niu_stop_rx_channels(np);
5988         niu_reset_rx_channels(np);
5989
5990 out_uninit_tx_channels:
5991         netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5992         niu_stop_tx_channels(np);
5993         niu_reset_tx_channels(np);
5994
5995         return err;
5996 }
5997
5998 static void niu_stop_hw(struct niu *np)
5999 {
6000         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6001         niu_enable_interrupts(np, 0);
6002
6003         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6004         niu_enable_rx_mac(np, 0);
6005
6006         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6007         niu_disable_ipp(np);
6008
6009         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6010         niu_stop_tx_channels(np);
6011
6012         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6013         niu_stop_rx_channels(np);
6014
6015         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6016         niu_reset_tx_channels(np);
6017
6018         netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6019         niu_reset_rx_channels(np);
6020 }
6021
6022 static void niu_set_irq_name(struct niu *np)
6023 {
6024         int port = np->port;
6025         int i, j = 1;
6026
6027         sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6028
6029         if (port == 0) {
6030                 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6031                 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6032                 j = 3;
6033         }
6034
6035         for (i = 0; i < np->num_ldg - j; i++) {
6036                 if (i < np->num_rx_rings)
6037                         sprintf(np->irq_name[i+j], "%s-rx-%d",
6038                                 np->dev->name, i);
6039                 else if (i < np->num_tx_rings + np->num_rx_rings)
6040                         sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6041                                 i - np->num_rx_rings);
6042         }
6043 }
6044
6045 static int niu_request_irq(struct niu *np)
6046 {
6047         int i, j, err;
6048
6049         niu_set_irq_name(np);
6050
6051         err = 0;
6052         for (i = 0; i < np->num_ldg; i++) {
6053                 struct niu_ldg *lp = &np->ldg[i];
6054
6055                 err = request_irq(lp->irq, niu_interrupt,
6056                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6057                                   np->irq_name[i], lp);
6058                 if (err)
6059                         goto out_free_irqs;
6060
6061         }
6062
6063         return 0;
6064
6065 out_free_irqs:
6066         for (j = 0; j < i; j++) {
6067                 struct niu_ldg *lp = &np->ldg[j];
6068
6069                 free_irq(lp->irq, lp);
6070         }
6071         return err;
6072 }
6073
6074 static void niu_free_irq(struct niu *np)
6075 {
6076         int i;
6077
6078         for (i = 0; i < np->num_ldg; i++) {
6079                 struct niu_ldg *lp = &np->ldg[i];
6080
6081                 free_irq(lp->irq, lp);
6082         }
6083 }
6084
6085 static void niu_enable_napi(struct niu *np)
6086 {
6087         int i;
6088
6089         for (i = 0; i < np->num_ldg; i++)
6090                 napi_enable(&np->ldg[i].napi);
6091 }
6092
6093 static void niu_disable_napi(struct niu *np)
6094 {
6095         int i;
6096
6097         for (i = 0; i < np->num_ldg; i++)
6098                 napi_disable(&np->ldg[i].napi);
6099 }
6100
6101 static int niu_open(struct net_device *dev)
6102 {
6103         struct niu *np = netdev_priv(dev);
6104         int err;
6105
6106         netif_carrier_off(dev);
6107
6108         err = niu_alloc_channels(np);
6109         if (err)
6110                 goto out_err;
6111
6112         err = niu_enable_interrupts(np, 0);
6113         if (err)
6114                 goto out_free_channels;
6115
6116         err = niu_request_irq(np);
6117         if (err)
6118                 goto out_free_channels;
6119
6120         niu_enable_napi(np);
6121
6122         spin_lock_irq(&np->lock);
6123
6124         err = niu_init_hw(np);
6125         if (!err) {
6126                 init_timer(&np->timer);
6127                 np->timer.expires = jiffies + HZ;
6128                 np->timer.data = (unsigned long) np;
6129                 np->timer.function = niu_timer;
6130
6131                 err = niu_enable_interrupts(np, 1);
6132                 if (err)
6133                         niu_stop_hw(np);
6134         }
6135
6136         spin_unlock_irq(&np->lock);
6137
6138         if (err) {
6139                 niu_disable_napi(np);
6140                 goto out_free_irq;
6141         }
6142
6143         netif_tx_start_all_queues(dev);
6144
6145         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6146                 netif_carrier_on(dev);
6147
6148         add_timer(&np->timer);
6149
6150         return 0;
6151
6152 out_free_irq:
6153         niu_free_irq(np);
6154
6155 out_free_channels:
6156         niu_free_channels(np);
6157
6158 out_err:
6159         return err;
6160 }
6161
6162 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6163 {
6164         cancel_work_sync(&np->reset_task);
6165
6166         niu_disable_napi(np);
6167         netif_tx_stop_all_queues(dev);
6168
6169         del_timer_sync(&np->timer);
6170
6171         spin_lock_irq(&np->lock);
6172
6173         niu_stop_hw(np);
6174
6175         spin_unlock_irq(&np->lock);
6176 }
6177
6178 static int niu_close(struct net_device *dev)
6179 {
6180         struct niu *np = netdev_priv(dev);
6181
6182         niu_full_shutdown(np, dev);
6183
6184         niu_free_irq(np);
6185
6186         niu_free_channels(np);
6187
6188         niu_handle_led(np, 0);
6189
6190         return 0;
6191 }
6192
6193 static void niu_sync_xmac_stats(struct niu *np)
6194 {
6195         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6196
6197         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6198         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6199
6200         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6201         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6202         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6203         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6204         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6205         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6206         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6207         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6208         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6209         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6210         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6211         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6212         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6213         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6214         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6215         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6216 }
6217
6218 static void niu_sync_bmac_stats(struct niu *np)
6219 {
6220         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6221
6222         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6223         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6224
6225         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6226         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6227         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6228         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6229 }
6230
6231 static void niu_sync_mac_stats(struct niu *np)
6232 {
6233         if (np->flags & NIU_FLAGS_XMAC)
6234                 niu_sync_xmac_stats(np);
6235         else
6236                 niu_sync_bmac_stats(np);
6237 }
6238
6239 static void niu_get_rx_stats(struct niu *np)
6240 {
6241         unsigned long pkts, dropped, errors, bytes;
6242         int i;
6243
6244         pkts = dropped = errors = bytes = 0;
6245         for (i = 0; i < np->num_rx_rings; i++) {
6246                 struct rx_ring_info *rp = &np->rx_rings[i];
6247
6248                 niu_sync_rx_discard_stats(np, rp, 0);
6249
6250                 pkts += rp->rx_packets;
6251                 bytes += rp->rx_bytes;
6252                 dropped += rp->rx_dropped;
6253                 errors += rp->rx_errors;
6254         }
6255         np->dev->stats.rx_packets = pkts;
6256         np->dev->stats.rx_bytes = bytes;
6257         np->dev->stats.rx_dropped = dropped;
6258         np->dev->stats.rx_errors = errors;
6259 }
6260
6261 static void niu_get_tx_stats(struct niu *np)
6262 {
6263         unsigned long pkts, errors, bytes;
6264         int i;
6265
6266         pkts = errors = bytes = 0;
6267         for (i = 0; i < np->num_tx_rings; i++) {
6268                 struct tx_ring_info *rp = &np->tx_rings[i];
6269
6270                 pkts += rp->tx_packets;
6271                 bytes += rp->tx_bytes;
6272                 errors += rp->tx_errors;
6273         }
6274         np->dev->stats.tx_packets = pkts;
6275         np->dev->stats.tx_bytes = bytes;
6276         np->dev->stats.tx_errors = errors;
6277 }
6278
6279 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6280 {
6281         struct niu *np = netdev_priv(dev);
6282
6283         niu_get_rx_stats(np);
6284         niu_get_tx_stats(np);
6285
6286         return &dev->stats;
6287 }
6288
6289 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6290 {
6291         int i;
6292
6293         for (i = 0; i < 16; i++)
6294                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6295 }
6296
6297 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6298 {
6299         int i;
6300
6301         for (i = 0; i < 16; i++)
6302                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6303 }
6304
6305 static void niu_load_hash(struct niu *np, u16 *hash)
6306 {
6307         if (np->flags & NIU_FLAGS_XMAC)
6308                 niu_load_hash_xmac(np, hash);
6309         else
6310                 niu_load_hash_bmac(np, hash);
6311 }
6312
6313 static void niu_set_rx_mode(struct net_device *dev)
6314 {
6315         struct niu *np = netdev_priv(dev);
6316         int i, alt_cnt, err;
6317         struct dev_addr_list *addr;
6318         struct netdev_hw_addr *ha;
6319         unsigned long flags;
6320         u16 hash[16] = { 0, };
6321
6322         spin_lock_irqsave(&np->lock, flags);
6323         niu_enable_rx_mac(np, 0);
6324
6325         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6326         if (dev->flags & IFF_PROMISC)
6327                 np->flags |= NIU_FLAGS_PROMISC;
6328         if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6329                 np->flags |= NIU_FLAGS_MCAST;
6330
6331         alt_cnt = netdev_uc_count(dev);
6332         if (alt_cnt > niu_num_alt_addr(np)) {
6333                 alt_cnt = 0;
6334                 np->flags |= NIU_FLAGS_PROMISC;
6335         }
6336
6337         if (alt_cnt) {
6338                 int index = 0;
6339
6340                 netdev_for_each_uc_addr(ha, dev) {
6341                         err = niu_set_alt_mac(np, index, ha->addr);
6342                         if (err)
6343                                 netdev_warn(dev, "Error %d adding alt mac %d\n",
6344                                             err, index);
6345                         err = niu_enable_alt_mac(np, index, 1);
6346                         if (err)
6347                                 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6348                                             err, index);
6349
6350                         index++;
6351                 }
6352         } else {
6353                 int alt_start;
6354                 if (np->flags & NIU_FLAGS_XMAC)
6355                         alt_start = 0;
6356                 else
6357                         alt_start = 1;
6358                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6359                         err = niu_enable_alt_mac(np, i, 0);
6360                         if (err)
6361                                 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6362                                             err, i);
6363                 }
6364         }
6365         if (dev->flags & IFF_ALLMULTI) {
6366                 for (i = 0; i < 16; i++)
6367                         hash[i] = 0xffff;
6368         } else if (!netdev_mc_empty(dev)) {
6369                 netdev_for_each_mc_addr(addr, dev) {
6370                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6371
6372                         crc >>= 24;
6373                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6374                 }
6375         }
6376
6377         if (np->flags & NIU_FLAGS_MCAST)
6378                 niu_load_hash(np, hash);
6379
6380         niu_enable_rx_mac(np, 1);
6381         spin_unlock_irqrestore(&np->lock, flags);
6382 }
6383
6384 static int niu_set_mac_addr(struct net_device *dev, void *p)
6385 {
6386         struct niu *np = netdev_priv(dev);
6387         struct sockaddr *addr = p;
6388         unsigned long flags;
6389
6390         if (!is_valid_ether_addr(addr->sa_data))
6391                 return -EINVAL;
6392
6393         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6394
6395         if (!netif_running(dev))
6396                 return 0;
6397
6398         spin_lock_irqsave(&np->lock, flags);
6399         niu_enable_rx_mac(np, 0);
6400         niu_set_primary_mac(np, dev->dev_addr);
6401         niu_enable_rx_mac(np, 1);
6402         spin_unlock_irqrestore(&np->lock, flags);
6403
6404         return 0;
6405 }
6406
6407 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6408 {
6409         return -EOPNOTSUPP;
6410 }
6411
6412 static void niu_netif_stop(struct niu *np)
6413 {
6414         np->dev->trans_start = jiffies; /* prevent tx timeout */
6415
6416         niu_disable_napi(np);
6417
6418         netif_tx_disable(np->dev);
6419 }
6420
6421 static void niu_netif_start(struct niu *np)
6422 {
6423         /* NOTE: unconditional netif_wake_queue is only appropriate
6424          * so long as all callers are assured to have free tx slots
6425          * (such as after niu_init_hw).
6426          */
6427         netif_tx_wake_all_queues(np->dev);
6428
6429         niu_enable_napi(np);
6430
6431         niu_enable_interrupts(np, 1);
6432 }
6433
6434 static void niu_reset_buffers(struct niu *np)
6435 {
6436         int i, j, k, err;
6437
6438         if (np->rx_rings) {
6439                 for (i = 0; i < np->num_rx_rings; i++) {
6440                         struct rx_ring_info *rp = &np->rx_rings[i];
6441
6442                         for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6443                                 struct page *page;
6444
6445                                 page = rp->rxhash[j];
6446                                 while (page) {
6447                                         struct page *next =
6448                                                 (struct page *) page->mapping;
6449                                         u64 base = page->index;
6450                                         base = base >> RBR_DESCR_ADDR_SHIFT;
6451                                         rp->rbr[k++] = cpu_to_le32(base);
6452                                         page = next;
6453                                 }
6454                         }
6455                         for (; k < MAX_RBR_RING_SIZE; k++) {
6456                                 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6457                                 if (unlikely(err))
6458                                         break;
6459                         }
6460
6461                         rp->rbr_index = rp->rbr_table_size - 1;
6462                         rp->rcr_index = 0;
6463                         rp->rbr_pending = 0;
6464                         rp->rbr_refill_pending = 0;
6465                 }
6466         }
6467         if (np->tx_rings) {
6468                 for (i = 0; i < np->num_tx_rings; i++) {
6469                         struct tx_ring_info *rp = &np->tx_rings[i];
6470
6471                         for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6472                                 if (rp->tx_buffs[j].skb)
6473                                         (void) release_tx_packet(np, rp, j);
6474                         }
6475
6476                         rp->pending = MAX_TX_RING_SIZE;
6477                         rp->prod = 0;
6478                         rp->cons = 0;
6479                         rp->wrap_bit = 0;
6480                 }
6481         }
6482 }
6483
6484 static void niu_reset_task(struct work_struct *work)
6485 {
6486         struct niu *np = container_of(work, struct niu, reset_task);
6487         unsigned long flags;
6488         int err;
6489
6490         spin_lock_irqsave(&np->lock, flags);
6491         if (!netif_running(np->dev)) {
6492                 spin_unlock_irqrestore(&np->lock, flags);
6493                 return;
6494         }
6495
6496         spin_unlock_irqrestore(&np->lock, flags);
6497
6498         del_timer_sync(&np->timer);
6499
6500         niu_netif_stop(np);
6501
6502         spin_lock_irqsave(&np->lock, flags);
6503
6504         niu_stop_hw(np);
6505
6506         spin_unlock_irqrestore(&np->lock, flags);
6507
6508         niu_reset_buffers(np);
6509
6510         spin_lock_irqsave(&np->lock, flags);
6511
6512         err = niu_init_hw(np);
6513         if (!err) {
6514                 np->timer.expires = jiffies + HZ;
6515                 add_timer(&np->timer);
6516                 niu_netif_start(np);
6517         }
6518
6519         spin_unlock_irqrestore(&np->lock, flags);
6520 }
6521
6522 static void niu_tx_timeout(struct net_device *dev)
6523 {
6524         struct niu *np = netdev_priv(dev);
6525
6526         dev_err(np->device, "%s: Transmit timed out, resetting\n",
6527                 dev->name);
6528
6529         schedule_work(&np->reset_task);
6530 }
6531
6532 static void niu_set_txd(struct tx_ring_info *rp, int index,
6533                         u64 mapping, u64 len, u64 mark,
6534                         u64 n_frags)
6535 {
6536         __le64 *desc = &rp->descr[index];
6537
6538         *desc = cpu_to_le64(mark |
6539                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6540                             (len << TX_DESC_TR_LEN_SHIFT) |
6541                             (mapping & TX_DESC_SAD));
6542 }
6543
6544 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6545                                 u64 pad_bytes, u64 len)
6546 {
6547         u16 eth_proto, eth_proto_inner;
6548         u64 csum_bits, l3off, ihl, ret;
6549         u8 ip_proto;
6550         int ipv6;
6551
6552         eth_proto = be16_to_cpu(ehdr->h_proto);
6553         eth_proto_inner = eth_proto;
6554         if (eth_proto == ETH_P_8021Q) {
6555                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6556                 __be16 val = vp->h_vlan_encapsulated_proto;
6557
6558                 eth_proto_inner = be16_to_cpu(val);
6559         }
6560
6561         ipv6 = ihl = 0;
6562         switch (skb->protocol) {
6563         case cpu_to_be16(ETH_P_IP):
6564                 ip_proto = ip_hdr(skb)->protocol;
6565                 ihl = ip_hdr(skb)->ihl;
6566                 break;
6567         case cpu_to_be16(ETH_P_IPV6):
6568                 ip_proto = ipv6_hdr(skb)->nexthdr;
6569                 ihl = (40 >> 2);
6570                 ipv6 = 1;
6571                 break;
6572         default:
6573                 ip_proto = ihl = 0;
6574                 break;
6575         }
6576
6577         csum_bits = TXHDR_CSUM_NONE;
6578         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6579                 u64 start, stuff;
6580
6581                 csum_bits = (ip_proto == IPPROTO_TCP ?
6582                              TXHDR_CSUM_TCP :
6583                              (ip_proto == IPPROTO_UDP ?
6584                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6585
6586                 start = skb_transport_offset(skb) -
6587                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6588                 stuff = start + skb->csum_offset;
6589
6590                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6591                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6592         }
6593
6594         l3off = skb_network_offset(skb) -
6595                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6596
6597         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6598                (len << TXHDR_LEN_SHIFT) |
6599                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6600                (ihl << TXHDR_IHL_SHIFT) |
6601                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6602                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6603                (ipv6 ? TXHDR_IP_VER : 0) |
6604                csum_bits);
6605
6606         return ret;
6607 }
6608
6609 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6610                                   struct net_device *dev)
6611 {
6612         struct niu *np = netdev_priv(dev);
6613         unsigned long align, headroom;
6614         struct netdev_queue *txq;
6615         struct tx_ring_info *rp;
6616         struct tx_pkt_hdr *tp;
6617         unsigned int len, nfg;
6618         struct ethhdr *ehdr;
6619         int prod, i, tlen;
6620         u64 mapping, mrk;
6621
6622         i = skb_get_queue_mapping(skb);
6623         rp = &np->tx_rings[i];
6624         txq = netdev_get_tx_queue(dev, i);
6625
6626         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6627                 netif_tx_stop_queue(txq);
6628                 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6629                 rp->tx_errors++;
6630                 return NETDEV_TX_BUSY;
6631         }
6632
6633         if (skb->len < ETH_ZLEN) {
6634                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6635
6636                 if (skb_pad(skb, pad_bytes))
6637                         goto out;
6638                 skb_put(skb, pad_bytes);
6639         }
6640
6641         len = sizeof(struct tx_pkt_hdr) + 15;
6642         if (skb_headroom(skb) < len) {
6643                 struct sk_buff *skb_new;
6644
6645                 skb_new = skb_realloc_headroom(skb, len);
6646                 if (!skb_new) {
6647                         rp->tx_errors++;
6648                         goto out_drop;
6649                 }
6650                 kfree_skb(skb);
6651                 skb = skb_new;
6652         } else
6653                 skb_orphan(skb);
6654
6655         align = ((unsigned long) skb->data & (16 - 1));
6656         headroom = align + sizeof(struct tx_pkt_hdr);
6657
6658         ehdr = (struct ethhdr *) skb->data;
6659         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6660
6661         len = skb->len - sizeof(struct tx_pkt_hdr);
6662         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6663         tp->resv = 0;
6664
6665         len = skb_headlen(skb);
6666         mapping = np->ops->map_single(np->device, skb->data,
6667                                       len, DMA_TO_DEVICE);
6668
6669         prod = rp->prod;
6670
6671         rp->tx_buffs[prod].skb = skb;
6672         rp->tx_buffs[prod].mapping = mapping;
6673
6674         mrk = TX_DESC_SOP;
6675         if (++rp->mark_counter == rp->mark_freq) {
6676                 rp->mark_counter = 0;
6677                 mrk |= TX_DESC_MARK;
6678                 rp->mark_pending++;
6679         }
6680
6681         tlen = len;
6682         nfg = skb_shinfo(skb)->nr_frags;
6683         while (tlen > 0) {
6684                 tlen -= MAX_TX_DESC_LEN;
6685                 nfg++;
6686         }
6687
6688         while (len > 0) {
6689                 unsigned int this_len = len;
6690
6691                 if (this_len > MAX_TX_DESC_LEN)
6692                         this_len = MAX_TX_DESC_LEN;
6693
6694                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6695                 mrk = nfg = 0;
6696
6697                 prod = NEXT_TX(rp, prod);
6698                 mapping += this_len;
6699                 len -= this_len;
6700         }
6701
6702         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6703                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6704
6705                 len = frag->size;
6706                 mapping = np->ops->map_page(np->device, frag->page,
6707                                             frag->page_offset, len,
6708                                             DMA_TO_DEVICE);
6709
6710                 rp->tx_buffs[prod].skb = NULL;
6711                 rp->tx_buffs[prod].mapping = mapping;
6712
6713                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6714
6715                 prod = NEXT_TX(rp, prod);
6716         }
6717
6718         if (prod < rp->prod)
6719                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6720         rp->prod = prod;
6721
6722         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6723
6724         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6725                 netif_tx_stop_queue(txq);
6726                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6727                         netif_tx_wake_queue(txq);
6728         }
6729
6730 out:
6731         return NETDEV_TX_OK;
6732
6733 out_drop:
6734         rp->tx_errors++;
6735         kfree_skb(skb);
6736         goto out;
6737 }
6738
6739 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6740 {
6741         struct niu *np = netdev_priv(dev);
6742         int err, orig_jumbo, new_jumbo;
6743
6744         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6745                 return -EINVAL;
6746
6747         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6748         new_jumbo = (new_mtu > ETH_DATA_LEN);
6749
6750         dev->mtu = new_mtu;
6751
6752         if (!netif_running(dev) ||
6753             (orig_jumbo == new_jumbo))
6754                 return 0;
6755
6756         niu_full_shutdown(np, dev);
6757
6758         niu_free_channels(np);
6759
6760         niu_enable_napi(np);
6761
6762         err = niu_alloc_channels(np);
6763         if (err)
6764                 return err;
6765
6766         spin_lock_irq(&np->lock);
6767
6768         err = niu_init_hw(np);
6769         if (!err) {
6770                 init_timer(&np->timer);
6771                 np->timer.expires = jiffies + HZ;
6772                 np->timer.data = (unsigned long) np;
6773                 np->timer.function = niu_timer;
6774
6775                 err = niu_enable_interrupts(np, 1);
6776                 if (err)
6777                         niu_stop_hw(np);
6778         }
6779
6780         spin_unlock_irq(&np->lock);
6781
6782         if (!err) {
6783                 netif_tx_start_all_queues(dev);
6784                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6785                         netif_carrier_on(dev);
6786
6787                 add_timer(&np->timer);
6788         }
6789
6790         return err;
6791 }
6792
6793 static void niu_get_drvinfo(struct net_device *dev,
6794                             struct ethtool_drvinfo *info)
6795 {
6796         struct niu *np = netdev_priv(dev);
6797         struct niu_vpd *vpd = &np->vpd;
6798
6799         strcpy(info->driver, DRV_MODULE_NAME);
6800         strcpy(info->version, DRV_MODULE_VERSION);
6801         sprintf(info->fw_version, "%d.%d",
6802                 vpd->fcode_major, vpd->fcode_minor);
6803         if (np->parent->plat_type != PLAT_TYPE_NIU)
6804                 strcpy(info->bus_info, pci_name(np->pdev));
6805 }
6806
6807 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6808 {
6809         struct niu *np = netdev_priv(dev);
6810         struct niu_link_config *lp;
6811
6812         lp = &np->link_config;
6813
6814         memset(cmd, 0, sizeof(*cmd));
6815         cmd->phy_address = np->phy_addr;
6816         cmd->supported = lp->supported;
6817         cmd->advertising = lp->active_advertising;
6818         cmd->autoneg = lp->active_autoneg;
6819         cmd->speed = lp->active_speed;
6820         cmd->duplex = lp->active_duplex;
6821         cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6822         cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6823                 XCVR_EXTERNAL : XCVR_INTERNAL;
6824
6825         return 0;
6826 }
6827
6828 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6829 {
6830         struct niu *np = netdev_priv(dev);
6831         struct niu_link_config *lp = &np->link_config;
6832
6833         lp->advertising = cmd->advertising;
6834         lp->speed = cmd->speed;
6835         lp->duplex = cmd->duplex;
6836         lp->autoneg = cmd->autoneg;
6837         return niu_init_link(np);
6838 }
6839
6840 static u32 niu_get_msglevel(struct net_device *dev)
6841 {
6842         struct niu *np = netdev_priv(dev);
6843         return np->msg_enable;
6844 }
6845
6846 static void niu_set_msglevel(struct net_device *dev, u32 value)
6847 {
6848         struct niu *np = netdev_priv(dev);
6849         np->msg_enable = value;
6850 }
6851
6852 static int niu_nway_reset(struct net_device *dev)
6853 {
6854         struct niu *np = netdev_priv(dev);
6855
6856         if (np->link_config.autoneg)
6857                 return niu_init_link(np);
6858
6859         return 0;
6860 }
6861
6862 static int niu_get_eeprom_len(struct net_device *dev)
6863 {
6864         struct niu *np = netdev_priv(dev);
6865
6866         return np->eeprom_len;
6867 }
6868
6869 static int niu_get_eeprom(struct net_device *dev,
6870                           struct ethtool_eeprom *eeprom, u8 *data)
6871 {
6872         struct niu *np = netdev_priv(dev);
6873         u32 offset, len, val;
6874
6875         offset = eeprom->offset;
6876         len = eeprom->len;
6877
6878         if (offset + len < offset)
6879                 return -EINVAL;
6880         if (offset >= np->eeprom_len)
6881                 return -EINVAL;
6882         if (offset + len > np->eeprom_len)
6883                 len = eeprom->len = np->eeprom_len - offset;
6884
6885         if (offset & 3) {
6886                 u32 b_offset, b_count;
6887
6888                 b_offset = offset & 3;
6889                 b_count = 4 - b_offset;
6890                 if (b_count > len)
6891                         b_count = len;
6892
6893                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6894                 memcpy(data, ((char *)&val) + b_offset, b_count);
6895                 data += b_count;
6896                 len -= b_count;
6897                 offset += b_count;
6898         }
6899         while (len >= 4) {
6900                 val = nr64(ESPC_NCR(offset / 4));
6901                 memcpy(data, &val, 4);
6902                 data += 4;
6903                 len -= 4;
6904                 offset += 4;
6905         }
6906         if (len) {
6907                 val = nr64(ESPC_NCR(offset / 4));
6908                 memcpy(data, &val, len);
6909         }
6910         return 0;
6911 }
6912
6913 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6914 {
6915         switch (flow_type) {
6916         case TCP_V4_FLOW:
6917         case TCP_V6_FLOW:
6918                 *pid = IPPROTO_TCP;
6919                 break;
6920         case UDP_V4_FLOW:
6921         case UDP_V6_FLOW:
6922                 *pid = IPPROTO_UDP;
6923                 break;
6924         case SCTP_V4_FLOW:
6925         case SCTP_V6_FLOW:
6926                 *pid = IPPROTO_SCTP;
6927                 break;
6928         case AH_V4_FLOW:
6929         case AH_V6_FLOW:
6930                 *pid = IPPROTO_AH;
6931                 break;
6932         case ESP_V4_FLOW:
6933         case ESP_V6_FLOW:
6934                 *pid = IPPROTO_ESP;
6935                 break;
6936         default:
6937                 *pid = 0;
6938                 break;
6939         }
6940 }
6941
6942 static int niu_class_to_ethflow(u64 class, int *flow_type)
6943 {
6944         switch (class) {
6945         case CLASS_CODE_TCP_IPV4:
6946                 *flow_type = TCP_V4_FLOW;
6947                 break;
6948         case CLASS_CODE_UDP_IPV4:
6949                 *flow_type = UDP_V4_FLOW;
6950                 break;
6951         case CLASS_CODE_AH_ESP_IPV4:
6952                 *flow_type = AH_V4_FLOW;
6953                 break;
6954         case CLASS_CODE_SCTP_IPV4:
6955                 *flow_type = SCTP_V4_FLOW;
6956                 break;
6957         case CLASS_CODE_TCP_IPV6:
6958                 *flow_type = TCP_V6_FLOW;
6959                 break;
6960         case CLASS_CODE_UDP_IPV6:
6961                 *flow_type = UDP_V6_FLOW;
6962                 break;
6963         case CLASS_CODE_AH_ESP_IPV6:
6964                 *flow_type = AH_V6_FLOW;
6965                 break;
6966         case CLASS_CODE_SCTP_IPV6:
6967                 *flow_type = SCTP_V6_FLOW;
6968                 break;
6969         case CLASS_CODE_USER_PROG1:
6970         case CLASS_CODE_USER_PROG2:
6971         case CLASS_CODE_USER_PROG3:
6972         case CLASS_CODE_USER_PROG4:
6973                 *flow_type = IP_USER_FLOW;
6974                 break;
6975         default:
6976                 return 0;
6977         }
6978
6979         return 1;
6980 }
6981
6982 static int niu_ethflow_to_class(int flow_type, u64 *class)
6983 {
6984         switch (flow_type) {
6985         case TCP_V4_FLOW:
6986                 *class = CLASS_CODE_TCP_IPV4;
6987                 break;
6988         case UDP_V4_FLOW:
6989                 *class = CLASS_CODE_UDP_IPV4;
6990                 break;
6991         case AH_V4_FLOW:
6992         case ESP_V4_FLOW:
6993                 *class = CLASS_CODE_AH_ESP_IPV4;
6994                 break;
6995         case SCTP_V4_FLOW:
6996                 *class = CLASS_CODE_SCTP_IPV4;
6997                 break;
6998         case TCP_V6_FLOW:
6999                 *class = CLASS_CODE_TCP_IPV6;
7000                 break;
7001         case UDP_V6_FLOW:
7002                 *class = CLASS_CODE_UDP_IPV6;
7003                 break;
7004         case AH_V6_FLOW:
7005         case ESP_V6_FLOW:
7006                 *class = CLASS_CODE_AH_ESP_IPV6;
7007                 break;
7008         case SCTP_V6_FLOW:
7009                 *class = CLASS_CODE_SCTP_IPV6;
7010                 break;
7011         default:
7012                 return 0;
7013         }
7014
7015         return 1;
7016 }
7017
7018 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7019 {
7020         u64 ethflow = 0;
7021
7022         if (flow_key & FLOW_KEY_L2DA)
7023                 ethflow |= RXH_L2DA;
7024         if (flow_key & FLOW_KEY_VLAN)
7025                 ethflow |= RXH_VLAN;
7026         if (flow_key & FLOW_KEY_IPSA)
7027                 ethflow |= RXH_IP_SRC;
7028         if (flow_key & FLOW_KEY_IPDA)
7029                 ethflow |= RXH_IP_DST;
7030         if (flow_key & FLOW_KEY_PROTO)
7031                 ethflow |= RXH_L3_PROTO;
7032         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7033                 ethflow |= RXH_L4_B_0_1;
7034         if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7035                 ethflow |= RXH_L4_B_2_3;
7036
7037         return ethflow;
7038
7039 }
7040
7041 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7042 {
7043         u64 key = 0;
7044
7045         if (ethflow & RXH_L2DA)
7046                 key |= FLOW_KEY_L2DA;
7047         if (ethflow & RXH_VLAN)
7048                 key |= FLOW_KEY_VLAN;
7049         if (ethflow & RXH_IP_SRC)
7050                 key |= FLOW_KEY_IPSA;
7051         if (ethflow & RXH_IP_DST)
7052                 key |= FLOW_KEY_IPDA;
7053         if (ethflow & RXH_L3_PROTO)
7054                 key |= FLOW_KEY_PROTO;
7055         if (ethflow & RXH_L4_B_0_1)
7056                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7057         if (ethflow & RXH_L4_B_2_3)
7058                 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7059
7060         *flow_key = key;
7061
7062         return 1;
7063
7064 }
7065
7066 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7067 {
7068         u64 class;
7069
7070         nfc->data = 0;
7071
7072         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7073                 return -EINVAL;
7074
7075         if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7076             TCAM_KEY_DISC)
7077                 nfc->data = RXH_DISCARD;
7078         else
7079                 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7080                                                       CLASS_CODE_USER_PROG1]);
7081         return 0;
7082 }
7083
7084 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7085                                         struct ethtool_rx_flow_spec *fsp)
7086 {
7087
7088         fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7089                 TCAM_V4KEY3_SADDR_SHIFT;
7090         fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7091                 TCAM_V4KEY3_DADDR_SHIFT;
7092         fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7093                 TCAM_V4KEY3_SADDR_SHIFT;
7094         fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7095                 TCAM_V4KEY3_DADDR_SHIFT;
7096
7097         fsp->h_u.tcp_ip4_spec.ip4src =
7098                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7099         fsp->m_u.tcp_ip4_spec.ip4src =
7100                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7101         fsp->h_u.tcp_ip4_spec.ip4dst =
7102                 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7103         fsp->m_u.tcp_ip4_spec.ip4dst =
7104                 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7105
7106         fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7107                 TCAM_V4KEY2_TOS_SHIFT;
7108         fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7109                 TCAM_V4KEY2_TOS_SHIFT;
7110
7111         switch (fsp->flow_type) {
7112         case TCP_V4_FLOW:
7113         case UDP_V4_FLOW:
7114         case SCTP_V4_FLOW:
7115                 fsp->h_u.tcp_ip4_spec.psrc =
7116                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7117                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7118                 fsp->h_u.tcp_ip4_spec.pdst =
7119                         ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7120                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7121                 fsp->m_u.tcp_ip4_spec.psrc =
7122                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7123                          TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7124                 fsp->m_u.tcp_ip4_spec.pdst =
7125                         ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7126                          TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7127
7128                 fsp->h_u.tcp_ip4_spec.psrc =
7129                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7130                 fsp->h_u.tcp_ip4_spec.pdst =
7131                         cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7132                 fsp->m_u.tcp_ip4_spec.psrc =
7133                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7134                 fsp->m_u.tcp_ip4_spec.pdst =
7135                         cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7136                 break;
7137         case AH_V4_FLOW:
7138         case ESP_V4_FLOW:
7139                 fsp->h_u.ah_ip4_spec.spi =
7140                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7141                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7142                 fsp->m_u.ah_ip4_spec.spi =
7143                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7144                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7145
7146                 fsp->h_u.ah_ip4_spec.spi =
7147                         cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7148                 fsp->m_u.ah_ip4_spec.spi =
7149                         cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7150                 break;
7151         case IP_USER_FLOW:
7152                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7153                         (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7154                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7155                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7156                         (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7157                         TCAM_V4KEY2_PORT_SPI_SHIFT;
7158
7159                 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7160                         cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7161                 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7162                         cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7163
7164                 fsp->h_u.usr_ip4_spec.proto =
7165                         (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7166                         TCAM_V4KEY2_PROTO_SHIFT;
7167                 fsp->m_u.usr_ip4_spec.proto =
7168                         (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7169                         TCAM_V4KEY2_PROTO_SHIFT;
7170
7171                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7172                 break;
7173         default:
7174                 break;
7175         }
7176 }
7177
7178 static int niu_get_ethtool_tcam_entry(struct niu *np,
7179                                       struct ethtool_rxnfc *nfc)
7180 {
7181         struct niu_parent *parent = np->parent;
7182         struct niu_tcam_entry *tp;
7183         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7184         u16 idx;
7185         u64 class;
7186         int ret = 0;
7187
7188         idx = tcam_get_index(np, (u16)nfc->fs.location);
7189
7190         tp = &parent->tcam[idx];
7191         if (!tp->valid) {
7192                 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7193                             parent->index, (u16)nfc->fs.location, idx);
7194                 return -EINVAL;
7195         }
7196
7197         /* fill the flow spec entry */
7198         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7199                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7200         ret = niu_class_to_ethflow(class, &fsp->flow_type);
7201
7202         if (ret < 0) {
7203                 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7204                             parent->index);
7205                 ret = -EINVAL;
7206                 goto out;
7207         }
7208
7209         if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7210                 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7211                         TCAM_V4KEY2_PROTO_SHIFT;
7212                 if (proto == IPPROTO_ESP) {
7213                         if (fsp->flow_type == AH_V4_FLOW)
7214                                 fsp->flow_type = ESP_V4_FLOW;
7215                         else
7216                                 fsp->flow_type = ESP_V6_FLOW;
7217                 }
7218         }
7219
7220         switch (fsp->flow_type) {
7221         case TCP_V4_FLOW:
7222         case UDP_V4_FLOW:
7223         case SCTP_V4_FLOW:
7224         case AH_V4_FLOW:
7225         case ESP_V4_FLOW:
7226                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7227                 break;
7228         case TCP_V6_FLOW:
7229         case UDP_V6_FLOW:
7230         case SCTP_V6_FLOW:
7231         case AH_V6_FLOW:
7232         case ESP_V6_FLOW:
7233                 /* Not yet implemented */
7234                 ret = -EINVAL;
7235                 break;
7236         case IP_USER_FLOW:
7237                 niu_get_ip4fs_from_tcam_key(tp, fsp);
7238                 break;
7239         default:
7240                 ret = -EINVAL;
7241                 break;
7242         }
7243
7244         if (ret < 0)
7245                 goto out;
7246
7247         if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7248                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7249         else
7250                 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7251                         TCAM_ASSOCDATA_OFFSET_SHIFT;
7252
7253         /* put the tcam size here */
7254         nfc->data = tcam_get_size(np);
7255 out:
7256         return ret;
7257 }
7258
7259 static int niu_get_ethtool_tcam_all(struct niu *np,
7260                                     struct ethtool_rxnfc *nfc,
7261                                     u32 *rule_locs)
7262 {
7263         struct niu_parent *parent = np->parent;
7264         struct niu_tcam_entry *tp;
7265         int i, idx, cnt;
7266         u16 n_entries;
7267         unsigned long flags;
7268
7269
7270         /* put the tcam size here */
7271         nfc->data = tcam_get_size(np);
7272
7273         niu_lock_parent(np, flags);
7274         n_entries = nfc->rule_cnt;
7275         for (cnt = 0, i = 0; i < nfc->data; i++) {
7276                 idx = tcam_get_index(np, i);
7277                 tp = &parent->tcam[idx];
7278                 if (!tp->valid)
7279                         continue;
7280                 rule_locs[cnt] = i;
7281                 cnt++;
7282         }
7283         niu_unlock_parent(np, flags);
7284
7285         if (n_entries != cnt) {
7286                 /* print warning, this should not happen */
7287                 netdev_info(np->dev, "niu%d: In %s(): n_entries[%d] != cnt[%d]!!!\n",
7288                             np->parent->index, __func__, n_entries, cnt);
7289         }
7290
7291         return 0;
7292 }
7293
7294 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7295                        void *rule_locs)
7296 {
7297         struct niu *np = netdev_priv(dev);
7298         int ret = 0;
7299
7300         switch (cmd->cmd) {
7301         case ETHTOOL_GRXFH:
7302                 ret = niu_get_hash_opts(np, cmd);
7303                 break;
7304         case ETHTOOL_GRXRINGS:
7305                 cmd->data = np->num_rx_rings;
7306                 break;
7307         case ETHTOOL_GRXCLSRLCNT:
7308                 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7309                 break;
7310         case ETHTOOL_GRXCLSRULE:
7311                 ret = niu_get_ethtool_tcam_entry(np, cmd);
7312                 break;
7313         case ETHTOOL_GRXCLSRLALL:
7314                 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7315                 break;
7316         default:
7317                 ret = -EINVAL;
7318                 break;
7319         }
7320
7321         return ret;
7322 }
7323
7324 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7325 {
7326         u64 class;
7327         u64 flow_key = 0;
7328         unsigned long flags;
7329
7330         if (!niu_ethflow_to_class(nfc->flow_type, &class))
7331                 return -EINVAL;
7332
7333         if (class < CLASS_CODE_USER_PROG1 ||
7334             class > CLASS_CODE_SCTP_IPV6)
7335                 return -EINVAL;
7336
7337         if (nfc->data & RXH_DISCARD) {
7338                 niu_lock_parent(np, flags);
7339                 flow_key = np->parent->tcam_key[class -
7340                                                CLASS_CODE_USER_PROG1];
7341                 flow_key |= TCAM_KEY_DISC;
7342                 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7343                 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7344                 niu_unlock_parent(np, flags);
7345                 return 0;
7346         } else {
7347                 /* Discard was set before, but is not set now */
7348                 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7349                     TCAM_KEY_DISC) {
7350                         niu_lock_parent(np, flags);
7351                         flow_key = np->parent->tcam_key[class -
7352                                                CLASS_CODE_USER_PROG1];
7353                         flow_key &= ~TCAM_KEY_DISC;
7354                         nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7355                              flow_key);
7356                         np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7357                                 flow_key;
7358                         niu_unlock_parent(np, flags);
7359                 }
7360         }
7361
7362         if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7363                 return -EINVAL;
7364
7365         niu_lock_parent(np, flags);
7366         nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7367         np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7368         niu_unlock_parent(np, flags);
7369
7370         return 0;
7371 }
7372
7373 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7374                                        struct niu_tcam_entry *tp,
7375                                        int l2_rdc_tab, u64 class)
7376 {
7377         u8 pid = 0;
7378         u32 sip, dip, sipm, dipm, spi, spim;
7379         u16 sport, dport, spm, dpm;
7380
7381         sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7382         sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7383         dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7384         dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7385
7386         tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7387         tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7388         tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7389         tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7390
7391         tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7392         tp->key[3] |= dip;
7393
7394         tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7395         tp->key_mask[3] |= dipm;
7396
7397         tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7398                        TCAM_V4KEY2_TOS_SHIFT);
7399         tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7400                             TCAM_V4KEY2_TOS_SHIFT);
7401         switch (fsp->flow_type) {
7402         case TCP_V4_FLOW:
7403         case UDP_V4_FLOW:
7404         case SCTP_V4_FLOW:
7405                 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7406                 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7407                 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7408                 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7409
7410                 tp->key[2] |= (((u64)sport << 16) | dport);
7411                 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7412                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7413                 break;
7414         case AH_V4_FLOW:
7415         case ESP_V4_FLOW:
7416                 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7417                 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7418
7419                 tp->key[2] |= spi;
7420                 tp->key_mask[2] |= spim;
7421                 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7422                 break;
7423         case IP_USER_FLOW:
7424                 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7425                 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7426
7427                 tp->key[2] |= spi;
7428                 tp->key_mask[2] |= spim;
7429                 pid = fsp->h_u.usr_ip4_spec.proto;
7430                 break;
7431         default:
7432                 break;
7433         }
7434
7435         tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7436         if (pid) {
7437                 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7438         }
7439 }
7440
7441 static int niu_add_ethtool_tcam_entry(struct niu *np,
7442                                       struct ethtool_rxnfc *nfc)
7443 {
7444         struct niu_parent *parent = np->parent;
7445         struct niu_tcam_entry *tp;
7446         struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7447         struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7448         int l2_rdc_table = rdc_table->first_table_num;
7449         u16 idx;
7450         u64 class;
7451         unsigned long flags;
7452         int err, ret;
7453
7454         ret = 0;
7455
7456         idx = nfc->fs.location;
7457         if (idx >= tcam_get_size(np))
7458                 return -EINVAL;
7459
7460         if (fsp->flow_type == IP_USER_FLOW) {
7461                 int i;
7462                 int add_usr_cls = 0;
7463                 int ipv6 = 0;
7464                 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7465                 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7466
7467                 niu_lock_parent(np, flags);
7468
7469                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7470                         if (parent->l3_cls[i]) {
7471                                 if (uspec->proto == parent->l3_cls_pid[i]) {
7472                                         class = parent->l3_cls[i];
7473                                         parent->l3_cls_refcnt[i]++;
7474                                         add_usr_cls = 1;
7475                                         break;
7476                                 }
7477                         } else {
7478                                 /* Program new user IP class */
7479                                 switch (i) {
7480                                 case 0:
7481                                         class = CLASS_CODE_USER_PROG1;
7482                                         break;
7483                                 case 1:
7484                                         class = CLASS_CODE_USER_PROG2;
7485                                         break;
7486                                 case 2:
7487                                         class = CLASS_CODE_USER_PROG3;
7488                                         break;
7489                                 case 3:
7490                                         class = CLASS_CODE_USER_PROG4;
7491                                         break;
7492                                 default:
7493                                         break;
7494                                 }
7495                                 if (uspec->ip_ver == ETH_RX_NFC_IP6)
7496                                         ipv6 = 1;
7497                                 ret = tcam_user_ip_class_set(np, class, ipv6,
7498                                                              uspec->proto,
7499                                                              uspec->tos,
7500                                                              umask->tos);
7501                                 if (ret)
7502                                         goto out;
7503
7504                                 ret = tcam_user_ip_class_enable(np, class, 1);
7505                                 if (ret)
7506                                         goto out;
7507                                 parent->l3_cls[i] = class;
7508                                 parent->l3_cls_pid[i] = uspec->proto;
7509                                 parent->l3_cls_refcnt[i]++;
7510                                 add_usr_cls = 1;
7511                                 break;
7512                         }
7513                 }
7514                 if (!add_usr_cls) {
7515                         netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7516                                     parent->index, __func__, uspec->proto);
7517                         ret = -EINVAL;
7518                         goto out;
7519                 }
7520                 niu_unlock_parent(np, flags);
7521         } else {
7522                 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7523                         return -EINVAL;
7524                 }
7525         }
7526
7527         niu_lock_parent(np, flags);
7528
7529         idx = tcam_get_index(np, idx);
7530         tp = &parent->tcam[idx];
7531
7532         memset(tp, 0, sizeof(*tp));
7533
7534         /* fill in the tcam key and mask */
7535         switch (fsp->flow_type) {
7536         case TCP_V4_FLOW:
7537         case UDP_V4_FLOW:
7538         case SCTP_V4_FLOW:
7539         case AH_V4_FLOW:
7540         case ESP_V4_FLOW:
7541                 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7542                 break;
7543         case TCP_V6_FLOW:
7544         case UDP_V6_FLOW:
7545         case SCTP_V6_FLOW:
7546         case AH_V6_FLOW:
7547         case ESP_V6_FLOW:
7548                 /* Not yet implemented */
7549                 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7550                             parent->index, __func__, fsp->flow_type);
7551                 ret = -EINVAL;
7552                 goto out;
7553         case IP_USER_FLOW:
7554                 if (fsp->h_u.usr_ip4_spec.ip_ver == ETH_RX_NFC_IP4) {
7555                         niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table,
7556                                                    class);
7557                 } else {
7558                         /* Not yet implemented */
7559                         netdev_info(np->dev, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
7560                                     parent->index, __func__);
7561                         ret = -EINVAL;
7562                         goto out;
7563                 }
7564                 break;
7565         default:
7566                 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7567                             parent->index, __func__, fsp->flow_type);
7568                 ret = -EINVAL;
7569                 goto out;
7570         }
7571
7572         /* fill in the assoc data */
7573         if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7574                 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7575         } else {
7576                 if (fsp->ring_cookie >= np->num_rx_rings) {
7577                         netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7578                                     parent->index, __func__,
7579                                     (long long)fsp->ring_cookie);
7580                         ret = -EINVAL;
7581                         goto out;
7582                 }
7583                 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7584                                   (fsp->ring_cookie <<
7585                                    TCAM_ASSOCDATA_OFFSET_SHIFT));
7586         }
7587
7588         err = tcam_write(np, idx, tp->key, tp->key_mask);
7589         if (err) {
7590                 ret = -EINVAL;
7591                 goto out;
7592         }
7593         err = tcam_assoc_write(np, idx, tp->assoc_data);
7594         if (err) {
7595                 ret = -EINVAL;
7596                 goto out;
7597         }
7598
7599         /* validate the entry */
7600         tp->valid = 1;
7601         np->clas.tcam_valid_entries++;
7602 out:
7603         niu_unlock_parent(np, flags);
7604
7605         return ret;
7606 }
7607
7608 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7609 {
7610         struct niu_parent *parent = np->parent;
7611         struct niu_tcam_entry *tp;
7612         u16 idx;
7613         unsigned long flags;
7614         u64 class;
7615         int ret = 0;
7616
7617         if (loc >= tcam_get_size(np))
7618                 return -EINVAL;
7619
7620         niu_lock_parent(np, flags);
7621
7622         idx = tcam_get_index(np, loc);
7623         tp = &parent->tcam[idx];
7624
7625         /* if the entry is of a user defined class, then update*/
7626         class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7627                 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7628
7629         if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7630                 int i;
7631                 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7632                         if (parent->l3_cls[i] == class) {
7633                                 parent->l3_cls_refcnt[i]--;
7634                                 if (!parent->l3_cls_refcnt[i]) {
7635                                         /* disable class */
7636                                         ret = tcam_user_ip_class_enable(np,
7637                                                                         class,
7638                                                                         0);
7639                                         if (ret)
7640                                                 goto out;
7641                                         parent->l3_cls[i] = 0;
7642                                         parent->l3_cls_pid[i] = 0;
7643                                 }
7644                                 break;
7645                         }
7646                 }
7647                 if (i == NIU_L3_PROG_CLS) {
7648                         netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7649                                     parent->index, __func__,
7650                                     (unsigned long long)class);
7651                         ret = -EINVAL;
7652                         goto out;
7653                 }
7654         }
7655
7656         ret = tcam_flush(np, idx);
7657         if (ret)
7658                 goto out;
7659
7660         /* invalidate the entry */
7661         tp->valid = 0;
7662         np->clas.tcam_valid_entries--;
7663 out:
7664         niu_unlock_parent(np, flags);
7665
7666         return ret;
7667 }
7668
7669 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7670 {
7671         struct niu *np = netdev_priv(dev);
7672         int ret = 0;
7673
7674         switch (cmd->cmd) {
7675         case ETHTOOL_SRXFH:
7676                 ret = niu_set_hash_opts(np, cmd);
7677                 break;
7678         case ETHTOOL_SRXCLSRLINS:
7679                 ret = niu_add_ethtool_tcam_entry(np, cmd);
7680                 break;
7681         case ETHTOOL_SRXCLSRLDEL:
7682                 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7683                 break;
7684         default:
7685                 ret = -EINVAL;
7686                 break;
7687         }
7688
7689         return ret;
7690 }
7691
7692 static const struct {
7693         const char string[ETH_GSTRING_LEN];
7694 } niu_xmac_stat_keys[] = {
7695         { "tx_frames" },
7696         { "tx_bytes" },
7697         { "tx_fifo_errors" },
7698         { "tx_overflow_errors" },
7699         { "tx_max_pkt_size_errors" },
7700         { "tx_underflow_errors" },
7701         { "rx_local_faults" },
7702         { "rx_remote_faults" },
7703         { "rx_link_faults" },
7704         { "rx_align_errors" },
7705         { "rx_frags" },
7706         { "rx_mcasts" },
7707         { "rx_bcasts" },
7708         { "rx_hist_cnt1" },
7709         { "rx_hist_cnt2" },
7710         { "rx_hist_cnt3" },
7711         { "rx_hist_cnt4" },
7712         { "rx_hist_cnt5" },
7713         { "rx_hist_cnt6" },
7714         { "rx_hist_cnt7" },
7715         { "rx_octets" },
7716         { "rx_code_violations" },
7717         { "rx_len_errors" },
7718         { "rx_crc_errors" },
7719         { "rx_underflows" },
7720         { "rx_overflows" },
7721         { "pause_off_state" },
7722         { "pause_on_state" },
7723         { "pause_received" },
7724 };
7725
7726 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
7727
7728 static const struct {
7729         const char string[ETH_GSTRING_LEN];
7730 } niu_bmac_stat_keys[] = {
7731         { "tx_underflow_errors" },
7732         { "tx_max_pkt_size_errors" },
7733         { "tx_bytes" },
7734         { "tx_frames" },
7735         { "rx_overflows" },
7736         { "rx_frames" },
7737         { "rx_align_errors" },
7738         { "rx_crc_errors" },
7739         { "rx_len_errors" },
7740         { "pause_off_state" },
7741         { "pause_on_state" },
7742         { "pause_received" },
7743 };
7744
7745 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
7746
7747 static const struct {
7748         const char string[ETH_GSTRING_LEN];
7749 } niu_rxchan_stat_keys[] = {
7750         { "rx_channel" },
7751         { "rx_packets" },
7752         { "rx_bytes" },
7753         { "rx_dropped" },
7754         { "rx_errors" },
7755 };
7756
7757 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
7758
7759 static const struct {
7760         const char string[ETH_GSTRING_LEN];
7761 } niu_txchan_stat_keys[] = {
7762         { "tx_channel" },
7763         { "tx_packets" },
7764         { "tx_bytes" },
7765         { "tx_errors" },
7766 };
7767
7768 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
7769
7770 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7771 {
7772         struct niu *np = netdev_priv(dev);
7773         int i;
7774
7775         if (stringset != ETH_SS_STATS)
7776                 return;
7777
7778         if (np->flags & NIU_FLAGS_XMAC) {
7779                 memcpy(data, niu_xmac_stat_keys,
7780                        sizeof(niu_xmac_stat_keys));
7781                 data += sizeof(niu_xmac_stat_keys);
7782         } else {
7783                 memcpy(data, niu_bmac_stat_keys,
7784                        sizeof(niu_bmac_stat_keys));
7785                 data += sizeof(niu_bmac_stat_keys);
7786         }
7787         for (i = 0; i < np->num_rx_rings; i++) {
7788                 memcpy(data, niu_rxchan_stat_keys,
7789                        sizeof(niu_rxchan_stat_keys));
7790                 data += sizeof(niu_rxchan_stat_keys);
7791         }
7792         for (i = 0; i < np->num_tx_rings; i++) {
7793                 memcpy(data, niu_txchan_stat_keys,
7794                        sizeof(niu_txchan_stat_keys));
7795                 data += sizeof(niu_txchan_stat_keys);
7796         }
7797 }
7798
7799 static int niu_get_sset_count(struct net_device *dev, int stringset)
7800 {
7801         struct niu *np = netdev_priv(dev);
7802
7803         if (stringset != ETH_SS_STATS)
7804                 return -EINVAL;
7805
7806         return ((np->flags & NIU_FLAGS_XMAC ?
7807                  NUM_XMAC_STAT_KEYS :
7808                  NUM_BMAC_STAT_KEYS) +
7809                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7810                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7811 }
7812
7813 static void niu_get_ethtool_stats(struct net_device *dev,
7814                                   struct ethtool_stats *stats, u64 *data)
7815 {
7816         struct niu *np = netdev_priv(dev);
7817         int i;
7818
7819         niu_sync_mac_stats(np);
7820         if (np->flags & NIU_FLAGS_XMAC) {
7821                 memcpy(data, &np->mac_stats.xmac,
7822                        sizeof(struct niu_xmac_stats));
7823                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7824         } else {
7825                 memcpy(data, &np->mac_stats.bmac,
7826                        sizeof(struct niu_bmac_stats));
7827                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7828         }
7829         for (i = 0; i < np->num_rx_rings; i++) {
7830                 struct rx_ring_info *rp = &np->rx_rings[i];
7831
7832                 niu_sync_rx_discard_stats(np, rp, 0);
7833
7834                 data[0] = rp->rx_channel;
7835                 data[1] = rp->rx_packets;
7836                 data[2] = rp->rx_bytes;
7837                 data[3] = rp->rx_dropped;
7838                 data[4] = rp->rx_errors;
7839                 data += 5;
7840         }
7841         for (i = 0; i < np->num_tx_rings; i++) {
7842                 struct tx_ring_info *rp = &np->tx_rings[i];
7843
7844                 data[0] = rp->tx_channel;
7845                 data[1] = rp->tx_packets;
7846                 data[2] = rp->tx_bytes;
7847                 data[3] = rp->tx_errors;
7848                 data += 4;
7849         }
7850 }
7851
7852 static u64 niu_led_state_save(struct niu *np)
7853 {
7854         if (np->flags & NIU_FLAGS_XMAC)
7855                 return nr64_mac(XMAC_CONFIG);
7856         else
7857                 return nr64_mac(BMAC_XIF_CONFIG);
7858 }
7859
7860 static void niu_led_state_restore(struct niu *np, u64 val)
7861 {
7862         if (np->flags & NIU_FLAGS_XMAC)
7863                 nw64_mac(XMAC_CONFIG, val);
7864         else
7865                 nw64_mac(BMAC_XIF_CONFIG, val);
7866 }
7867
7868 static void niu_force_led(struct niu *np, int on)
7869 {
7870         u64 val, reg, bit;
7871
7872         if (np->flags & NIU_FLAGS_XMAC) {
7873                 reg = XMAC_CONFIG;
7874                 bit = XMAC_CONFIG_FORCE_LED_ON;
7875         } else {
7876                 reg = BMAC_XIF_CONFIG;
7877                 bit = BMAC_XIF_CONFIG_LINK_LED;
7878         }
7879
7880         val = nr64_mac(reg);
7881         if (on)
7882                 val |= bit;
7883         else
7884                 val &= ~bit;
7885         nw64_mac(reg, val);
7886 }
7887
7888 static int niu_phys_id(struct net_device *dev, u32 data)
7889 {
7890         struct niu *np = netdev_priv(dev);
7891         u64 orig_led_state;
7892         int i;
7893
7894         if (!netif_running(dev))
7895                 return -EAGAIN;
7896
7897         if (data == 0)
7898                 data = 2;
7899
7900         orig_led_state = niu_led_state_save(np);
7901         for (i = 0; i < (data * 2); i++) {
7902                 int on = ((i % 2) == 0);
7903
7904                 niu_force_led(np, on);
7905
7906                 if (msleep_interruptible(500))
7907                         break;
7908         }
7909         niu_led_state_restore(np, orig_led_state);
7910
7911         return 0;
7912 }
7913
7914 static const struct ethtool_ops niu_ethtool_ops = {
7915         .get_drvinfo            = niu_get_drvinfo,
7916         .get_link               = ethtool_op_get_link,
7917         .get_msglevel           = niu_get_msglevel,
7918         .set_msglevel           = niu_set_msglevel,
7919         .nway_reset             = niu_nway_reset,
7920         .get_eeprom_len         = niu_get_eeprom_len,
7921         .get_eeprom             = niu_get_eeprom,
7922         .get_settings           = niu_get_settings,
7923         .set_settings           = niu_set_settings,
7924         .get_strings            = niu_get_strings,
7925         .get_sset_count         = niu_get_sset_count,
7926         .get_ethtool_stats      = niu_get_ethtool_stats,
7927         .phys_id                = niu_phys_id,
7928         .get_rxnfc              = niu_get_nfc,
7929         .set_rxnfc              = niu_set_nfc,
7930 };
7931
7932 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7933                               int ldg, int ldn)
7934 {
7935         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7936                 return -EINVAL;
7937         if (ldn < 0 || ldn > LDN_MAX)
7938                 return -EINVAL;
7939
7940         parent->ldg_map[ldn] = ldg;
7941
7942         if (np->parent->plat_type == PLAT_TYPE_NIU) {
7943                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7944                  * the firmware, and we're not supposed to change them.
7945                  * Validate the mapping, because if it's wrong we probably
7946                  * won't get any interrupts and that's painful to debug.
7947                  */
7948                 if (nr64(LDG_NUM(ldn)) != ldg) {
7949                         dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7950                                 np->port, ldn, ldg,
7951                                 (unsigned long long) nr64(LDG_NUM(ldn)));
7952                         return -EINVAL;
7953                 }
7954         } else
7955                 nw64(LDG_NUM(ldn), ldg);
7956
7957         return 0;
7958 }
7959
7960 static int niu_set_ldg_timer_res(struct niu *np, int res)
7961 {
7962         if (res < 0 || res > LDG_TIMER_RES_VAL)
7963                 return -EINVAL;
7964
7965
7966         nw64(LDG_TIMER_RES, res);
7967
7968         return 0;
7969 }
7970
7971 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7972 {
7973         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7974             (func < 0 || func > 3) ||
7975             (vector < 0 || vector > 0x1f))
7976                 return -EINVAL;
7977
7978         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7979
7980         return 0;
7981 }
7982
7983 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7984 {
7985         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7986                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7987         int limit;
7988
7989         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7990                 return -EINVAL;
7991
7992         frame = frame_base;
7993         nw64(ESPC_PIO_STAT, frame);
7994         limit = 64;
7995         do {
7996                 udelay(5);
7997                 frame = nr64(ESPC_PIO_STAT);
7998                 if (frame & ESPC_PIO_STAT_READ_END)
7999                         break;
8000         } while (limit--);
8001         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8002                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8003                         (unsigned long long) frame);
8004                 return -ENODEV;
8005         }
8006
8007         frame = frame_base;
8008         nw64(ESPC_PIO_STAT, frame);
8009         limit = 64;
8010         do {
8011                 udelay(5);
8012                 frame = nr64(ESPC_PIO_STAT);
8013                 if (frame & ESPC_PIO_STAT_READ_END)
8014                         break;
8015         } while (limit--);
8016         if (!(frame & ESPC_PIO_STAT_READ_END)) {
8017                 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8018                         (unsigned long long) frame);
8019                 return -ENODEV;
8020         }
8021
8022         frame = nr64(ESPC_PIO_STAT);
8023         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8024 }
8025
8026 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8027 {
8028         int err = niu_pci_eeprom_read(np, off);
8029         u16 val;
8030
8031         if (err < 0)
8032                 return err;
8033         val = (err << 8);
8034         err = niu_pci_eeprom_read(np, off + 1);
8035         if (err < 0)
8036                 return err;
8037         val |= (err & 0xff);
8038
8039         return val;
8040 }
8041
8042 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8043 {
8044         int err = niu_pci_eeprom_read(np, off);
8045         u16 val;
8046
8047         if (err < 0)
8048                 return err;
8049
8050         val = (err & 0xff);
8051         err = niu_pci_eeprom_read(np, off + 1);
8052         if (err < 0)
8053                 return err;
8054
8055         val |= (err & 0xff) << 8;
8056
8057         return val;
8058 }
8059
8060 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8061                                               u32 off,
8062                                               char *namebuf,
8063                                               int namebuf_len)
8064 {
8065         int i;
8066
8067         for (i = 0; i < namebuf_len; i++) {
8068                 int err = niu_pci_eeprom_read(np, off + i);
8069                 if (err < 0)
8070                         return err;
8071                 *namebuf++ = err;
8072                 if (!err)
8073                         break;
8074         }
8075         if (i >= namebuf_len)
8076                 return -EINVAL;
8077
8078         return i + 1;
8079 }
8080
8081 static void __devinit niu_vpd_parse_version(struct niu *np)
8082 {
8083         struct niu_vpd *vpd = &np->vpd;
8084         int len = strlen(vpd->version) + 1;
8085         const char *s = vpd->version;
8086         int i;
8087
8088         for (i = 0; i < len - 5; i++) {
8089                 if (!strncmp(s + i, "FCode ", 6))
8090                         break;
8091         }
8092         if (i >= len - 5)
8093                 return;
8094
8095         s += i + 5;
8096         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8097
8098         netif_printk(np, probe, KERN_DEBUG, np->dev,
8099                      "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8100                      vpd->fcode_major, vpd->fcode_minor);
8101         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8102             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8103              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8104                 np->flags |= NIU_FLAGS_VPD_VALID;
8105 }
8106
8107 /* ESPC_PIO_EN_ENABLE must be set */
8108 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8109                                             u32 start, u32 end)
8110 {
8111         unsigned int found_mask = 0;
8112 #define FOUND_MASK_MODEL        0x00000001
8113 #define FOUND_MASK_BMODEL       0x00000002
8114 #define FOUND_MASK_VERS         0x00000004
8115 #define FOUND_MASK_MAC          0x00000008
8116 #define FOUND_MASK_NMAC         0x00000010
8117 #define FOUND_MASK_PHY          0x00000020
8118 #define FOUND_MASK_ALL          0x0000003f
8119
8120         netif_printk(np, probe, KERN_DEBUG, np->dev,
8121                      "VPD_SCAN: start[%x] end[%x]\n", start, end);
8122         while (start < end) {
8123                 int len, err, instance, type, prop_len;
8124                 char namebuf[64];
8125                 u8 *prop_buf;
8126                 int max_len;
8127
8128                 if (found_mask == FOUND_MASK_ALL) {
8129                         niu_vpd_parse_version(np);
8130                         return 1;
8131                 }
8132
8133                 err = niu_pci_eeprom_read(np, start + 2);
8134                 if (err < 0)
8135                         return err;
8136                 len = err;
8137                 start += 3;
8138
8139                 instance = niu_pci_eeprom_read(np, start);
8140                 type = niu_pci_eeprom_read(np, start + 3);
8141                 prop_len = niu_pci_eeprom_read(np, start + 4);
8142                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8143                 if (err < 0)
8144                         return err;
8145
8146                 prop_buf = NULL;
8147                 max_len = 0;
8148                 if (!strcmp(namebuf, "model")) {
8149                         prop_buf = np->vpd.model;
8150                         max_len = NIU_VPD_MODEL_MAX;
8151                         found_mask |= FOUND_MASK_MODEL;
8152                 } else if (!strcmp(namebuf, "board-model")) {
8153                         prop_buf = np->vpd.board_model;
8154                         max_len = NIU_VPD_BD_MODEL_MAX;
8155                         found_mask |= FOUND_MASK_BMODEL;
8156                 } else if (!strcmp(namebuf, "version")) {
8157                         prop_buf = np->vpd.version;
8158                         max_len = NIU_VPD_VERSION_MAX;
8159                         found_mask |= FOUND_MASK_VERS;
8160                 } else if (!strcmp(namebuf, "local-mac-address")) {
8161                         prop_buf = np->vpd.local_mac;
8162                         max_len = ETH_ALEN;
8163                         found_mask |= FOUND_MASK_MAC;
8164                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8165                         prop_buf = &np->vpd.mac_num;
8166                         max_len = 1;
8167                         found_mask |= FOUND_MASK_NMAC;
8168                 } else if (!strcmp(namebuf, "phy-type")) {
8169                         prop_buf = np->vpd.phy_type;
8170                         max_len = NIU_VPD_PHY_TYPE_MAX;
8171                         found_mask |= FOUND_MASK_PHY;
8172                 }
8173
8174                 if (max_len && prop_len > max_len) {
8175                         dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8176                         return -EINVAL;
8177                 }
8178
8179                 if (prop_buf) {
8180                         u32 off = start + 5 + err;
8181                         int i;
8182
8183                         netif_printk(np, probe, KERN_DEBUG, np->dev,
8184                                      "VPD_SCAN: Reading in property [%s] len[%d]\n",
8185                                      namebuf, prop_len);
8186                         for (i = 0; i < prop_len; i++)
8187                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8188                 }
8189
8190                 start += len;
8191         }
8192
8193         return 0;
8194 }
8195
8196 /* ESPC_PIO_EN_ENABLE must be set */
8197 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8198 {
8199         u32 offset;
8200         int err;
8201
8202         err = niu_pci_eeprom_read16_swp(np, start + 1);
8203         if (err < 0)
8204                 return;
8205
8206         offset = err + 3;
8207
8208         while (start + offset < ESPC_EEPROM_SIZE) {
8209                 u32 here = start + offset;
8210                 u32 end;
8211
8212                 err = niu_pci_eeprom_read(np, here);
8213                 if (err != 0x90)
8214                         return;
8215
8216                 err = niu_pci_eeprom_read16_swp(np, here + 1);
8217                 if (err < 0)
8218                         return;
8219
8220                 here = start + offset + 3;
8221                 end = start + offset + err;
8222
8223                 offset += err;
8224
8225                 err = niu_pci_vpd_scan_props(np, here, end);
8226                 if (err < 0 || err == 1)
8227                         return;
8228         }
8229 }
8230
8231 /* ESPC_PIO_EN_ENABLE must be set */
8232 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8233 {
8234         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8235         int err;
8236
8237         while (start < end) {
8238                 ret = start;
8239
8240                 /* ROM header signature?  */
8241                 err = niu_pci_eeprom_read16(np, start +  0);
8242                 if (err != 0x55aa)
8243                         return 0;
8244
8245                 /* Apply offset to PCI data structure.  */
8246                 err = niu_pci_eeprom_read16(np, start + 23);
8247                 if (err < 0)
8248                         return 0;
8249                 start += err;
8250
8251                 /* Check for "PCIR" signature.  */
8252                 err = niu_pci_eeprom_read16(np, start +  0);
8253                 if (err != 0x5043)
8254                         return 0;
8255                 err = niu_pci_eeprom_read16(np, start +  2);
8256                 if (err != 0x4952)
8257                         return 0;
8258
8259                 /* Check for OBP image type.  */
8260                 err = niu_pci_eeprom_read(np, start + 20);
8261                 if (err < 0)
8262                         return 0;
8263                 if (err != 0x01) {
8264                         err = niu_pci_eeprom_read(np, ret + 2);
8265                         if (err < 0)
8266                                 return 0;
8267
8268                         start = ret + (err * 512);
8269                         continue;
8270                 }
8271
8272                 err = niu_pci_eeprom_read16_swp(np, start + 8);
8273                 if (err < 0)
8274                         return err;
8275                 ret += err;
8276
8277                 err = niu_pci_eeprom_read(np, ret + 0);
8278                 if (err != 0x82)
8279                         return 0;
8280
8281                 return ret;
8282         }
8283
8284         return 0;
8285 }
8286
8287 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8288                                               const char *phy_prop)
8289 {
8290         if (!strcmp(phy_prop, "mif")) {
8291                 /* 1G copper, MII */
8292                 np->flags &= ~(NIU_FLAGS_FIBER |
8293                                NIU_FLAGS_10G);
8294                 np->mac_xcvr = MAC_XCVR_MII;
8295         } else if (!strcmp(phy_prop, "xgf")) {
8296                 /* 10G fiber, XPCS */
8297                 np->flags |= (NIU_FLAGS_10G |
8298                               NIU_FLAGS_FIBER);
8299                 np->mac_xcvr = MAC_XCVR_XPCS;
8300         } else if (!strcmp(phy_prop, "pcs")) {
8301                 /* 1G fiber, PCS */
8302                 np->flags &= ~NIU_FLAGS_10G;
8303                 np->flags |= NIU_FLAGS_FIBER;
8304                 np->mac_xcvr = MAC_XCVR_PCS;
8305         } else if (!strcmp(phy_prop, "xgc")) {
8306                 /* 10G copper, XPCS */
8307                 np->flags |= NIU_FLAGS_10G;
8308                 np->flags &= ~NIU_FLAGS_FIBER;
8309                 np->mac_xcvr = MAC_XCVR_XPCS;
8310         } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8311                 /* 10G Serdes or 1G Serdes, default to 10G */
8312                 np->flags |= NIU_FLAGS_10G;
8313                 np->flags &= ~NIU_FLAGS_FIBER;
8314                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8315                 np->mac_xcvr = MAC_XCVR_XPCS;
8316         } else {
8317                 return -EINVAL;
8318         }
8319         return 0;
8320 }
8321
8322 static int niu_pci_vpd_get_nports(struct niu *np)
8323 {
8324         int ports = 0;
8325
8326         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8327             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8328             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8329             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8330             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8331                 ports = 4;
8332         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8333                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8334                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8335                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8336                 ports = 2;
8337         }
8338
8339         return ports;
8340 }
8341
8342 static void __devinit niu_pci_vpd_validate(struct niu *np)
8343 {
8344         struct net_device *dev = np->dev;
8345         struct niu_vpd *vpd = &np->vpd;
8346         u8 val8;
8347
8348         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8349                 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8350
8351                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8352                 return;
8353         }
8354
8355         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8356             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8357                 np->flags |= NIU_FLAGS_10G;
8358                 np->flags &= ~NIU_FLAGS_FIBER;
8359                 np->flags |= NIU_FLAGS_XCVR_SERDES;
8360                 np->mac_xcvr = MAC_XCVR_PCS;
8361                 if (np->port > 1) {
8362                         np->flags |= NIU_FLAGS_FIBER;
8363                         np->flags &= ~NIU_FLAGS_10G;
8364                 }
8365                 if (np->flags & NIU_FLAGS_10G)
8366                         np->mac_xcvr = MAC_XCVR_XPCS;
8367         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8368                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8369                               NIU_FLAGS_HOTPLUG_PHY);
8370         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8371                 dev_err(np->device, "Illegal phy string [%s]\n",
8372                         np->vpd.phy_type);
8373                 dev_err(np->device, "Falling back to SPROM\n");
8374                 np->flags &= ~NIU_FLAGS_VPD_VALID;
8375                 return;
8376         }
8377
8378         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8379
8380         val8 = dev->perm_addr[5];
8381         dev->perm_addr[5] += np->port;
8382         if (dev->perm_addr[5] < val8)
8383                 dev->perm_addr[4]++;
8384
8385         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8386 }
8387
8388 static int __devinit niu_pci_probe_sprom(struct niu *np)
8389 {
8390         struct net_device *dev = np->dev;
8391         int len, i;
8392         u64 val, sum;
8393         u8 val8;
8394
8395         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8396         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8397         len = val / 4;
8398
8399         np->eeprom_len = len;
8400
8401         netif_printk(np, probe, KERN_DEBUG, np->dev,
8402                      "SPROM: Image size %llu\n", (unsigned long long)val);
8403
8404         sum = 0;
8405         for (i = 0; i < len; i++) {
8406                 val = nr64(ESPC_NCR(i));
8407                 sum += (val >>  0) & 0xff;
8408                 sum += (val >>  8) & 0xff;
8409                 sum += (val >> 16) & 0xff;
8410                 sum += (val >> 24) & 0xff;
8411         }
8412         netif_printk(np, probe, KERN_DEBUG, np->dev,
8413                      "SPROM: Checksum %x\n", (int)(sum & 0xff));
8414         if ((sum & 0xff) != 0xab) {
8415                 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8416                 return -EINVAL;
8417         }
8418
8419         val = nr64(ESPC_PHY_TYPE);
8420         switch (np->port) {
8421         case 0:
8422                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8423                         ESPC_PHY_TYPE_PORT0_SHIFT;
8424                 break;
8425         case 1:
8426                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8427                         ESPC_PHY_TYPE_PORT1_SHIFT;
8428                 break;
8429         case 2:
8430                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8431                         ESPC_PHY_TYPE_PORT2_SHIFT;
8432                 break;
8433         case 3:
8434                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8435                         ESPC_PHY_TYPE_PORT3_SHIFT;
8436                 break;
8437         default:
8438                 dev_err(np->device, "Bogus port number %u\n",
8439                         np->port);
8440                 return -EINVAL;
8441         }
8442         netif_printk(np, probe, KERN_DEBUG, np->dev,
8443                      "SPROM: PHY type %x\n", val8);
8444
8445         switch (val8) {
8446         case ESPC_PHY_TYPE_1G_COPPER:
8447                 /* 1G copper, MII */
8448                 np->flags &= ~(NIU_FLAGS_FIBER |
8449                                NIU_FLAGS_10G);
8450                 np->mac_xcvr = MAC_XCVR_MII;
8451                 break;
8452
8453         case ESPC_PHY_TYPE_1G_FIBER:
8454                 /* 1G fiber, PCS */
8455                 np->flags &= ~NIU_FLAGS_10G;
8456                 np->flags |= NIU_FLAGS_FIBER;
8457                 np->mac_xcvr = MAC_XCVR_PCS;
8458                 break;
8459
8460         case ESPC_PHY_TYPE_10G_COPPER:
8461                 /* 10G copper, XPCS */
8462                 np->flags |= NIU_FLAGS_10G;
8463                 np->flags &= ~NIU_FLAGS_FIBER;
8464                 np->mac_xcvr = MAC_XCVR_XPCS;
8465                 break;
8466
8467         case ESPC_PHY_TYPE_10G_FIBER:
8468                 /* 10G fiber, XPCS */
8469                 np->flags |= (NIU_FLAGS_10G |
8470                               NIU_FLAGS_FIBER);
8471                 np->mac_xcvr = MAC_XCVR_XPCS;
8472                 break;
8473
8474         default:
8475                 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8476                 return -EINVAL;
8477         }
8478
8479         val = nr64(ESPC_MAC_ADDR0);
8480         netif_printk(np, probe, KERN_DEBUG, np->dev,
8481                      "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8482         dev->perm_addr[0] = (val >>  0) & 0xff;
8483         dev->perm_addr[1] = (val >>  8) & 0xff;
8484         dev->perm_addr[2] = (val >> 16) & 0xff;
8485         dev->perm_addr[3] = (val >> 24) & 0xff;
8486
8487         val = nr64(ESPC_MAC_ADDR1);
8488         netif_printk(np, probe, KERN_DEBUG, np->dev,
8489                      "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8490         dev->perm_addr[4] = (val >>  0) & 0xff;
8491         dev->perm_addr[5] = (val >>  8) & 0xff;
8492
8493         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8494                 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8495                         dev->perm_addr);
8496                 return -EINVAL;
8497         }
8498
8499         val8 = dev->perm_addr[5];
8500         dev->perm_addr[5] += np->port;
8501         if (dev->perm_addr[5] < val8)
8502                 dev->perm_addr[4]++;
8503
8504         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8505
8506         val = nr64(ESPC_MOD_STR_LEN);
8507         netif_printk(np, probe, KERN_DEBUG, np->dev,
8508                      "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8509         if (val >= 8 * 4)
8510                 return -EINVAL;
8511
8512         for (i = 0; i < val; i += 4) {
8513                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8514
8515                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
8516                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
8517                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8518                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8519         }
8520         np->vpd.model[val] = '\0';
8521
8522         val = nr64(ESPC_BD_MOD_STR_LEN);
8523         netif_printk(np, probe, KERN_DEBUG, np->dev,
8524                      "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8525         if (val >= 4 * 4)
8526                 return -EINVAL;
8527
8528         for (i = 0; i < val; i += 4) {
8529                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8530
8531                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
8532                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
8533                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8534                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8535         }
8536         np->vpd.board_model[val] = '\0';
8537
8538         np->vpd.mac_num =
8539                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8540         netif_printk(np, probe, KERN_DEBUG, np->dev,
8541                      "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8542
8543         return 0;
8544 }
8545
8546 static int __devinit niu_get_and_validate_port(struct niu *np)
8547 {
8548         struct niu_parent *parent = np->parent;
8549
8550         if (np->port <= 1)
8551                 np->flags |= NIU_FLAGS_XMAC;
8552
8553         if (!parent->num_ports) {
8554                 if (parent->plat_type == PLAT_TYPE_NIU) {
8555                         parent->num_ports = 2;
8556                 } else {
8557                         parent->num_ports = niu_pci_vpd_get_nports(np);
8558                         if (!parent->num_ports) {
8559                                 /* Fall back to SPROM as last resort.
8560                                  * This will fail on most cards.
8561                                  */
8562                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8563                                         ESPC_NUM_PORTS_MACS_VAL;
8564
8565                                 /* All of the current probing methods fail on
8566                                  * Maramba on-board parts.
8567                                  */
8568                                 if (!parent->num_ports)
8569                                         parent->num_ports = 4;
8570                         }
8571                 }
8572         }
8573
8574         if (np->port >= parent->num_ports)
8575                 return -ENODEV;
8576
8577         return 0;
8578 }
8579
8580 static int __devinit phy_record(struct niu_parent *parent,
8581                                 struct phy_probe_info *p,
8582                                 int dev_id_1, int dev_id_2, u8 phy_port,
8583                                 int type)
8584 {
8585         u32 id = (dev_id_1 << 16) | dev_id_2;
8586         u8 idx;
8587
8588         if (dev_id_1 < 0 || dev_id_2 < 0)
8589                 return 0;
8590         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8591                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8592                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8593                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
8594                         return 0;
8595         } else {
8596                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8597                         return 0;
8598         }
8599
8600         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8601                 parent->index, id,
8602                 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8603                 type == PHY_TYPE_PCS ? "PCS" : "MII",
8604                 phy_port);
8605
8606         if (p->cur[type] >= NIU_MAX_PORTS) {
8607                 pr_err("Too many PHY ports\n");
8608                 return -EINVAL;
8609         }
8610         idx = p->cur[type];
8611         p->phy_id[type][idx] = id;
8612         p->phy_port[type][idx] = phy_port;
8613         p->cur[type] = idx + 1;
8614         return 0;
8615 }
8616
8617 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8618 {
8619         int i;
8620
8621         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8622                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8623                         return 1;
8624         }
8625         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8626                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8627                         return 1;
8628         }
8629
8630         return 0;
8631 }
8632
8633 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8634 {
8635         int port, cnt;
8636
8637         cnt = 0;
8638         *lowest = 32;
8639         for (port = 8; port < 32; port++) {
8640                 if (port_has_10g(p, port)) {
8641                         if (!cnt)
8642                                 *lowest = port;
8643                         cnt++;
8644                 }
8645         }
8646
8647         return cnt;
8648 }
8649
8650 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8651 {
8652         *lowest = 32;
8653         if (p->cur[PHY_TYPE_MII])
8654                 *lowest = p->phy_port[PHY_TYPE_MII][0];
8655
8656         return p->cur[PHY_TYPE_MII];
8657 }
8658
8659 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8660 {
8661         int num_ports = parent->num_ports;
8662         int i;
8663
8664         for (i = 0; i < num_ports; i++) {
8665                 parent->rxchan_per_port[i] = (16 / num_ports);
8666                 parent->txchan_per_port[i] = (16 / num_ports);
8667
8668                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8669                         parent->index, i,
8670                         parent->rxchan_per_port[i],
8671                         parent->txchan_per_port[i]);
8672         }
8673 }
8674
8675 static void __devinit niu_divide_channels(struct niu_parent *parent,
8676                                           int num_10g, int num_1g)
8677 {
8678         int num_ports = parent->num_ports;
8679         int rx_chans_per_10g, rx_chans_per_1g;
8680         int tx_chans_per_10g, tx_chans_per_1g;
8681         int i, tot_rx, tot_tx;
8682
8683         if (!num_10g || !num_1g) {
8684                 rx_chans_per_10g = rx_chans_per_1g =
8685                         (NIU_NUM_RXCHAN / num_ports);
8686                 tx_chans_per_10g = tx_chans_per_1g =
8687                         (NIU_NUM_TXCHAN / num_ports);
8688         } else {
8689                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8690                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8691                                     (rx_chans_per_1g * num_1g)) /
8692                         num_10g;
8693
8694                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8695                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8696                                     (tx_chans_per_1g * num_1g)) /
8697                         num_10g;
8698         }
8699
8700         tot_rx = tot_tx = 0;
8701         for (i = 0; i < num_ports; i++) {
8702                 int type = phy_decode(parent->port_phy, i);
8703
8704                 if (type == PORT_TYPE_10G) {
8705                         parent->rxchan_per_port[i] = rx_chans_per_10g;
8706                         parent->txchan_per_port[i] = tx_chans_per_10g;
8707                 } else {
8708                         parent->rxchan_per_port[i] = rx_chans_per_1g;
8709                         parent->txchan_per_port[i] = tx_chans_per_1g;
8710                 }
8711                 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8712                         parent->index, i,
8713                         parent->rxchan_per_port[i],
8714                         parent->txchan_per_port[i]);
8715                 tot_rx += parent->rxchan_per_port[i];
8716                 tot_tx += parent->txchan_per_port[i];
8717         }
8718
8719         if (tot_rx > NIU_NUM_RXCHAN) {
8720                 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8721                        parent->index, tot_rx);
8722                 for (i = 0; i < num_ports; i++)
8723                         parent->rxchan_per_port[i] = 1;
8724         }
8725         if (tot_tx > NIU_NUM_TXCHAN) {
8726                 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8727                        parent->index, tot_tx);
8728                 for (i = 0; i < num_ports; i++)
8729                         parent->txchan_per_port[i] = 1;
8730         }
8731         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8732                 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8733                            parent->index, tot_rx, tot_tx);
8734         }
8735 }
8736
8737 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8738                                             int num_10g, int num_1g)
8739 {
8740         int i, num_ports = parent->num_ports;
8741         int rdc_group, rdc_groups_per_port;
8742         int rdc_channel_base;
8743
8744         rdc_group = 0;
8745         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8746
8747         rdc_channel_base = 0;
8748
8749         for (i = 0; i < num_ports; i++) {
8750                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8751                 int grp, num_channels = parent->rxchan_per_port[i];
8752                 int this_channel_offset;
8753
8754                 tp->first_table_num = rdc_group;
8755                 tp->num_tables = rdc_groups_per_port;
8756                 this_channel_offset = 0;
8757                 for (grp = 0; grp < tp->num_tables; grp++) {
8758                         struct rdc_table *rt = &tp->tables[grp];
8759                         int slot;
8760
8761                         pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8762                                 parent->index, i, tp->first_table_num + grp);
8763                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8764                                 rt->rxdma_channel[slot] =
8765                                         rdc_channel_base + this_channel_offset;
8766
8767                                 pr_cont("%d ", rt->rxdma_channel[slot]);
8768
8769                                 if (++this_channel_offset == num_channels)
8770                                         this_channel_offset = 0;
8771                         }
8772                         pr_cont("]\n");
8773                 }
8774
8775                 parent->rdc_default[i] = rdc_channel_base;
8776
8777                 rdc_channel_base += num_channels;
8778                 rdc_group += rdc_groups_per_port;
8779         }
8780 }
8781
8782 static int __devinit fill_phy_probe_info(struct niu *np,
8783                                          struct niu_parent *parent,
8784                                          struct phy_probe_info *info)
8785 {
8786         unsigned long flags;
8787         int port, err;
8788
8789         memset(info, 0, sizeof(*info));
8790
8791         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
8792         niu_lock_parent(np, flags);
8793         err = 0;
8794         for (port = 8; port < 32; port++) {
8795                 int dev_id_1, dev_id_2;
8796
8797                 dev_id_1 = mdio_read(np, port,
8798                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8799                 dev_id_2 = mdio_read(np, port,
8800                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8801                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8802                                  PHY_TYPE_PMA_PMD);
8803                 if (err)
8804                         break;
8805                 dev_id_1 = mdio_read(np, port,
8806                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
8807                 dev_id_2 = mdio_read(np, port,
8808                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
8809                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8810                                  PHY_TYPE_PCS);
8811                 if (err)
8812                         break;
8813                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8814                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8815                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8816                                  PHY_TYPE_MII);
8817                 if (err)
8818                         break;
8819         }
8820         niu_unlock_parent(np, flags);
8821
8822         return err;
8823 }
8824
8825 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8826 {
8827         struct phy_probe_info *info = &parent->phy_probe_info;
8828         int lowest_10g, lowest_1g;
8829         int num_10g, num_1g;
8830         u32 val;
8831         int err;
8832
8833         num_10g = num_1g = 0;
8834
8835         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8836             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8837                 num_10g = 0;
8838                 num_1g = 2;
8839                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8840                 parent->num_ports = 4;
8841                 val = (phy_encode(PORT_TYPE_1G, 0) |
8842                        phy_encode(PORT_TYPE_1G, 1) |
8843                        phy_encode(PORT_TYPE_1G, 2) |
8844                        phy_encode(PORT_TYPE_1G, 3));
8845         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8846                 num_10g = 2;
8847                 num_1g = 0;
8848                 parent->num_ports = 2;
8849                 val = (phy_encode(PORT_TYPE_10G, 0) |
8850                        phy_encode(PORT_TYPE_10G, 1));
8851         } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8852                    (parent->plat_type == PLAT_TYPE_NIU)) {
8853                 /* this is the Monza case */
8854                 if (np->flags & NIU_FLAGS_10G) {
8855                         val = (phy_encode(PORT_TYPE_10G, 0) |
8856                                phy_encode(PORT_TYPE_10G, 1));
8857                 } else {
8858                         val = (phy_encode(PORT_TYPE_1G, 0) |
8859                                phy_encode(PORT_TYPE_1G, 1));
8860                 }
8861         } else {
8862                 err = fill_phy_probe_info(np, parent, info);
8863                 if (err)
8864                         return err;
8865
8866                 num_10g = count_10g_ports(info, &lowest_10g);
8867                 num_1g = count_1g_ports(info, &lowest_1g);
8868
8869                 switch ((num_10g << 4) | num_1g) {
8870                 case 0x24:
8871                         if (lowest_1g == 10)
8872                                 parent->plat_type = PLAT_TYPE_VF_P0;
8873                         else if (lowest_1g == 26)
8874                                 parent->plat_type = PLAT_TYPE_VF_P1;
8875                         else
8876                                 goto unknown_vg_1g_port;
8877
8878                         /* fallthru */
8879                 case 0x22:
8880                         val = (phy_encode(PORT_TYPE_10G, 0) |
8881                                phy_encode(PORT_TYPE_10G, 1) |
8882                                phy_encode(PORT_TYPE_1G, 2) |
8883                                phy_encode(PORT_TYPE_1G, 3));
8884                         break;
8885
8886                 case 0x20:
8887                         val = (phy_encode(PORT_TYPE_10G, 0) |
8888                                phy_encode(PORT_TYPE_10G, 1));
8889                         break;
8890
8891                 case 0x10:
8892                         val = phy_encode(PORT_TYPE_10G, np->port);
8893                         break;
8894
8895                 case 0x14:
8896                         if (lowest_1g == 10)
8897                                 parent->plat_type = PLAT_TYPE_VF_P0;
8898                         else if (lowest_1g == 26)
8899                                 parent->plat_type = PLAT_TYPE_VF_P1;
8900                         else
8901                                 goto unknown_vg_1g_port;
8902
8903                         /* fallthru */
8904                 case 0x13:
8905                         if ((lowest_10g & 0x7) == 0)
8906                                 val = (phy_encode(PORT_TYPE_10G, 0) |
8907                                        phy_encode(PORT_TYPE_1G, 1) |
8908                                        phy_encode(PORT_TYPE_1G, 2) |
8909                                        phy_encode(PORT_TYPE_1G, 3));
8910                         else
8911                                 val = (phy_encode(PORT_TYPE_1G, 0) |
8912                                        phy_encode(PORT_TYPE_10G, 1) |
8913                                        phy_encode(PORT_TYPE_1G, 2) |
8914                                        phy_encode(PORT_TYPE_1G, 3));
8915                         break;
8916
8917                 case 0x04:
8918                         if (lowest_1g == 10)
8919                                 parent->plat_type = PLAT_TYPE_VF_P0;
8920                         else if (lowest_1g == 26)
8921                                 parent->plat_type = PLAT_TYPE_VF_P1;
8922                         else
8923                                 goto unknown_vg_1g_port;
8924
8925                         val = (phy_encode(PORT_TYPE_1G, 0) |
8926                                phy_encode(PORT_TYPE_1G, 1) |
8927                                phy_encode(PORT_TYPE_1G, 2) |
8928                                phy_encode(PORT_TYPE_1G, 3));
8929                         break;
8930
8931                 default:
8932                         pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8933                                num_10g, num_1g);
8934                         return -EINVAL;
8935                 }
8936         }
8937
8938         parent->port_phy = val;
8939
8940         if (parent->plat_type == PLAT_TYPE_NIU)
8941                 niu_n2_divide_channels(parent);
8942         else
8943                 niu_divide_channels(parent, num_10g, num_1g);
8944
8945         niu_divide_rdc_groups(parent, num_10g, num_1g);
8946
8947         return 0;
8948
8949 unknown_vg_1g_port:
8950         pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8951         return -EINVAL;
8952 }
8953
8954 static int __devinit niu_probe_ports(struct niu *np)
8955 {
8956         struct niu_parent *parent = np->parent;
8957         int err, i;
8958
8959         if (parent->port_phy == PORT_PHY_UNKNOWN) {
8960                 err = walk_phys(np, parent);
8961                 if (err)
8962                         return err;
8963
8964                 niu_set_ldg_timer_res(np, 2);
8965                 for (i = 0; i <= LDN_MAX; i++)
8966                         niu_ldn_irq_enable(np, i, 0);
8967         }
8968
8969         if (parent->port_phy == PORT_PHY_INVALID)
8970                 return -EINVAL;
8971
8972         return 0;
8973 }
8974
8975 static int __devinit niu_classifier_swstate_init(struct niu *np)
8976 {
8977         struct niu_classifier *cp = &np->clas;
8978
8979         cp->tcam_top = (u16) np->port;
8980         cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8981         cp->h1_init = 0xffffffff;
8982         cp->h2_init = 0xffff;
8983
8984         return fflp_early_init(np);
8985 }
8986
8987 static void __devinit niu_link_config_init(struct niu *np)
8988 {
8989         struct niu_link_config *lp = &np->link_config;
8990
8991         lp->advertising = (ADVERTISED_10baseT_Half |
8992                            ADVERTISED_10baseT_Full |
8993                            ADVERTISED_100baseT_Half |
8994                            ADVERTISED_100baseT_Full |
8995                            ADVERTISED_1000baseT_Half |
8996                            ADVERTISED_1000baseT_Full |
8997                            ADVERTISED_10000baseT_Full |
8998                            ADVERTISED_Autoneg);
8999         lp->speed = lp->active_speed = SPEED_INVALID;
9000         lp->duplex = DUPLEX_FULL;
9001         lp->active_duplex = DUPLEX_INVALID;
9002         lp->autoneg = 1;
9003 #if 0
9004         lp->loopback_mode = LOOPBACK_MAC;
9005         lp->active_speed = SPEED_10000;
9006         lp->active_duplex = DUPLEX_FULL;
9007 #else
9008         lp->loopback_mode = LOOPBACK_DISABLED;
9009 #endif
9010 }
9011
9012 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9013 {
9014         switch (np->port) {
9015         case 0:
9016                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9017                 np->ipp_off  = 0x00000;
9018                 np->pcs_off  = 0x04000;
9019                 np->xpcs_off = 0x02000;
9020                 break;
9021
9022         case 1:
9023                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9024                 np->ipp_off  = 0x08000;
9025                 np->pcs_off  = 0x0a000;
9026                 np->xpcs_off = 0x08000;
9027                 break;
9028
9029         case 2:
9030                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9031                 np->ipp_off  = 0x04000;
9032                 np->pcs_off  = 0x0e000;
9033                 np->xpcs_off = ~0UL;
9034                 break;
9035
9036         case 3:
9037                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9038                 np->ipp_off  = 0x0c000;
9039                 np->pcs_off  = 0x12000;
9040                 np->xpcs_off = ~0UL;
9041                 break;
9042
9043         default:
9044                 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9045                 return -EINVAL;
9046         }
9047
9048         return 0;
9049 }
9050
9051 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9052 {
9053         struct msix_entry msi_vec[NIU_NUM_LDG];
9054         struct niu_parent *parent = np->parent;
9055         struct pci_dev *pdev = np->pdev;
9056         int i, num_irqs, err;
9057         u8 first_ldg;
9058
9059         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9060         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9061                 ldg_num_map[i] = first_ldg + i;
9062
9063         num_irqs = (parent->rxchan_per_port[np->port] +
9064                     parent->txchan_per_port[np->port] +
9065                     (np->port == 0 ? 3 : 1));
9066         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9067
9068 retry:
9069         for (i = 0; i < num_irqs; i++) {
9070                 msi_vec[i].vector = 0;
9071                 msi_vec[i].entry = i;
9072         }
9073
9074         err = pci_enable_msix(pdev, msi_vec, num_irqs);
9075         if (err < 0) {
9076                 np->flags &= ~NIU_FLAGS_MSIX;
9077                 return;
9078         }
9079         if (err > 0) {
9080                 num_irqs = err;
9081                 goto retry;
9082         }
9083
9084         np->flags |= NIU_FLAGS_MSIX;
9085         for (i = 0; i < num_irqs; i++)
9086                 np->ldg[i].irq = msi_vec[i].vector;
9087         np->num_ldg = num_irqs;
9088 }
9089
9090 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9091 {
9092 #ifdef CONFIG_SPARC64
9093         struct of_device *op = np->op;
9094         const u32 *int_prop;
9095         int i;
9096
9097         int_prop = of_get_property(op->node, "interrupts", NULL);
9098         if (!int_prop)
9099                 return -ENODEV;
9100
9101         for (i = 0; i < op->num_irqs; i++) {
9102                 ldg_num_map[i] = int_prop[i];
9103                 np->ldg[i].irq = op->irqs[i];
9104         }
9105
9106         np->num_ldg = op->num_irqs;
9107
9108         return 0;
9109 #else
9110         return -EINVAL;
9111 #endif
9112 }
9113
9114 static int __devinit niu_ldg_init(struct niu *np)
9115 {
9116         struct niu_parent *parent = np->parent;
9117         u8 ldg_num_map[NIU_NUM_LDG];
9118         int first_chan, num_chan;
9119         int i, err, ldg_rotor;
9120         u8 port;
9121
9122         np->num_ldg = 1;
9123         np->ldg[0].irq = np->dev->irq;
9124         if (parent->plat_type == PLAT_TYPE_NIU) {
9125                 err = niu_n2_irq_init(np, ldg_num_map);
9126                 if (err)
9127                         return err;
9128         } else
9129                 niu_try_msix(np, ldg_num_map);
9130
9131         port = np->port;
9132         for (i = 0; i < np->num_ldg; i++) {
9133                 struct niu_ldg *lp = &np->ldg[i];
9134
9135                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9136
9137                 lp->np = np;
9138                 lp->ldg_num = ldg_num_map[i];
9139                 lp->timer = 2; /* XXX */
9140
9141                 /* On N2 NIU the firmware has setup the SID mappings so they go
9142                  * to the correct values that will route the LDG to the proper
9143                  * interrupt in the NCU interrupt table.
9144                  */
9145                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9146                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9147                         if (err)
9148                                 return err;
9149                 }
9150         }
9151
9152         /* We adopt the LDG assignment ordering used by the N2 NIU
9153          * 'interrupt' properties because that simplifies a lot of
9154          * things.  This ordering is:
9155          *
9156          *      MAC
9157          *      MIF     (if port zero)
9158          *      SYSERR  (if port zero)
9159          *      RX channels
9160          *      TX channels
9161          */
9162
9163         ldg_rotor = 0;
9164
9165         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9166                                   LDN_MAC(port));
9167         if (err)
9168                 return err;
9169
9170         ldg_rotor++;
9171         if (ldg_rotor == np->num_ldg)
9172                 ldg_rotor = 0;
9173
9174         if (port == 0) {
9175                 err = niu_ldg_assign_ldn(np, parent,
9176                                          ldg_num_map[ldg_rotor],
9177                                          LDN_MIF);
9178                 if (err)
9179                         return err;
9180
9181                 ldg_rotor++;
9182                 if (ldg_rotor == np->num_ldg)
9183                         ldg_rotor = 0;
9184
9185                 err = niu_ldg_assign_ldn(np, parent,
9186                                          ldg_num_map[ldg_rotor],
9187                                          LDN_DEVICE_ERROR);
9188                 if (err)
9189                         return err;
9190
9191                 ldg_rotor++;
9192                 if (ldg_rotor == np->num_ldg)
9193                         ldg_rotor = 0;
9194
9195         }
9196
9197         first_chan = 0;
9198         for (i = 0; i < port; i++)
9199                 first_chan += parent->rxchan_per_port[port];
9200         num_chan = parent->rxchan_per_port[port];
9201
9202         for (i = first_chan; i < (first_chan + num_chan); i++) {
9203                 err = niu_ldg_assign_ldn(np, parent,
9204                                          ldg_num_map[ldg_rotor],
9205                                          LDN_RXDMA(i));
9206                 if (err)
9207                         return err;
9208                 ldg_rotor++;
9209                 if (ldg_rotor == np->num_ldg)
9210                         ldg_rotor = 0;
9211         }
9212
9213         first_chan = 0;
9214         for (i = 0; i < port; i++)
9215                 first_chan += parent->txchan_per_port[port];
9216         num_chan = parent->txchan_per_port[port];
9217         for (i = first_chan; i < (first_chan + num_chan); i++) {
9218                 err = niu_ldg_assign_ldn(np, parent,
9219                                          ldg_num_map[ldg_rotor],
9220                                          LDN_TXDMA(i));
9221                 if (err)
9222                         return err;
9223                 ldg_rotor++;
9224                 if (ldg_rotor == np->num_ldg)
9225                         ldg_rotor = 0;
9226         }
9227
9228         return 0;
9229 }
9230
9231 static void __devexit niu_ldg_free(struct niu *np)
9232 {
9233         if (np->flags & NIU_FLAGS_MSIX)
9234                 pci_disable_msix(np->pdev);
9235 }
9236
9237 static int __devinit niu_get_of_props(struct niu *np)
9238 {
9239 #ifdef CONFIG_SPARC64
9240         struct net_device *dev = np->dev;
9241         struct device_node *dp;
9242         const char *phy_type;
9243         const u8 *mac_addr;
9244         const char *model;
9245         int prop_len;
9246
9247         if (np->parent->plat_type == PLAT_TYPE_NIU)
9248                 dp = np->op->node;
9249         else
9250                 dp = pci_device_to_OF_node(np->pdev);
9251
9252         phy_type = of_get_property(dp, "phy-type", &prop_len);
9253         if (!phy_type) {
9254                 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9255                            dp->full_name);
9256                 return -EINVAL;
9257         }
9258
9259         if (!strcmp(phy_type, "none"))
9260                 return -ENODEV;
9261
9262         strcpy(np->vpd.phy_type, phy_type);
9263
9264         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9265                 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9266                            dp->full_name, np->vpd.phy_type);
9267                 return -EINVAL;
9268         }
9269
9270         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9271         if (!mac_addr) {
9272                 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9273                            dp->full_name);
9274                 return -EINVAL;
9275         }
9276         if (prop_len != dev->addr_len) {
9277                 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9278                            dp->full_name, prop_len);
9279         }
9280         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9281         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9282                 netdev_err(dev, "%s: OF MAC address is invalid\n",
9283                            dp->full_name);
9284                 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
9285                 return -EINVAL;
9286         }
9287
9288         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9289
9290         model = of_get_property(dp, "model", &prop_len);
9291
9292         if (model)
9293                 strcpy(np->vpd.model, model);
9294
9295         if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9296                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9297                         NIU_FLAGS_HOTPLUG_PHY);
9298         }
9299
9300         return 0;
9301 #else
9302         return -EINVAL;
9303 #endif
9304 }
9305
9306 static int __devinit niu_get_invariants(struct niu *np)
9307 {
9308         int err, have_props;
9309         u32 offset;
9310
9311         err = niu_get_of_props(np);
9312         if (err == -ENODEV)
9313                 return err;
9314
9315         have_props = !err;
9316
9317         err = niu_init_mac_ipp_pcs_base(np);
9318         if (err)
9319                 return err;
9320
9321         if (have_props) {
9322                 err = niu_get_and_validate_port(np);
9323                 if (err)
9324                         return err;
9325
9326         } else  {
9327                 if (np->parent->plat_type == PLAT_TYPE_NIU)
9328                         return -EINVAL;
9329
9330                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9331                 offset = niu_pci_vpd_offset(np);
9332                 netif_printk(np, probe, KERN_DEBUG, np->dev,
9333                              "%s() VPD offset [%08x]\n", __func__, offset);
9334                 if (offset)
9335                         niu_pci_vpd_fetch(np, offset);
9336                 nw64(ESPC_PIO_EN, 0);
9337
9338                 if (np->flags & NIU_FLAGS_VPD_VALID) {
9339                         niu_pci_vpd_validate(np);
9340                         err = niu_get_and_validate_port(np);
9341                         if (err)
9342                                 return err;
9343                 }
9344
9345                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9346                         err = niu_get_and_validate_port(np);
9347                         if (err)
9348                                 return err;
9349                         err = niu_pci_probe_sprom(np);
9350                         if (err)
9351                                 return err;
9352                 }
9353         }
9354
9355         err = niu_probe_ports(np);
9356         if (err)
9357                 return err;
9358
9359         niu_ldg_init(np);
9360
9361         niu_classifier_swstate_init(np);
9362         niu_link_config_init(np);
9363
9364         err = niu_determine_phy_disposition(np);
9365         if (!err)
9366                 err = niu_init_link(np);
9367
9368         return err;
9369 }
9370
9371 static LIST_HEAD(niu_parent_list);
9372 static DEFINE_MUTEX(niu_parent_lock);
9373 static int niu_parent_index;
9374
9375 static ssize_t show_port_phy(struct device *dev,
9376                              struct device_attribute *attr, char *buf)
9377 {
9378         struct platform_device *plat_dev = to_platform_device(dev);
9379         struct niu_parent *p = plat_dev->dev.platform_data;
9380         u32 port_phy = p->port_phy;
9381         char *orig_buf = buf;
9382         int i;
9383
9384         if (port_phy == PORT_PHY_UNKNOWN ||
9385             port_phy == PORT_PHY_INVALID)
9386                 return 0;
9387
9388         for (i = 0; i < p->num_ports; i++) {
9389                 const char *type_str;
9390                 int type;
9391
9392                 type = phy_decode(port_phy, i);
9393                 if (type == PORT_TYPE_10G)
9394                         type_str = "10G";
9395                 else
9396                         type_str = "1G";
9397                 buf += sprintf(buf,
9398                                (i == 0) ? "%s" : " %s",
9399                                type_str);
9400         }
9401         buf += sprintf(buf, "\n");
9402         return buf - orig_buf;
9403 }
9404
9405 static ssize_t show_plat_type(struct device *dev,
9406                               struct device_attribute *attr, char *buf)
9407 {
9408         struct platform_device *plat_dev = to_platform_device(dev);
9409         struct niu_parent *p = plat_dev->dev.platform_data;
9410         const char *type_str;
9411
9412         switch (p->plat_type) {
9413         case PLAT_TYPE_ATLAS:
9414                 type_str = "atlas";
9415                 break;
9416         case PLAT_TYPE_NIU:
9417                 type_str = "niu";
9418                 break;
9419         case PLAT_TYPE_VF_P0:
9420                 type_str = "vf_p0";
9421                 break;
9422         case PLAT_TYPE_VF_P1:
9423                 type_str = "vf_p1";
9424                 break;
9425         default:
9426                 type_str = "unknown";
9427                 break;
9428         }
9429
9430         return sprintf(buf, "%s\n", type_str);
9431 }
9432
9433 static ssize_t __show_chan_per_port(struct device *dev,
9434                                     struct device_attribute *attr, char *buf,
9435                                     int rx)
9436 {
9437         struct platform_device *plat_dev = to_platform_device(dev);
9438         struct niu_parent *p = plat_dev->dev.platform_data;
9439         char *orig_buf = buf;
9440         u8 *arr;
9441         int i;
9442
9443         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9444
9445         for (i = 0; i < p->num_ports; i++) {
9446                 buf += sprintf(buf,
9447                                (i == 0) ? "%d" : " %d",
9448                                arr[i]);
9449         }
9450         buf += sprintf(buf, "\n");
9451
9452         return buf - orig_buf;
9453 }
9454
9455 static ssize_t show_rxchan_per_port(struct device *dev,
9456                                     struct device_attribute *attr, char *buf)
9457 {
9458         return __show_chan_per_port(dev, attr, buf, 1);
9459 }
9460
9461 static ssize_t show_txchan_per_port(struct device *dev,
9462                                     struct device_attribute *attr, char *buf)
9463 {
9464         return __show_chan_per_port(dev, attr, buf, 1);
9465 }
9466
9467 static ssize_t show_num_ports(struct device *dev,
9468                               struct device_attribute *attr, char *buf)
9469 {
9470         struct platform_device *plat_dev = to_platform_device(dev);
9471         struct niu_parent *p = plat_dev->dev.platform_data;
9472
9473         return sprintf(buf, "%d\n", p->num_ports);
9474 }
9475
9476 static struct device_attribute niu_parent_attributes[] = {
9477         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9478         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9479         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9480         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9481         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9482         {}
9483 };
9484
9485 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9486                                                     union niu_parent_id *id,
9487                                                     u8 ptype)
9488 {
9489         struct platform_device *plat_dev;
9490         struct niu_parent *p;
9491         int i;
9492
9493         plat_dev = platform_device_register_simple("niu", niu_parent_index,
9494                                                    NULL, 0);
9495         if (IS_ERR(plat_dev))
9496                 return NULL;
9497
9498         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9499                 int err = device_create_file(&plat_dev->dev,
9500                                              &niu_parent_attributes[i]);
9501                 if (err)
9502                         goto fail_unregister;
9503         }
9504
9505         p = kzalloc(sizeof(*p), GFP_KERNEL);
9506         if (!p)
9507                 goto fail_unregister;
9508
9509         p->index = niu_parent_index++;
9510
9511         plat_dev->dev.platform_data = p;
9512         p->plat_dev = plat_dev;
9513
9514         memcpy(&p->id, id, sizeof(*id));
9515         p->plat_type = ptype;
9516         INIT_LIST_HEAD(&p->list);
9517         atomic_set(&p->refcnt, 0);
9518         list_add(&p->list, &niu_parent_list);
9519         spin_lock_init(&p->lock);
9520
9521         p->rxdma_clock_divider = 7500;
9522
9523         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9524         if (p->plat_type == PLAT_TYPE_NIU)
9525                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9526
9527         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9528                 int index = i - CLASS_CODE_USER_PROG1;
9529
9530                 p->tcam_key[index] = TCAM_KEY_TSEL;
9531                 p->flow_key[index] = (FLOW_KEY_IPSA |
9532                                       FLOW_KEY_IPDA |
9533                                       FLOW_KEY_PROTO |
9534                                       (FLOW_KEY_L4_BYTE12 <<
9535                                        FLOW_KEY_L4_0_SHIFT) |
9536                                       (FLOW_KEY_L4_BYTE12 <<
9537                                        FLOW_KEY_L4_1_SHIFT));
9538         }
9539
9540         for (i = 0; i < LDN_MAX + 1; i++)
9541                 p->ldg_map[i] = LDG_INVALID;
9542
9543         return p;
9544
9545 fail_unregister:
9546         platform_device_unregister(plat_dev);
9547         return NULL;
9548 }
9549
9550 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9551                                                     union niu_parent_id *id,
9552                                                     u8 ptype)
9553 {
9554         struct niu_parent *p, *tmp;
9555         int port = np->port;
9556
9557         mutex_lock(&niu_parent_lock);
9558         p = NULL;
9559         list_for_each_entry(tmp, &niu_parent_list, list) {
9560                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9561                         p = tmp;
9562                         break;
9563                 }
9564         }
9565         if (!p)
9566                 p = niu_new_parent(np, id, ptype);
9567
9568         if (p) {
9569                 char port_name[6];
9570                 int err;
9571
9572                 sprintf(port_name, "port%d", port);
9573                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9574                                         &np->device->kobj,
9575                                         port_name);
9576                 if (!err) {
9577                         p->ports[port] = np;
9578                         atomic_inc(&p->refcnt);
9579                 }
9580         }
9581         mutex_unlock(&niu_parent_lock);
9582
9583         return p;
9584 }
9585
9586 static void niu_put_parent(struct niu *np)
9587 {
9588         struct niu_parent *p = np->parent;
9589         u8 port = np->port;
9590         char port_name[6];
9591
9592         BUG_ON(!p || p->ports[port] != np);
9593
9594         netif_printk(np, probe, KERN_DEBUG, np->dev,
9595                      "%s() port[%u]\n", __func__, port);
9596
9597         sprintf(port_name, "port%d", port);
9598
9599         mutex_lock(&niu_parent_lock);
9600
9601         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9602
9603         p->ports[port] = NULL;
9604         np->parent = NULL;
9605
9606         if (atomic_dec_and_test(&p->refcnt)) {
9607                 list_del(&p->list);
9608                 platform_device_unregister(p->plat_dev);
9609         }
9610
9611         mutex_unlock(&niu_parent_lock);
9612 }
9613
9614 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9615                                     u64 *handle, gfp_t flag)
9616 {
9617         dma_addr_t dh;
9618         void *ret;
9619
9620         ret = dma_alloc_coherent(dev, size, &dh, flag);
9621         if (ret)
9622                 *handle = dh;
9623         return ret;
9624 }
9625
9626 static void niu_pci_free_coherent(struct device *dev, size_t size,
9627                                   void *cpu_addr, u64 handle)
9628 {
9629         dma_free_coherent(dev, size, cpu_addr, handle);
9630 }
9631
9632 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9633                             unsigned long offset, size_t size,
9634                             enum dma_data_direction direction)
9635 {
9636         return dma_map_page(dev, page, offset, size, direction);
9637 }
9638
9639 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9640                                size_t size, enum dma_data_direction direction)
9641 {
9642         dma_unmap_page(dev, dma_address, size, direction);
9643 }
9644
9645 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9646                               size_t size,
9647                               enum dma_data_direction direction)
9648 {
9649         return dma_map_single(dev, cpu_addr, size, direction);
9650 }
9651
9652 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9653                                  size_t size,
9654                                  enum dma_data_direction direction)
9655 {
9656         dma_unmap_single(dev, dma_address, size, direction);
9657 }
9658
9659 static const struct niu_ops niu_pci_ops = {
9660         .alloc_coherent = niu_pci_alloc_coherent,
9661         .free_coherent  = niu_pci_free_coherent,
9662         .map_page       = niu_pci_map_page,
9663         .unmap_page     = niu_pci_unmap_page,
9664         .map_single     = niu_pci_map_single,
9665         .unmap_single   = niu_pci_unmap_single,
9666 };
9667
9668 static void __devinit niu_driver_version(void)
9669 {
9670         static int niu_version_printed;
9671
9672         if (niu_version_printed++ == 0)
9673                 pr_info("%s", version);
9674 }
9675
9676 static struct net_device * __devinit niu_alloc_and_init(
9677         struct device *gen_dev, struct pci_dev *pdev,
9678         struct of_device *op, const struct niu_ops *ops,
9679         u8 port)
9680 {
9681         struct net_device *dev;
9682         struct niu *np;
9683
9684         dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9685         if (!dev) {
9686                 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
9687                 return NULL;
9688         }
9689
9690         SET_NETDEV_DEV(dev, gen_dev);
9691
9692         np = netdev_priv(dev);
9693         np->dev = dev;
9694         np->pdev = pdev;
9695         np->op = op;
9696         np->device = gen_dev;
9697         np->ops = ops;
9698
9699         np->msg_enable = niu_debug;
9700
9701         spin_lock_init(&np->lock);
9702         INIT_WORK(&np->reset_task, niu_reset_task);
9703
9704         np->port = port;
9705
9706         return dev;
9707 }
9708
9709 static const struct net_device_ops niu_netdev_ops = {
9710         .ndo_open               = niu_open,
9711         .ndo_stop               = niu_close,
9712         .ndo_start_xmit         = niu_start_xmit,
9713         .ndo_get_stats          = niu_get_stats,
9714         .ndo_set_multicast_list = niu_set_rx_mode,
9715         .ndo_validate_addr      = eth_validate_addr,
9716         .ndo_set_mac_address    = niu_set_mac_addr,
9717         .ndo_do_ioctl           = niu_ioctl,
9718         .ndo_tx_timeout         = niu_tx_timeout,
9719         .ndo_change_mtu         = niu_change_mtu,
9720 };
9721
9722 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9723 {
9724         dev->netdev_ops = &niu_netdev_ops;
9725         dev->ethtool_ops = &niu_ethtool_ops;
9726         dev->watchdog_timeo = NIU_TX_TIMEOUT;
9727 }
9728
9729 static void __devinit niu_device_announce(struct niu *np)
9730 {
9731         struct net_device *dev = np->dev;
9732
9733         pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9734
9735         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9736                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9737                                 dev->name,
9738                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9739                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9740                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9741                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9742                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9743                                 np->vpd.phy_type);
9744         } else {
9745                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9746                                 dev->name,
9747                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9748                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9749                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9750                                  (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9751                                   "COPPER")),
9752                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9753                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9754                                 np->vpd.phy_type);
9755         }
9756 }
9757
9758 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9759                                       const struct pci_device_id *ent)
9760 {
9761         union niu_parent_id parent_id;
9762         struct net_device *dev;
9763         struct niu *np;
9764         int err, pos;
9765         u64 dma_mask;
9766         u16 val16;
9767
9768         niu_driver_version();
9769
9770         err = pci_enable_device(pdev);
9771         if (err) {
9772                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9773                 return err;
9774         }
9775
9776         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9777             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9778                 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9779                 err = -ENODEV;
9780                 goto err_out_disable_pdev;
9781         }
9782
9783         err = pci_request_regions(pdev, DRV_MODULE_NAME);
9784         if (err) {
9785                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9786                 goto err_out_disable_pdev;
9787         }
9788
9789         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9790         if (pos <= 0) {
9791                 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9792                 goto err_out_free_res;
9793         }
9794
9795         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9796                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
9797         if (!dev) {
9798                 err = -ENOMEM;
9799                 goto err_out_free_res;
9800         }
9801         np = netdev_priv(dev);
9802
9803         memset(&parent_id, 0, sizeof(parent_id));
9804         parent_id.pci.domain = pci_domain_nr(pdev->bus);
9805         parent_id.pci.bus = pdev->bus->number;
9806         parent_id.pci.device = PCI_SLOT(pdev->devfn);
9807
9808         np->parent = niu_get_parent(np, &parent_id,
9809                                     PLAT_TYPE_ATLAS);
9810         if (!np->parent) {
9811                 err = -ENOMEM;
9812                 goto err_out_free_dev;
9813         }
9814
9815         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9816         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9817         val16 |= (PCI_EXP_DEVCTL_CERE |
9818                   PCI_EXP_DEVCTL_NFERE |
9819                   PCI_EXP_DEVCTL_FERE |
9820                   PCI_EXP_DEVCTL_URRE |
9821                   PCI_EXP_DEVCTL_RELAX_EN);
9822         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9823
9824         dma_mask = DMA_BIT_MASK(44);
9825         err = pci_set_dma_mask(pdev, dma_mask);
9826         if (!err) {
9827                 dev->features |= NETIF_F_HIGHDMA;
9828                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9829                 if (err) {
9830                         dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9831                         goto err_out_release_parent;
9832                 }
9833         }
9834         if (err || dma_mask == DMA_BIT_MASK(32)) {
9835                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9836                 if (err) {
9837                         dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9838                         goto err_out_release_parent;
9839                 }
9840         }
9841
9842         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9843
9844         np->regs = pci_ioremap_bar(pdev, 0);
9845         if (!np->regs) {
9846                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9847                 err = -ENOMEM;
9848                 goto err_out_release_parent;
9849         }
9850
9851         pci_set_master(pdev);
9852         pci_save_state(pdev);
9853
9854         dev->irq = pdev->irq;
9855
9856         niu_assign_netdev_ops(dev);
9857
9858         err = niu_get_invariants(np);
9859         if (err) {
9860                 if (err != -ENODEV)
9861                         dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9862                 goto err_out_iounmap;
9863         }
9864
9865         err = register_netdev(dev);
9866         if (err) {
9867                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9868                 goto err_out_iounmap;
9869         }
9870
9871         pci_set_drvdata(pdev, dev);
9872
9873         niu_device_announce(np);
9874
9875         return 0;
9876
9877 err_out_iounmap:
9878         if (np->regs) {
9879                 iounmap(np->regs);
9880                 np->regs = NULL;
9881         }
9882
9883 err_out_release_parent:
9884         niu_put_parent(np);
9885
9886 err_out_free_dev:
9887         free_netdev(dev);
9888
9889 err_out_free_res:
9890         pci_release_regions(pdev);
9891
9892 err_out_disable_pdev:
9893         pci_disable_device(pdev);
9894         pci_set_drvdata(pdev, NULL);
9895
9896         return err;
9897 }
9898
9899 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9900 {
9901         struct net_device *dev = pci_get_drvdata(pdev);
9902
9903         if (dev) {
9904                 struct niu *np = netdev_priv(dev);
9905
9906                 unregister_netdev(dev);
9907                 if (np->regs) {
9908                         iounmap(np->regs);
9909                         np->regs = NULL;
9910                 }
9911
9912                 niu_ldg_free(np);
9913
9914                 niu_put_parent(np);
9915
9916                 free_netdev(dev);
9917                 pci_release_regions(pdev);
9918                 pci_disable_device(pdev);
9919                 pci_set_drvdata(pdev, NULL);
9920         }
9921 }
9922
9923 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9924 {
9925         struct net_device *dev = pci_get_drvdata(pdev);
9926         struct niu *np = netdev_priv(dev);
9927         unsigned long flags;
9928
9929         if (!netif_running(dev))
9930                 return 0;
9931
9932         flush_scheduled_work();
9933         niu_netif_stop(np);
9934
9935         del_timer_sync(&np->timer);
9936
9937         spin_lock_irqsave(&np->lock, flags);
9938         niu_enable_interrupts(np, 0);
9939         spin_unlock_irqrestore(&np->lock, flags);
9940
9941         netif_device_detach(dev);
9942
9943         spin_lock_irqsave(&np->lock, flags);
9944         niu_stop_hw(np);
9945         spin_unlock_irqrestore(&np->lock, flags);
9946
9947         pci_save_state(pdev);
9948
9949         return 0;
9950 }
9951
9952 static int niu_resume(struct pci_dev *pdev)
9953 {
9954         struct net_device *dev = pci_get_drvdata(pdev);
9955         struct niu *np = netdev_priv(dev);
9956         unsigned long flags;
9957         int err;
9958
9959         if (!netif_running(dev))
9960                 return 0;
9961
9962         pci_restore_state(pdev);
9963
9964         netif_device_attach(dev);
9965
9966         spin_lock_irqsave(&np->lock, flags);
9967
9968         err = niu_init_hw(np);
9969         if (!err) {
9970                 np->timer.expires = jiffies + HZ;
9971                 add_timer(&np->timer);
9972                 niu_netif_start(np);
9973         }
9974
9975         spin_unlock_irqrestore(&np->lock, flags);
9976
9977         return err;
9978 }
9979
9980 static struct pci_driver niu_pci_driver = {
9981         .name           = DRV_MODULE_NAME,
9982         .id_table       = niu_pci_tbl,
9983         .probe          = niu_pci_init_one,
9984         .remove         = __devexit_p(niu_pci_remove_one),
9985         .suspend        = niu_suspend,
9986         .resume         = niu_resume,
9987 };
9988
9989 #ifdef CONFIG_SPARC64
9990 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9991                                      u64 *dma_addr, gfp_t flag)
9992 {
9993         unsigned long order = get_order(size);
9994         unsigned long page = __get_free_pages(flag, order);
9995
9996         if (page == 0UL)
9997                 return NULL;
9998         memset((char *)page, 0, PAGE_SIZE << order);
9999         *dma_addr = __pa(page);
10000
10001         return (void *) page;
10002 }
10003
10004 static void niu_phys_free_coherent(struct device *dev, size_t size,
10005                                    void *cpu_addr, u64 handle)
10006 {
10007         unsigned long order = get_order(size);
10008
10009         free_pages((unsigned long) cpu_addr, order);
10010 }
10011
10012 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10013                              unsigned long offset, size_t size,
10014                              enum dma_data_direction direction)
10015 {
10016         return page_to_phys(page) + offset;
10017 }
10018
10019 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10020                                 size_t size, enum dma_data_direction direction)
10021 {
10022         /* Nothing to do.  */
10023 }
10024
10025 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10026                                size_t size,
10027                                enum dma_data_direction direction)
10028 {
10029         return __pa(cpu_addr);
10030 }
10031
10032 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10033                                   size_t size,
10034                                   enum dma_data_direction direction)
10035 {
10036         /* Nothing to do.  */
10037 }
10038
10039 static const struct niu_ops niu_phys_ops = {
10040         .alloc_coherent = niu_phys_alloc_coherent,
10041         .free_coherent  = niu_phys_free_coherent,
10042         .map_page       = niu_phys_map_page,
10043         .unmap_page     = niu_phys_unmap_page,
10044         .map_single     = niu_phys_map_single,
10045         .unmap_single   = niu_phys_unmap_single,
10046 };
10047
10048 static int __devinit niu_of_probe(struct of_device *op,
10049                                   const struct of_device_id *match)
10050 {
10051         union niu_parent_id parent_id;
10052         struct net_device *dev;
10053         struct niu *np;
10054         const u32 *reg;
10055         int err;
10056
10057         niu_driver_version();
10058
10059         reg = of_get_property(op->node, "reg", NULL);
10060         if (!reg) {
10061                 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10062                         op->node->full_name);
10063                 return -ENODEV;
10064         }
10065
10066         dev = niu_alloc_and_init(&op->dev, NULL, op,
10067                                  &niu_phys_ops, reg[0] & 0x1);
10068         if (!dev) {
10069                 err = -ENOMEM;
10070                 goto err_out;
10071         }
10072         np = netdev_priv(dev);
10073
10074         memset(&parent_id, 0, sizeof(parent_id));
10075         parent_id.of = of_get_parent(op->node);
10076
10077         np->parent = niu_get_parent(np, &parent_id,
10078                                     PLAT_TYPE_NIU);
10079         if (!np->parent) {
10080                 err = -ENOMEM;
10081                 goto err_out_free_dev;
10082         }
10083
10084         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
10085
10086         np->regs = of_ioremap(&op->resource[1], 0,
10087                               resource_size(&op->resource[1]),
10088                               "niu regs");
10089         if (!np->regs) {
10090                 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10091                 err = -ENOMEM;
10092                 goto err_out_release_parent;
10093         }
10094
10095         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10096                                     resource_size(&op->resource[2]),
10097                                     "niu vregs-1");
10098         if (!np->vir_regs_1) {
10099                 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10100                 err = -ENOMEM;
10101                 goto err_out_iounmap;
10102         }
10103
10104         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10105                                     resource_size(&op->resource[3]),
10106                                     "niu vregs-2");
10107         if (!np->vir_regs_2) {
10108                 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10109                 err = -ENOMEM;
10110                 goto err_out_iounmap;
10111         }
10112
10113         niu_assign_netdev_ops(dev);
10114
10115         err = niu_get_invariants(np);
10116         if (err) {
10117                 if (err != -ENODEV)
10118                         dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10119                 goto err_out_iounmap;
10120         }
10121
10122         err = register_netdev(dev);
10123         if (err) {
10124                 dev_err(&op->dev, "Cannot register net device, aborting\n");
10125                 goto err_out_iounmap;
10126         }
10127
10128         dev_set_drvdata(&op->dev, dev);
10129
10130         niu_device_announce(np);
10131
10132         return 0;
10133
10134 err_out_iounmap:
10135         if (np->vir_regs_1) {
10136                 of_iounmap(&op->resource[2], np->vir_regs_1,
10137                            resource_size(&op->resource[2]));
10138                 np->vir_regs_1 = NULL;
10139         }
10140
10141         if (np->vir_regs_2) {
10142                 of_iounmap(&op->resource[3], np->vir_regs_2,
10143                            resource_size(&op->resource[3]));
10144                 np->vir_regs_2 = NULL;
10145         }
10146
10147         if (np->regs) {
10148                 of_iounmap(&op->resource[1], np->regs,
10149                            resource_size(&op->resource[1]));
10150                 np->regs = NULL;
10151         }
10152
10153 err_out_release_parent:
10154         niu_put_parent(np);
10155
10156 err_out_free_dev:
10157         free_netdev(dev);
10158
10159 err_out:
10160         return err;
10161 }
10162
10163 static int __devexit niu_of_remove(struct of_device *op)
10164 {
10165         struct net_device *dev = dev_get_drvdata(&op->dev);
10166
10167         if (dev) {
10168                 struct niu *np = netdev_priv(dev);
10169
10170                 unregister_netdev(dev);
10171
10172                 if (np->vir_regs_1) {
10173                         of_iounmap(&op->resource[2], np->vir_regs_1,
10174                                    resource_size(&op->resource[2]));
10175                         np->vir_regs_1 = NULL;
10176                 }
10177
10178                 if (np->vir_regs_2) {
10179                         of_iounmap(&op->resource[3], np->vir_regs_2,
10180                                    resource_size(&op->resource[3]));
10181                         np->vir_regs_2 = NULL;
10182                 }
10183
10184                 if (np->regs) {
10185                         of_iounmap(&op->resource[1], np->regs,
10186                                    resource_size(&op->resource[1]));
10187                         np->regs = NULL;
10188                 }
10189
10190                 niu_ldg_free(np);
10191
10192                 niu_put_parent(np);
10193
10194                 free_netdev(dev);
10195                 dev_set_drvdata(&op->dev, NULL);
10196         }
10197         return 0;
10198 }
10199
10200 static const struct of_device_id niu_match[] = {
10201         {
10202                 .name = "network",
10203                 .compatible = "SUNW,niusl",
10204         },
10205         {},
10206 };
10207 MODULE_DEVICE_TABLE(of, niu_match);
10208
10209 static struct of_platform_driver niu_of_driver = {
10210         .name           = "niu",
10211         .match_table    = niu_match,
10212         .probe          = niu_of_probe,
10213         .remove         = __devexit_p(niu_of_remove),
10214 };
10215
10216 #endif /* CONFIG_SPARC64 */
10217
10218 static int __init niu_init(void)
10219 {
10220         int err = 0;
10221
10222         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10223
10224         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10225
10226 #ifdef CONFIG_SPARC64
10227         err = of_register_driver(&niu_of_driver, &of_bus_type);
10228 #endif
10229
10230         if (!err) {
10231                 err = pci_register_driver(&niu_pci_driver);
10232 #ifdef CONFIG_SPARC64
10233                 if (err)
10234                         of_unregister_driver(&niu_of_driver);
10235 #endif
10236         }
10237
10238         return err;
10239 }
10240
10241 static void __exit niu_exit(void)
10242 {
10243         pci_unregister_driver(&niu_pci_driver);
10244 #ifdef CONFIG_SPARC64
10245         of_unregister_driver(&niu_of_driver);
10246 #endif
10247 }
10248
10249 module_init(niu_init);
10250 module_exit(niu_exit);