drivers/net/phy/marvell.c

   1 /*
   2  * drivers/net/phy/marvell.c
   3  *
   4  * Driver for Marvell PHYs
   5  *
   6  * Author: Andy Fleming
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  *
  10  * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/string.h>
  20 #include <linux/errno.h>
  21 #include <linux/unistd.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/init.h>
  24 #include <linux/delay.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/mm.h>
  30 #include <linux/module.h>
  31 #include <linux/mii.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/phy.h>
  34 #include <linux/marvell_phy.h>
  35 #include <linux/of.h>
  36
  37 #include <linux/io.h>
  38 #include <asm/irq.h>
  39 #include <linux/uaccess.h>
  40
  41 #define MII_MARVELL_PHY_PAGE            22
  42
  43 #define MII_M1011_IEVENT                0x13
  44 #define MII_M1011_IEVENT_CLEAR          0x0000
  45
  46 #define MII_M1011_IMASK                 0x12
  47 #define MII_M1011_IMASK_INIT            0x6400
  48 #define MII_M1011_IMASK_CLEAR           0x0000
  49
  50 #define MII_M1011_PHY_SCR               0x10
  51 #define MII_M1011_PHY_SCR_AUTO_CROSS    0x0060
  52
  53 #define MII_M1145_PHY_EXT_SR            0x1b
  54 #define MII_M1145_PHY_EXT_CR            0x14
  55 #define MII_M1145_RGMII_RX_DELAY        0x0080
  56 #define MII_M1145_RGMII_TX_DELAY        0x0002
  57 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK       0x4
  58 #define MII_M1145_HWCFG_MODE_MASK               0xf
  59 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO       0x8000
  60
  61 #define MII_M1111_PHY_LED_CONTROL       0x18
  62 #define MII_M1111_PHY_LED_DIRECT        0x4100
  63 #define MII_M1111_PHY_LED_COMBINE       0x411c
  64 #define MII_M1111_PHY_EXT_CR            0x14
  65 #define MII_M1111_RX_DELAY              0x80
  66 #define MII_M1111_TX_DELAY              0x2
  67 #define MII_M1111_PHY_EXT_SR            0x1b
  68
  69 #define MII_M1111_HWCFG_MODE_MASK               0xf
  70 #define MII_M1111_HWCFG_MODE_COPPER_RGMII       0xb
  71 #define MII_M1111_HWCFG_MODE_FIBER_RGMII        0x3
  72 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK       0x4
  73 #define MII_M1111_HWCFG_MODE_COPPER_RTBI        0x9
  74 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO       0x8000
  75 #define MII_M1111_HWCFG_FIBER_COPPER_RES        0x2000
  76
  77 #define MII_M1111_COPPER                0
  78 #define MII_M1111_FIBER                 1
  79
  80 #define MII_88E1121_PHY_MSCR_PAGE       2
  81 #define MII_88E1121_PHY_MSCR_REG        21
  82 #define MII_88E1121_PHY_MSCR_RX_DELAY   BIT(5)
  83 #define MII_88E1121_PHY_MSCR_TX_DELAY   BIT(4)
  84 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
  85
  86 #define MII_88E1318S_PHY_MSCR1_REG      16
  87 #define MII_88E1318S_PHY_MSCR1_PAD_ODD  BIT(6)
  88
  89 /* Copper Specific Interrupt Enable Register */
  90 #define MII_88E1318S_PHY_CSIER                              0x12
  91 /* WOL Event Interrupt Enable */
  92 #define MII_88E1318S_PHY_CSIER_WOL_EIE                      BIT(7)
  93
  94 /* LED Timer Control Register */
  95 #define MII_88E1318S_PHY_LED_PAGE                           0x03
  96 #define MII_88E1318S_PHY_LED_TCR                            0x12
  97 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT                  BIT(15)
  98 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE                BIT(7)
  99 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW             BIT(11)
 100
 101 /* Magic Packet MAC address registers */
 102 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2                 0x17
 103 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1                 0x18
 104 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0                 0x19
 105
 106 #define MII_88E1318S_PHY_WOL_PAGE                           0x11
 107 #define MII_88E1318S_PHY_WOL_CTRL                           0x10
 108 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS          BIT(12)
 109 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
 110
 111 #define MII_88E1121_PHY_LED_CTRL        16
 112 #define MII_88E1121_PHY_LED_PAGE        3
 113 #define MII_88E1121_PHY_LED_DEF         0x0030
 114
 115 #define MII_M1011_PHY_STATUS            0x11
 116 #define MII_M1011_PHY_STATUS_1000       0x8000
 117 #define MII_M1011_PHY_STATUS_100        0x4000
 118 #define MII_M1011_PHY_STATUS_SPD_MASK   0xc000
 119 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
 120 #define MII_M1011_PHY_STATUS_RESOLVED   0x0800
 121 #define MII_M1011_PHY_STATUS_LINK       0x0400
 122
 123 #define MII_M1116R_CONTROL_REG_MAC      21
 124
 125 #define MII_88E3016_PHY_SPEC_CTRL       0x10
 126 #define MII_88E3016_DISABLE_SCRAMBLER   0x0200
 127 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
 128
 129 MODULE_DESCRIPTION("Marvell PHY driver");
 130 MODULE_AUTHOR("Andy Fleming");
 131 MODULE_LICENSE("GPL");
 132
 133 static int marvell_ack_interrupt(struct phy_device *phydev)
 134 {
 135         int err;
 136
 137         /* Clear the interrupts by reading the reg */
 138         err = phy_read(phydev, MII_M1011_IEVENT);
 139
 140         if (err < 0)
 141                 return err;
 142
 143         return 0;
 144 }
 145
 146 static int marvell_config_intr(struct phy_device *phydev)
 147 {
 148         int err;
 149
 150         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 151                 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 152         else
 153                 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
 154
 155         return err;
 156 }
 157
 158 static int marvell_config_aneg(struct phy_device *phydev)
 159 {
 160         int err;
 161
 162         /* The Marvell PHY has an errata which requires
 163          * that certain registers get written in order
 164          * to restart autonegotiation */
 165         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 166
 167         if (err < 0)
 168                 return err;
 169
 170         err = phy_write(phydev, 0x1d, 0x1f);
 171         if (err < 0)
 172                 return err;
 173
 174         err = phy_write(phydev, 0x1e, 0x200c);
 175         if (err < 0)
 176                 return err;
 177
 178         err = phy_write(phydev, 0x1d, 0x5);
 179         if (err < 0)
 180                 return err;
 181
 182         err = phy_write(phydev, 0x1e, 0);
 183         if (err < 0)
 184                 return err;
 185
 186         err = phy_write(phydev, 0x1e, 0x100);
 187         if (err < 0)
 188                 return err;
 189
 190         err = phy_write(phydev, MII_M1011_PHY_SCR,
 191                         MII_M1011_PHY_SCR_AUTO_CROSS);
 192         if (err < 0)
 193                 return err;
 194
 195         err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
 196                         MII_M1111_PHY_LED_DIRECT);
 197         if (err < 0)
 198                 return err;
 199
 200         err = genphy_config_aneg(phydev);
 201         if (err < 0)
 202                 return err;
 203
 204         if (phydev->autoneg != AUTONEG_ENABLE) {
 205                 int bmcr;
 206
 207                 /*
 208                  * A write to speed/duplex bits (that is performed by
 209                  * genphy_config_aneg() call above) must be followed by
 210                  * a software reset. Otherwise, the write has no effect.
 211                  */
 212                 bmcr = phy_read(phydev, MII_BMCR);
 213                 if (bmcr < 0)
 214                         return bmcr;
 215
 216                 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
 217                 if (err < 0)
 218                         return err;
 219         }
 220
 221         return 0;
 222 }
 223
 224 #ifdef CONFIG_OF_MDIO
 225 /*
 226  * Set and/or override some configuration registers based on the
 227  * marvell,reg-init property stored in the of_node for the phydev.
 228  *
 229  * marvell,reg-init = <reg-page reg mask value>,...;
 230  *
 231  * There may be one or more sets of <reg-page reg mask value>:
 232  *
 233  * reg-page: which register bank to use.
 234  * reg: the register.
 235  * mask: if non-zero, ANDed with existing register value.
 236  * value: ORed with the masked value and written to the regiser.
 237  *
 238  */
 239 static int marvell_of_reg_init(struct phy_device *phydev)
 240 {
 241         const __be32 *paddr;
 242         int len, i, saved_page, current_page, page_changed, ret;
 243
 244         if (!phydev->dev.of_node)
 245                 return 0;
 246
 247         paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
 248         if (!paddr || len < (4 * sizeof(*paddr)))
 249                 return 0;
 250
 251         saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 252         if (saved_page < 0)
 253                 return saved_page;
 254         page_changed = 0;
 255         current_page = saved_page;
 256
 257         ret = 0;
 258         len /= sizeof(*paddr);
 259         for (i = 0; i < len - 3; i += 4) {
 260                 u16 reg_page = be32_to_cpup(paddr + i);
 261                 u16 reg = be32_to_cpup(paddr + i + 1);
 262                 u16 mask = be32_to_cpup(paddr + i + 2);
 263                 u16 val_bits = be32_to_cpup(paddr + i + 3);
 264                 int val;
 265
 266                 if (reg_page != current_page) {
 267                         current_page = reg_page;
 268                         page_changed = 1;
 269                         ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
 270                         if (ret < 0)
 271                                 goto err;
 272                 }
 273
 274                 val = 0;
 275                 if (mask) {
 276                         val = phy_read(phydev, reg);
 277                         if (val < 0) {
 278                                 ret = val;
 279                                 goto err;
 280                         }
 281                         val &= mask;
 282                 }
 283                 val |= val_bits;
 284
 285                 ret = phy_write(phydev, reg, val);
 286                 if (ret < 0)
 287                         goto err;
 288
 289         }
 290 err:
 291         if (page_changed) {
 292                 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
 293                 if (ret == 0)
 294                         ret = i;
 295         }
 296         return ret;
 297 }
 298 #else
 299 static int marvell_of_reg_init(struct phy_device *phydev)
 300 {
 301         return 0;
 302 }
 303 #endif /* CONFIG_OF_MDIO */
 304
 305 static int m88e1121_config_aneg(struct phy_device *phydev)
 306 {
 307         int err, oldpage, mscr;
 308
 309         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 310
 311         err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 312                         MII_88E1121_PHY_MSCR_PAGE);
 313         if (err < 0)
 314                 return err;
 315
 316         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
 317             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 318             (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 319             (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 320
 321                 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
 322                         MII_88E1121_PHY_MSCR_DELAY_MASK;
 323
 324                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 325                         mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
 326                                  MII_88E1121_PHY_MSCR_TX_DELAY);
 327                 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 328                         mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
 329                 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 330                         mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
 331
 332                 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
 333                 if (err < 0)
 334                         return err;
 335         }
 336
 337         phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 338
 339         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 340         if (err < 0)
 341                 return err;
 342
 343         err = phy_write(phydev, MII_M1011_PHY_SCR,
 344                         MII_M1011_PHY_SCR_AUTO_CROSS);
 345         if (err < 0)
 346                 return err;
 347
 348         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 349
 350         phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
 351         phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
 352         phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 353
 354         err = genphy_config_aneg(phydev);
 355
 356         return err;
 357 }
 358
 359 static int m88e1318_config_aneg(struct phy_device *phydev)
 360 {
 361         int err, oldpage, mscr;
 362
 363         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 364
 365         err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 366                         MII_88E1121_PHY_MSCR_PAGE);
 367         if (err < 0)
 368                 return err;
 369
 370         mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
 371         mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
 372
 373         err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
 374         if (err < 0)
 375                 return err;
 376
 377         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 378         if (err < 0)
 379                 return err;
 380
 381         return m88e1121_config_aneg(phydev);
 382 }
 383
 384 static int m88e1510_config_aneg(struct phy_device *phydev)
 385 {
 386         int err;
 387
 388         err = m88e1318_config_aneg(phydev);
 389         if (err < 0)
 390                 return err;
 391
 392         return marvell_of_reg_init(phydev);
 393 }
 394
 395 static int m88e1116r_config_init(struct phy_device *phydev)
 396 {
 397         int temp;
 398         int err;
 399
 400         temp = phy_read(phydev, MII_BMCR);
 401         temp |= BMCR_RESET;
 402         err = phy_write(phydev, MII_BMCR, temp);
 403         if (err < 0)
 404                 return err;
 405
 406         mdelay(500);
 407
 408         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
 409         if (err < 0)
 410                 return err;
 411
 412         temp = phy_read(phydev, MII_M1011_PHY_SCR);
 413         temp |= (7 << 12);      /* max number of gigabit attempts */
 414         temp |= (1 << 11);      /* enable downshift */
 415         temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
 416         err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
 417         if (err < 0)
 418                 return err;
 419
 420         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
 421         if (err < 0)
 422                 return err;
 423         temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
 424         temp |= (1 << 5);
 425         temp |= (1 << 4);
 426         err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
 427         if (err < 0)
 428                 return err;
 429         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
 430         if (err < 0)
 431                 return err;
 432
 433         temp = phy_read(phydev, MII_BMCR);
 434         temp |= BMCR_RESET;
 435         err = phy_write(phydev, MII_BMCR, temp);
 436         if (err < 0)
 437                 return err;
 438
 439         mdelay(500);
 440
 441         return 0;
 442 }
 443
 444 static int m88e3016_config_init(struct phy_device *phydev)
 445 {
 446         int reg;
 447
 448         /* Enable Scrambler and Auto-Crossover */
 449         reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
 450         if (reg < 0)
 451                 return reg;
 452
 453         reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
 454         reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
 455
 456         reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
 457         if (reg < 0)
 458                 return reg;
 459
 460         return 0;
 461 }
 462
 463 static int m88e1111_config_init(struct phy_device *phydev)
 464 {
 465         int err;
 466         int temp;
 467
 468         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
 469             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 470             (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 471             (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 472
 473                 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
 474                 if (temp < 0)
 475                         return temp;
 476
 477                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 478                         temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
 479                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
 480                         temp &= ~MII_M1111_TX_DELAY;
 481                         temp |= MII_M1111_RX_DELAY;
 482                 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 483                         temp &= ~MII_M1111_RX_DELAY;
 484                         temp |= MII_M1111_TX_DELAY;
 485                 }
 486
 487                 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
 488                 if (err < 0)
 489                         return err;
 490
 491                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 492                 if (temp < 0)
 493                         return temp;
 494
 495                 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
 496
 497                 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
 498                         temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
 499                 else
 500                         temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
 501
 502                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 503                 if (err < 0)
 504                         return err;
 505         }
 506
 507         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 508                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 509                 if (temp < 0)
 510                         return temp;
 511
 512                 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
 513                 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
 514                 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 515
 516                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 517                 if (err < 0)
 518                         return err;
 519         }
 520
 521         if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
 522                 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
 523                 if (temp < 0)
 524                         return temp;
 525                 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
 526                 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
 527                 if (err < 0)
 528                         return err;
 529
 530                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 531                 if (temp < 0)
 532                         return temp;
 533                 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
 534                 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 535                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 536                 if (err < 0)
 537                         return err;
 538
 539                 /* soft reset */
 540                 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 541                 if (err < 0)
 542                         return err;
 543                 do
 544                         temp = phy_read(phydev, MII_BMCR);
 545                 while (temp & BMCR_RESET);
 546
 547                 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
 548                 if (temp < 0)
 549                         return temp;
 550                 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
 551                 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
 552                 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
 553                 if (err < 0)
 554                         return err;
 555         }
 556
 557         err = marvell_of_reg_init(phydev);
 558         if (err < 0)
 559                 return err;
 560
 561         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 562 }
 563
 564 static int m88e1118_config_aneg(struct phy_device *phydev)
 565 {
 566         int err;
 567
 568         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 569         if (err < 0)
 570                 return err;
 571
 572         err = phy_write(phydev, MII_M1011_PHY_SCR,
 573                         MII_M1011_PHY_SCR_AUTO_CROSS);
 574         if (err < 0)
 575                 return err;
 576
 577         err = genphy_config_aneg(phydev);
 578         return 0;
 579 }
 580
 581 static int m88e1118_config_init(struct phy_device *phydev)
 582 {
 583         int err;
 584
 585         /* Change address */
 586         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
 587         if (err < 0)
 588                 return err;
 589
 590         /* Enable 1000 Mbit */
 591         err = phy_write(phydev, 0x15, 0x1070);
 592         if (err < 0)
 593                 return err;
 594
 595         /* Change address */
 596         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
 597         if (err < 0)
 598                 return err;
 599
 600         /* Adjust LED Control */
 601         if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
 602                 err = phy_write(phydev, 0x10, 0x1100);
 603         else
 604                 err = phy_write(phydev, 0x10, 0x021e);
 605         if (err < 0)
 606                 return err;
 607
 608         err = marvell_of_reg_init(phydev);
 609         if (err < 0)
 610                 return err;
 611
 612         /* Reset address */
 613         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
 614         if (err < 0)
 615                 return err;
 616
 617         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 618 }
 619
 620 static int m88e1149_config_init(struct phy_device *phydev)
 621 {
 622         int err;
 623
 624         /* Change address */
 625         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
 626         if (err < 0)
 627                 return err;
 628
 629         /* Enable 1000 Mbit */
 630         err = phy_write(phydev, 0x15, 0x1048);
 631         if (err < 0)
 632                 return err;
 633
 634         err = marvell_of_reg_init(phydev);
 635         if (err < 0)
 636                 return err;
 637
 638         /* Reset address */
 639         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
 640         if (err < 0)
 641                 return err;
 642
 643         return phy_write(phydev, MII_BMCR, BMCR_RESET);
 644 }
 645
 646 static int m88e1145_config_init(struct phy_device *phydev)
 647 {
 648         int err;
 649         int temp;
 650
 651         /* Take care of errata E0 & E1 */
 652         err = phy_write(phydev, 0x1d, 0x001b);
 653         if (err < 0)
 654                 return err;
 655
 656         err = phy_write(phydev, 0x1e, 0x418f);
 657         if (err < 0)
 658                 return err;
 659
 660         err = phy_write(phydev, 0x1d, 0x0016);
 661         if (err < 0)
 662                 return err;
 663
 664         err = phy_write(phydev, 0x1e, 0xa2da);
 665         if (err < 0)
 666                 return err;
 667
 668         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
 669                 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
 670                 if (temp < 0)
 671                         return temp;
 672
 673                 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
 674
 675                 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
 676                 if (err < 0)
 677                         return err;
 678
 679                 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
 680                         err = phy_write(phydev, 0x1d, 0x0012);
 681                         if (err < 0)
 682                                 return err;
 683
 684                         temp = phy_read(phydev, 0x1e);
 685                         if (temp < 0)
 686                                 return temp;
 687
 688                         temp &= 0xf03f;
 689                         temp |= 2 << 9; /* 36 ohm */
 690                         temp |= 2 << 6; /* 39 ohm */
 691
 692                         err = phy_write(phydev, 0x1e, temp);
 693                         if (err < 0)
 694                                 return err;
 695
 696                         err = phy_write(phydev, 0x1d, 0x3);
 697                         if (err < 0)
 698                                 return err;
 699
 700                         err = phy_write(phydev, 0x1e, 0x8000);
 701                         if (err < 0)
 702                                 return err;
 703                 }
 704         }
 705
 706         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 707                 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
 708                 if (temp < 0)
 709                         return temp;
 710
 711                 temp &= ~(MII_M1145_HWCFG_MODE_MASK);
 712                 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
 713                 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
 714
 715                 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
 716                 if (err < 0)
 717                         return err;
 718         }
 719
 720         err = marvell_of_reg_init(phydev);
 721         if (err < 0)
 722                 return err;
 723
 724         return 0;
 725 }
 726
 727 /* marvell_read_status
 728  *
 729  * Generic status code does not detect Fiber correctly!
 730  * Description:
 731  *   Check the link, then figure out the current state
 732  *   by comparing what we advertise with what the link partner
 733  *   advertises.  Start by checking the gigabit possibilities,
 734  *   then move on to 10/100.
 735  */
 736 static int marvell_read_status(struct phy_device *phydev)
 737 {
 738         int adv;
 739         int err;
 740         int lpa;
 741         int status = 0;
 742
 743         /* Update the link, but return if there
 744          * was an error */
 745         err = genphy_update_link(phydev);
 746         if (err)
 747                 return err;
 748
 749         if (AUTONEG_ENABLE == phydev->autoneg) {
 750                 status = phy_read(phydev, MII_M1011_PHY_STATUS);
 751                 if (status < 0)
 752                         return status;
 753
 754                 lpa = phy_read(phydev, MII_LPA);
 755                 if (lpa < 0)
 756                         return lpa;
 757
 758                 adv = phy_read(phydev, MII_ADVERTISE);
 759                 if (adv < 0)
 760                         return adv;
 761
 762                 lpa &= adv;
 763
 764                 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
 765                         phydev->duplex = DUPLEX_FULL;
 766                 else
 767                         phydev->duplex = DUPLEX_HALF;
 768
 769                 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
 770                 phydev->pause = phydev->asym_pause = 0;
 771
 772                 switch (status) {
 773                 case MII_M1011_PHY_STATUS_1000:
 774                         phydev->speed = SPEED_1000;
 775                         break;
 776
 777                 case MII_M1011_PHY_STATUS_100:
 778                         phydev->speed = SPEED_100;
 779                         break;
 780
 781                 default:
 782                         phydev->speed = SPEED_10;
 783                         break;
 784                 }
 785
 786                 if (phydev->duplex == DUPLEX_FULL) {
 787                         phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
 788                         phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
 789                 }
 790         } else {
 791                 int bmcr = phy_read(phydev, MII_BMCR);
 792
 793                 if (bmcr < 0)
 794                         return bmcr;
 795
 796                 if (bmcr & BMCR_FULLDPLX)
 797                         phydev->duplex = DUPLEX_FULL;
 798                 else
 799                         phydev->duplex = DUPLEX_HALF;
 800
 801                 if (bmcr & BMCR_SPEED1000)
 802                         phydev->speed = SPEED_1000;
 803                 else if (bmcr & BMCR_SPEED100)
 804                         phydev->speed = SPEED_100;
 805                 else
 806                         phydev->speed = SPEED_10;
 807
 808                 phydev->pause = phydev->asym_pause = 0;
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int marvell_aneg_done(struct phy_device *phydev)
 815 {
 816         int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
 817         return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
 818 }
 819
 820 static int m88e1121_did_interrupt(struct phy_device *phydev)
 821 {
 822         int imask;
 823
 824         imask = phy_read(phydev, MII_M1011_IEVENT);
 825
 826         if (imask & MII_M1011_IMASK_INIT)
 827                 return 1;
 828
 829         return 0;
 830 }
 831
 832 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 833 {
 834         wol->supported = WAKE_MAGIC;
 835         wol->wolopts = 0;
 836
 837         if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
 838                       MII_88E1318S_PHY_WOL_PAGE) < 0)
 839                 return;
 840
 841         if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
 842             MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
 843                 wol->wolopts |= WAKE_MAGIC;
 844
 845         if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
 846                 return;
 847 }
 848
 849 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
 850 {
 851         int err, oldpage, temp;
 852
 853         oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
 854
 855         if (wol->wolopts & WAKE_MAGIC) {
 856                 /* Explicitly switch to page 0x00, just to be sure */
 857                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
 858                 if (err < 0)
 859                         return err;
 860
 861                 /* Enable the WOL interrupt */
 862                 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
 863                 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
 864                 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
 865                 if (err < 0)
 866                         return err;
 867
 868                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 869                                 MII_88E1318S_PHY_LED_PAGE);
 870                 if (err < 0)
 871                         return err;
 872
 873                 /* Setup LED[2] as interrupt pin (active low) */
 874                 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
 875                 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
 876                 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
 877                 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
 878                 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
 879                 if (err < 0)
 880                         return err;
 881
 882                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 883                                 MII_88E1318S_PHY_WOL_PAGE);
 884                 if (err < 0)
 885                         return err;
 886
 887                 /* Store the device address for the magic packet */
 888                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
 889                                 ((phydev->attached_dev->dev_addr[5] << 8) |
 890                                  phydev->attached_dev->dev_addr[4]));
 891                 if (err < 0)
 892                         return err;
 893                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
 894                                 ((phydev->attached_dev->dev_addr[3] << 8) |
 895                                  phydev->attached_dev->dev_addr[2]));
 896                 if (err < 0)
 897                         return err;
 898                 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
 899                                 ((phydev->attached_dev->dev_addr[1] << 8) |
 900                                  phydev->attached_dev->dev_addr[0]));
 901                 if (err < 0)
 902                         return err;
 903
 904                 /* Clear WOL status and enable magic packet matching */
 905                 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
 906                 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
 907                 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
 908                 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
 909                 if (err < 0)
 910                         return err;
 911         } else {
 912                 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
 913                                 MII_88E1318S_PHY_WOL_PAGE);
 914                 if (err < 0)
 915                         return err;
 916
 917                 /* Clear WOL status and disable magic packet matching */
 918                 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
 919                 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
 920                 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
 921                 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
 922                 if (err < 0)
 923                         return err;
 924         }
 925
 926         err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
 927         if (err < 0)
 928                 return err;
 929
 930         return 0;
 931 }
 932
 933 static struct phy_driver marvell_drivers[] = {
 934         {
 935                 .phy_id = MARVELL_PHY_ID_88E1101,
 936                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 937                 .name = "Marvell 88E1101",
 938                 .features = PHY_GBIT_FEATURES,
 939                 .flags = PHY_HAS_INTERRUPT,
 940                 .config_aneg = &marvell_config_aneg,
 941                 .read_status = &genphy_read_status,
 942                 .ack_interrupt = &marvell_ack_interrupt,
 943                 .config_intr = &marvell_config_intr,
 944                 .resume = &genphy_resume,
 945                 .suspend = &genphy_suspend,
 946                 .driver = { .owner = THIS_MODULE },
 947         },
 948         {
 949                 .phy_id = MARVELL_PHY_ID_88E1112,
 950                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 951                 .name = "Marvell 88E1112",
 952                 .features = PHY_GBIT_FEATURES,
 953                 .flags = PHY_HAS_INTERRUPT,
 954                 .config_init = &m88e1111_config_init,
 955                 .config_aneg = &marvell_config_aneg,
 956                 .read_status = &genphy_read_status,
 957                 .ack_interrupt = &marvell_ack_interrupt,
 958                 .config_intr = &marvell_config_intr,
 959                 .resume = &genphy_resume,
 960                 .suspend = &genphy_suspend,
 961                 .driver = { .owner = THIS_MODULE },
 962         },
 963         {
 964                 .phy_id = MARVELL_PHY_ID_88E1111,
 965                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 966                 .name = "Marvell 88E1111",
 967                 .features = PHY_GBIT_FEATURES,
 968                 .flags = PHY_HAS_INTERRUPT,
 969                 .config_init = &m88e1111_config_init,
 970                 .config_aneg = &marvell_config_aneg,
 971                 .read_status = &marvell_read_status,
 972                 .ack_interrupt = &marvell_ack_interrupt,
 973                 .config_intr = &marvell_config_intr,
 974                 .resume = &genphy_resume,
 975                 .suspend = &genphy_suspend,
 976                 .driver = { .owner = THIS_MODULE },
 977         },
 978         {
 979                 .phy_id = MARVELL_PHY_ID_88E1118,
 980                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 981                 .name = "Marvell 88E1118",
 982                 .features = PHY_GBIT_FEATURES,
 983                 .flags = PHY_HAS_INTERRUPT,
 984                 .config_init = &m88e1118_config_init,
 985                 .config_aneg = &m88e1118_config_aneg,
 986                 .read_status = &genphy_read_status,
 987                 .ack_interrupt = &marvell_ack_interrupt,
 988                 .config_intr = &marvell_config_intr,
 989                 .resume = &genphy_resume,
 990                 .suspend = &genphy_suspend,
 991                 .driver = {.owner = THIS_MODULE,},
 992         },
 993         {
 994                 .phy_id = MARVELL_PHY_ID_88E1121R,
 995                 .phy_id_mask = MARVELL_PHY_ID_MASK,
 996                 .name = "Marvell 88E1121R",
 997                 .features = PHY_GBIT_FEATURES,
 998                 .flags = PHY_HAS_INTERRUPT,
 999                 .config_aneg = &m88e1121_config_aneg,
1000                 .read_status = &marvell_read_status,
1001                 .ack_interrupt = &marvell_ack_interrupt,
1002                 .config_intr = &marvell_config_intr,
1003                 .did_interrupt = &m88e1121_did_interrupt,
1004                 .resume = &genphy_resume,
1005                 .suspend = &genphy_suspend,
1006                 .driver = { .owner = THIS_MODULE },
1007         },
1008         {
1009                 .phy_id = MARVELL_PHY_ID_88E1318S,
1010                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1011                 .name = "Marvell 88E1318S",
1012                 .features = PHY_GBIT_FEATURES,
1013                 .flags = PHY_HAS_INTERRUPT,
1014                 .config_aneg = &m88e1318_config_aneg,
1015                 .read_status = &marvell_read_status,
1016                 .ack_interrupt = &marvell_ack_interrupt,
1017                 .config_intr = &marvell_config_intr,
1018                 .did_interrupt = &m88e1121_did_interrupt,
1019                 .get_wol = &m88e1318_get_wol,
1020                 .set_wol = &m88e1318_set_wol,
1021                 .resume = &genphy_resume,
1022                 .suspend = &genphy_suspend,
1023                 .driver = { .owner = THIS_MODULE },
1024         },
1025         {
1026                 .phy_id = MARVELL_PHY_ID_88E1145,
1027                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1028                 .name = "Marvell 88E1145",
1029                 .features = PHY_GBIT_FEATURES,
1030                 .flags = PHY_HAS_INTERRUPT,
1031                 .config_init = &m88e1145_config_init,
1032                 .config_aneg = &marvell_config_aneg,
1033                 .read_status = &genphy_read_status,
1034                 .ack_interrupt = &marvell_ack_interrupt,
1035                 .config_intr = &marvell_config_intr,
1036                 .resume = &genphy_resume,
1037                 .suspend = &genphy_suspend,
1038                 .driver = { .owner = THIS_MODULE },
1039         },
1040         {
1041                 .phy_id = MARVELL_PHY_ID_88E1149R,
1042                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1043                 .name = "Marvell 88E1149R",
1044                 .features = PHY_GBIT_FEATURES,
1045                 .flags = PHY_HAS_INTERRUPT,
1046                 .config_init = &m88e1149_config_init,
1047                 .config_aneg = &m88e1118_config_aneg,
1048                 .read_status = &genphy_read_status,
1049                 .ack_interrupt = &marvell_ack_interrupt,
1050                 .config_intr = &marvell_config_intr,
1051                 .resume = &genphy_resume,
1052                 .suspend = &genphy_suspend,
1053                 .driver = { .owner = THIS_MODULE },
1054         },
1055         {
1056                 .phy_id = MARVELL_PHY_ID_88E1240,
1057                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1058                 .name = "Marvell 88E1240",
1059                 .features = PHY_GBIT_FEATURES,
1060                 .flags = PHY_HAS_INTERRUPT,
1061                 .config_init = &m88e1111_config_init,
1062                 .config_aneg = &marvell_config_aneg,
1063                 .read_status = &genphy_read_status,
1064                 .ack_interrupt = &marvell_ack_interrupt,
1065                 .config_intr = &marvell_config_intr,
1066                 .resume = &genphy_resume,
1067                 .suspend = &genphy_suspend,
1068                 .driver = { .owner = THIS_MODULE },
1069         },
1070         {
1071                 .phy_id = MARVELL_PHY_ID_88E1116R,
1072                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1073                 .name = "Marvell 88E1116R",
1074                 .features = PHY_GBIT_FEATURES,
1075                 .flags = PHY_HAS_INTERRUPT,
1076                 .config_init = &m88e1116r_config_init,
1077                 .config_aneg = &genphy_config_aneg,
1078                 .read_status = &genphy_read_status,
1079                 .ack_interrupt = &marvell_ack_interrupt,
1080                 .config_intr = &marvell_config_intr,
1081                 .resume = &genphy_resume,
1082                 .suspend = &genphy_suspend,
1083                 .driver = { .owner = THIS_MODULE },
1084         },
1085         {
1086                 .phy_id = MARVELL_PHY_ID_88E1510,
1087                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1088                 .name = "Marvell 88E1510",
1089                 .features = PHY_GBIT_FEATURES,
1090                 .flags = PHY_HAS_INTERRUPT,
1091                 .config_aneg = &m88e1510_config_aneg,
1092                 .read_status = &marvell_read_status,
1093                 .ack_interrupt = &marvell_ack_interrupt,
1094                 .config_intr = &marvell_config_intr,
1095                 .did_interrupt = &m88e1121_did_interrupt,
1096                 .resume = &genphy_resume,
1097                 .suspend = &genphy_suspend,
1098                 .driver = { .owner = THIS_MODULE },
1099         },
1100         {
1101                 .phy_id = MARVELL_PHY_ID_88E3016,
1102                 .phy_id_mask = MARVELL_PHY_ID_MASK,
1103                 .name = "Marvell 88E3016",
1104                 .features = PHY_BASIC_FEATURES,
1105                 .flags = PHY_HAS_INTERRUPT,
1106                 .config_aneg = &genphy_config_aneg,
1107                 .config_init = &m88e3016_config_init,
1108                 .aneg_done = &marvell_aneg_done,
1109                 .read_status = &marvell_read_status,
1110                 .ack_interrupt = &marvell_ack_interrupt,
1111                 .config_intr = &marvell_config_intr,
1112                 .did_interrupt = &m88e1121_did_interrupt,
1113                 .resume = &genphy_resume,
1114                 .suspend = &genphy_suspend,
1115                 .driver = { .owner = THIS_MODULE },
1116         },
1117 };
1118
1119 static int __init marvell_init(void)
1120 {
1121         return phy_drivers_register(marvell_drivers,
1122                  ARRAY_SIZE(marvell_drivers));
1123 }
1124
1125 static void __exit marvell_exit(void)
1126 {
1127         phy_drivers_unregister(marvell_drivers,
1128                  ARRAY_SIZE(marvell_drivers));
1129 }
1130
1131 module_init(marvell_init);
1132 module_exit(marvell_exit);
1133
1134 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1135         { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1136         { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1137         { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1138         { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1139         { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1140         { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1141         { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1142         { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1143         { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1144         { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1145         { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1146         { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1147         { }
1148 };
1149
1150 MODULE_DEVICE_TABLE(mdio, marvell_tbl);