1 /************************************************************************
2 * regs.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
18 typedef struct _XENA_dev_config {
19 /* Convention: mHAL_XXX is mask, vHAL_XXX is value */
21 /* General Control-Status Registers */
22 u64 general_int_status;
23 #define GEN_INTR_TXPIC BIT(0)
24 #define GEN_INTR_TXDMA BIT(1)
25 #define GEN_INTR_TXMAC BIT(2)
26 #define GEN_INTR_TXXGXS BIT(3)
27 #define GEN_INTR_TXTRAFFIC BIT(8)
28 #define GEN_INTR_RXPIC BIT(32)
29 #define GEN_INTR_RXDMA BIT(33)
30 #define GEN_INTR_RXMAC BIT(34)
31 #define GEN_INTR_MC BIT(35)
32 #define GEN_INTR_RXXGXS BIT(36)
33 #define GEN_INTR_RXTRAFFIC BIT(40)
34 #define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
35 GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
36 GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
37 GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
42 u8 unused0[0x100 - 0x10];
45 /* XGXS must be removed from reset only once. */
46 #define SW_RESET_XENA vBIT(0xA5,0,8)
47 #define SW_RESET_FLASH vBIT(0xA5,8,8)
48 #define SW_RESET_EOI vBIT(0xA5,16,8)
49 #define SW_RESET_ALL (SW_RESET_XENA | \
52 /* The SW_RESET register must read this value after a successful reset. */
53 #define SW_RESET_RAW_VAL 0xA5000000
57 #define ADAPTER_STATUS_TDMA_READY BIT(0)
58 #define ADAPTER_STATUS_RDMA_READY BIT(1)
59 #define ADAPTER_STATUS_PFC_READY BIT(2)
60 #define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
61 #define ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
62 #define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
63 #define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
64 #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
65 #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
66 #define ADAPTER_STATUS_MC_DRAM_READY BIT(24)
67 #define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
68 #define ADAPTER_STATUS_M_PLL_LOCK BIT(30)
69 #define ADAPTER_STATUS_P_PLL_LOCK BIT(31)
72 #define ADAPTER_CNTL_EN BIT(7)
73 #define ADAPTER_EOI_TX_ON BIT(15)
74 #define ADAPTER_LED_ON BIT(23)
75 #define ADAPTER_UDPI(val) vBIT(val,36,4)
76 #define ADAPTER_WAIT_INT BIT(48)
77 #define ADAPTER_ECC_EN BIT(55)
80 #define SERR_SOURCE_PIC BIT(0)
81 #define SERR_SOURCE_TXDMA BIT(1)
82 #define SERR_SOURCE_RXDMA BIT(2)
83 #define SERR_SOURCE_MAC BIT(3)
84 #define SERR_SOURCE_MC BIT(4)
85 #define SERR_SOURCE_XGXS BIT(5)
86 #define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
93 u8 unused_0[0x800 - 0x120];
95 /* PCI-X Controller registers */
98 #define PIC_INT_TX BIT(0)
99 #define PIC_INT_FLSH BIT(1)
100 #define PIC_INT_MDIO BIT(2)
101 #define PIC_INT_IIC BIT(3)
102 #define PIC_INT_GPIO BIT(4)
103 #define PIC_INT_RX BIT(32)
107 #define PCIX_INT_REG_ECC_SG_ERR BIT(0)
108 #define PCIX_INT_REG_ECC_DB_ERR BIT(1)
109 #define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
110 #define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
111 #define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
112 #define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
113 #define PCIX_INT_REG_TRT_FSM_SERR BIT(13)
114 #define PCIX_INT_REG_SRT_FSM_SERR BIT(14)
115 #define PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
116 #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
117 #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
118 #define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
119 #define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
121 #define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
122 #define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
123 #define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
132 #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
133 #define PIC_FLSH_INT_REG_ERR BIT(62)
138 #define MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
139 #define MDIO_INT_REG_DTX_BUS_ERR BIT(8)
140 #define MDIO_INT_REG_LASI BIT(39)
145 #define IIC_INT_REG_BUS_FSM_ERR BIT(4)
146 #define IIC_INT_REG_BIT_FSM_ERR BIT(5)
147 #define IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
148 #define IIC_INT_REG_REQ_FSM_ERR BIT(7)
149 #define IIC_INT_REG_ACK_ERR BIT(8)
161 #define TX_TRAFFIC_INT_n(n) BIT(n)
165 #define RX_TRAFFIC_INT_n(n) BIT(n)
168 /* PIC Control registers */
170 #define PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
171 #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4)
174 #define SWAPPER_CTRL_PIF_R_FE BIT(0)
175 #define SWAPPER_CTRL_PIF_R_SE BIT(1)
176 #define SWAPPER_CTRL_PIF_W_FE BIT(8)
177 #define SWAPPER_CTRL_PIF_W_SE BIT(9)
178 #define SWAPPER_CTRL_TXP_FE BIT(16)
179 #define SWAPPER_CTRL_TXP_SE BIT(17)
180 #define SWAPPER_CTRL_TXD_R_FE BIT(18)
181 #define SWAPPER_CTRL_TXD_R_SE BIT(19)
182 #define SWAPPER_CTRL_TXD_W_FE BIT(20)
183 #define SWAPPER_CTRL_TXD_W_SE BIT(21)
184 #define SWAPPER_CTRL_TXF_R_FE BIT(22)
185 #define SWAPPER_CTRL_TXF_R_SE BIT(23)
186 #define SWAPPER_CTRL_RXD_R_FE BIT(32)
187 #define SWAPPER_CTRL_RXD_R_SE BIT(33)
188 #define SWAPPER_CTRL_RXD_W_FE BIT(34)
189 #define SWAPPER_CTRL_RXD_W_SE BIT(35)
190 #define SWAPPER_CTRL_RXF_W_FE BIT(36)
191 #define SWAPPER_CTRL_RXF_W_SE BIT(37)
192 #define SWAPPER_CTRL_XMSI_FE BIT(40)
193 #define SWAPPER_CTRL_XMSI_SE BIT(41)
194 #define SWAPPER_CTRL_STATS_FE BIT(48)
195 #define SWAPPER_CTRL_STATS_SE BIT(49)
197 u64 pif_rd_swapper_fb;
198 #define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
200 u64 scheduled_int_ctrl;
201 #define SCHED_INT_CTRL_TIMER_EN BIT(0)
202 #define SCHED_INT_CTRL_ONE_SHOT BIT(1)
203 #define SCHED_INT_CTRL_INT2MSI TBD
204 #define SCHED_INT_PERIOD TBD
207 #define TXREQTO_VAL(val) vBIT(val,0,32)
208 #define TXREQTO_EN BIT(63)
211 #define STATREQTO_VAL(n) TBD
212 #define STATREQTO_EN BIT(63)
214 u64 read_retry_delay;
215 u64 read_retry_acceleration;
216 u64 write_retry_delay;
217 u64 write_retry_acceleration;
239 /* Automated statistics collection */
241 #define STAT_CFG_STAT_EN BIT(0)
242 #define STAT_CFG_ONE_SHOT_EN BIT(1)
243 #define STAT_CFG_STAT_NS_EN BIT(8)
244 #define STAT_CFG_STAT_RO BIT(9)
245 #define STAT_TRSF_PER(n) TBD
246 #define PER_SEC 0x208d5
247 #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
251 /* General Configuration */
257 #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
258 #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
259 #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
260 #define I2C_CONTROL_READ BIT(24)
261 #define I2C_CONTROL_NACK BIT(25)
262 #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
263 #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
264 #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
265 #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
268 #define GPIO_CTRL_GPIO_0 BIT(8)
272 /* TxDMA registers */
273 u64 txdma_int_status;
275 #define TXDMA_PFC_INT BIT(0)
276 #define TXDMA_TDA_INT BIT(1)
277 #define TXDMA_PCC_INT BIT(2)
278 #define TXDMA_TTI_INT BIT(3)
279 #define TXDMA_LSO_INT BIT(4)
280 #define TXDMA_TPA_INT BIT(5)
281 #define TXDMA_SM_INT BIT(6)
291 #define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)
312 u8 unused8[0x100 - 0xB8];
315 u64 tx_dma_wrap_stat;
317 /* Tx FIFO controller */
318 #define X_MAX_FIFOS 8
319 #define X_FIFO_MAX_LEN 0x1FFF /*8191 */
320 u64 tx_fifo_partition_0;
321 #define TX_FIFO_PARTITION_EN BIT(0)
322 #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
323 #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
324 #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
325 #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
327 u64 tx_fifo_partition_1;
328 #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
329 #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
330 #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
331 #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
333 u64 tx_fifo_partition_2;
334 #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
335 #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
336 #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
337 #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
339 u64 tx_fifo_partition_3;
340 #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
341 #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
342 #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
343 #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
345 #define TX_FIFO_PARTITION_PRI_0 0 /* highest */
346 #define TX_FIFO_PARTITION_PRI_1 1
347 #define TX_FIFO_PARTITION_PRI_2 2
348 #define TX_FIFO_PARTITION_PRI_3 3
349 #define TX_FIFO_PARTITION_PRI_4 4
350 #define TX_FIFO_PARTITION_PRI_5 5
351 #define TX_FIFO_PARTITION_PRI_6 6
352 #define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
354 u64 tx_w_round_robin_0;
355 u64 tx_w_round_robin_1;
356 u64 tx_w_round_robin_2;
357 u64 tx_w_round_robin_3;
358 u64 tx_w_round_robin_4;
361 #define TTI_CMD_MEM_WE BIT(7)
362 #define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
363 #define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
364 #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
367 #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
368 #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
369 #define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
370 #define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
371 #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
372 #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
373 #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
376 #define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
377 #define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
378 #define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
379 #define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
381 /* Tx Protocol assist */
383 #define TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
384 #define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
385 #define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
386 #define TX_PA_CFG_IGNORE_L2_ERR BIT(6)
388 /* Recent add, used only debug purposes. */
391 u8 unused9[0x700 - 0x178];
393 u64 txdma_debug_ctrl;
395 u8 unused10[0x1800 - 0x1708];
397 /* RxDMA Registers */
398 u64 rxdma_int_status;
400 #define RXDMA_INT_RC_INT_M BIT(0)
401 #define RXDMA_INT_RPA_INT_M BIT(1)
402 #define RXDMA_INT_RDA_INT_M BIT(2)
403 #define RXDMA_INT_RTI_INT_M BIT(3)
413 u64 prc_pcix_err_reg;
414 u64 prc_pcix_err_mask;
415 u64 prc_pcix_err_alarm;
425 u8 unused11[0x100 - 0x88];
428 u64 rx_queue_priority;
429 #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
430 #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
431 #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
432 #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
433 #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
434 #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
435 #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
436 #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
438 #define RX_QUEUE_PRI_0 0 /* highest */
439 #define RX_QUEUE_PRI_1 1
440 #define RX_QUEUE_PRI_2 2
441 #define RX_QUEUE_PRI_3 3
442 #define RX_QUEUE_PRI_4 4
443 #define RX_QUEUE_PRI_5 5
444 #define RX_QUEUE_PRI_6 6
445 #define RX_QUEUE_PRI_7 7 /* lowest */
447 u64 rx_w_round_robin_0;
448 u64 rx_w_round_robin_1;
449 u64 rx_w_round_robin_2;
450 u64 rx_w_round_robin_3;
451 u64 rx_w_round_robin_4;
453 /* Per-ring controller regs */
454 #define RX_MAX_RINGS 8
456 #define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
457 #define RX_MIN_RINGS_SZ 0x3F /* 63 */
459 u64 prc_rxd0_n[RX_MAX_RINGS];
460 u64 prc_ctrl_n[RX_MAX_RINGS];
461 #define PRC_CTRL_RC_ENABLED BIT(7)
462 #define PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
463 #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
464 #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
465 #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
466 #define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
467 #define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23))
468 #define PRC_CTRL_NO_SNOOP_DESC BIT(22)
469 #define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
470 #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
472 u64 prc_alarm_action;
473 #define PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
474 #define PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
475 #define PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
476 #define PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
477 #define PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
478 #define PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
479 #define PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
480 #define PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
481 #define PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
482 #define PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
483 #define PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
484 #define PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
485 #define PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
486 #define PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
487 #define PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
488 #define PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
490 /* Receive traffic interrupts */
492 #define RTI_CMD_MEM_WE BIT(7)
493 #define RTI_CMD_MEM_STROBE BIT(15)
494 #define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
495 #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
496 #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
499 #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
500 #define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
501 #define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
502 #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
503 #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
504 #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
507 #define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
508 #define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
509 #define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
510 #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
513 #define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
514 #define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
515 #define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
516 #define RX_PA_CFG_IGNORE_L2_ERR BIT(6)
518 u8 unused12[0x700 - 0x1D8];
520 u64 rxdma_debug_ctrl;
522 u8 unused13[0x2000 - 0x1f08];
524 /* Media Access Controller Register */
527 #define MAC_INT_STATUS_TMAC_INT BIT(0)
528 #define MAC_INT_STATUS_RMAC_INT BIT(1)
530 u64 mac_tmac_err_reg;
531 #define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15)
532 #define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23)
533 #define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31)
534 u64 mac_tmac_err_mask;
535 u64 mac_tmac_err_alarm;
537 u64 mac_rmac_err_reg;
538 #define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0)
539 #define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14)
540 #define RMAC_ERR_REG_ECC_DB_ERR BIT(15)
541 #define RMAC_LINK_STATE_CHANGE_INT BIT(31)
542 u64 mac_rmac_err_mask;
543 u64 mac_rmac_err_alarm;
545 u8 unused14[0x100 - 0x40];
548 #define MAC_CFG_TMAC_ENABLE BIT(0)
549 #define MAC_CFG_RMAC_ENABLE BIT(1)
550 #define MAC_CFG_LAN_NOT_WAN BIT(2)
551 #define MAC_CFG_TMAC_LOOPBACK BIT(3)
552 #define MAC_CFG_TMAC_APPEND_PAD BIT(4)
553 #define MAC_CFG_RMAC_STRIP_FCS BIT(5)
554 #define MAC_CFG_RMAC_STRIP_PAD BIT(6)
555 #define MAC_CFG_RMAC_PROM_ENABLE BIT(7)
556 #define MAC_RMAC_DISCARD_PFRM BIT(8)
557 #define MAC_RMAC_BCAST_ENABLE BIT(9)
558 #define MAC_RMAC_ALL_ADDR_ENABLE BIT(10)
559 #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
562 #define TMAC_AVG_IPG(val) vBIT(val,0,8)
564 u64 rmac_max_pyld_len;
565 #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
566 #define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
567 #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
570 #define RMAC_ERR_FCS BIT(0)
571 #define RMAC_ERR_FCS_ACCEPT BIT(1)
572 #define RMAC_ERR_TOO_LONG BIT(1)
573 #define RMAC_ERR_TOO_LONG_ACCEPT BIT(1)
574 #define RMAC_ERR_RUNT BIT(2)
575 #define RMAC_ERR_RUNT_ACCEPT BIT(2)
576 #define RMAC_ERR_LEN_MISMATCH BIT(3)
577 #define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)
580 #define RMAC_CFG_KEY(val) vBIT(val,0,16)
582 #define MAX_MAC_ADDRESSES 16
583 #define MAX_MC_ADDRESSES 32 /* Multicast addresses */
584 #define MAC_MAC_ADDR_START_OFFSET 0
585 #define MAC_MC_ADDR_START_OFFSET 16
586 #define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */
587 u64 rmac_addr_cmd_mem;
588 #define RMAC_ADDR_CMD_MEM_WE BIT(7)
589 #define RMAC_ADDR_CMD_MEM_RD 0
590 #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)
591 #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
592 #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
594 u64 rmac_addr_data0_mem;
595 #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
596 #define RMAC_ADDR_DATA0_MEM_USER BIT(48)
598 u64 rmac_addr_data1_mem;
599 #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
605 #define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
606 #define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
607 #define RMAC_ADDR_BCAST_EN vBIT(0)_48
608 #define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
613 #define RMAC_PAUSE_GEN BIT(0)
614 #define RMAC_PAUSE_GEN_ENABLE BIT(0)
615 #define RMAC_PAUSE_RX BIT(1)
616 #define RMAC_PAUSE_RX_ENABLE BIT(1)
617 #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
618 #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
622 u64 rmac_red_rate_q0q3;
623 u64 rmac_red_rate_q4q7;
626 #define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
627 #define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
628 #define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
629 #define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
630 #define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
631 #define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
633 #define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
634 MAC_RX_LINK_UTIL_DISABLE
636 u64 rmac_invalid_ipg;
638 /* rx traffic steering */
639 #define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
640 u64 rts_frm_len_n[8];
642 u64 rts_qos_steering;
644 #define MAX_DIX_MAP 4
645 u64 rts_dix_map_n[MAX_DIX_MAP];
646 #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
647 #define RTS_DIX_MAP_SCW(val) BIT(val,21)
649 u64 rts_q_alternates;
653 #define RTS_CTRL_IGNORE_SNAP_OUI BIT(2)
654 #define RTS_CTRL_IGNORE_LLC_CTRL BIT(3)
657 #define RTS_PN_CAM_CTRL_WE BIT(7)
658 #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)
659 #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
660 #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
662 #define RTS_PN_CAM_DATA_TCP_SELECT BIT(7)
663 #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
664 #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
667 #define RTS_DS_MEM_CTRL_WE BIT(7)
668 #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)
669 #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
670 #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
672 #define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
674 u8 unused16[0x700 - 0x220];
677 #define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
679 u8 unused17[0x2800 - 0x2708];
681 /* memory controller registers */
683 #define MC_INT_STATUS_MC_INT BIT(0)
685 #define MC_INT_MASK_MC_INT BIT(0)
688 #define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
689 #define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
690 #define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
691 #define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
692 #define MC_ERR_REG_SM_ERR BIT(31)
696 u8 unused18[0x100 - 0x28];
698 /* MC configuration */
700 #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
701 #define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
702 #define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
703 #define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
704 #define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
705 #define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
706 #define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
707 #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
710 #define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
711 #define MC_RLDRAM_MRS_ENABLE BIT(47)
713 u64 mc_rldram_interleave;
715 u64 mc_pause_thresh_q0q3;
716 u64 mc_pause_thresh_q4q7;
718 u64 mc_red_thresh_q[8];
720 u8 unused19[0x200 - 0x168];
721 u64 mc_rldram_ref_per;
722 u8 unused20[0x220 - 0x208];
723 u64 mc_rldram_test_ctrl;
724 #define MC_RLDRAM_TEST_MODE BIT(47)
725 #define MC_RLDRAM_TEST_WRITE BIT(7)
726 #define MC_RLDRAM_TEST_GO BIT(15)
727 #define MC_RLDRAM_TEST_DONE BIT(23)
728 #define MC_RLDRAM_TEST_PASS BIT(31)
730 u8 unused21[0x240 - 0x228];
731 u64 mc_rldram_test_add;
732 u8 unused22[0x260 - 0x248];
733 u64 mc_rldram_test_d0;
734 u8 unused23[0x280 - 0x268];
735 u64 mc_rldram_test_d1;
736 u8 unused24[0x300 - 0x288];
737 u64 mc_rldram_test_d2;
738 u8 unused25[0x700 - 0x308];
741 u8 unused26[0x3000 - 0x2f08];
744 /* XGXS control registers */
747 #define XGXS_INT_STATUS_TXGXS BIT(0)
748 #define XGXS_INT_STATUS_RXGXS BIT(1)
750 #define XGXS_INT_MASK_TXGXS BIT(0)
751 #define XGXS_INT_MASK_RXGXS BIT(1)
753 u64 xgxs_txgxs_err_reg;
754 #define TXGXS_ECC_DB_ERR BIT(15)
755 u64 xgxs_txgxs_err_mask;
756 u64 xgxs_txgxs_err_alarm;
758 u64 xgxs_rxgxs_err_reg;
759 u64 xgxs_rxgxs_err_mask;
760 u64 xgxs_rxgxs_err_alarm;
762 u8 unused27[0x100 - 0x40];
768 u64 xgxs_efifo_cfg; /* CHANGED */
769 u64 rxgxs_ber_0; /* CHANGED */
770 u64 rxgxs_ber_1; /* CHANGED */
774 #define XENA_REG_SPACE sizeof(XENA_dev_config_t)
775 #define XENA_EEPROM_SPACE (0x01 << 11)