2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.13"
53 #define PFX DRV_NAME " "
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98 static int idle_timeout = 0;
99 module_param(idle_timeout, int, 0);
100 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 /* This device causes data corruption problems that are not resolved */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 MODULE_DEVICE_TABLE(pci, sky2_id_table);
141 /* Avoid conditionals by using array */
142 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
144 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
146 /* This driver supports yukon2 chipset only */
147 static const char *yukon2_name[] = {
149 "EC Ultra", /* 0xb4 */
150 "Extreme", /* 0xb5 */
155 /* Access to external PHY */
156 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164 for (i = 0; i < PHY_RETRIES; i++) {
165 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
170 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
174 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
178 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
179 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
181 for (i = 0; i < PHY_RETRIES; i++) {
182 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
183 *val = gma_read16(hw, port, GM_SMI_DATA);
193 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
197 if (__gm_phy_read(hw, port, reg, &v) != 0)
198 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
203 static void sky2_power_on(struct sky2_hw *hw)
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw, B0_POWER_CTRL,
207 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
209 /* disable Core Clock Division, */
210 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
212 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
213 /* enable bits are inverted */
214 sky2_write8(hw, B2_Y2_CLK_GATE,
215 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
216 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
217 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
219 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
221 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
224 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
225 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
226 reg1 &= P_ASPM_CONTROL_MSK;
227 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
228 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
232 static void sky2_power_aux(struct sky2_hw *hw)
234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237 /* enable bits are inverted */
238 sky2_write8(hw, B2_Y2_CLK_GATE,
239 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
240 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
241 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
243 /* switch power to VAUX */
244 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
245 sky2_write8(hw, B0_POWER_CTRL,
246 (PC_VAUX_ENA | PC_VCC_ENA |
247 PC_VAUX_ON | PC_VCC_OFF));
250 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
254 /* disable all GMAC IRQ's */
255 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
256 /* disable PHY IRQs */
257 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
260 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
261 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
262 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
264 reg = gma_read16(hw, port, GM_RX_CTRL);
265 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
266 gma_write16(hw, port, GM_RX_CTRL, reg);
269 /* flow control to advertise bits */
270 static const u16 copper_fc_adv[] = {
272 [FC_TX] = PHY_M_AN_ASP,
273 [FC_RX] = PHY_M_AN_PC,
274 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
277 /* flow control to advertise bits when using 1000BaseX */
278 static const u16 fiber_fc_adv[] = {
279 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
280 [FC_TX] = PHY_M_P_ASYM_MD_X,
281 [FC_RX] = PHY_M_P_SYM_MD_X,
282 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
285 /* flow control to GMA disable bits */
286 static const u16 gm_fc_disable[] = {
287 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
288 [FC_TX] = GM_GPCR_FC_RX_DIS,
289 [FC_RX] = GM_GPCR_FC_TX_DIS,
294 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
299 if (sky2->autoneg == AUTONEG_ENABLE
300 && !(hw->chip_id == CHIP_ID_YUKON_XL
301 || hw->chip_id == CHIP_ID_YUKON_EC_U
302 || hw->chip_id == CHIP_ID_YUKON_EX)) {
303 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
305 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
307 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
309 if (hw->chip_id == CHIP_ID_YUKON_EC)
310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
312 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
314 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
317 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
318 if (sky2_is_copper(hw)) {
319 if (hw->chip_id == CHIP_ID_YUKON_FE) {
320 /* enable automatic crossover */
321 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 /* disable energy detect */
324 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326 /* enable automatic crossover */
327 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329 if (sky2->autoneg == AUTONEG_ENABLE
330 && (hw->chip_id == CHIP_ID_YUKON_XL
331 || hw->chip_id == CHIP_ID_YUKON_EC_U
332 || hw->chip_id == CHIP_ID_YUKON_EX)) {
333 ctrl &= ~PHY_M_PC_DSC_MSK;
334 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 /* workaround for deviation #4.88 (CRC errors) */
339 /* disable Automatic Crossover */
341 ctrl &= ~PHY_M_PC_MDIX_MSK;
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346 /* special setup for PHY 88E1112 Fiber */
347 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
348 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
350 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 ctrl &= ~PHY_M_MAC_MD_MSK;
354 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
357 if (hw->pmd_type == 'P') {
358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
361 /* for SFP-module set SIGDET polarity to low */
362 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
363 ctrl |= PHY_M_FIB_SIGD_POL;
364 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
367 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
375 if (sky2->autoneg == AUTONEG_ENABLE) {
376 if (sky2_is_copper(hw)) {
377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
390 adv |= copper_fc_adv[sky2->flow_mode];
391 } else { /* special defines for FIBER (88E1040S only) */
392 if (sky2->advertising & ADVERTISED_1000baseT_Full)
393 adv |= PHY_M_AN_1000X_AFD;
394 if (sky2->advertising & ADVERTISED_1000baseT_Half)
395 adv |= PHY_M_AN_1000X_AHD;
397 adv |= fiber_fc_adv[sky2->flow_mode];
400 /* Restart Auto-negotiation */
401 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
403 /* forced speed/duplex settings */
404 ct1000 = PHY_M_1000C_MSE;
406 /* Disable auto update for duplex flow control and speed */
407 reg |= GM_GPCR_AU_ALL_DIS;
409 switch (sky2->speed) {
411 ctrl |= PHY_CT_SP1000;
412 reg |= GM_GPCR_SPEED_1000;
415 ctrl |= PHY_CT_SP100;
416 reg |= GM_GPCR_SPEED_100;
420 if (sky2->duplex == DUPLEX_FULL) {
421 reg |= GM_GPCR_DUP_FULL;
422 ctrl |= PHY_CT_DUP_MD;
423 } else if (sky2->speed < SPEED_1000)
424 sky2->flow_mode = FC_NONE;
427 reg |= gm_fc_disable[sky2->flow_mode];
429 /* Forward pause packets to GMAC? */
430 if (sky2->flow_mode & FC_RX)
431 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
433 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
436 gma_write16(hw, port, GM_GP_CTRL, reg);
438 if (hw->chip_id != CHIP_ID_YUKON_FE)
439 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
441 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
442 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
444 /* Setup Phy LED's */
445 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
448 switch (hw->chip_id) {
449 case CHIP_ID_YUKON_FE:
450 /* on 88E3082 these bits are at 11..9 (shifted left) */
451 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
453 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
455 /* delete ACT LED control bits */
456 ctrl &= ~PHY_M_FELP_LED1_MSK;
457 /* change ACT LED control to blink mode */
458 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
459 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
462 case CHIP_ID_YUKON_XL:
463 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
465 /* select page 3 to access LED control register */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
468 /* set LED Function Control register */
469 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
470 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
471 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
472 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
473 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
475 /* set Polarity Control register */
476 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
477 (PHY_M_POLC_LS1_P_MIX(4) |
478 PHY_M_POLC_IS0_P_MIX(4) |
479 PHY_M_POLC_LOS_CTRL(2) |
480 PHY_M_POLC_INIT_CTRL(2) |
481 PHY_M_POLC_STA1_CTRL(2) |
482 PHY_M_POLC_STA0_CTRL(2)));
484 /* restore page register */
485 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
488 case CHIP_ID_YUKON_EC_U:
489 case CHIP_ID_YUKON_EX:
490 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
492 /* select page 3 to access LED control register */
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
495 /* set LED Function Control register */
496 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
497 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
498 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
499 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
500 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
502 /* set Blink Rate in LED Timer Control Register */
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
504 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
505 /* restore page register */
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
510 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
511 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
512 /* turn off the Rx LED (LED_RX) */
513 ledover &= ~PHY_M_LED_MO_RX;
516 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
517 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
518 /* apply fixes in PHY AFE */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
521 /* increase differential signal amplitude in 10BASE-T */
522 gm_phy_write(hw, port, 0x18, 0xaa99);
523 gm_phy_write(hw, port, 0x17, 0x2011);
525 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
526 gm_phy_write(hw, port, 0x18, 0xa204);
527 gm_phy_write(hw, port, 0x17, 0x2002);
529 /* set page register to 0 */
530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
531 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
532 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
534 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
535 /* turn on 100 Mbps LED (LED_LINK100) */
536 ledover |= PHY_M_LED_MO_100;
540 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
544 /* Enable phy interrupt on auto-negotiation complete (or link up) */
545 if (sky2->autoneg == AUTONEG_ENABLE)
546 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
548 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
551 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
554 static const u32 phy_power[]
555 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
557 /* looks like this XL is back asswards .. */
558 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
561 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
562 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
564 /* Turn off phy power saving */
565 reg1 &= ~phy_power[port];
567 reg1 |= phy_power[port];
569 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
570 sky2_pci_read32(hw, PCI_DEV_REG1);
571 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
575 /* Force a renegotiation */
576 static void sky2_phy_reinit(struct sky2_port *sky2)
578 spin_lock_bh(&sky2->phy_lock);
579 sky2_phy_init(sky2->hw, sky2->port);
580 spin_unlock_bh(&sky2->phy_lock);
583 /* Put device in state to listen for Wake On Lan */
584 static void sky2_wol_init(struct sky2_port *sky2)
586 struct sky2_hw *hw = sky2->hw;
587 unsigned port = sky2->port;
588 enum flow_control save_mode;
592 /* Bring hardware out of reset */
593 sky2_write16(hw, B0_CTST, CS_RST_CLR);
594 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
596 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
600 * sky2_reset will re-enable on resume
602 save_mode = sky2->flow_mode;
603 ctrl = sky2->advertising;
605 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
606 sky2->flow_mode = FC_NONE;
607 sky2_phy_power(hw, port, 1);
608 sky2_phy_reinit(sky2);
610 sky2->flow_mode = save_mode;
611 sky2->advertising = ctrl;
613 /* Set GMAC to no flow control and auto update for speed/duplex */
614 gma_write16(hw, port, GM_GP_CTRL,
615 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
616 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
618 /* Set WOL address */
619 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
620 sky2->netdev->dev_addr, ETH_ALEN);
622 /* Turn on appropriate WOL control bits */
623 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
625 if (sky2->wol & WAKE_PHY)
626 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
628 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
630 if (sky2->wol & WAKE_MAGIC)
631 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
633 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
635 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
636 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
638 /* Turn on legacy PCI-Express PME mode */
639 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
640 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
641 reg1 |= PCI_Y2_PME_LEGACY;
642 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
643 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
646 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
650 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
652 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
655 const u8 *addr = hw->dev[port]->dev_addr;
657 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
658 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
660 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
662 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
663 /* WA DEV_472 -- looks like crossed wires on port 2 */
664 /* clear GMAC 1 Control reset */
665 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
667 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
668 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
669 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
670 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
671 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
674 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
676 /* Enable Transmit FIFO Underrun */
677 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
679 spin_lock_bh(&sky2->phy_lock);
680 sky2_phy_init(hw, port);
681 spin_unlock_bh(&sky2->phy_lock);
684 reg = gma_read16(hw, port, GM_PHY_ADDR);
685 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
687 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
688 gma_read16(hw, port, i);
689 gma_write16(hw, port, GM_PHY_ADDR, reg);
691 /* transmit control */
692 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
694 /* receive control reg: unicast + multicast + no FCS */
695 gma_write16(hw, port, GM_RX_CTRL,
696 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
698 /* transmit flow control */
699 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
701 /* transmit parameter */
702 gma_write16(hw, port, GM_TX_PARAM,
703 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
704 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
705 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
706 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
708 /* serial mode register */
709 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
710 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
712 if (hw->dev[port]->mtu > ETH_DATA_LEN)
713 reg |= GM_SMOD_JUMBO_ENA;
715 gma_write16(hw, port, GM_SERIAL_MODE, reg);
717 /* virtual address for data */
718 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
720 /* physical address: used for pause frames */
721 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
723 /* ignore counter overflows */
724 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
725 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
726 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
728 /* Configure Rx MAC FIFO */
729 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
730 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
731 GMF_OPER_ON | GMF_RX_F_FL_ON);
733 /* Flush Rx MAC FIFO on any flow control or error */
734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
736 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
737 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
739 /* Configure Tx MAC FIFO */
740 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
741 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
743 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
744 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
745 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
747 /* set Tx GMAC FIFO Almost Empty Threshold */
748 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
749 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
751 if (hw->dev[port]->mtu > ETH_DATA_LEN)
752 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
753 TX_JUMBO_ENA | TX_STFW_DIS);
755 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
756 TX_JUMBO_DIS | TX_STFW_ENA);
761 /* Assign Ram Buffer allocation to queue */
762 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
766 /* convert from K bytes to qwords used for hw register */
769 end = start + space - 1;
771 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
772 sky2_write32(hw, RB_ADDR(q, RB_START), start);
773 sky2_write32(hw, RB_ADDR(q, RB_END), end);
774 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
775 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
777 if (q == Q_R1 || q == Q_R2) {
778 u32 tp = space - space/4;
780 /* On receive queue's set the thresholds
781 * give receiver priority when > 3/4 full
782 * send pause when down to 2K
784 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
785 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
788 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
789 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
791 /* Enable store & forward on Tx queue's because
792 * Tx FIFO is only 1K on Yukon
794 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
797 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
798 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
801 /* Setup Bus Memory Interface */
802 static void sky2_qset(struct sky2_hw *hw, u16 q)
804 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
805 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
806 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
807 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
810 /* Setup prefetch unit registers. This is the interface between
811 * hardware and driver list elements
813 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
816 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
817 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
818 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
820 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
821 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
823 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
826 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
828 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
830 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
835 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
836 struct sky2_tx_le *le)
838 return sky2->tx_ring + (le - sky2->tx_le);
841 /* Update chip's next pointer */
842 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
844 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
846 sky2_write16(hw, q, idx);
851 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
853 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
854 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
859 /* Return high part of DMA address (could be 32 or 64 bit) */
860 static inline u32 high32(dma_addr_t a)
862 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
865 /* Build description to hardware for one receive segment */
866 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
867 dma_addr_t map, unsigned len)
869 struct sky2_rx_le *le;
870 u32 hi = high32(map);
872 if (sky2->rx_addr64 != hi) {
873 le = sky2_next_rx(sky2);
874 le->addr = cpu_to_le32(hi);
875 le->opcode = OP_ADDR64 | HW_OWNER;
876 sky2->rx_addr64 = high32(map + len);
879 le = sky2_next_rx(sky2);
880 le->addr = cpu_to_le32((u32) map);
881 le->length = cpu_to_le16(len);
882 le->opcode = op | HW_OWNER;
885 /* Build description to hardware for one possibly fragmented skb */
886 static void sky2_rx_submit(struct sky2_port *sky2,
887 const struct rx_ring_info *re)
891 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
893 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
894 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
898 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
901 struct sk_buff *skb = re->skb;
904 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
905 pci_unmap_len_set(re, data_size, size);
907 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
908 re->frag_addr[i] = pci_map_page(pdev,
909 skb_shinfo(skb)->frags[i].page,
910 skb_shinfo(skb)->frags[i].page_offset,
911 skb_shinfo(skb)->frags[i].size,
915 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
917 struct sk_buff *skb = re->skb;
920 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
923 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
924 pci_unmap_page(pdev, re->frag_addr[i],
925 skb_shinfo(skb)->frags[i].size,
929 /* Tell chip where to start receive checksum.
930 * Actually has two checksums, but set both same to avoid possible byte
933 static void rx_set_checksum(struct sky2_port *sky2)
935 struct sky2_rx_le *le;
937 le = sky2_next_rx(sky2);
938 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
940 le->opcode = OP_TCPSTART | HW_OWNER;
942 sky2_write32(sky2->hw,
943 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
944 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
949 * The RX Stop command will not work for Yukon-2 if the BMU does not
950 * reach the end of packet and since we can't make sure that we have
951 * incoming data, we must reset the BMU while it is not doing a DMA
952 * transfer. Since it is possible that the RX path is still active,
953 * the RX RAM buffer will be stopped first, so any possible incoming
954 * data will not trigger a DMA. After the RAM buffer is stopped, the
955 * BMU is polled until any DMA in progress is ended and only then it
958 static void sky2_rx_stop(struct sky2_port *sky2)
960 struct sky2_hw *hw = sky2->hw;
961 unsigned rxq = rxqaddr[sky2->port];
964 /* disable the RAM Buffer receive queue */
965 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
967 for (i = 0; i < 0xffff; i++)
968 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
969 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
972 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
975 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
977 /* reset the Rx prefetch unit */
978 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
981 /* Clean out receive buffer area, assumes receiver hardware stopped */
982 static void sky2_rx_clean(struct sky2_port *sky2)
986 memset(sky2->rx_le, 0, RX_LE_BYTES);
987 for (i = 0; i < sky2->rx_pending; i++) {
988 struct rx_ring_info *re = sky2->rx_ring + i;
991 sky2_rx_unmap_skb(sky2->hw->pdev, re);
998 /* Basic MII support */
999 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1001 struct mii_ioctl_data *data = if_mii(ifr);
1002 struct sky2_port *sky2 = netdev_priv(dev);
1003 struct sky2_hw *hw = sky2->hw;
1004 int err = -EOPNOTSUPP;
1006 if (!netif_running(dev))
1007 return -ENODEV; /* Phy still in reset */
1011 data->phy_id = PHY_ADDR_MARV;
1017 spin_lock_bh(&sky2->phy_lock);
1018 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1019 spin_unlock_bh(&sky2->phy_lock);
1021 data->val_out = val;
1026 if (!capable(CAP_NET_ADMIN))
1029 spin_lock_bh(&sky2->phy_lock);
1030 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1032 spin_unlock_bh(&sky2->phy_lock);
1038 #ifdef SKY2_VLAN_TAG_USED
1039 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1041 struct sky2_port *sky2 = netdev_priv(dev);
1042 struct sky2_hw *hw = sky2->hw;
1043 u16 port = sky2->port;
1045 netif_tx_lock_bh(dev);
1047 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1048 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1051 netif_tx_unlock_bh(dev);
1054 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1056 struct sky2_port *sky2 = netdev_priv(dev);
1057 struct sky2_hw *hw = sky2->hw;
1058 u16 port = sky2->port;
1060 netif_tx_lock_bh(dev);
1062 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1063 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1064 vlan_group_set_device(sky2->vlgrp, vid, NULL);
1066 netif_tx_unlock_bh(dev);
1071 * Allocate an skb for receiving. If the MTU is large enough
1072 * make the skb non-linear with a fragment list of pages.
1074 * It appears the hardware has a bug in the FIFO logic that
1075 * cause it to hang if the FIFO gets overrun and the receive buffer
1076 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1077 * aligned except if slab debugging is enabled.
1079 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1081 struct sk_buff *skb;
1085 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1089 p = (unsigned long) skb->data;
1090 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1092 for (i = 0; i < sky2->rx_nfrags; i++) {
1093 struct page *page = alloc_page(GFP_ATOMIC);
1097 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1108 * Allocate and setup receiver buffer pool.
1109 * Normal case this ends up creating one list element for skb
1110 * in the receive ring. Worst case if using large MTU and each
1111 * allocation falls on a different 64 bit region, that results
1112 * in 6 list elements per ring entry.
1113 * One element is used for checksum enable/disable, and one
1114 * extra to avoid wrap.
1116 static int sky2_rx_start(struct sky2_port *sky2)
1118 struct sky2_hw *hw = sky2->hw;
1119 struct rx_ring_info *re;
1120 unsigned rxq = rxqaddr[sky2->port];
1121 unsigned i, size, space, thresh;
1123 sky2->rx_put = sky2->rx_next = 0;
1126 /* On PCI express lowering the watermark gives better performance */
1127 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1128 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1130 /* These chips have no ram buffer?
1131 * MAC Rx RAM Read is controlled by hardware */
1132 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1133 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1134 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1135 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1137 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1139 rx_set_checksum(sky2);
1141 /* Space needed for frame data + headers rounded up */
1142 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1145 /* Stopping point for hardware truncation */
1146 thresh = (size - 8) / sizeof(u32);
1148 /* Account for overhead of skb - to avoid order > 0 allocation */
1149 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1150 + sizeof(struct skb_shared_info);
1152 sky2->rx_nfrags = space >> PAGE_SHIFT;
1153 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1155 if (sky2->rx_nfrags != 0) {
1156 /* Compute residue after pages */
1157 space = sky2->rx_nfrags << PAGE_SHIFT;
1164 /* Optimize to handle small packets and headers */
1165 if (size < copybreak)
1167 if (size < ETH_HLEN)
1170 sky2->rx_data_size = size;
1173 for (i = 0; i < sky2->rx_pending; i++) {
1174 re = sky2->rx_ring + i;
1176 re->skb = sky2_rx_alloc(sky2);
1180 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1181 sky2_rx_submit(sky2, re);
1185 * The receiver hangs if it receives frames larger than the
1186 * packet buffer. As a workaround, truncate oversize frames, but
1187 * the register is limited to 9 bits, so if you do frames > 2052
1188 * you better get the MTU right!
1191 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1193 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1194 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1197 /* Tell chip about available buffers */
1198 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1201 sky2_rx_clean(sky2);
1205 /* Bring up network interface. */
1206 static int sky2_up(struct net_device *dev)
1208 struct sky2_port *sky2 = netdev_priv(dev);
1209 struct sky2_hw *hw = sky2->hw;
1210 unsigned port = sky2->port;
1212 int cap, err = -ENOMEM;
1213 struct net_device *otherdev = hw->dev[sky2->port^1];
1216 * On dual port PCI-X card, there is an problem where status
1217 * can be received out of order due to split transactions
1219 if (otherdev && netif_running(otherdev) &&
1220 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1221 struct sky2_port *osky2 = netdev_priv(otherdev);
1224 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1225 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1226 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1232 if (netif_msg_ifup(sky2))
1233 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1235 /* must be power of 2 */
1236 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1238 sizeof(struct sky2_tx_le),
1243 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1247 sky2->tx_prod = sky2->tx_cons = 0;
1249 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1253 memset(sky2->rx_le, 0, RX_LE_BYTES);
1255 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1260 sky2_phy_power(hw, port, 1);
1262 sky2_mac_init(hw, port);
1264 /* Register is number of 4K blocks on internal RAM buffer. */
1265 ramsize = sky2_read8(hw, B2_E_0) * 4;
1266 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1272 rxspace = ramsize / 2;
1274 rxspace = 8 + (2*(ramsize - 16))/3;
1276 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1277 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1279 /* Make sure SyncQ is disabled */
1280 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1284 sky2_qset(hw, txqaddr[port]);
1286 /* Set almost empty threshold */
1287 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1288 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1289 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1291 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1294 err = sky2_rx_start(sky2);
1298 /* Enable interrupts from phy/mac for port */
1299 imask = sky2_read32(hw, B0_IMSK);
1300 imask |= portirq_msk[port];
1301 sky2_write32(hw, B0_IMSK, imask);
1307 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1308 sky2->rx_le, sky2->rx_le_map);
1312 pci_free_consistent(hw->pdev,
1313 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1314 sky2->tx_le, sky2->tx_le_map);
1317 kfree(sky2->tx_ring);
1318 kfree(sky2->rx_ring);
1320 sky2->tx_ring = NULL;
1321 sky2->rx_ring = NULL;
1325 /* Modular subtraction in ring */
1326 static inline int tx_dist(unsigned tail, unsigned head)
1328 return (head - tail) & (TX_RING_SIZE - 1);
1331 /* Number of list elements available for next tx */
1332 static inline int tx_avail(const struct sky2_port *sky2)
1334 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1337 /* Estimate of number of transmit list elements required */
1338 static unsigned tx_le_req(const struct sk_buff *skb)
1342 count = sizeof(dma_addr_t) / sizeof(u32);
1343 count += skb_shinfo(skb)->nr_frags * count;
1345 if (skb_is_gso(skb))
1348 if (skb->ip_summed == CHECKSUM_PARTIAL)
1355 * Put one packet in ring for transmit.
1356 * A single packet can generate multiple list elements, and
1357 * the number of ring elements will probably be less than the number
1358 * of list elements used.
1360 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1362 struct sky2_port *sky2 = netdev_priv(dev);
1363 struct sky2_hw *hw = sky2->hw;
1364 struct sky2_tx_le *le = NULL;
1365 struct tx_ring_info *re;
1372 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1373 return NETDEV_TX_BUSY;
1375 if (unlikely(netif_msg_tx_queued(sky2)))
1376 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1377 dev->name, sky2->tx_prod, skb->len);
1379 len = skb_headlen(skb);
1380 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1381 addr64 = high32(mapping);
1383 /* Send high bits if changed or crosses boundary */
1384 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1385 le = get_tx_le(sky2);
1386 le->addr = cpu_to_le32(addr64);
1387 le->opcode = OP_ADDR64 | HW_OWNER;
1388 sky2->tx_addr64 = high32(mapping + len);
1391 /* Check for TCP Segmentation Offload */
1392 mss = skb_shinfo(skb)->gso_size;
1394 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1395 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1398 if (mss != sky2->tx_last_mss) {
1399 le = get_tx_le(sky2);
1400 le->addr = cpu_to_le32(mss);
1401 le->opcode = OP_LRGLEN | HW_OWNER;
1402 sky2->tx_last_mss = mss;
1407 #ifdef SKY2_VLAN_TAG_USED
1408 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1409 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1411 le = get_tx_le(sky2);
1413 le->opcode = OP_VLAN|HW_OWNER;
1415 le->opcode |= OP_VLAN;
1416 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1421 /* Handle TCP checksum offload */
1422 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1423 unsigned offset = skb->h.raw - skb->data;
1426 tcpsum = offset << 16; /* sum start */
1427 tcpsum |= offset + skb->csum_offset; /* sum write */
1429 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1430 if (skb->nh.iph->protocol == IPPROTO_UDP)
1433 if (tcpsum != sky2->tx_tcpsum) {
1434 sky2->tx_tcpsum = tcpsum;
1436 le = get_tx_le(sky2);
1437 le->addr = cpu_to_le32(tcpsum);
1438 le->length = 0; /* initial checksum value */
1439 le->ctrl = 1; /* one packet */
1440 le->opcode = OP_TCPLISW | HW_OWNER;
1444 le = get_tx_le(sky2);
1445 le->addr = cpu_to_le32((u32) mapping);
1446 le->length = cpu_to_le16(len);
1448 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1450 re = tx_le_re(sky2, le);
1452 pci_unmap_addr_set(re, mapaddr, mapping);
1453 pci_unmap_len_set(re, maplen, len);
1455 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1456 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1458 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1459 frag->size, PCI_DMA_TODEVICE);
1460 addr64 = high32(mapping);
1461 if (addr64 != sky2->tx_addr64) {
1462 le = get_tx_le(sky2);
1463 le->addr = cpu_to_le32(addr64);
1465 le->opcode = OP_ADDR64 | HW_OWNER;
1466 sky2->tx_addr64 = addr64;
1469 le = get_tx_le(sky2);
1470 le->addr = cpu_to_le32((u32) mapping);
1471 le->length = cpu_to_le16(frag->size);
1473 le->opcode = OP_BUFFER | HW_OWNER;
1475 re = tx_le_re(sky2, le);
1477 pci_unmap_addr_set(re, mapaddr, mapping);
1478 pci_unmap_len_set(re, maplen, frag->size);
1483 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1484 netif_stop_queue(dev);
1486 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1488 dev->trans_start = jiffies;
1489 return NETDEV_TX_OK;
1493 * Free ring elements from starting at tx_cons until "done"
1495 * NB: the hardware will tell us about partial completion of multi-part
1496 * buffers so make sure not to free skb to early.
1498 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1500 struct net_device *dev = sky2->netdev;
1501 struct pci_dev *pdev = sky2->hw->pdev;
1504 BUG_ON(done >= TX_RING_SIZE);
1506 for (idx = sky2->tx_cons; idx != done;
1507 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1508 struct sky2_tx_le *le = sky2->tx_le + idx;
1509 struct tx_ring_info *re = sky2->tx_ring + idx;
1511 switch(le->opcode & ~HW_OWNER) {
1514 pci_unmap_single(pdev,
1515 pci_unmap_addr(re, mapaddr),
1516 pci_unmap_len(re, maplen),
1520 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1521 pci_unmap_len(re, maplen),
1526 if (le->ctrl & EOP) {
1527 if (unlikely(netif_msg_tx_done(sky2)))
1528 printk(KERN_DEBUG "%s: tx done %u\n",
1530 sky2->net_stats.tx_packets++;
1531 sky2->net_stats.tx_bytes += re->skb->len;
1533 dev_kfree_skb_any(re->skb);
1536 le->opcode = 0; /* paranoia */
1539 sky2->tx_cons = idx;
1540 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1541 netif_wake_queue(dev);
1544 /* Cleanup all untransmitted buffers, assume transmitter not running */
1545 static void sky2_tx_clean(struct net_device *dev)
1547 struct sky2_port *sky2 = netdev_priv(dev);
1549 netif_tx_lock_bh(dev);
1550 sky2_tx_complete(sky2, sky2->tx_prod);
1551 netif_tx_unlock_bh(dev);
1554 /* Network shutdown */
1555 static int sky2_down(struct net_device *dev)
1557 struct sky2_port *sky2 = netdev_priv(dev);
1558 struct sky2_hw *hw = sky2->hw;
1559 unsigned port = sky2->port;
1563 /* Never really got started! */
1567 if (netif_msg_ifdown(sky2))
1568 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1570 /* Stop more packets from being queued */
1571 netif_stop_queue(dev);
1572 netif_carrier_off(dev);
1574 /* Disable port IRQ */
1575 imask = sky2_read32(hw, B0_IMSK);
1576 imask &= ~portirq_msk[port];
1577 sky2_write32(hw, B0_IMSK, imask);
1580 * Both ports share the NAPI poll on port 0, so if necessary undo the
1581 * the disable that is done in dev_close.
1583 if (sky2->port == 0 && hw->ports > 1)
1584 netif_poll_enable(dev);
1586 sky2_gmac_reset(hw, port);
1588 /* Stop transmitter */
1589 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1590 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1592 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1593 RB_RST_SET | RB_DIS_OP_MD);
1595 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1596 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1597 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1599 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1601 /* Workaround shared GMAC reset */
1602 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1603 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1604 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1606 /* Disable Force Sync bit and Enable Alloc bit */
1607 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1608 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1610 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1611 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1612 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1614 /* Reset the PCI FIFO of the async Tx queue */
1615 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1616 BMU_RST_SET | BMU_FIFO_RST);
1618 /* Reset the Tx prefetch units */
1619 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1622 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1626 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1627 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1629 sky2_phy_power(hw, port, 0);
1631 /* turn off LED's */
1632 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1634 synchronize_irq(hw->pdev->irq);
1637 sky2_rx_clean(sky2);
1639 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1640 sky2->rx_le, sky2->rx_le_map);
1641 kfree(sky2->rx_ring);
1643 pci_free_consistent(hw->pdev,
1644 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1645 sky2->tx_le, sky2->tx_le_map);
1646 kfree(sky2->tx_ring);
1651 sky2->rx_ring = NULL;
1652 sky2->tx_ring = NULL;
1657 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1659 if (!sky2_is_copper(hw))
1662 if (hw->chip_id == CHIP_ID_YUKON_FE)
1663 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1665 switch (aux & PHY_M_PS_SPEED_MSK) {
1666 case PHY_M_PS_SPEED_1000:
1668 case PHY_M_PS_SPEED_100:
1675 static void sky2_link_up(struct sky2_port *sky2)
1677 struct sky2_hw *hw = sky2->hw;
1678 unsigned port = sky2->port;
1680 static const char *fc_name[] = {
1688 reg = gma_read16(hw, port, GM_GP_CTRL);
1689 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1690 gma_write16(hw, port, GM_GP_CTRL, reg);
1692 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1694 netif_carrier_on(sky2->netdev);
1695 netif_wake_queue(sky2->netdev);
1697 /* Turn on link LED */
1698 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1699 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1701 if (hw->chip_id == CHIP_ID_YUKON_XL
1702 || hw->chip_id == CHIP_ID_YUKON_EC_U
1703 || hw->chip_id == CHIP_ID_YUKON_EX) {
1704 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1705 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1707 switch(sky2->speed) {
1709 led |= PHY_M_LEDC_INIT_CTRL(7);
1713 led |= PHY_M_LEDC_STA1_CTRL(7);
1717 led |= PHY_M_LEDC_STA0_CTRL(7);
1721 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1722 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1723 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1726 if (netif_msg_link(sky2))
1727 printk(KERN_INFO PFX
1728 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1729 sky2->netdev->name, sky2->speed,
1730 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1731 fc_name[sky2->flow_status]);
1734 static void sky2_link_down(struct sky2_port *sky2)
1736 struct sky2_hw *hw = sky2->hw;
1737 unsigned port = sky2->port;
1740 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1742 reg = gma_read16(hw, port, GM_GP_CTRL);
1743 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1744 gma_write16(hw, port, GM_GP_CTRL, reg);
1746 netif_carrier_off(sky2->netdev);
1747 netif_stop_queue(sky2->netdev);
1749 /* Turn on link LED */
1750 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1752 if (netif_msg_link(sky2))
1753 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1755 sky2_phy_init(hw, port);
1758 static enum flow_control sky2_flow(int rx, int tx)
1761 return tx ? FC_BOTH : FC_RX;
1763 return tx ? FC_TX : FC_NONE;
1766 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1768 struct sky2_hw *hw = sky2->hw;
1769 unsigned port = sky2->port;
1772 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1773 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1774 if (lpa & PHY_M_AN_RF) {
1775 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1779 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1780 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1781 sky2->netdev->name);
1785 sky2->speed = sky2_phy_speed(hw, aux);
1786 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1788 /* Since the pause result bits seem to in different positions on
1789 * different chips. look at registers.
1791 if (!sky2_is_copper(hw)) {
1792 /* Shift for bits in fiber PHY */
1793 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1794 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1796 if (advert & ADVERTISE_1000XPAUSE)
1797 advert |= ADVERTISE_PAUSE_CAP;
1798 if (advert & ADVERTISE_1000XPSE_ASYM)
1799 advert |= ADVERTISE_PAUSE_ASYM;
1800 if (lpa & LPA_1000XPAUSE)
1801 lpa |= LPA_PAUSE_CAP;
1802 if (lpa & LPA_1000XPAUSE_ASYM)
1803 lpa |= LPA_PAUSE_ASYM;
1806 sky2->flow_status = FC_NONE;
1807 if (advert & ADVERTISE_PAUSE_CAP) {
1808 if (lpa & LPA_PAUSE_CAP)
1809 sky2->flow_status = FC_BOTH;
1810 else if (advert & ADVERTISE_PAUSE_ASYM)
1811 sky2->flow_status = FC_RX;
1812 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1813 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1814 sky2->flow_status = FC_TX;
1817 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1818 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1819 sky2->flow_status = FC_NONE;
1821 if (sky2->flow_status & FC_TX)
1822 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1824 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1829 /* Interrupt from PHY */
1830 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1832 struct net_device *dev = hw->dev[port];
1833 struct sky2_port *sky2 = netdev_priv(dev);
1834 u16 istatus, phystat;
1836 if (!netif_running(dev))
1839 spin_lock(&sky2->phy_lock);
1840 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1841 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1843 if (netif_msg_intr(sky2))
1844 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1845 sky2->netdev->name, istatus, phystat);
1847 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1848 if (sky2_autoneg_done(sky2, phystat) == 0)
1853 if (istatus & PHY_M_IS_LSP_CHANGE)
1854 sky2->speed = sky2_phy_speed(hw, phystat);
1856 if (istatus & PHY_M_IS_DUP_CHANGE)
1858 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1860 if (istatus & PHY_M_IS_LST_CHANGE) {
1861 if (phystat & PHY_M_PS_LINK_UP)
1864 sky2_link_down(sky2);
1867 spin_unlock(&sky2->phy_lock);
1870 /* Transmit timeout is only called if we are running, carrier is up
1871 * and tx queue is full (stopped).
1873 static void sky2_tx_timeout(struct net_device *dev)
1875 struct sky2_port *sky2 = netdev_priv(dev);
1876 struct sky2_hw *hw = sky2->hw;
1878 if (netif_msg_timer(sky2))
1879 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1881 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1882 dev->name, sky2->tx_cons, sky2->tx_prod,
1883 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1884 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1886 /* can't restart safely under softirq */
1887 schedule_work(&hw->restart_work);
1890 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1892 struct sky2_port *sky2 = netdev_priv(dev);
1893 struct sky2_hw *hw = sky2->hw;
1894 unsigned port = sky2->port;
1899 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1902 if (!netif_running(dev)) {
1907 imask = sky2_read32(hw, B0_IMSK);
1908 sky2_write32(hw, B0_IMSK, 0);
1910 dev->trans_start = jiffies; /* prevent tx timeout */
1911 netif_stop_queue(dev);
1912 netif_poll_disable(hw->dev[0]);
1914 synchronize_irq(hw->pdev->irq);
1916 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1917 if (new_mtu > ETH_DATA_LEN) {
1918 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1919 TX_JUMBO_ENA | TX_STFW_DIS);
1920 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1922 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1923 TX_JUMBO_DIS | TX_STFW_ENA);
1926 ctl = gma_read16(hw, port, GM_GP_CTRL);
1927 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1929 sky2_rx_clean(sky2);
1933 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1934 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1936 if (dev->mtu > ETH_DATA_LEN)
1937 mode |= GM_SMOD_JUMBO_ENA;
1939 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1941 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1943 err = sky2_rx_start(sky2);
1944 sky2_write32(hw, B0_IMSK, imask);
1949 gma_write16(hw, port, GM_GP_CTRL, ctl);
1951 netif_poll_enable(hw->dev[0]);
1952 netif_wake_queue(dev);
1958 /* For small just reuse existing skb for next receive */
1959 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1960 const struct rx_ring_info *re,
1963 struct sk_buff *skb;
1965 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1967 skb_reserve(skb, 2);
1968 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1969 length, PCI_DMA_FROMDEVICE);
1970 memcpy(skb->data, re->skb->data, length);
1971 skb->ip_summed = re->skb->ip_summed;
1972 skb->csum = re->skb->csum;
1973 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1974 length, PCI_DMA_FROMDEVICE);
1975 re->skb->ip_summed = CHECKSUM_NONE;
1976 skb_put(skb, length);
1981 /* Adjust length of skb with fragments to match received data */
1982 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1983 unsigned int length)
1988 /* put header into skb */
1989 size = min(length, hdr_space);
1994 num_frags = skb_shinfo(skb)->nr_frags;
1995 for (i = 0; i < num_frags; i++) {
1996 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1999 /* don't need this page */
2000 __free_page(frag->page);
2001 --skb_shinfo(skb)->nr_frags;
2003 size = min(length, (unsigned) PAGE_SIZE);
2006 skb->data_len += size;
2007 skb->truesize += size;
2014 /* Normal packet - take skb from ring element and put in a new one */
2015 static struct sk_buff *receive_new(struct sky2_port *sky2,
2016 struct rx_ring_info *re,
2017 unsigned int length)
2019 struct sk_buff *skb, *nskb;
2020 unsigned hdr_space = sky2->rx_data_size;
2022 pr_debug(PFX "receive new length=%d\n", length);
2024 /* Don't be tricky about reusing pages (yet) */
2025 nskb = sky2_rx_alloc(sky2);
2026 if (unlikely(!nskb))
2030 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2032 prefetch(skb->data);
2034 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2036 if (skb_shinfo(skb)->nr_frags)
2037 skb_put_frags(skb, hdr_space, length);
2039 skb_put(skb, length);
2044 * Receive one packet.
2045 * For larger packets, get new buffer.
2047 static struct sk_buff *sky2_receive(struct net_device *dev,
2048 u16 length, u32 status)
2050 struct sky2_port *sky2 = netdev_priv(dev);
2051 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2052 struct sk_buff *skb = NULL;
2054 if (unlikely(netif_msg_rx_status(sky2)))
2055 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2056 dev->name, sky2->rx_next, status, length);
2058 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2059 prefetch(sky2->rx_ring + sky2->rx_next);
2061 if (status & GMR_FS_ANY_ERR)
2064 if (!(status & GMR_FS_RX_OK))
2067 if (length < copybreak)
2068 skb = receive_copy(sky2, re, length);
2070 skb = receive_new(sky2, re, length);
2072 sky2_rx_submit(sky2, re);
2077 ++sky2->net_stats.rx_errors;
2078 if (status & GMR_FS_RX_FF_OV) {
2079 sky2->net_stats.rx_over_errors++;
2083 if (netif_msg_rx_err(sky2) && net_ratelimit())
2084 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2085 dev->name, status, length);
2087 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2088 sky2->net_stats.rx_length_errors++;
2089 if (status & GMR_FS_FRAGMENT)
2090 sky2->net_stats.rx_frame_errors++;
2091 if (status & GMR_FS_CRC_ERR)
2092 sky2->net_stats.rx_crc_errors++;
2097 /* Transmit complete */
2098 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2100 struct sky2_port *sky2 = netdev_priv(dev);
2102 if (netif_running(dev)) {
2104 sky2_tx_complete(sky2, last);
2105 netif_tx_unlock(dev);
2109 /* Process status response ring */
2110 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2112 struct sky2_port *sky2;
2114 unsigned buf_write[2] = { 0, 0 };
2115 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2119 while (hw->st_idx != hwidx) {
2120 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2121 struct net_device *dev;
2122 struct sk_buff *skb;
2126 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2128 BUG_ON(le->link >= 2);
2129 dev = hw->dev[le->link];
2131 sky2 = netdev_priv(dev);
2132 length = le16_to_cpu(le->length);
2133 status = le32_to_cpu(le->status);
2135 switch (le->opcode & ~HW_OWNER) {
2137 skb = sky2_receive(dev, length, status);
2141 skb->protocol = eth_type_trans(skb, dev);
2142 sky2->net_stats.rx_packets++;
2143 sky2->net_stats.rx_bytes += skb->len;
2144 dev->last_rx = jiffies;
2146 #ifdef SKY2_VLAN_TAG_USED
2147 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2148 vlan_hwaccel_receive_skb(skb,
2150 be16_to_cpu(sky2->rx_tag));
2153 netif_receive_skb(skb);
2155 /* Update receiver after 16 frames */
2156 if (++buf_write[le->link] == RX_BUF_WRITE) {
2158 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2159 buf_write[le->link] = 0;
2162 /* Stop after net poll weight */
2163 if (++work_done >= to_do)
2167 #ifdef SKY2_VLAN_TAG_USED
2169 sky2->rx_tag = length;
2173 sky2->rx_tag = length;
2180 /* Both checksum counters are programmed to start at
2181 * the same offset, so unless there is a problem they
2182 * should match. This failure is an early indication that
2183 * hardware receive checksumming won't work.
2185 if (likely(status >> 16 == (status & 0xffff))) {
2186 skb = sky2->rx_ring[sky2->rx_next].skb;
2187 skb->ip_summed = CHECKSUM_COMPLETE;
2188 skb->csum = status & 0xffff;
2190 printk(KERN_NOTICE PFX "%s: hardware receive "
2191 "checksum problem (status = %#x)\n",
2194 sky2_write32(sky2->hw,
2195 Q_ADDR(rxqaddr[le->link], Q_CSR),
2201 /* TX index reports status for both ports */
2202 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2203 sky2_tx_done(hw->dev[0], status & 0xfff);
2205 sky2_tx_done(hw->dev[1],
2206 ((status >> 24) & 0xff)
2207 | (u16)(length & 0xf) << 8);
2211 if (net_ratelimit())
2212 printk(KERN_WARNING PFX
2213 "unknown status opcode 0x%x\n", le->opcode);
2218 /* Fully processed status ring so clear irq */
2219 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2223 sky2 = netdev_priv(hw->dev[0]);
2224 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2228 sky2 = netdev_priv(hw->dev[1]);
2229 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2235 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2237 struct net_device *dev = hw->dev[port];
2239 if (net_ratelimit())
2240 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2243 if (status & Y2_IS_PAR_RD1) {
2244 if (net_ratelimit())
2245 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2248 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2251 if (status & Y2_IS_PAR_WR1) {
2252 if (net_ratelimit())
2253 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2256 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2259 if (status & Y2_IS_PAR_MAC1) {
2260 if (net_ratelimit())
2261 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2262 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2265 if (status & Y2_IS_PAR_RX1) {
2266 if (net_ratelimit())
2267 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2268 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2271 if (status & Y2_IS_TCP_TXA1) {
2272 if (net_ratelimit())
2273 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2275 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2279 static void sky2_hw_intr(struct sky2_hw *hw)
2281 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2283 if (status & Y2_IS_TIST_OV)
2284 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2286 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2289 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2290 if (net_ratelimit())
2291 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2294 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2295 sky2_pci_write16(hw, PCI_STATUS,
2296 pci_err | PCI_STATUS_ERROR_BITS);
2297 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2300 if (status & Y2_IS_PCI_EXP) {
2301 /* PCI-Express uncorrectable Error occurred */
2304 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2306 if (net_ratelimit())
2307 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2310 /* clear the interrupt */
2311 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2312 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2314 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2316 if (pex_err & PEX_FATAL_ERRORS) {
2317 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2318 hwmsk &= ~Y2_IS_PCI_EXP;
2319 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2323 if (status & Y2_HWE_L1_MASK)
2324 sky2_hw_error(hw, 0, status);
2326 if (status & Y2_HWE_L1_MASK)
2327 sky2_hw_error(hw, 1, status);
2330 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2332 struct net_device *dev = hw->dev[port];
2333 struct sky2_port *sky2 = netdev_priv(dev);
2334 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2336 if (netif_msg_intr(sky2))
2337 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2340 if (status & GM_IS_RX_FF_OR) {
2341 ++sky2->net_stats.rx_fifo_errors;
2342 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2345 if (status & GM_IS_TX_FF_UR) {
2346 ++sky2->net_stats.tx_fifo_errors;
2347 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2351 /* This should never happen it is a bug. */
2352 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2353 u16 q, unsigned ring_size)
2355 struct net_device *dev = hw->dev[port];
2356 struct sky2_port *sky2 = netdev_priv(dev);
2358 const u64 *le = (q == Q_R1 || q == Q_R2)
2359 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2361 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2362 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2363 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2364 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2366 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2369 /* If idle then force a fake soft NAPI poll once a second
2370 * to work around cases where sharing an edge triggered interrupt.
2372 static inline void sky2_idle_start(struct sky2_hw *hw)
2374 if (idle_timeout > 0)
2375 mod_timer(&hw->idle_timer,
2376 jiffies + msecs_to_jiffies(idle_timeout));
2379 static void sky2_idle(unsigned long arg)
2381 struct sky2_hw *hw = (struct sky2_hw *) arg;
2382 struct net_device *dev = hw->dev[0];
2384 if (__netif_rx_schedule_prep(dev))
2385 __netif_rx_schedule(dev);
2387 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2390 /* Hardware/software error handling */
2391 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2393 if (net_ratelimit())
2394 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2396 if (status & Y2_IS_HW_ERR)
2399 if (status & Y2_IS_IRQ_MAC1)
2400 sky2_mac_intr(hw, 0);
2402 if (status & Y2_IS_IRQ_MAC2)
2403 sky2_mac_intr(hw, 1);
2405 if (status & Y2_IS_CHK_RX1)
2406 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2408 if (status & Y2_IS_CHK_RX2)
2409 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2411 if (status & Y2_IS_CHK_TXA1)
2412 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2414 if (status & Y2_IS_CHK_TXA2)
2415 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2418 static int sky2_poll(struct net_device *dev0, int *budget)
2420 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2421 int work_limit = min(dev0->quota, *budget);
2423 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2425 if (unlikely(status & Y2_IS_ERROR))
2426 sky2_err_intr(hw, status);
2428 if (status & Y2_IS_IRQ_PHY1)
2429 sky2_phy_intr(hw, 0);
2431 if (status & Y2_IS_IRQ_PHY2)
2432 sky2_phy_intr(hw, 1);
2434 work_done = sky2_status_intr(hw, work_limit);
2435 if (work_done < work_limit) {
2436 netif_rx_complete(dev0);
2438 sky2_read32(hw, B0_Y2_SP_LISR);
2441 *budget -= work_done;
2442 dev0->quota -= work_done;
2447 static irqreturn_t sky2_intr(int irq, void *dev_id)
2449 struct sky2_hw *hw = dev_id;
2450 struct net_device *dev0 = hw->dev[0];
2453 /* Reading this mask interrupts as side effect */
2454 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2455 if (status == 0 || status == ~0)
2458 prefetch(&hw->st_le[hw->st_idx]);
2459 if (likely(__netif_rx_schedule_prep(dev0)))
2460 __netif_rx_schedule(dev0);
2465 #ifdef CONFIG_NET_POLL_CONTROLLER
2466 static void sky2_netpoll(struct net_device *dev)
2468 struct sky2_port *sky2 = netdev_priv(dev);
2469 struct net_device *dev0 = sky2->hw->dev[0];
2471 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2472 __netif_rx_schedule(dev0);
2476 /* Chip internal frequency for clock calculations */
2477 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2479 switch (hw->chip_id) {
2480 case CHIP_ID_YUKON_EC:
2481 case CHIP_ID_YUKON_EC_U:
2482 case CHIP_ID_YUKON_EX:
2483 return 125; /* 125 Mhz */
2484 case CHIP_ID_YUKON_FE:
2485 return 100; /* 100 Mhz */
2486 default: /* YUKON_XL */
2487 return 156; /* 156 Mhz */
2491 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2493 return sky2_mhz(hw) * us;
2496 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2498 return clk / sky2_mhz(hw);
2502 static int __devinit sky2_init(struct sky2_hw *hw)
2506 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2508 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2509 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2510 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2515 if (hw->chip_id == CHIP_ID_YUKON_EX)
2516 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2517 "Please report success or failure to <netdev@vger.kernel.org>\n");
2519 /* Make sure and enable all clocks */
2520 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2521 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2523 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2525 /* This rev is really old, and requires untested workarounds */
2526 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2527 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2528 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2529 hw->chip_id, hw->chip_rev);
2533 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2535 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2536 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2537 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2544 static void sky2_reset(struct sky2_hw *hw)
2550 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2551 status = sky2_read16(hw, HCU_CCSR);
2552 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2553 HCU_CCSR_UC_STATE_MSK);
2554 sky2_write16(hw, HCU_CCSR, status);
2556 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2557 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2560 sky2_write8(hw, B0_CTST, CS_RST_SET);
2561 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2563 /* clear PCI errors, if any */
2564 status = sky2_pci_read16(hw, PCI_STATUS);
2566 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2567 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2570 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2572 /* clear any PEX errors */
2573 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2574 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2579 for (i = 0; i < hw->ports; i++) {
2580 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2581 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2584 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2586 /* Clear I2C IRQ noise */
2587 sky2_write32(hw, B2_I2C_IRQ, 1);
2589 /* turn off hardware timer (unused) */
2590 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2591 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2593 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2595 /* Turn off descriptor polling */
2596 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2598 /* Turn off receive timestamp */
2599 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2600 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2602 /* enable the Tx Arbiters */
2603 for (i = 0; i < hw->ports; i++)
2604 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2606 /* Initialize ram interface */
2607 for (i = 0; i < hw->ports; i++) {
2608 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2610 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2611 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2612 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2613 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2614 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2615 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2616 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2617 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2618 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2619 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2620 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2621 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2624 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2626 for (i = 0; i < hw->ports; i++)
2627 sky2_gmac_reset(hw, i);
2629 memset(hw->st_le, 0, STATUS_LE_BYTES);
2632 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2633 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2635 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2636 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2638 /* Set the list last index */
2639 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2641 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2642 sky2_write8(hw, STAT_FIFO_WM, 16);
2644 /* set Status-FIFO ISR watermark */
2645 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2646 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2648 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2650 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2651 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2652 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2654 /* enable status unit */
2655 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2657 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2658 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2659 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2662 static void sky2_restart(struct work_struct *work)
2664 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2665 struct net_device *dev;
2668 dev_dbg(&hw->pdev->dev, "restarting\n");
2670 del_timer_sync(&hw->idle_timer);
2673 sky2_write32(hw, B0_IMSK, 0);
2674 sky2_read32(hw, B0_IMSK);
2676 netif_poll_disable(hw->dev[0]);
2678 for (i = 0; i < hw->ports; i++) {
2680 if (netif_running(dev))
2685 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2686 netif_poll_enable(hw->dev[0]);
2688 for (i = 0; i < hw->ports; i++) {
2690 if (netif_running(dev)) {
2693 printk(KERN_INFO PFX "%s: could not restart %d\n",
2700 sky2_idle_start(hw);
2705 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2707 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2710 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2712 const struct sky2_port *sky2 = netdev_priv(dev);
2714 wol->supported = sky2_wol_supported(sky2->hw);
2715 wol->wolopts = sky2->wol;
2718 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2720 struct sky2_port *sky2 = netdev_priv(dev);
2721 struct sky2_hw *hw = sky2->hw;
2723 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2726 sky2->wol = wol->wolopts;
2728 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2729 sky2_write32(hw, B0_CTST, sky2->wol
2730 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2732 if (!netif_running(dev))
2733 sky2_wol_init(sky2);
2737 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2739 if (sky2_is_copper(hw)) {
2740 u32 modes = SUPPORTED_10baseT_Half
2741 | SUPPORTED_10baseT_Full
2742 | SUPPORTED_100baseT_Half
2743 | SUPPORTED_100baseT_Full
2744 | SUPPORTED_Autoneg | SUPPORTED_TP;
2746 if (hw->chip_id != CHIP_ID_YUKON_FE)
2747 modes |= SUPPORTED_1000baseT_Half
2748 | SUPPORTED_1000baseT_Full;
2751 return SUPPORTED_1000baseT_Half
2752 | SUPPORTED_1000baseT_Full
2757 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2759 struct sky2_port *sky2 = netdev_priv(dev);
2760 struct sky2_hw *hw = sky2->hw;
2762 ecmd->transceiver = XCVR_INTERNAL;
2763 ecmd->supported = sky2_supported_modes(hw);
2764 ecmd->phy_address = PHY_ADDR_MARV;
2765 if (sky2_is_copper(hw)) {
2766 ecmd->supported = SUPPORTED_10baseT_Half
2767 | SUPPORTED_10baseT_Full
2768 | SUPPORTED_100baseT_Half
2769 | SUPPORTED_100baseT_Full
2770 | SUPPORTED_1000baseT_Half
2771 | SUPPORTED_1000baseT_Full
2772 | SUPPORTED_Autoneg | SUPPORTED_TP;
2773 ecmd->port = PORT_TP;
2774 ecmd->speed = sky2->speed;
2776 ecmd->speed = SPEED_1000;
2777 ecmd->port = PORT_FIBRE;
2780 ecmd->advertising = sky2->advertising;
2781 ecmd->autoneg = sky2->autoneg;
2782 ecmd->duplex = sky2->duplex;
2786 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2788 struct sky2_port *sky2 = netdev_priv(dev);
2789 const struct sky2_hw *hw = sky2->hw;
2790 u32 supported = sky2_supported_modes(hw);
2792 if (ecmd->autoneg == AUTONEG_ENABLE) {
2793 ecmd->advertising = supported;
2799 switch (ecmd->speed) {
2801 if (ecmd->duplex == DUPLEX_FULL)
2802 setting = SUPPORTED_1000baseT_Full;
2803 else if (ecmd->duplex == DUPLEX_HALF)
2804 setting = SUPPORTED_1000baseT_Half;
2809 if (ecmd->duplex == DUPLEX_FULL)
2810 setting = SUPPORTED_100baseT_Full;
2811 else if (ecmd->duplex == DUPLEX_HALF)
2812 setting = SUPPORTED_100baseT_Half;
2818 if (ecmd->duplex == DUPLEX_FULL)
2819 setting = SUPPORTED_10baseT_Full;
2820 else if (ecmd->duplex == DUPLEX_HALF)
2821 setting = SUPPORTED_10baseT_Half;
2829 if ((setting & supported) == 0)
2832 sky2->speed = ecmd->speed;
2833 sky2->duplex = ecmd->duplex;
2836 sky2->autoneg = ecmd->autoneg;
2837 sky2->advertising = ecmd->advertising;
2839 if (netif_running(dev))
2840 sky2_phy_reinit(sky2);
2845 static void sky2_get_drvinfo(struct net_device *dev,
2846 struct ethtool_drvinfo *info)
2848 struct sky2_port *sky2 = netdev_priv(dev);
2850 strcpy(info->driver, DRV_NAME);
2851 strcpy(info->version, DRV_VERSION);
2852 strcpy(info->fw_version, "N/A");
2853 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2856 static const struct sky2_stat {
2857 char name[ETH_GSTRING_LEN];
2860 { "tx_bytes", GM_TXO_OK_HI },
2861 { "rx_bytes", GM_RXO_OK_HI },
2862 { "tx_broadcast", GM_TXF_BC_OK },
2863 { "rx_broadcast", GM_RXF_BC_OK },
2864 { "tx_multicast", GM_TXF_MC_OK },
2865 { "rx_multicast", GM_RXF_MC_OK },
2866 { "tx_unicast", GM_TXF_UC_OK },
2867 { "rx_unicast", GM_RXF_UC_OK },
2868 { "tx_mac_pause", GM_TXF_MPAUSE },
2869 { "rx_mac_pause", GM_RXF_MPAUSE },
2870 { "collisions", GM_TXF_COL },
2871 { "late_collision",GM_TXF_LAT_COL },
2872 { "aborted", GM_TXF_ABO_COL },
2873 { "single_collisions", GM_TXF_SNG_COL },
2874 { "multi_collisions", GM_TXF_MUL_COL },
2876 { "rx_short", GM_RXF_SHT },
2877 { "rx_runt", GM_RXE_FRAG },
2878 { "rx_64_byte_packets", GM_RXF_64B },
2879 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2880 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2881 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2882 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2883 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2884 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2885 { "rx_too_long", GM_RXF_LNG_ERR },
2886 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2887 { "rx_jabber", GM_RXF_JAB_PKT },
2888 { "rx_fcs_error", GM_RXF_FCS_ERR },
2890 { "tx_64_byte_packets", GM_TXF_64B },
2891 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2892 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2893 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2894 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2895 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2896 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2897 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2900 static u32 sky2_get_rx_csum(struct net_device *dev)
2902 struct sky2_port *sky2 = netdev_priv(dev);
2904 return sky2->rx_csum;
2907 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2909 struct sky2_port *sky2 = netdev_priv(dev);
2911 sky2->rx_csum = data;
2913 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2914 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2919 static u32 sky2_get_msglevel(struct net_device *netdev)
2921 struct sky2_port *sky2 = netdev_priv(netdev);
2922 return sky2->msg_enable;
2925 static int sky2_nway_reset(struct net_device *dev)
2927 struct sky2_port *sky2 = netdev_priv(dev);
2929 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2932 sky2_phy_reinit(sky2);
2937 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2939 struct sky2_hw *hw = sky2->hw;
2940 unsigned port = sky2->port;
2943 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2944 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2945 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2946 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2948 for (i = 2; i < count; i++)
2949 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2952 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2954 struct sky2_port *sky2 = netdev_priv(netdev);
2955 sky2->msg_enable = value;
2958 static int sky2_get_stats_count(struct net_device *dev)
2960 return ARRAY_SIZE(sky2_stats);
2963 static void sky2_get_ethtool_stats(struct net_device *dev,
2964 struct ethtool_stats *stats, u64 * data)
2966 struct sky2_port *sky2 = netdev_priv(dev);
2968 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2971 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2975 switch (stringset) {
2977 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2978 memcpy(data + i * ETH_GSTRING_LEN,
2979 sky2_stats[i].name, ETH_GSTRING_LEN);
2984 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2986 struct sky2_port *sky2 = netdev_priv(dev);
2987 return &sky2->net_stats;
2990 static int sky2_set_mac_address(struct net_device *dev, void *p)
2992 struct sky2_port *sky2 = netdev_priv(dev);
2993 struct sky2_hw *hw = sky2->hw;
2994 unsigned port = sky2->port;
2995 const struct sockaddr *addr = p;
2997 if (!is_valid_ether_addr(addr->sa_data))
2998 return -EADDRNOTAVAIL;
3000 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3001 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3002 dev->dev_addr, ETH_ALEN);
3003 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3004 dev->dev_addr, ETH_ALEN);
3006 /* virtual address for data */
3007 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3009 /* physical address: used for pause frames */
3010 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3015 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3019 bit = ether_crc(ETH_ALEN, addr) & 63;
3020 filter[bit >> 3] |= 1 << (bit & 7);
3023 static void sky2_set_multicast(struct net_device *dev)
3025 struct sky2_port *sky2 = netdev_priv(dev);
3026 struct sky2_hw *hw = sky2->hw;
3027 unsigned port = sky2->port;
3028 struct dev_mc_list *list = dev->mc_list;
3032 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3034 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3035 memset(filter, 0, sizeof(filter));
3037 reg = gma_read16(hw, port, GM_RX_CTRL);
3038 reg |= GM_RXCR_UCF_ENA;
3040 if (dev->flags & IFF_PROMISC) /* promiscuous */
3041 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3042 else if (dev->flags & IFF_ALLMULTI)
3043 memset(filter, 0xff, sizeof(filter));
3044 else if (dev->mc_count == 0 && !rx_pause)
3045 reg &= ~GM_RXCR_MCF_ENA;
3048 reg |= GM_RXCR_MCF_ENA;
3051 sky2_add_filter(filter, pause_mc_addr);
3053 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3054 sky2_add_filter(filter, list->dmi_addr);
3057 gma_write16(hw, port, GM_MC_ADDR_H1,
3058 (u16) filter[0] | ((u16) filter[1] << 8));
3059 gma_write16(hw, port, GM_MC_ADDR_H2,
3060 (u16) filter[2] | ((u16) filter[3] << 8));
3061 gma_write16(hw, port, GM_MC_ADDR_H3,
3062 (u16) filter[4] | ((u16) filter[5] << 8));
3063 gma_write16(hw, port, GM_MC_ADDR_H4,
3064 (u16) filter[6] | ((u16) filter[7] << 8));
3066 gma_write16(hw, port, GM_RX_CTRL, reg);
3069 /* Can have one global because blinking is controlled by
3070 * ethtool and that is always under RTNL mutex
3072 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3076 switch (hw->chip_id) {
3077 case CHIP_ID_YUKON_XL:
3078 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3079 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3080 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3081 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3082 PHY_M_LEDC_INIT_CTRL(7) |
3083 PHY_M_LEDC_STA1_CTRL(7) |
3084 PHY_M_LEDC_STA0_CTRL(7))
3087 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3091 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3092 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3093 on ? PHY_M_LED_ALL : 0);
3097 /* blink LED's for finding board */
3098 static int sky2_phys_id(struct net_device *dev, u32 data)
3100 struct sky2_port *sky2 = netdev_priv(dev);
3101 struct sky2_hw *hw = sky2->hw;
3102 unsigned port = sky2->port;
3103 u16 ledctrl, ledover = 0;
3108 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3109 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3113 /* save initial values */
3114 spin_lock_bh(&sky2->phy_lock);
3115 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3116 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3117 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3118 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3119 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3121 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3122 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3126 while (!interrupted && ms > 0) {
3127 sky2_led(hw, port, onoff);
3130 spin_unlock_bh(&sky2->phy_lock);
3131 interrupted = msleep_interruptible(250);
3132 spin_lock_bh(&sky2->phy_lock);
3137 /* resume regularly scheduled programming */
3138 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3139 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3140 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3141 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3142 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3144 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3145 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3147 spin_unlock_bh(&sky2->phy_lock);
3152 static void sky2_get_pauseparam(struct net_device *dev,
3153 struct ethtool_pauseparam *ecmd)
3155 struct sky2_port *sky2 = netdev_priv(dev);
3157 switch (sky2->flow_mode) {
3159 ecmd->tx_pause = ecmd->rx_pause = 0;
3162 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3165 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3168 ecmd->tx_pause = ecmd->rx_pause = 1;
3171 ecmd->autoneg = sky2->autoneg;
3174 static int sky2_set_pauseparam(struct net_device *dev,
3175 struct ethtool_pauseparam *ecmd)
3177 struct sky2_port *sky2 = netdev_priv(dev);
3179 sky2->autoneg = ecmd->autoneg;
3180 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3182 if (netif_running(dev))
3183 sky2_phy_reinit(sky2);
3188 static int sky2_get_coalesce(struct net_device *dev,
3189 struct ethtool_coalesce *ecmd)
3191 struct sky2_port *sky2 = netdev_priv(dev);
3192 struct sky2_hw *hw = sky2->hw;
3194 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3195 ecmd->tx_coalesce_usecs = 0;
3197 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3198 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3200 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3202 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3203 ecmd->rx_coalesce_usecs = 0;
3205 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3206 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3208 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3210 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3211 ecmd->rx_coalesce_usecs_irq = 0;
3213 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3214 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3217 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3222 /* Note: this affect both ports */
3223 static int sky2_set_coalesce(struct net_device *dev,
3224 struct ethtool_coalesce *ecmd)
3226 struct sky2_port *sky2 = netdev_priv(dev);
3227 struct sky2_hw *hw = sky2->hw;
3228 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3230 if (ecmd->tx_coalesce_usecs > tmax ||
3231 ecmd->rx_coalesce_usecs > tmax ||
3232 ecmd->rx_coalesce_usecs_irq > tmax)
3235 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3237 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3239 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3242 if (ecmd->tx_coalesce_usecs == 0)
3243 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3245 sky2_write32(hw, STAT_TX_TIMER_INI,
3246 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3247 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3249 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3251 if (ecmd->rx_coalesce_usecs == 0)
3252 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3254 sky2_write32(hw, STAT_LEV_TIMER_INI,
3255 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3256 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3258 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3260 if (ecmd->rx_coalesce_usecs_irq == 0)
3261 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3263 sky2_write32(hw, STAT_ISR_TIMER_INI,
3264 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3265 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3267 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3271 static void sky2_get_ringparam(struct net_device *dev,
3272 struct ethtool_ringparam *ering)
3274 struct sky2_port *sky2 = netdev_priv(dev);
3276 ering->rx_max_pending = RX_MAX_PENDING;
3277 ering->rx_mini_max_pending = 0;
3278 ering->rx_jumbo_max_pending = 0;
3279 ering->tx_max_pending = TX_RING_SIZE - 1;
3281 ering->rx_pending = sky2->rx_pending;
3282 ering->rx_mini_pending = 0;
3283 ering->rx_jumbo_pending = 0;
3284 ering->tx_pending = sky2->tx_pending;
3287 static int sky2_set_ringparam(struct net_device *dev,
3288 struct ethtool_ringparam *ering)
3290 struct sky2_port *sky2 = netdev_priv(dev);
3293 if (ering->rx_pending > RX_MAX_PENDING ||
3294 ering->rx_pending < 8 ||
3295 ering->tx_pending < MAX_SKB_TX_LE ||
3296 ering->tx_pending > TX_RING_SIZE - 1)
3299 if (netif_running(dev))
3302 sky2->rx_pending = ering->rx_pending;
3303 sky2->tx_pending = ering->tx_pending;
3305 if (netif_running(dev)) {
3310 sky2_set_multicast(dev);
3316 static int sky2_get_regs_len(struct net_device *dev)
3322 * Returns copy of control register region
3323 * Note: access to the RAM address register set will cause timeouts.
3325 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3328 const struct sky2_port *sky2 = netdev_priv(dev);
3329 const void __iomem *io = sky2->hw->regs;
3331 BUG_ON(regs->len < B3_RI_WTO_R1);
3333 memset(p, 0, regs->len);
3335 memcpy_fromio(p, io, B3_RAM_ADDR);
3337 memcpy_fromio(p + B3_RI_WTO_R1,
3339 regs->len - B3_RI_WTO_R1);
3342 /* In order to do Jumbo packets on these chips, need to turn off the
3343 * transmit store/forward. Therefore checksum offload won't work.
3345 static int no_tx_offload(struct net_device *dev)
3347 const struct sky2_port *sky2 = netdev_priv(dev);
3348 const struct sky2_hw *hw = sky2->hw;
3350 return dev->mtu > ETH_DATA_LEN &&
3351 (hw->chip_id == CHIP_ID_YUKON_EX
3352 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3355 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3357 if (data && no_tx_offload(dev))
3360 return ethtool_op_set_tx_csum(dev, data);
3364 static int sky2_set_tso(struct net_device *dev, u32 data)
3366 if (data && no_tx_offload(dev))
3369 return ethtool_op_set_tso(dev, data);
3372 static const struct ethtool_ops sky2_ethtool_ops = {
3373 .get_settings = sky2_get_settings,
3374 .set_settings = sky2_set_settings,
3375 .get_drvinfo = sky2_get_drvinfo,
3376 .get_wol = sky2_get_wol,
3377 .set_wol = sky2_set_wol,
3378 .get_msglevel = sky2_get_msglevel,
3379 .set_msglevel = sky2_set_msglevel,
3380 .nway_reset = sky2_nway_reset,
3381 .get_regs_len = sky2_get_regs_len,
3382 .get_regs = sky2_get_regs,
3383 .get_link = ethtool_op_get_link,
3384 .get_sg = ethtool_op_get_sg,
3385 .set_sg = ethtool_op_set_sg,
3386 .get_tx_csum = ethtool_op_get_tx_csum,
3387 .set_tx_csum = sky2_set_tx_csum,
3388 .get_tso = ethtool_op_get_tso,
3389 .set_tso = sky2_set_tso,
3390 .get_rx_csum = sky2_get_rx_csum,
3391 .set_rx_csum = sky2_set_rx_csum,
3392 .get_strings = sky2_get_strings,
3393 .get_coalesce = sky2_get_coalesce,
3394 .set_coalesce = sky2_set_coalesce,
3395 .get_ringparam = sky2_get_ringparam,
3396 .set_ringparam = sky2_set_ringparam,
3397 .get_pauseparam = sky2_get_pauseparam,
3398 .set_pauseparam = sky2_set_pauseparam,
3399 .phys_id = sky2_phys_id,
3400 .get_stats_count = sky2_get_stats_count,
3401 .get_ethtool_stats = sky2_get_ethtool_stats,
3402 .get_perm_addr = ethtool_op_get_perm_addr,
3405 /* Initialize network device */
3406 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3408 int highmem, int wol)
3410 struct sky2_port *sky2;
3411 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3414 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3418 SET_MODULE_OWNER(dev);
3419 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3420 dev->irq = hw->pdev->irq;
3421 dev->open = sky2_up;
3422 dev->stop = sky2_down;
3423 dev->do_ioctl = sky2_ioctl;
3424 dev->hard_start_xmit = sky2_xmit_frame;
3425 dev->get_stats = sky2_get_stats;
3426 dev->set_multicast_list = sky2_set_multicast;
3427 dev->set_mac_address = sky2_set_mac_address;
3428 dev->change_mtu = sky2_change_mtu;
3429 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3430 dev->tx_timeout = sky2_tx_timeout;
3431 dev->watchdog_timeo = TX_WATCHDOG;
3433 dev->poll = sky2_poll;
3434 dev->weight = NAPI_WEIGHT;
3435 #ifdef CONFIG_NET_POLL_CONTROLLER
3436 /* Network console (only works on port 0)
3437 * because netpoll makes assumptions about NAPI
3440 dev->poll_controller = sky2_netpoll;
3443 sky2 = netdev_priv(dev);
3446 sky2->msg_enable = netif_msg_init(debug, default_msg);
3448 /* Auto speed and flow control */
3449 sky2->autoneg = AUTONEG_ENABLE;
3450 sky2->flow_mode = FC_BOTH;
3454 sky2->advertising = sky2_supported_modes(hw);
3458 spin_lock_init(&sky2->phy_lock);
3459 sky2->tx_pending = TX_DEF_PENDING;
3460 sky2->rx_pending = RX_DEF_PENDING;
3462 hw->dev[port] = dev;
3466 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3468 dev->features |= NETIF_F_HIGHDMA;
3470 #ifdef SKY2_VLAN_TAG_USED
3471 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3472 dev->vlan_rx_register = sky2_vlan_rx_register;
3473 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3476 /* read the mac address */
3477 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3478 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3480 /* device is off until link detection */
3481 netif_carrier_off(dev);
3482 netif_stop_queue(dev);
3487 static void __devinit sky2_show_addr(struct net_device *dev)
3489 const struct sky2_port *sky2 = netdev_priv(dev);
3491 if (netif_msg_probe(sky2))
3492 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3494 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3495 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3498 /* Handle software interrupt used during MSI test */
3499 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3501 struct sky2_hw *hw = dev_id;
3502 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3507 if (status & Y2_IS_IRQ_SW) {
3509 wake_up(&hw->msi_wait);
3510 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3512 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3517 /* Test interrupt path by forcing a a software IRQ */
3518 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3520 struct pci_dev *pdev = hw->pdev;
3523 init_waitqueue_head (&hw->msi_wait);
3525 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3527 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3529 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3533 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3534 sky2_read8(hw, B0_CTST);
3536 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3539 /* MSI test failed, go back to INTx mode */
3540 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3541 "switching to INTx mode.\n");
3544 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3547 sky2_write32(hw, B0_IMSK, 0);
3548 sky2_read32(hw, B0_IMSK);
3550 free_irq(pdev->irq, hw);
3555 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3557 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3562 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3564 return value & PCI_PM_CTRL_PME_ENABLE;
3567 static int __devinit sky2_probe(struct pci_dev *pdev,
3568 const struct pci_device_id *ent)
3570 struct net_device *dev;
3572 int err, using_dac = 0, wol_default;
3574 err = pci_enable_device(pdev);
3576 dev_err(&pdev->dev, "cannot enable PCI device\n");
3580 err = pci_request_regions(pdev, DRV_NAME);
3582 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3586 pci_set_master(pdev);
3588 if (sizeof(dma_addr_t) > sizeof(u32) &&
3589 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3591 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3593 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3594 "for consistent allocations\n");
3595 goto err_out_free_regions;
3598 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3600 dev_err(&pdev->dev, "no usable DMA configuration\n");
3601 goto err_out_free_regions;
3605 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3608 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3610 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3611 goto err_out_free_regions;
3616 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3618 dev_err(&pdev->dev, "cannot map device registers\n");
3619 goto err_out_free_hw;
3623 /* The sk98lin vendor driver uses hardware byte swapping but
3624 * this driver uses software swapping.
3628 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3629 reg &= ~PCI_REV_DESC;
3630 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3634 /* ring for status responses */
3635 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3638 goto err_out_iounmap;
3640 err = sky2_init(hw);
3642 goto err_out_iounmap;
3644 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3645 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3646 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3647 hw->chip_id, hw->chip_rev);
3651 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3654 goto err_out_free_pci;
3657 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3658 err = sky2_test_msi(hw);
3659 if (err == -EOPNOTSUPP)
3660 pci_disable_msi(pdev);
3662 goto err_out_free_netdev;
3665 err = register_netdev(dev);
3667 dev_err(&pdev->dev, "cannot register net device\n");
3668 goto err_out_free_netdev;
3671 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3674 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3675 goto err_out_unregister;
3677 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3679 sky2_show_addr(dev);
3681 if (hw->ports > 1) {
3682 struct net_device *dev1;
3684 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3686 dev_warn(&pdev->dev, "allocation for second device failed\n");
3687 else if ((err = register_netdev(dev1))) {
3688 dev_warn(&pdev->dev,
3689 "register of second port failed (%d)\n", err);
3693 sky2_show_addr(dev1);
3696 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3697 INIT_WORK(&hw->restart_work, sky2_restart);
3699 sky2_idle_start(hw);
3701 pci_set_drvdata(pdev, hw);
3707 pci_disable_msi(pdev);
3708 unregister_netdev(dev);
3709 err_out_free_netdev:
3712 sky2_write8(hw, B0_CTST, CS_RST_SET);
3713 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3718 err_out_free_regions:
3719 pci_release_regions(pdev);
3720 pci_disable_device(pdev);
3725 static void __devexit sky2_remove(struct pci_dev *pdev)
3727 struct sky2_hw *hw = pci_get_drvdata(pdev);
3728 struct net_device *dev0, *dev1;
3733 del_timer_sync(&hw->idle_timer);
3735 flush_scheduled_work();
3737 sky2_write32(hw, B0_IMSK, 0);
3738 synchronize_irq(hw->pdev->irq);
3743 unregister_netdev(dev1);
3744 unregister_netdev(dev0);
3748 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3749 sky2_write8(hw, B0_CTST, CS_RST_SET);
3750 sky2_read8(hw, B0_CTST);
3752 free_irq(pdev->irq, hw);
3754 pci_disable_msi(pdev);
3755 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3756 pci_release_regions(pdev);
3757 pci_disable_device(pdev);
3765 pci_set_drvdata(pdev, NULL);
3769 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3771 struct sky2_hw *hw = pci_get_drvdata(pdev);
3774 del_timer_sync(&hw->idle_timer);
3775 netif_poll_disable(hw->dev[0]);
3777 for (i = 0; i < hw->ports; i++) {
3778 struct net_device *dev = hw->dev[i];
3779 struct sky2_port *sky2 = netdev_priv(dev);
3781 if (netif_running(dev))
3785 sky2_wol_init(sky2);
3790 sky2_write32(hw, B0_IMSK, 0);
3793 pci_save_state(pdev);
3794 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3795 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3800 static int sky2_resume(struct pci_dev *pdev)
3802 struct sky2_hw *hw = pci_get_drvdata(pdev);
3805 err = pci_set_power_state(pdev, PCI_D0);
3809 err = pci_restore_state(pdev);
3813 pci_enable_wake(pdev, PCI_D0, 0);
3815 /* Re-enable all clocks */
3816 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3817 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3821 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3823 for (i = 0; i < hw->ports; i++) {
3824 struct net_device *dev = hw->dev[i];
3825 if (netif_running(dev)) {
3828 printk(KERN_ERR PFX "%s: could not up: %d\n",
3836 netif_poll_enable(hw->dev[0]);
3837 sky2_idle_start(hw);
3840 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3841 pci_disable_device(pdev);
3846 static void sky2_shutdown(struct pci_dev *pdev)
3848 struct sky2_hw *hw = pci_get_drvdata(pdev);
3851 del_timer_sync(&hw->idle_timer);
3852 netif_poll_disable(hw->dev[0]);
3854 for (i = 0; i < hw->ports; i++) {
3855 struct net_device *dev = hw->dev[i];
3856 struct sky2_port *sky2 = netdev_priv(dev);
3860 sky2_wol_init(sky2);
3867 pci_enable_wake(pdev, PCI_D3hot, wol);
3868 pci_enable_wake(pdev, PCI_D3cold, wol);
3870 pci_disable_device(pdev);
3871 pci_set_power_state(pdev, PCI_D3hot);
3875 static struct pci_driver sky2_driver = {
3877 .id_table = sky2_id_table,
3878 .probe = sky2_probe,
3879 .remove = __devexit_p(sky2_remove),
3881 .suspend = sky2_suspend,
3882 .resume = sky2_resume,
3884 .shutdown = sky2_shutdown,
3887 static int __init sky2_init_module(void)
3889 return pci_register_driver(&sky2_driver);
3892 static void __exit sky2_cleanup_module(void)
3894 pci_unregister_driver(&sky2_driver);
3897 module_init(sky2_init_module);
3898 module_exit(sky2_cleanup_module);
3900 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3901 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3902 MODULE_LICENSE("GPL");
3903 MODULE_VERSION(DRV_VERSION);