1 /* $Id: sunhme.c,v 1.124 2002/01/15 06:25:51 davem Exp $
2 * sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
3 * auto carrier detecting ethernet driver. Also known as the
4 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
6 * Copyright (C) 1996, 1998, 1999, 2002, 2003 David S. Miller (davem@redhat.com)
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
16 #include <linux/config.h>
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/fcntl.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
24 #include <linux/slab.h>
25 #include <linux/string.h>
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ethtool.h>
29 #include <linux/mii.h>
30 #include <linux/crc32.h>
31 #include <linux/random.h>
32 #include <linux/errno.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/bitops.h>
38 #include <asm/system.h>
41 #include <asm/byteorder.h>
44 #include <asm/idprom.h>
46 #include <asm/openprom.h>
47 #include <asm/oplib.h>
49 #include <asm/auxio.h>
50 #ifndef CONFIG_SPARC64
51 #include <asm/io-unit.h>
54 #include <asm/uaccess.h>
56 #include <asm/pgtable.h>
60 #include <linux/pci.h>
68 #define DRV_NAME "sunhme"
69 #define DRV_VERSION "2.02"
70 #define DRV_RELDATE "8/24/03"
71 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
73 static char version[] =
74 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
76 MODULE_VERSION(DRV_VERSION);
77 MODULE_AUTHOR(DRV_AUTHOR);
78 MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
79 MODULE_LICENSE("GPL");
81 static int macaddr[6];
83 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
84 module_param_array(macaddr, int, NULL, 0);
85 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
87 static struct happy_meal *root_happy_dev;
90 static struct quattro *qfe_sbus_list;
94 static struct quattro *qfe_pci_list;
104 struct hme_tx_logent {
108 #define TXLOG_ACTION_IRQ 0x01
109 #define TXLOG_ACTION_TXMIT 0x02
110 #define TXLOG_ACTION_TBUSY 0x04
111 #define TXLOG_ACTION_NBUFS 0x08
114 #define TX_LOG_LEN 128
115 static struct hme_tx_logent tx_log[TX_LOG_LEN];
116 static int txlog_cur_entry;
117 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
119 struct hme_tx_logent *tlp;
123 tlp = &tx_log[txlog_cur_entry];
124 tlp->tstamp = (unsigned int)jiffies;
125 tlp->tx_new = hp->tx_new;
126 tlp->tx_old = hp->tx_old;
129 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
130 restore_flags(flags);
132 static __inline__ void tx_dump_log(void)
136 this = txlog_cur_entry;
137 for (i = 0; i < TX_LOG_LEN; i++) {
138 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
140 tx_log[this].tx_new, tx_log[this].tx_old,
141 tx_log[this].action, tx_log[this].status);
142 this = (this + 1) & (TX_LOG_LEN - 1);
145 static __inline__ void tx_dump_ring(struct happy_meal *hp)
147 struct hmeal_init_block *hb = hp->happy_block;
148 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
151 for (i = 0; i < TX_RING_SIZE; i+=4) {
152 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
154 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
155 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
156 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
157 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
161 #define tx_add_log(hp, a, s) do { } while(0)
162 #define tx_dump_log() do { } while(0)
163 #define tx_dump_ring(hp) do { } while(0)
167 #define HMD(x) printk x
172 /* #define AUTO_SWITCH_DEBUG */
174 #ifdef AUTO_SWITCH_DEBUG
175 #define ASD(x) printk x
180 #define DEFAULT_IPG0 16 /* For lance-mode only */
181 #define DEFAULT_IPG1 8 /* For all modes */
182 #define DEFAULT_IPG2 4 /* For all modes */
183 #define DEFAULT_JAMSIZE 4 /* Toe jam */
185 #if defined(CONFIG_PCI) && defined(MODULE)
186 /* This happy_pci_ids is declared __initdata because it is only used
187 as an advisory to depmod. If this is ported to the new PCI interface
188 where it could be referenced at any time due to hot plugging,
189 the __initdata reference should be removed. */
191 static struct pci_device_id happymeal_pci_ids[] = {
193 .vendor = PCI_VENDOR_ID_SUN,
194 .device = PCI_DEVICE_ID_SUN_HAPPYMEAL,
195 .subvendor = PCI_ANY_ID,
196 .subdevice = PCI_ANY_ID,
198 { } /* Terminating entry */
201 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
205 /* NOTE: In the descriptor writes one _must_ write the address
206 * member _first_. The card must not be allowed to see
207 * the updated descriptor flags until the address is
208 * correct. I've added a write memory barrier between
209 * the two stores so that I can sleep well at night... -DaveM
212 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
213 static void sbus_hme_write32(void __iomem *reg, u32 val)
215 sbus_writel(val, reg);
218 static u32 sbus_hme_read32(void __iomem *reg)
220 return sbus_readl(reg);
223 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
227 rxd->rx_flags = flags;
230 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
234 txd->tx_flags = flags;
237 static u32 sbus_hme_read_desc32(u32 *p)
242 static void pci_hme_write32(void __iomem *reg, u32 val)
247 static u32 pci_hme_read32(void __iomem *reg)
252 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
254 rxd->rx_addr = cpu_to_le32(addr);
256 rxd->rx_flags = cpu_to_le32(flags);
259 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
261 txd->tx_addr = cpu_to_le32(addr);
263 txd->tx_flags = cpu_to_le32(flags);
266 static u32 pci_hme_read_desc32(u32 *p)
268 return cpu_to_le32p(p);
271 #define hme_write32(__hp, __reg, __val) \
272 ((__hp)->write32((__reg), (__val)))
273 #define hme_read32(__hp, __reg) \
274 ((__hp)->read32(__reg))
275 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
276 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
277 #define hme_write_txd(__hp, __txd, __flags, __addr) \
278 ((__hp)->write_txd((__txd), (__flags), (__addr)))
279 #define hme_read_desc32(__hp, __p) \
280 ((__hp)->read_desc32(__p))
281 #define hme_dma_map(__hp, __ptr, __size, __dir) \
282 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
283 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
284 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
285 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
286 ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)))
287 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
288 ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)))
291 /* SBUS only compilation */
292 #define hme_write32(__hp, __reg, __val) \
293 sbus_writel((__val), (__reg))
294 #define hme_read32(__hp, __reg) \
296 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
297 do { (__rxd)->rx_addr = (__addr); \
299 (__rxd)->rx_flags = (__flags); \
301 #define hme_write_txd(__hp, __txd, __flags, __addr) \
302 do { (__txd)->tx_addr = (__addr); \
304 (__txd)->tx_flags = (__flags); \
306 #define hme_read_desc32(__hp, __p) (*(__p))
307 #define hme_dma_map(__hp, __ptr, __size, __dir) \
308 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
309 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
310 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
311 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
312 sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
313 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
314 sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
316 /* PCI only compilation */
317 #define hme_write32(__hp, __reg, __val) \
318 writel((__val), (__reg))
319 #define hme_read32(__hp, __reg) \
321 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
322 do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
324 (__rxd)->rx_flags = cpu_to_le32(__flags); \
326 #define hme_write_txd(__hp, __txd, __flags, __addr) \
327 do { (__txd)->tx_addr = cpu_to_le32(__addr); \
329 (__txd)->tx_flags = cpu_to_le32(__flags); \
331 #define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
332 #define hme_dma_map(__hp, __ptr, __size, __dir) \
333 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
334 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
335 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
336 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
337 pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
338 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
339 pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
344 #ifdef SBUS_DMA_BIDIRECTIONAL
345 # define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
347 # define DMA_BIDIRECTIONAL 0
350 #ifdef SBUS_DMA_FROMDEVICE
351 # define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
353 # define DMA_TODEVICE 1
356 #ifdef SBUS_DMA_TODEVICE
357 # define DMA_TODEVICE SBUS_DMA_TODEVICE
359 # define DMA_FROMDEVICE 2
363 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
364 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
366 hme_write32(hp, tregs + TCVR_BBDATA, bit);
367 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
368 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
372 static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
376 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
377 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
378 ret = hme_read32(hp, tregs + TCVR_CFG);
380 ret &= TCV_CFG_MDIO0;
382 ret &= TCV_CFG_MDIO1;
388 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
392 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
394 retval = hme_read32(hp, tregs + TCVR_CFG);
396 retval &= TCV_CFG_MDIO0;
398 retval &= TCV_CFG_MDIO1;
399 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
404 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
406 static int happy_meal_bb_read(struct happy_meal *hp,
407 void __iomem *tregs, int reg)
413 ASD(("happy_meal_bb_read: reg=%d ", reg));
415 /* Enable the MIF BitBang outputs. */
416 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
418 /* Force BitBang into the idle state. */
419 for (i = 0; i < 32; i++)
420 BB_PUT_BIT(hp, tregs, 1);
422 /* Give it the read sequence. */
423 BB_PUT_BIT(hp, tregs, 0);
424 BB_PUT_BIT(hp, tregs, 1);
425 BB_PUT_BIT(hp, tregs, 1);
426 BB_PUT_BIT(hp, tregs, 0);
428 /* Give it the PHY address. */
429 tmp = hp->paddr & 0xff;
430 for (i = 4; i >= 0; i--)
431 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
433 /* Tell it what register we want to read. */
435 for (i = 4; i >= 0; i--)
436 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
438 /* Close down the MIF BitBang outputs. */
439 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
441 /* Now read in the value. */
442 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
443 for (i = 15; i >= 0; i--)
444 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
445 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
446 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
447 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
448 ASD(("value=%x\n", retval));
452 static void happy_meal_bb_write(struct happy_meal *hp,
453 void __iomem *tregs, int reg,
454 unsigned short value)
459 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
461 /* Enable the MIF BitBang outputs. */
462 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
464 /* Force BitBang into the idle state. */
465 for (i = 0; i < 32; i++)
466 BB_PUT_BIT(hp, tregs, 1);
468 /* Give it write sequence. */
469 BB_PUT_BIT(hp, tregs, 0);
470 BB_PUT_BIT(hp, tregs, 1);
471 BB_PUT_BIT(hp, tregs, 0);
472 BB_PUT_BIT(hp, tregs, 1);
474 /* Give it the PHY address. */
475 tmp = (hp->paddr & 0xff);
476 for (i = 4; i >= 0; i--)
477 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
479 /* Tell it what register we will be writing. */
481 for (i = 4; i >= 0; i--)
482 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
484 /* Tell it to become ready for the bits. */
485 BB_PUT_BIT(hp, tregs, 1);
486 BB_PUT_BIT(hp, tregs, 0);
488 for (i = 15; i >= 0; i--)
489 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
491 /* Close down the MIF BitBang outputs. */
492 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
495 #define TCVR_READ_TRIES 16
497 static int happy_meal_tcvr_read(struct happy_meal *hp,
498 void __iomem *tregs, int reg)
500 int tries = TCVR_READ_TRIES;
503 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
504 if (hp->tcvr_type == none) {
505 ASD(("no transceiver, value=TCVR_FAILURE\n"));
509 if (!(hp->happy_flags & HFLAG_FENABLE)) {
510 ASD(("doing bit bang\n"));
511 return happy_meal_bb_read(hp, tregs, reg);
514 hme_write32(hp, tregs + TCVR_FRAME,
515 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
516 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
519 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
522 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
523 ASD(("value=%04x\n", retval));
527 #define TCVR_WRITE_TRIES 16
529 static void happy_meal_tcvr_write(struct happy_meal *hp,
530 void __iomem *tregs, int reg,
531 unsigned short value)
533 int tries = TCVR_WRITE_TRIES;
535 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
537 /* Welcome to Sun Microsystems, can I take your order please? */
538 if (!(hp->happy_flags & HFLAG_FENABLE)) {
539 happy_meal_bb_write(hp, tregs, reg, value);
543 /* Would you like fries with that? */
544 hme_write32(hp, tregs + TCVR_FRAME,
545 (FRAME_WRITE | (hp->paddr << 23) |
546 ((reg & 0xff) << 18) | (value & 0xffff)));
547 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
552 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
554 /* Fifty-two cents is your change, have a nice day. */
557 /* Auto negotiation. The scheme is very simple. We have a timer routine
558 * that keeps watching the auto negotiation process as it progresses.
559 * The DP83840 is first told to start doing it's thing, we set up the time
560 * and place the timer state machine in it's initial state.
562 * Here the timer peeks at the DP83840 status registers at each click to see
563 * if the auto negotiation has completed, we assume here that the DP83840 PHY
564 * will time out at some point and just tell us what (didn't) happen. For
565 * complete coverage we only allow so many of the ticks at this level to run,
566 * when this has expired we print a warning message and try another strategy.
567 * This "other" strategy is to force the interface into various speed/duplex
568 * configurations and we stop when we see a link-up condition before the
569 * maximum number of "peek" ticks have occurred.
571 * Once a valid link status has been detected we configure the BigMAC and
572 * the rest of the Happy Meal to speak the most efficient protocol we could
573 * get a clean link for. The priority for link configurations, highest first
575 * 100 Base-T Full Duplex
576 * 100 Base-T Half Duplex
577 * 10 Base-T Full Duplex
578 * 10 Base-T Half Duplex
580 * We start a new timer now, after a successful auto negotiation status has
581 * been detected. This timer just waits for the link-up bit to get set in
582 * the BMCR of the DP83840. When this occurs we print a kernel log message
583 * describing the link type in use and the fact that it is up.
585 * If a fatal error of some sort is signalled and detected in the interrupt
586 * service routine, and the chip is reset, or the link is ifconfig'd down
587 * and then back up, this entire process repeats itself all over again.
589 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
591 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
593 /* Downgrade from full to half duplex. Only possible
596 if (hp->sw_bmcr & BMCR_FULLDPLX) {
597 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
598 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
602 /* Downgrade from 100 to 10. */
603 if (hp->sw_bmcr & BMCR_SPEED100) {
604 hp->sw_bmcr &= ~(BMCR_SPEED100);
605 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
609 /* We've tried everything. */
613 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
615 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
616 if (hp->tcvr_type == external)
620 printk("transceiver at ");
621 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
622 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
623 if (hp->sw_lpa & LPA_100FULL)
624 printk("100Mb/s, Full Duplex.\n");
626 printk("100Mb/s, Half Duplex.\n");
628 if (hp->sw_lpa & LPA_10FULL)
629 printk("10Mb/s, Full Duplex.\n");
631 printk("10Mb/s, Half Duplex.\n");
635 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
637 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
638 if (hp->tcvr_type == external)
642 printk("transceiver at ");
643 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
644 if (hp->sw_bmcr & BMCR_SPEED100)
648 if (hp->sw_bmcr & BMCR_FULLDPLX)
649 printk("Full Duplex.\n");
651 printk("Half Duplex.\n");
654 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
658 /* All we care about is making sure the bigmac tx_cfg has a
659 * proper duplex setting.
661 if (hp->timer_state == arbwait) {
662 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
663 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
665 if (hp->sw_lpa & LPA_100FULL)
667 else if (hp->sw_lpa & LPA_100HALF)
669 else if (hp->sw_lpa & LPA_10FULL)
674 /* Forcing a link mode. */
675 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
676 if (hp->sw_bmcr & BMCR_FULLDPLX)
682 /* Before changing other bits in the tx_cfg register, and in
683 * general any of other the TX config registers too, you
686 * 2) Poll with reads until that bit reads back as zero
687 * 3) Make TX configuration changes
688 * 4) Set Enable once more
690 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
691 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
692 ~(BIGMAC_TXCFG_ENABLE));
693 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
696 hp->happy_flags |= HFLAG_FULL;
697 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
698 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
699 BIGMAC_TXCFG_FULLDPLX);
701 hp->happy_flags &= ~(HFLAG_FULL);
702 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
703 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
704 ~(BIGMAC_TXCFG_FULLDPLX));
706 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
707 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
708 BIGMAC_TXCFG_ENABLE);
714 static int happy_meal_init(struct happy_meal *hp);
716 static int is_lucent_phy(struct happy_meal *hp)
718 void __iomem *tregs = hp->tcvregs;
719 unsigned short mr2, mr3;
722 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
723 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
724 if ((mr2 & 0xffff) == 0x0180 &&
725 ((mr3 & 0xffff) >> 10) == 0x1d)
731 static void happy_meal_timer(unsigned long data)
733 struct happy_meal *hp = (struct happy_meal *) data;
734 void __iomem *tregs = hp->tcvregs;
735 int restart_timer = 0;
737 spin_lock_irq(&hp->happy_lock);
740 switch(hp->timer_state) {
742 /* Only allow for 5 ticks, thats 10 seconds and much too
743 * long to wait for arbitration to complete.
745 if (hp->timer_ticks >= 10) {
746 /* Enter force mode. */
748 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
749 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
751 hp->sw_bmcr = BMCR_SPEED100;
752 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
754 if (!is_lucent_phy(hp)) {
755 /* OK, seems we need do disable the transceiver for the first
756 * tick to make sure we get an accurate link state at the
759 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
760 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
761 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
763 hp->timer_state = ltrywait;
767 /* Anything interesting happen? */
768 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
769 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
772 /* Just what we've been waiting for... */
773 ret = set_happy_link_modes(hp, tregs);
775 /* Ooops, something bad happened, go to force
778 * XXX Broken hubs which don't support 802.3u
779 * XXX auto-negotiation make this happen as well.
784 /* Success, at least so far, advance our state engine. */
785 hp->timer_state = lupwait;
794 /* Auto negotiation was successful and we are awaiting a
795 * link up status. I have decided to let this timer run
796 * forever until some sort of error is signalled, reporting
797 * a message to the user at 10 second intervals.
799 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
800 if (hp->sw_bmsr & BMSR_LSTATUS) {
801 /* Wheee, it's up, display the link mode in use and put
802 * the timer to sleep.
804 display_link_mode(hp, tregs);
805 hp->timer_state = asleep;
808 if (hp->timer_ticks >= 10) {
809 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
810 "not completely up.\n", hp->dev->name);
820 /* Making the timeout here too long can make it take
821 * annoyingly long to attempt all of the link mode
822 * permutations, but then again this is essentially
823 * error recovery code for the most part.
825 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
826 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
827 if (hp->timer_ticks == 1) {
828 if (!is_lucent_phy(hp)) {
829 /* Re-enable transceiver, we'll re-enable the transceiver next
830 * tick, then check link state on the following tick.
832 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
833 happy_meal_tcvr_write(hp, tregs,
834 DP83840_CSCONFIG, hp->sw_csconfig);
839 if (hp->timer_ticks == 2) {
840 if (!is_lucent_phy(hp)) {
841 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
842 happy_meal_tcvr_write(hp, tregs,
843 DP83840_CSCONFIG, hp->sw_csconfig);
848 if (hp->sw_bmsr & BMSR_LSTATUS) {
849 /* Force mode selection success. */
850 display_forced_link_mode(hp, tregs);
851 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
852 hp->timer_state = asleep;
855 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
858 ret = try_next_permutation(hp, tregs);
860 /* Aieee, tried them all, reset the
861 * chip and try all over again.
864 /* Let the user know... */
865 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
868 ret = happy_meal_init(hp);
871 printk(KERN_ERR "%s: Error, cannot re-init the "
872 "Happy Meal.\n", hp->dev->name);
876 if (!is_lucent_phy(hp)) {
877 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
879 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
880 happy_meal_tcvr_write(hp, tregs,
881 DP83840_CSCONFIG, hp->sw_csconfig);
893 /* Can't happens.... */
894 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
898 hp->timer_state = asleep; /* foo on you */
903 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
904 add_timer(&hp->happy_timer);
908 spin_unlock_irq(&hp->happy_lock);
911 #define TX_RESET_TRIES 32
912 #define RX_RESET_TRIES 32
914 /* hp->happy_lock must be held */
915 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
917 int tries = TX_RESET_TRIES;
919 HMD(("happy_meal_tx_reset: reset, "));
921 /* Would you like to try our SMCC Delux? */
922 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
923 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
926 /* Lettuce, tomato, buggy hardware (no extra charge)? */
928 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
934 /* hp->happy_lock must be held */
935 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
937 int tries = RX_RESET_TRIES;
939 HMD(("happy_meal_rx_reset: reset, "));
941 /* We have a special on GNU/Viking hardware bugs today. */
942 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
943 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
946 /* Will that be all? */
948 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
950 /* Don't forget your vik_1137125_wa. Have a nice day. */
954 #define STOP_TRIES 16
956 /* hp->happy_lock must be held */
957 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
959 int tries = STOP_TRIES;
961 HMD(("happy_meal_stop: reset, "));
963 /* We're consolidating our STB products, it's your lucky day. */
964 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
965 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
968 /* Come back next week when we are "Sun Microelectronics". */
970 printk(KERN_ERR "happy meal: Fry guys.");
972 /* Remember: "Different name, same old buggy as shit hardware." */
976 /* hp->happy_lock must be held */
977 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
979 struct net_device_stats *stats = &hp->net_stats;
981 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
982 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
984 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
985 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
987 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
988 hme_write32(hp, bregs + BMAC_GLECTR, 0);
990 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
993 (hme_read32(hp, bregs + BMAC_EXCTR) +
994 hme_read32(hp, bregs + BMAC_LTCTR));
995 hme_write32(hp, bregs + BMAC_EXCTR, 0);
996 hme_write32(hp, bregs + BMAC_LTCTR, 0);
999 /* hp->happy_lock must be held */
1000 static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
1002 ASD(("happy_meal_poll_stop: "));
1004 /* If polling disabled or not polling already, nothing to do. */
1005 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
1006 (HFLAG_POLLENABLE | HFLAG_POLL)) {
1007 HMD(("not polling, return\n"));
1011 /* Shut up the MIF. */
1012 ASD(("were polling, mif ints off, "));
1013 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1015 /* Turn off polling. */
1016 ASD(("polling off, "));
1017 hme_write32(hp, tregs + TCVR_CFG,
1018 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
1020 /* We are no longer polling. */
1021 hp->happy_flags &= ~(HFLAG_POLL);
1023 /* Let the bits set. */
1028 /* Only Sun can take such nice parts and fuck up the programming interface
1029 * like this. Good job guys...
1031 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
1032 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1034 /* hp->happy_lock must be held */
1035 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
1038 int result, tries = TCVR_RESET_TRIES;
1040 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1041 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1042 if (hp->tcvr_type == external) {
1044 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1045 hp->tcvr_type = internal;
1046 hp->paddr = TCV_PADDR_ITX;
1048 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1049 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1050 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1051 if (result == TCVR_FAILURE) {
1052 ASD(("phyread_fail>\n"));
1055 ASD(("phyread_ok,PSELECT>"));
1056 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1057 hp->tcvr_type = external;
1058 hp->paddr = TCV_PADDR_ETX;
1060 if (tconfig & TCV_CFG_MDIO1) {
1061 ASD(("internal<PSELECT,"));
1062 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1064 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1065 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1066 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1067 if (result == TCVR_FAILURE) {
1068 ASD(("phyread_fail>\n"));
1071 ASD(("phyread_ok,~PSELECT>"));
1072 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1073 hp->tcvr_type = internal;
1074 hp->paddr = TCV_PADDR_ITX;
1078 ASD(("BMCR_RESET "));
1079 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1082 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1083 if (result == TCVR_FAILURE)
1085 hp->sw_bmcr = result;
1086 if (!(result & BMCR_RESET))
1091 ASD(("BMCR RESET FAILED!\n"));
1094 ASD(("RESET_OK\n"));
1096 /* Get fresh copies of the PHY registers. */
1097 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1098 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1099 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1100 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1103 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1104 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1106 tries = TCVR_UNISOLATE_TRIES;
1108 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1109 if (result == TCVR_FAILURE)
1111 if (!(result & BMCR_ISOLATE))
1116 ASD((" FAILED!\n"));
1119 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1120 if (!is_lucent_phy(hp)) {
1121 result = happy_meal_tcvr_read(hp, tregs,
1123 happy_meal_tcvr_write(hp, tregs,
1124 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1129 /* Figure out whether we have an internal or external transceiver.
1131 * hp->happy_lock must be held
1133 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1135 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1137 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1138 if (hp->happy_flags & HFLAG_POLL) {
1139 /* If we are polling, we must stop to get the transceiver type. */
1140 ASD(("<polling> "));
1141 if (hp->tcvr_type == internal) {
1142 if (tconfig & TCV_CFG_MDIO1) {
1143 ASD(("<internal> <poll stop> "));
1144 happy_meal_poll_stop(hp, tregs);
1145 hp->paddr = TCV_PADDR_ETX;
1146 hp->tcvr_type = external;
1147 ASD(("<external>\n"));
1148 tconfig &= ~(TCV_CFG_PENABLE);
1149 tconfig |= TCV_CFG_PSELECT;
1150 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1153 if (hp->tcvr_type == external) {
1154 ASD(("<external> "));
1155 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1156 ASD(("<poll stop> "));
1157 happy_meal_poll_stop(hp, tregs);
1158 hp->paddr = TCV_PADDR_ITX;
1159 hp->tcvr_type = internal;
1160 ASD(("<internal>\n"));
1161 hme_write32(hp, tregs + TCVR_CFG,
1162 hme_read32(hp, tregs + TCVR_CFG) &
1163 ~(TCV_CFG_PSELECT));
1171 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1173 /* Else we can just work off of the MDIO bits. */
1174 ASD(("<not polling> "));
1175 if (reread & TCV_CFG_MDIO1) {
1176 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1177 hp->paddr = TCV_PADDR_ETX;
1178 hp->tcvr_type = external;
1179 ASD(("<external>\n"));
1181 if (reread & TCV_CFG_MDIO0) {
1182 hme_write32(hp, tregs + TCVR_CFG,
1183 tconfig & ~(TCV_CFG_PSELECT));
1184 hp->paddr = TCV_PADDR_ITX;
1185 hp->tcvr_type = internal;
1186 ASD(("<internal>\n"));
1188 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1189 hp->tcvr_type = none; /* Grrr... */
1196 /* The receive ring buffers are a bit tricky to get right. Here goes...
1198 * The buffers we dma into must be 64 byte aligned. So we use a special
1199 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1202 * We use skb_reserve() to align the data block we get in the skb. We
1203 * also program the etxregs->cfg register to use an offset of 2. This
1204 * imperical constant plus the ethernet header size will always leave
1205 * us with a nicely aligned ip header once we pass things up to the
1208 * The numbers work out to:
1210 * Max ethernet frame size 1518
1211 * Ethernet header size 14
1212 * Happy Meal base offset 2
1214 * Say a skb data area is at 0xf001b010, and its size alloced is
1215 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1217 * First our alloc_skb() routine aligns the data base to a 64 byte
1218 * boundary. We now have 0xf001b040 as our skb data address. We
1219 * plug this into the receive descriptor address.
1221 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1222 * So now the data we will end up looking at starts at 0xf001b042. When
1223 * the packet arrives, we will check out the size received and subtract
1224 * this from the skb->length. Then we just pass the packet up to the
1225 * protocols as is, and allocate a new skb to replace this slot we have
1226 * just received from.
1228 * The ethernet layer will strip the ether header from the front of the
1229 * skb we just sent to it, this leaves us with the ip header sitting
1230 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1231 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1232 * bit checksum is obtained from the low bits of the receive descriptor
1235 * skb->csum = rxd->rx_flags & 0xffff;
1236 * skb->ip_summed = CHECKSUM_HW;
1238 * before sending off the skb to the protocols, and we are good as gold.
1240 static void happy_meal_clean_rings(struct happy_meal *hp)
1244 for (i = 0; i < RX_RING_SIZE; i++) {
1245 if (hp->rx_skbs[i] != NULL) {
1246 struct sk_buff *skb = hp->rx_skbs[i];
1247 struct happy_meal_rxd *rxd;
1250 rxd = &hp->happy_block->happy_meal_rxd[i];
1251 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1252 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1253 dev_kfree_skb_any(skb);
1254 hp->rx_skbs[i] = NULL;
1258 for (i = 0; i < TX_RING_SIZE; i++) {
1259 if (hp->tx_skbs[i] != NULL) {
1260 struct sk_buff *skb = hp->tx_skbs[i];
1261 struct happy_meal_txd *txd;
1265 hp->tx_skbs[i] = NULL;
1267 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1268 txd = &hp->happy_block->happy_meal_txd[i];
1269 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1270 hme_dma_unmap(hp, dma_addr,
1271 (hme_read_desc32(hp, &txd->tx_flags)
1275 if (frag != skb_shinfo(skb)->nr_frags)
1279 dev_kfree_skb_any(skb);
1284 /* hp->happy_lock must be held */
1285 static void happy_meal_init_rings(struct happy_meal *hp)
1287 struct hmeal_init_block *hb = hp->happy_block;
1288 struct net_device *dev = hp->dev;
1291 HMD(("happy_meal_init_rings: counters to zero, "));
1292 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1294 /* Free any skippy bufs left around in the rings. */
1296 happy_meal_clean_rings(hp);
1298 /* Now get new skippy bufs for the receive ring. */
1299 HMD(("init rxring, "));
1300 for (i = 0; i < RX_RING_SIZE; i++) {
1301 struct sk_buff *skb;
1303 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1305 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1308 hp->rx_skbs[i] = skb;
1311 /* Because we reserve afterwards. */
1312 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1313 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1314 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1315 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1316 skb_reserve(skb, RX_OFFSET);
1319 HMD(("init txring, "));
1320 for (i = 0; i < TX_RING_SIZE; i++)
1321 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1326 /* hp->happy_lock must be held */
1327 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1328 void __iomem *tregs,
1329 struct ethtool_cmd *ep)
1333 /* Read all of the registers we are interested in now. */
1334 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1335 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1336 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1337 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1339 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1341 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1342 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1343 /* Advertise everything we can support. */
1344 if (hp->sw_bmsr & BMSR_10HALF)
1345 hp->sw_advertise |= (ADVERTISE_10HALF);
1347 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1349 if (hp->sw_bmsr & BMSR_10FULL)
1350 hp->sw_advertise |= (ADVERTISE_10FULL);
1352 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1353 if (hp->sw_bmsr & BMSR_100HALF)
1354 hp->sw_advertise |= (ADVERTISE_100HALF);
1356 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1357 if (hp->sw_bmsr & BMSR_100FULL)
1358 hp->sw_advertise |= (ADVERTISE_100FULL);
1360 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1361 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1363 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1364 * XXX and this is because the DP83840 does not support it, changes
1365 * XXX would need to be made to the tx/rx logic in the driver as well
1366 * XXX so I completely skip checking for it in the BMSR for now.
1369 #ifdef AUTO_SWITCH_DEBUG
1370 ASD(("%s: Advertising [ ", hp->dev->name));
1371 if (hp->sw_advertise & ADVERTISE_10HALF)
1373 if (hp->sw_advertise & ADVERTISE_10FULL)
1375 if (hp->sw_advertise & ADVERTISE_100HALF)
1377 if (hp->sw_advertise & ADVERTISE_100FULL)
1381 /* Enable Auto-Negotiation, this is usually on already... */
1382 hp->sw_bmcr |= BMCR_ANENABLE;
1383 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1385 /* Restart it to make sure it is going. */
1386 hp->sw_bmcr |= BMCR_ANRESTART;
1387 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1389 /* BMCR_ANRESTART self clears when the process has begun. */
1391 timeout = 64; /* More than enough. */
1393 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1394 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1395 break; /* got it. */
1399 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1400 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1401 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1405 hp->timer_state = arbwait;
1409 /* Force the link up, trying first a particular mode.
1410 * Either we are here at the request of ethtool or
1411 * because the Happy Meal would not start to autoneg.
1414 /* Disable auto-negotiation in BMCR, enable the duplex and
1415 * speed setting, init the timer state machine, and fire it off.
1417 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1418 hp->sw_bmcr = BMCR_SPEED100;
1420 if (ep->speed == SPEED_100)
1421 hp->sw_bmcr = BMCR_SPEED100;
1424 if (ep->duplex == DUPLEX_FULL)
1425 hp->sw_bmcr |= BMCR_FULLDPLX;
1427 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1429 if (!is_lucent_phy(hp)) {
1430 /* OK, seems we need do disable the transceiver for the first
1431 * tick to make sure we get an accurate link state at the
1434 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1436 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1437 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1440 hp->timer_state = ltrywait;
1443 hp->timer_ticks = 0;
1444 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1445 hp->happy_timer.data = (unsigned long) hp;
1446 hp->happy_timer.function = &happy_meal_timer;
1447 add_timer(&hp->happy_timer);
1450 /* hp->happy_lock must be held */
1451 static int happy_meal_init(struct happy_meal *hp)
1453 void __iomem *gregs = hp->gregs;
1454 void __iomem *etxregs = hp->etxregs;
1455 void __iomem *erxregs = hp->erxregs;
1456 void __iomem *bregs = hp->bigmacregs;
1457 void __iomem *tregs = hp->tcvregs;
1459 unsigned char *e = &hp->dev->dev_addr[0];
1461 /* If auto-negotiation timer is running, kill it. */
1462 del_timer(&hp->happy_timer);
1464 HMD(("happy_meal_init: happy_flags[%08x] ",
1466 if (!(hp->happy_flags & HFLAG_INIT)) {
1467 HMD(("set HFLAG_INIT, "));
1468 hp->happy_flags |= HFLAG_INIT;
1469 happy_meal_get_counters(hp, bregs);
1473 HMD(("to happy_meal_poll_stop\n"));
1474 happy_meal_poll_stop(hp, tregs);
1476 /* Stop transmitter and receiver. */
1477 HMD(("happy_meal_init: to happy_meal_stop\n"));
1478 happy_meal_stop(hp, gregs);
1480 /* Alloc and reset the tx/rx descriptor chains. */
1481 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1482 happy_meal_init_rings(hp);
1484 /* Shut up the MIF. */
1485 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1486 hme_read32(hp, tregs + TCVR_IMASK)));
1487 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1489 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1490 if (hp->happy_flags & HFLAG_FENABLE) {
1491 HMD(("use frame old[%08x], ",
1492 hme_read32(hp, tregs + TCVR_CFG)));
1493 hme_write32(hp, tregs + TCVR_CFG,
1494 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1496 HMD(("use bitbang old[%08x], ",
1497 hme_read32(hp, tregs + TCVR_CFG)));
1498 hme_write32(hp, tregs + TCVR_CFG,
1499 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1502 /* Check the state of the transceiver. */
1503 HMD(("to happy_meal_transceiver_check\n"));
1504 happy_meal_transceiver_check(hp, tregs);
1506 /* Put the Big Mac into a sane state. */
1507 HMD(("happy_meal_init: "));
1508 switch(hp->tcvr_type) {
1510 /* Cannot operate if we don't know the transceiver type! */
1511 HMD(("AAIEEE no transceiver type, EAGAIN"));
1515 /* Using the MII buffers. */
1516 HMD(("internal, using MII, "));
1517 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1521 /* Not using the MII, disable it. */
1522 HMD(("external, disable MII, "));
1523 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1527 if (happy_meal_tcvr_reset(hp, tregs))
1530 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1531 HMD(("tx/rx reset, "));
1532 happy_meal_tx_reset(hp, bregs);
1533 happy_meal_rx_reset(hp, bregs);
1535 /* Set jam size and inter-packet gaps to reasonable defaults. */
1536 HMD(("jsize/ipg1/ipg2, "));
1537 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1538 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1539 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1541 /* Load up the MAC address and random seed. */
1542 HMD(("rseed/macaddr, "));
1544 /* The docs recommend to use the 10LSB of our MAC here. */
1545 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1547 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1548 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1549 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1552 if ((hp->dev->flags & IFF_ALLMULTI) ||
1553 (hp->dev->mc_count > 64)) {
1554 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1555 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1556 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1557 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1558 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1560 struct dev_mc_list *dmi = hp->dev->mc_list;
1565 for (i = 0; i < 4; i++)
1568 for (i = 0; i < hp->dev->mc_count; i++) {
1569 addrs = dmi->dmi_addr;
1575 crc = ether_crc_le(6, addrs);
1577 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1579 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1580 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1581 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1582 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1584 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1585 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1586 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1587 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1590 /* Set the RX and TX ring ptrs. */
1591 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1592 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1593 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1594 hme_write32(hp, erxregs + ERX_RING,
1595 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1596 hme_write32(hp, etxregs + ETX_RING,
1597 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1599 /* Parity issues in the ERX unit of some HME revisions can cause some
1600 * registers to not be written unless their parity is even. Detect such
1601 * lost writes and simply rewrite with a low bit set (which will be ignored
1602 * since the rxring needs to be 2K aligned).
1604 if (hme_read32(hp, erxregs + ERX_RING) !=
1605 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1606 hme_write32(hp, erxregs + ERX_RING,
1607 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1610 /* Set the supported burst sizes. */
1611 HMD(("happy_meal_init: old[%08x] bursts<",
1612 hme_read32(hp, gregs + GREG_CFG)));
1614 #ifndef CONFIG_SPARC
1615 /* It is always PCI and can handle 64byte bursts. */
1616 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1618 if ((hp->happy_bursts & DMA_BURST64) &&
1619 ((hp->happy_flags & HFLAG_PCI) != 0
1621 || sbus_can_burst64(hp->happy_dev)
1624 u32 gcfg = GREG_CFG_BURST64;
1626 /* I have no idea if I should set the extended
1627 * transfer mode bit for Cheerio, so for now I
1631 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1632 sbus_can_dma_64bit(hp->happy_dev)) {
1633 sbus_set_sbus64(hp->happy_dev,
1635 gcfg |= GREG_CFG_64BIT;
1640 hme_write32(hp, gregs + GREG_CFG, gcfg);
1641 } else if (hp->happy_bursts & DMA_BURST32) {
1643 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1644 } else if (hp->happy_bursts & DMA_BURST16) {
1646 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1649 hme_write32(hp, gregs + GREG_CFG, 0);
1651 #endif /* CONFIG_SPARC */
1653 /* Turn off interrupts we do not want to hear. */
1654 HMD((", enable global interrupts, "));
1655 hme_write32(hp, gregs + GREG_IMASK,
1656 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1657 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1659 /* Set the transmit ring buffer size. */
1660 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1661 hme_read32(hp, etxregs + ETX_RSIZE)));
1662 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1664 /* Enable transmitter DVMA. */
1665 HMD(("tx dma enable old[%08x], ",
1666 hme_read32(hp, etxregs + ETX_CFG)));
1667 hme_write32(hp, etxregs + ETX_CFG,
1668 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1670 /* This chip really rots, for the receiver sometimes when you
1671 * write to its control registers not all the bits get there
1672 * properly. I cannot think of a sane way to provide complete
1673 * coverage for this hardware bug yet.
1675 HMD(("erx regs bug old[%08x]\n",
1676 hme_read32(hp, erxregs + ERX_CFG)));
1677 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1678 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1679 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1680 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1681 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1682 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1683 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1684 /* XXX Should return failure here... */
1687 /* Enable Big Mac hash table filter. */
1688 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1689 hme_read32(hp, bregs + BMAC_RXCFG)));
1690 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1691 if (hp->dev->flags & IFF_PROMISC)
1692 rxcfg |= BIGMAC_RXCFG_PMISC;
1693 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1695 /* Let the bits settle in the chip. */
1698 /* Ok, configure the Big Mac transmitter. */
1699 HMD(("BIGMAC init, "));
1701 if (hp->happy_flags & HFLAG_FULL)
1702 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1704 /* Don't turn on the "don't give up" bit for now. It could cause hme
1705 * to deadlock with the PHY if a Jabber occurs.
1707 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1709 /* Give up after 16 TX attempts. */
1710 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1712 /* Enable the output drivers no matter what. */
1713 regtmp = BIGMAC_XCFG_ODENABLE;
1715 /* If card can do lance mode, enable it. */
1716 if (hp->happy_flags & HFLAG_LANCE)
1717 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1719 /* Disable the MII buffers if using external transceiver. */
1720 if (hp->tcvr_type == external)
1721 regtmp |= BIGMAC_XCFG_MIIDISAB;
1723 HMD(("XIF config old[%08x], ",
1724 hme_read32(hp, bregs + BMAC_XIFCFG)));
1725 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1727 /* Start things up. */
1728 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1729 hme_read32(hp, bregs + BMAC_TXCFG),
1730 hme_read32(hp, bregs + BMAC_RXCFG)));
1731 hme_write32(hp, bregs + BMAC_TXCFG,
1732 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1733 hme_write32(hp, bregs + BMAC_RXCFG,
1734 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1736 /* Get the autonegotiation started, and the watch timer ticking. */
1737 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1743 /* hp->happy_lock must be held */
1744 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1746 void __iomem *tregs = hp->tcvregs;
1747 void __iomem *bregs = hp->bigmacregs;
1748 void __iomem *gregs = hp->gregs;
1750 happy_meal_stop(hp, gregs);
1751 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1752 if (hp->happy_flags & HFLAG_FENABLE)
1753 hme_write32(hp, tregs + TCVR_CFG,
1754 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1756 hme_write32(hp, tregs + TCVR_CFG,
1757 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1758 happy_meal_transceiver_check(hp, tregs);
1759 switch(hp->tcvr_type) {
1763 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1766 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1769 if (happy_meal_tcvr_reset(hp, tregs))
1772 /* Latch PHY registers as of now. */
1773 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1774 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1776 /* Advertise everything we can support. */
1777 if (hp->sw_bmsr & BMSR_10HALF)
1778 hp->sw_advertise |= (ADVERTISE_10HALF);
1780 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1782 if (hp->sw_bmsr & BMSR_10FULL)
1783 hp->sw_advertise |= (ADVERTISE_10FULL);
1785 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1786 if (hp->sw_bmsr & BMSR_100HALF)
1787 hp->sw_advertise |= (ADVERTISE_100HALF);
1789 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1790 if (hp->sw_bmsr & BMSR_100FULL)
1791 hp->sw_advertise |= (ADVERTISE_100FULL);
1793 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1795 /* Update the PHY advertisement register. */
1796 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1799 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1800 * the hardware, so we cannot re-read it and get a correct value.
1802 * hp->happy_lock must be held
1804 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1808 /* Only print messages for non-counter related interrupts. */
1809 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1810 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1811 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1812 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1813 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1815 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1816 hp->dev->name, status);
1818 if (status & GREG_STAT_RFIFOVF) {
1819 /* Receive FIFO overflow is harmless and the hardware will take
1820 care of it, just some packets are lost. Who cares. */
1821 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1824 if (status & GREG_STAT_STSTERR) {
1825 /* BigMAC SQE link test failed. */
1826 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1830 if (status & GREG_STAT_TFIFO_UND) {
1831 /* Transmit FIFO underrun, again DMA error likely. */
1832 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1837 if (status & GREG_STAT_MAXPKTERR) {
1838 /* Driver error, tried to transmit something larger
1839 * than ethernet max mtu.
1841 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1845 if (status & GREG_STAT_NORXD) {
1846 /* This is harmless, it just means the system is
1847 * quite loaded and the incoming packet rate was
1848 * faster than the interrupt handler could keep up
1851 printk(KERN_INFO "%s: Happy Meal out of receive "
1852 "descriptors, packet dropped.\n",
1856 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1857 /* All sorts of DMA receive errors. */
1858 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1859 if (status & GREG_STAT_RXERR)
1860 printk("GenericError ");
1861 if (status & GREG_STAT_RXPERR)
1862 printk("ParityError ");
1863 if (status & GREG_STAT_RXTERR)
1864 printk("RxTagBotch ");
1869 if (status & GREG_STAT_EOPERR) {
1870 /* Driver bug, didn't set EOP bit in tx descriptor given
1871 * to the happy meal.
1873 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1878 if (status & GREG_STAT_MIFIRQ) {
1879 /* MIF signalled an interrupt, were we polling it? */
1880 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1884 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1885 /* All sorts of transmit DMA errors. */
1886 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1887 if (status & GREG_STAT_TXEACK)
1888 printk("GenericError ");
1889 if (status & GREG_STAT_TXLERR)
1890 printk("LateError ");
1891 if (status & GREG_STAT_TXPERR)
1892 printk("ParityErro ");
1893 if (status & GREG_STAT_TXTERR)
1894 printk("TagBotch ");
1899 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1900 /* Bus or parity error when cpu accessed happy meal registers
1901 * or it's internal FIFO's. Should never see this.
1903 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1905 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1910 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1911 happy_meal_init(hp);
1917 /* hp->happy_lock must be held */
1918 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1920 void __iomem *tregs = hp->tcvregs;
1922 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1923 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1924 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1926 /* Use the fastest transmission protocol possible. */
1927 if (hp->sw_lpa & LPA_100FULL) {
1928 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1929 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1930 } else if (hp->sw_lpa & LPA_100HALF) {
1931 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1932 hp->sw_bmcr |= BMCR_SPEED100;
1933 } else if (hp->sw_lpa & LPA_10FULL) {
1934 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1935 hp->sw_bmcr |= BMCR_FULLDPLX;
1937 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1939 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1941 /* Finally stop polling and shut up the MIF. */
1942 happy_meal_poll_stop(hp, tregs);
1946 #define TXD(x) printk x
1951 /* hp->happy_lock must be held */
1952 static void happy_meal_tx(struct happy_meal *hp)
1954 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1955 struct happy_meal_txd *this;
1956 struct net_device *dev = hp->dev;
1961 while (elem != hp->tx_new) {
1962 struct sk_buff *skb;
1963 u32 flags, dma_addr, dma_len;
1966 TXD(("[%d]", elem));
1967 this = &txbase[elem];
1968 flags = hme_read_desc32(hp, &this->tx_flags);
1969 if (flags & TXFLAG_OWN)
1971 skb = hp->tx_skbs[elem];
1972 if (skb_shinfo(skb)->nr_frags) {
1975 last = elem + skb_shinfo(skb)->nr_frags;
1976 last &= (TX_RING_SIZE - 1);
1977 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1978 if (flags & TXFLAG_OWN)
1981 hp->tx_skbs[elem] = NULL;
1982 hp->net_stats.tx_bytes += skb->len;
1984 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1985 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1986 dma_len = hme_read_desc32(hp, &this->tx_flags);
1988 dma_len &= TXFLAG_SIZE;
1989 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
1991 elem = NEXT_TX(elem);
1992 this = &txbase[elem];
1995 dev_kfree_skb_irq(skb);
1996 hp->net_stats.tx_packets++;
2001 if (netif_queue_stopped(dev) &&
2002 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
2003 netif_wake_queue(dev);
2007 #define RXD(x) printk x
2012 /* Originally I used to handle the allocation failure by just giving back just
2013 * that one ring buffer to the happy meal. Problem is that usually when that
2014 * condition is triggered, the happy meal expects you to do something reasonable
2015 * with all of the packets it has DMA'd in. So now I just drop the entire
2016 * ring when we cannot get a new skb and give them all back to the happy meal,
2017 * maybe things will be "happier" now.
2019 * hp->happy_lock must be held
2021 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
2023 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
2024 struct happy_meal_rxd *this;
2025 int elem = hp->rx_new, drops = 0;
2029 this = &rxbase[elem];
2030 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2031 struct sk_buff *skb;
2032 int len = flags >> 16;
2033 u16 csum = flags & RXFLAG_CSUM;
2034 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2036 RXD(("[%d ", elem));
2038 /* Check for errors. */
2039 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2040 RXD(("ERR(%08x)]", flags));
2041 hp->net_stats.rx_errors++;
2043 hp->net_stats.rx_length_errors++;
2044 if (len & (RXFLAG_OVERFLOW >> 16)) {
2045 hp->net_stats.rx_over_errors++;
2046 hp->net_stats.rx_fifo_errors++;
2049 /* Return it to the Happy meal. */
2051 hp->net_stats.rx_dropped++;
2052 hme_write_rxd(hp, this,
2053 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2057 skb = hp->rx_skbs[elem];
2058 if (len > RX_COPY_THRESHOLD) {
2059 struct sk_buff *new_skb;
2061 /* Now refill the entry, if we can. */
2062 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2063 if (new_skb == NULL) {
2067 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2068 hp->rx_skbs[elem] = new_skb;
2070 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2071 hme_write_rxd(hp, this,
2072 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2073 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2074 skb_reserve(new_skb, RX_OFFSET);
2076 /* Trim the original skb for the netif. */
2079 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2081 if (copy_skb == NULL) {
2086 copy_skb->dev = dev;
2087 skb_reserve(copy_skb, 2);
2088 skb_put(copy_skb, len);
2089 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE);
2090 memcpy(copy_skb->data, skb->data, len);
2091 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE);
2093 /* Reuse original ring buffer. */
2094 hme_write_rxd(hp, this,
2095 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2101 /* This card is _fucking_ hot... */
2102 skb->csum = ntohs(csum ^ 0xffff);
2103 skb->ip_summed = CHECKSUM_HW;
2105 RXD(("len=%d csum=%4x]", len, csum));
2106 skb->protocol = eth_type_trans(skb, dev);
2109 dev->last_rx = jiffies;
2110 hp->net_stats.rx_packets++;
2111 hp->net_stats.rx_bytes += len;
2113 elem = NEXT_RX(elem);
2114 this = &rxbase[elem];
2118 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2122 static irqreturn_t happy_meal_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2124 struct net_device *dev = (struct net_device *) dev_id;
2125 struct happy_meal *hp = dev->priv;
2126 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2128 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2130 spin_lock(&hp->happy_lock);
2132 if (happy_status & GREG_STAT_ERRORS) {
2134 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2138 if (happy_status & GREG_STAT_MIFIRQ) {
2140 happy_meal_mif_interrupt(hp);
2143 if (happy_status & GREG_STAT_TXALL) {
2148 if (happy_status & GREG_STAT_RXTOHOST) {
2150 happy_meal_rx(hp, dev);
2155 spin_unlock(&hp->happy_lock);
2161 static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie, struct pt_regs *ptregs)
2163 struct quattro *qp = (struct quattro *) cookie;
2166 for (i = 0; i < 4; i++) {
2167 struct net_device *dev = qp->happy_meals[i];
2168 struct happy_meal *hp = dev->priv;
2169 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2171 HMD(("quattro_interrupt: status=%08x ", happy_status));
2173 if (!(happy_status & (GREG_STAT_ERRORS |
2176 GREG_STAT_RXTOHOST)))
2179 spin_lock(&hp->happy_lock);
2181 if (happy_status & GREG_STAT_ERRORS) {
2183 if (happy_meal_is_not_so_happy(hp, happy_status))
2187 if (happy_status & GREG_STAT_MIFIRQ) {
2189 happy_meal_mif_interrupt(hp);
2192 if (happy_status & GREG_STAT_TXALL) {
2197 if (happy_status & GREG_STAT_RXTOHOST) {
2199 happy_meal_rx(hp, dev);
2203 spin_unlock(&hp->happy_lock);
2211 static int happy_meal_open(struct net_device *dev)
2213 struct happy_meal *hp = dev->priv;
2216 HMD(("happy_meal_open: "));
2218 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2219 * into a single source which we register handling at probe time.
2221 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2222 if (request_irq(dev->irq, &happy_meal_interrupt,
2223 SA_SHIRQ, dev->name, (void *)dev)) {
2225 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2232 HMD(("to happy_meal_init\n"));
2234 spin_lock_irq(&hp->happy_lock);
2235 res = happy_meal_init(hp);
2236 spin_unlock_irq(&hp->happy_lock);
2238 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2239 free_irq(dev->irq, dev);
2243 static int happy_meal_close(struct net_device *dev)
2245 struct happy_meal *hp = dev->priv;
2247 spin_lock_irq(&hp->happy_lock);
2248 happy_meal_stop(hp, hp->gregs);
2249 happy_meal_clean_rings(hp);
2251 /* If auto-negotiation timer is running, kill it. */
2252 del_timer(&hp->happy_timer);
2254 spin_unlock_irq(&hp->happy_lock);
2256 /* On Quattro QFE cards, all hme interrupts are concentrated
2257 * into a single source which we register handling at probe
2258 * time and never unregister.
2260 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2261 free_irq(dev->irq, dev);
2267 #define SXD(x) printk x
2272 static void happy_meal_tx_timeout(struct net_device *dev)
2274 struct happy_meal *hp = dev->priv;
2276 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2278 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2279 hme_read32(hp, hp->gregs + GREG_STAT),
2280 hme_read32(hp, hp->etxregs + ETX_CFG),
2281 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2283 spin_lock_irq(&hp->happy_lock);
2284 happy_meal_init(hp);
2285 spin_unlock_irq(&hp->happy_lock);
2287 netif_wake_queue(dev);
2290 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2292 struct happy_meal *hp = dev->priv;
2296 tx_flags = TXFLAG_OWN;
2297 if (skb->ip_summed == CHECKSUM_HW) {
2298 u32 csum_start_off, csum_stuff_off;
2300 csum_start_off = (u32) (skb->h.raw - skb->data);
2301 csum_stuff_off = (u32) ((skb->h.raw + skb->csum) - skb->data);
2303 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2304 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2305 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2308 spin_lock_irq(&hp->happy_lock);
2310 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2311 netif_stop_queue(dev);
2312 spin_unlock_irq(&hp->happy_lock);
2313 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2319 SXD(("SX<l[%d]e[%d]>", len, entry));
2320 hp->tx_skbs[entry] = skb;
2322 if (skb_shinfo(skb)->nr_frags == 0) {
2326 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2327 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2328 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2329 (tx_flags | (len & TXFLAG_SIZE)),
2331 entry = NEXT_TX(entry);
2333 u32 first_len, first_mapping;
2334 int frag, first_entry = entry;
2336 /* We must give this initial chunk to the device last.
2337 * Otherwise we could race with the device.
2339 first_len = skb_headlen(skb);
2340 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2341 entry = NEXT_TX(entry);
2343 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2344 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2345 u32 len, mapping, this_txflags;
2347 len = this_frag->size;
2348 mapping = hme_dma_map(hp,
2349 ((void *) page_address(this_frag->page) +
2350 this_frag->page_offset),
2352 this_txflags = tx_flags;
2353 if (frag == skb_shinfo(skb)->nr_frags - 1)
2354 this_txflags |= TXFLAG_EOP;
2355 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2356 (this_txflags | (len & TXFLAG_SIZE)),
2358 entry = NEXT_TX(entry);
2360 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2361 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2367 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2368 netif_stop_queue(dev);
2371 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2373 spin_unlock_irq(&hp->happy_lock);
2375 dev->trans_start = jiffies;
2377 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2381 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2383 struct happy_meal *hp = dev->priv;
2385 spin_lock_irq(&hp->happy_lock);
2386 happy_meal_get_counters(hp, hp->bigmacregs);
2387 spin_unlock_irq(&hp->happy_lock);
2389 return &hp->net_stats;
2392 static void happy_meal_set_multicast(struct net_device *dev)
2394 struct happy_meal *hp = dev->priv;
2395 void __iomem *bregs = hp->bigmacregs;
2396 struct dev_mc_list *dmi = dev->mc_list;
2401 spin_lock_irq(&hp->happy_lock);
2403 netif_stop_queue(dev);
2405 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2406 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2407 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2408 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2409 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2410 } else if (dev->flags & IFF_PROMISC) {
2411 hme_write32(hp, bregs + BMAC_RXCFG,
2412 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2416 for (i = 0; i < 4; i++)
2419 for (i = 0; i < dev->mc_count; i++) {
2420 addrs = dmi->dmi_addr;
2426 crc = ether_crc_le(6, addrs);
2428 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2430 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2431 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2432 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2433 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2436 netif_wake_queue(dev);
2438 spin_unlock_irq(&hp->happy_lock);
2441 /* Ethtool support... */
2442 static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2444 struct happy_meal *hp = dev->priv;
2447 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2448 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2449 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2451 /* XXX hardcoded stuff for now */
2452 cmd->port = PORT_TP; /* XXX no MII support */
2453 cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2454 cmd->phy_address = 0; /* XXX fixed PHYAD */
2456 /* Record PHY settings. */
2457 spin_lock_irq(&hp->happy_lock);
2458 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2459 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2460 spin_unlock_irq(&hp->happy_lock);
2462 if (hp->sw_bmcr & BMCR_ANENABLE) {
2463 cmd->autoneg = AUTONEG_ENABLE;
2465 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2466 SPEED_100 : SPEED_10;
2467 if (cmd->speed == SPEED_100)
2469 (hp->sw_lpa & (LPA_100FULL)) ?
2470 DUPLEX_FULL : DUPLEX_HALF;
2473 (hp->sw_lpa & (LPA_10FULL)) ?
2474 DUPLEX_FULL : DUPLEX_HALF;
2476 cmd->autoneg = AUTONEG_DISABLE;
2478 (hp->sw_bmcr & BMCR_SPEED100) ?
2479 SPEED_100 : SPEED_10;
2481 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2482 DUPLEX_FULL : DUPLEX_HALF;
2487 static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2489 struct happy_meal *hp = dev->priv;
2491 /* Verify the settings we care about. */
2492 if (cmd->autoneg != AUTONEG_ENABLE &&
2493 cmd->autoneg != AUTONEG_DISABLE)
2495 if (cmd->autoneg == AUTONEG_DISABLE &&
2496 ((cmd->speed != SPEED_100 &&
2497 cmd->speed != SPEED_10) ||
2498 (cmd->duplex != DUPLEX_HALF &&
2499 cmd->duplex != DUPLEX_FULL)))
2502 /* Ok, do it to it. */
2503 spin_lock_irq(&hp->happy_lock);
2504 del_timer(&hp->happy_timer);
2505 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2506 spin_unlock_irq(&hp->happy_lock);
2511 static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2513 struct happy_meal *hp = dev->priv;
2515 strcpy(info->driver, "sunhme");
2516 strcpy(info->version, "2.02");
2517 if (hp->happy_flags & HFLAG_PCI) {
2518 struct pci_dev *pdev = hp->happy_dev;
2519 strcpy(info->bus_info, pci_name(pdev));
2523 struct sbus_dev *sdev = hp->happy_dev;
2524 sprintf(info->bus_info, "SBUS:%d",
2530 static u32 hme_get_link(struct net_device *dev)
2532 struct happy_meal *hp = dev->priv;
2534 spin_lock_irq(&hp->happy_lock);
2535 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2536 spin_unlock_irq(&hp->happy_lock);
2538 return (hp->sw_bmsr & BMSR_LSTATUS);
2541 static struct ethtool_ops hme_ethtool_ops = {
2542 .get_settings = hme_get_settings,
2543 .set_settings = hme_set_settings,
2544 .get_drvinfo = hme_get_drvinfo,
2545 .get_link = hme_get_link,
2548 static int hme_version_printed;
2551 void __init quattro_get_ranges(struct quattro *qp)
2553 struct sbus_dev *sdev = qp->quattro_dev;
2556 err = prom_getproperty(sdev->prom_node,
2558 (char *)&qp->ranges[0],
2559 sizeof(qp->ranges));
2560 if (err == 0 || err == -1) {
2564 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2567 static void __init quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2569 struct sbus_dev *sdev = hp->happy_dev;
2572 for (rng = 0; rng < qp->nranges; rng++) {
2573 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2576 for (reg = 0; reg < 5; reg++) {
2577 if (sdev->reg_addrs[reg].which_io ==
2578 rngp->ot_child_space)
2584 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2585 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2589 /* Given a happy meal sbus device, find it's quattro parent.
2590 * If none exist, allocate and return a new one.
2592 * Return NULL on failure.
2594 static struct quattro * __init quattro_sbus_find(struct sbus_dev *goal_sdev)
2596 struct sbus_bus *sbus;
2597 struct sbus_dev *sdev;
2601 if (qfe_sbus_list == NULL)
2604 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2605 for (i = 0, sdev = qp->quattro_dev;
2606 (sdev != NULL) && (i < 4);
2607 sdev = sdev->next, i++) {
2608 if (sdev == goal_sdev)
2612 for_each_sbus(sbus) {
2613 for_each_sbusdev(sdev, sbus) {
2614 if (sdev == goal_sdev)
2619 /* Cannot find quattro parent, fail. */
2623 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2627 for (i = 0; i < 4; i++)
2628 qp->happy_meals[i] = NULL;
2630 qp->quattro_dev = goal_sdev;
2631 qp->next = qfe_sbus_list;
2633 quattro_get_ranges(qp);
2638 /* After all quattro cards have been probed, we call these functions
2639 * to register the IRQ handlers.
2641 static void __init quattro_sbus_register_irqs(void)
2645 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2646 struct sbus_dev *sdev = qp->quattro_dev;
2649 err = request_irq(sdev->irqs[0],
2650 quattro_sbus_interrupt,
2651 SA_SHIRQ, "Quattro",
2654 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2655 panic("QFE request irq");
2659 #endif /* CONFIG_SBUS */
2662 static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2664 struct pci_dev *bdev = pdev->bus->self;
2667 if (!bdev) return NULL;
2668 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2669 struct pci_dev *qpdev = qp->quattro_dev;
2674 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2678 for (i = 0; i < 4; i++)
2679 qp->happy_meals[i] = NULL;
2681 qp->quattro_dev = bdev;
2682 qp->next = qfe_pci_list;
2685 /* No range tricks necessary on PCI. */
2690 #endif /* CONFIG_PCI */
2693 static int __init happy_meal_sbus_init(struct sbus_dev *sdev, int is_qfe)
2695 struct quattro *qp = NULL;
2696 struct happy_meal *hp;
2697 struct net_device *dev;
2698 int i, qfe_slot = -1;
2702 qp = quattro_sbus_find(sdev);
2705 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2706 if (qp->happy_meals[qfe_slot] == NULL)
2713 dev = alloc_etherdev(sizeof(struct happy_meal));
2716 SET_MODULE_OWNER(dev);
2718 if (hme_version_printed++ == 0)
2719 printk(KERN_INFO "%s", version);
2721 /* If user did not specify a MAC address specifically, use
2722 * the Quattro local-mac-address property...
2724 for (i = 0; i < 6; i++) {
2725 if (macaddr[i] != 0)
2728 if (i < 6) { /* a mac address was given */
2729 for (i = 0; i < 6; i++)
2730 dev->dev_addr[i] = macaddr[i];
2732 } else if (qfe_slot != -1 &&
2733 prom_getproplen(sdev->prom_node,
2734 "local-mac-address") == 6) {
2735 prom_getproperty(sdev->prom_node, "local-mac-address",
2738 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2743 hp->happy_dev = sdev;
2745 spin_lock_init(&hp->happy_lock);
2748 if (sdev->num_registers != 5) {
2749 printk(KERN_ERR "happymeal: Device does not have 5 regs, it has %d.\n",
2750 sdev->num_registers);
2751 printk(KERN_ERR "happymeal: Would you like that for here or to go?\n");
2752 goto err_out_free_netdev;
2756 hp->qfe_parent = qp;
2757 hp->qfe_ent = qfe_slot;
2758 qp->happy_meals[qfe_slot] = dev;
2759 quattro_apply_ranges(qp, hp);
2762 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2763 GREG_REG_SIZE, "HME Global Regs");
2765 printk(KERN_ERR "happymeal: Cannot map Happy Meal global registers.\n");
2766 goto err_out_free_netdev;
2769 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2770 ETX_REG_SIZE, "HME TX Regs");
2772 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Transmit registers.\n");
2773 goto err_out_iounmap;
2776 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2777 ERX_REG_SIZE, "HME RX Regs");
2779 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Receive registers.\n");
2780 goto err_out_iounmap;
2783 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2784 BMAC_REG_SIZE, "HME BIGMAC Regs");
2785 if (!hp->bigmacregs) {
2786 printk(KERN_ERR "happymeal: Cannot map Happy Meal BIGMAC registers.\n");
2787 goto err_out_iounmap;
2790 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2791 TCVR_REG_SIZE, "HME Tranceiver Regs");
2793 printk(KERN_ERR "happymeal: Cannot map Happy Meal Tranceiver registers.\n");
2794 goto err_out_iounmap;
2797 hp->hm_revision = prom_getintdefault(sdev->prom_node, "hm-rev", 0xff);
2798 if (hp->hm_revision == 0xff)
2799 hp->hm_revision = 0xa0;
2801 /* Now enable the feature flags we can. */
2802 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2803 hp->happy_flags = HFLAG_20_21;
2804 else if (hp->hm_revision != 0xa0)
2805 hp->happy_flags = HFLAG_NOT_A0;
2808 hp->happy_flags |= HFLAG_QUATTRO;
2810 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2811 hp->happy_bursts = prom_getintdefault(sdev->bus->prom_node,
2812 "burst-sizes", 0x00);
2814 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2818 if (!hp->happy_block) {
2819 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2820 goto err_out_iounmap;
2823 /* Force check of the link first time we are brought up. */
2826 /* Force timer state to 'asleep' with count of zero. */
2827 hp->timer_state = asleep;
2828 hp->timer_ticks = 0;
2830 init_timer(&hp->happy_timer);
2833 dev->open = &happy_meal_open;
2834 dev->stop = &happy_meal_close;
2835 dev->hard_start_xmit = &happy_meal_start_xmit;
2836 dev->get_stats = &happy_meal_get_stats;
2837 dev->set_multicast_list = &happy_meal_set_multicast;
2838 dev->tx_timeout = &happy_meal_tx_timeout;
2839 dev->watchdog_timeo = 5*HZ;
2840 dev->ethtool_ops = &hme_ethtool_ops;
2842 /* Happy Meal can do it all... except VLAN. */
2843 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_VLAN_CHALLENGED;
2845 dev->irq = sdev->irqs[0];
2847 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2848 /* Hook up PCI register/dma accessors. */
2849 hp->read_desc32 = sbus_hme_read_desc32;
2850 hp->write_txd = sbus_hme_write_txd;
2851 hp->write_rxd = sbus_hme_write_rxd;
2852 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2853 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2854 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
2855 sbus_dma_sync_single_for_cpu;
2856 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
2857 sbus_dma_sync_single_for_device;
2858 hp->read32 = sbus_hme_read32;
2859 hp->write32 = sbus_hme_write32;
2862 /* Grrr, Happy Meal comes up by default not advertising
2863 * full duplex 100baseT capabilities, fix this.
2865 spin_lock_irq(&hp->happy_lock);
2866 happy_meal_set_initial_advertisement(hp);
2867 spin_unlock_irq(&hp->happy_lock);
2869 if (register_netdev(hp->dev)) {
2870 printk(KERN_ERR "happymeal: Cannot register net device, "
2872 goto err_out_free_consistent;
2876 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2877 dev->name, qfe_slot);
2879 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2882 for (i = 0; i < 6; i++)
2884 dev->dev_addr[i], i == 5 ? ' ' : ':');
2887 /* We are home free at this point, link us in to the happy
2890 hp->next_module = root_happy_dev;
2891 root_happy_dev = hp;
2895 err_out_free_consistent:
2896 sbus_free_consistent(hp->happy_dev,
2903 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2905 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2907 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2909 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2911 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2913 err_out_free_netdev:
2922 #ifndef CONFIG_SPARC
2923 static int is_quattro_p(struct pci_dev *pdev)
2925 struct pci_dev *busdev = pdev->bus->self;
2926 struct list_head *tmp;
2929 if (busdev == NULL ||
2930 busdev->vendor != PCI_VENDOR_ID_DEC ||
2931 busdev->device != PCI_DEVICE_ID_DEC_21153)
2935 tmp = pdev->bus->devices.next;
2936 while (tmp != &pdev->bus->devices) {
2937 struct pci_dev *this_pdev = pci_dev_b(tmp);
2939 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2940 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2952 /* Fetch MAC address from vital product data of PCI ROM. */
2953 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2957 for (this_offset = 0x20; this_offset < len; this_offset++) {
2958 void __iomem *p = rom_base + this_offset;
2960 if (readb(p + 0) != 0x90 ||
2961 readb(p + 1) != 0x00 ||
2962 readb(p + 2) != 0x09 ||
2963 readb(p + 3) != 0x4e ||
2964 readb(p + 4) != 0x41 ||
2965 readb(p + 5) != 0x06)
2974 for (i = 0; i < 6; i++)
2975 dev_addr[i] = readb(p + i);
2983 static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2986 void __iomem *p = pci_map_rom(pdev, &size);
2992 if (is_quattro_p(pdev))
2993 index = PCI_SLOT(pdev->devfn);
2995 found = readb(p) == 0x55 &&
2996 readb(p + 1) == 0xaa &&
2997 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2998 pci_unmap_rom(pdev, p);
3003 /* Sun MAC prefix then 3 random bytes. */
3007 get_random_bytes(&dev_addr[3], 3);
3010 #endif /* !(CONFIG_SPARC) */
3012 static int __init happy_meal_pci_init(struct pci_dev *pdev)
3014 struct quattro *qp = NULL;
3016 struct pcidev_cookie *pcp;
3018 struct happy_meal *hp;
3019 struct net_device *dev;
3020 void __iomem *hpreg_base;
3021 unsigned long hpreg_res;
3022 int i, qfe_slot = -1;
3026 /* Now make sure pci_dev cookie is there. */
3028 pcp = pdev->sysdata;
3030 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
3034 strcpy(prom_name, pcp->prom_node->name);
3036 if (is_quattro_p(pdev))
3037 strcpy(prom_name, "SUNW,qfe");
3039 strcpy(prom_name, "SUNW,hme");
3043 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
3044 qp = quattro_pci_find(pdev);
3047 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3048 if (qp->happy_meals[qfe_slot] == NULL)
3054 dev = alloc_etherdev(sizeof(struct happy_meal));
3058 SET_MODULE_OWNER(dev);
3059 SET_NETDEV_DEV(dev, &pdev->dev);
3061 if (hme_version_printed++ == 0)
3062 printk(KERN_INFO "%s", version);
3064 dev->base_addr = (long) pdev;
3066 hp = (struct happy_meal *)dev->priv;
3067 memset(hp, 0, sizeof(*hp));
3069 hp->happy_dev = pdev;
3071 spin_lock_init(&hp->happy_lock);
3074 hp->qfe_parent = qp;
3075 hp->qfe_ent = qfe_slot;
3076 qp->happy_meals[qfe_slot] = dev;
3079 hpreg_res = pci_resource_start(pdev, 0);
3081 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3082 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3083 goto err_out_clear_quattro;
3085 if (pci_request_regions(pdev, DRV_NAME)) {
3086 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3088 goto err_out_clear_quattro;
3091 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) {
3092 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3093 goto err_out_free_res;
3096 for (i = 0; i < 6; i++) {
3097 if (macaddr[i] != 0)
3100 if (i < 6) { /* a mac address was given */
3101 for (i = 0; i < 6; i++)
3102 dev->dev_addr[i] = macaddr[i];
3106 unsigned char *addr;
3109 if (qfe_slot != -1 &&
3110 (addr = of_get_property(pcp->prom_node,
3111 "local-mac-address", &len)) != NULL
3113 memcpy(dev->dev_addr, addr, 6);
3115 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3118 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3122 /* Layout registers. */
3123 hp->gregs = (hpreg_base + 0x0000UL);
3124 hp->etxregs = (hpreg_base + 0x2000UL);
3125 hp->erxregs = (hpreg_base + 0x4000UL);
3126 hp->bigmacregs = (hpreg_base + 0x6000UL);
3127 hp->tcvregs = (hpreg_base + 0x7000UL);
3130 hp->hm_revision = of_getintprop_default(pcp->prom_node, "hm-rev", 0xff);
3131 if (hp->hm_revision == 0xff) {
3134 pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
3135 hp->hm_revision = 0xc0 | (prev & 0x0f);
3138 /* works with this on non-sparc hosts */
3139 hp->hm_revision = 0x20;
3142 /* Now enable the feature flags we can. */
3143 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3144 hp->happy_flags = HFLAG_20_21;
3145 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3146 hp->happy_flags = HFLAG_NOT_A0;
3149 hp->happy_flags |= HFLAG_QUATTRO;
3151 /* And of course, indicate this is PCI. */
3152 hp->happy_flags |= HFLAG_PCI;
3155 /* Assume PCI happy meals can handle all burst sizes. */
3156 hp->happy_bursts = DMA_BURSTBITS;
3159 hp->happy_block = (struct hmeal_init_block *)
3160 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3163 if (!hp->happy_block) {
3164 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3165 goto err_out_iounmap;
3169 hp->timer_state = asleep;
3170 hp->timer_ticks = 0;
3172 init_timer(&hp->happy_timer);
3175 dev->open = &happy_meal_open;
3176 dev->stop = &happy_meal_close;
3177 dev->hard_start_xmit = &happy_meal_start_xmit;
3178 dev->get_stats = &happy_meal_get_stats;
3179 dev->set_multicast_list = &happy_meal_set_multicast;
3180 dev->tx_timeout = &happy_meal_tx_timeout;
3181 dev->watchdog_timeo = 5*HZ;
3182 dev->ethtool_ops = &hme_ethtool_ops;
3183 dev->irq = pdev->irq;
3186 /* Happy Meal can do it all... */
3187 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3189 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3190 /* Hook up PCI register/dma accessors. */
3191 hp->read_desc32 = pci_hme_read_desc32;
3192 hp->write_txd = pci_hme_write_txd;
3193 hp->write_rxd = pci_hme_write_rxd;
3194 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3195 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3196 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
3197 pci_dma_sync_single_for_cpu;
3198 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
3199 pci_dma_sync_single_for_device;
3200 hp->read32 = pci_hme_read32;
3201 hp->write32 = pci_hme_write32;
3204 /* Grrr, Happy Meal comes up by default not advertising
3205 * full duplex 100baseT capabilities, fix this.
3207 spin_lock_irq(&hp->happy_lock);
3208 happy_meal_set_initial_advertisement(hp);
3209 spin_unlock_irq(&hp->happy_lock);
3211 if (register_netdev(hp->dev)) {
3212 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3214 goto err_out_iounmap;
3218 struct pci_dev *qpdev = qp->quattro_dev;
3221 if (!strncmp(dev->name, "eth", 3)) {
3222 int i = simple_strtoul(dev->name + 3, NULL, 10);
3223 sprintf(prom_name, "-%d", i + 3);
3225 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3226 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3227 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3228 printk("DEC 21153 PCI Bridge\n");
3230 printk("unknown bridge %04x.%04x\n",
3231 qpdev->vendor, qpdev->device);
3235 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3236 dev->name, qfe_slot);
3238 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3241 for (i = 0; i < 6; i++)
3242 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
3246 /* We are home free at this point, link us in to the happy
3249 hp->next_module = root_happy_dev;
3250 root_happy_dev = hp;
3258 pci_release_regions(pdev);
3260 err_out_clear_quattro:
3262 qp->happy_meals[qfe_slot] = NULL;
3272 static int __init happy_meal_sbus_probe(void)
3274 struct sbus_bus *sbus;
3275 struct sbus_dev *sdev;
3279 for_each_sbus(sbus) {
3280 for_each_sbusdev(sdev, sbus) {
3281 char *name = sdev->prom_name;
3283 if (!strcmp(name, "SUNW,hme")) {
3285 prom_getstring(sdev->prom_node, "model",
3286 model, sizeof(model));
3287 if (!strcmp(model, "SUNW,sbus-qfe"))
3288 happy_meal_sbus_init(sdev, 1);
3290 happy_meal_sbus_init(sdev, 0);
3291 } else if (!strcmp(name, "qfe") ||
3292 !strcmp(name, "SUNW,qfe")) {
3294 happy_meal_sbus_init(sdev, 1);
3299 quattro_sbus_register_irqs();
3305 static int __init happy_meal_pci_probe(void)
3307 struct pci_dev *pdev = NULL;
3310 while ((pdev = pci_find_device(PCI_VENDOR_ID_SUN,
3311 PCI_DEVICE_ID_SUN_HAPPYMEAL, pdev)) != NULL) {
3312 if (pci_enable_device(pdev))
3314 pci_set_master(pdev);
3316 happy_meal_pci_init(pdev);
3322 static int __init happy_meal_probe(void)
3324 static int called = 0;
3327 root_happy_dev = NULL;
3335 cards += happy_meal_sbus_probe();
3338 cards += happy_meal_pci_probe();
3346 static void __exit happy_meal_cleanup_module(void)
3349 struct quattro *last_seen_qfe = NULL;
3352 while (root_happy_dev) {
3353 struct happy_meal *hp = root_happy_dev;
3354 struct happy_meal *next = root_happy_dev->next_module;
3355 struct net_device *dev = hp->dev;
3357 /* Unregister netdev before unmapping registers as this
3358 * call can end up trying to access those registers.
3360 unregister_netdev(dev);
3363 if (!(hp->happy_flags & HFLAG_PCI)) {
3364 if (hp->happy_flags & HFLAG_QUATTRO) {
3365 if (hp->qfe_parent != last_seen_qfe) {
3366 free_irq(dev->irq, hp->qfe_parent);
3367 last_seen_qfe = hp->qfe_parent;
3371 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3372 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3373 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3374 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3375 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3376 sbus_free_consistent(hp->happy_dev,
3383 if ((hp->happy_flags & HFLAG_PCI)) {
3384 pci_free_consistent(hp->happy_dev,
3389 pci_release_regions(hp->happy_dev);
3394 root_happy_dev = next;
3397 /* Now cleanup the quattro lists. */
3399 while (qfe_sbus_list) {
3400 struct quattro *qfe = qfe_sbus_list;
3401 struct quattro *next = qfe->next;
3405 qfe_sbus_list = next;
3409 while (qfe_pci_list) {
3410 struct quattro *qfe = qfe_pci_list;
3411 struct quattro *next = qfe->next;
3415 qfe_pci_list = next;
3420 module_init(happy_meal_probe);
3421 module_exit(happy_meal_cleanup_module);