2 * Copyright 2007, 2010 Freescale Semiconductor, Inc.
4 * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
7 * ULI 526x Ethernet port driver.
8 * Based on the Linux driver: drivers/net/tulip/uli526x.c
10 * SPDX-License-Identifier: GPL-2.0+
21 /* some kernel function compatible define */
25 /* Board/System/Debug information/definition */
26 #define ULI_VENDOR_ID 0x10B9
27 #define ULI5261_DEVICE_ID 0x5261
28 #define ULI5263_DEVICE_ID 0x5263
30 #define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
32 #define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
34 #define ULI526X_IO_SIZE 0x100
35 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
36 #define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
37 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
38 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
39 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
40 #define TX_BUF_ALLOC 0x300
41 #define RX_ALLOC_SIZE PKTSIZE
42 #define ULI526X_RESET 1
44 #define CR6_DEFAULT 0x22200000
45 #define CR7_DEFAULT 0x180c1
46 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
47 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
48 #define MAX_PACKET_SIZE 1514
49 #define ULI5261_MAX_MULTICAST 14
50 #define RX_COPY_SIZE 100
51 #define MAX_CHECK_PACKET 0x8000
53 #define ULI526X_10MHF 0
54 #define ULI526X_100MHF 1
55 #define ULI526X_10MFD 4
56 #define ULI526X_100MFD 5
57 #define ULI526X_AUTO 8
59 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
60 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
61 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
62 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
63 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
64 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
66 /* CR9 definition: SROM/MII */
67 #define CR9_SROM_READ 0x4800
70 #define CR9_CRDOUT 0x8
71 #define SROM_DATA_0 0x0
72 #define SROM_DATA_1 0x4
73 #define PHY_DATA_1 0x20000
74 #define PHY_DATA_0 0x00000
75 #define MDCLKH 0x10000
77 #define PHY_POWER_DOWN 0x800
79 #define SROM_V41_CODE 0x14
81 #define SROM_CLK_WRITE(data, ioaddr) do { \
82 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
84 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
86 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
90 /* Structure/enum declaration */
93 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
94 char *tx_buf_ptr; /* Data for us */
95 struct tx_desc *next_tx_desc;
99 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
100 char *rx_buf_ptr; /* Data for us */
101 struct rx_desc *next_rx_desc;
104 struct uli526x_board_info {
105 u32 chip_id; /* Chip vendor/Device ID */
108 long ioaddr; /* I/O base address */
115 /* pointer for memory physical address */
116 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
117 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
118 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
119 dma_addr_t first_tx_desc_dma;
120 dma_addr_t first_rx_desc_dma;
122 /* descriptor pointer */
123 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
124 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
125 unsigned char *desc_pool_ptr; /* descriptor pool memory */
126 struct tx_desc *first_tx_desc;
127 struct tx_desc *tx_insert_ptr;
128 struct tx_desc *tx_remove_ptr;
129 struct rx_desc *first_rx_desc;
130 struct rx_desc *rx_ready_ptr; /* packet come pointer */
131 unsigned long tx_packet_cnt; /* transmitted packet count */
133 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
135 u8 media_mode; /* user specify media mode */
136 u8 op_mode; /* real work dedia mode */
140 unsigned char srom[128];
143 enum uli526x_offsets {
144 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
145 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
146 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
150 enum uli526x_CR6_bits {
151 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
152 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
153 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
156 /* Global variable declaration -- */
158 static unsigned char uli526x_media_mode = ULI526X_AUTO;
160 static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
161 __attribute__ ((aligned(32)));
162 static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
164 /* For module input parameter */
167 /* function declaration -- */
168 static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length);
169 static const struct ethtool_ops netdev_ethtool_ops;
170 static u16 read_srom_word(long, int);
171 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
172 static void allocate_rx_buffer(struct uli526x_board_info *);
173 static void update_cr6(u32, unsigned long);
174 static u16 uli_phy_read(unsigned long, u8, u8, u32);
175 static u16 phy_readby_cr10(unsigned long, u8, u8);
176 static void uli_phy_write(unsigned long, u8, u8, u16, u32);
177 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
178 static void phy_write_1bit(unsigned long, u32, u32);
179 static u16 phy_read_1bit(unsigned long, u32);
180 static int uli526x_rx_packet(struct eth_device *);
181 static void uli526x_free_tx_pkt(struct eth_device *,
182 struct uli526x_board_info *);
183 static void uli526x_reuse_buf(struct rx_desc *);
184 static void uli526x_init(struct eth_device *);
185 static void uli526x_set_phyxcer(struct uli526x_board_info *);
188 static int uli526x_init_one(struct eth_device *, bd_t *);
189 static void uli526x_disable(struct eth_device *);
190 static void set_mac_addr(struct eth_device *);
192 static struct pci_device_id uli526x_pci_tbl[] = {
193 { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
194 { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
198 /* ULI526X network board routine */
201 * Search ULI526X board, register it
204 int uli526x_initialize(bd_t *bis)
208 struct eth_device *dev;
209 struct uli526x_board_info *db; /* board information structure */
215 /* Find PCI device */
216 devno = pci_find_devices(uli526x_pci_tbl, idx++);
220 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
223 dev = (struct eth_device *)malloc(sizeof *dev);
225 printf("uli526x: Can not allocate memory\n");
228 memset(dev, 0, sizeof(*dev));
229 sprintf(dev->name, "uli526x#%d", card_number);
230 db = (struct uli526x_board_info *)
231 malloc(sizeof(struct uli526x_board_info));
235 dev->iobase = iobase;
237 dev->init = uli526x_init_one;
238 dev->halt = uli526x_disable;
239 dev->send = uli526x_start_xmit;
240 dev->recv = uli526x_rx_packet;
243 db->ioaddr = dev->iobase;
246 pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
248 printf("uli526x: uli526x @0x%x\n", iobase);
249 printf("uli526x: chip_id%x\n", db->chip_id);
253 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
259 static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
262 struct uli526x_board_info *db = dev->priv;
270 uli526x_media_mode = mode;
273 uli526x_media_mode = ULI526X_AUTO;
277 /* Allocate Tx/Rx descriptor memory */
278 db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
279 db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
280 if (db->desc_pool_ptr == NULL)
283 db->buf_pool_ptr = (uchar *)&buf_pool[0];
284 db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
285 if (db->buf_pool_ptr == NULL)
288 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
289 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
291 db->buf_pool_start = db->buf_pool_ptr;
292 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
295 printf("%s(): db->ioaddr= 0x%x\n",
296 __FUNCTION__, db->ioaddr);
297 printf("%s(): media_mode= 0x%x\n",
298 __FUNCTION__, uli526x_media_mode);
299 printf("%s(): db->desc_pool_ptr= 0x%x\n",
300 __FUNCTION__, db->desc_pool_ptr);
301 printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
302 __FUNCTION__, db->desc_pool_dma_ptr);
303 printf("%s(): db->buf_pool_ptr= 0x%x\n",
304 __FUNCTION__, db->buf_pool_ptr);
305 printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
306 __FUNCTION__, db->buf_pool_dma_ptr);
309 /* read 64 word srom data */
310 for (i = 0; i < 64; i++)
311 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
314 /* Set Node address */
315 if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
316 ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
317 /* SROM absent, so write MAC address to ID Table */
319 else { /*Exist SROM*/
320 for (i = 0; i < 6; i++)
321 dev->enetaddr[i] = db->srom[20 + i];
324 for (i = 0; i < 6; i++)
325 printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
327 db->PHY_reg4 = 0x1e0;
329 /* system variable init */
330 db->cr6_data = CR6_DEFAULT ;
331 db->cr6_data |= ULI526X_TXTH_256;
332 db->cr0_data = CR0_DEFAULT;
337 static void uli526x_disable(struct eth_device *dev)
340 printf("uli526x_disable\n");
342 struct uli526x_board_info *db = dev->priv;
344 if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
345 /* Reset & stop ULI526X board */
346 outl(ULI526X_RESET, db->ioaddr + DCR0);
348 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
350 /* reset the board */
351 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
352 update_cr6(db->cr6_data, dev->iobase);
353 outl(0, dev->iobase + DCR7); /* Disable Interrupt */
354 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
358 /* Initialize ULI526X board
359 * Reset ULI526X board
360 * Initialize TX/Rx descriptor chain structure
361 * Send the set-up frame
362 * Enable Tx/Rx machine
365 static void uli526x_init(struct eth_device *dev)
368 struct uli526x_board_info *db = dev->priv;
373 /* Reset M526x MAC controller */
374 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
376 outl(db->cr0_data, db->ioaddr + DCR0);
379 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
381 db->tx_packet_cnt = 0;
382 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
384 phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
385 if (phy_value != 0xffff && phy_value != 0) {
386 db->phy_addr = phy_tmp;
392 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
393 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
396 printf("Can not find the phy address!!!");
398 /* Parser SROM and media mode */
399 db->media_mode = uli526x_media_mode;
401 if (!(inl(db->ioaddr + DCR12) & 0x8)) {
402 /* Phyxcer capability setting */
403 phy_reg_reset = uli_phy_read(db->ioaddr,
404 db->phy_addr, 0, db->chip_id);
405 phy_reg_reset = (phy_reg_reset | 0x8000);
406 uli_phy_write(db->ioaddr, db->phy_addr, 0,
407 phy_reg_reset, db->chip_id);
410 /* Process Phyxcer Media Mode */
411 uli526x_set_phyxcer(db);
413 /* Media Mode Process */
414 if (!(db->media_mode & ULI526X_AUTO))
415 db->op_mode = db->media_mode; /* Force Mode */
417 /* Initialize Transmit/Receive decriptor and CR3/4 */
418 uli526x_descriptor_init(db, db->ioaddr);
420 /* Init CR6 to program M526X operation */
421 update_cr6(db->cr6_data, db->ioaddr);
423 /* Init CR7, interrupt active bit */
424 db->cr7_data = CR7_DEFAULT;
425 outl(db->cr7_data, db->ioaddr + DCR7);
427 /* Init CR15, Tx jabber and Rx watchdog timer */
428 outl(db->cr15_data, db->ioaddr + DCR15);
430 /* Enable ULI526X Tx/Rx function */
431 db->cr6_data |= CR6_RXSC | CR6_TXSC;
432 update_cr6(db->cr6_data, db->ioaddr);
433 while (!(inl(db->ioaddr + DCR12) & 0x8))
438 * Hardware start transmission.
439 * Send a packet to media from the upper layer.
442 static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length)
444 struct uli526x_board_info *db = dev->priv;
445 struct tx_desc *txptr;
446 unsigned int len = length;
447 /* Too large packet check */
448 if (len > MAX_PACKET_SIZE) {
449 printf(": big packet = %d\n", len);
453 /* No Tx resource check, it never happen nromally */
454 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
455 printf("No Tx resource %ld\n", db->tx_packet_cnt);
459 /* Disable NIC interrupt */
460 outl(0, dev->iobase + DCR7);
462 /* transmit this packet */
463 txptr = db->tx_insert_ptr;
464 memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
465 txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
467 /* Point to next transmit free descriptor */
468 db->tx_insert_ptr = txptr->next_tx_desc;
470 /* Transmit Packet Process */
471 if ((db->tx_packet_cnt < TX_DESC_CNT)) {
472 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
473 db->tx_packet_cnt++; /* Ready to send */
474 outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
477 /* Got ULI526X status */
478 db->cr5_data = inl(db->ioaddr + DCR5);
479 outl(db->cr5_data, db->ioaddr + DCR5);
482 printf("%s(): length = 0x%x\n", __FUNCTION__, length);
483 printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
486 outl(db->cr7_data, dev->iobase + DCR7);
487 uli526x_free_tx_pkt(dev, db);
493 * Free TX resource after TX complete
496 static void uli526x_free_tx_pkt(struct eth_device *dev,
497 struct uli526x_board_info *db)
499 struct tx_desc *txptr;
502 txptr = db->tx_remove_ptr;
503 while (db->tx_packet_cnt) {
504 tdes0 = le32_to_cpu(txptr->tdes0);
505 /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
506 if (tdes0 & 0x80000000)
509 /* A packet sent completed */
512 if (tdes0 != 0x7fffffff) {
514 printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
516 if (tdes0 & TDES0_ERR_MASK) {
517 if (tdes0 & 0x0002) { /* UnderRun */
518 if (!(db->cr6_data & CR6_SFT)) {
519 db->cr6_data = db->cr6_data |
521 update_cr6(db->cr6_data,
528 txptr = txptr->next_tx_desc;
531 /* Update TX remove pointer to next */
532 db->tx_remove_ptr = txptr;
537 * Receive the come packet and pass to upper layer
540 static int uli526x_rx_packet(struct eth_device *dev)
542 struct uli526x_board_info *db = dev->priv;
543 struct rx_desc *rxptr;
547 rxptr = db->rx_ready_ptr;
549 rdes0 = le32_to_cpu(rxptr->rdes0);
551 printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0);
553 if (!(rdes0 & 0x80000000)) { /* packet owner check */
554 if ((rdes0 & 0x300) != 0x300) {
555 /* A packet without First/Last flag */
557 printf("A packet without First/Last flag");
558 uli526x_reuse_buf(rxptr);
560 /* A packet with First/Last flag */
561 rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
563 printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
565 /* error summary bit check */
566 if (rdes0 & 0x8000) {
567 /* This is a error packet */
568 printf("Error: rdes0: %x\n", rdes0);
571 if (!(rdes0 & 0x8000) ||
572 ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
575 printf("%s(): rx_skb_ptr =%x\n",
576 __FUNCTION__, rxptr->rx_buf_ptr);
577 printf("%s(): rxlen =%x\n",
578 __FUNCTION__, rxlen);
580 printf("%s(): buf addr =%x\n",
581 __FUNCTION__, rxptr->rx_buf_ptr);
582 printf("%s(): rxlen =%x\n",
583 __FUNCTION__, rxlen);
585 for (i = 0; i < 0x20; i++)
586 printf("%s(): data[%x] =%x\n",
587 __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
590 net_process_received_packet(
591 (uchar *)rxptr->rx_buf_ptr, rxlen);
592 uli526x_reuse_buf(rxptr);
595 /* Reuse SKB buffer when the packet is error */
596 printf("Reuse buffer, rdes0");
597 uli526x_reuse_buf(rxptr);
601 rxptr = rxptr->next_rx_desc;
604 db->rx_ready_ptr = rxptr;
609 * Reuse the RX buffer
612 static void uli526x_reuse_buf(struct rx_desc *rxptr)
615 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
616 rxptr->rdes0 = cpu_to_le32(0x80000000);
618 printf("Buffer reuse method error");
621 * Initialize transmit/Receive descriptor
622 * Using Chain structure, and allocate Tx/Rx buffer
625 static void uli526x_descriptor_init(struct uli526x_board_info *db,
626 unsigned long ioaddr)
628 struct tx_desc *tmp_tx;
629 struct rx_desc *tmp_rx;
630 unsigned char *tmp_buf;
631 dma_addr_t tmp_tx_dma, tmp_rx_dma;
632 dma_addr_t tmp_buf_dma;
634 /* tx descriptor start pointer */
635 db->tx_insert_ptr = db->first_tx_desc;
636 db->tx_remove_ptr = db->first_tx_desc;
638 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
640 /* rx descriptor start pointer */
641 db->first_rx_desc = (void *)db->first_tx_desc +
642 sizeof(struct tx_desc) * TX_DESC_CNT;
643 db->first_rx_desc_dma = db->first_tx_desc_dma +
644 sizeof(struct tx_desc) * TX_DESC_CNT;
645 db->rx_ready_ptr = db->first_rx_desc;
646 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
648 printf("%s(): db->first_tx_desc= 0x%x\n",
649 __FUNCTION__, db->first_tx_desc);
650 printf("%s(): db->first_rx_desc_dma= 0x%x\n",
651 __FUNCTION__, db->first_rx_desc_dma);
653 /* Init Transmit chain */
654 tmp_buf = db->buf_pool_start;
655 tmp_buf_dma = db->buf_pool_dma_start;
656 tmp_tx_dma = db->first_tx_desc_dma;
657 for (tmp_tx = db->first_tx_desc, i = 0;
658 i < TX_DESC_CNT; i++, tmp_tx++) {
659 tmp_tx->tx_buf_ptr = (char *)tmp_buf;
660 tmp_tx->tdes0 = cpu_to_le32(0);
661 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
662 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
663 tmp_tx_dma += sizeof(struct tx_desc);
664 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
665 tmp_tx->next_tx_desc = tmp_tx + 1;
666 tmp_buf = tmp_buf + TX_BUF_ALLOC;
667 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
669 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
670 tmp_tx->next_tx_desc = db->first_tx_desc;
672 /* Init Receive descriptor chain */
673 tmp_rx_dma = db->first_rx_desc_dma;
674 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
676 tmp_rx->rdes0 = cpu_to_le32(0);
677 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
678 tmp_rx_dma += sizeof(struct rx_desc);
679 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
680 tmp_rx->next_rx_desc = tmp_rx + 1;
682 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
683 tmp_rx->next_rx_desc = db->first_rx_desc;
685 /* pre-allocate Rx buffer */
686 allocate_rx_buffer(db);
691 * Firstly stop ULI526X, then written value and start
694 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
697 outl(cr6_data, ioaddr + DCR6);
702 * Allocate rx buffer,
705 static void allocate_rx_buffer(struct uli526x_board_info *db)
708 struct rx_desc *rxptr;
709 rxptr = db->first_rx_desc;
712 for (index = 0; index < RX_DESC_CNT; index++) {
713 addr = (u32)net_rx_packets[index];
714 addr += (16 - (addr & 15));
715 rxptr->rx_buf_ptr = (char *) addr;
716 rxptr->rdes2 = cpu_to_le32(addr);
717 rxptr->rdes0 = cpu_to_le32(0x80000000);
719 printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
720 printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
721 printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
722 printf("%s(): rxptr buf address = 0x%x\n", \
723 __FUNCTION__, rxptr->rx_buf_ptr);
724 printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
726 rxptr = rxptr->next_rx_desc;
731 * Read one word data from the serial ROM
734 static u16 read_srom_word(long ioaddr, int offset)
738 long cr9_ioaddr = ioaddr + DCR9;
740 outl(CR9_SROM_READ, cr9_ioaddr);
741 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
743 /* Send the Read Command 110b */
744 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
745 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
746 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
748 /* Send the offset */
749 for (i = 5; i >= 0; i--) {
750 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
751 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
754 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
756 for (i = 16; i > 0; i--) {
757 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
759 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
761 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
765 outl(CR9_SROM_READ, cr9_ioaddr);
770 * Set 10/100 phyxcer capability
771 * AUTO mode : phyxcer register4 is NIC capability
772 * Force mode: phyxcer register4 is the force media
775 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
779 /* Phyxcer capability setting */
780 phy_reg = uli_phy_read(db->ioaddr,
781 db->phy_addr, 4, db->chip_id) & ~0x01e0;
783 if (db->media_mode & ULI526X_AUTO) {
785 phy_reg |= db->PHY_reg4;
788 switch (db->media_mode) {
789 case ULI526X_10MHF: phy_reg |= 0x20; break;
790 case ULI526X_10MFD: phy_reg |= 0x40; break;
791 case ULI526X_100MHF: phy_reg |= 0x80; break;
792 case ULI526X_100MFD: phy_reg |= 0x100; break;
797 /* Write new capability to Phyxcer Reg4 */
798 if (!(phy_reg & 0x01e0)) {
799 phy_reg |= db->PHY_reg4;
800 db->media_mode |= ULI526X_AUTO;
802 uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
804 /* Restart Auto-Negotiation */
805 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
810 * Write a word to Phy register
813 static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
814 u16 phy_data, u32 chip_id)
817 unsigned long ioaddr;
819 if (chip_id == PCI_ULI5263_ID) {
820 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
823 /* M5261/M5263 Chip */
824 ioaddr = iobase + DCR9;
826 /* Send 33 synchronization clock to Phy controller */
827 for (i = 0; i < 35; i++)
828 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
830 /* Send start command(01) to Phy */
831 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
832 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
834 /* Send write command(01) to Phy */
835 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
836 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
838 /* Send Phy address */
839 for (i = 0x10; i > 0; i = i >> 1)
840 phy_write_1bit(ioaddr, phy_addr & i ?
841 PHY_DATA_1 : PHY_DATA_0, chip_id);
843 /* Send register address */
844 for (i = 0x10; i > 0; i = i >> 1)
845 phy_write_1bit(ioaddr, offset & i ?
846 PHY_DATA_1 : PHY_DATA_0, chip_id);
848 /* written trasnition */
849 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
850 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
852 /* Write a word data to PHY controller */
853 for (i = 0x8000; i > 0; i >>= 1)
854 phy_write_1bit(ioaddr, phy_data & i ?
855 PHY_DATA_1 : PHY_DATA_0, chip_id);
859 * Read a word data from phy register
862 static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
867 unsigned long ioaddr;
869 if (chip_id == PCI_ULI5263_ID)
870 return phy_readby_cr10(iobase, phy_addr, offset);
871 /* M5261/M5263 Chip */
872 ioaddr = iobase + DCR9;
874 /* Send 33 synchronization clock to Phy controller */
875 for (i = 0; i < 35; i++)
876 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
878 /* Send start command(01) to Phy */
879 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
880 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
882 /* Send read command(10) to Phy */
883 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
884 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
886 /* Send Phy address */
887 for (i = 0x10; i > 0; i = i >> 1)
888 phy_write_1bit(ioaddr, phy_addr & i ?
889 PHY_DATA_1 : PHY_DATA_0, chip_id);
891 /* Send register address */
892 for (i = 0x10; i > 0; i = i >> 1)
893 phy_write_1bit(ioaddr, offset & i ?
894 PHY_DATA_1 : PHY_DATA_0, chip_id);
896 /* Skip transition state */
897 phy_read_1bit(ioaddr, chip_id);
899 /* read 16bit data */
900 for (phy_data = 0, i = 0; i < 16; i++) {
902 phy_data |= phy_read_1bit(ioaddr, chip_id);
908 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
910 unsigned long ioaddr, cr10_value;
912 ioaddr = iobase + DCR10;
913 cr10_value = phy_addr;
914 cr10_value = (cr10_value<<5) + offset;
915 cr10_value = (cr10_value<<16) + 0x08000000;
916 outl(cr10_value, ioaddr);
919 cr10_value = inl(ioaddr);
920 if (cr10_value & 0x10000000)
923 return (cr10_value&0x0ffff);
926 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
927 u8 offset, u16 phy_data)
929 unsigned long ioaddr, cr10_value;
931 ioaddr = iobase + DCR10;
932 cr10_value = phy_addr;
933 cr10_value = (cr10_value<<5) + offset;
934 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
935 outl(cr10_value, ioaddr);
939 * Write one bit data to Phy Controller
942 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
944 outl(phy_data , ioaddr); /* MII Clock Low */
946 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
948 outl(phy_data , ioaddr); /* MII Clock Low */
953 * Read one bit phy data from PHY controller
956 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
960 outl(0x50000 , ioaddr);
962 phy_data = (inl(ioaddr) >> 19) & 0x1;
963 outl(0x40000 , ioaddr);
970 * Set MAC address to ID Table
973 static void set_mac_addr(struct eth_device *dev)
977 struct uli526x_board_info *db = dev->priv;
978 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
979 /* Reset dianostic pointer port */
980 outl(0x1c0, db->ioaddr + DCR13);
981 outl(0, db->ioaddr + DCR14); /* Clear reset port */
982 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
983 outl(0, db->ioaddr + DCR14); /* Clear reset port */
984 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
985 /* Select ID Table access port */
986 outl(0x1b0, db->ioaddr + DCR13);
987 /* Read MAC address from CR14 */
988 for (i = 0; i < 3; i++) {
989 addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
990 outl(addr, db->ioaddr + DCR14);
993 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
994 outl(0, db->ioaddr + DCR0); /* Clear CR0 */