]> git.kernelconcepts.de Git - karo-tx-linux.git/blob - drivers/net/usb/r8152.c
net: rename vlan_tx_* helpers since "tx" is misleading there
[karo-tx-linux.git] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
25 #include <uapi/linux/mdio.h>
26 #include <linux/mdio.h>
27 #include <linux/usb/cdc.h>
28
29 /* Version Information */
30 #define DRIVER_VERSION "v1.07.0 (2014/10/09)"
31 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
32 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
33 #define MODULENAME "r8152"
34
35 #define R8152_PHY_ID            32
36
37 #define PLA_IDR                 0xc000
38 #define PLA_RCR                 0xc010
39 #define PLA_RMS                 0xc016
40 #define PLA_RXFIFO_CTRL0        0xc0a0
41 #define PLA_RXFIFO_CTRL1        0xc0a4
42 #define PLA_RXFIFO_CTRL2        0xc0a8
43 #define PLA_FMC                 0xc0b4
44 #define PLA_CFG_WOL             0xc0b6
45 #define PLA_TEREDO_CFG          0xc0bc
46 #define PLA_MAR                 0xcd00
47 #define PLA_BACKUP              0xd000
48 #define PAL_BDC_CR              0xd1a0
49 #define PLA_TEREDO_TIMER        0xd2cc
50 #define PLA_REALWOW_TIMER       0xd2e8
51 #define PLA_LEDSEL              0xdd90
52 #define PLA_LED_FEATURE         0xdd92
53 #define PLA_PHYAR               0xde00
54 #define PLA_BOOT_CTRL           0xe004
55 #define PLA_GPHY_INTR_IMR       0xe022
56 #define PLA_EEE_CR              0xe040
57 #define PLA_EEEP_CR             0xe080
58 #define PLA_MAC_PWR_CTRL        0xe0c0
59 #define PLA_MAC_PWR_CTRL2       0xe0ca
60 #define PLA_MAC_PWR_CTRL3       0xe0cc
61 #define PLA_MAC_PWR_CTRL4       0xe0ce
62 #define PLA_WDT6_CTRL           0xe428
63 #define PLA_TCR0                0xe610
64 #define PLA_TCR1                0xe612
65 #define PLA_MTPS                0xe615
66 #define PLA_TXFIFO_CTRL         0xe618
67 #define PLA_RSTTALLY            0xe800
68 #define PLA_CR                  0xe813
69 #define PLA_CRWECR              0xe81c
70 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
71 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
72 #define PLA_CONFIG5             0xe822
73 #define PLA_PHY_PWR             0xe84c
74 #define PLA_OOB_CTRL            0xe84f
75 #define PLA_CPCR                0xe854
76 #define PLA_MISC_0              0xe858
77 #define PLA_MISC_1              0xe85a
78 #define PLA_OCP_GPHY_BASE       0xe86c
79 #define PLA_TALLYCNT            0xe890
80 #define PLA_SFF_STS_7           0xe8de
81 #define PLA_PHYSTATUS           0xe908
82 #define PLA_BP_BA               0xfc26
83 #define PLA_BP_0                0xfc28
84 #define PLA_BP_1                0xfc2a
85 #define PLA_BP_2                0xfc2c
86 #define PLA_BP_3                0xfc2e
87 #define PLA_BP_4                0xfc30
88 #define PLA_BP_5                0xfc32
89 #define PLA_BP_6                0xfc34
90 #define PLA_BP_7                0xfc36
91 #define PLA_BP_EN               0xfc38
92
93 #define USB_U2P3_CTRL           0xb460
94 #define USB_DEV_STAT            0xb808
95 #define USB_USB_CTRL            0xd406
96 #define USB_PHY_CTRL            0xd408
97 #define USB_TX_AGG              0xd40a
98 #define USB_RX_BUF_TH           0xd40c
99 #define USB_USB_TIMER           0xd428
100 #define USB_RX_EARLY_AGG        0xd42c
101 #define USB_PM_CTRL_STATUS      0xd432
102 #define USB_TX_DMA              0xd434
103 #define USB_TOLERANCE           0xd490
104 #define USB_LPM_CTRL            0xd41a
105 #define USB_UPS_CTRL            0xd800
106 #define USB_MISC_0              0xd81a
107 #define USB_POWER_CUT           0xd80a
108 #define USB_AFE_CTRL2           0xd824
109 #define USB_WDT11_CTRL          0xe43c
110 #define USB_BP_BA               0xfc26
111 #define USB_BP_0                0xfc28
112 #define USB_BP_1                0xfc2a
113 #define USB_BP_2                0xfc2c
114 #define USB_BP_3                0xfc2e
115 #define USB_BP_4                0xfc30
116 #define USB_BP_5                0xfc32
117 #define USB_BP_6                0xfc34
118 #define USB_BP_7                0xfc36
119 #define USB_BP_EN               0xfc38
120
121 /* OCP Registers */
122 #define OCP_ALDPS_CONFIG        0x2010
123 #define OCP_EEE_CONFIG1         0x2080
124 #define OCP_EEE_CONFIG2         0x2092
125 #define OCP_EEE_CONFIG3         0x2094
126 #define OCP_BASE_MII            0xa400
127 #define OCP_EEE_AR              0xa41a
128 #define OCP_EEE_DATA            0xa41c
129 #define OCP_PHY_STATUS          0xa420
130 #define OCP_POWER_CFG           0xa430
131 #define OCP_EEE_CFG             0xa432
132 #define OCP_SRAM_ADDR           0xa436
133 #define OCP_SRAM_DATA           0xa438
134 #define OCP_DOWN_SPEED          0xa442
135 #define OCP_EEE_ABLE            0xa5c4
136 #define OCP_EEE_ADV             0xa5d0
137 #define OCP_EEE_LPABLE          0xa5d2
138 #define OCP_ADC_CFG             0xbc06
139
140 /* SRAM Register */
141 #define SRAM_LPF_CFG            0x8012
142 #define SRAM_10M_AMP1           0x8080
143 #define SRAM_10M_AMP2           0x8082
144 #define SRAM_IMPEDANCE          0x8084
145
146 /* PLA_RCR */
147 #define RCR_AAP                 0x00000001
148 #define RCR_APM                 0x00000002
149 #define RCR_AM                  0x00000004
150 #define RCR_AB                  0x00000008
151 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
152
153 /* PLA_RXFIFO_CTRL0 */
154 #define RXFIFO_THR1_NORMAL      0x00080002
155 #define RXFIFO_THR1_OOB         0x01800003
156
157 /* PLA_RXFIFO_CTRL1 */
158 #define RXFIFO_THR2_FULL        0x00000060
159 #define RXFIFO_THR2_HIGH        0x00000038
160 #define RXFIFO_THR2_OOB         0x0000004a
161 #define RXFIFO_THR2_NORMAL      0x00a0
162
163 /* PLA_RXFIFO_CTRL2 */
164 #define RXFIFO_THR3_FULL        0x00000078
165 #define RXFIFO_THR3_HIGH        0x00000048
166 #define RXFIFO_THR3_OOB         0x0000005a
167 #define RXFIFO_THR3_NORMAL      0x0110
168
169 /* PLA_TXFIFO_CTRL */
170 #define TXFIFO_THR_NORMAL       0x00400008
171 #define TXFIFO_THR_NORMAL2      0x01000008
172
173 /* PLA_FMC */
174 #define FMC_FCR_MCU_EN          0x0001
175
176 /* PLA_EEEP_CR */
177 #define EEEP_CR_EEEP_TX         0x0002
178
179 /* PLA_WDT6_CTRL */
180 #define WDT6_SET_MODE           0x0010
181
182 /* PLA_TCR0 */
183 #define TCR0_TX_EMPTY           0x0800
184 #define TCR0_AUTO_FIFO          0x0080
185
186 /* PLA_TCR1 */
187 #define VERSION_MASK            0x7cf0
188
189 /* PLA_MTPS */
190 #define MTPS_JUMBO              (12 * 1024 / 64)
191 #define MTPS_DEFAULT            (6 * 1024 / 64)
192
193 /* PLA_RSTTALLY */
194 #define TALLY_RESET             0x0001
195
196 /* PLA_CR */
197 #define CR_RST                  0x10
198 #define CR_RE                   0x08
199 #define CR_TE                   0x04
200
201 /* PLA_CRWECR */
202 #define CRWECR_NORAML           0x00
203 #define CRWECR_CONFIG           0xc0
204
205 /* PLA_OOB_CTRL */
206 #define NOW_IS_OOB              0x80
207 #define TXFIFO_EMPTY            0x20
208 #define RXFIFO_EMPTY            0x10
209 #define LINK_LIST_READY         0x02
210 #define DIS_MCU_CLROOB          0x01
211 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
212
213 /* PLA_MISC_1 */
214 #define RXDY_GATED_EN           0x0008
215
216 /* PLA_SFF_STS_7 */
217 #define RE_INIT_LL              0x8000
218 #define MCU_BORW_EN             0x4000
219
220 /* PLA_CPCR */
221 #define CPCR_RX_VLAN            0x0040
222
223 /* PLA_CFG_WOL */
224 #define MAGIC_EN                0x0001
225
226 /* PLA_TEREDO_CFG */
227 #define TEREDO_SEL              0x8000
228 #define TEREDO_WAKE_MASK        0x7f00
229 #define TEREDO_RS_EVENT_MASK    0x00fe
230 #define OOB_TEREDO_EN           0x0001
231
232 /* PAL_BDC_CR */
233 #define ALDPS_PROXY_MODE        0x0001
234
235 /* PLA_CONFIG34 */
236 #define LINK_ON_WAKE_EN         0x0010
237 #define LINK_OFF_WAKE_EN        0x0008
238
239 /* PLA_CONFIG5 */
240 #define BWF_EN                  0x0040
241 #define MWF_EN                  0x0020
242 #define UWF_EN                  0x0010
243 #define LAN_WAKE_EN             0x0002
244
245 /* PLA_LED_FEATURE */
246 #define LED_MODE_MASK           0x0700
247
248 /* PLA_PHY_PWR */
249 #define TX_10M_IDLE_EN          0x0080
250 #define PFM_PWM_SWITCH          0x0040
251
252 /* PLA_MAC_PWR_CTRL */
253 #define D3_CLK_GATED_EN         0x00004000
254 #define MCU_CLK_RATIO           0x07010f07
255 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
256 #define ALDPS_SPDWN_RATIO       0x0f87
257
258 /* PLA_MAC_PWR_CTRL2 */
259 #define EEE_SPDWN_RATIO         0x8007
260
261 /* PLA_MAC_PWR_CTRL3 */
262 #define PKT_AVAIL_SPDWN_EN      0x0100
263 #define SUSPEND_SPDWN_EN        0x0004
264 #define U1U2_SPDWN_EN           0x0002
265 #define L1_SPDWN_EN             0x0001
266
267 /* PLA_MAC_PWR_CTRL4 */
268 #define PWRSAVE_SPDWN_EN        0x1000
269 #define RXDV_SPDWN_EN           0x0800
270 #define TX10MIDLE_EN            0x0100
271 #define TP100_SPDWN_EN          0x0020
272 #define TP500_SPDWN_EN          0x0010
273 #define TP1000_SPDWN_EN         0x0008
274 #define EEE_SPDWN_EN            0x0001
275
276 /* PLA_GPHY_INTR_IMR */
277 #define GPHY_STS_MSK            0x0001
278 #define SPEED_DOWN_MSK          0x0002
279 #define SPDWN_RXDV_MSK          0x0004
280 #define SPDWN_LINKCHG_MSK       0x0008
281
282 /* PLA_PHYAR */
283 #define PHYAR_FLAG              0x80000000
284
285 /* PLA_EEE_CR */
286 #define EEE_RX_EN               0x0001
287 #define EEE_TX_EN               0x0002
288
289 /* PLA_BOOT_CTRL */
290 #define AUTOLOAD_DONE           0x0002
291
292 /* USB_DEV_STAT */
293 #define STAT_SPEED_MASK         0x0006
294 #define STAT_SPEED_HIGH         0x0000
295 #define STAT_SPEED_FULL         0x0002
296
297 /* USB_TX_AGG */
298 #define TX_AGG_MAX_THRESHOLD    0x03
299
300 /* USB_RX_BUF_TH */
301 #define RX_THR_SUPPER           0x0c350180
302 #define RX_THR_HIGH             0x7a120180
303 #define RX_THR_SLOW             0xffff0180
304
305 /* USB_TX_DMA */
306 #define TEST_MODE_DISABLE       0x00000001
307 #define TX_SIZE_ADJUST1         0x00000100
308
309 /* USB_UPS_CTRL */
310 #define POWER_CUT               0x0100
311
312 /* USB_PM_CTRL_STATUS */
313 #define RESUME_INDICATE         0x0001
314
315 /* USB_USB_CTRL */
316 #define RX_AGG_DISABLE          0x0010
317
318 /* USB_U2P3_CTRL */
319 #define U2P3_ENABLE             0x0001
320
321 /* USB_POWER_CUT */
322 #define PWR_EN                  0x0001
323 #define PHASE2_EN               0x0008
324
325 /* USB_MISC_0 */
326 #define PCUT_STATUS             0x0001
327
328 /* USB_RX_EARLY_AGG */
329 #define EARLY_AGG_SUPPER        0x0e832981
330 #define EARLY_AGG_HIGH          0x0e837a12
331 #define EARLY_AGG_SLOW          0x0e83ffff
332
333 /* USB_WDT11_CTRL */
334 #define TIMER11_EN              0x0001
335
336 /* USB_LPM_CTRL */
337 #define LPM_TIMER_MASK          0x0c
338 #define LPM_TIMER_500MS         0x04    /* 500 ms */
339 #define LPM_TIMER_500US         0x0c    /* 500 us */
340
341 /* USB_AFE_CTRL2 */
342 #define SEN_VAL_MASK            0xf800
343 #define SEN_VAL_NORMAL          0xa000
344 #define SEL_RXIDLE              0x0100
345
346 /* OCP_ALDPS_CONFIG */
347 #define ENPWRSAVE               0x8000
348 #define ENPDNPS                 0x0200
349 #define LINKENA                 0x0100
350 #define DIS_SDSAVE              0x0010
351
352 /* OCP_PHY_STATUS */
353 #define PHY_STAT_MASK           0x0007
354 #define PHY_STAT_LAN_ON         3
355 #define PHY_STAT_PWRDN          5
356
357 /* OCP_POWER_CFG */
358 #define EEE_CLKDIV_EN           0x8000
359 #define EN_ALDPS                0x0004
360 #define EN_10M_PLLOFF           0x0001
361
362 /* OCP_EEE_CONFIG1 */
363 #define RG_TXLPI_MSK_HFDUP      0x8000
364 #define RG_MATCLR_EN            0x4000
365 #define EEE_10_CAP              0x2000
366 #define EEE_NWAY_EN             0x1000
367 #define TX_QUIET_EN             0x0200
368 #define RX_QUIET_EN             0x0100
369 #define sd_rise_time_mask       0x0070
370 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
371 #define RG_RXLPI_MSK_HFDUP      0x0008
372 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
373
374 /* OCP_EEE_CONFIG2 */
375 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
376 #define RG_DACQUIET_EN          0x0400
377 #define RG_LDVQUIET_EN          0x0200
378 #define RG_CKRSEL               0x0020
379 #define RG_EEEPRG_EN            0x0010
380
381 /* OCP_EEE_CONFIG3 */
382 #define fast_snr_mask           0xff80
383 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
384 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
385 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
386
387 /* OCP_EEE_AR */
388 /* bit[15:14] function */
389 #define FUN_ADDR                0x0000
390 #define FUN_DATA                0x4000
391 /* bit[4:0] device addr */
392
393 /* OCP_EEE_CFG */
394 #define CTAP_SHORT_EN           0x0040
395 #define EEE10_EN                0x0010
396
397 /* OCP_DOWN_SPEED */
398 #define EN_10M_BGOFF            0x0080
399
400 /* OCP_ADC_CFG */
401 #define CKADSEL_L               0x0100
402 #define ADC_EN                  0x0080
403 #define EN_EMI_L                0x0040
404
405 /* SRAM_LPF_CFG */
406 #define LPF_AUTO_TUNE           0x8000
407
408 /* SRAM_10M_AMP1 */
409 #define GDAC_IB_UPALL           0x0008
410
411 /* SRAM_10M_AMP2 */
412 #define AMP_DN                  0x0200
413
414 /* SRAM_IMPEDANCE */
415 #define RX_DRIVING_MASK         0x6000
416
417 enum rtl_register_content {
418         _1000bps        = 0x10,
419         _100bps         = 0x08,
420         _10bps          = 0x04,
421         LINK_STATUS     = 0x02,
422         FULL_DUP        = 0x01,
423 };
424
425 #define RTL8152_MAX_TX          4
426 #define RTL8152_MAX_RX          10
427 #define INTBUFSIZE              2
428 #define CRC_SIZE                4
429 #define TX_ALIGN                4
430 #define RX_ALIGN                8
431
432 #define INTR_LINK               0x0004
433
434 #define RTL8152_REQT_READ       0xc0
435 #define RTL8152_REQT_WRITE      0x40
436 #define RTL8152_REQ_GET_REGS    0x05
437 #define RTL8152_REQ_SET_REGS    0x05
438
439 #define BYTE_EN_DWORD           0xff
440 #define BYTE_EN_WORD            0x33
441 #define BYTE_EN_BYTE            0x11
442 #define BYTE_EN_SIX_BYTES       0x3f
443 #define BYTE_EN_START_MASK      0x0f
444 #define BYTE_EN_END_MASK        0xf0
445
446 #define RTL8153_MAX_PACKET      9216 /* 9K */
447 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
448 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
449 #define RTL8153_RMS             RTL8153_MAX_PACKET
450 #define RTL8152_TX_TIMEOUT      (5 * HZ)
451
452 /* rtl8152 flags */
453 enum rtl8152_flags {
454         RTL8152_UNPLUG = 0,
455         RTL8152_SET_RX_MODE,
456         WORK_ENABLE,
457         RTL8152_LINK_CHG,
458         SELECTIVE_SUSPEND,
459         PHY_RESET,
460         SCHEDULE_TASKLET,
461 };
462
463 /* Define these values to match your device */
464 #define VENDOR_ID_REALTEK               0x0bda
465 #define VENDOR_ID_SAMSUNG               0x04e8
466
467 #define MCU_TYPE_PLA                    0x0100
468 #define MCU_TYPE_USB                    0x0000
469
470 struct tally_counter {
471         __le64  tx_packets;
472         __le64  rx_packets;
473         __le64  tx_errors;
474         __le32  rx_errors;
475         __le16  rx_missed;
476         __le16  align_errors;
477         __le32  tx_one_collision;
478         __le32  tx_multi_collision;
479         __le64  rx_unicast;
480         __le64  rx_broadcast;
481         __le32  rx_multicast;
482         __le16  tx_aborted;
483         __le16  tx_underrun;
484 };
485
486 struct rx_desc {
487         __le32 opts1;
488 #define RX_LEN_MASK                     0x7fff
489
490         __le32 opts2;
491 #define RD_UDP_CS                       (1 << 23)
492 #define RD_TCP_CS                       (1 << 22)
493 #define RD_IPV6_CS                      (1 << 20)
494 #define RD_IPV4_CS                      (1 << 19)
495
496         __le32 opts3;
497 #define IPF                             (1 << 23) /* IP checksum fail */
498 #define UDPF                            (1 << 22) /* UDP checksum fail */
499 #define TCPF                            (1 << 21) /* TCP checksum fail */
500 #define RX_VLAN_TAG                     (1 << 16)
501
502         __le32 opts4;
503         __le32 opts5;
504         __le32 opts6;
505 };
506
507 struct tx_desc {
508         __le32 opts1;
509 #define TX_FS                   (1 << 31) /* First segment of a packet */
510 #define TX_LS                   (1 << 30) /* Final segment of a packet */
511 #define GTSENDV4                (1 << 28)
512 #define GTSENDV6                (1 << 27)
513 #define GTTCPHO_SHIFT           18
514 #define GTTCPHO_MAX             0x7fU
515 #define TX_LEN_MAX              0x3ffffU
516
517         __le32 opts2;
518 #define UDP_CS                  (1 << 31) /* Calculate UDP/IP checksum */
519 #define TCP_CS                  (1 << 30) /* Calculate TCP/IP checksum */
520 #define IPV4_CS                 (1 << 29) /* Calculate IPv4 checksum */
521 #define IPV6_CS                 (1 << 28) /* Calculate IPv6 checksum */
522 #define MSS_SHIFT               17
523 #define MSS_MAX                 0x7ffU
524 #define TCPHO_SHIFT             17
525 #define TCPHO_MAX               0x7ffU
526 #define TX_VLAN_TAG                     (1 << 16)
527 };
528
529 struct r8152;
530
531 struct rx_agg {
532         struct list_head list;
533         struct urb *urb;
534         struct r8152 *context;
535         void *buffer;
536         void *head;
537 };
538
539 struct tx_agg {
540         struct list_head list;
541         struct urb *urb;
542         struct r8152 *context;
543         void *buffer;
544         void *head;
545         u32 skb_num;
546         u32 skb_len;
547 };
548
549 struct r8152 {
550         unsigned long flags;
551         struct usb_device *udev;
552         struct tasklet_struct tl;
553         struct usb_interface *intf;
554         struct net_device *netdev;
555         struct urb *intr_urb;
556         struct tx_agg tx_info[RTL8152_MAX_TX];
557         struct rx_agg rx_info[RTL8152_MAX_RX];
558         struct list_head rx_done, tx_free;
559         struct sk_buff_head tx_queue;
560         spinlock_t rx_lock, tx_lock;
561         struct delayed_work schedule;
562         struct mii_if_info mii;
563         struct mutex control;   /* use for hw setting */
564
565         struct rtl_ops {
566                 void (*init)(struct r8152 *);
567                 int (*enable)(struct r8152 *);
568                 void (*disable)(struct r8152 *);
569                 void (*up)(struct r8152 *);
570                 void (*down)(struct r8152 *);
571                 void (*unload)(struct r8152 *);
572                 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
573                 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
574         } rtl_ops;
575
576         int intr_interval;
577         u32 saved_wolopts;
578         u32 msg_enable;
579         u32 tx_qlen;
580         u16 ocp_base;
581         u8 *intr_buff;
582         u8 version;
583         u8 speed;
584 };
585
586 enum rtl_version {
587         RTL_VER_UNKNOWN = 0,
588         RTL_VER_01,
589         RTL_VER_02,
590         RTL_VER_03,
591         RTL_VER_04,
592         RTL_VER_05,
593         RTL_VER_MAX
594 };
595
596 enum tx_csum_stat {
597         TX_CSUM_SUCCESS = 0,
598         TX_CSUM_TSO,
599         TX_CSUM_NONE
600 };
601
602 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
603  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
604  */
605 static const int multicast_filter_limit = 32;
606 static unsigned int agg_buf_sz = 16384;
607
608 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
609                                  VLAN_ETH_HLEN - VLAN_HLEN)
610
611 static
612 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
613 {
614         int ret;
615         void *tmp;
616
617         tmp = kmalloc(size, GFP_KERNEL);
618         if (!tmp)
619                 return -ENOMEM;
620
621         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
622                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
623                               value, index, tmp, size, 500);
624
625         memcpy(data, tmp, size);
626         kfree(tmp);
627
628         return ret;
629 }
630
631 static
632 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
633 {
634         int ret;
635         void *tmp;
636
637         tmp = kmemdup(data, size, GFP_KERNEL);
638         if (!tmp)
639                 return -ENOMEM;
640
641         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
642                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
643                               value, index, tmp, size, 500);
644
645         kfree(tmp);
646
647         return ret;
648 }
649
650 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
651                             void *data, u16 type)
652 {
653         u16 limit = 64;
654         int ret = 0;
655
656         if (test_bit(RTL8152_UNPLUG, &tp->flags))
657                 return -ENODEV;
658
659         /* both size and indix must be 4 bytes align */
660         if ((size & 3) || !size || (index & 3) || !data)
661                 return -EPERM;
662
663         if ((u32)index + (u32)size > 0xffff)
664                 return -EPERM;
665
666         while (size) {
667                 if (size > limit) {
668                         ret = get_registers(tp, index, type, limit, data);
669                         if (ret < 0)
670                                 break;
671
672                         index += limit;
673                         data += limit;
674                         size -= limit;
675                 } else {
676                         ret = get_registers(tp, index, type, size, data);
677                         if (ret < 0)
678                                 break;
679
680                         index += size;
681                         data += size;
682                         size = 0;
683                         break;
684                 }
685         }
686
687         if (ret == -ENODEV)
688                 set_bit(RTL8152_UNPLUG, &tp->flags);
689
690         return ret;
691 }
692
693 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
694                              u16 size, void *data, u16 type)
695 {
696         int ret;
697         u16 byteen_start, byteen_end, byen;
698         u16 limit = 512;
699
700         if (test_bit(RTL8152_UNPLUG, &tp->flags))
701                 return -ENODEV;
702
703         /* both size and indix must be 4 bytes align */
704         if ((size & 3) || !size || (index & 3) || !data)
705                 return -EPERM;
706
707         if ((u32)index + (u32)size > 0xffff)
708                 return -EPERM;
709
710         byteen_start = byteen & BYTE_EN_START_MASK;
711         byteen_end = byteen & BYTE_EN_END_MASK;
712
713         byen = byteen_start | (byteen_start << 4);
714         ret = set_registers(tp, index, type | byen, 4, data);
715         if (ret < 0)
716                 goto error1;
717
718         index += 4;
719         data += 4;
720         size -= 4;
721
722         if (size) {
723                 size -= 4;
724
725                 while (size) {
726                         if (size > limit) {
727                                 ret = set_registers(tp, index,
728                                                     type | BYTE_EN_DWORD,
729                                                     limit, data);
730                                 if (ret < 0)
731                                         goto error1;
732
733                                 index += limit;
734                                 data += limit;
735                                 size -= limit;
736                         } else {
737                                 ret = set_registers(tp, index,
738                                                     type | BYTE_EN_DWORD,
739                                                     size, data);
740                                 if (ret < 0)
741                                         goto error1;
742
743                                 index += size;
744                                 data += size;
745                                 size = 0;
746                                 break;
747                         }
748                 }
749
750                 byen = byteen_end | (byteen_end >> 4);
751                 ret = set_registers(tp, index, type | byen, 4, data);
752                 if (ret < 0)
753                         goto error1;
754         }
755
756 error1:
757         if (ret == -ENODEV)
758                 set_bit(RTL8152_UNPLUG, &tp->flags);
759
760         return ret;
761 }
762
763 static inline
764 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
765 {
766         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
767 }
768
769 static inline
770 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
771 {
772         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
773 }
774
775 static inline
776 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
777 {
778         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
779 }
780
781 static inline
782 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
783 {
784         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
785 }
786
787 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
788 {
789         __le32 data;
790
791         generic_ocp_read(tp, index, sizeof(data), &data, type);
792
793         return __le32_to_cpu(data);
794 }
795
796 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
797 {
798         __le32 tmp = __cpu_to_le32(data);
799
800         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
801 }
802
803 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
804 {
805         u32 data;
806         __le32 tmp;
807         u8 shift = index & 2;
808
809         index &= ~3;
810
811         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
812
813         data = __le32_to_cpu(tmp);
814         data >>= (shift * 8);
815         data &= 0xffff;
816
817         return (u16)data;
818 }
819
820 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
821 {
822         u32 mask = 0xffff;
823         __le32 tmp;
824         u16 byen = BYTE_EN_WORD;
825         u8 shift = index & 2;
826
827         data &= mask;
828
829         if (index & 2) {
830                 byen <<= shift;
831                 mask <<= (shift * 8);
832                 data <<= (shift * 8);
833                 index &= ~3;
834         }
835
836         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
837
838         data |= __le32_to_cpu(tmp) & ~mask;
839         tmp = __cpu_to_le32(data);
840
841         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
842 }
843
844 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
845 {
846         u32 data;
847         __le32 tmp;
848         u8 shift = index & 3;
849
850         index &= ~3;
851
852         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
853
854         data = __le32_to_cpu(tmp);
855         data >>= (shift * 8);
856         data &= 0xff;
857
858         return (u8)data;
859 }
860
861 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
862 {
863         u32 mask = 0xff;
864         __le32 tmp;
865         u16 byen = BYTE_EN_BYTE;
866         u8 shift = index & 3;
867
868         data &= mask;
869
870         if (index & 3) {
871                 byen <<= shift;
872                 mask <<= (shift * 8);
873                 data <<= (shift * 8);
874                 index &= ~3;
875         }
876
877         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
878
879         data |= __le32_to_cpu(tmp) & ~mask;
880         tmp = __cpu_to_le32(data);
881
882         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
883 }
884
885 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
886 {
887         u16 ocp_base, ocp_index;
888
889         ocp_base = addr & 0xf000;
890         if (ocp_base != tp->ocp_base) {
891                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
892                 tp->ocp_base = ocp_base;
893         }
894
895         ocp_index = (addr & 0x0fff) | 0xb000;
896         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
897 }
898
899 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
900 {
901         u16 ocp_base, ocp_index;
902
903         ocp_base = addr & 0xf000;
904         if (ocp_base != tp->ocp_base) {
905                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
906                 tp->ocp_base = ocp_base;
907         }
908
909         ocp_index = (addr & 0x0fff) | 0xb000;
910         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
911 }
912
913 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
914 {
915         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
916 }
917
918 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
919 {
920         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
921 }
922
923 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
924 {
925         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
926         ocp_reg_write(tp, OCP_SRAM_DATA, data);
927 }
928
929 static u16 sram_read(struct r8152 *tp, u16 addr)
930 {
931         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
932         return ocp_reg_read(tp, OCP_SRAM_DATA);
933 }
934
935 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
936 {
937         struct r8152 *tp = netdev_priv(netdev);
938         int ret;
939
940         if (test_bit(RTL8152_UNPLUG, &tp->flags))
941                 return -ENODEV;
942
943         if (phy_id != R8152_PHY_ID)
944                 return -EINVAL;
945
946         ret = r8152_mdio_read(tp, reg);
947
948         return ret;
949 }
950
951 static
952 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
953 {
954         struct r8152 *tp = netdev_priv(netdev);
955
956         if (test_bit(RTL8152_UNPLUG, &tp->flags))
957                 return;
958
959         if (phy_id != R8152_PHY_ID)
960                 return;
961
962         r8152_mdio_write(tp, reg, val);
963 }
964
965 static int
966 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
967
968 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
969 {
970         struct r8152 *tp = netdev_priv(netdev);
971         struct sockaddr *addr = p;
972         int ret = -EADDRNOTAVAIL;
973
974         if (!is_valid_ether_addr(addr->sa_data))
975                 goto out1;
976
977         ret = usb_autopm_get_interface(tp->intf);
978         if (ret < 0)
979                 goto out1;
980
981         mutex_lock(&tp->control);
982
983         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
984
985         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
986         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
987         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
988
989         mutex_unlock(&tp->control);
990
991         usb_autopm_put_interface(tp->intf);
992 out1:
993         return ret;
994 }
995
996 static int set_ethernet_addr(struct r8152 *tp)
997 {
998         struct net_device *dev = tp->netdev;
999         struct sockaddr sa;
1000         int ret;
1001
1002         if (tp->version == RTL_VER_01)
1003                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1004         else
1005                 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1006
1007         if (ret < 0) {
1008                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1009         } else if (!is_valid_ether_addr(sa.sa_data)) {
1010                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1011                           sa.sa_data);
1012                 eth_hw_addr_random(dev);
1013                 ether_addr_copy(sa.sa_data, dev->dev_addr);
1014                 ret = rtl8152_set_mac_address(dev, &sa);
1015                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1016                            sa.sa_data);
1017         } else {
1018                 if (tp->version == RTL_VER_01)
1019                         ether_addr_copy(dev->dev_addr, sa.sa_data);
1020                 else
1021                         ret = rtl8152_set_mac_address(dev, &sa);
1022         }
1023
1024         return ret;
1025 }
1026
1027 static void read_bulk_callback(struct urb *urb)
1028 {
1029         struct net_device *netdev;
1030         int status = urb->status;
1031         struct rx_agg *agg;
1032         struct r8152 *tp;
1033
1034         agg = urb->context;
1035         if (!agg)
1036                 return;
1037
1038         tp = agg->context;
1039         if (!tp)
1040                 return;
1041
1042         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1043                 return;
1044
1045         if (!test_bit(WORK_ENABLE, &tp->flags))
1046                 return;
1047
1048         netdev = tp->netdev;
1049
1050         /* When link down, the driver would cancel all bulks. */
1051         /* This avoid the re-submitting bulk */
1052         if (!netif_carrier_ok(netdev))
1053                 return;
1054
1055         usb_mark_last_busy(tp->udev);
1056
1057         switch (status) {
1058         case 0:
1059                 if (urb->actual_length < ETH_ZLEN)
1060                         break;
1061
1062                 spin_lock(&tp->rx_lock);
1063                 list_add_tail(&agg->list, &tp->rx_done);
1064                 spin_unlock(&tp->rx_lock);
1065                 tasklet_schedule(&tp->tl);
1066                 return;
1067         case -ESHUTDOWN:
1068                 set_bit(RTL8152_UNPLUG, &tp->flags);
1069                 netif_device_detach(tp->netdev);
1070                 return;
1071         case -ENOENT:
1072                 return; /* the urb is in unlink state */
1073         case -ETIME:
1074                 if (net_ratelimit())
1075                         netdev_warn(netdev, "maybe reset is needed?\n");
1076                 break;
1077         default:
1078                 if (net_ratelimit())
1079                         netdev_warn(netdev, "Rx status %d\n", status);
1080                 break;
1081         }
1082
1083         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1084 }
1085
1086 static void write_bulk_callback(struct urb *urb)
1087 {
1088         struct net_device_stats *stats;
1089         struct net_device *netdev;
1090         struct tx_agg *agg;
1091         struct r8152 *tp;
1092         int status = urb->status;
1093
1094         agg = urb->context;
1095         if (!agg)
1096                 return;
1097
1098         tp = agg->context;
1099         if (!tp)
1100                 return;
1101
1102         netdev = tp->netdev;
1103         stats = &netdev->stats;
1104         if (status) {
1105                 if (net_ratelimit())
1106                         netdev_warn(netdev, "Tx status %d\n", status);
1107                 stats->tx_errors += agg->skb_num;
1108         } else {
1109                 stats->tx_packets += agg->skb_num;
1110                 stats->tx_bytes += agg->skb_len;
1111         }
1112
1113         spin_lock(&tp->tx_lock);
1114         list_add_tail(&agg->list, &tp->tx_free);
1115         spin_unlock(&tp->tx_lock);
1116
1117         usb_autopm_put_interface_async(tp->intf);
1118
1119         if (!netif_carrier_ok(netdev))
1120                 return;
1121
1122         if (!test_bit(WORK_ENABLE, &tp->flags))
1123                 return;
1124
1125         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1126                 return;
1127
1128         if (!skb_queue_empty(&tp->tx_queue))
1129                 tasklet_schedule(&tp->tl);
1130 }
1131
1132 static void intr_callback(struct urb *urb)
1133 {
1134         struct r8152 *tp;
1135         __le16 *d;
1136         int status = urb->status;
1137         int res;
1138
1139         tp = urb->context;
1140         if (!tp)
1141                 return;
1142
1143         if (!test_bit(WORK_ENABLE, &tp->flags))
1144                 return;
1145
1146         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1147                 return;
1148
1149         switch (status) {
1150         case 0:                 /* success */
1151                 break;
1152         case -ECONNRESET:       /* unlink */
1153         case -ESHUTDOWN:
1154                 netif_device_detach(tp->netdev);
1155         case -ENOENT:
1156         case -EPROTO:
1157                 netif_info(tp, intr, tp->netdev,
1158                            "Stop submitting intr, status %d\n", status);
1159                 return;
1160         case -EOVERFLOW:
1161                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1162                 goto resubmit;
1163         /* -EPIPE:  should clear the halt */
1164         default:
1165                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1166                 goto resubmit;
1167         }
1168
1169         d = urb->transfer_buffer;
1170         if (INTR_LINK & __le16_to_cpu(d[0])) {
1171                 if (!(tp->speed & LINK_STATUS)) {
1172                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1173                         schedule_delayed_work(&tp->schedule, 0);
1174                 }
1175         } else {
1176                 if (tp->speed & LINK_STATUS) {
1177                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1178                         schedule_delayed_work(&tp->schedule, 0);
1179                 }
1180         }
1181
1182 resubmit:
1183         res = usb_submit_urb(urb, GFP_ATOMIC);
1184         if (res == -ENODEV) {
1185                 set_bit(RTL8152_UNPLUG, &tp->flags);
1186                 netif_device_detach(tp->netdev);
1187         } else if (res) {
1188                 netif_err(tp, intr, tp->netdev,
1189                           "can't resubmit intr, status %d\n", res);
1190         }
1191 }
1192
1193 static inline void *rx_agg_align(void *data)
1194 {
1195         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1196 }
1197
1198 static inline void *tx_agg_align(void *data)
1199 {
1200         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1201 }
1202
1203 static void free_all_mem(struct r8152 *tp)
1204 {
1205         int i;
1206
1207         for (i = 0; i < RTL8152_MAX_RX; i++) {
1208                 usb_free_urb(tp->rx_info[i].urb);
1209                 tp->rx_info[i].urb = NULL;
1210
1211                 kfree(tp->rx_info[i].buffer);
1212                 tp->rx_info[i].buffer = NULL;
1213                 tp->rx_info[i].head = NULL;
1214         }
1215
1216         for (i = 0; i < RTL8152_MAX_TX; i++) {
1217                 usb_free_urb(tp->tx_info[i].urb);
1218                 tp->tx_info[i].urb = NULL;
1219
1220                 kfree(tp->tx_info[i].buffer);
1221                 tp->tx_info[i].buffer = NULL;
1222                 tp->tx_info[i].head = NULL;
1223         }
1224
1225         usb_free_urb(tp->intr_urb);
1226         tp->intr_urb = NULL;
1227
1228         kfree(tp->intr_buff);
1229         tp->intr_buff = NULL;
1230 }
1231
1232 static int alloc_all_mem(struct r8152 *tp)
1233 {
1234         struct net_device *netdev = tp->netdev;
1235         struct usb_interface *intf = tp->intf;
1236         struct usb_host_interface *alt = intf->cur_altsetting;
1237         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1238         struct urb *urb;
1239         int node, i;
1240         u8 *buf;
1241
1242         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1243
1244         spin_lock_init(&tp->rx_lock);
1245         spin_lock_init(&tp->tx_lock);
1246         INIT_LIST_HEAD(&tp->tx_free);
1247         skb_queue_head_init(&tp->tx_queue);
1248
1249         for (i = 0; i < RTL8152_MAX_RX; i++) {
1250                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1251                 if (!buf)
1252                         goto err1;
1253
1254                 if (buf != rx_agg_align(buf)) {
1255                         kfree(buf);
1256                         buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1257                                            node);
1258                         if (!buf)
1259                                 goto err1;
1260                 }
1261
1262                 urb = usb_alloc_urb(0, GFP_KERNEL);
1263                 if (!urb) {
1264                         kfree(buf);
1265                         goto err1;
1266                 }
1267
1268                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1269                 tp->rx_info[i].context = tp;
1270                 tp->rx_info[i].urb = urb;
1271                 tp->rx_info[i].buffer = buf;
1272                 tp->rx_info[i].head = rx_agg_align(buf);
1273         }
1274
1275         for (i = 0; i < RTL8152_MAX_TX; i++) {
1276                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1277                 if (!buf)
1278                         goto err1;
1279
1280                 if (buf != tx_agg_align(buf)) {
1281                         kfree(buf);
1282                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1283                                            node);
1284                         if (!buf)
1285                                 goto err1;
1286                 }
1287
1288                 urb = usb_alloc_urb(0, GFP_KERNEL);
1289                 if (!urb) {
1290                         kfree(buf);
1291                         goto err1;
1292                 }
1293
1294                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1295                 tp->tx_info[i].context = tp;
1296                 tp->tx_info[i].urb = urb;
1297                 tp->tx_info[i].buffer = buf;
1298                 tp->tx_info[i].head = tx_agg_align(buf);
1299
1300                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1301         }
1302
1303         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1304         if (!tp->intr_urb)
1305                 goto err1;
1306
1307         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1308         if (!tp->intr_buff)
1309                 goto err1;
1310
1311         tp->intr_interval = (int)ep_intr->desc.bInterval;
1312         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1313                          tp->intr_buff, INTBUFSIZE, intr_callback,
1314                          tp, tp->intr_interval);
1315
1316         return 0;
1317
1318 err1:
1319         free_all_mem(tp);
1320         return -ENOMEM;
1321 }
1322
1323 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1324 {
1325         struct tx_agg *agg = NULL;
1326         unsigned long flags;
1327
1328         if (list_empty(&tp->tx_free))
1329                 return NULL;
1330
1331         spin_lock_irqsave(&tp->tx_lock, flags);
1332         if (!list_empty(&tp->tx_free)) {
1333                 struct list_head *cursor;
1334
1335                 cursor = tp->tx_free.next;
1336                 list_del_init(cursor);
1337                 agg = list_entry(cursor, struct tx_agg, list);
1338         }
1339         spin_unlock_irqrestore(&tp->tx_lock, flags);
1340
1341         return agg;
1342 }
1343
1344 static inline __be16 get_protocol(struct sk_buff *skb)
1345 {
1346         __be16 protocol;
1347
1348         if (skb->protocol == htons(ETH_P_8021Q))
1349                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1350         else
1351                 protocol = skb->protocol;
1352
1353         return protocol;
1354 }
1355
1356 /* r8152_csum_workaround()
1357  * The hw limites the value the transport offset. When the offset is out of the
1358  * range, calculate the checksum by sw.
1359  */
1360 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1361                                   struct sk_buff_head *list)
1362 {
1363         if (skb_shinfo(skb)->gso_size) {
1364                 netdev_features_t features = tp->netdev->features;
1365                 struct sk_buff_head seg_list;
1366                 struct sk_buff *segs, *nskb;
1367
1368                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1369                 segs = skb_gso_segment(skb, features);
1370                 if (IS_ERR(segs) || !segs)
1371                         goto drop;
1372
1373                 __skb_queue_head_init(&seg_list);
1374
1375                 do {
1376                         nskb = segs;
1377                         segs = segs->next;
1378                         nskb->next = NULL;
1379                         __skb_queue_tail(&seg_list, nskb);
1380                 } while (segs);
1381
1382                 skb_queue_splice(&seg_list, list);
1383                 dev_kfree_skb(skb);
1384         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1385                 if (skb_checksum_help(skb) < 0)
1386                         goto drop;
1387
1388                 __skb_queue_head(list, skb);
1389         } else {
1390                 struct net_device_stats *stats;
1391
1392 drop:
1393                 stats = &tp->netdev->stats;
1394                 stats->tx_dropped++;
1395                 dev_kfree_skb(skb);
1396         }
1397 }
1398
1399 /* msdn_giant_send_check()
1400  * According to the document of microsoft, the TCP Pseudo Header excludes the
1401  * packet length for IPv6 TCP large packets.
1402  */
1403 static int msdn_giant_send_check(struct sk_buff *skb)
1404 {
1405         const struct ipv6hdr *ipv6h;
1406         struct tcphdr *th;
1407         int ret;
1408
1409         ret = skb_cow_head(skb, 0);
1410         if (ret)
1411                 return ret;
1412
1413         ipv6h = ipv6_hdr(skb);
1414         th = tcp_hdr(skb);
1415
1416         th->check = 0;
1417         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1418
1419         return ret;
1420 }
1421
1422 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1423 {
1424         if (skb_vlan_tag_present(skb)) {
1425                 u32 opts2;
1426
1427                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1428                 desc->opts2 |= cpu_to_le32(opts2);
1429         }
1430 }
1431
1432 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1433 {
1434         u32 opts2 = le32_to_cpu(desc->opts2);
1435
1436         if (opts2 & RX_VLAN_TAG)
1437                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1438                                        swab16(opts2 & 0xffff));
1439 }
1440
1441 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1442                          struct sk_buff *skb, u32 len, u32 transport_offset)
1443 {
1444         u32 mss = skb_shinfo(skb)->gso_size;
1445         u32 opts1, opts2 = 0;
1446         int ret = TX_CSUM_SUCCESS;
1447
1448         WARN_ON_ONCE(len > TX_LEN_MAX);
1449
1450         opts1 = len | TX_FS | TX_LS;
1451
1452         if (mss) {
1453                 if (transport_offset > GTTCPHO_MAX) {
1454                         netif_warn(tp, tx_err, tp->netdev,
1455                                    "Invalid transport offset 0x%x for TSO\n",
1456                                    transport_offset);
1457                         ret = TX_CSUM_TSO;
1458                         goto unavailable;
1459                 }
1460
1461                 switch (get_protocol(skb)) {
1462                 case htons(ETH_P_IP):
1463                         opts1 |= GTSENDV4;
1464                         break;
1465
1466                 case htons(ETH_P_IPV6):
1467                         if (msdn_giant_send_check(skb)) {
1468                                 ret = TX_CSUM_TSO;
1469                                 goto unavailable;
1470                         }
1471                         opts1 |= GTSENDV6;
1472                         break;
1473
1474                 default:
1475                         WARN_ON_ONCE(1);
1476                         break;
1477                 }
1478
1479                 opts1 |= transport_offset << GTTCPHO_SHIFT;
1480                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1481         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1482                 u8 ip_protocol;
1483
1484                 if (transport_offset > TCPHO_MAX) {
1485                         netif_warn(tp, tx_err, tp->netdev,
1486                                    "Invalid transport offset 0x%x\n",
1487                                    transport_offset);
1488                         ret = TX_CSUM_NONE;
1489                         goto unavailable;
1490                 }
1491
1492                 switch (get_protocol(skb)) {
1493                 case htons(ETH_P_IP):
1494                         opts2 |= IPV4_CS;
1495                         ip_protocol = ip_hdr(skb)->protocol;
1496                         break;
1497
1498                 case htons(ETH_P_IPV6):
1499                         opts2 |= IPV6_CS;
1500                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1501                         break;
1502
1503                 default:
1504                         ip_protocol = IPPROTO_RAW;
1505                         break;
1506                 }
1507
1508                 if (ip_protocol == IPPROTO_TCP)
1509                         opts2 |= TCP_CS;
1510                 else if (ip_protocol == IPPROTO_UDP)
1511                         opts2 |= UDP_CS;
1512                 else
1513                         WARN_ON_ONCE(1);
1514
1515                 opts2 |= transport_offset << TCPHO_SHIFT;
1516         }
1517
1518         desc->opts2 = cpu_to_le32(opts2);
1519         desc->opts1 = cpu_to_le32(opts1);
1520
1521 unavailable:
1522         return ret;
1523 }
1524
1525 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1526 {
1527         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1528         int remain, ret;
1529         u8 *tx_data;
1530
1531         __skb_queue_head_init(&skb_head);
1532         spin_lock(&tx_queue->lock);
1533         skb_queue_splice_init(tx_queue, &skb_head);
1534         spin_unlock(&tx_queue->lock);
1535
1536         tx_data = agg->head;
1537         agg->skb_num = 0;
1538         agg->skb_len = 0;
1539         remain = agg_buf_sz;
1540
1541         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1542                 struct tx_desc *tx_desc;
1543                 struct sk_buff *skb;
1544                 unsigned int len;
1545                 u32 offset;
1546
1547                 skb = __skb_dequeue(&skb_head);
1548                 if (!skb)
1549                         break;
1550
1551                 len = skb->len + sizeof(*tx_desc);
1552
1553                 if (len > remain) {
1554                         __skb_queue_head(&skb_head, skb);
1555                         break;
1556                 }
1557
1558                 tx_data = tx_agg_align(tx_data);
1559                 tx_desc = (struct tx_desc *)tx_data;
1560
1561                 offset = (u32)skb_transport_offset(skb);
1562
1563                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1564                         r8152_csum_workaround(tp, skb, &skb_head);
1565                         continue;
1566                 }
1567
1568                 rtl_tx_vlan_tag(tx_desc, skb);
1569
1570                 tx_data += sizeof(*tx_desc);
1571
1572                 len = skb->len;
1573                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1574                         struct net_device_stats *stats = &tp->netdev->stats;
1575
1576                         stats->tx_dropped++;
1577                         dev_kfree_skb_any(skb);
1578                         tx_data -= sizeof(*tx_desc);
1579                         continue;
1580                 }
1581
1582                 tx_data += len;
1583                 agg->skb_len += len;
1584                 agg->skb_num++;
1585
1586                 dev_kfree_skb_any(skb);
1587
1588                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1589         }
1590
1591         if (!skb_queue_empty(&skb_head)) {
1592                 spin_lock(&tx_queue->lock);
1593                 skb_queue_splice(&skb_head, tx_queue);
1594                 spin_unlock(&tx_queue->lock);
1595         }
1596
1597         netif_tx_lock(tp->netdev);
1598
1599         if (netif_queue_stopped(tp->netdev) &&
1600             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1601                 netif_wake_queue(tp->netdev);
1602
1603         netif_tx_unlock(tp->netdev);
1604
1605         ret = usb_autopm_get_interface_async(tp->intf);
1606         if (ret < 0)
1607                 goto out_tx_fill;
1608
1609         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1610                           agg->head, (int)(tx_data - (u8 *)agg->head),
1611                           (usb_complete_t)write_bulk_callback, agg);
1612
1613         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1614         if (ret < 0)
1615                 usb_autopm_put_interface_async(tp->intf);
1616
1617 out_tx_fill:
1618         return ret;
1619 }
1620
1621 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1622 {
1623         u8 checksum = CHECKSUM_NONE;
1624         u32 opts2, opts3;
1625
1626         if (tp->version == RTL_VER_01)
1627                 goto return_result;
1628
1629         opts2 = le32_to_cpu(rx_desc->opts2);
1630         opts3 = le32_to_cpu(rx_desc->opts3);
1631
1632         if (opts2 & RD_IPV4_CS) {
1633                 if (opts3 & IPF)
1634                         checksum = CHECKSUM_NONE;
1635                 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1636                         checksum = CHECKSUM_NONE;
1637                 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1638                         checksum = CHECKSUM_NONE;
1639                 else
1640                         checksum = CHECKSUM_UNNECESSARY;
1641         } else if (RD_IPV6_CS) {
1642                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1643                         checksum = CHECKSUM_UNNECESSARY;
1644                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1645                         checksum = CHECKSUM_UNNECESSARY;
1646         }
1647
1648 return_result:
1649         return checksum;
1650 }
1651
1652 static void rx_bottom(struct r8152 *tp)
1653 {
1654         unsigned long flags;
1655         struct list_head *cursor, *next, rx_queue;
1656
1657         if (list_empty(&tp->rx_done))
1658                 return;
1659
1660         INIT_LIST_HEAD(&rx_queue);
1661         spin_lock_irqsave(&tp->rx_lock, flags);
1662         list_splice_init(&tp->rx_done, &rx_queue);
1663         spin_unlock_irqrestore(&tp->rx_lock, flags);
1664
1665         list_for_each_safe(cursor, next, &rx_queue) {
1666                 struct rx_desc *rx_desc;
1667                 struct rx_agg *agg;
1668                 int len_used = 0;
1669                 struct urb *urb;
1670                 u8 *rx_data;
1671
1672                 list_del_init(cursor);
1673
1674                 agg = list_entry(cursor, struct rx_agg, list);
1675                 urb = agg->urb;
1676                 if (urb->actual_length < ETH_ZLEN)
1677                         goto submit;
1678
1679                 rx_desc = agg->head;
1680                 rx_data = agg->head;
1681                 len_used += sizeof(struct rx_desc);
1682
1683                 while (urb->actual_length > len_used) {
1684                         struct net_device *netdev = tp->netdev;
1685                         struct net_device_stats *stats = &netdev->stats;
1686                         unsigned int pkt_len;
1687                         struct sk_buff *skb;
1688
1689                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1690                         if (pkt_len < ETH_ZLEN)
1691                                 break;
1692
1693                         len_used += pkt_len;
1694                         if (urb->actual_length < len_used)
1695                                 break;
1696
1697                         pkt_len -= CRC_SIZE;
1698                         rx_data += sizeof(struct rx_desc);
1699
1700                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1701                         if (!skb) {
1702                                 stats->rx_dropped++;
1703                                 goto find_next_rx;
1704                         }
1705
1706                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1707                         memcpy(skb->data, rx_data, pkt_len);
1708                         skb_put(skb, pkt_len);
1709                         skb->protocol = eth_type_trans(skb, netdev);
1710                         rtl_rx_vlan_tag(rx_desc, skb);
1711                         netif_receive_skb(skb);
1712                         stats->rx_packets++;
1713                         stats->rx_bytes += pkt_len;
1714
1715 find_next_rx:
1716                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1717                         rx_desc = (struct rx_desc *)rx_data;
1718                         len_used = (int)(rx_data - (u8 *)agg->head);
1719                         len_used += sizeof(struct rx_desc);
1720                 }
1721
1722 submit:
1723                 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1724         }
1725 }
1726
1727 static void tx_bottom(struct r8152 *tp)
1728 {
1729         int res;
1730
1731         do {
1732                 struct tx_agg *agg;
1733
1734                 if (skb_queue_empty(&tp->tx_queue))
1735                         break;
1736
1737                 agg = r8152_get_tx_agg(tp);
1738                 if (!agg)
1739                         break;
1740
1741                 res = r8152_tx_agg_fill(tp, agg);
1742                 if (res) {
1743                         struct net_device *netdev = tp->netdev;
1744
1745                         if (res == -ENODEV) {
1746                                 set_bit(RTL8152_UNPLUG, &tp->flags);
1747                                 netif_device_detach(netdev);
1748                         } else {
1749                                 struct net_device_stats *stats = &netdev->stats;
1750                                 unsigned long flags;
1751
1752                                 netif_warn(tp, tx_err, netdev,
1753                                            "failed tx_urb %d\n", res);
1754                                 stats->tx_dropped += agg->skb_num;
1755
1756                                 spin_lock_irqsave(&tp->tx_lock, flags);
1757                                 list_add_tail(&agg->list, &tp->tx_free);
1758                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1759                         }
1760                 }
1761         } while (res == 0);
1762 }
1763
1764 static void bottom_half(unsigned long data)
1765 {
1766         struct r8152 *tp;
1767
1768         tp = (struct r8152 *)data;
1769
1770         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1771                 return;
1772
1773         if (!test_bit(WORK_ENABLE, &tp->flags))
1774                 return;
1775
1776         /* When link down, the driver would cancel all bulks. */
1777         /* This avoid the re-submitting bulk */
1778         if (!netif_carrier_ok(tp->netdev))
1779                 return;
1780
1781         clear_bit(SCHEDULE_TASKLET, &tp->flags);
1782
1783         rx_bottom(tp);
1784         tx_bottom(tp);
1785 }
1786
1787 static
1788 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1789 {
1790         int ret;
1791
1792         /* The rx would be stopped, so skip submitting */
1793         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1794             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1795                 return 0;
1796
1797         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1798                           agg->head, agg_buf_sz,
1799                           (usb_complete_t)read_bulk_callback, agg);
1800
1801         ret = usb_submit_urb(agg->urb, mem_flags);
1802         if (ret == -ENODEV) {
1803                 set_bit(RTL8152_UNPLUG, &tp->flags);
1804                 netif_device_detach(tp->netdev);
1805         } else if (ret) {
1806                 struct urb *urb = agg->urb;
1807                 unsigned long flags;
1808
1809                 urb->actual_length = 0;
1810                 spin_lock_irqsave(&tp->rx_lock, flags);
1811                 list_add_tail(&agg->list, &tp->rx_done);
1812                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1813                 tasklet_schedule(&tp->tl);
1814         }
1815
1816         return ret;
1817 }
1818
1819 static void rtl_drop_queued_tx(struct r8152 *tp)
1820 {
1821         struct net_device_stats *stats = &tp->netdev->stats;
1822         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1823         struct sk_buff *skb;
1824
1825         if (skb_queue_empty(tx_queue))
1826                 return;
1827
1828         __skb_queue_head_init(&skb_head);
1829         spin_lock_bh(&tx_queue->lock);
1830         skb_queue_splice_init(tx_queue, &skb_head);
1831         spin_unlock_bh(&tx_queue->lock);
1832
1833         while ((skb = __skb_dequeue(&skb_head))) {
1834                 dev_kfree_skb(skb);
1835                 stats->tx_dropped++;
1836         }
1837 }
1838
1839 static void rtl8152_tx_timeout(struct net_device *netdev)
1840 {
1841         struct r8152 *tp = netdev_priv(netdev);
1842         int i;
1843
1844         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1845         for (i = 0; i < RTL8152_MAX_TX; i++)
1846                 usb_unlink_urb(tp->tx_info[i].urb);
1847 }
1848
1849 static void rtl8152_set_rx_mode(struct net_device *netdev)
1850 {
1851         struct r8152 *tp = netdev_priv(netdev);
1852
1853         if (tp->speed & LINK_STATUS) {
1854                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1855                 schedule_delayed_work(&tp->schedule, 0);
1856         }
1857 }
1858
1859 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1860 {
1861         struct r8152 *tp = netdev_priv(netdev);
1862         u32 mc_filter[2];       /* Multicast hash filter */
1863         __le32 tmp[2];
1864         u32 ocp_data;
1865
1866         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1867         netif_stop_queue(netdev);
1868         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1869         ocp_data &= ~RCR_ACPT_ALL;
1870         ocp_data |= RCR_AB | RCR_APM;
1871
1872         if (netdev->flags & IFF_PROMISC) {
1873                 /* Unconditionally log net taps. */
1874                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1875                 ocp_data |= RCR_AM | RCR_AAP;
1876                 mc_filter[1] = 0xffffffff;
1877                 mc_filter[0] = 0xffffffff;
1878         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1879                    (netdev->flags & IFF_ALLMULTI)) {
1880                 /* Too many to filter perfectly -- accept all multicasts. */
1881                 ocp_data |= RCR_AM;
1882                 mc_filter[1] = 0xffffffff;
1883                 mc_filter[0] = 0xffffffff;
1884         } else {
1885                 struct netdev_hw_addr *ha;
1886
1887                 mc_filter[1] = 0;
1888                 mc_filter[0] = 0;
1889                 netdev_for_each_mc_addr(ha, netdev) {
1890                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1891
1892                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1893                         ocp_data |= RCR_AM;
1894                 }
1895         }
1896
1897         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1898         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1899
1900         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1901         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1902         netif_wake_queue(netdev);
1903 }
1904
1905 static netdev_features_t
1906 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
1907                        netdev_features_t features)
1908 {
1909         u32 mss = skb_shinfo(skb)->gso_size;
1910         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
1911         int offset = skb_transport_offset(skb);
1912
1913         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
1914                 features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
1915         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
1916                 features &= ~NETIF_F_GSO_MASK;
1917
1918         return features;
1919 }
1920
1921 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1922                                       struct net_device *netdev)
1923 {
1924         struct r8152 *tp = netdev_priv(netdev);
1925
1926         skb_tx_timestamp(skb);
1927
1928         skb_queue_tail(&tp->tx_queue, skb);
1929
1930         if (!list_empty(&tp->tx_free)) {
1931                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1932                         set_bit(SCHEDULE_TASKLET, &tp->flags);
1933                         schedule_delayed_work(&tp->schedule, 0);
1934                 } else {
1935                         usb_mark_last_busy(tp->udev);
1936                         tasklet_schedule(&tp->tl);
1937                 }
1938         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
1939                 netif_stop_queue(netdev);
1940         }
1941
1942         return NETDEV_TX_OK;
1943 }
1944
1945 static void r8152b_reset_packet_filter(struct r8152 *tp)
1946 {
1947         u32     ocp_data;
1948
1949         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1950         ocp_data &= ~FMC_FCR_MCU_EN;
1951         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1952         ocp_data |= FMC_FCR_MCU_EN;
1953         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1954 }
1955
1956 static void rtl8152_nic_reset(struct r8152 *tp)
1957 {
1958         int     i;
1959
1960         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1961
1962         for (i = 0; i < 1000; i++) {
1963                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1964                         break;
1965                 usleep_range(100, 400);
1966         }
1967 }
1968
1969 static void set_tx_qlen(struct r8152 *tp)
1970 {
1971         struct net_device *netdev = tp->netdev;
1972
1973         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1974                                     sizeof(struct tx_desc));
1975 }
1976
1977 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1978 {
1979         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1980 }
1981
1982 static void rtl_set_eee_plus(struct r8152 *tp)
1983 {
1984         u32 ocp_data;
1985         u8 speed;
1986
1987         speed = rtl8152_get_speed(tp);
1988         if (speed & _10bps) {
1989                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1990                 ocp_data |= EEEP_CR_EEEP_TX;
1991                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1992         } else {
1993                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1994                 ocp_data &= ~EEEP_CR_EEEP_TX;
1995                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1996         }
1997 }
1998
1999 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2000 {
2001         u32 ocp_data;
2002
2003         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2004         if (enable)
2005                 ocp_data |= RXDY_GATED_EN;
2006         else
2007                 ocp_data &= ~RXDY_GATED_EN;
2008         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2009 }
2010
2011 static int rtl_start_rx(struct r8152 *tp)
2012 {
2013         int i, ret = 0;
2014
2015         INIT_LIST_HEAD(&tp->rx_done);
2016         for (i = 0; i < RTL8152_MAX_RX; i++) {
2017                 INIT_LIST_HEAD(&tp->rx_info[i].list);
2018                 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2019                 if (ret)
2020                         break;
2021         }
2022
2023         if (ret && ++i < RTL8152_MAX_RX) {
2024                 struct list_head rx_queue;
2025                 unsigned long flags;
2026
2027                 INIT_LIST_HEAD(&rx_queue);
2028
2029                 do {
2030                         struct rx_agg *agg = &tp->rx_info[i++];
2031                         struct urb *urb = agg->urb;
2032
2033                         urb->actual_length = 0;
2034                         list_add_tail(&agg->list, &rx_queue);
2035                 } while (i < RTL8152_MAX_RX);
2036
2037                 spin_lock_irqsave(&tp->rx_lock, flags);
2038                 list_splice_tail(&rx_queue, &tp->rx_done);
2039                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2040         }
2041
2042         return ret;
2043 }
2044
2045 static int rtl_stop_rx(struct r8152 *tp)
2046 {
2047         int i;
2048
2049         for (i = 0; i < RTL8152_MAX_RX; i++)
2050                 usb_kill_urb(tp->rx_info[i].urb);
2051
2052         return 0;
2053 }
2054
2055 static int rtl_enable(struct r8152 *tp)
2056 {
2057         u32 ocp_data;
2058
2059         r8152b_reset_packet_filter(tp);
2060
2061         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2062         ocp_data |= CR_RE | CR_TE;
2063         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2064
2065         rxdy_gated_en(tp, false);
2066
2067         return 0;
2068 }
2069
2070 static int rtl8152_enable(struct r8152 *tp)
2071 {
2072         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2073                 return -ENODEV;
2074
2075         set_tx_qlen(tp);
2076         rtl_set_eee_plus(tp);
2077
2078         return rtl_enable(tp);
2079 }
2080
2081 static void r8153_set_rx_agg(struct r8152 *tp)
2082 {
2083         u8 speed;
2084
2085         speed = rtl8152_get_speed(tp);
2086         if (speed & _1000bps) {
2087                 if (tp->udev->speed == USB_SPEED_SUPER) {
2088                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2089                                         RX_THR_SUPPER);
2090                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2091                                         EARLY_AGG_SUPPER);
2092                 } else {
2093                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2094                                         RX_THR_HIGH);
2095                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2096                                         EARLY_AGG_HIGH);
2097                 }
2098         } else {
2099                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2100                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2101                                 EARLY_AGG_SLOW);
2102         }
2103 }
2104
2105 static int rtl8153_enable(struct r8152 *tp)
2106 {
2107         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2108                 return -ENODEV;
2109
2110         set_tx_qlen(tp);
2111         rtl_set_eee_plus(tp);
2112         r8153_set_rx_agg(tp);
2113
2114         return rtl_enable(tp);
2115 }
2116
2117 static void rtl_disable(struct r8152 *tp)
2118 {
2119         u32 ocp_data;
2120         int i;
2121
2122         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2123                 rtl_drop_queued_tx(tp);
2124                 return;
2125         }
2126
2127         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2128         ocp_data &= ~RCR_ACPT_ALL;
2129         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2130
2131         rtl_drop_queued_tx(tp);
2132
2133         for (i = 0; i < RTL8152_MAX_TX; i++)
2134                 usb_kill_urb(tp->tx_info[i].urb);
2135
2136         rxdy_gated_en(tp, true);
2137
2138         for (i = 0; i < 1000; i++) {
2139                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2140                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2141                         break;
2142                 usleep_range(1000, 2000);
2143         }
2144
2145         for (i = 0; i < 1000; i++) {
2146                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2147                         break;
2148                 usleep_range(1000, 2000);
2149         }
2150
2151         rtl_stop_rx(tp);
2152
2153         rtl8152_nic_reset(tp);
2154 }
2155
2156 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2157 {
2158         u32 ocp_data;
2159
2160         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2161         if (enable)
2162                 ocp_data |= POWER_CUT;
2163         else
2164                 ocp_data &= ~POWER_CUT;
2165         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2166
2167         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2168         ocp_data &= ~RESUME_INDICATE;
2169         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2170 }
2171
2172 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2173 {
2174         u32 ocp_data;
2175
2176         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2177         if (enable)
2178                 ocp_data |= CPCR_RX_VLAN;
2179         else
2180                 ocp_data &= ~CPCR_RX_VLAN;
2181         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2182 }
2183
2184 static int rtl8152_set_features(struct net_device *dev,
2185                                 netdev_features_t features)
2186 {
2187         netdev_features_t changed = features ^ dev->features;
2188         struct r8152 *tp = netdev_priv(dev);
2189         int ret;
2190
2191         ret = usb_autopm_get_interface(tp->intf);
2192         if (ret < 0)
2193                 goto out;
2194
2195         mutex_lock(&tp->control);
2196
2197         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2198                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2199                         rtl_rx_vlan_en(tp, true);
2200                 else
2201                         rtl_rx_vlan_en(tp, false);
2202         }
2203
2204         mutex_unlock(&tp->control);
2205
2206         usb_autopm_put_interface(tp->intf);
2207
2208 out:
2209         return ret;
2210 }
2211
2212 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2213
2214 static u32 __rtl_get_wol(struct r8152 *tp)
2215 {
2216         u32 ocp_data;
2217         u32 wolopts = 0;
2218
2219         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2220         if (!(ocp_data & LAN_WAKE_EN))
2221                 return 0;
2222
2223         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2224         if (ocp_data & LINK_ON_WAKE_EN)
2225                 wolopts |= WAKE_PHY;
2226
2227         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2228         if (ocp_data & UWF_EN)
2229                 wolopts |= WAKE_UCAST;
2230         if (ocp_data & BWF_EN)
2231                 wolopts |= WAKE_BCAST;
2232         if (ocp_data & MWF_EN)
2233                 wolopts |= WAKE_MCAST;
2234
2235         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2236         if (ocp_data & MAGIC_EN)
2237                 wolopts |= WAKE_MAGIC;
2238
2239         return wolopts;
2240 }
2241
2242 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2243 {
2244         u32 ocp_data;
2245
2246         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2247
2248         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2249         ocp_data &= ~LINK_ON_WAKE_EN;
2250         if (wolopts & WAKE_PHY)
2251                 ocp_data |= LINK_ON_WAKE_EN;
2252         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2253
2254         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2255         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2256         if (wolopts & WAKE_UCAST)
2257                 ocp_data |= UWF_EN;
2258         if (wolopts & WAKE_BCAST)
2259                 ocp_data |= BWF_EN;
2260         if (wolopts & WAKE_MCAST)
2261                 ocp_data |= MWF_EN;
2262         if (wolopts & WAKE_ANY)
2263                 ocp_data |= LAN_WAKE_EN;
2264         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2265
2266         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2267
2268         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2269         ocp_data &= ~MAGIC_EN;
2270         if (wolopts & WAKE_MAGIC)
2271                 ocp_data |= MAGIC_EN;
2272         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2273
2274         if (wolopts & WAKE_ANY)
2275                 device_set_wakeup_enable(&tp->udev->dev, true);
2276         else
2277                 device_set_wakeup_enable(&tp->udev->dev, false);
2278 }
2279
2280 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2281 {
2282         if (enable) {
2283                 u32 ocp_data;
2284
2285                 __rtl_set_wol(tp, WAKE_ANY);
2286
2287                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2288
2289                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2290                 ocp_data |= LINK_OFF_WAKE_EN;
2291                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2292
2293                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2294         } else {
2295                 __rtl_set_wol(tp, tp->saved_wolopts);
2296         }
2297 }
2298
2299 static void rtl_phy_reset(struct r8152 *tp)
2300 {
2301         u16 data;
2302         int i;
2303
2304         clear_bit(PHY_RESET, &tp->flags);
2305
2306         data = r8152_mdio_read(tp, MII_BMCR);
2307
2308         /* don't reset again before the previous one complete */
2309         if (data & BMCR_RESET)
2310                 return;
2311
2312         data |= BMCR_RESET;
2313         r8152_mdio_write(tp, MII_BMCR, data);
2314
2315         for (i = 0; i < 50; i++) {
2316                 msleep(20);
2317                 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2318                         break;
2319         }
2320 }
2321
2322 static void r8153_teredo_off(struct r8152 *tp)
2323 {
2324         u32 ocp_data;
2325
2326         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2327         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2328         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2329
2330         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2331         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2332         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2333 }
2334
2335 static void r8152b_disable_aldps(struct r8152 *tp)
2336 {
2337         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2338         msleep(20);
2339 }
2340
2341 static inline void r8152b_enable_aldps(struct r8152 *tp)
2342 {
2343         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2344                                             LINKENA | DIS_SDSAVE);
2345 }
2346
2347 static void rtl8152_disable(struct r8152 *tp)
2348 {
2349         r8152b_disable_aldps(tp);
2350         rtl_disable(tp);
2351         r8152b_enable_aldps(tp);
2352 }
2353
2354 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2355 {
2356         u16 data;
2357
2358         data = r8152_mdio_read(tp, MII_BMCR);
2359         if (data & BMCR_PDOWN) {
2360                 data &= ~BMCR_PDOWN;
2361                 r8152_mdio_write(tp, MII_BMCR, data);
2362         }
2363
2364         set_bit(PHY_RESET, &tp->flags);
2365 }
2366
2367 static void r8152b_exit_oob(struct r8152 *tp)
2368 {
2369         u32 ocp_data;
2370         int i;
2371
2372         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2373         ocp_data &= ~RCR_ACPT_ALL;
2374         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2375
2376         rxdy_gated_en(tp, true);
2377         r8153_teredo_off(tp);
2378         r8152b_hw_phy_cfg(tp);
2379
2380         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2381         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2382
2383         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2384         ocp_data &= ~NOW_IS_OOB;
2385         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2386
2387         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2388         ocp_data &= ~MCU_BORW_EN;
2389         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2390
2391         for (i = 0; i < 1000; i++) {
2392                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2393                 if (ocp_data & LINK_LIST_READY)
2394                         break;
2395                 usleep_range(1000, 2000);
2396         }
2397
2398         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2399         ocp_data |= RE_INIT_LL;
2400         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2401
2402         for (i = 0; i < 1000; i++) {
2403                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2404                 if (ocp_data & LINK_LIST_READY)
2405                         break;
2406                 usleep_range(1000, 2000);
2407         }
2408
2409         rtl8152_nic_reset(tp);
2410
2411         /* rx share fifo credit full threshold */
2412         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2413
2414         if (tp->udev->speed == USB_SPEED_FULL ||
2415             tp->udev->speed == USB_SPEED_LOW) {
2416                 /* rx share fifo credit near full threshold */
2417                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2418                                 RXFIFO_THR2_FULL);
2419                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2420                                 RXFIFO_THR3_FULL);
2421         } else {
2422                 /* rx share fifo credit near full threshold */
2423                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2424                                 RXFIFO_THR2_HIGH);
2425                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2426                                 RXFIFO_THR3_HIGH);
2427         }
2428
2429         /* TX share fifo free credit full threshold */
2430         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2431
2432         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2433         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2434         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2435                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2436
2437         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2438
2439         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2440
2441         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2442         ocp_data |= TCR0_AUTO_FIFO;
2443         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2444 }
2445
2446 static void r8152b_enter_oob(struct r8152 *tp)
2447 {
2448         u32 ocp_data;
2449         int i;
2450
2451         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2452         ocp_data &= ~NOW_IS_OOB;
2453         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2454
2455         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2456         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2457         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2458
2459         rtl_disable(tp);
2460
2461         for (i = 0; i < 1000; i++) {
2462                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2463                 if (ocp_data & LINK_LIST_READY)
2464                         break;
2465                 usleep_range(1000, 2000);
2466         }
2467
2468         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2469         ocp_data |= RE_INIT_LL;
2470         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2471
2472         for (i = 0; i < 1000; i++) {
2473                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2474                 if (ocp_data & LINK_LIST_READY)
2475                         break;
2476                 usleep_range(1000, 2000);
2477         }
2478
2479         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2480
2481         rtl_rx_vlan_en(tp, true);
2482
2483         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2484         ocp_data |= ALDPS_PROXY_MODE;
2485         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2486
2487         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2488         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2489         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2490
2491         rxdy_gated_en(tp, false);
2492
2493         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2494         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2495         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2496 }
2497
2498 static void r8153_hw_phy_cfg(struct r8152 *tp)
2499 {
2500         u32 ocp_data;
2501         u16 data;
2502
2503         ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2504         data = r8152_mdio_read(tp, MII_BMCR);
2505         if (data & BMCR_PDOWN) {
2506                 data &= ~BMCR_PDOWN;
2507                 r8152_mdio_write(tp, MII_BMCR, data);
2508         }
2509
2510         if (tp->version == RTL_VER_03) {
2511                 data = ocp_reg_read(tp, OCP_EEE_CFG);
2512                 data &= ~CTAP_SHORT_EN;
2513                 ocp_reg_write(tp, OCP_EEE_CFG, data);
2514         }
2515
2516         data = ocp_reg_read(tp, OCP_POWER_CFG);
2517         data |= EEE_CLKDIV_EN;
2518         ocp_reg_write(tp, OCP_POWER_CFG, data);
2519
2520         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2521         data |= EN_10M_BGOFF;
2522         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2523         data = ocp_reg_read(tp, OCP_POWER_CFG);
2524         data |= EN_10M_PLLOFF;
2525         ocp_reg_write(tp, OCP_POWER_CFG, data);
2526         data = sram_read(tp, SRAM_IMPEDANCE);
2527         data &= ~RX_DRIVING_MASK;
2528         sram_write(tp, SRAM_IMPEDANCE, data);
2529
2530         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2531         ocp_data |= PFM_PWM_SWITCH;
2532         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2533
2534         data = sram_read(tp, SRAM_LPF_CFG);
2535         data |= LPF_AUTO_TUNE;
2536         sram_write(tp, SRAM_LPF_CFG, data);
2537
2538         data = sram_read(tp, SRAM_10M_AMP1);
2539         data |= GDAC_IB_UPALL;
2540         sram_write(tp, SRAM_10M_AMP1, data);
2541         data = sram_read(tp, SRAM_10M_AMP2);
2542         data |= AMP_DN;
2543         sram_write(tp, SRAM_10M_AMP2, data);
2544
2545         set_bit(PHY_RESET, &tp->flags);
2546 }
2547
2548 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2549 {
2550         u8 u1u2[8];
2551
2552         if (enable)
2553                 memset(u1u2, 0xff, sizeof(u1u2));
2554         else
2555                 memset(u1u2, 0x00, sizeof(u1u2));
2556
2557         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2558 }
2559
2560 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2561 {
2562         u32 ocp_data;
2563
2564         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2565         if (enable)
2566                 ocp_data |= U2P3_ENABLE;
2567         else
2568                 ocp_data &= ~U2P3_ENABLE;
2569         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2570 }
2571
2572 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2573 {
2574         u32 ocp_data;
2575
2576         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2577         if (enable)
2578                 ocp_data |= PWR_EN | PHASE2_EN;
2579         else
2580                 ocp_data &= ~(PWR_EN | PHASE2_EN);
2581         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2582
2583         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2584         ocp_data &= ~PCUT_STATUS;
2585         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2586 }
2587
2588 static void r8153_first_init(struct r8152 *tp)
2589 {
2590         u32 ocp_data;
2591         int i;
2592
2593         rxdy_gated_en(tp, true);
2594         r8153_teredo_off(tp);
2595
2596         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2597         ocp_data &= ~RCR_ACPT_ALL;
2598         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2599
2600         r8153_hw_phy_cfg(tp);
2601
2602         rtl8152_nic_reset(tp);
2603
2604         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2605         ocp_data &= ~NOW_IS_OOB;
2606         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2607
2608         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2609         ocp_data &= ~MCU_BORW_EN;
2610         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2611
2612         for (i = 0; i < 1000; i++) {
2613                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2614                 if (ocp_data & LINK_LIST_READY)
2615                         break;
2616                 usleep_range(1000, 2000);
2617         }
2618
2619         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2620         ocp_data |= RE_INIT_LL;
2621         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2622
2623         for (i = 0; i < 1000; i++) {
2624                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2625                 if (ocp_data & LINK_LIST_READY)
2626                         break;
2627                 usleep_range(1000, 2000);
2628         }
2629
2630         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
2631
2632         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2633         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2634
2635         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2636         ocp_data |= TCR0_AUTO_FIFO;
2637         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2638
2639         rtl8152_nic_reset(tp);
2640
2641         /* rx share fifo credit full threshold */
2642         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2643         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2644         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2645         /* TX share fifo free credit full threshold */
2646         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2647
2648         /* rx aggregation */
2649         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2650         ocp_data &= ~RX_AGG_DISABLE;
2651         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2652 }
2653
2654 static void r8153_enter_oob(struct r8152 *tp)
2655 {
2656         u32 ocp_data;
2657         int i;
2658
2659         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2660         ocp_data &= ~NOW_IS_OOB;
2661         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2662
2663         rtl_disable(tp);
2664
2665         for (i = 0; i < 1000; i++) {
2666                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2667                 if (ocp_data & LINK_LIST_READY)
2668                         break;
2669                 usleep_range(1000, 2000);
2670         }
2671
2672         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2673         ocp_data |= RE_INIT_LL;
2674         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2675
2676         for (i = 0; i < 1000; i++) {
2677                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2678                 if (ocp_data & LINK_LIST_READY)
2679                         break;
2680                 usleep_range(1000, 2000);
2681         }
2682
2683         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2684
2685         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2686         ocp_data &= ~TEREDO_WAKE_MASK;
2687         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2688
2689         rtl_rx_vlan_en(tp, true);
2690
2691         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2692         ocp_data |= ALDPS_PROXY_MODE;
2693         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2694
2695         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2696         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2697         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2698
2699         rxdy_gated_en(tp, false);
2700
2701         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2702         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2703         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2704 }
2705
2706 static void r8153_disable_aldps(struct r8152 *tp)
2707 {
2708         u16 data;
2709
2710         data = ocp_reg_read(tp, OCP_POWER_CFG);
2711         data &= ~EN_ALDPS;
2712         ocp_reg_write(tp, OCP_POWER_CFG, data);
2713         msleep(20);
2714 }
2715
2716 static void r8153_enable_aldps(struct r8152 *tp)
2717 {
2718         u16 data;
2719
2720         data = ocp_reg_read(tp, OCP_POWER_CFG);
2721         data |= EN_ALDPS;
2722         ocp_reg_write(tp, OCP_POWER_CFG, data);
2723 }
2724
2725 static void rtl8153_disable(struct r8152 *tp)
2726 {
2727         r8153_disable_aldps(tp);
2728         rtl_disable(tp);
2729         r8153_enable_aldps(tp);
2730 }
2731
2732 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2733 {
2734         u16 bmcr, anar, gbcr;
2735         int ret = 0;
2736
2737         cancel_delayed_work_sync(&tp->schedule);
2738         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2739         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2740                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2741         if (tp->mii.supports_gmii) {
2742                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2743                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2744         } else {
2745                 gbcr = 0;
2746         }
2747
2748         if (autoneg == AUTONEG_DISABLE) {
2749                 if (speed == SPEED_10) {
2750                         bmcr = 0;
2751                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2752                 } else if (speed == SPEED_100) {
2753                         bmcr = BMCR_SPEED100;
2754                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2755                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2756                         bmcr = BMCR_SPEED1000;
2757                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2758                 } else {
2759                         ret = -EINVAL;
2760                         goto out;
2761                 }
2762
2763                 if (duplex == DUPLEX_FULL)
2764                         bmcr |= BMCR_FULLDPLX;
2765         } else {
2766                 if (speed == SPEED_10) {
2767                         if (duplex == DUPLEX_FULL)
2768                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2769                         else
2770                                 anar |= ADVERTISE_10HALF;
2771                 } else if (speed == SPEED_100) {
2772                         if (duplex == DUPLEX_FULL) {
2773                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2774                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2775                         } else {
2776                                 anar |= ADVERTISE_10HALF;
2777                                 anar |= ADVERTISE_100HALF;
2778                         }
2779                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2780                         if (duplex == DUPLEX_FULL) {
2781                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2782                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2783                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2784                         } else {
2785                                 anar |= ADVERTISE_10HALF;
2786                                 anar |= ADVERTISE_100HALF;
2787                                 gbcr |= ADVERTISE_1000HALF;
2788                         }
2789                 } else {
2790                         ret = -EINVAL;
2791                         goto out;
2792                 }
2793
2794                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2795         }
2796
2797         if (test_bit(PHY_RESET, &tp->flags))
2798                 bmcr |= BMCR_RESET;
2799
2800         if (tp->mii.supports_gmii)
2801                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2802
2803         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2804         r8152_mdio_write(tp, MII_BMCR, bmcr);
2805
2806         if (test_bit(PHY_RESET, &tp->flags)) {
2807                 int i;
2808
2809                 clear_bit(PHY_RESET, &tp->flags);
2810                 for (i = 0; i < 50; i++) {
2811                         msleep(20);
2812                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2813                                 break;
2814                 }
2815         }
2816
2817 out:
2818
2819         return ret;
2820 }
2821
2822 static void rtl8152_up(struct r8152 *tp)
2823 {
2824         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2825                 return;
2826
2827         r8152b_disable_aldps(tp);
2828         r8152b_exit_oob(tp);
2829         r8152b_enable_aldps(tp);
2830 }
2831
2832 static void rtl8152_down(struct r8152 *tp)
2833 {
2834         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2835                 rtl_drop_queued_tx(tp);
2836                 return;
2837         }
2838
2839         r8152_power_cut_en(tp, false);
2840         r8152b_disable_aldps(tp);
2841         r8152b_enter_oob(tp);
2842         r8152b_enable_aldps(tp);
2843 }
2844
2845 static void rtl8153_up(struct r8152 *tp)
2846 {
2847         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2848                 return;
2849
2850         r8153_disable_aldps(tp);
2851         r8153_first_init(tp);
2852         r8153_enable_aldps(tp);
2853 }
2854
2855 static void rtl8153_down(struct r8152 *tp)
2856 {
2857         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2858                 rtl_drop_queued_tx(tp);
2859                 return;
2860         }
2861
2862         r8153_u1u2en(tp, false);
2863         r8153_power_cut_en(tp, false);
2864         r8153_disable_aldps(tp);
2865         r8153_enter_oob(tp);
2866         r8153_enable_aldps(tp);
2867 }
2868
2869 static void set_carrier(struct r8152 *tp)
2870 {
2871         struct net_device *netdev = tp->netdev;
2872         u8 speed;
2873
2874         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2875         speed = rtl8152_get_speed(tp);
2876
2877         if (speed & LINK_STATUS) {
2878                 if (!(tp->speed & LINK_STATUS)) {
2879                         tp->rtl_ops.enable(tp);
2880                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2881                         netif_carrier_on(netdev);
2882                         rtl_start_rx(tp);
2883                 }
2884         } else {
2885                 if (tp->speed & LINK_STATUS) {
2886                         netif_carrier_off(netdev);
2887                         tasklet_disable(&tp->tl);
2888                         tp->rtl_ops.disable(tp);
2889                         tasklet_enable(&tp->tl);
2890                 }
2891         }
2892         tp->speed = speed;
2893 }
2894
2895 static void rtl_work_func_t(struct work_struct *work)
2896 {
2897         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2898
2899         /* If the device is unplugged or !netif_running(), the workqueue
2900          * doesn't need to wake the device, and could return directly.
2901          */
2902         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
2903                 return;
2904
2905         if (usb_autopm_get_interface(tp->intf) < 0)
2906                 return;
2907
2908         if (!test_bit(WORK_ENABLE, &tp->flags))
2909                 goto out1;
2910
2911         if (!mutex_trylock(&tp->control)) {
2912                 schedule_delayed_work(&tp->schedule, 0);
2913                 goto out1;
2914         }
2915
2916         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2917                 set_carrier(tp);
2918
2919         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2920                 _rtl8152_set_rx_mode(tp->netdev);
2921
2922         if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2923             (tp->speed & LINK_STATUS)) {
2924                 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2925                 tasklet_schedule(&tp->tl);
2926         }
2927
2928         if (test_bit(PHY_RESET, &tp->flags))
2929                 rtl_phy_reset(tp);
2930
2931         mutex_unlock(&tp->control);
2932
2933 out1:
2934         usb_autopm_put_interface(tp->intf);
2935 }
2936
2937 static int rtl8152_open(struct net_device *netdev)
2938 {
2939         struct r8152 *tp = netdev_priv(netdev);
2940         int res = 0;
2941
2942         res = alloc_all_mem(tp);
2943         if (res)
2944                 goto out;
2945
2946         /* set speed to 0 to avoid autoresume try to submit rx */
2947         tp->speed = 0;
2948
2949         res = usb_autopm_get_interface(tp->intf);
2950         if (res < 0) {
2951                 free_all_mem(tp);
2952                 goto out;
2953         }
2954
2955         mutex_lock(&tp->control);
2956
2957         /* The WORK_ENABLE may be set when autoresume occurs */
2958         if (test_bit(WORK_ENABLE, &tp->flags)) {
2959                 clear_bit(WORK_ENABLE, &tp->flags);
2960                 usb_kill_urb(tp->intr_urb);
2961                 cancel_delayed_work_sync(&tp->schedule);
2962
2963                 /* disable the tx/rx, if the workqueue has enabled them. */
2964                 if (tp->speed & LINK_STATUS)
2965                         tp->rtl_ops.disable(tp);
2966         }
2967
2968         tp->rtl_ops.up(tp);
2969
2970         rtl8152_set_speed(tp, AUTONEG_ENABLE,
2971                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2972                           DUPLEX_FULL);
2973         tp->speed = 0;
2974         netif_carrier_off(netdev);
2975         netif_start_queue(netdev);
2976         set_bit(WORK_ENABLE, &tp->flags);
2977
2978         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2979         if (res) {
2980                 if (res == -ENODEV)
2981                         netif_device_detach(tp->netdev);
2982                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2983                            res);
2984                 free_all_mem(tp);
2985         } else {
2986                 tasklet_enable(&tp->tl);
2987         }
2988
2989         mutex_unlock(&tp->control);
2990
2991         usb_autopm_put_interface(tp->intf);
2992
2993 out:
2994         return res;
2995 }
2996
2997 static int rtl8152_close(struct net_device *netdev)
2998 {
2999         struct r8152 *tp = netdev_priv(netdev);
3000         int res = 0;
3001
3002         tasklet_disable(&tp->tl);
3003         clear_bit(WORK_ENABLE, &tp->flags);
3004         usb_kill_urb(tp->intr_urb);
3005         cancel_delayed_work_sync(&tp->schedule);
3006         netif_stop_queue(netdev);
3007
3008         res = usb_autopm_get_interface(tp->intf);
3009         if (res < 0) {
3010                 rtl_drop_queued_tx(tp);
3011         } else {
3012                 mutex_lock(&tp->control);
3013
3014                 /* The autosuspend may have been enabled and wouldn't
3015                  * be disable when autoresume occurs, because the
3016                  * netif_running() would be false.
3017                  */
3018                 rtl_runtime_suspend_enable(tp, false);
3019
3020                 tp->rtl_ops.down(tp);
3021
3022                 mutex_unlock(&tp->control);
3023
3024                 usb_autopm_put_interface(tp->intf);
3025         }
3026
3027         free_all_mem(tp);
3028
3029         return res;
3030 }
3031
3032 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
3033 {
3034         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
3035         ocp_reg_write(tp, OCP_EEE_DATA, reg);
3036         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
3037 }
3038
3039 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
3040 {
3041         u16 data;
3042
3043         r8152_mmd_indirect(tp, dev, reg);
3044         data = ocp_reg_read(tp, OCP_EEE_DATA);
3045         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3046
3047         return data;
3048 }
3049
3050 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
3051 {
3052         r8152_mmd_indirect(tp, dev, reg);
3053         ocp_reg_write(tp, OCP_EEE_DATA, data);
3054         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3055 }
3056
3057 static void r8152_eee_en(struct r8152 *tp, bool enable)
3058 {
3059         u16 config1, config2, config3;
3060         u32 ocp_data;
3061
3062         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3063         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3064         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3065         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3066
3067         if (enable) {
3068                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3069                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3070                 config1 |= sd_rise_time(1);
3071                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3072                 config3 |= fast_snr(42);
3073         } else {
3074                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3075                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3076                              RX_QUIET_EN);
3077                 config1 |= sd_rise_time(7);
3078                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3079                 config3 |= fast_snr(511);
3080         }
3081
3082         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3083         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3084         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3085         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
3086 }
3087
3088 static void r8152b_enable_eee(struct r8152 *tp)
3089 {
3090         r8152_eee_en(tp, true);
3091         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3092 }
3093
3094 static void r8153_eee_en(struct r8152 *tp, bool enable)
3095 {
3096         u32 ocp_data;
3097         u16 config;
3098
3099         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3100         config = ocp_reg_read(tp, OCP_EEE_CFG);
3101
3102         if (enable) {
3103                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3104                 config |= EEE10_EN;
3105         } else {
3106                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3107                 config &= ~EEE10_EN;
3108         }
3109
3110         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3111         ocp_reg_write(tp, OCP_EEE_CFG, config);
3112 }
3113
3114 static void r8153_enable_eee(struct r8152 *tp)
3115 {
3116         r8153_eee_en(tp, true);
3117         ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3118 }
3119
3120 static void r8152b_enable_fc(struct r8152 *tp)
3121 {
3122         u16 anar;
3123
3124         anar = r8152_mdio_read(tp, MII_ADVERTISE);
3125         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3126         r8152_mdio_write(tp, MII_ADVERTISE, anar);
3127 }
3128
3129 static void rtl_tally_reset(struct r8152 *tp)
3130 {
3131         u32 ocp_data;
3132
3133         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3134         ocp_data |= TALLY_RESET;
3135         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3136 }
3137
3138 static void r8152b_init(struct r8152 *tp)
3139 {
3140         u32 ocp_data;
3141
3142         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3143                 return;
3144
3145         r8152b_disable_aldps(tp);
3146
3147         if (tp->version == RTL_VER_01) {
3148                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3149                 ocp_data &= ~LED_MODE_MASK;
3150                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3151         }
3152
3153         r8152_power_cut_en(tp, false);
3154
3155         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3156         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3157         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3158         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3159         ocp_data &= ~MCU_CLK_RATIO_MASK;
3160         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3161         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3162         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3163                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3164         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3165
3166         r8152b_enable_eee(tp);
3167         r8152b_enable_aldps(tp);
3168         r8152b_enable_fc(tp);
3169         rtl_tally_reset(tp);
3170
3171         /* enable rx aggregation */
3172         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3173         ocp_data &= ~RX_AGG_DISABLE;
3174         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3175 }
3176
3177 static void r8153_init(struct r8152 *tp)
3178 {
3179         u32 ocp_data;
3180         int i;
3181
3182         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3183                 return;
3184
3185         r8153_disable_aldps(tp);
3186         r8153_u1u2en(tp, false);
3187
3188         for (i = 0; i < 500; i++) {
3189                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3190                     AUTOLOAD_DONE)
3191                         break;
3192                 msleep(20);
3193         }
3194
3195         for (i = 0; i < 500; i++) {
3196                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3197                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3198                         break;
3199                 msleep(20);
3200         }
3201
3202         r8153_u2p3en(tp, false);
3203
3204         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3205         ocp_data &= ~TIMER11_EN;
3206         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3207
3208         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3209         ocp_data &= ~LED_MODE_MASK;
3210         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3211
3212         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3213         ocp_data &= ~LPM_TIMER_MASK;
3214         if (tp->udev->speed == USB_SPEED_SUPER)
3215                 ocp_data |= LPM_TIMER_500US;
3216         else
3217                 ocp_data |= LPM_TIMER_500MS;
3218         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3219
3220         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3221         ocp_data &= ~SEN_VAL_MASK;
3222         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3223         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3224
3225         r8153_power_cut_en(tp, false);
3226         r8153_u1u2en(tp, true);
3227
3228         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3229         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3230         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3231                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3232                        U1U2_SPDWN_EN | L1_SPDWN_EN);
3233         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3234                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3235                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3236                        EEE_SPDWN_EN);
3237
3238         r8153_enable_eee(tp);
3239         r8153_enable_aldps(tp);
3240         r8152b_enable_fc(tp);
3241         rtl_tally_reset(tp);
3242 }
3243
3244 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3245 {
3246         struct r8152 *tp = usb_get_intfdata(intf);
3247         struct net_device *netdev = tp->netdev;
3248         int ret = 0;
3249
3250         mutex_lock(&tp->control);
3251
3252         if (PMSG_IS_AUTO(message)) {
3253                 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3254                         ret = -EBUSY;
3255                         goto out1;
3256                 }
3257
3258                 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3259         } else {
3260                 netif_device_detach(netdev);
3261         }
3262
3263         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
3264                 clear_bit(WORK_ENABLE, &tp->flags);
3265                 usb_kill_urb(tp->intr_urb);
3266                 tasklet_disable(&tp->tl);
3267                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3268                         rtl_stop_rx(tp);
3269                         rtl_runtime_suspend_enable(tp, true);
3270                 } else {
3271                         cancel_delayed_work_sync(&tp->schedule);
3272                         tp->rtl_ops.down(tp);
3273                 }
3274                 tasklet_enable(&tp->tl);
3275         }
3276 out1:
3277         mutex_unlock(&tp->control);
3278
3279         return ret;
3280 }
3281
3282 static int rtl8152_resume(struct usb_interface *intf)
3283 {
3284         struct r8152 *tp = usb_get_intfdata(intf);
3285
3286         mutex_lock(&tp->control);
3287
3288         if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3289                 tp->rtl_ops.init(tp);
3290                 netif_device_attach(tp->netdev);
3291         }
3292
3293         if (netif_running(tp->netdev)) {
3294                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3295                         rtl_runtime_suspend_enable(tp, false);
3296                         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3297                         set_bit(WORK_ENABLE, &tp->flags);
3298                         if (tp->speed & LINK_STATUS)
3299                                 rtl_start_rx(tp);
3300                 } else {
3301                         tp->rtl_ops.up(tp);
3302                         rtl8152_set_speed(tp, AUTONEG_ENABLE,
3303                                           tp->mii.supports_gmii ?
3304                                           SPEED_1000 : SPEED_100,
3305                                           DUPLEX_FULL);
3306                         tp->speed = 0;
3307                         netif_carrier_off(tp->netdev);
3308                         set_bit(WORK_ENABLE, &tp->flags);
3309                 }
3310                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3311         } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3312                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3313         }
3314
3315         mutex_unlock(&tp->control);
3316
3317         return 0;
3318 }
3319
3320 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3321 {
3322         struct r8152 *tp = netdev_priv(dev);
3323
3324         if (usb_autopm_get_interface(tp->intf) < 0)
3325                 return;
3326
3327         mutex_lock(&tp->control);
3328
3329         wol->supported = WAKE_ANY;
3330         wol->wolopts = __rtl_get_wol(tp);
3331
3332         mutex_unlock(&tp->control);
3333
3334         usb_autopm_put_interface(tp->intf);
3335 }
3336
3337 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3338 {
3339         struct r8152 *tp = netdev_priv(dev);
3340         int ret;
3341
3342         ret = usb_autopm_get_interface(tp->intf);
3343         if (ret < 0)
3344                 goto out_set_wol;
3345
3346         mutex_lock(&tp->control);
3347
3348         __rtl_set_wol(tp, wol->wolopts);
3349         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3350
3351         mutex_unlock(&tp->control);
3352
3353         usb_autopm_put_interface(tp->intf);
3354
3355 out_set_wol:
3356         return ret;
3357 }
3358
3359 static u32 rtl8152_get_msglevel(struct net_device *dev)
3360 {
3361         struct r8152 *tp = netdev_priv(dev);
3362
3363         return tp->msg_enable;
3364 }
3365
3366 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3367 {
3368         struct r8152 *tp = netdev_priv(dev);
3369
3370         tp->msg_enable = value;
3371 }
3372
3373 static void rtl8152_get_drvinfo(struct net_device *netdev,
3374                                 struct ethtool_drvinfo *info)
3375 {
3376         struct r8152 *tp = netdev_priv(netdev);
3377
3378         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3379         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3380         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3381 }
3382
3383 static
3384 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3385 {
3386         struct r8152 *tp = netdev_priv(netdev);
3387         int ret;
3388
3389         if (!tp->mii.mdio_read)
3390                 return -EOPNOTSUPP;
3391
3392         ret = usb_autopm_get_interface(tp->intf);
3393         if (ret < 0)
3394                 goto out;
3395
3396         mutex_lock(&tp->control);
3397
3398         ret = mii_ethtool_gset(&tp->mii, cmd);
3399
3400         mutex_unlock(&tp->control);
3401
3402         usb_autopm_put_interface(tp->intf);
3403
3404 out:
3405         return ret;
3406 }
3407
3408 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3409 {
3410         struct r8152 *tp = netdev_priv(dev);
3411         int ret;
3412
3413         ret = usb_autopm_get_interface(tp->intf);
3414         if (ret < 0)
3415                 goto out;
3416
3417         mutex_lock(&tp->control);
3418
3419         ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3420
3421         mutex_unlock(&tp->control);
3422
3423         usb_autopm_put_interface(tp->intf);
3424
3425 out:
3426         return ret;
3427 }
3428
3429 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3430         "tx_packets",
3431         "rx_packets",
3432         "tx_errors",
3433         "rx_errors",
3434         "rx_missed",
3435         "align_errors",
3436         "tx_single_collisions",
3437         "tx_multi_collisions",
3438         "rx_unicast",
3439         "rx_broadcast",
3440         "rx_multicast",
3441         "tx_aborted",
3442         "tx_underrun",
3443 };
3444
3445 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3446 {
3447         switch (sset) {
3448         case ETH_SS_STATS:
3449                 return ARRAY_SIZE(rtl8152_gstrings);
3450         default:
3451                 return -EOPNOTSUPP;
3452         }
3453 }
3454
3455 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3456                                       struct ethtool_stats *stats, u64 *data)
3457 {
3458         struct r8152 *tp = netdev_priv(dev);
3459         struct tally_counter tally;
3460
3461         if (usb_autopm_get_interface(tp->intf) < 0)
3462                 return;
3463
3464         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3465
3466         usb_autopm_put_interface(tp->intf);
3467
3468         data[0] = le64_to_cpu(tally.tx_packets);
3469         data[1] = le64_to_cpu(tally.rx_packets);
3470         data[2] = le64_to_cpu(tally.tx_errors);
3471         data[3] = le32_to_cpu(tally.rx_errors);
3472         data[4] = le16_to_cpu(tally.rx_missed);
3473         data[5] = le16_to_cpu(tally.align_errors);
3474         data[6] = le32_to_cpu(tally.tx_one_collision);
3475         data[7] = le32_to_cpu(tally.tx_multi_collision);
3476         data[8] = le64_to_cpu(tally.rx_unicast);
3477         data[9] = le64_to_cpu(tally.rx_broadcast);
3478         data[10] = le32_to_cpu(tally.rx_multicast);
3479         data[11] = le16_to_cpu(tally.tx_aborted);
3480         data[12] = le16_to_cpu(tally.tx_underrun);
3481 }
3482
3483 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3484 {
3485         switch (stringset) {
3486         case ETH_SS_STATS:
3487                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3488                 break;
3489         }
3490 }
3491
3492 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3493 {
3494         u32 ocp_data, lp, adv, supported = 0;
3495         u16 val;
3496
3497         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3498         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3499
3500         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3501         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3502
3503         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3504         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3505
3506         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3507         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3508
3509         eee->eee_enabled = !!ocp_data;
3510         eee->eee_active = !!(supported & adv & lp);
3511         eee->supported = supported;
3512         eee->advertised = adv;
3513         eee->lp_advertised = lp;
3514
3515         return 0;
3516 }
3517
3518 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3519 {
3520         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3521
3522         r8152_eee_en(tp, eee->eee_enabled);
3523
3524         if (!eee->eee_enabled)
3525                 val = 0;
3526
3527         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3528
3529         return 0;
3530 }
3531
3532 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3533 {
3534         u32 ocp_data, lp, adv, supported = 0;
3535         u16 val;
3536
3537         val = ocp_reg_read(tp, OCP_EEE_ABLE);
3538         supported = mmd_eee_cap_to_ethtool_sup_t(val);
3539
3540         val = ocp_reg_read(tp, OCP_EEE_ADV);
3541         adv = mmd_eee_adv_to_ethtool_adv_t(val);
3542
3543         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3544         lp = mmd_eee_adv_to_ethtool_adv_t(val);
3545
3546         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3547         ocp_data &= EEE_RX_EN | EEE_TX_EN;
3548
3549         eee->eee_enabled = !!ocp_data;
3550         eee->eee_active = !!(supported & adv & lp);
3551         eee->supported = supported;
3552         eee->advertised = adv;
3553         eee->lp_advertised = lp;
3554
3555         return 0;
3556 }
3557
3558 static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3559 {
3560         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3561
3562         r8153_eee_en(tp, eee->eee_enabled);
3563
3564         if (!eee->eee_enabled)
3565                 val = 0;
3566
3567         ocp_reg_write(tp, OCP_EEE_ADV, val);
3568
3569         return 0;
3570 }
3571
3572 static int
3573 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3574 {
3575         struct r8152 *tp = netdev_priv(net);
3576         int ret;
3577
3578         ret = usb_autopm_get_interface(tp->intf);
3579         if (ret < 0)
3580                 goto out;
3581
3582         mutex_lock(&tp->control);
3583
3584         ret = tp->rtl_ops.eee_get(tp, edata);
3585
3586         mutex_unlock(&tp->control);
3587
3588         usb_autopm_put_interface(tp->intf);
3589
3590 out:
3591         return ret;
3592 }
3593
3594 static int
3595 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3596 {
3597         struct r8152 *tp = netdev_priv(net);
3598         int ret;
3599
3600         ret = usb_autopm_get_interface(tp->intf);
3601         if (ret < 0)
3602                 goto out;
3603
3604         mutex_lock(&tp->control);
3605
3606         ret = tp->rtl_ops.eee_set(tp, edata);
3607         if (!ret)
3608                 ret = mii_nway_restart(&tp->mii);
3609
3610         mutex_unlock(&tp->control);
3611
3612         usb_autopm_put_interface(tp->intf);
3613
3614 out:
3615         return ret;
3616 }
3617
3618 static int rtl8152_nway_reset(struct net_device *dev)
3619 {
3620         struct r8152 *tp = netdev_priv(dev);
3621         int ret;
3622
3623         ret = usb_autopm_get_interface(tp->intf);
3624         if (ret < 0)
3625                 goto out;
3626
3627         mutex_lock(&tp->control);
3628
3629         ret = mii_nway_restart(&tp->mii);
3630
3631         mutex_unlock(&tp->control);
3632
3633         usb_autopm_put_interface(tp->intf);
3634
3635 out:
3636         return ret;
3637 }
3638
3639 static struct ethtool_ops ops = {
3640         .get_drvinfo = rtl8152_get_drvinfo,
3641         .get_settings = rtl8152_get_settings,
3642         .set_settings = rtl8152_set_settings,
3643         .get_link = ethtool_op_get_link,
3644         .nway_reset = rtl8152_nway_reset,
3645         .get_msglevel = rtl8152_get_msglevel,
3646         .set_msglevel = rtl8152_set_msglevel,
3647         .get_wol = rtl8152_get_wol,
3648         .set_wol = rtl8152_set_wol,
3649         .get_strings = rtl8152_get_strings,
3650         .get_sset_count = rtl8152_get_sset_count,
3651         .get_ethtool_stats = rtl8152_get_ethtool_stats,
3652         .get_eee = rtl_ethtool_get_eee,
3653         .set_eee = rtl_ethtool_set_eee,
3654 };
3655
3656 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3657 {
3658         struct r8152 *tp = netdev_priv(netdev);
3659         struct mii_ioctl_data *data = if_mii(rq);
3660         int res;
3661
3662         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3663                 return -ENODEV;
3664
3665         res = usb_autopm_get_interface(tp->intf);
3666         if (res < 0)
3667                 goto out;
3668
3669         switch (cmd) {
3670         case SIOCGMIIPHY:
3671                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3672                 break;
3673
3674         case SIOCGMIIREG:
3675                 mutex_lock(&tp->control);
3676                 data->val_out = r8152_mdio_read(tp, data->reg_num);
3677                 mutex_unlock(&tp->control);
3678                 break;
3679
3680         case SIOCSMIIREG:
3681                 if (!capable(CAP_NET_ADMIN)) {
3682                         res = -EPERM;
3683                         break;
3684                 }
3685                 mutex_lock(&tp->control);
3686                 r8152_mdio_write(tp, data->reg_num, data->val_in);
3687                 mutex_unlock(&tp->control);
3688                 break;
3689
3690         default:
3691                 res = -EOPNOTSUPP;
3692         }
3693
3694         usb_autopm_put_interface(tp->intf);
3695
3696 out:
3697         return res;
3698 }
3699
3700 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3701 {
3702         struct r8152 *tp = netdev_priv(dev);
3703
3704         switch (tp->version) {
3705         case RTL_VER_01:
3706         case RTL_VER_02:
3707                 return eth_change_mtu(dev, new_mtu);
3708         default:
3709                 break;
3710         }
3711
3712         if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3713                 return -EINVAL;
3714
3715         dev->mtu = new_mtu;
3716
3717         return 0;
3718 }
3719
3720 static const struct net_device_ops rtl8152_netdev_ops = {
3721         .ndo_open               = rtl8152_open,
3722         .ndo_stop               = rtl8152_close,
3723         .ndo_do_ioctl           = rtl8152_ioctl,
3724         .ndo_start_xmit         = rtl8152_start_xmit,
3725         .ndo_tx_timeout         = rtl8152_tx_timeout,
3726         .ndo_set_features       = rtl8152_set_features,
3727         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
3728         .ndo_set_mac_address    = rtl8152_set_mac_address,
3729         .ndo_change_mtu         = rtl8152_change_mtu,
3730         .ndo_validate_addr      = eth_validate_addr,
3731         .ndo_features_check     = rtl8152_features_check,
3732 };
3733
3734 static void r8152b_get_version(struct r8152 *tp)
3735 {
3736         u32     ocp_data;
3737         u16     version;
3738
3739         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3740         version = (u16)(ocp_data & VERSION_MASK);
3741
3742         switch (version) {
3743         case 0x4c00:
3744                 tp->version = RTL_VER_01;
3745                 break;
3746         case 0x4c10:
3747                 tp->version = RTL_VER_02;
3748                 break;
3749         case 0x5c00:
3750                 tp->version = RTL_VER_03;
3751                 tp->mii.supports_gmii = 1;
3752                 break;
3753         case 0x5c10:
3754                 tp->version = RTL_VER_04;
3755                 tp->mii.supports_gmii = 1;
3756                 break;
3757         case 0x5c20:
3758                 tp->version = RTL_VER_05;
3759                 tp->mii.supports_gmii = 1;
3760                 break;
3761         default:
3762                 netif_info(tp, probe, tp->netdev,
3763                            "Unknown version 0x%04x\n", version);
3764                 break;
3765         }
3766 }
3767
3768 static void rtl8152_unload(struct r8152 *tp)
3769 {
3770         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3771                 return;
3772
3773         if (tp->version != RTL_VER_01)
3774                 r8152_power_cut_en(tp, true);
3775 }
3776
3777 static void rtl8153_unload(struct r8152 *tp)
3778 {
3779         if (test_bit(RTL8152_UNPLUG, &tp->flags))
3780                 return;
3781
3782         r8153_power_cut_en(tp, false);
3783 }
3784
3785 static int rtl_ops_init(struct r8152 *tp)
3786 {
3787         struct rtl_ops *ops = &tp->rtl_ops;
3788         int ret = 0;
3789
3790         switch (tp->version) {
3791         case RTL_VER_01:
3792         case RTL_VER_02:
3793                 ops->init               = r8152b_init;
3794                 ops->enable             = rtl8152_enable;
3795                 ops->disable            = rtl8152_disable;
3796                 ops->up                 = rtl8152_up;
3797                 ops->down               = rtl8152_down;
3798                 ops->unload             = rtl8152_unload;
3799                 ops->eee_get            = r8152_get_eee;
3800                 ops->eee_set            = r8152_set_eee;
3801                 break;
3802
3803         case RTL_VER_03:
3804         case RTL_VER_04:
3805         case RTL_VER_05:
3806                 ops->init               = r8153_init;
3807                 ops->enable             = rtl8153_enable;
3808                 ops->disable            = rtl8153_disable;
3809                 ops->up                 = rtl8153_up;
3810                 ops->down               = rtl8153_down;
3811                 ops->unload             = rtl8153_unload;
3812                 ops->eee_get            = r8153_get_eee;
3813                 ops->eee_set            = r8153_set_eee;
3814                 break;
3815
3816         default:
3817                 ret = -ENODEV;
3818                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3819                 break;
3820         }
3821
3822         return ret;
3823 }
3824
3825 static int rtl8152_probe(struct usb_interface *intf,
3826                          const struct usb_device_id *id)
3827 {
3828         struct usb_device *udev = interface_to_usbdev(intf);
3829         struct r8152 *tp;
3830         struct net_device *netdev;
3831         int ret;
3832
3833         if (udev->actconfig->desc.bConfigurationValue != 1) {
3834                 usb_driver_set_configuration(udev, 1);
3835                 return -ENODEV;
3836         }
3837
3838         usb_reset_device(udev);
3839         netdev = alloc_etherdev(sizeof(struct r8152));
3840         if (!netdev) {
3841                 dev_err(&intf->dev, "Out of memory\n");
3842                 return -ENOMEM;
3843         }
3844
3845         SET_NETDEV_DEV(netdev, &intf->dev);
3846         tp = netdev_priv(netdev);
3847         tp->msg_enable = 0x7FFF;
3848
3849         tp->udev = udev;
3850         tp->netdev = netdev;
3851         tp->intf = intf;
3852
3853         r8152b_get_version(tp);
3854         ret = rtl_ops_init(tp);
3855         if (ret)
3856                 goto out;
3857
3858         tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3859         mutex_init(&tp->control);
3860         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3861
3862         netdev->netdev_ops = &rtl8152_netdev_ops;
3863         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3864
3865         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3866                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3867                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3868                             NETIF_F_HW_VLAN_CTAG_TX;
3869         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3870                               NETIF_F_TSO | NETIF_F_FRAGLIST |
3871                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3872                               NETIF_F_HW_VLAN_CTAG_RX |
3873                               NETIF_F_HW_VLAN_CTAG_TX;
3874         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3875                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3876                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3877
3878         netdev->ethtool_ops = &ops;
3879         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3880
3881         tp->mii.dev = netdev;
3882         tp->mii.mdio_read = read_mii_word;
3883         tp->mii.mdio_write = write_mii_word;
3884         tp->mii.phy_id_mask = 0x3f;
3885         tp->mii.reg_num_mask = 0x1f;
3886         tp->mii.phy_id = R8152_PHY_ID;
3887
3888         intf->needs_remote_wakeup = 1;
3889
3890         tp->rtl_ops.init(tp);
3891         set_ethernet_addr(tp);
3892
3893         usb_set_intfdata(intf, tp);
3894
3895         ret = register_netdev(netdev);
3896         if (ret != 0) {
3897                 netif_err(tp, probe, netdev, "couldn't register the device\n");
3898                 goto out1;
3899         }
3900
3901         tp->saved_wolopts = __rtl_get_wol(tp);
3902         if (tp->saved_wolopts)
3903                 device_set_wakeup_enable(&udev->dev, true);
3904         else
3905                 device_set_wakeup_enable(&udev->dev, false);
3906
3907         tasklet_disable(&tp->tl);
3908
3909         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3910
3911         return 0;
3912
3913 out1:
3914         usb_set_intfdata(intf, NULL);
3915         tasklet_kill(&tp->tl);
3916 out:
3917         free_netdev(netdev);
3918         return ret;
3919 }
3920
3921 static void rtl8152_disconnect(struct usb_interface *intf)
3922 {
3923         struct r8152 *tp = usb_get_intfdata(intf);
3924
3925         usb_set_intfdata(intf, NULL);
3926         if (tp) {
3927                 struct usb_device *udev = tp->udev;
3928
3929                 if (udev->state == USB_STATE_NOTATTACHED)
3930                         set_bit(RTL8152_UNPLUG, &tp->flags);
3931
3932                 tasklet_kill(&tp->tl);
3933                 unregister_netdev(tp->netdev);
3934                 tp->rtl_ops.unload(tp);
3935                 free_netdev(tp->netdev);
3936         }
3937 }
3938
3939 #define REALTEK_USB_DEVICE(vend, prod)  \
3940         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
3941                        USB_DEVICE_ID_MATCH_INT_CLASS, \
3942         .idVendor = (vend), \
3943         .idProduct = (prod), \
3944         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
3945 }, \
3946 { \
3947         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
3948                        USB_DEVICE_ID_MATCH_DEVICE, \
3949         .idVendor = (vend), \
3950         .idProduct = (prod), \
3951         .bInterfaceClass = USB_CLASS_COMM, \
3952         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
3953         .bInterfaceProtocol = USB_CDC_PROTO_NONE
3954
3955 /* table of devices that work with this driver */
3956 static struct usb_device_id rtl8152_table[] = {
3957         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
3958         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
3959         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
3960         {}
3961 };
3962
3963 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3964
3965 static struct usb_driver rtl8152_driver = {
3966         .name =         MODULENAME,
3967         .id_table =     rtl8152_table,
3968         .probe =        rtl8152_probe,
3969         .disconnect =   rtl8152_disconnect,
3970         .suspend =      rtl8152_suspend,
3971         .resume =       rtl8152_resume,
3972         .reset_resume = rtl8152_resume,
3973         .supports_autosuspend = 1,
3974         .disable_hub_initiated_lpm = 1,
3975 };
3976
3977 module_usb_driver(rtl8152_driver);
3978
3979 MODULE_AUTHOR(DRIVER_AUTHOR);
3980 MODULE_DESCRIPTION(DRIVER_DESC);
3981 MODULE_LICENSE("GPL");