2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/etherdevice.h>
25 void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
27 htt->num_pending_tx--;
28 if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
29 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
32 static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
34 spin_lock_bh(&htt->tx_lock);
35 __ath10k_htt_tx_dec_pending(htt);
36 spin_unlock_bh(&htt->tx_lock);
39 static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
43 spin_lock_bh(&htt->tx_lock);
45 if (htt->num_pending_tx >= htt->max_num_pending_tx) {
50 htt->num_pending_tx++;
51 if (htt->num_pending_tx == htt->max_num_pending_tx)
52 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL);
55 spin_unlock_bh(&htt->tx_lock);
59 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb)
61 struct ath10k *ar = htt->ar;
64 lockdep_assert_held(&htt->tx_lock);
66 ret = idr_alloc(&htt->pending_tx, skb, 0, 0x10000, GFP_ATOMIC);
68 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret);
73 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
75 struct ath10k *ar = htt->ar;
77 lockdep_assert_held(&htt->tx_lock);
79 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
81 idr_remove(&htt->pending_tx, msdu_id);
84 int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
86 struct ath10k *ar = htt->ar;
88 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
89 htt->max_num_pending_tx);
91 spin_lock_init(&htt->tx_lock);
92 idr_init(&htt->pending_tx);
94 htt->tx_pool = dma_pool_create("ath10k htt tx pool", htt->ar->dev,
95 sizeof(struct ath10k_htt_txbuf), 4, 0);
97 idr_destroy(&htt->pending_tx);
104 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx)
106 struct ath10k *ar = ctx;
107 struct ath10k_htt *htt = &ar->htt;
108 struct htt_tx_done tx_done = {0};
110 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id);
113 tx_done.msdu_id = msdu_id;
115 spin_lock_bh(&htt->tx_lock);
116 ath10k_txrx_tx_unref(htt, &tx_done);
117 spin_unlock_bh(&htt->tx_lock);
122 void ath10k_htt_tx_free(struct ath10k_htt *htt)
124 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar);
125 idr_destroy(&htt->pending_tx);
126 dma_pool_destroy(htt->tx_pool);
129 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
131 dev_kfree_skb_any(skb);
134 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
136 struct ath10k *ar = htt->ar;
142 len += sizeof(cmd->hdr);
143 len += sizeof(cmd->ver_req);
145 skb = ath10k_htc_alloc_skb(ar, len);
150 cmd = (struct htt_cmd *)skb->data;
151 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
153 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
155 dev_kfree_skb_any(skb);
162 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
164 struct ath10k *ar = htt->ar;
165 struct htt_stats_req *req;
170 len += sizeof(cmd->hdr);
171 len += sizeof(cmd->stats_req);
173 skb = ath10k_htc_alloc_skb(ar, len);
178 cmd = (struct htt_cmd *)skb->data;
179 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
181 req = &cmd->stats_req;
183 memset(req, 0, sizeof(*req));
185 /* currently we support only max 8 bit masks so no need to worry
186 * about endian support */
187 req->upload_types[0] = mask;
188 req->reset_types[0] = mask;
189 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
190 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
191 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
193 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
195 ath10k_warn(ar, "failed to send htt type stats request: %d",
197 dev_kfree_skb_any(skb);
204 int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
206 struct ath10k *ar = htt->ar;
209 struct htt_rx_ring_setup_ring *ring;
210 const int num_rx_ring = 1;
217 * the HW expects the buffer to be an integral number of 4-byte
220 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
221 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
223 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
224 + (sizeof(*ring) * num_rx_ring);
225 skb = ath10k_htc_alloc_skb(ar, len);
231 cmd = (struct htt_cmd *)skb->data;
232 ring = &cmd->rx_setup.rings[0];
234 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
235 cmd->rx_setup.hdr.num_rings = 1;
237 /* FIXME: do we need all of this? */
239 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
240 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
241 flags |= HTT_RX_RING_FLAGS_PPDU_START;
242 flags |= HTT_RX_RING_FLAGS_PPDU_END;
243 flags |= HTT_RX_RING_FLAGS_MPDU_START;
244 flags |= HTT_RX_RING_FLAGS_MPDU_END;
245 flags |= HTT_RX_RING_FLAGS_MSDU_START;
246 flags |= HTT_RX_RING_FLAGS_MSDU_END;
247 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
248 flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
249 flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
250 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
251 flags |= HTT_RX_RING_FLAGS_CTRL_RX;
252 flags |= HTT_RX_RING_FLAGS_MGMT_RX;
253 flags |= HTT_RX_RING_FLAGS_NULL_RX;
254 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;
256 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
258 ring->fw_idx_shadow_reg_paddr =
259 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
260 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
261 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
262 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
263 ring->flags = __cpu_to_le16(flags);
264 ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
266 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
268 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
269 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
270 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
271 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
272 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
273 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
274 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
275 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
276 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
277 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
281 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
283 dev_kfree_skb_any(skb);
290 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
291 u8 max_subfrms_ampdu,
292 u8 max_subfrms_amsdu)
294 struct ath10k *ar = htt->ar;
295 struct htt_aggr_conf *aggr_conf;
301 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */
303 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
306 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
309 len = sizeof(cmd->hdr);
310 len += sizeof(cmd->aggr_conf);
312 skb = ath10k_htc_alloc_skb(ar, len);
317 cmd = (struct htt_cmd *)skb->data;
318 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
320 aggr_conf = &cmd->aggr_conf;
321 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
322 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
324 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
325 aggr_conf->max_num_amsdu_subframes,
326 aggr_conf->max_num_ampdu_subframes);
328 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
330 dev_kfree_skb_any(skb);
337 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
339 struct ath10k *ar = htt->ar;
340 struct device *dev = ar->dev;
341 struct sk_buff *txdesc = NULL;
343 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
344 u8 vdev_id = skb_cb->vdev_id;
349 res = ath10k_htt_tx_inc_pending(htt);
353 len += sizeof(cmd->hdr);
354 len += sizeof(cmd->mgmt_tx);
356 spin_lock_bh(&htt->tx_lock);
357 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
359 spin_unlock_bh(&htt->tx_lock);
363 spin_unlock_bh(&htt->tx_lock);
365 txdesc = ath10k_htc_alloc_skb(ar, len);
368 goto err_free_msdu_id;
371 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
373 res = dma_mapping_error(dev, skb_cb->paddr);
375 goto err_free_txdesc;
377 skb_put(txdesc, len);
378 cmd = (struct htt_cmd *)txdesc->data;
379 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX;
380 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
381 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len);
382 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id);
383 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id);
384 memcpy(cmd->mgmt_tx.hdr, msdu->data,
385 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
387 skb_cb->htt.txbuf = NULL;
389 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
396 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
398 dev_kfree_skb_any(txdesc);
400 spin_lock_bh(&htt->tx_lock);
401 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
402 spin_unlock_bh(&htt->tx_lock);
404 ath10k_htt_tx_dec_pending(htt);
409 int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
411 struct ath10k *ar = htt->ar;
412 struct device *dev = ar->dev;
413 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
414 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
415 struct ath10k_hif_sg_item sg_items[2];
416 struct htt_data_tx_desc_frag *frags;
417 u8 vdev_id = skb_cb->vdev_id;
418 u8 tid = skb_cb->htt.tid;
422 u16 msdu_id, flags1 = 0;
423 dma_addr_t paddr = 0;
426 res = ath10k_htt_tx_inc_pending(htt);
430 spin_lock_bh(&htt->tx_lock);
431 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu);
433 spin_unlock_bh(&htt->tx_lock);
437 spin_unlock_bh(&htt->tx_lock);
439 prefetch_len = min(htt->prefetch_len, msdu->len);
440 prefetch_len = roundup(prefetch_len, 4);
442 skb_cb->htt.txbuf = dma_pool_alloc(htt->tx_pool, GFP_ATOMIC,
444 if (!skb_cb->htt.txbuf) {
446 goto err_free_msdu_id;
448 skb_cb->htt.txbuf_paddr = paddr;
450 if ((ieee80211_is_action(hdr->frame_control) ||
451 ieee80211_is_deauth(hdr->frame_control) ||
452 ieee80211_is_disassoc(hdr->frame_control)) &&
453 ieee80211_has_protected(hdr->frame_control))
454 skb_put(msdu, IEEE80211_CCMP_MIC_LEN);
456 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
458 res = dma_mapping_error(dev, skb_cb->paddr);
462 switch (skb_cb->txmode) {
463 case ATH10K_HW_TXRX_RAW:
464 case ATH10K_HW_TXRX_NATIVE_WIFI:
465 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
467 case ATH10K_HW_TXRX_ETHERNET:
468 frags = skb_cb->htt.txbuf->frags;
470 frags[0].paddr = __cpu_to_le32(skb_cb->paddr);
471 frags[0].len = __cpu_to_le32(msdu->len);
475 flags0 |= SM(skb_cb->txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
477 frags_paddr = skb_cb->htt.txbuf_paddr;
479 case ATH10K_HW_TXRX_MGMT:
480 flags0 |= SM(ATH10K_HW_TXRX_MGMT,
481 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
482 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
484 frags_paddr = skb_cb->paddr;
488 /* Normally all commands go through HTC which manages tx credits for
489 * each endpoint and notifies when tx is completed.
491 * HTT endpoint is creditless so there's no need to care about HTC
492 * flags. In that case it is trivial to fill the HTC header here.
494 * MSDU transmission is considered completed upon HTT event. This
495 * implies no relevant resources can be freed until after the event is
496 * received. That's why HTC tx completion handler itself is ignored by
497 * setting NULL to transfer_context for all sg items.
499 * There is simply no point in pushing HTT TX_FRM through HTC tx path
500 * as it's a waste of resources. By bypassing HTC it is possible to
501 * avoid extra memory allocations, compress data structures and thus
502 * improve performance. */
504 skb_cb->htt.txbuf->htc_hdr.eid = htt->eid;
505 skb_cb->htt.txbuf->htc_hdr.len = __cpu_to_le16(
506 sizeof(skb_cb->htt.txbuf->cmd_hdr) +
507 sizeof(skb_cb->htt.txbuf->cmd_tx) +
509 skb_cb->htt.txbuf->htc_hdr.flags = 0;
511 if (!skb_cb->is_protected)
512 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
514 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
515 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
516 if (msdu->ip_summed == CHECKSUM_PARTIAL) {
517 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
518 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
521 /* Prevent firmware from sending up tx inspection requests. There's
522 * nothing ath10k can do with frames requested for inspection so force
523 * it to simply rely a regular tx completion with discard status.
525 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
527 skb_cb->htt.txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
528 skb_cb->htt.txbuf->cmd_tx.flags0 = flags0;
529 skb_cb->htt.txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
530 skb_cb->htt.txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
531 skb_cb->htt.txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
532 skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
533 skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le16(HTT_INVALID_PEERID);
534 skb_cb->htt.txbuf->cmd_tx.freq = __cpu_to_le16(skb_cb->htt.freq);
536 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
537 ath10k_dbg(ar, ATH10K_DBG_HTT,
538 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu freq %hu\n",
539 flags0, flags1, msdu->len, msdu_id, frags_paddr,
540 (u32)skb_cb->paddr, vdev_id, tid, skb_cb->htt.freq);
541 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
542 msdu->data, msdu->len);
543 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
544 trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
546 sg_items[0].transfer_id = 0;
547 sg_items[0].transfer_context = NULL;
548 sg_items[0].vaddr = &skb_cb->htt.txbuf->htc_hdr;
549 sg_items[0].paddr = skb_cb->htt.txbuf_paddr +
550 sizeof(skb_cb->htt.txbuf->frags);
551 sg_items[0].len = sizeof(skb_cb->htt.txbuf->htc_hdr) +
552 sizeof(skb_cb->htt.txbuf->cmd_hdr) +
553 sizeof(skb_cb->htt.txbuf->cmd_tx);
555 sg_items[1].transfer_id = 0;
556 sg_items[1].transfer_context = NULL;
557 sg_items[1].vaddr = msdu->data;
558 sg_items[1].paddr = skb_cb->paddr;
559 sg_items[1].len = prefetch_len;
561 res = ath10k_hif_tx_sg(htt->ar,
562 htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
563 sg_items, ARRAY_SIZE(sg_items));
570 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
572 dma_pool_free(htt->tx_pool,
574 skb_cb->htt.txbuf_paddr);
576 spin_lock_bh(&htt->tx_lock);
577 ath10k_htt_tx_free_msdu_id(htt, msdu_id);
578 spin_unlock_bh(&htt->tx_lock);
580 ath10k_htt_tx_dec_pending(htt);