4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/delay.h>
32 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
34 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
35 const struct ath5k_rf_reg *rf_regs,
36 u32 val, u8 reg_id, bool set)
38 const struct ath5k_rf_reg *rfreg = NULL;
39 u8 offset, bank, num_bits, col, position;
41 u32 mask, data, last_bit, bits_shifted, first_bit;
47 rfb = ah->ah_rf_banks;
49 for (i = 0; i < ah->ah_rf_regs_count; i++) {
50 if (rf_regs[i].index == reg_id) {
56 if (rfb == NULL || rfreg == NULL) {
57 ATH5K_PRINTF("Rf register not found!\n");
58 /* should not happen */
63 num_bits = rfreg->field.len;
64 first_bit = rfreg->field.pos;
65 col = rfreg->field.col;
67 /* first_bit is an offset from bank's
68 * start. Since we have all banks on
69 * the same array, we use this offset
70 * to mark each bank's start */
71 offset = ah->ah_offset[bank];
74 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
75 ATH5K_PRINTF("invalid values at offset %u\n", offset);
79 entry = ((first_bit - 1) / 8) + offset;
80 position = (first_bit - 1) % 8;
83 data = ath5k_hw_bitswap(val, num_bits);
85 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
86 position = 0, entry++) {
88 last_bit = (position + bits_left > 8) ? 8 :
91 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
96 rfb[entry] |= ((data << position) << (col * 8)) & mask;
97 data >>= (8 - position);
99 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
101 bits_shifted += last_bit - position;
104 bits_left -= 8 - position;
107 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
112 /**********************\
113 * RF Gain optimization *
114 \**********************/
117 * This code is used to optimize rf gain on different environments
118 * (temperature mostly) based on feedback from a power detector.
120 * It's only used on RF5111 and RF5112, later RF chips seem to have
121 * auto adjustment on hw -notice they have a much smaller BANK 7 and
122 * no gain optimization ladder-.
124 * For more infos check out this patent doc
125 * http://www.freepatentsonline.com/7400691.html
127 * This paper describes power drops as seen on the receiver due to
129 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
130 * %20of%20Power%20Control.pdf
132 * And this is the MadWiFi bug entry related to the above
133 * http://madwifi-project.org/ticket/1659
134 * with various measurements and diagrams
136 * TODO: Deal with power drops due to probes by setting an apropriate
137 * tx power on the probe packets ! Make this part of the calibration process.
140 /* Initialize ah_gain durring attach */
141 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
143 /* Initialize the gain optimization values */
144 switch (ah->ah_radio) {
146 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
147 ah->ah_gain.g_low = 20;
148 ah->ah_gain.g_high = 35;
149 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
152 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
153 ah->ah_gain.g_low = 20;
154 ah->ah_gain.g_high = 85;
155 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
164 /* Schedule a gain probe check on the next transmited packet.
165 * That means our next packet is going to be sent with lower
166 * tx power and a Peak to Average Power Detector (PAPD) will try
167 * to measure the gain.
169 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
170 * just after we enable the probe so that we don't mess with
171 * standard traffic ? Maybe it's time to use sw interrupts and
172 * a probe tasklet !!!
174 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
177 /* Skip if gain calibration is inactive or
178 * we already handle a probe request */
179 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
182 /* Send the packet with 2dB below max power as
183 * patent doc suggest */
184 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
185 AR5K_PHY_PAPD_PROBE_TXPOWER) |
186 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
188 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
192 /* Calculate gain_F measurement correction
193 * based on the current step for RF5112 rev. 2 */
194 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
198 const struct ath5k_gain_opt *go;
199 const struct ath5k_gain_opt_step *g_step;
200 const struct ath5k_rf_reg *rf_regs;
202 /* Only RF5112 Rev. 2 supports it */
203 if ((ah->ah_radio != AR5K_RF5112) ||
204 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
207 go = &rfgain_opt_5112;
208 rf_regs = rf_regs_5112a;
209 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
211 g_step = &go->go_step[ah->ah_gain.g_step_idx];
213 if (ah->ah_rf_banks == NULL)
216 rf = ah->ah_rf_banks;
217 ah->ah_gain.g_f_corr = 0;
219 /* No VGA (Variable Gain Amplifier) override, skip */
220 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
223 /* Mix gain stepping */
224 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
226 /* Mix gain override */
227 mix = g_step->gos_param[0];
231 ah->ah_gain.g_f_corr = step * 2;
234 ah->ah_gain.g_f_corr = (step - 5) * 2;
237 ah->ah_gain.g_f_corr = step;
240 ah->ah_gain.g_f_corr = 0;
244 return ah->ah_gain.g_f_corr;
247 /* Check if current gain_F measurement is in the range of our
248 * power detector windows. If we get a measurement outside range
249 * we know it's not accurate (detectors can't measure anything outside
250 * their detection window) so we must ignore it */
251 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
253 const struct ath5k_rf_reg *rf_regs;
254 u32 step, mix_ovr, level[4];
257 if (ah->ah_rf_banks == NULL)
260 rf = ah->ah_rf_banks;
262 if (ah->ah_radio == AR5K_RF5111) {
264 rf_regs = rf_regs_5111;
265 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
267 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
271 level[1] = (step == 63) ? 50 : step + 4;
272 level[2] = (step != 63) ? 64 : level[0];
273 level[3] = level[2] + 50 ;
275 ah->ah_gain.g_high = level[3] -
276 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
277 ah->ah_gain.g_low = level[0] +
278 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
281 rf_regs = rf_regs_5112;
282 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
284 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
287 level[0] = level[2] = 0;
290 level[1] = level[3] = 83;
292 level[1] = level[3] = 107;
293 ah->ah_gain.g_high = 55;
297 return (ah->ah_gain.g_current >= level[0] &&
298 ah->ah_gain.g_current <= level[1]) ||
299 (ah->ah_gain.g_current >= level[2] &&
300 ah->ah_gain.g_current <= level[3]);
303 /* Perform gain_F adjustment by choosing the right set
304 * of parameters from rf gain optimization ladder */
305 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
307 const struct ath5k_gain_opt *go;
308 const struct ath5k_gain_opt_step *g_step;
311 switch (ah->ah_radio) {
313 go = &rfgain_opt_5111;
316 go = &rfgain_opt_5112;
322 g_step = &go->go_step[ah->ah_gain.g_step_idx];
324 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
326 /* Reached maximum */
327 if (ah->ah_gain.g_step_idx == 0)
330 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
331 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
332 ah->ah_gain.g_step_idx > 0;
333 g_step = &go->go_step[ah->ah_gain.g_step_idx])
334 ah->ah_gain.g_target -= 2 *
335 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
342 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
344 /* Reached minimum */
345 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
348 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
349 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
350 ah->ah_gain.g_step_idx < go->go_steps_count-1;
351 g_step = &go->go_step[ah->ah_gain.g_step_idx])
352 ah->ah_gain.g_target -= 2 *
353 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
361 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
362 "ret %d, gain step %u, current gain %u, target gain %u\n",
363 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
364 ah->ah_gain.g_target);
369 /* Main callback for thermal rf gain calibration engine
370 * Check for a new gain reading and schedule an adjustment
373 * TODO: Use sw interrupt to schedule reset if gain_F needs
375 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
378 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
380 ATH5K_TRACE(ah->ah_sc);
382 if (ah->ah_rf_banks == NULL ||
383 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
384 return AR5K_RFGAIN_INACTIVE;
386 /* No check requested, either engine is inactive
387 * or an adjustment is already requested */
388 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
391 /* Read the PAPD (Peak to Average Power Detector)
393 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
395 /* No probe is scheduled, read gain_F measurement */
396 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
397 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
398 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
400 /* If tx packet is CCK correct the gain_F measurement
401 * by cck ofdm gain delta */
402 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
403 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
404 ah->ah_gain.g_current +=
405 ee->ee_cck_ofdm_gain_delta;
407 ah->ah_gain.g_current +=
408 AR5K_GAIN_CCK_PROBE_CORR;
411 /* Further correct gain_F measurement for
413 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
414 ath5k_hw_rf_gainf_corr(ah);
415 ah->ah_gain.g_current =
416 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
417 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
421 /* Check if measurement is ok and if we need
422 * to adjust gain, schedule a gain adjustment,
423 * else switch back to the acive state */
424 if (ath5k_hw_rf_check_gainf_readback(ah) &&
425 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
426 ath5k_hw_rf_gainf_adjust(ah)) {
427 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
429 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
434 return ah->ah_gain.g_state;
437 /* Write initial rf gain table to set the RF sensitivity
438 * this one works on all RF chips and has nothing to do
439 * with gain_F calibration */
440 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
442 const struct ath5k_ini_rfgain *ath5k_rfg;
443 unsigned int i, size;
445 switch (ah->ah_radio) {
447 ath5k_rfg = rfgain_5111;
448 size = ARRAY_SIZE(rfgain_5111);
451 ath5k_rfg = rfgain_5112;
452 size = ARRAY_SIZE(rfgain_5112);
455 ath5k_rfg = rfgain_2413;
456 size = ARRAY_SIZE(rfgain_2413);
459 ath5k_rfg = rfgain_2316;
460 size = ARRAY_SIZE(rfgain_2316);
463 ath5k_rfg = rfgain_5413;
464 size = ARRAY_SIZE(rfgain_5413);
468 ath5k_rfg = rfgain_2425;
469 size = ARRAY_SIZE(rfgain_2425);
476 case AR5K_INI_RFGAIN_2GHZ:
477 case AR5K_INI_RFGAIN_5GHZ:
483 for (i = 0; i < size; i++) {
485 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
486 (u32)ath5k_rfg[i].rfg_register);
494 /********************\
495 * RF Registers setup *
496 \********************/
500 * Setup RF registers by writing rf buffer on hw
502 int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
505 const struct ath5k_rf_reg *rf_regs;
506 const struct ath5k_ini_rfbuffer *ini_rfb;
507 const struct ath5k_gain_opt *go = NULL;
508 const struct ath5k_gain_opt_step *g_step;
509 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
512 int i, obdb = -1, bank = -1;
514 switch (ah->ah_radio) {
516 rf_regs = rf_regs_5111;
517 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
519 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
520 go = &rfgain_opt_5111;
523 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
524 rf_regs = rf_regs_5112a;
525 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
527 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
529 rf_regs = rf_regs_5112;
530 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
532 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
534 go = &rfgain_opt_5112;
537 rf_regs = rf_regs_2413;
538 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
540 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
543 rf_regs = rf_regs_2316;
544 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
546 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
549 rf_regs = rf_regs_5413;
550 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
552 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
555 rf_regs = rf_regs_2425;
556 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
558 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
561 rf_regs = rf_regs_2425;
562 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
563 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
565 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
568 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
575 /* If it's the first time we set rf buffer, allocate
576 * ah->ah_rf_banks based on ah->ah_rf_banks_size
578 if (ah->ah_rf_banks == NULL) {
579 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
581 if (ah->ah_rf_banks == NULL) {
582 ATH5K_ERR(ah->ah_sc, "out of memory\n");
587 /* Copy values to modify them */
588 rfb = ah->ah_rf_banks;
590 for (i = 0; i < ah->ah_rf_banks_size; i++) {
591 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
592 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
596 /* Bank changed, write down the offset */
597 if (bank != ini_rfb[i].rfb_bank) {
598 bank = ini_rfb[i].rfb_bank;
599 ah->ah_offset[bank] = i;
602 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
605 /* Set Output and Driver bias current (OB/DB) */
606 if (channel->hw_value & CHANNEL_2GHZ) {
608 if (channel->hw_value & CHANNEL_CCK)
609 ee_mode = AR5K_EEPROM_MODE_11B;
611 ee_mode = AR5K_EEPROM_MODE_11G;
613 /* For RF511X/RF211X combination we
614 * use b_OB and b_DB parameters stored
615 * in eeprom on ee->ee_ob[ee_mode][0]
617 * For all other chips we use OB/DB for 2Ghz
618 * stored in the b/g modal section just like
619 * 802.11a on ee->ee_ob[ee_mode][1] */
620 if ((ah->ah_radio == AR5K_RF5111) ||
621 (ah->ah_radio == AR5K_RF5112))
626 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
627 AR5K_RF_OB_2GHZ, true);
629 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
630 AR5K_RF_DB_2GHZ, true);
632 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
633 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
634 (ah->ah_radio == AR5K_RF5111)) {
636 /* For 11a, Turbo and XR we need to choose
637 * OB/DB based on frequency range */
638 ee_mode = AR5K_EEPROM_MODE_11A;
639 obdb = channel->center_freq >= 5725 ? 3 :
640 (channel->center_freq >= 5500 ? 2 :
641 (channel->center_freq >= 5260 ? 1 :
642 (channel->center_freq > 4000 ? 0 : -1)));
647 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
648 AR5K_RF_OB_5GHZ, true);
650 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
651 AR5K_RF_DB_5GHZ, true);
654 g_step = &go->go_step[ah->ah_gain.g_step_idx];
656 /* Bank Modifications (chip-specific) */
657 if (ah->ah_radio == AR5K_RF5111) {
659 /* Set gain_F settings according to current step */
660 if (channel->hw_value & CHANNEL_OFDM) {
662 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
663 AR5K_PHY_FRAME_CTL_TX_CLIP,
664 g_step->gos_param[0]);
666 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
667 AR5K_RF_PWD_90, true);
669 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
670 AR5K_RF_PWD_84, true);
672 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
673 AR5K_RF_RFGAIN_SEL, true);
675 /* We programmed gain_F parameters, switch back
677 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
683 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
684 AR5K_RF_PWD_XPD, true);
686 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
687 AR5K_RF_XPD_GAIN, true);
689 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
690 AR5K_RF_GAIN_I, true);
692 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
693 AR5K_RF_PLO_SEL, true);
695 /* TODO: Half/quarter channel support */
698 if (ah->ah_radio == AR5K_RF5112) {
700 /* Set gain_F settings according to current step */
701 if (channel->hw_value & CHANNEL_OFDM) {
703 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
704 AR5K_RF_MIXGAIN_OVR, true);
706 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
707 AR5K_RF_PWD_138, true);
709 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
710 AR5K_RF_PWD_137, true);
712 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
713 AR5K_RF_PWD_136, true);
715 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
716 AR5K_RF_PWD_132, true);
718 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
719 AR5K_RF_PWD_131, true);
721 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
722 AR5K_RF_PWD_130, true);
724 /* We programmed gain_F parameters, switch back
726 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
731 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
732 AR5K_RF_XPD_SEL, true);
734 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
735 /* Rev. 1 supports only one xpd */
736 ath5k_hw_rfb_op(ah, rf_regs,
737 ee->ee_x_gain[ee_mode],
738 AR5K_RF_XPD_GAIN, true);
741 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
742 if (ee->ee_pd_gains[ee_mode] > 1) {
743 ath5k_hw_rfb_op(ah, rf_regs,
745 AR5K_RF_PD_GAIN_LO, true);
746 ath5k_hw_rfb_op(ah, rf_regs,
748 AR5K_RF_PD_GAIN_HI, true);
750 ath5k_hw_rfb_op(ah, rf_regs,
752 AR5K_RF_PD_GAIN_LO, true);
753 ath5k_hw_rfb_op(ah, rf_regs,
755 AR5K_RF_PD_GAIN_HI, true);
758 /* Lower synth voltage on Rev 2 */
759 ath5k_hw_rfb_op(ah, rf_regs, 2,
760 AR5K_RF_HIGH_VC_CP, true);
762 ath5k_hw_rfb_op(ah, rf_regs, 2,
763 AR5K_RF_MID_VC_CP, true);
765 ath5k_hw_rfb_op(ah, rf_regs, 2,
766 AR5K_RF_LOW_VC_CP, true);
768 ath5k_hw_rfb_op(ah, rf_regs, 2,
769 AR5K_RF_PUSH_UP, true);
771 /* Decrease power consumption on 5213+ BaseBand */
772 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
773 ath5k_hw_rfb_op(ah, rf_regs, 1,
774 AR5K_RF_PAD2GND, true);
776 ath5k_hw_rfb_op(ah, rf_regs, 1,
777 AR5K_RF_XB2_LVL, true);
779 ath5k_hw_rfb_op(ah, rf_regs, 1,
780 AR5K_RF_XB5_LVL, true);
782 ath5k_hw_rfb_op(ah, rf_regs, 1,
783 AR5K_RF_PWD_167, true);
785 ath5k_hw_rfb_op(ah, rf_regs, 1,
786 AR5K_RF_PWD_166, true);
790 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
791 AR5K_RF_GAIN_I, true);
793 /* TODO: Half/quarter channel support */
797 if (ah->ah_radio == AR5K_RF5413 &&
798 channel->hw_value & CHANNEL_2GHZ) {
800 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
803 /* Set optimum value for early revisions (on pci-e chips) */
804 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
805 ah->ah_mac_srev < AR5K_SREV_AR5413)
806 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
807 AR5K_RF_PWD_ICLOBUF_2G, true);
811 /* Write RF banks on hw */
812 for (i = 0; i < ah->ah_rf_banks_size; i++) {
814 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
821 /**************************\
822 PHY/RF channel functions
823 \**************************/
826 * Check if a channel is supported
828 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
830 /* Check if the channel is in our supported range */
831 if (flags & CHANNEL_2GHZ) {
832 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
833 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
835 } else if (flags & CHANNEL_5GHZ)
836 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
837 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
844 * Convertion needed for RF5110
846 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
851 * Convert IEEE channel/MHz to an internal channel value used
852 * by the AR5210 chipset. This has not been verified with
853 * newer chipsets like the AR5212A who have a completely
854 * different RF/PHY part.
856 athchan = (ath5k_hw_bitswap(
857 (ieee80211_frequency_to_channel(
858 channel->center_freq) - 24) / 2, 5)
859 << 1) | (1 << 6) | 0x1;
864 * Set channel on RF5110
866 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
867 struct ieee80211_channel *channel)
872 * Set the channel and wait
874 data = ath5k_hw_rf5110_chan2athchan(channel);
875 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
876 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
883 * Convertion needed for 5111
885 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
886 struct ath5k_athchan_2ghz *athchan)
890 /* Cast this value to catch negative channel numbers (>= -19) */
894 * Map 2GHz IEEE channel to 5GHz Atheros channel
897 athchan->a2_athchan = 115 + channel;
898 athchan->a2_flags = 0x46;
899 } else if (channel == 14) {
900 athchan->a2_athchan = 124;
901 athchan->a2_flags = 0x44;
902 } else if (channel >= 15 && channel <= 26) {
903 athchan->a2_athchan = ((channel - 14) * 4) + 132;
904 athchan->a2_flags = 0x46;
912 * Set channel on 5111
914 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
915 struct ieee80211_channel *channel)
917 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
918 unsigned int ath5k_channel =
919 ieee80211_frequency_to_channel(channel->center_freq);
920 u32 data0, data1, clock;
924 * Set the channel on the RF5111 radio
928 if (channel->hw_value & CHANNEL_2GHZ) {
929 /* Map 2GHz channel to 5GHz Atheros channel ID */
930 ret = ath5k_hw_rf5111_chan2athchan(
931 ieee80211_frequency_to_channel(channel->center_freq),
932 &ath5k_channel_2ghz);
936 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
937 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
941 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
943 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
944 (clock << 1) | (1 << 10) | 1;
947 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
948 << 2) | (clock << 1) | (1 << 10) | 1;
951 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
953 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
954 AR5K_RF_BUFFER_CONTROL_3);
960 * Set channel on 5112 and newer
962 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
963 struct ieee80211_channel *channel)
965 u32 data, data0, data1, data2;
968 data = data0 = data1 = data2 = 0;
969 c = channel->center_freq;
972 if (!((c - 2224) % 5)) {
973 data0 = ((2 * (c - 704)) - 3040) / 10;
975 } else if (!((c - 2192) % 5)) {
976 data0 = ((2 * (c - 672)) - 3040) / 10;
981 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
982 } else if ((c - (c % 5)) != 2 || c > 5435) {
983 if (!(c % 20) && c >= 5120) {
984 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
985 data2 = ath5k_hw_bitswap(3, 2);
986 } else if (!(c % 10)) {
987 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
988 data2 = ath5k_hw_bitswap(2, 2);
989 } else if (!(c % 5)) {
990 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
991 data2 = ath5k_hw_bitswap(1, 2);
995 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
996 data2 = ath5k_hw_bitswap(0, 2);
999 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1001 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1002 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1008 * Set the channel on the RF2425
1010 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1011 struct ieee80211_channel *channel)
1013 u32 data, data0, data2;
1016 data = data0 = data2 = 0;
1017 c = channel->center_freq;
1020 data0 = ath5k_hw_bitswap((c - 2272), 8);
1023 } else if ((c - (c % 5)) != 2 || c > 5435) {
1024 if (!(c % 20) && c < 5120)
1025 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1027 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1029 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1032 data2 = ath5k_hw_bitswap(1, 2);
1034 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1035 data2 = ath5k_hw_bitswap(0, 2);
1038 data = (data0 << 4) | data2 << 2 | 0x1001;
1040 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1041 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1047 * Set a channel on the radio chip
1049 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1053 * Check bounds supported by the PHY (we don't care about regultory
1054 * restrictions at this point). Note: hw_value already has the band
1055 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1056 * of the band by that */
1057 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1058 ATH5K_ERR(ah->ah_sc,
1059 "channel frequency (%u MHz) out of supported "
1061 channel->center_freq);
1066 * Set the channel and wait
1068 switch (ah->ah_radio) {
1070 ret = ath5k_hw_rf5110_channel(ah, channel);
1073 ret = ath5k_hw_rf5111_channel(ah, channel);
1076 ret = ath5k_hw_rf2425_channel(ah, channel);
1079 ret = ath5k_hw_rf5112_channel(ah, channel);
1086 /* Set JAPAN setting for channel 14 */
1087 if (channel->center_freq == 2484) {
1088 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1089 AR5K_PHY_CCKTXCTL_JAPAN);
1091 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1092 AR5K_PHY_CCKTXCTL_WORLD);
1095 ah->ah_current_channel = channel;
1096 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1105 static int sign_extend(int val, const int nbits)
1107 int order = BIT(nbits-1);
1108 return (val ^ order) - order;
1111 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1115 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1116 return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
1119 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1123 ah->ah_nfcal_hist.index = 0;
1124 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1125 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1128 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1130 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1131 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1132 hist->nfval[hist->index] = noise_floor;
1135 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1137 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1141 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1142 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1143 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1144 if (sort[j] > sort[j-1]) {
1146 sort[j] = sort[j-1];
1151 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1152 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1153 "cal %d:%d\n", i, sort[i]);
1155 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1159 * When we tell the hardware to perform a noise floor calibration
1160 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1161 * sample-and-hold the minimum noise level seen at the antennas.
1162 * This value is then stored in a ring buffer of recently measured
1163 * noise floor values so we have a moving window of the last few
1166 * The median of the values in the history is then loaded into the
1167 * hardware for its own use for RSSI and CCA measurements.
1169 static void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1171 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1176 /* keep last value if calibration hasn't completed */
1177 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1178 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1179 "NF did not complete in calibration window\n");
1184 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1188 ee_mode = AR5K_EEPROM_MODE_11A;
1192 ee_mode = AR5K_EEPROM_MODE_11G;
1196 ee_mode = AR5K_EEPROM_MODE_11B;
1201 /* completed NF calibration, test threshold */
1202 nf = ath5k_hw_read_measured_noise_floor(ah);
1203 threshold = ee->ee_noise_floor_thr[ee_mode];
1205 if (nf > threshold) {
1206 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1207 "noise floor failure detected; "
1208 "read %d, threshold %d\n",
1211 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1214 ath5k_hw_update_nfcal_hist(ah, nf);
1215 nf = ath5k_hw_get_median_noise_floor(ah);
1217 /* load noise floor (in .5 dBm) so the hardware will use it */
1218 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1219 val |= (nf * 2) & AR5K_PHY_NF_M;
1220 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1222 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1223 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1225 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1229 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1230 * so that we're not capped by the median we just loaded.
1231 * This will be used as the initial value for the next noise
1232 * floor calibration.
1234 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1235 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1236 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1237 AR5K_PHY_AGCCTL_NF_EN |
1238 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1239 AR5K_PHY_AGCCTL_NF);
1241 ah->ah_noise_floor = nf;
1243 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1244 "noise floor calibrated: %d\n", nf);
1248 * Perform a PHY calibration on RF5110
1249 * -Fix BPSK/QAM Constellation (I/Q correction)
1250 * -Calculate Noise Floor
1252 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1253 struct ieee80211_channel *channel)
1255 u32 phy_sig, phy_agc, phy_sat, beacon;
1259 * Disable beacons and RX/TX queues, wait
1261 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1262 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1263 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1264 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1269 * Set the channel (with AGC turned off)
1271 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1273 ret = ath5k_hw_channel(ah, channel);
1276 * Activate PHY and wait
1278 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1281 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1287 * Calibrate the radio chip
1290 /* Remember normal state */
1291 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1292 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1293 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1295 /* Update radio registers */
1296 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1297 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1299 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1300 AR5K_PHY_AGCCOARSE_LO)) |
1301 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1302 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1304 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1305 AR5K_PHY_ADCSAT_THR)) |
1306 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1307 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1311 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1313 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1314 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1319 * Enable calibration and wait until completion
1321 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1323 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1324 AR5K_PHY_AGCCTL_CAL, 0, false);
1326 /* Reset to normal state */
1327 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1328 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1329 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1332 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1333 channel->center_freq);
1337 ath5k_hw_update_noise_floor(ah);
1340 * Re-enable RX/TX and beacons
1342 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1343 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1344 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1350 * Perform a PHY calibration on RF5111/5112 and newer chips
1352 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1353 struct ieee80211_channel *channel)
1356 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1358 ATH5K_TRACE(ah->ah_sc);
1360 if (!ah->ah_calibration ||
1361 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1364 /* Calibration has finished, get the results and re-run */
1366 /* work around empty results which can apparently happen on 5212 */
1367 for (i = 0; i <= 10; i++) {
1368 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1369 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1370 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1371 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1372 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1377 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1379 if (ah->ah_version == AR5K_AR5211)
1380 q_coffd = q_pwr >> 6;
1382 q_coffd = q_pwr >> 7;
1384 /* protect against divide by 0 and loss of sign bits */
1385 if (i_coffd == 0 || q_coffd < 2)
1388 i_coff = (-iq_corr) / i_coffd;
1389 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1391 q_coff = (i_pwr / q_coffd) - 128;
1392 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1394 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1395 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1396 i_coff, q_coff, i_coffd, q_coffd);
1398 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1399 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1400 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1401 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1403 /* Re-enable calibration -if we don't we'll commit
1404 * the same values again and again */
1405 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1406 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1407 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1411 /* TODO: Separate noise floor calibration from I/Q calibration
1412 * since noise floor calibration interrupts rx path while I/Q
1413 * calibration doesn't. We don't need to run noise floor calibration
1414 * as often as I/Q calibration.*/
1415 ath5k_hw_update_noise_floor(ah);
1417 /* Initiate a gain_F calibration */
1418 ath5k_hw_request_rfgain_probe(ah);
1424 * Perform a PHY calibration
1426 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1427 struct ieee80211_channel *channel)
1431 if (ah->ah_radio == AR5K_RF5110)
1432 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1434 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1439 /***************************\
1440 * Spur mitigation functions *
1441 \***************************/
1443 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1444 struct ieee80211_channel *channel)
1448 if ((ah->ah_radio == AR5K_RF5112) ||
1449 (ah->ah_radio == AR5K_RF5413) ||
1450 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1455 if ((channel->center_freq % refclk_freq != 0) &&
1456 ((channel->center_freq % refclk_freq < 10) ||
1457 (channel->center_freq % refclk_freq > 22)))
1464 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1465 struct ieee80211_channel *channel)
1467 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1468 u32 mag_mask[4] = {0, 0, 0, 0};
1469 u32 pilot_mask[2] = {0, 0};
1470 /* Note: fbin values are scaled up by 2 */
1471 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1472 s32 spur_delta_phase, spur_freq_sigma_delta;
1473 s32 spur_offset, num_symbols_x16;
1474 u8 num_symbol_offsets, i, freq_band;
1476 /* Convert current frequency to fbin value (the same way channels
1477 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1478 * up by 2 so we can compare it later */
1479 if (channel->hw_value & CHANNEL_2GHZ) {
1480 chan_fbin = (channel->center_freq - 2300) * 10;
1481 freq_band = AR5K_EEPROM_BAND_2GHZ;
1483 chan_fbin = (channel->center_freq - 4900) * 10;
1484 freq_band = AR5K_EEPROM_BAND_5GHZ;
1487 /* Check if any spur_chan_fbin from EEPROM is
1488 * within our current channel's spur detection range */
1489 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1490 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1491 /* XXX: Half/Quarter channels ?*/
1492 if (channel->hw_value & CHANNEL_TURBO)
1493 spur_detection_window *= 2;
1495 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1496 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1498 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1499 * so it's zero if we got nothing from EEPROM */
1500 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1501 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1505 if ((chan_fbin - spur_detection_window <=
1506 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1507 (chan_fbin + spur_detection_window >=
1508 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1509 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1514 /* We need to enable spur filter for this channel */
1515 if (spur_chan_fbin) {
1516 spur_offset = spur_chan_fbin - chan_fbin;
1519 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1520 * spur_delta_phase -> spur_offset / chip_freq << 11
1521 * Note: Both values have 100KHz resolution
1523 /* XXX: Half/Quarter rate channels ? */
1524 switch (channel->hw_value) {
1526 /* Both sample_freq and chip_freq are 40MHz */
1527 spur_delta_phase = (spur_offset << 17) / 25;
1528 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1529 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1532 /* sample_freq -> 40MHz chip_freq -> 44MHz
1533 * (for b compatibility) */
1534 spur_freq_sigma_delta = (spur_offset << 8) / 55;
1535 spur_delta_phase = (spur_offset << 17) / 25;
1536 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1540 /* Both sample_freq and chip_freq are 80MHz */
1541 spur_delta_phase = (spur_offset << 16) / 25;
1542 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1543 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1549 /* Calculate pilot and magnitude masks */
1551 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1552 * and divide by symbol_width to find how many symbols we have
1553 * Note: number of symbols is scaled up by 16 */
1554 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1556 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1557 if (!(num_symbols_x16 & 0xF))
1559 num_symbol_offsets = 3;
1562 num_symbol_offsets = 4;
1564 for (i = 0; i < num_symbol_offsets; i++) {
1566 /* Calculate pilot mask */
1568 (num_symbols_x16 / 16) + i + 25;
1570 /* Pilot magnitude mask seems to be a way to
1571 * declare the boundaries for our detection
1572 * window or something, it's 2 for the middle
1573 * value(s) where the symbol is expected to be
1574 * and 1 on the boundary values */
1576 (i == 0 || i == (num_symbol_offsets - 1))
1579 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1580 if (curr_sym_off <= 25)
1581 pilot_mask[0] |= 1 << curr_sym_off;
1582 else if (curr_sym_off >= 27)
1583 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1584 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1585 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1587 /* Calculate magnitude mask (for viterbi decoder) */
1588 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1590 plt_mag_map << (curr_sym_off + 1) * 2;
1591 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1593 plt_mag_map << (curr_sym_off - 15) * 2;
1594 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1596 plt_mag_map << (curr_sym_off - 31) * 2;
1597 else if (curr_sym_off >= 46 && curr_sym_off <= 53)
1599 plt_mag_map << (curr_sym_off - 47) * 2;
1603 /* Write settings on hw to enable spur filter */
1604 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1605 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1606 /* XXX: Self correlator also ? */
1607 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1608 AR5K_PHY_IQ_PILOT_MASK_EN |
1609 AR5K_PHY_IQ_CHAN_MASK_EN |
1610 AR5K_PHY_IQ_SPUR_FILT_EN);
1612 /* Set delta phase and freq sigma delta */
1613 ath5k_hw_reg_write(ah,
1614 AR5K_REG_SM(spur_delta_phase,
1615 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1616 AR5K_REG_SM(spur_freq_sigma_delta,
1617 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1618 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1619 AR5K_PHY_TIMING_11);
1621 /* Write pilot masks */
1622 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1623 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1624 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1627 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1628 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1629 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1632 /* Write magnitude masks */
1633 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1634 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1635 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1636 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1637 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1640 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1641 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1642 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1643 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1644 AR5K_PHY_BIN_MASK2_4_MASK_4,
1647 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1648 AR5K_PHY_IQ_SPUR_FILT_EN) {
1649 /* Clean up spur mitigation settings and disable fliter */
1650 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1651 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1652 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1653 AR5K_PHY_IQ_PILOT_MASK_EN |
1654 AR5K_PHY_IQ_CHAN_MASK_EN |
1655 AR5K_PHY_IQ_SPUR_FILT_EN);
1656 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1658 /* Clear pilot masks */
1659 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1660 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1661 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1664 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1665 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1666 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1669 /* Clear magnitude masks */
1670 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1671 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1672 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1673 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1674 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1677 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1678 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1679 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1680 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1681 AR5K_PHY_BIN_MASK2_4_MASK_4,
1686 /********************\
1688 \********************/
1690 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1692 ATH5K_TRACE(ah->ah_sc);
1694 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1700 * Get the PHY Chip revision
1702 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1708 ATH5K_TRACE(ah->ah_sc);
1711 * Set the radio chip access register
1715 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1718 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1726 /* ...wait until PHY is ready and read the selected radio revision */
1727 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1729 for (i = 0; i < 8; i++)
1730 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1732 if (ah->ah_version == AR5K_AR5210) {
1733 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1734 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1736 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1737 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1738 ((srev & 0x0f) << 4), 8);
1741 /* Reset to the 5GHz mode */
1742 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1751 static void /*TODO:Boundary check*/
1752 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1754 ATH5K_TRACE(ah->ah_sc);
1756 if (ah->ah_version != AR5K_AR5210)
1757 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1761 * Enable/disable fast rx antenna diversity
1764 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1767 case AR5K_EEPROM_MODE_11G:
1768 /* XXX: This is set to
1769 * disabled on initvals !!! */
1770 case AR5K_EEPROM_MODE_11A:
1772 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1773 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1775 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1776 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1778 case AR5K_EEPROM_MODE_11B:
1779 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1780 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1787 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1788 AR5K_PHY_RESTART_DIV_GC, 0xc);
1790 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1791 AR5K_PHY_FAST_ANT_DIV_EN);
1793 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1794 AR5K_PHY_RESTART_DIV_GC, 0x8);
1796 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1797 AR5K_PHY_FAST_ANT_DIV_EN);
1802 * Set antenna operating mode
1805 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1807 struct ieee80211_channel *channel = ah->ah_current_channel;
1808 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1809 bool use_def_for_sg;
1810 u8 def_ant, tx_ant, ee_mode;
1813 def_ant = ah->ah_def_ant;
1815 ATH5K_TRACE(ah->ah_sc);
1817 switch (channel->hw_value & CHANNEL_MODES) {
1821 ee_mode = AR5K_EEPROM_MODE_11A;
1825 ee_mode = AR5K_EEPROM_MODE_11G;
1828 ee_mode = AR5K_EEPROM_MODE_11B;
1831 ATH5K_ERR(ah->ah_sc,
1832 "invalid channel: %d\n", channel->center_freq);
1837 case AR5K_ANTMODE_DEFAULT:
1839 use_def_for_tx = false;
1840 update_def_on_tx = false;
1841 use_def_for_rts = false;
1842 use_def_for_sg = false;
1845 case AR5K_ANTMODE_FIXED_A:
1848 use_def_for_tx = true;
1849 update_def_on_tx = false;
1850 use_def_for_rts = true;
1851 use_def_for_sg = true;
1854 case AR5K_ANTMODE_FIXED_B:
1857 use_def_for_tx = true;
1858 update_def_on_tx = false;
1859 use_def_for_rts = true;
1860 use_def_for_sg = true;
1863 case AR5K_ANTMODE_SINGLE_AP:
1864 def_ant = 1; /* updated on tx */
1866 use_def_for_tx = true;
1867 update_def_on_tx = true;
1868 use_def_for_rts = true;
1869 use_def_for_sg = true;
1872 case AR5K_ANTMODE_SECTOR_AP:
1873 tx_ant = 1; /* variable */
1874 use_def_for_tx = false;
1875 update_def_on_tx = false;
1876 use_def_for_rts = true;
1877 use_def_for_sg = false;
1880 case AR5K_ANTMODE_SECTOR_STA:
1881 tx_ant = 1; /* variable */
1882 use_def_for_tx = true;
1883 update_def_on_tx = false;
1884 use_def_for_rts = true;
1885 use_def_for_sg = false;
1888 case AR5K_ANTMODE_DEBUG:
1891 use_def_for_tx = false;
1892 update_def_on_tx = false;
1893 use_def_for_rts = false;
1894 use_def_for_sg = false;
1901 ah->ah_tx_ant = tx_ant;
1902 ah->ah_ant_mode = ant_mode;
1903 ah->ah_def_ant = def_ant;
1905 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1906 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1907 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1908 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1910 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1913 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1915 /* Note: set diversity before default antenna
1916 * because it won't work correctly */
1917 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1918 ath5k_hw_set_def_antenna(ah, def_ant);
1931 * Do linear interpolation between two given (x, y) points
1934 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1935 s16 y_left, s16 y_right)
1939 /* Avoid divide by zero and skip interpolation
1940 * if we have the same point */
1941 if ((x_left == x_right) || (y_left == y_right))
1945 * Since we use ints and not fps, we need to scale up in
1946 * order to get a sane ratio value (or else we 'll eg. get
1947 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1948 * to have some accuracy both for 0.5 and 0.25 steps.
1950 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1952 /* Now scale down to be in range */
1953 result = y_left + (ratio * (target - x_left) / 100);
1959 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1961 * Since we have the top of the curve and we draw the line below
1962 * until we reach 1 (1 pcdac step) we need to know which point
1963 * (x value) that is so that we don't go below y axis and have negative
1964 * pcdac values when creating the curve, or fill the table with zeroes.
1967 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1968 const s16 *pwrL, const s16 *pwrR)
1971 s16 min_pwrL, min_pwrR;
1974 /* Some vendors write the same pcdac value twice !!! */
1975 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
1976 return max(pwrL[0], pwrR[0]);
1978 if (pwrL[0] == pwrL[1])
1984 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
1986 stepL[0], stepL[1]);
1992 if (pwrR[0] == pwrR[1])
1998 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2000 stepR[0], stepR[1]);
2006 /* Keep the right boundary so that it works for both curves */
2007 return max(min_pwrL, min_pwrR);
2011 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2012 * Power to PCDAC curve.
2014 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2015 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2016 * PCDAC/PDADC step for each curve is 64 but we can write more than
2017 * one curves on hw so we can go up to 128 (which is the max step we
2018 * can write on the final table).
2020 * We write y values (PCDAC/PDADC steps) on hw.
2023 ath5k_create_power_curve(s16 pmin, s16 pmax,
2024 const s16 *pwr, const u8 *vpd,
2026 u8 *vpd_table, u8 type)
2028 u8 idx[2] = { 0, 1 };
2035 /* We want the whole line, so adjust boundaries
2036 * to cover the entire power range. Note that
2037 * power values are already 0.25dB so no need
2038 * to multiply pwr_i by 2 */
2039 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2045 /* Find surrounding turning points (TPs)
2046 * and interpolate between them */
2047 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2048 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2050 /* We passed the right TP, move to the next set of TPs
2051 * if we pass the last TP, extrapolate above using the last
2052 * two TPs for ratio */
2053 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2058 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2059 pwr[idx[0]], pwr[idx[1]],
2060 vpd[idx[0]], vpd[idx[1]]);
2062 /* Increase by 0.5dB
2063 * (0.25 dB units) */
2069 * Get the surrounding per-channel power calibration piers
2070 * for a given frequency so that we can interpolate between
2071 * them and come up with an apropriate dataset for our current
2075 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2076 struct ieee80211_channel *channel,
2077 struct ath5k_chan_pcal_info **pcinfo_l,
2078 struct ath5k_chan_pcal_info **pcinfo_r)
2080 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2081 struct ath5k_chan_pcal_info *pcinfo;
2084 u32 target = channel->center_freq;
2089 if (!(channel->hw_value & CHANNEL_OFDM)) {
2090 pcinfo = ee->ee_pwr_cal_b;
2091 mode = AR5K_EEPROM_MODE_11B;
2092 } else if (channel->hw_value & CHANNEL_2GHZ) {
2093 pcinfo = ee->ee_pwr_cal_g;
2094 mode = AR5K_EEPROM_MODE_11G;
2096 pcinfo = ee->ee_pwr_cal_a;
2097 mode = AR5K_EEPROM_MODE_11A;
2099 max = ee->ee_n_piers[mode] - 1;
2101 /* Frequency is below our calibrated
2102 * range. Use the lowest power curve
2104 if (target < pcinfo[0].freq) {
2109 /* Frequency is above our calibrated
2110 * range. Use the highest power curve
2112 if (target > pcinfo[max].freq) {
2113 idx_l = idx_r = max;
2117 /* Frequency is inside our calibrated
2118 * channel range. Pick the surrounding
2119 * calibration piers so that we can
2121 for (i = 0; i <= max; i++) {
2123 /* Frequency matches one of our calibration
2124 * piers, no need to interpolate, just use
2125 * that calibration pier */
2126 if (pcinfo[i].freq == target) {
2131 /* We found a calibration pier that's above
2132 * frequency, use this pier and the previous
2133 * one to interpolate */
2134 if (target < pcinfo[i].freq) {
2142 *pcinfo_l = &pcinfo[idx_l];
2143 *pcinfo_r = &pcinfo[idx_r];
2149 * Get the surrounding per-rate power calibration data
2150 * for a given frequency and interpolate between power
2151 * values to set max target power supported by hw for
2155 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2156 struct ieee80211_channel *channel,
2157 struct ath5k_rate_pcal_info *rates)
2159 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2160 struct ath5k_rate_pcal_info *rpinfo;
2163 u32 target = channel->center_freq;
2168 if (!(channel->hw_value & CHANNEL_OFDM)) {
2169 rpinfo = ee->ee_rate_tpwr_b;
2170 mode = AR5K_EEPROM_MODE_11B;
2171 } else if (channel->hw_value & CHANNEL_2GHZ) {
2172 rpinfo = ee->ee_rate_tpwr_g;
2173 mode = AR5K_EEPROM_MODE_11G;
2175 rpinfo = ee->ee_rate_tpwr_a;
2176 mode = AR5K_EEPROM_MODE_11A;
2178 max = ee->ee_rate_target_pwr_num[mode] - 1;
2180 /* Get the surrounding calibration
2181 * piers - same as above */
2182 if (target < rpinfo[0].freq) {
2187 if (target > rpinfo[max].freq) {
2188 idx_l = idx_r = max;
2192 for (i = 0; i <= max; i++) {
2194 if (rpinfo[i].freq == target) {
2199 if (target < rpinfo[i].freq) {
2207 /* Now interpolate power value, based on the frequency */
2208 rates->freq = target;
2210 rates->target_power_6to24 =
2211 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2213 rpinfo[idx_l].target_power_6to24,
2214 rpinfo[idx_r].target_power_6to24);
2216 rates->target_power_36 =
2217 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2219 rpinfo[idx_l].target_power_36,
2220 rpinfo[idx_r].target_power_36);
2222 rates->target_power_48 =
2223 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2225 rpinfo[idx_l].target_power_48,
2226 rpinfo[idx_r].target_power_48);
2228 rates->target_power_54 =
2229 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2231 rpinfo[idx_l].target_power_54,
2232 rpinfo[idx_r].target_power_54);
2236 * Get the max edge power for this channel if
2237 * we have such data from EEPROM's Conformance Test
2238 * Limits (CTL), and limit max power if needed.
2241 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2242 struct ieee80211_channel *channel)
2244 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2245 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2246 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2247 u8 *ctl_val = ee->ee_ctl;
2248 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2253 u32 target = channel->center_freq;
2255 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2257 switch (channel->hw_value & CHANNEL_MODES) {
2259 ctl_mode |= AR5K_CTL_11A;
2262 ctl_mode |= AR5K_CTL_11G;
2265 ctl_mode |= AR5K_CTL_11B;
2268 ctl_mode |= AR5K_CTL_TURBO;
2271 ctl_mode |= AR5K_CTL_TURBOG;
2279 for (i = 0; i < ee->ee_ctls; i++) {
2280 if (ctl_val[i] == ctl_mode) {
2286 /* If we have a CTL dataset available grab it and find the
2287 * edge power for our frequency */
2288 if (ctl_idx == 0xFF)
2291 /* Edge powers are sorted by frequency from lower
2292 * to higher. Each CTL corresponds to 8 edge power
2294 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2296 /* Don't do boundaries check because we
2297 * might have more that one bands defined
2300 /* Get the edge power that's closer to our
2302 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2304 if (target <= rep[rep_idx].freq)
2305 edge_pwr = (s16) rep[rep_idx].edge;
2309 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2314 * Power to PCDAC table functions
2318 * Fill Power to PCDAC table on RF5111
2320 * No further processing is needed for RF5111, the only thing we have to
2321 * do is fill the values below and above calibration range since eeprom data
2322 * may not cover the entire PCDAC table.
2325 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2328 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2329 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2330 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2331 s16 min_pwr, max_pwr;
2333 /* Get table boundaries */
2334 min_pwr = table_min[0];
2335 pcdac_0 = pcdac_tmp[0];
2337 max_pwr = table_max[0];
2338 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2340 /* Extrapolate below minimum using pcdac_0 */
2342 for (i = 0; i < min_pwr; i++)
2343 pcdac_out[pcdac_i++] = pcdac_0;
2345 /* Copy values from pcdac_tmp */
2347 for (i = 0 ; pwr_idx <= max_pwr &&
2348 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2349 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2353 /* Extrapolate above maximum */
2354 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2355 pcdac_out[pcdac_i++] = pcdac_n;
2360 * Combine available XPD Curves and fill Linear Power to PCDAC table
2363 * RFX112 can have up to 2 curves (one for low txpower range and one for
2364 * higher txpower range). We need to put them both on pcdac_out and place
2365 * them in the correct location. In case we only have one curve available
2366 * just fit it on pcdac_out (it's supposed to cover the entire range of
2367 * available pwr levels since it's always the higher power curve). Extrapolate
2368 * below and above final table if needed.
2371 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2372 s16 *table_max, u8 pdcurves)
2374 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2381 s16 mid_pwr_idx = 0;
2382 /* Edge flag turs on the 7nth bit on the PCDAC
2383 * to delcare the higher power curve (force values
2384 * to be greater than 64). If we only have one curve
2385 * we don't need to set this, if we have 2 curves and
2386 * fill the table backwards this can also be used to
2387 * switch from higher power curve to lower power curve */
2391 /* When we have only one curve available
2392 * that's the higher power curve. If we have
2393 * two curves the first is the high power curve
2394 * and the next is the low power curve. */
2396 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2397 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2398 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2399 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2401 /* If table size goes beyond 31.5dB, keep the
2402 * upper 31.5dB range when setting tx power.
2403 * Note: 126 = 31.5 dB in quarter dB steps */
2404 if (table_max[0] - table_min[1] > 126)
2405 min_pwr_idx = table_max[0] - 126;
2407 min_pwr_idx = table_min[1];
2409 /* Since we fill table backwards
2410 * start from high power curve */
2411 pcdac_tmp = pcdac_high_pwr;
2415 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2416 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2417 min_pwr_idx = table_min[0];
2418 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2419 pcdac_tmp = pcdac_high_pwr;
2423 /* This is used when setting tx power*/
2424 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2426 /* Fill Power to PCDAC table backwards */
2428 for (i = 63; i >= 0; i--) {
2429 /* Entering lower power range, reset
2430 * edge flag and set pcdac_tmp to lower
2432 if (edge_flag == 0x40 &&
2433 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2435 pcdac_tmp = pcdac_low_pwr;
2436 pwr = mid_pwr_idx/2;
2439 /* Don't go below 1, extrapolate below if we have
2440 * already swithced to the lower power curve -or
2441 * we only have one curve and edge_flag is zero
2443 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2445 pcdac_out[i] = pcdac_out[i + 1];
2451 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2453 /* Extrapolate above if pcdac is greater than
2454 * 126 -this can happen because we OR pcdac_out
2455 * value with edge_flag on high power curve */
2456 if (pcdac_out[i] > 126)
2459 /* Decrease by a 0.5dB step */
2464 /* Write PCDAC values on hw */
2466 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2468 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2472 * Write TX power values
2474 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2475 ath5k_hw_reg_write(ah,
2476 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2477 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2478 AR5K_PHY_PCDAC_TXPOWER(i));
2484 * Power to PDADC table functions
2488 * Set the gain boundaries and create final Power to PDADC table
2490 * We can have up to 4 pd curves, we need to do a simmilar process
2491 * as we do for RF5112. This time we don't have an edge_flag but we
2492 * set the gain boundaries on a separate register.
2495 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2496 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2498 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2499 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2502 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2505 /* Note: Register value is initialized on initvals
2506 * there is no feedback from hw.
2507 * XXX: What about pd_gain_overlap from EEPROM ? */
2508 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2509 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2511 /* Create final PDADC table */
2512 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2513 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2515 if (pdg == pdcurves - 1)
2516 /* 2 dB boundary stretch for last
2517 * (higher power) curve */
2518 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2520 /* Set gain boundary in the middle
2521 * between this curve and the next one */
2522 gain_boundaries[pdg] =
2523 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2525 /* Sanity check in case our 2 db stretch got out of
2527 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2528 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2530 /* For the first curve (lower power)
2531 * start from 0 dB */
2535 /* For the other curves use the gain overlap */
2536 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2539 /* Force each power step to be at least 0.5 dB */
2540 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2541 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2545 /* If pdadc_0 is negative, we need to extrapolate
2546 * below this pdgain by a number of pwr_steps */
2547 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2548 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2549 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2553 /* Set last pwr level, using gain boundaries */
2554 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2555 /* Limit it to be inside pwr range */
2556 table_size = pwr_max[pdg] - pwr_min[pdg];
2557 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2559 /* Fill pdadc_out table */
2560 while (pdadc_0 < max_idx)
2561 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2563 /* Need to extrapolate above this pdgain? */
2564 if (pdadc_n <= max_idx)
2567 /* Force each power step to be at least 0.5 dB */
2568 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2569 pwr_step = pdadc_tmp[table_size - 1] -
2570 pdadc_tmp[table_size - 2];
2574 /* Extrapolate above */
2575 while ((pdadc_0 < (s16) pdadc_n) &&
2576 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2577 s16 tmp = pdadc_tmp[table_size - 1] +
2578 (pdadc_0 - max_idx) * pwr_step;
2579 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2584 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2585 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2589 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2590 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2594 /* Set gain boundaries */
2595 ath5k_hw_reg_write(ah,
2596 AR5K_REG_SM(pd_gain_overlap,
2597 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2598 AR5K_REG_SM(gain_boundaries[0],
2599 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2600 AR5K_REG_SM(gain_boundaries[1],
2601 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2602 AR5K_REG_SM(gain_boundaries[2],
2603 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2604 AR5K_REG_SM(gain_boundaries[3],
2605 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2608 /* Used for setting rate power table */
2609 ah->ah_txpower.txp_min_idx = pwr_min[0];
2613 /* Write PDADC values on hw */
2615 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2616 u8 pdcurves, u8 *pdg_to_idx)
2618 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2622 /* Select the right pdgain curves */
2624 /* Clear current settings */
2625 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2626 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2627 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2628 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2629 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2632 * Use pd_gains curve from eeprom
2634 * This overrides the default setting from initvals
2635 * in case some vendors (e.g. Zcomax) don't use the default
2636 * curves. If we don't honor their settings we 'll get a
2637 * 5dB (1 * gain overlap ?) drop.
2639 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2643 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2646 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2649 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2652 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2655 * Write TX power values
2657 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2658 ath5k_hw_reg_write(ah,
2659 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2660 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2661 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2662 ((pdadc_out[4*i + 3] & 0xff) << 24),
2663 AR5K_PHY_PDADC_TXPOWER(i));
2669 * Common code for PCDAC/PDADC tables
2673 * This is the main function that uses all of the above
2674 * to set PCDAC/PDADC table on hw for the current channel.
2675 * This table is used for tx power calibration on the basband,
2676 * without it we get weird tx power levels and in some cases
2677 * distorted spectral mask
2680 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2681 struct ieee80211_channel *channel,
2682 u8 ee_mode, u8 type)
2684 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2685 struct ath5k_chan_pcal_info *pcinfo_L;
2686 struct ath5k_chan_pcal_info *pcinfo_R;
2687 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2688 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2689 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2690 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2693 u32 target = channel->center_freq;
2696 /* Get surounding freq piers for this channel */
2697 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2701 /* Loop over pd gain curves on
2702 * surounding freq piers by index */
2703 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2705 /* Fill curves in reverse order
2706 * from lower power (max gain)
2707 * to higher power. Use curve -> idx
2708 * backmapping we did on eeprom init */
2709 u8 idx = pdg_curve_to_idx[pdg];
2711 /* Grab the needed curves by index */
2712 pdg_L = &pcinfo_L->pd_curves[idx];
2713 pdg_R = &pcinfo_R->pd_curves[idx];
2715 /* Initialize the temp tables */
2716 tmpL = ah->ah_txpower.tmpL[pdg];
2717 tmpR = ah->ah_txpower.tmpR[pdg];
2719 /* Set curve's x boundaries and create
2720 * curves so that they cover the same
2721 * range (if we don't do that one table
2722 * will have values on some range and the
2723 * other one won't have any so interpolation
2725 table_min[pdg] = min(pdg_L->pd_pwr[0],
2726 pdg_R->pd_pwr[0]) / 2;
2728 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2729 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2731 /* Now create the curves on surrounding channels
2732 * and interpolate if needed to get the final
2733 * curve for this gain on this channel */
2735 case AR5K_PWRTABLE_LINEAR_PCDAC:
2736 /* Override min/max so that we don't loose
2737 * accuracy (don't divide by 2) */
2738 table_min[pdg] = min(pdg_L->pd_pwr[0],
2742 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2743 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2745 /* Override minimum so that we don't get
2746 * out of bounds while extrapolating
2747 * below. Don't do this when we have 2
2748 * curves and we are on the high power curve
2749 * because table_min is ok in this case */
2750 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2753 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2758 /* Don't go too low because we will
2759 * miss the upper part of the curve.
2760 * Note: 126 = 31.5dB (max power supported)
2761 * in 0.25dB units */
2762 if (table_max[pdg] - table_min[pdg] > 126)
2763 table_min[pdg] = table_max[pdg] - 126;
2767 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2768 case AR5K_PWRTABLE_PWR_TO_PDADC:
2770 ath5k_create_power_curve(table_min[pdg],
2774 pdg_L->pd_points, tmpL, type);
2776 /* We are in a calibration
2777 * pier, no need to interpolate
2778 * between freq piers */
2779 if (pcinfo_L == pcinfo_R)
2782 ath5k_create_power_curve(table_min[pdg],
2786 pdg_R->pd_points, tmpR, type);
2792 /* Interpolate between curves
2793 * of surounding freq piers to
2794 * get the final curve for this
2795 * pd gain. Re-use tmpL for interpolation
2797 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2798 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2799 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2800 (s16) pcinfo_L->freq,
2801 (s16) pcinfo_R->freq,
2807 /* Now we have a set of curves for this
2808 * channel on tmpL (x range is table_max - table_min
2809 * and y values are tmpL[pdg][]) sorted in the same
2810 * order as EEPROM (because we've used the backmapping).
2811 * So for RF5112 it's from higher power to lower power
2812 * and for RF2413 it's from lower power to higher power.
2813 * For RF5111 we only have one curve. */
2815 /* Fill min and max power levels for this
2816 * channel by interpolating the values on
2817 * surounding channels to complete the dataset */
2818 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2819 (s16) pcinfo_L->freq,
2820 (s16) pcinfo_R->freq,
2821 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2823 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2824 (s16) pcinfo_L->freq,
2825 (s16) pcinfo_R->freq,
2826 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2828 /* We are ready to go, fill PCDAC/PDADC
2829 * table and write settings on hardware */
2831 case AR5K_PWRTABLE_LINEAR_PCDAC:
2832 /* For RF5112 we can have one or two curves
2833 * and each curve covers a certain power lvl
2834 * range so we need to do some more processing */
2835 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2836 ee->ee_pd_gains[ee_mode]);
2838 /* Set txp.offset so that we can
2839 * match max power value with max
2841 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2843 /* Write settings on hw */
2844 ath5k_setup_pcdac_table(ah);
2846 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2847 /* We are done for RF5111 since it has only
2848 * one curve, just fit the curve on the table */
2849 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2851 /* No rate powertable adjustment for RF5111 */
2852 ah->ah_txpower.txp_min_idx = 0;
2853 ah->ah_txpower.txp_offset = 0;
2855 /* Write settings on hw */
2856 ath5k_setup_pcdac_table(ah);
2858 case AR5K_PWRTABLE_PWR_TO_PDADC:
2859 /* Set PDADC boundaries and fill
2860 * final PDADC table */
2861 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2862 ee->ee_pd_gains[ee_mode]);
2864 /* Write settings on hw */
2865 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2867 /* Set txp.offset, note that table_min
2868 * can be negative */
2869 ah->ah_txpower.txp_offset = table_min[0];
2880 * Per-rate tx power setting
2882 * This is the code that sets the desired tx power (below
2883 * maximum) on hw for each rate (we also have TPC that sets
2884 * power per packet). We do that by providing an index on the
2885 * PCDAC/PDADC table we set up.
2889 * Set rate power table
2891 * For now we only limit txpower based on maximum tx power
2892 * supported by hw (what's inside rate_info). We need to limit
2893 * this even more, based on regulatory domain etc.
2895 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2896 * and is indexed as follows:
2897 * rates[0] - rates[7] -> OFDM rates
2898 * rates[8] - rates[14] -> CCK rates
2899 * rates[15] -> XR rates (they all have the same power)
2902 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2903 struct ath5k_rate_pcal_info *rate_info,
2909 /* max_pwr is power level we got from driver/user in 0.5dB
2910 * units, switch to 0.25dB units so we can compare */
2912 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2914 /* apply rate limits */
2915 rates = ah->ah_txpower.txp_rates_power_table;
2917 /* OFDM rates 6 to 24Mb/s */
2918 for (i = 0; i < 5; i++)
2919 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2921 /* Rest OFDM rates */
2922 rates[5] = min(rates[0], rate_info->target_power_36);
2923 rates[6] = min(rates[0], rate_info->target_power_48);
2924 rates[7] = min(rates[0], rate_info->target_power_54);
2928 rates[8] = min(rates[0], rate_info->target_power_6to24);
2930 rates[9] = min(rates[0], rate_info->target_power_36);
2932 rates[10] = min(rates[0], rate_info->target_power_36);
2934 rates[11] = min(rates[0], rate_info->target_power_48);
2936 rates[12] = min(rates[0], rate_info->target_power_48);
2938 rates[13] = min(rates[0], rate_info->target_power_54);
2940 rates[14] = min(rates[0], rate_info->target_power_54);
2943 rates[15] = min(rates[0], rate_info->target_power_6to24);
2945 /* CCK rates have different peak to average ratio
2946 * so we have to tweak their power so that gainf
2947 * correction works ok. For this we use OFDM to
2948 * CCK delta from eeprom */
2949 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2950 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2951 for (i = 8; i <= 15; i++)
2952 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2954 /* Now that we have all rates setup use table offset to
2955 * match the power range set by user with the power indices
2956 * on PCDAC/PDADC table */
2957 for (i = 0; i < 16; i++) {
2958 rates[i] += ah->ah_txpower.txp_offset;
2959 /* Don't get out of bounds */
2964 /* Min/max in 0.25dB units */
2965 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2966 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
2967 ah->ah_txpower.txp_ofdm = rates[7];
2972 * Set transmition power
2975 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2976 u8 ee_mode, u8 txpower)
2978 struct ath5k_rate_pcal_info rate_info;
2982 ATH5K_TRACE(ah->ah_sc);
2983 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2984 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2988 /* Reset TX power values */
2989 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2990 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
2991 ah->ah_txpower.txp_min_pwr = 0;
2992 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
2994 /* Initialize TX power table */
2995 switch (ah->ah_radio) {
2997 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3000 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3007 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3013 /* FIXME: Only on channel/mode change */
3014 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
3018 /* Limit max power if we have a CTL available */
3019 ath5k_get_max_ctl_power(ah, channel);
3021 /* FIXME: Tx power limit for this regdomain
3022 * XXX: Mac80211/CRDA will do that anyway ? */
3024 /* FIXME: Antenna reduction stuff */
3026 /* FIXME: Limit power on turbo modes */
3028 /* FIXME: TPC scale reduction */
3030 /* Get surounding channels for per-rate power table
3032 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3034 /* Setup rate power table */
3035 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3037 /* Write rate power table on hw */
3038 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3039 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3040 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3042 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3043 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3044 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3046 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3047 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3048 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3050 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3051 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3052 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3054 /* FIXME: TPC support */
3055 if (ah->ah_txpower.txp_tpc) {
3056 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3057 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3059 ath5k_hw_reg_write(ah,
3060 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3061 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3062 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3065 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3066 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3072 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3075 struct ieee80211_channel *channel = ah->ah_current_channel;
3078 ATH5K_TRACE(ah->ah_sc);
3080 switch (channel->hw_value & CHANNEL_MODES) {
3084 ee_mode = AR5K_EEPROM_MODE_11A;
3088 ee_mode = AR5K_EEPROM_MODE_11G;
3091 ee_mode = AR5K_EEPROM_MODE_11B;
3094 ATH5K_ERR(ah->ah_sc,
3095 "invalid channel: %d\n", channel->center_freq);
3099 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3100 "changing txpower to %d\n", txpower);
3102 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);