2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #include "ar9003_phy.h"
20 #include "ar9003_rtt.h"
21 #include "ar9003_mci.h"
23 #define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
24 #define MAX_MAG_DELTA 11
25 #define MAX_PHS_DELTA 10
29 int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
30 int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MAXIQCAL];
34 enum ar9003_cal_types {
35 IQ_MISMATCH_CAL = BIT(0),
38 static void ar9003_hw_setup_calibration(struct ath_hw *ah,
39 struct ath9k_cal_list *currCal)
41 struct ath_common *common = ath9k_hw_common(ah);
43 /* Select calibration to run */
44 switch (currCal->calData->calType) {
47 * Start calibration with
48 * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
50 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
51 AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
52 currCal->calData->calCountMax);
53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
55 ath_dbg(common, CALIBRATE,
56 "starting IQ Mismatch Calibration\n");
59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
62 ath_err(common, "Invalid calibration type\n");
68 * Generic calibration routine.
69 * Recalibrate the lower PHY chips to account for temperature/environment
72 static bool ar9003_hw_per_calibration(struct ath_hw *ah,
73 struct ath9k_channel *ichan,
75 struct ath9k_cal_list *currCal)
77 struct ath9k_hw_cal_data *caldata = ah->caldata;
78 /* Cal is assumed not done until explicitly set below */
79 bool iscaldone = false;
81 /* Calibration in progress. */
82 if (currCal->calState == CAL_RUNNING) {
83 /* Check to see if it has finished. */
84 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
86 * Accumulate cal measures for active chains
88 currCal->calData->calCollect(ah);
91 if (ah->cal_samples >=
92 currCal->calData->calNumSamples) {
93 unsigned int i, numChains = 0;
94 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
95 if (rxchainmask & (1 << i))
100 * Process accumulated data
102 currCal->calData->calPostProc(ah, numChains);
104 /* Calibration has finished. */
105 caldata->CalValid |= currCal->calData->calType;
106 currCal->calState = CAL_DONE;
110 * Set-up collection of another sub-sample until we
113 ar9003_hw_setup_calibration(ah, currCal);
116 } else if (!(caldata->CalValid & currCal->calData->calType)) {
117 /* If current cal is marked invalid in channel, kick it off */
118 ath9k_hw_reset_calibration(ah, currCal);
124 static bool ar9003_hw_calibrate(struct ath_hw *ah,
125 struct ath9k_channel *chan,
129 bool iscaldone = true;
130 struct ath9k_cal_list *currCal = ah->cal_list_curr;
133 * For given calibration:
134 * 1. Call generic cal routine
135 * 2. When this cal is done (isCalDone) if we have more cals waiting
136 * (eg after reset), mask this to upper layers by not propagating
137 * isCalDone if it is set to TRUE.
138 * Instead, change isCalDone to FALSE and setup the waiting cal(s)
142 (currCal->calState == CAL_RUNNING ||
143 currCal->calState == CAL_WAITING)) {
144 iscaldone = ar9003_hw_per_calibration(ah, chan,
145 rxchainmask, currCal);
147 ah->cal_list_curr = currCal = currCal->calNext;
149 if (currCal->calState == CAL_WAITING) {
151 ath9k_hw_reset_calibration(ah, currCal);
157 * Do NF cal only at longer intervals. Get the value from
158 * the previous NF cal and update history buffer.
160 if (longcal && ath9k_hw_getnf(ah, chan)) {
162 * Load the NF from history buffer of the current channel.
163 * NF is slow time-variant, so it is OK to use a historical
166 ath9k_hw_loadnf(ah, ah->curchan);
168 /* start NF calibration, without updating BB NF register */
169 ath9k_hw_start_nfcal(ah, false);
175 static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
179 /* Accumulate IQ cal measures for active chains */
180 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
181 if (ah->txchainmask & BIT(i)) {
182 ah->totalPowerMeasI[i] +=
183 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
184 ah->totalPowerMeasQ[i] +=
185 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
186 ah->totalIqCorrMeas[i] +=
187 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
188 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
189 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
190 ah->cal_samples, i, ah->totalPowerMeasI[i],
191 ah->totalPowerMeasQ[i],
192 ah->totalIqCorrMeas[i]);
197 static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
199 struct ath_common *common = ath9k_hw_common(ah);
200 u32 powerMeasQ, powerMeasI, iqCorrMeas;
201 u32 qCoffDenom, iCoffDenom;
202 int32_t qCoff, iCoff;
204 static const u_int32_t offset_array[3] = {
205 AR_PHY_RX_IQCAL_CORR_B0,
206 AR_PHY_RX_IQCAL_CORR_B1,
207 AR_PHY_RX_IQCAL_CORR_B2,
210 for (i = 0; i < numChains; i++) {
211 powerMeasI = ah->totalPowerMeasI[i];
212 powerMeasQ = ah->totalPowerMeasQ[i];
213 iqCorrMeas = ah->totalIqCorrMeas[i];
215 ath_dbg(common, CALIBRATE,
216 "Starting IQ Cal and Correction for Chain %d\n", i);
218 ath_dbg(common, CALIBRATE,
219 "Original: Chn %d iq_corr_meas = 0x%08x\n",
220 i, ah->totalIqCorrMeas[i]);
224 if (iqCorrMeas > 0x80000000) {
225 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
229 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n",
231 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n",
233 ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg);
235 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
236 qCoffDenom = powerMeasQ / 64;
238 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
239 iCoff = iqCorrMeas / iCoffDenom;
240 qCoff = powerMeasI / qCoffDenom - 64;
241 ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n",
243 ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n",
246 /* Force bounds on iCoff */
249 else if (iCoff <= -63)
252 /* Negate iCoff if iqCorrNeg == 0 */
253 if (iqCorrNeg == 0x0)
256 /* Force bounds on qCoff */
259 else if (qCoff <= -63)
262 iCoff = iCoff & 0x7f;
263 qCoff = qCoff & 0x7f;
265 ath_dbg(common, CALIBRATE,
266 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
268 ath_dbg(common, CALIBRATE,
269 "Register offset (0x%04x) before update = 0x%x\n",
271 REG_READ(ah, offset_array[i]));
273 if (AR_SREV_9565(ah) &&
274 (iCoff == 63 || qCoff == 63 ||
275 iCoff == -63 || qCoff == -63))
278 REG_RMW_FIELD(ah, offset_array[i],
279 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
281 REG_RMW_FIELD(ah, offset_array[i],
282 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
284 ath_dbg(common, CALIBRATE,
285 "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
287 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
288 REG_READ(ah, offset_array[i]));
289 ath_dbg(common, CALIBRATE,
290 "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
292 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
293 REG_READ(ah, offset_array[i]));
295 ath_dbg(common, CALIBRATE,
296 "IQ Cal and Correction done for Chain %d\n", i);
300 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
301 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
302 ath_dbg(common, CALIBRATE,
303 "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
304 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
305 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
306 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
309 static const struct ath9k_percal_data iq_cal_single_sample = {
313 ar9003_hw_iqcal_collect,
314 ar9003_hw_iqcalibrate
317 static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
319 ah->iq_caldata.calData = &iq_cal_single_sample;
321 if (AR_SREV_9300_20_OR_LATER(ah)) {
322 ah->enabled_cals |= TX_IQ_CAL;
323 if (AR_SREV_9485_OR_LATER(ah) && !AR_SREV_9340(ah))
324 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
327 ah->supp_cals = IQ_MISMATCH_CAL;
330 #define OFF_UPPER_LT 24
331 #define OFF_LOWER_LT 7
333 static bool ar9003_hw_dynamic_osdac_selection(struct ath_hw *ah,
336 struct ath_common *common = ath9k_hw_common(ah);
337 int ch0_done, osdac_ch0, dc_off_ch0_i1, dc_off_ch0_q1, dc_off_ch0_i2,
338 dc_off_ch0_q2, dc_off_ch0_i3, dc_off_ch0_q3;
339 int ch1_done, osdac_ch1, dc_off_ch1_i1, dc_off_ch1_q1, dc_off_ch1_i2,
340 dc_off_ch1_q2, dc_off_ch1_i3, dc_off_ch1_q3;
341 int ch2_done, osdac_ch2, dc_off_ch2_i1, dc_off_ch2_q1, dc_off_ch2_i2,
342 dc_off_ch2_q2, dc_off_ch2_i3, dc_off_ch2_q3;
347 * Clear offset and IQ calibration, run AGC cal.
349 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
350 AR_PHY_AGC_CONTROL_OFFSET_CAL);
351 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
352 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
353 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
354 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
356 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
357 AR_PHY_AGC_CONTROL_CAL,
360 ath_dbg(common, CALIBRATE,
361 "AGC cal without offset cal failed to complete in 1ms");
366 * Allow only offset calibration and disable the others
367 * (Carrier Leak calibration, TX Filter calibration and
368 * Peak Detector offset calibration).
370 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
371 AR_PHY_AGC_CONTROL_OFFSET_CAL);
372 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
373 AR_PHY_CL_CAL_ENABLE);
374 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
375 AR_PHY_AGC_CONTROL_FLTR_CAL);
376 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
377 AR_PHY_AGC_CONTROL_PKDET_CAL);
383 while ((ch0_done == 0) || (ch1_done == 0) || (ch2_done == 0)) {
384 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3;
385 osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3;
386 osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3;
388 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
390 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
391 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
393 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
394 AR_PHY_AGC_CONTROL_CAL,
397 ath_dbg(common, CALIBRATE,
398 "DC offset cal failed to complete in 1ms");
402 REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
407 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
408 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8)));
409 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
410 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8)));
411 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
412 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8)));
414 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
415 dc_off_ch0_i1 = (temp >> 26) & 0x1f;
416 dc_off_ch0_q1 = (temp >> 21) & 0x1f;
418 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
419 dc_off_ch1_i1 = (temp >> 26) & 0x1f;
420 dc_off_ch1_q1 = (temp >> 21) & 0x1f;
422 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
423 dc_off_ch2_i1 = (temp >> 26) & 0x1f;
424 dc_off_ch2_q1 = (temp >> 21) & 0x1f;
429 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
430 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8)));
431 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
432 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8)));
433 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
434 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8)));
436 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
437 dc_off_ch0_i2 = (temp >> 26) & 0x1f;
438 dc_off_ch0_q2 = (temp >> 21) & 0x1f;
440 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
441 dc_off_ch1_i2 = (temp >> 26) & 0x1f;
442 dc_off_ch1_q2 = (temp >> 21) & 0x1f;
444 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
445 dc_off_ch2_i2 = (temp >> 26) & 0x1f;
446 dc_off_ch2_q2 = (temp >> 21) & 0x1f;
451 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3,
452 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8)));
453 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3,
454 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8)));
455 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3,
456 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8)));
458 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3);
459 dc_off_ch0_i3 = (temp >> 26) & 0x1f;
460 dc_off_ch0_q3 = (temp >> 21) & 0x1f;
462 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3);
463 dc_off_ch1_i3 = (temp >> 26) & 0x1f;
464 dc_off_ch1_q3 = (temp >> 21) & 0x1f;
466 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3);
467 dc_off_ch2_i3 = (temp >> 26) & 0x1f;
468 dc_off_ch2_q3 = (temp >> 21) & 0x1f;
470 if ((dc_off_ch0_i1 > OFF_UPPER_LT) || (dc_off_ch0_i1 < OFF_LOWER_LT) ||
471 (dc_off_ch0_i2 > OFF_UPPER_LT) || (dc_off_ch0_i2 < OFF_LOWER_LT) ||
472 (dc_off_ch0_i3 > OFF_UPPER_LT) || (dc_off_ch0_i3 < OFF_LOWER_LT) ||
473 (dc_off_ch0_q1 > OFF_UPPER_LT) || (dc_off_ch0_q1 < OFF_LOWER_LT) ||
474 (dc_off_ch0_q2 > OFF_UPPER_LT) || (dc_off_ch0_q2 < OFF_LOWER_LT) ||
475 (dc_off_ch0_q3 > OFF_UPPER_LT) || (dc_off_ch0_q3 < OFF_LOWER_LT)) {
476 if (osdac_ch0 == 3) {
481 val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff;
482 val |= (osdac_ch0 << 30);
483 REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val);
491 if ((dc_off_ch1_i1 > OFF_UPPER_LT) || (dc_off_ch1_i1 < OFF_LOWER_LT) ||
492 (dc_off_ch1_i2 > OFF_UPPER_LT) || (dc_off_ch1_i2 < OFF_LOWER_LT) ||
493 (dc_off_ch1_i3 > OFF_UPPER_LT) || (dc_off_ch1_i3 < OFF_LOWER_LT) ||
494 (dc_off_ch1_q1 > OFF_UPPER_LT) || (dc_off_ch1_q1 < OFF_LOWER_LT) ||
495 (dc_off_ch1_q2 > OFF_UPPER_LT) || (dc_off_ch1_q2 < OFF_LOWER_LT) ||
496 (dc_off_ch1_q3 > OFF_UPPER_LT) || (dc_off_ch1_q3 < OFF_LOWER_LT)) {
497 if (osdac_ch1 == 3) {
502 val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff;
503 val |= (osdac_ch1 << 30);
504 REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val);
512 if ((dc_off_ch2_i1 > OFF_UPPER_LT) || (dc_off_ch2_i1 < OFF_LOWER_LT) ||
513 (dc_off_ch2_i2 > OFF_UPPER_LT) || (dc_off_ch2_i2 < OFF_LOWER_LT) ||
514 (dc_off_ch2_i3 > OFF_UPPER_LT) || (dc_off_ch2_i3 < OFF_LOWER_LT) ||
515 (dc_off_ch2_q1 > OFF_UPPER_LT) || (dc_off_ch2_q1 < OFF_LOWER_LT) ||
516 (dc_off_ch2_q2 > OFF_UPPER_LT) || (dc_off_ch2_q2 < OFF_LOWER_LT) ||
517 (dc_off_ch2_q3 > OFF_UPPER_LT) || (dc_off_ch2_q3 < OFF_LOWER_LT)) {
518 if (osdac_ch2 == 3) {
523 val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff;
524 val |= (osdac_ch2 << 30);
525 REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val);
534 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
535 AR_PHY_AGC_CONTROL_OFFSET_CAL);
536 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
539 * We don't need to check txiqcal_done here since it is always
542 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
543 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
549 * solve 4x4 linear equation used in loopback iq cal.
551 static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
562 s32 f1 = cos_2phi_1 - cos_2phi_2,
563 f3 = sin_2phi_1 - sin_2phi_2,
565 s32 mag_tx, phs_tx, mag_rx, phs_rx;
566 const s32 result_shift = 1 << 15;
567 struct ath_common *common = ath9k_hw_common(ah);
569 f2 = ((f1 >> 3) * (f1 >> 3) + (f3 >> 3) * (f3 >> 3)) >> 9;
572 ath_dbg(common, CALIBRATE, "Divide by 0\n");
576 /* mag mismatch, tx */
577 mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
578 /* phs mismatch, tx */
579 phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
581 mag_tx = (mag_tx / f2);
582 phs_tx = (phs_tx / f2);
584 /* mag mismatch, rx */
585 mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
587 /* phs mismatch, rx */
588 phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
591 solved_eq[0] = mag_tx;
592 solved_eq[1] = phs_tx;
593 solved_eq[2] = mag_rx;
594 solved_eq[3] = phs_rx;
599 static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
601 s32 abs_i = abs(in_re),
613 return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
618 static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
623 s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
624 i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
625 i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
626 i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
627 s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
628 phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
629 sin_2phi_1, cos_2phi_1,
630 sin_2phi_2, cos_2phi_2;
631 s32 mag_tx, phs_tx, mag_rx, phs_rx;
632 s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
634 const s32 res_scale = 1 << 15;
635 const s32 delpt_shift = 1 << 8;
637 struct ath_common *common = ath9k_hw_common(ah);
639 i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
640 i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
641 iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
643 if (i2_m_q2_a0_d0 > 0x800)
644 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
646 if (i2_p_q2_a0_d0 > 0x800)
647 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
649 if (iq_corr_a0_d0 > 0x800)
650 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
652 i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
653 i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
654 iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
656 if (i2_m_q2_a0_d1 > 0x800)
657 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
659 if (iq_corr_a0_d1 > 0x800)
660 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
662 i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
663 i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
664 iq_corr_a1_d0 = iq_res[4] & 0xfff;
666 if (i2_m_q2_a1_d0 > 0x800)
667 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
669 if (i2_p_q2_a1_d0 > 0x800)
670 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
672 if (iq_corr_a1_d0 > 0x800)
673 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
675 i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
676 i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
677 iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
679 if (i2_m_q2_a1_d1 > 0x800)
680 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
682 if (i2_p_q2_a1_d1 > 0x800)
683 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
685 if (iq_corr_a1_d1 > 0x800)
686 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
688 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
689 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
690 ath_dbg(common, CALIBRATE,
696 i2_p_q2_a0_d0, i2_p_q2_a0_d1,
697 i2_p_q2_a1_d0, i2_p_q2_a1_d1);
701 if ((i2_p_q2_a0_d0 < 1024) || (i2_p_q2_a0_d0 > 2047) ||
702 (i2_p_q2_a1_d0 < 0) || (i2_p_q2_a1_d1 < 0) ||
703 (i2_p_q2_a0_d0 <= i2_m_q2_a0_d0) ||
704 (i2_p_q2_a0_d0 <= iq_corr_a0_d0) ||
705 (i2_p_q2_a0_d1 <= i2_m_q2_a0_d1) ||
706 (i2_p_q2_a0_d1 <= iq_corr_a0_d1) ||
707 (i2_p_q2_a1_d0 <= i2_m_q2_a1_d0) ||
708 (i2_p_q2_a1_d0 <= iq_corr_a1_d0) ||
709 (i2_p_q2_a1_d1 <= i2_m_q2_a1_d1) ||
710 (i2_p_q2_a1_d1 <= iq_corr_a1_d1)) {
714 mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
715 phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
717 mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
718 phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
720 mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
721 phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
723 mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
724 phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
726 /* w/o analog phase shift */
727 sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
728 /* w/o analog phase shift */
729 cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
730 /* w/ analog phase shift */
731 sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
732 /* w/ analog phase shift */
733 cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
736 * force sin^2 + cos^2 = 1;
737 * find magnitude by approximation
739 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
740 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
742 if ((mag1 == 0) || (mag2 == 0)) {
743 ath_dbg(common, CALIBRATE, "Divide by 0: mag1=%d, mag2=%d\n",
748 /* normalization sin and cos by mag */
749 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
750 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
751 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
752 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
754 /* calculate IQ mismatch */
755 if (!ar9003_hw_solve_iq_cal(ah,
756 sin_2phi_1, cos_2phi_1,
757 sin_2phi_2, cos_2phi_2,
758 mag_a0_d0, phs_a0_d0,
760 phs_a1_d0, solved_eq)) {
761 ath_dbg(common, CALIBRATE,
762 "Call to ar9003_hw_solve_iq_cal() failed\n");
766 mag_tx = solved_eq[0];
767 phs_tx = solved_eq[1];
768 mag_rx = solved_eq[2];
769 phs_rx = solved_eq[3];
771 ath_dbg(common, CALIBRATE,
772 "chain %d: mag mismatch=%d phase mismatch=%d\n",
773 chain_idx, mag_tx/res_scale, phs_tx/res_scale);
775 if (res_scale == mag_tx) {
776 ath_dbg(common, CALIBRATE,
777 "Divide by 0: mag_tx=%d, res_scale=%d\n",
782 /* calculate and quantize Tx IQ correction factor */
783 mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
784 phs_corr_tx = -phs_tx;
786 q_q_coff = (mag_corr_tx * 128 / res_scale);
787 q_i_coff = (phs_corr_tx * 256 / res_scale);
789 ath_dbg(common, CALIBRATE, "tx chain %d: mag corr=%d phase corr=%d\n",
790 chain_idx, q_q_coff, q_i_coff);
801 iqc_coeff[0] = (q_q_coff * 128) + (0x7f & q_i_coff);
803 ath_dbg(common, CALIBRATE, "tx chain %d: iq corr coeff=%x\n",
804 chain_idx, iqc_coeff[0]);
806 if (-mag_rx == res_scale) {
807 ath_dbg(common, CALIBRATE,
808 "Divide by 0: mag_rx=%d, res_scale=%d\n",
813 /* calculate and quantize Rx IQ correction factors */
814 mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
815 phs_corr_rx = -phs_rx;
817 q_q_coff = (mag_corr_rx * 128 / res_scale);
818 q_i_coff = (phs_corr_rx * 256 / res_scale);
820 ath_dbg(common, CALIBRATE, "rx chain %d: mag corr=%d phase corr=%d\n",
821 chain_idx, q_q_coff, q_i_coff);
832 iqc_coeff[1] = (q_q_coff * 128) + (0x7f & q_i_coff);
834 ath_dbg(common, CALIBRATE, "rx chain %d: iq corr coeff=%x\n",
835 chain_idx, iqc_coeff[1]);
840 static void ar9003_hw_detect_outlier(int mp_coeff[][MAXIQCAL],
844 int mp_max = -64, max_idx = 0;
845 int mp_min = 63, min_idx = 0;
846 int mp_avg = 0, i, outlier_idx = 0, mp_count = 0;
848 /* find min/max mismatch across all calibrated gains */
849 for (i = 0; i < nmeasurement; i++) {
850 if (mp_coeff[i][0] > mp_max) {
851 mp_max = mp_coeff[i][0];
853 } else if (mp_coeff[i][0] < mp_min) {
854 mp_min = mp_coeff[i][0];
859 /* find average (exclude max abs value) */
860 for (i = 0; i < nmeasurement; i++) {
861 if ((abs(mp_coeff[i][0]) < abs(mp_max)) ||
862 (abs(mp_coeff[i][0]) < abs(mp_min))) {
863 mp_avg += mp_coeff[i][0];
869 * finding mean magnitude/phase if possible, otherwise
870 * just use the last value as the mean
875 mp_avg = mp_coeff[nmeasurement - 1][0];
878 if (abs(mp_max - mp_min) > max_delta) {
879 if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
880 outlier_idx = max_idx;
882 outlier_idx = min_idx;
884 mp_coeff[outlier_idx][0] = mp_avg;
888 static void ar9003_hw_tx_iq_cal_outlier_detection(struct ath_hw *ah,
892 int i, im, nmeasurement;
893 int magnitude, phase;
894 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
895 struct ath9k_hw_cal_data *caldata = ah->caldata;
897 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
898 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
899 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
900 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
901 if (!AR_SREV_9485(ah)) {
902 tx_corr_coeff[i * 2][1] =
903 tx_corr_coeff[(i * 2) + 1][1] =
904 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
906 tx_corr_coeff[i * 2][2] =
907 tx_corr_coeff[(i * 2) + 1][2] =
908 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
912 /* Load the average of 2 passes */
913 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
914 if (!(ah->txchainmask & (1 << i)))
916 nmeasurement = REG_READ_FIELD(ah,
917 AR_PHY_TX_IQCAL_STATUS_B0,
918 AR_PHY_CALIBRATED_GAINS_0);
920 if (nmeasurement > MAX_MEASUREMENT)
921 nmeasurement = MAX_MEASUREMENT;
924 * Skip normal outlier detection for AR9550.
926 if (!AR_SREV_9550(ah)) {
927 /* detect outlier only if nmeasurement > 1 */
928 if (nmeasurement > 1) {
929 /* Detect magnitude outlier */
930 ar9003_hw_detect_outlier(coeff->mag_coeff[i],
934 /* Detect phase outlier */
935 ar9003_hw_detect_outlier(coeff->phs_coeff[i],
941 for (im = 0; im < nmeasurement; im++) {
942 magnitude = coeff->mag_coeff[i][im][0];
943 phase = coeff->phs_coeff[i][im][0];
945 coeff->iqc_coeff[0] =
946 (phase & 0x7f) | ((magnitude & 0x7f) << 7);
949 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
950 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
951 coeff->iqc_coeff[0]);
953 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
954 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
955 coeff->iqc_coeff[0]);
958 caldata->tx_corr_coeff[im][i] =
962 caldata->num_measures[i] = nmeasurement;
965 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
966 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
967 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
968 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
972 set_bit(TXIQCAL_DONE, &caldata->cal_flags);
974 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
980 static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
982 struct ath_common *common = ath9k_hw_common(ah);
985 tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
986 AR_PHY_TXGAIN_FORCE);
988 REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
989 AR_PHY_TXGAIN_FORCE, 0);
991 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
992 AR_PHY_TX_IQCAL_START_DO_CAL, 1);
994 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
995 AR_PHY_TX_IQCAL_START_DO_CAL, 0,
997 ath_dbg(common, CALIBRATE, "Tx IQ Cal is not completed\n");
1003 static void __ar955x_tx_iq_cal_sort(struct ath_hw *ah,
1004 struct coeff *coeff,
1005 int i, int nmeasurement)
1007 struct ath_common *common = ath9k_hw_common(ah);
1008 int im, ix, iy, temp;
1010 for (im = 0; im < nmeasurement; im++) {
1011 for (ix = 0; ix < MAXIQCAL - 1; ix++) {
1012 for (iy = ix + 1; iy <= MAXIQCAL - 1; iy++) {
1013 if (coeff->mag_coeff[i][im][iy] <
1014 coeff->mag_coeff[i][im][ix]) {
1015 temp = coeff->mag_coeff[i][im][ix];
1016 coeff->mag_coeff[i][im][ix] =
1017 coeff->mag_coeff[i][im][iy];
1018 coeff->mag_coeff[i][im][iy] = temp;
1020 if (coeff->phs_coeff[i][im][iy] <
1021 coeff->phs_coeff[i][im][ix]) {
1022 temp = coeff->phs_coeff[i][im][ix];
1023 coeff->phs_coeff[i][im][ix] =
1024 coeff->phs_coeff[i][im][iy];
1025 coeff->phs_coeff[i][im][iy] = temp;
1029 coeff->mag_coeff[i][im][0] = coeff->mag_coeff[i][im][MAXIQCAL / 2];
1030 coeff->phs_coeff[i][im][0] = coeff->phs_coeff[i][im][MAXIQCAL / 2];
1032 ath_dbg(common, CALIBRATE,
1033 "IQCAL: Median [ch%d][gain%d]: mag = %d phase = %d\n",
1035 coeff->mag_coeff[i][im][0],
1036 coeff->phs_coeff[i][im][0]);
1040 static bool ar955x_tx_iq_cal_median(struct ath_hw *ah,
1041 struct coeff *coeff,
1047 if ((iqcal_idx + 1) != MAXIQCAL)
1050 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1051 __ar955x_tx_iq_cal_sort(ah, coeff, i, nmeasurement);
1057 static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah,
1061 struct ath_common *common = ath9k_hw_common(ah);
1062 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
1063 AR_PHY_TX_IQCAL_STATUS_B0,
1064 AR_PHY_TX_IQCAL_STATUS_B1,
1065 AR_PHY_TX_IQCAL_STATUS_B2,
1067 const u_int32_t chan_info_tab[] = {
1068 AR_PHY_CHAN_INFO_TAB_0,
1069 AR_PHY_CHAN_INFO_TAB_1,
1070 AR_PHY_CHAN_INFO_TAB_2,
1072 static struct coeff coeff;
1075 int nmeasurement = 0;
1076 bool outlier_detect = true;
1078 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1079 if (!(ah->txchainmask & (1 << i)))
1082 nmeasurement = REG_READ_FIELD(ah,
1083 AR_PHY_TX_IQCAL_STATUS_B0,
1084 AR_PHY_CALIBRATED_GAINS_0);
1085 if (nmeasurement > MAX_MEASUREMENT)
1086 nmeasurement = MAX_MEASUREMENT;
1088 for (im = 0; im < nmeasurement; im++) {
1089 ath_dbg(common, CALIBRATE,
1090 "Doing Tx IQ Cal for chain %d\n", i);
1092 if (REG_READ(ah, txiqcal_status[i]) &
1093 AR_PHY_TX_IQCAL_STATUS_FAILED) {
1094 ath_dbg(common, CALIBRATE,
1095 "Tx IQ Cal failed for chain %d\n", i);
1099 for (j = 0; j < 3; j++) {
1100 u32 idx = 2 * j, offset = 4 * (3 * im + j);
1103 AR_PHY_CHAN_INFO_MEMORY,
1104 AR_PHY_CHAN_INFO_TAB_S2_READ,
1108 iq_res[idx] = REG_READ(ah,
1113 AR_PHY_CHAN_INFO_MEMORY,
1114 AR_PHY_CHAN_INFO_TAB_S2_READ,
1118 iq_res[idx + 1] = 0xffff & REG_READ(ah,
1119 chan_info_tab[i] + offset);
1121 ath_dbg(common, CALIBRATE,
1122 "IQ_RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
1123 idx, iq_res[idx], idx + 1,
1127 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
1129 ath_dbg(common, CALIBRATE,
1130 "Failed in calculation of IQ correction\n");
1134 coeff.phs_coeff[i][im][iqcal_idx] =
1135 coeff.iqc_coeff[0] & 0x7f;
1136 coeff.mag_coeff[i][im][iqcal_idx] =
1137 (coeff.iqc_coeff[0] >> 7) & 0x7f;
1139 if (coeff.mag_coeff[i][im][iqcal_idx] > 63)
1140 coeff.mag_coeff[i][im][iqcal_idx] -= 128;
1141 if (coeff.phs_coeff[i][im][iqcal_idx] > 63)
1142 coeff.phs_coeff[i][im][iqcal_idx] -= 128;
1146 if (AR_SREV_9550(ah))
1147 outlier_detect = ar955x_tx_iq_cal_median(ah, &coeff,
1148 iqcal_idx, nmeasurement);
1150 ar9003_hw_tx_iq_cal_outlier_detection(ah, &coeff, is_reusable);
1155 ath_dbg(common, CALIBRATE, "Tx IQ Cal failed\n");
1159 static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
1161 struct ath9k_hw_cal_data *caldata = ah->caldata;
1162 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
1165 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
1166 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
1167 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
1168 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
1169 if (!AR_SREV_9485(ah)) {
1170 tx_corr_coeff[i * 2][1] =
1171 tx_corr_coeff[(i * 2) + 1][1] =
1172 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
1174 tx_corr_coeff[i * 2][2] =
1175 tx_corr_coeff[(i * 2) + 1][2] =
1176 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
1180 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1181 if (!(ah->txchainmask & (1 << i)))
1184 for (im = 0; im < caldata->num_measures[i]; im++) {
1186 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
1187 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
1188 caldata->tx_corr_coeff[im][i]);
1190 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
1191 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
1192 caldata->tx_corr_coeff[im][i]);
1196 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
1197 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
1198 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
1199 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
1202 static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g)
1204 int offset[8] = {0}, total = 0, test;
1207 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1208 AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE, 0x1);
1209 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1210 AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC, 0x0);
1212 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1213 AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR, 0x0);
1215 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1216 AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR, 0x0);
1218 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1219 AR_PHY_65NM_RXTX2_RXON_OVR, 0x1);
1220 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1221 AR_PHY_65NM_RXTX2_RXON, 0x0);
1223 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1224 AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE, 0x1);
1225 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1226 AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR, 0x1);
1227 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1228 AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0x1);
1230 if (AR_SREV_9330_11(ah)) {
1231 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1232 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0);
1235 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1236 AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, 0x0);
1238 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1239 AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR, 0x0);
1242 for (i = 6; i > 0; i--) {
1243 offset[i] = BIT(i - 1);
1244 test = total + offset[i];
1247 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1248 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR,
1251 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1252 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR,
1255 agc_out = REG_READ_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1256 AR_PHY_65NM_RXRF_AGC_AGC_OUT);
1257 offset[i] = (agc_out) ? 0 : 1;
1258 total += (offset[i] << (i - 1));
1262 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1263 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, total);
1265 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1266 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR, total);
1268 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain),
1269 AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE, 0);
1270 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain),
1271 AR_PHY_65NM_RXTX2_RXON_OVR, 0);
1272 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain),
1273 AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR, 0);
1276 static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah,
1277 struct ath9k_channel *chan,
1280 struct ath9k_hw_cal_data *caldata = ah->caldata;
1283 if (!AR_SREV_9462(ah) && !AR_SREV_9565(ah) && !AR_SREV_9485(ah))
1286 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && !run_rtt_cal)
1289 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1290 if (!(ah->rxchainmask & (1 << i)))
1292 ar9003_hw_manual_peak_cal(ah, i, IS_CHAN_2GHZ(chan));
1296 set_bit(SW_PKDET_DONE, &caldata->cal_flags);
1298 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && caldata) {
1299 if (IS_CHAN_2GHZ(chan)){
1300 caldata->caldac[0] = REG_READ_FIELD(ah,
1301 AR_PHY_65NM_RXRF_AGC(0),
1302 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR);
1303 caldata->caldac[1] = REG_READ_FIELD(ah,
1304 AR_PHY_65NM_RXRF_AGC(1),
1305 AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR);
1307 caldata->caldac[0] = REG_READ_FIELD(ah,
1308 AR_PHY_65NM_RXRF_AGC(0),
1309 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR);
1310 caldata->caldac[1] = REG_READ_FIELD(ah,
1311 AR_PHY_65NM_RXRF_AGC(1),
1312 AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR);
1317 static void ar9003_hw_cl_cal_post_proc(struct ath_hw *ah, bool is_reusable)
1319 u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
1322 struct ath9k_hw_cal_data *caldata = ah->caldata;
1323 bool txclcal_done = false;
1326 if (!caldata || !(ah->enabled_cals & TX_CL_CAL))
1329 txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
1330 AR_PHY_AGC_CONTROL_CLC_SUCCESS);
1332 if (test_bit(TXCLCAL_DONE, &caldata->cal_flags)) {
1333 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1334 if (!(ah->txchainmask & (1 << i)))
1336 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1337 REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
1338 caldata->tx_clcal[i][j]);
1340 } else if (is_reusable && txclcal_done) {
1341 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1342 if (!(ah->txchainmask & (1 << i)))
1344 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1345 caldata->tx_clcal[i][j] =
1346 REG_READ(ah, CL_TAB_ENTRY(cl_idx[i]));
1348 set_bit(TXCLCAL_DONE, &caldata->cal_flags);
1352 static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
1353 struct ath9k_channel *chan)
1355 struct ath_common *common = ath9k_hw_common(ah);
1356 struct ath9k_hw_cal_data *caldata = ah->caldata;
1357 bool txiqcal_done = false;
1358 bool is_reusable = true, status = true;
1359 bool run_rtt_cal = false, run_agc_cal;
1360 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
1362 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
1363 AR_PHY_AGC_CONTROL_FLTR_CAL |
1364 AR_PHY_AGC_CONTROL_PKDET_CAL;
1366 /* Use chip chainmask only for calibration */
1367 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1370 if (!ar9003_hw_rtt_restore(ah, chan))
1374 ath_dbg(common, CALIBRATE, "RTT calibration to be done\n");
1377 run_agc_cal = run_rtt_cal;
1380 ar9003_hw_rtt_enable(ah);
1381 ar9003_hw_rtt_set_mask(ah, 0x00);
1382 ar9003_hw_rtt_clear_hist(ah);
1387 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
1388 agc_supp_cals &= agc_ctrl;
1389 agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
1390 AR_PHY_AGC_CONTROL_FLTR_CAL |
1391 AR_PHY_AGC_CONTROL_PKDET_CAL);
1392 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1394 if (ah->ah_flags & AH_FASTCC)
1399 if (ah->enabled_cals & TX_CL_CAL) {
1400 if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))
1401 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
1402 AR_PHY_CL_CAL_ENABLE);
1404 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
1405 AR_PHY_CL_CAL_ENABLE);
1410 if ((IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) ||
1411 !(ah->enabled_cals & TX_IQ_CAL))
1414 /* Do Tx IQ Calibration */
1415 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
1416 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
1420 * For AR9485 or later chips, TxIQ cal runs as part of
1423 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
1424 if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags))
1425 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1426 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
1428 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1429 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
1430 txiqcal_done = run_agc_cal = true;
1434 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1435 ar9003_mci_init_cal_req(ah, &is_reusable);
1437 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
1438 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
1439 /* Disable BB_active */
1440 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1442 REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);
1443 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1446 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1447 /* Calibrate the AGC */
1448 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1449 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1450 AR_PHY_AGC_CONTROL_CAL);
1452 /* Poll for offset calibration complete */
1453 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1454 AR_PHY_AGC_CONTROL_CAL,
1455 0, AH_WAIT_TIMEOUT);
1457 ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal);
1460 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
1461 REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);
1465 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
1466 ar9003_mci_init_cal_done(ah);
1468 if (rtt && !run_rtt_cal) {
1469 agc_ctrl |= agc_supp_cals;
1470 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1475 ar9003_hw_rtt_disable(ah);
1477 ath_dbg(common, CALIBRATE,
1478 "offset calibration failed to complete in %d ms; noisy environment?\n",
1479 AH_WAIT_TIMEOUT / 1000);
1484 ar9003_hw_tx_iq_cal_post_proc(ah, 0, is_reusable);
1485 else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))
1486 ar9003_hw_tx_iq_cal_reload(ah);
1488 ar9003_hw_cl_cal_post_proc(ah, is_reusable);
1490 if (run_rtt_cal && caldata) {
1492 if (!ath9k_hw_rfbus_req(ah)) {
1493 ath_err(ath9k_hw_common(ah),
1494 "Could not stop baseband\n");
1496 ar9003_hw_rtt_fill_hist(ah);
1498 if (test_bit(SW_PKDET_DONE, &caldata->cal_flags))
1499 ar9003_hw_rtt_load_hist(ah);
1502 ath9k_hw_rfbus_done(ah);
1505 ar9003_hw_rtt_disable(ah);
1508 /* Revert chainmask to runtime parameters */
1509 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1511 /* Initialize list pointers */
1512 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1514 INIT_CAL(&ah->iq_caldata);
1515 INSERT_CAL(ah, &ah->iq_caldata);
1516 ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
1518 /* Initialize current pointer to first element in list */
1519 ah->cal_list_curr = ah->cal_list;
1521 if (ah->cal_list_curr)
1522 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1525 caldata->CalValid = 0;
1530 static bool do_ar9003_agc_cal(struct ath_hw *ah)
1532 struct ath_common *common = ath9k_hw_common(ah);
1535 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1536 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1537 AR_PHY_AGC_CONTROL_CAL);
1539 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1540 AR_PHY_AGC_CONTROL_CAL,
1541 0, AH_WAIT_TIMEOUT);
1543 ath_dbg(common, CALIBRATE,
1544 "offset calibration failed to complete in %d ms,"
1545 "noisy environment?\n",
1546 AH_WAIT_TIMEOUT / 1000);
1553 static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
1554 struct ath9k_channel *chan)
1556 struct ath_common *common = ath9k_hw_common(ah);
1557 struct ath9k_hw_cal_data *caldata = ah->caldata;
1558 bool txiqcal_done = false;
1560 bool run_agc_cal = false, sep_iq_cal = false;
1563 /* Use chip chainmask only for calibration */
1564 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
1566 if (ah->enabled_cals & TX_CL_CAL) {
1567 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1571 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
1574 /* Do Tx IQ Calibration */
1575 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
1576 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
1580 * For AR9485 or later chips, TxIQ cal runs as part of
1581 * AGC calibration. Specifically, AR9550 in SoC chips.
1583 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
1584 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
1585 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) {
1586 txiqcal_done = true;
1588 txiqcal_done = false;
1597 * In the SoC family, this will run for AR9300, AR9331 and AR9340.
1600 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
1601 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1603 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1606 if (AR_SREV_9550(ah) && IS_CHAN_2GHZ(chan)) {
1607 if (!ar9003_hw_dynamic_osdac_selection(ah, txiqcal_done))
1612 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1613 if (AR_SREV_9330_11(ah))
1614 ar9003_hw_manual_peak_cal(ah, 0, IS_CHAN_2GHZ(chan));
1617 * For non-AR9550 chips, we just trigger AGC calibration
1618 * in the HW, poll for completion and then process
1621 * For AR955x, we run it multiple times and use
1622 * median IQ correction.
1624 if (!AR_SREV_9550(ah)) {
1625 status = do_ar9003_agc_cal(ah);
1630 ar9003_hw_tx_iq_cal_post_proc(ah, 0, false);
1632 if (!txiqcal_done) {
1633 status = do_ar9003_agc_cal(ah);
1637 for (i = 0; i < MAXIQCAL; i++) {
1638 status = do_ar9003_agc_cal(ah);
1641 ar9003_hw_tx_iq_cal_post_proc(ah, i, false);
1647 /* Revert chainmask to runtime parameters */
1648 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1650 /* Initialize list pointers */
1651 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1653 INIT_CAL(&ah->iq_caldata);
1654 INSERT_CAL(ah, &ah->iq_caldata);
1655 ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
1657 /* Initialize current pointer to first element in list */
1658 ah->cal_list_curr = ah->cal_list;
1660 if (ah->cal_list_curr)
1661 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1664 caldata->CalValid = 0;
1669 void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
1671 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1672 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1674 if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
1675 priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
1677 priv_ops->init_cal = ar9003_hw_init_cal_soc;
1679 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
1680 priv_ops->setup_calibration = ar9003_hw_setup_calibration;
1682 ops->calibrate = ar9003_hw_calibrate;