drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_phy.h"
  19
  20 static const int firstep_table[] =
  21 /* level:  0   1   2   3   4   5   6   7   8  */
  22         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  23
  24 static const int cycpwrThr1_table[] =
  25 /* level:  0   1   2   3   4   5   6   7   8  */
  26         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  27
  28 /*
  29  * register values to turn OFDM weak signal detection OFF
  30  */
  31 static const int m1ThreshLow_off = 127;
  32 static const int m2ThreshLow_off = 127;
  33 static const int m1Thresh_off = 127;
  34 static const int m2Thresh_off = 127;
  35 static const int m2CountThr_off =  31;
  36 static const int m2CountThrLow_off =  63;
  37 static const int m1ThreshLowExt_off = 127;
  38 static const int m2ThreshLowExt_off = 127;
  39 static const int m1ThreshExt_off = 127;
  40 static const int m2ThreshExt_off = 127;
  41
  42 /**
  43  * ar9003_hw_set_channel - set channel on single-chip device
  44  * @ah: atheros hardware structure
  45  * @chan:
  46  *
  47  * This is the function to change channel on single-chip devices, that is
  48  * all devices after ar9280.
  49  *
  50  * This function takes the channel value in MHz and sets
  51  * hardware channel value. Assumes writes have been enabled to analog bus.
  52  *
  53  * Actual Expression,
  54  *
  55  * For 2GHz channel,
  56  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  57  * (freq_ref = 40MHz)
  58  *
  59  * For 5GHz channel,
  60  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  61  * (freq_ref = 40MHz/(24>>amodeRefSel))
  62  *
  63  * For 5GHz channels which are 5MHz spaced,
  64  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  65  * (freq_ref = 40MHz)
  66  */
  67 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  68 {
  69         u16 bMode, fracMode = 0, aModeRefSel = 0;
  70         u32 freq, channelSel = 0, reg32 = 0;
  71         struct chan_centers centers;
  72         int loadSynthChannel;
  73
  74         ath9k_hw_get_channel_centers(ah, chan, &centers);
  75         freq = centers.synth_center;
  76
  77         if (freq < 4800) {     /* 2 GHz, fractional mode */
  78                 if (AR_SREV_9330(ah)) {
  79                         u32 chan_frac;
  80                         u32 div;
  81
  82                         if (ah->is_clk_25mhz)
  83                                 div = 75;
  84                         else
  85                                 div = 120;
  86
  87                         channelSel = (freq * 4) / div;
  88                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
  89                         channelSel = (channelSel << 17) | chan_frac;
  90                 } else if (AR_SREV_9485(ah)) {
  91                         u32 chan_frac;
  92
  93                         /*
  94                          * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
  95                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
  96                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
  97                          */
  98                         channelSel = (freq * 4) / 120;
  99                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
 100                         channelSel = (channelSel << 17) | chan_frac;
 101                 } else if (AR_SREV_9340(ah)) {
 102                         if (ah->is_clk_25mhz) {
 103                                 u32 chan_frac;
 104
 105                                 channelSel = (freq * 2) / 75;
 106                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 107                                 channelSel = (channelSel << 17) | chan_frac;
 108                         } else
 109                                 channelSel = CHANSEL_2G(freq) >> 1;
 110                 } else
 111                         channelSel = CHANSEL_2G(freq);
 112                 /* Set to 2G mode */
 113                 bMode = 1;
 114         } else {
 115                 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
 116                         u32 chan_frac;
 117
 118                         channelSel = (freq * 2) / 75;
 119                         chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 120                         channelSel = (channelSel << 17) | chan_frac;
 121                 } else {
 122                         channelSel = CHANSEL_5G(freq);
 123                         /* Doubler is ON, so, divide channelSel by 2. */
 124                         channelSel >>= 1;
 125                 }
 126                 /* Set to 5G mode */
 127                 bMode = 0;
 128         }
 129
 130         /* Enable fractional mode for all channels */
 131         fracMode = 1;
 132         aModeRefSel = 0;
 133         loadSynthChannel = 0;
 134
 135         reg32 = (bMode << 29);
 136         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 137
 138         /* Enable Long shift Select for Synthesizer */
 139         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 140                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 141
 142         /* Program Synth. setting */
 143         reg32 = (channelSel << 2) | (fracMode << 30) |
 144                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 145         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 146
 147         /* Toggle Load Synth channel bit */
 148         loadSynthChannel = 1;
 149         reg32 = (channelSel << 2) | (fracMode << 30) |
 150                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 151         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 152
 153         ah->curchan = chan;
 154         ah->curchan_rad_index = -1;
 155
 156         return 0;
 157 }
 158
 159 /**
 160  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 161  * @ah: atheros hardware structure
 162  * @chan:
 163  *
 164  * For single-chip solutions. Converts to baseband spur frequency given the
 165  * input channel frequency and compute register settings below.
 166  *
 167  * Spur mitigation for MRC CCK
 168  */
 169 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 170                                             struct ath9k_channel *chan)
 171 {
 172         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 173         int cur_bb_spur, negative = 0, cck_spur_freq;
 174         int i;
 175         int range, max_spur_cnts, synth_freq;
 176         u8 *spur_fbin_ptr = NULL;
 177
 178         /*
 179          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 180          * is out-of-band and can be ignored.
 181          */
 182
 183         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
 184                 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
 185                                                          IS_CHAN_2GHZ(chan));
 186                 if (spur_fbin_ptr[0] == 0) /* No spur */
 187                         return;
 188                 max_spur_cnts = 5;
 189                 if (IS_CHAN_HT40(chan)) {
 190                         range = 19;
 191                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 192                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 193                                 synth_freq = chan->channel + 10;
 194                         else
 195                                 synth_freq = chan->channel - 10;
 196                 } else {
 197                         range = 10;
 198                         synth_freq = chan->channel;
 199                 }
 200         } else {
 201                 range = 10;
 202                 max_spur_cnts = 4;
 203                 synth_freq = chan->channel;
 204         }
 205
 206         for (i = 0; i < max_spur_cnts; i++) {
 207                 negative = 0;
 208                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
 209                         cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
 210                                         IS_CHAN_2GHZ(chan)) - synth_freq;
 211                 else
 212                         cur_bb_spur = spur_freq[i] - synth_freq;
 213
 214                 if (cur_bb_spur < 0) {
 215                         negative = 1;
 216                         cur_bb_spur = -cur_bb_spur;
 217                 }
 218                 if (cur_bb_spur < range) {
 219                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 220
 221                         if (negative == 1)
 222                                 cck_spur_freq = -cck_spur_freq;
 223
 224                         cck_spur_freq = cck_spur_freq & 0xfffff;
 225
 226                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 227                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 228                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 229                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 230                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 231                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 232                                       0x2);
 233                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 234                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 235                                       0x1);
 236                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 237                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 238                                       cck_spur_freq);
 239
 240                         return;
 241                 }
 242         }
 243
 244         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 245                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 246         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 247                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 248         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 249                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 250 }
 251
 252 /* Clean all spur register fields */
 253 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 254 {
 255         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 256                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 257         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 258                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 259         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 260                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 261         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 262                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 263         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 264                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 265         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 266                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 267         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 268                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 269         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 270                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 271         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 272                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 273
 274         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 275                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 276         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 277                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 278         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 279                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 280         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 281                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 282         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 283                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 284         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 285                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 286         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 287                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 288         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 289                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 290         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 291                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 292         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 293                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 294 }
 295
 296 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 297                                 int freq_offset,
 298                                 int spur_freq_sd,
 299                                 int spur_delta_phase,
 300                                 int spur_subchannel_sd)
 301 {
 302         int mask_index = 0;
 303
 304         /* OFDM Spur mitigation */
 305         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 306                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 307         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 308                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 309         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 310                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 311         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 312                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 313         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 314                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 315         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 316                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 317         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 318                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 319         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 320                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 321         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 322                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 323
 324         if (REG_READ_FIELD(ah, AR_PHY_MODE,
 325                            AR_PHY_MODE_DYNAMIC) == 0x1)
 326                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 327                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 328
 329         mask_index = (freq_offset << 4) / 5;
 330         if (mask_index < 0)
 331                 mask_index = mask_index - 1;
 332
 333         mask_index = mask_index & 0x7f;
 334
 335         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 336                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 337         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 338                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 339         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 340                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 341         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 342                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 343         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 344                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 345         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 346                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 347         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 348                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 349         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 350                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 351         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 352                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 353         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 354                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 355 }
 356
 357 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 358                                      struct ath9k_channel *chan,
 359                                      int freq_offset)
 360 {
 361         int spur_freq_sd = 0;
 362         int spur_subchannel_sd = 0;
 363         int spur_delta_phase = 0;
 364
 365         if (IS_CHAN_HT40(chan)) {
 366                 if (freq_offset < 0) {
 367                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 368                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 369                                 spur_subchannel_sd = 1;
 370                         else
 371                                 spur_subchannel_sd = 0;
 372
 373                         spur_freq_sd = (freq_offset << 9) / 11;
 374
 375                 } else {
 376                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 377                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 378                                 spur_subchannel_sd = 0;
 379                         else
 380                                 spur_subchannel_sd = 1;
 381
 382                         spur_freq_sd = (freq_offset << 9) / 11;
 383
 384                 }
 385
 386                 spur_delta_phase = (freq_offset << 17) / 5;
 387
 388         } else {
 389                 spur_subchannel_sd = 0;
 390                 spur_freq_sd = (freq_offset << 9) /11;
 391                 spur_delta_phase = (freq_offset << 18) / 5;
 392         }
 393
 394         spur_freq_sd = spur_freq_sd & 0x3ff;
 395         spur_delta_phase = spur_delta_phase & 0xfffff;
 396
 397         ar9003_hw_spur_ofdm(ah,
 398                             freq_offset,
 399                             spur_freq_sd,
 400                             spur_delta_phase,
 401                             spur_subchannel_sd);
 402 }
 403
 404 /* Spur mitigation for OFDM */
 405 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 406                                          struct ath9k_channel *chan)
 407 {
 408         int synth_freq;
 409         int range = 10;
 410         int freq_offset = 0;
 411         int mode;
 412         u8* spurChansPtr;
 413         unsigned int i;
 414         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 415
 416         if (IS_CHAN_5GHZ(chan)) {
 417                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 418                 mode = 0;
 419         }
 420         else {
 421                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 422                 mode = 1;
 423         }
 424
 425         if (spurChansPtr[0] == 0)
 426                 return; /* No spur in the mode */
 427
 428         if (IS_CHAN_HT40(chan)) {
 429                 range = 19;
 430                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 431                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 432                         synth_freq = chan->channel - 10;
 433                 else
 434                         synth_freq = chan->channel + 10;
 435         } else {
 436                 range = 10;
 437                 synth_freq = chan->channel;
 438         }
 439
 440         ar9003_hw_spur_ofdm_clear(ah);
 441
 442         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 443                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
 444                 if (abs(freq_offset) < range) {
 445                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
 446                         break;
 447                 }
 448         }
 449 }
 450
 451 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 452                                     struct ath9k_channel *chan)
 453 {
 454         ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 455         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 456 }
 457
 458 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 459                                          struct ath9k_channel *chan)
 460 {
 461         u32 pll;
 462
 463         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 464
 465         if (chan && IS_CHAN_HALF_RATE(chan))
 466                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 467         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 468                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 469
 470         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 471
 472         return pll;
 473 }
 474
 475 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 476                                        struct ath9k_channel *chan)
 477 {
 478         u32 phymode;
 479         u32 enableDacFifo = 0;
 480
 481         enableDacFifo =
 482                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 483
 484         /* Enable 11n HT, 20 MHz */
 485         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
 486                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 487
 488         /* Configure baseband for dynamic 20/40 operation */
 489         if (IS_CHAN_HT40(chan)) {
 490                 phymode |= AR_PHY_GC_DYN2040_EN;
 491                 /* Configure control (primary) channel at +-10MHz */
 492                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 493                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 494                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 495
 496         }
 497
 498         /* make sure we preserve INI settings */
 499         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 500         /* turn off Green Field detection for STA for now */
 501         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 502
 503         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 504
 505         /* Configure MAC for 20/40 operation */
 506         ath9k_hw_set11nmac2040(ah);
 507
 508         /* global transmit timeout (25 TUs default)*/
 509         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 510         /* carrier sense timeout */
 511         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 512 }
 513
 514 static void ar9003_hw_init_bb(struct ath_hw *ah,
 515                               struct ath9k_channel *chan)
 516 {
 517         u32 synthDelay;
 518
 519         /*
 520          * Wait for the frequency synth to settle (synth goes on
 521          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 522          * Value is in 100ns increments.
 523          */
 524         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 525         if (IS_CHAN_B(chan))
 526                 synthDelay = (4 * synthDelay) / 22;
 527         else
 528                 synthDelay /= 10;
 529
 530         /* Activate the PHY (includes baseband activate + synthesizer on) */
 531         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 532
 533         /*
 534          * There is an issue if the AP starts the calibration before
 535          * the base band timeout completes.  This could result in the
 536          * rx_clear false triggering.  As a workaround we add delay an
 537          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
 538          * does not happen.
 539          */
 540         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 541 }
 542
 543 static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 544 {
 545         switch (rx) {
 546         case 0x5:
 547                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 548                             AR_PHY_SWAP_ALT_CHAIN);
 549         case 0x3:
 550         case 0x1:
 551         case 0x2:
 552         case 0x7:
 553                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 554                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 555                 break;
 556         default:
 557                 break;
 558         }
 559
 560         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 561                 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
 562         else if (AR_SREV_9480(ah))
 563                 /* xxx only when MCI support is enabled */
 564                 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
 565         else
 566                 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 567
 568         if (tx == 0x5) {
 569                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 570                             AR_PHY_SWAP_ALT_CHAIN);
 571         }
 572 }
 573
 574 /*
 575  * Override INI values with chip specific configuration.
 576  */
 577 static void ar9003_hw_override_ini(struct ath_hw *ah)
 578 {
 579         u32 val;
 580
 581         /*
 582          * Set the RX_ABORT and RX_DIS and clear it only after
 583          * RXE is set for MAC. This prevents frames with
 584          * corrupted descriptor status.
 585          */
 586         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 587
 588         /*
 589          * For AR9280 and above, there is a new feature that allows
 590          * Multicast search based on both MAC Address and Key ID. By default,
 591          * this feature is enabled. But since the driver is not using this
 592          * feature, we switch it off; otherwise multicast search based on
 593          * MAC addr only will fail.
 594          */
 595         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 596         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 597                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 598 }
 599
 600 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 601                                struct ar5416IniArray *iniArr,
 602                                int column)
 603 {
 604         unsigned int i, regWrites = 0;
 605
 606         /* New INI format: Array may be undefined (pre, core, post arrays) */
 607         if (!iniArr->ia_array)
 608                 return;
 609
 610         /*
 611          * New INI format: Pre, core, and post arrays for a given subsystem
 612          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 613          * the array is non-modal and force the column to 1.
 614          */
 615         if (column >= iniArr->ia_columns)
 616                 column = 1;
 617
 618         for (i = 0; i < iniArr->ia_rows; i++) {
 619                 u32 reg = INI_RA(iniArr, i, 0);
 620                 u32 val = INI_RA(iniArr, i, column);
 621
 622                 REG_WRITE(ah, reg, val);
 623
 624                 DO_DELAY(regWrites);
 625         }
 626 }
 627
 628 static int ar9003_hw_process_ini(struct ath_hw *ah,
 629                                  struct ath9k_channel *chan)
 630 {
 631         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 632         unsigned int regWrites = 0, i;
 633         struct ieee80211_channel *channel = chan->chan;
 634         u32 modesIndex;
 635
 636         switch (chan->chanmode) {
 637         case CHANNEL_A:
 638         case CHANNEL_A_HT20:
 639                 modesIndex = 1;
 640                 break;
 641         case CHANNEL_A_HT40PLUS:
 642         case CHANNEL_A_HT40MINUS:
 643                 modesIndex = 2;
 644                 break;
 645         case CHANNEL_G:
 646         case CHANNEL_G_HT20:
 647         case CHANNEL_B:
 648                 modesIndex = 4;
 649                 break;
 650         case CHANNEL_G_HT40PLUS:
 651         case CHANNEL_G_HT40MINUS:
 652                 modesIndex = 3;
 653                 break;
 654
 655         default:
 656                 return -EINVAL;
 657         }
 658
 659         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 660                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 661                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 662                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 663                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 664                 if (i == ATH_INI_POST && AR_SREV_9480_20(ah))
 665                         ar9003_hw_prog_ini(ah,
 666                                            &ah->ini_radio_post_sys2ant,
 667                                            modesIndex);
 668         }
 669
 670         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 671         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 672
 673         /*
 674          * For 5GHz channels requiring Fast Clock, apply
 675          * different modal values.
 676          */
 677         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 678                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
 679                                 modesIndex, regWrites);
 680
 681         if (AR_SREV_9300(ah))
 682                 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
 683
 684         if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
 685                 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
 686
 687         if (AR_SREV_9480(ah))
 688                 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
 689
 690         ar9003_hw_override_ini(ah);
 691         ar9003_hw_set_channel_regs(ah, chan);
 692         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 693
 694         /* Set TX power */
 695         ah->eep_ops->set_txpower(ah, chan,
 696                                  ath9k_regd_get_ctl(regulatory, chan),
 697                                  channel->max_antenna_gain * 2,
 698                                  channel->max_power * 2,
 699                                  min((u32) MAX_RATE_POWER,
 700                                  (u32) regulatory->power_limit), false);
 701
 702         return 0;
 703 }
 704
 705 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 706                                  struct ath9k_channel *chan)
 707 {
 708         u32 rfMode = 0;
 709
 710         if (chan == NULL)
 711                 return;
 712
 713         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 714                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 715
 716         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 717                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 718
 719         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 720 }
 721
 722 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 723 {
 724         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 725 }
 726
 727 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 728                                       struct ath9k_channel *chan)
 729 {
 730         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 731         u32 clockMhzScaled = 0x64000000;
 732         struct chan_centers centers;
 733
 734         /*
 735          * half and quarter rate can divide the scaled clock by 2 or 4
 736          * scale for selected channel bandwidth
 737          */
 738         if (IS_CHAN_HALF_RATE(chan))
 739                 clockMhzScaled = clockMhzScaled >> 1;
 740         else if (IS_CHAN_QUARTER_RATE(chan))
 741                 clockMhzScaled = clockMhzScaled >> 2;
 742
 743         /*
 744          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 745          * scaled coef to provide precision for this floating calculation
 746          */
 747         ath9k_hw_get_channel_centers(ah, chan, &centers);
 748         coef_scaled = clockMhzScaled / centers.synth_center;
 749
 750         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 751                                       &ds_coef_exp);
 752
 753         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 754                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 755         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 756                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 757
 758         /*
 759          * For Short GI,
 760          * scaled coeff is 9/10 that of normal coeff
 761          */
 762         coef_scaled = (9 * coef_scaled) / 10;
 763
 764         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 765                                       &ds_coef_exp);
 766
 767         /* for short gi */
 768         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 769                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 770         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 771                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 772 }
 773
 774 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 775 {
 776         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 777         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 778                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 779 }
 780
 781 /*
 782  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 783  * Read the phy active delay register. Value is in 100ns increments.
 784  */
 785 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 786 {
 787         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 788         if (IS_CHAN_B(ah->curchan))
 789                 synthDelay = (4 * synthDelay) / 22;
 790         else
 791                 synthDelay /= 10;
 792
 793         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 794
 795         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 796 }
 797
 798 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 799 {
 800         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
 801         if (value)
 802                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 803         else
 804                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 805         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
 806 }
 807
 808 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 809                                   enum ath9k_ani_cmd cmd, int param)
 810 {
 811         struct ath_common *common = ath9k_hw_common(ah);
 812         struct ath9k_channel *chan = ah->curchan;
 813         struct ar5416AniState *aniState = &chan->ani;
 814         s32 value, value2;
 815
 816         switch (cmd & ah->ani_function) {
 817         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 818                 /*
 819                  * on == 1 means ofdm weak signal detection is ON
 820                  * on == 1 is the default, for less noise immunity
 821                  *
 822                  * on == 0 means ofdm weak signal detection is OFF
 823                  * on == 0 means more noise imm
 824                  */
 825                 u32 on = param ? 1 : 0;
 826                 /*
 827                  * make register setting for default
 828                  * (weak sig detect ON) come from INI file
 829                  */
 830                 int m1ThreshLow = on ?
 831                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
 832                 int m2ThreshLow = on ?
 833                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
 834                 int m1Thresh = on ?
 835                         aniState->iniDef.m1Thresh : m1Thresh_off;
 836                 int m2Thresh = on ?
 837                         aniState->iniDef.m2Thresh : m2Thresh_off;
 838                 int m2CountThr = on ?
 839                         aniState->iniDef.m2CountThr : m2CountThr_off;
 840                 int m2CountThrLow = on ?
 841                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
 842                 int m1ThreshLowExt = on ?
 843                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
 844                 int m2ThreshLowExt = on ?
 845                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
 846                 int m1ThreshExt = on ?
 847                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
 848                 int m2ThreshExt = on ?
 849                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 850
 851                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 852                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 853                               m1ThreshLow);
 854                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 855                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 856                               m2ThreshLow);
 857                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 858                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
 859                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 860                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
 861                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 862                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
 863                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 864                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
 865                               m2CountThrLow);
 866
 867                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 868                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
 869                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 870                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
 871                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 872                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
 873                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 874                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
 875
 876                 if (on)
 877                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
 878                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 879                 else
 880                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
 881                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 882
 883                 if (!on != aniState->ofdmWeakSigDetectOff) {
 884                         ath_dbg(common, ATH_DBG_ANI,
 885                                 "** ch %d: ofdm weak signal: %s=>%s\n",
 886                                 chan->channel,
 887                                 !aniState->ofdmWeakSigDetectOff ?
 888                                 "on" : "off",
 889                                 on ? "on" : "off");
 890                         if (on)
 891                                 ah->stats.ast_ani_ofdmon++;
 892                         else
 893                                 ah->stats.ast_ani_ofdmoff++;
 894                         aniState->ofdmWeakSigDetectOff = !on;
 895                 }
 896                 break;
 897         }
 898         case ATH9K_ANI_FIRSTEP_LEVEL:{
 899                 u32 level = param;
 900
 901                 if (level >= ARRAY_SIZE(firstep_table)) {
 902                         ath_dbg(common, ATH_DBG_ANI,
 903                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
 904                                 level, ARRAY_SIZE(firstep_table));
 905                         return false;
 906                 }
 907
 908                 /*
 909                  * make register setting relative to default
 910                  * from INI file & cap value
 911                  */
 912                 value = firstep_table[level] -
 913                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
 914                         aniState->iniDef.firstep;
 915                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 916                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 917                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 918                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 919                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 920                               AR_PHY_FIND_SIG_FIRSTEP,
 921                               value);
 922                 /*
 923                  * we need to set first step low register too
 924                  * make register setting relative to default
 925                  * from INI file & cap value
 926                  */
 927                 value2 = firstep_table[level] -
 928                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
 929                          aniState->iniDef.firstepLow;
 930                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 931                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 932                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 933                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 934
 935                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
 936                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
 937
 938                 if (level != aniState->firstepLevel) {
 939                         ath_dbg(common, ATH_DBG_ANI,
 940                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
 941                                 chan->channel,
 942                                 aniState->firstepLevel,
 943                                 level,
 944                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
 945                                 value,
 946                                 aniState->iniDef.firstep);
 947                         ath_dbg(common, ATH_DBG_ANI,
 948                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
 949                                 chan->channel,
 950                                 aniState->firstepLevel,
 951                                 level,
 952                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
 953                                 value2,
 954                                 aniState->iniDef.firstepLow);
 955                         if (level > aniState->firstepLevel)
 956                                 ah->stats.ast_ani_stepup++;
 957                         else if (level < aniState->firstepLevel)
 958                                 ah->stats.ast_ani_stepdown++;
 959                         aniState->firstepLevel = level;
 960                 }
 961                 break;
 962         }
 963         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
 964                 u32 level = param;
 965
 966                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
 967                         ath_dbg(common, ATH_DBG_ANI,
 968                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
 969                                 level, ARRAY_SIZE(cycpwrThr1_table));
 970                         return false;
 971                 }
 972                 /*
 973                  * make register setting relative to default
 974                  * from INI file & cap value
 975                  */
 976                 value = cycpwrThr1_table[level] -
 977                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
 978                         aniState->iniDef.cycpwrThr1;
 979                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
 980                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
 981                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
 982                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
 983                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
 984                               AR_PHY_TIMING5_CYCPWR_THR1,
 985                               value);
 986
 987                 /*
 988                  * set AR_PHY_EXT_CCA for extension channel
 989                  * make register setting relative to default
 990                  * from INI file & cap value
 991                  */
 992                 value2 = cycpwrThr1_table[level] -
 993                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
 994                          aniState->iniDef.cycpwrThr1Ext;
 995                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
 996                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
 997                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
 998                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
 999                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1000                               AR_PHY_EXT_CYCPWR_THR1, value2);
1001
1002                 if (level != aniState->spurImmunityLevel) {
1003                         ath_dbg(common, ATH_DBG_ANI,
1004                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1005                                 chan->channel,
1006                                 aniState->spurImmunityLevel,
1007                                 level,
1008                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1009                                 value,
1010                                 aniState->iniDef.cycpwrThr1);
1011                         ath_dbg(common, ATH_DBG_ANI,
1012                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1013                                 chan->channel,
1014                                 aniState->spurImmunityLevel,
1015                                 level,
1016                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1017                                 value2,
1018                                 aniState->iniDef.cycpwrThr1Ext);
1019                         if (level > aniState->spurImmunityLevel)
1020                                 ah->stats.ast_ani_spurup++;
1021                         else if (level < aniState->spurImmunityLevel)
1022                                 ah->stats.ast_ani_spurdown++;
1023                         aniState->spurImmunityLevel = level;
1024                 }
1025                 break;
1026         }
1027         case ATH9K_ANI_MRC_CCK:{
1028                 /*
1029                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1030                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1031                  */
1032                 bool is_on = param ? 1 : 0;
1033                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1034                               AR_PHY_MRC_CCK_ENABLE, is_on);
1035                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1036                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1037                 if (!is_on != aniState->mrcCCKOff) {
1038                         ath_dbg(common, ATH_DBG_ANI,
1039                                 "** ch %d: MRC CCK: %s=>%s\n",
1040                                 chan->channel,
1041                                 !aniState->mrcCCKOff ? "on" : "off",
1042                                 is_on ? "on" : "off");
1043                 if (is_on)
1044                         ah->stats.ast_ani_ccklow++;
1045                 else
1046                         ah->stats.ast_ani_cckhigh++;
1047                 aniState->mrcCCKOff = !is_on;
1048                 }
1049         break;
1050         }
1051         case ATH9K_ANI_PRESENT:
1052                 break;
1053         default:
1054                 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1055                 return false;
1056         }
1057
1058         ath_dbg(common, ATH_DBG_ANI,
1059                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1060                 aniState->spurImmunityLevel,
1061                 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1062                 aniState->firstepLevel,
1063                 !aniState->mrcCCKOff ? "on" : "off",
1064                 aniState->listenTime,
1065                 aniState->ofdmPhyErrCount,
1066                 aniState->cckPhyErrCount);
1067         return true;
1068 }
1069
1070 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1071                               int16_t nfarray[NUM_NF_READINGS])
1072 {
1073 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1074 #define AR_PHY_CH_MINCCA_PWR_S  20
1075 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1076 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1077
1078         int16_t nf;
1079         int i;
1080
1081         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1082                 if (ah->rxchainmask & BIT(i)) {
1083                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1084                                          AR_PHY_CH_MINCCA_PWR);
1085                         nfarray[i] = sign_extend32(nf, 8);
1086
1087                         if (IS_CHAN_HT40(ah->curchan)) {
1088                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1089
1090                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1091                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1092                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1093                         }
1094                 }
1095         }
1096 }
1097
1098 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1099 {
1100         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1101         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1102         if (AR_SREV_9330(ah))
1103                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1104         else
1105                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1106         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1107         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1108         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1109 }
1110
1111 /*
1112  * Initialize the ANI register values with default (ini) values.
1113  * This routine is called during a (full) hardware reset after
1114  * all the registers are initialised from the INI.
1115  */
1116 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1117 {
1118         struct ar5416AniState *aniState;
1119         struct ath_common *common = ath9k_hw_common(ah);
1120         struct ath9k_channel *chan = ah->curchan;
1121         struct ath9k_ani_default *iniDef;
1122         u32 val;
1123
1124         aniState = &ah->curchan->ani;
1125         iniDef = &aniState->iniDef;
1126
1127         ath_dbg(common, ATH_DBG_ANI,
1128                 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1129                 ah->hw_version.macVersion,
1130                 ah->hw_version.macRev,
1131                 ah->opmode,
1132                 chan->channel,
1133                 chan->channelFlags);
1134
1135         val = REG_READ(ah, AR_PHY_SFCORR);
1136         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1137         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1138         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1139
1140         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1141         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1142         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1143         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1144
1145         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1146         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1147         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1148         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1149         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1150         iniDef->firstep = REG_READ_FIELD(ah,
1151                                          AR_PHY_FIND_SIG,
1152                                          AR_PHY_FIND_SIG_FIRSTEP);
1153         iniDef->firstepLow = REG_READ_FIELD(ah,
1154                                             AR_PHY_FIND_SIG_LOW,
1155                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1156         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1157                                             AR_PHY_TIMING5,
1158                                             AR_PHY_TIMING5_CYCPWR_THR1);
1159         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1160                                                AR_PHY_EXT_CCA,
1161                                                AR_PHY_EXT_CYCPWR_THR1);
1162
1163         /* these levels just got reset to defaults by the INI */
1164         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1165         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1166         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1167         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1168 }
1169
1170 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1171                                        struct ath_hw_radar_conf *conf)
1172 {
1173         u32 radar_0 = 0, radar_1 = 0;
1174
1175         if (!conf) {
1176                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1177                 return;
1178         }
1179
1180         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1181         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1182         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1183         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1184         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1185         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1186
1187         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1188         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1189         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1190         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1191         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1192
1193         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1194         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1195         if (conf->ext_channel)
1196                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1197         else
1198                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1199 }
1200
1201 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1202 {
1203         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1204
1205         conf->fir_power = -28;
1206         conf->radar_rssi = 0;
1207         conf->pulse_height = 10;
1208         conf->pulse_rssi = 24;
1209         conf->pulse_inband = 8;
1210         conf->pulse_maxlen = 255;
1211         conf->pulse_inband_step = 12;
1212         conf->radar_inband = 8;
1213 }
1214
1215 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1216                                    struct ath_hw_antcomb_conf *antconf)
1217 {
1218         u32 regval;
1219
1220         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1221         antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1222                                   AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1223         antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1224                                  AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1225         antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1226                                   AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1227
1228         if (AR_SREV_9330_11(ah)) {
1229                 antconf->lna1_lna2_delta = -9;
1230                 antconf->div_group = 1;
1231         } else if (AR_SREV_9485(ah)) {
1232                 antconf->lna1_lna2_delta = -9;
1233                 antconf->div_group = 2;
1234         } else {
1235                 antconf->lna1_lna2_delta = -3;
1236                 antconf->div_group = 0;
1237         }
1238 }
1239
1240 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1241                                    struct ath_hw_antcomb_conf *antconf)
1242 {
1243         u32 regval;
1244
1245         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1246         regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1247                     AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1248                     AR_PHY_9485_ANT_FAST_DIV_BIAS |
1249                     AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1250                     AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1251         regval |= ((antconf->main_lna_conf <<
1252                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1253                    & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1254         regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1255                    & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1256         regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1257                    & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1258         regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1259                    & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1260         regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1261                    & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1262
1263         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1264 }
1265
1266 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1267 {
1268         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1269         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1270         static const u32 ar9300_cca_regs[6] = {
1271                 AR_PHY_CCA_0,
1272                 AR_PHY_CCA_1,
1273                 AR_PHY_CCA_2,
1274                 AR_PHY_EXT_CCA,
1275                 AR_PHY_EXT_CCA_1,
1276                 AR_PHY_EXT_CCA_2,
1277         };
1278
1279         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1280         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1281         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1282         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1283         priv_ops->init_bb = ar9003_hw_init_bb;
1284         priv_ops->process_ini = ar9003_hw_process_ini;
1285         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1286         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1287         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1288         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1289         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1290         priv_ops->set_diversity = ar9003_hw_set_diversity;
1291         priv_ops->ani_control = ar9003_hw_ani_control;
1292         priv_ops->do_getnf = ar9003_hw_do_getnf;
1293         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1294         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1295
1296         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1297         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1298
1299         ar9003_hw_set_nf_limits(ah);
1300         ar9003_hw_set_radar_conf(ah);
1301         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1302 }
1303
1304 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1305 {
1306         struct ath_common *common = ath9k_hw_common(ah);
1307         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1308         u32 val, idle_count;
1309
1310         if (!idle_tmo_ms) {
1311                 /* disable IRQ, disable chip-reset for BB panic */
1312                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1313                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1314                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1315                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1316
1317                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1318                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1319                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1320                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1321                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1322
1323                 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1324                 return;
1325         }
1326
1327         /* enable IRQ, disable chip-reset for BB watchdog */
1328         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1329         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1330                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1331                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1332
1333         /* bound limit to 10 secs */
1334         if (idle_tmo_ms > 10000)
1335                 idle_tmo_ms = 10000;
1336
1337         /*
1338          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1339          *
1340          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1341          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1342          *
1343          * Given we use fast clock now in 5 GHz, these time units should
1344          * be common for both 2 GHz and 5 GHz.
1345          */
1346         idle_count = (100 * idle_tmo_ms) / 74;
1347         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1348                 idle_count = (100 * idle_tmo_ms) / 37;
1349
1350         /*
1351          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1352          * set idle time-out.
1353          */
1354         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1355                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1356                   AR_PHY_WATCHDOG_IDLE_MASK |
1357                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1358
1359         ath_dbg(common, ATH_DBG_RESET,
1360                 "Enabled BB Watchdog timeout (%u ms)\n",
1361                 idle_tmo_ms);
1362 }
1363
1364 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1365 {
1366         /*
1367          * we want to avoid printing in ISR context so we save the
1368          * watchdog status to be printed later in bottom half context.
1369          */
1370         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1371
1372         /*
1373          * the watchdog timer should reset on status read but to be sure
1374          * sure we write 0 to the watchdog status bit.
1375          */
1376         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1377                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1378 }
1379
1380 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1381 {
1382         struct ath_common *common = ath9k_hw_common(ah);
1383         u32 status;
1384
1385         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1386                 return;
1387
1388         status = ah->bb_watchdog_last_status;
1389         ath_dbg(common, ATH_DBG_RESET,
1390                 "\n==== BB update: BB status=0x%08x ====\n", status);
1391         ath_dbg(common, ATH_DBG_RESET,
1392                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1393                 MS(status, AR_PHY_WATCHDOG_INFO),
1394                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1395                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1396                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1397                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1398                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1399                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1400                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1401                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1402
1403         ath_dbg(common, ATH_DBG_RESET,
1404                 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1405                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1406                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1407         ath_dbg(common, ATH_DBG_RESET,
1408                 "** BB mode: BB_gen_controls=0x%08x **\n",
1409                 REG_READ(ah, AR_PHY_GEN_CTRL));
1410
1411 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1412         if (common->cc_survey.cycles)
1413                 ath_dbg(common, ATH_DBG_RESET,
1414                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1415                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1416
1417         ath_dbg(common, ATH_DBG_RESET,
1418                 "==== BB update: done ====\n\n");
1419 }
1420 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1421
1422 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1423 {
1424         u32 val;
1425
1426         /* While receiving unsupported rate frame rx state machine
1427          * gets into a state 0xb and if phy_restart happens in that
1428          * state, BB would go hang. If RXSM is in 0xb state after
1429          * first bb panic, ensure to disable the phy_restart.
1430          */
1431         if (!((MS(ah->bb_watchdog_last_status,
1432                   AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1433             ah->bb_hang_rx_ofdm))
1434                 return;
1435
1436         ah->bb_hang_rx_ofdm = true;
1437         val = REG_READ(ah, AR_PHY_RESTART);
1438         val &= ~AR_PHY_RESTART_ENA;
1439
1440         REG_WRITE(ah, AR_PHY_RESTART, val);
1441 }
1442 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);