2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 MODULE_AUTHOR("Atheros Communications");
20 MODULE_LICENSE("Dual BSD/GPL");
21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
24 module_param_named(debug, ath9k_debug, uint, 0);
25 MODULE_PARM_DESC(debug, "Debugging mask");
27 int htc_modparam_nohwcrypt;
28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31 #define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
37 #define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
44 #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
46 static struct ieee80211_channel ath9k_2ghz_channels[] = {
47 CHAN2G(2412, 0), /* Channel 1 */
48 CHAN2G(2417, 1), /* Channel 2 */
49 CHAN2G(2422, 2), /* Channel 3 */
50 CHAN2G(2427, 3), /* Channel 4 */
51 CHAN2G(2432, 4), /* Channel 5 */
52 CHAN2G(2437, 5), /* Channel 6 */
53 CHAN2G(2442, 6), /* Channel 7 */
54 CHAN2G(2447, 7), /* Channel 8 */
55 CHAN2G(2452, 8), /* Channel 9 */
56 CHAN2G(2457, 9), /* Channel 10 */
57 CHAN2G(2462, 10), /* Channel 11 */
58 CHAN2G(2467, 11), /* Channel 12 */
59 CHAN2G(2472, 12), /* Channel 13 */
60 CHAN2G(2484, 13), /* Channel 14 */
63 static struct ieee80211_channel ath9k_5ghz_channels[] = {
64 /* _We_ call this UNII 1 */
65 CHAN5G(5180, 14), /* Channel 36 */
66 CHAN5G(5200, 15), /* Channel 40 */
67 CHAN5G(5220, 16), /* Channel 44 */
68 CHAN5G(5240, 17), /* Channel 48 */
69 /* _We_ call this UNII 2 */
70 CHAN5G(5260, 18), /* Channel 52 */
71 CHAN5G(5280, 19), /* Channel 56 */
72 CHAN5G(5300, 20), /* Channel 60 */
73 CHAN5G(5320, 21), /* Channel 64 */
74 /* _We_ call this "Middle band" */
75 CHAN5G(5500, 22), /* Channel 100 */
76 CHAN5G(5520, 23), /* Channel 104 */
77 CHAN5G(5540, 24), /* Channel 108 */
78 CHAN5G(5560, 25), /* Channel 112 */
79 CHAN5G(5580, 26), /* Channel 116 */
80 CHAN5G(5600, 27), /* Channel 120 */
81 CHAN5G(5620, 28), /* Channel 124 */
82 CHAN5G(5640, 29), /* Channel 128 */
83 CHAN5G(5660, 30), /* Channel 132 */
84 CHAN5G(5680, 31), /* Channel 136 */
85 CHAN5G(5700, 32), /* Channel 140 */
86 /* _We_ call this UNII 3 */
87 CHAN5G(5745, 33), /* Channel 149 */
88 CHAN5G(5765, 34), /* Channel 153 */
89 CHAN5G(5785, 35), /* Channel 157 */
90 CHAN5G(5805, 36), /* Channel 161 */
91 CHAN5G(5825, 37), /* Channel 165 */
94 /* Atheros hardware rate code addition for short premble */
95 #define SHPCHECK(__hw_rate, __flags) \
96 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
98 #define RATE(_bitrate, _hw_rate, _flags) { \
99 .bitrate = (_bitrate), \
101 .hw_value = (_hw_rate), \
102 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
105 static struct ieee80211_rate ath9k_legacy_rates[] = {
107 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
108 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
109 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
120 #ifdef CONFIG_MAC80211_LEDS
121 static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
122 { .throughput = 0 * 1024, .blink_time = 334 },
123 { .throughput = 1 * 1024, .blink_time = 260 },
124 { .throughput = 5 * 1024, .blink_time = 220 },
125 { .throughput = 10 * 1024, .blink_time = 190 },
126 { .throughput = 20 * 1024, .blink_time = 170 },
127 { .throughput = 50 * 1024, .blink_time = 150 },
128 { .throughput = 70 * 1024, .blink_time = 130 },
129 { .throughput = 100 * 1024, .blink_time = 110 },
130 { .throughput = 200 * 1024, .blink_time = 80 },
131 { .throughput = 300 * 1024, .blink_time = 50 },
135 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
139 if (atomic_read(&priv->htc->tgt_ready) > 0) {
140 atomic_dec(&priv->htc->tgt_ready);
144 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
145 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
147 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
151 atomic_dec(&priv->htc->tgt_ready);
156 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
158 ath9k_hw_deinit(priv->ah);
163 static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
165 struct ieee80211_hw *hw = priv->hw;
167 wiphy_rfkill_stop_polling(hw->wiphy);
168 ath9k_deinit_leds(priv);
169 ieee80211_unregister_hw(hw);
170 ath9k_rx_cleanup(priv);
171 ath9k_tx_cleanup(priv);
172 ath9k_deinit_priv(priv);
175 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
179 enum htc_endpoint_id,
181 enum htc_endpoint_id *ep_id)
183 struct htc_service_connreq req;
185 memset(&req, 0, sizeof(struct htc_service_connreq));
187 req.service_id = service_id;
188 req.ep_callbacks.priv = priv;
189 req.ep_callbacks.rx = ath9k_htc_rxep;
190 req.ep_callbacks.tx = tx;
192 return htc_connect_service(priv->htc, &req, ep_id);
195 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
201 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
206 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
212 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
219 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
225 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
231 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
237 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
243 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
249 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
255 * Setup required credits before initializing HTC.
256 * This is a bit hacky, but, since queuing is done in
257 * the HIF layer, shouldn't matter much.
260 if (IS_AR7010_DEVICE(drv_info))
261 priv->htc->credits = 45;
263 priv->htc->credits = 33;
265 ret = htc_init(priv->htc);
269 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
275 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
279 static int ath9k_reg_notifier(struct wiphy *wiphy,
280 struct regulatory_request *request)
282 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
283 struct ath9k_htc_priv *priv = hw->priv;
285 return ath_reg_notifier_apply(wiphy, request,
286 ath9k_hw_regulatory(priv->ah));
289 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
291 struct ath_hw *ah = (struct ath_hw *) hw_priv;
292 struct ath_common *common = ath9k_hw_common(ah);
293 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
294 __be32 val, reg = cpu_to_be32(reg_offset);
297 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
298 (u8 *) ®, sizeof(reg),
299 (u8 *) &val, sizeof(val),
302 ath_dbg(common, ATH_DBG_WMI,
303 "REGISTER READ FAILED: (0x%04x, %d)\n",
308 return be32_to_cpu(val);
311 static void ath9k_multi_regread(void *hw_priv, u32 *addr,
314 struct ath_hw *ah = (struct ath_hw *) hw_priv;
315 struct ath_common *common = ath9k_hw_common(ah);
316 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
321 for (i = 0; i < count; i++) {
322 tmpaddr[i] = cpu_to_be32(addr[i]);
325 ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
326 (u8 *)tmpaddr , sizeof(u32) * count,
327 (u8 *)tmpval, sizeof(u32) * count,
330 ath_dbg(common, ATH_DBG_WMI,
331 "Multiple REGISTER READ FAILED (count: %d)\n", count);
334 for (i = 0; i < count; i++) {
335 val[i] = be32_to_cpu(tmpval[i]);
339 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
341 struct ath_hw *ah = (struct ath_hw *) hw_priv;
342 struct ath_common *common = ath9k_hw_common(ah);
343 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
344 const __be32 buf[2] = {
345 cpu_to_be32(reg_offset),
350 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
351 (u8 *) &buf, sizeof(buf),
352 (u8 *) &val, sizeof(val),
355 ath_dbg(common, ATH_DBG_WMI,
356 "REGISTER WRITE FAILED:(0x%04x, %d)\n",
361 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
363 struct ath_hw *ah = (struct ath_hw *) hw_priv;
364 struct ath_common *common = ath9k_hw_common(ah);
365 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
369 mutex_lock(&priv->wmi->multi_write_mutex);
371 /* Store the register/value */
372 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
373 cpu_to_be32(reg_offset);
374 priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
377 priv->wmi->multi_write_idx++;
379 /* If the buffer is full, send it out. */
380 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
381 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
382 (u8 *) &priv->wmi->multi_write,
383 sizeof(struct register_write) * priv->wmi->multi_write_idx,
384 (u8 *) &rsp_status, sizeof(rsp_status),
387 ath_dbg(common, ATH_DBG_WMI,
388 "REGISTER WRITE FAILED, multi len: %d\n",
389 priv->wmi->multi_write_idx);
391 priv->wmi->multi_write_idx = 0;
394 mutex_unlock(&priv->wmi->multi_write_mutex);
397 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
399 struct ath_hw *ah = (struct ath_hw *) hw_priv;
400 struct ath_common *common = ath9k_hw_common(ah);
401 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
403 if (atomic_read(&priv->wmi->mwrite_cnt))
404 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
406 ath9k_regwrite_single(hw_priv, val, reg_offset);
409 static void ath9k_enable_regwrite_buffer(void *hw_priv)
411 struct ath_hw *ah = (struct ath_hw *) hw_priv;
412 struct ath_common *common = ath9k_hw_common(ah);
413 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
415 atomic_inc(&priv->wmi->mwrite_cnt);
418 static void ath9k_regwrite_flush(void *hw_priv)
420 struct ath_hw *ah = (struct ath_hw *) hw_priv;
421 struct ath_common *common = ath9k_hw_common(ah);
422 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
426 atomic_dec(&priv->wmi->mwrite_cnt);
428 mutex_lock(&priv->wmi->multi_write_mutex);
430 if (priv->wmi->multi_write_idx) {
431 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
432 (u8 *) &priv->wmi->multi_write,
433 sizeof(struct register_write) * priv->wmi->multi_write_idx,
434 (u8 *) &rsp_status, sizeof(rsp_status),
437 ath_dbg(common, ATH_DBG_WMI,
438 "REGISTER WRITE FAILED, multi len: %d\n",
439 priv->wmi->multi_write_idx);
441 priv->wmi->multi_write_idx = 0;
444 mutex_unlock(&priv->wmi->multi_write_mutex);
447 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
451 val = ath9k_regread(hw_priv, reg_offset);
454 ath9k_regwrite(hw_priv, val, reg_offset);
458 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
460 *csz = L1_CACHE_BYTES >> 2;
463 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
465 struct ath_hw *ah = (struct ath_hw *) common->ah;
467 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
469 if (!ath9k_hw_wait(ah,
470 AR_EEPROM_STATUS_DATA,
471 AR_EEPROM_STATUS_DATA_BUSY |
472 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
476 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
477 AR_EEPROM_STATUS_DATA_VAL);
482 static const struct ath_bus_ops ath9k_usb_bus_ops = {
483 .ath_bus_type = ATH_USB,
484 .read_cachesize = ath_usb_read_cachesize,
485 .eeprom_read = ath_usb_eeprom_read,
488 static void setup_ht_cap(struct ath9k_htc_priv *priv,
489 struct ieee80211_sta_ht_cap *ht_info)
491 struct ath_common *common = ath9k_hw_common(priv->ah);
492 u8 tx_streams, rx_streams;
495 ht_info->ht_supported = true;
496 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
497 IEEE80211_HT_CAP_SM_PS |
498 IEEE80211_HT_CAP_SGI_40 |
499 IEEE80211_HT_CAP_DSSSCCK40;
501 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
502 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
504 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
506 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
507 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
509 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
511 /* ath9k_htc supports only 1 or 2 stream devices */
512 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
513 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
515 ath_dbg(common, ATH_DBG_CONFIG,
516 "TX streams %d, RX streams: %d\n",
517 tx_streams, rx_streams);
519 if (tx_streams != rx_streams) {
520 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
521 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
522 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
525 for (i = 0; i < rx_streams; i++)
526 ht_info->mcs.rx_mask[i] = 0xff;
528 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
531 static int ath9k_init_queues(struct ath9k_htc_priv *priv)
533 struct ath_common *common = ath9k_hw_common(priv->ah);
536 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
537 priv->hwq_map[i] = -1;
539 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
540 if (priv->beaconq == -1) {
541 ath_err(common, "Unable to setup BEACON xmit queue\n");
545 priv->cabq = ath9k_htc_cabq_setup(priv);
546 if (priv->cabq == -1) {
547 ath_err(common, "Unable to setup CAB xmit queue\n");
551 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
552 ath_err(common, "Unable to setup xmit queue for BE traffic\n");
556 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
557 ath_err(common, "Unable to setup xmit queue for BK traffic\n");
560 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
561 ath_err(common, "Unable to setup xmit queue for VI traffic\n");
564 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
565 ath_err(common, "Unable to setup xmit queue for VO traffic\n");
575 static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
577 struct ath_common *common = ath9k_hw_common(priv->ah);
580 /* Get the hardware key cache size. */
581 common->keymax = AR_KEYTABLE_SIZE;
583 if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
584 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
587 * Reset the key cache since some parts do not
588 * reset the contents on initial power up.
590 for (i = 0; i < common->keymax; i++)
591 ath_hw_keyreset(common, (u16) i);
594 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
596 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
597 priv->sbands[IEEE80211_BAND_2GHZ].channels =
599 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
600 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
601 ARRAY_SIZE(ath9k_2ghz_channels);
602 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
603 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
604 ARRAY_SIZE(ath9k_legacy_rates);
607 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
608 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
609 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
610 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
611 ARRAY_SIZE(ath9k_5ghz_channels);
612 priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
613 ath9k_legacy_rates + 4;
614 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
615 ARRAY_SIZE(ath9k_legacy_rates) - 4;
619 static void ath9k_init_misc(struct ath9k_htc_priv *priv)
621 struct ath_common *common = ath9k_hw_common(priv->ah);
623 common->tx_chainmask = priv->ah->caps.tx_chainmask;
624 common->rx_chainmask = priv->ah->caps.rx_chainmask;
626 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
628 priv->ah->opmode = NL80211_IFTYPE_STATION;
631 static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
635 switch (priv->ah->btcoex_hw.scheme) {
636 case ATH_BTCOEX_CFG_NONE:
638 case ATH_BTCOEX_CFG_3WIRE:
639 priv->ah->btcoex_hw.btactive_gpio = 7;
640 priv->ah->btcoex_hw.btpriority_gpio = 6;
641 priv->ah->btcoex_hw.wlanactive_gpio = 8;
642 priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
643 ath9k_hw_btcoex_init_3wire(priv->ah);
644 ath_htc_init_btcoex_work(priv);
645 qnum = priv->hwq_map[WME_AC_BE];
646 ath9k_hw_init_btcoex_hw(priv->ah, qnum);
654 static int ath9k_init_priv(struct ath9k_htc_priv *priv,
655 u16 devid, char *product,
658 struct ath_hw *ah = NULL;
659 struct ath_common *common;
660 int i, ret = 0, csz = 0;
662 priv->op_flags |= OP_INVALID;
664 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
668 ah->hw_version.devid = devid;
669 ah->hw_version.subsysid = 0; /* FIXME */
670 ah->hw_version.usbdev = drv_info;
671 ah->ah_flags |= AH_USE_EEPROM;
672 ah->reg_ops.read = ath9k_regread;
673 ah->reg_ops.multi_read = ath9k_multi_regread;
674 ah->reg_ops.write = ath9k_regwrite;
675 ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
676 ah->reg_ops.write_flush = ath9k_regwrite_flush;
677 ah->reg_ops.rmw = ath9k_reg_rmw;
680 common = ath9k_hw_common(ah);
681 common->ops = &ah->reg_ops;
682 common->bus_ops = &ath9k_usb_bus_ops;
684 common->hw = priv->hw;
686 common->debug_mask = ath9k_debug;
688 spin_lock_init(&priv->beacon_lock);
689 spin_lock_init(&priv->tx.tx_lock);
690 mutex_init(&priv->mutex);
691 mutex_init(&priv->htc_pm_lock);
692 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
693 (unsigned long)priv);
694 tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
695 (unsigned long)priv);
696 INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
697 INIT_WORK(&priv->ps_work, ath9k_ps_work);
698 INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
699 setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
700 (unsigned long)priv);
703 * Cache line size is used to size and align various
704 * structures used to communicate with the hardware.
706 ath_read_cachesize(common, &csz);
707 common->cachelsz = csz << 2; /* convert to bytes */
709 ret = ath9k_hw_init(ah);
712 "Unable to initialize hardware; initialization status: %d\n",
717 ret = ath9k_init_queues(priv);
721 for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
722 priv->cur_beacon_conf.bslot[i] = NULL;
724 ath9k_init_crypto(priv);
725 ath9k_init_channels_rates(priv);
726 ath9k_init_misc(priv);
728 if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
729 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
730 ath9k_init_btcoex(priv);
745 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
746 struct ieee80211_hw *hw)
748 struct ath_common *common = ath9k_hw_common(priv->ah);
750 hw->flags = IEEE80211_HW_SIGNAL_DBM |
751 IEEE80211_HW_AMPDU_AGGREGATION |
752 IEEE80211_HW_SPECTRUM_MGMT |
753 IEEE80211_HW_HAS_RATE_CONTROL |
754 IEEE80211_HW_RX_INCLUDES_FCS |
755 IEEE80211_HW_SUPPORTS_PS |
756 IEEE80211_HW_PS_NULLFUNC_STACK |
757 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
758 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
760 hw->wiphy->interface_modes =
761 BIT(NL80211_IFTYPE_STATION) |
762 BIT(NL80211_IFTYPE_ADHOC) |
763 BIT(NL80211_IFTYPE_AP) |
764 BIT(NL80211_IFTYPE_P2P_GO) |
765 BIT(NL80211_IFTYPE_P2P_CLIENT);
767 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
770 hw->channel_change_time = 5000;
771 hw->max_listen_interval = 10;
773 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
774 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
776 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
777 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
778 sizeof(struct htc_frame_hdr) + 4;
780 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
781 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
782 &priv->sbands[IEEE80211_BAND_2GHZ];
783 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
784 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
785 &priv->sbands[IEEE80211_BAND_5GHZ];
787 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
788 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
790 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
791 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
793 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
796 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
799 static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
801 struct ieee80211_hw *hw = priv->hw;
802 struct wmi_fw_version cmd_rsp;
805 memset(&cmd_rsp, 0, sizeof(cmd_rsp));
807 WMI_CMD(WMI_GET_FW_VERSION);
811 priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
812 priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
814 snprintf(hw->wiphy->fw_version, ETHTOOL_BUSINFO_LEN, "%d.%d",
815 priv->fw_version_major,
816 priv->fw_version_minor);
818 dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
819 priv->fw_version_major,
820 priv->fw_version_minor);
823 * Check if the available FW matches the driver's
826 if (priv->fw_version_major != MAJOR_VERSION_REQ ||
827 priv->fw_version_minor != MINOR_VERSION_REQ) {
828 dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
829 MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
836 static int ath9k_init_device(struct ath9k_htc_priv *priv,
837 u16 devid, char *product, u32 drv_info)
839 struct ieee80211_hw *hw = priv->hw;
840 struct ath_common *common;
843 struct ath_regulatory *reg;
846 /* Bring up device */
847 error = ath9k_init_priv(priv, devid, product, drv_info);
852 common = ath9k_hw_common(ah);
853 ath9k_set_hw_capab(priv, hw);
855 error = ath9k_init_firmware_version(priv);
859 /* Initialize regulatory */
860 error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
865 reg = &common->regulatory;
868 error = ath9k_tx_init(priv);
873 error = ath9k_rx_init(priv);
877 #ifdef CONFIG_MAC80211_LEDS
878 /* must be initialized before ieee80211_register_hw */
879 priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
880 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
881 ARRAY_SIZE(ath9k_htc_tpt_blink));
884 /* Register with mac80211 */
885 error = ieee80211_register_hw(hw);
889 /* Handle world regulatory */
890 if (!ath_is_world_regd(reg)) {
891 error = regulatory_hint(hw->wiphy, reg->alpha2);
896 error = ath9k_htc_init_debug(priv->ah);
898 ath_err(common, "Unable to create debugfs files\n");
902 ath_dbg(common, ATH_DBG_CONFIG,
903 "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, "
904 "BE:%d, BK:%d, VI:%d, VO:%d\n",
915 ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
916 wiphy_info(hw->wiphy, "%s\n", hw_name);
918 ath9k_init_leds(priv);
919 ath9k_start_rfkill_poll(priv);
924 ieee80211_unregister_hw(hw);
926 ath9k_rx_cleanup(priv);
928 ath9k_tx_cleanup(priv);
934 ath9k_deinit_priv(priv);
939 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
940 u16 devid, char *product, u32 drv_info)
942 struct ieee80211_hw *hw;
943 struct ath9k_htc_priv *priv;
946 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
952 priv->htc = htc_handle;
954 htc_handle->drv_priv = priv;
955 SET_IEEE80211_DEV(hw, priv->dev);
957 ret = ath9k_htc_wait_for_target(priv);
961 priv->wmi = ath9k_init_wmi(priv);
967 ret = ath9k_init_htc_services(priv, devid, drv_info);
971 ret = ath9k_init_device(priv, devid, product, drv_info);
978 ath9k_deinit_wmi(priv);
980 ieee80211_free_hw(hw);
984 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
986 if (htc_handle->drv_priv) {
988 /* Check if the device has been yanked out. */
990 htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
992 ath9k_deinit_device(htc_handle->drv_priv);
993 ath9k_deinit_wmi(htc_handle->drv_priv);
994 ieee80211_free_hw(htc_handle->drv_priv->hw);
1000 void ath9k_htc_suspend(struct htc_target *htc_handle)
1002 ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
1005 int ath9k_htc_resume(struct htc_target *htc_handle)
1007 struct ath9k_htc_priv *priv = htc_handle->drv_priv;
1010 ret = ath9k_htc_wait_for_target(priv);
1014 ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
1015 priv->ah->hw_version.usbdev);
1020 static int __init ath9k_htc_init(void)
1022 if (ath9k_hif_usb_init() < 0) {
1024 "ath9k_htc: No USB devices found,"
1025 " driver not installed.\n");
1031 module_init(ath9k_htc_init);
1033 static void __exit ath9k_htc_exit(void)
1035 ath9k_hif_usb_exit();
1036 printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
1038 module_exit(ath9k_htc_exit);