2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/time.h>
21 #include <linux/bitops.h>
22 #include <linux/etherdevice.h>
23 #include <linux/gpio.h>
24 #include <asm/unaligned.h>
28 #include "ar9003_mac.h"
29 #include "ar9003_mci.h"
30 #include "ar9003_phy.h"
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
42 struct ath_common *common = ath9k_hw_common(ah);
43 struct ath9k_channel *chan = ah->curchan;
44 unsigned int clockrate;
46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
49 else if (!chan) /* should really check for CCK instead */
50 clockrate = ATH9K_CLOCK_RATE_CCK;
51 else if (IS_CHAN_2GHZ(chan))
52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
59 if (IS_CHAN_HT40(chan))
61 if (IS_CHAN_HALF_RATE(chan))
63 if (IS_CHAN_QUARTER_RATE(chan))
67 common->clockrate = clockrate;
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
72 struct ath_common *common = ath9k_hw_common(ah);
74 return usecs * common->clockrate;
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
81 BUG_ON(timeout < AH_TIME_QUANTUM);
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
84 if ((REG_READ(ah, reg) & mask) == val)
87 udelay(AH_TIME_QUANTUM);
90 ath_dbg(ath9k_hw_common(ah), ANY,
91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
96 EXPORT_SYMBOL(ath9k_hw_wait);
98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
103 if (IS_CHAN_HALF_RATE(chan))
105 else if (IS_CHAN_QUARTER_RATE(chan))
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
112 int column, unsigned int *writecnt)
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
122 REGWRITE_BUFFER_FLUSH(ah);
125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
127 u32 *tmp_reg_list, *tmp_data;
130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
155 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
167 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
169 u32 frameLen, u16 rateix,
172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
178 case WLAN_RC_PHY_CCK:
179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
185 case WLAN_RC_PHY_OFDM:
186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_QUARTER
191 + OFDM_PREAMBLE_TIME_QUARTER
192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
196 numBits = OFDM_PLCP_BITS + (frameLen << 3);
197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
198 txTime = OFDM_SIFS_TIME_HALF +
199 OFDM_PREAMBLE_TIME_HALF
200 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
203 numBits = OFDM_PLCP_BITS + (frameLen << 3);
204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
206 + (numSymbols * OFDM_SYMBOL_TIME);
210 ath_err(ath9k_hw_common(ah),
211 "Unknown phy %u (rate ix %u)\n", phy, rateix);
218 EXPORT_SYMBOL(ath9k_hw_computetxtime);
220 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
221 struct ath9k_channel *chan,
222 struct chan_centers *centers)
226 if (!IS_CHAN_HT40(chan)) {
227 centers->ctl_center = centers->ext_center =
228 centers->synth_center = chan->channel;
232 if (IS_CHAN_HT40PLUS(chan)) {
233 centers->synth_center =
234 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
237 centers->synth_center =
238 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
242 centers->ctl_center =
243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
244 /* 25 MHz spacing is supported by hw but not on upper layers */
245 centers->ext_center =
246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
253 static void ath9k_hw_read_revisions(struct ath_hw *ah)
257 if (ah->get_mac_revision)
258 ah->hw_version.macRev = ah->get_mac_revision();
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (!ah->get_mac_revision) {
267 val = REG_READ(ah, AR_SREV);
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
271 case AR9300_DEVID_AR9340:
272 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
274 case AR9300_DEVID_QCA955X:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
277 case AR9300_DEVID_AR953X:
278 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
280 case AR9300_DEVID_QCA956X:
281 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
288 val = REG_READ(ah, AR_SREV);
289 ah->hw_version.macVersion =
290 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
294 ah->is_pciexpress = true;
296 ah->is_pciexpress = (val &
297 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
299 if (!AR_SREV_9100(ah))
300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
302 ah->hw_version.macRev = val & AR_SREV_REVISION;
304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
305 ah->is_pciexpress = true;
309 /************************************/
310 /* HW Attach, Detach, Init Routines */
311 /************************************/
313 static void ath9k_hw_disablepcie(struct ath_hw *ah)
315 if (!AR_SREV_5416(ah))
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
331 /* This should work for all families including legacy */
332 static bool ath9k_hw_chip_test(struct ath_hw *ah)
334 struct ath_common *common = ath9k_hw_common(ah);
335 u32 regAddr[2] = { AR_STA_ID0 };
337 static const u32 patternData[4] = {
338 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
342 if (!AR_SREV_9300_20_OR_LATER(ah)) {
344 regAddr[1] = AR_PHY_BASE + (8 << 2);
348 for (i = 0; i < loop_max; i++) {
349 u32 addr = regAddr[i];
352 regHold[i] = REG_READ(ah, addr);
353 for (j = 0; j < 0x100; j++) {
354 wrData = (j << 16) | j;
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (rdData != wrData) {
359 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
360 addr, wrData, rdData);
364 for (j = 0; j < 4; j++) {
365 wrData = patternData[j];
366 REG_WRITE(ah, addr, wrData);
367 rdData = REG_READ(ah, addr);
368 if (wrData != rdData) {
370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 addr, wrData, rdData);
375 REG_WRITE(ah, regAddr[i], regHold[i]);
382 static void ath9k_hw_init_config(struct ath_hw *ah)
384 struct ath_common *common = ath9k_hw_common(ah);
386 ah->config.dma_beacon_response_time = 1;
387 ah->config.sw_beacon_response_time = 6;
388 ah->config.cwm_ignore_extcca = 0;
389 ah->config.analog_shiftreg = 1;
391 ah->config.rx_intr_mitigation = true;
393 if (AR_SREV_9300_20_OR_LATER(ah)) {
394 ah->config.rimt_last = 500;
395 ah->config.rimt_first = 2000;
397 ah->config.rimt_last = 250;
398 ah->config.rimt_first = 700;
401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
402 ah->config.pll_pwrsave = 7;
405 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
406 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
407 * This means we use it for all AR5416 devices, and the few
408 * minor PCI AR9280 devices out there.
410 * Serialization is required because these devices do not handle
411 * well the case of two concurrent reads/writes due to the latency
412 * involved. During one read/write another read/write can be issued
413 * on another CPU while the previous read/write may still be working
414 * on our hardware, if we hit this case the hardware poops in a loop.
415 * We prevent this by serializing reads and writes.
417 * This issue is not present on PCI-Express devices or pre-AR5416
418 * devices (legacy, 802.11abg).
420 if (num_possible_cpus() > 1)
421 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
426 !ah->is_pciexpress)) {
427 ah->config.serialize_regmode = SER_REG_MODE_ON;
429 ah->config.serialize_regmode = SER_REG_MODE_OFF;
433 ath_dbg(common, RESET, "serialize_regmode is %d\n",
434 ah->config.serialize_regmode);
436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
442 static void ath9k_hw_init_defaults(struct ath_hw *ah)
444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
446 regulatory->country_code = CTRY_DEFAULT;
447 regulatory->power_limit = MAX_RATE_POWER;
449 ah->hw_version.magic = AR5416_MAGIC;
450 ah->hw_version.subvendorid = 0;
452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
453 AR_STA_ID1_MCAST_KSRCH;
454 if (AR_SREV_9100(ah))
455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
457 ah->slottime = ATH9K_SLOT_TIME_9;
458 ah->globaltxtimeout = (u32) -1;
459 ah->power_mode = ATH9K_PM_UNDEFINED;
460 ah->htc_reset_init = true;
462 ah->tpc_enabled = false;
464 ah->ani_function = ATH9K_ANI_ALL;
465 if (!AR_SREV_9300_20_OR_LATER(ah))
466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
474 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
476 struct ath_common *common = ath9k_hw_common(ah);
480 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
483 for (i = 0; i < 3; i++) {
484 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
486 common->macaddr[2 * i] = eeval >> 8;
487 common->macaddr[2 * i + 1] = eeval & 0xff;
489 if (!is_valid_ether_addr(common->macaddr)) {
491 "eeprom contains invalid mac address: %pM\n",
494 random_ether_addr(common->macaddr);
496 "random mac address will be used: %pM\n",
503 static int ath9k_hw_post_init(struct ath_hw *ah)
505 struct ath_common *common = ath9k_hw_common(ah);
508 if (common->bus_ops->ath_bus_type != ATH_USB) {
509 if (!ath9k_hw_chip_test(ah))
513 if (!AR_SREV_9300_20_OR_LATER(ah)) {
514 ecode = ar9002_hw_rf_claim(ah);
519 ecode = ath9k_hw_eeprom_init(ah);
523 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
524 ah->eep_ops->get_eeprom_ver(ah),
525 ah->eep_ops->get_eeprom_rev(ah));
527 ath9k_hw_ani_init(ah);
530 * EEPROM needs to be initialized before we do this.
531 * This is required for regulatory compliance.
533 if (AR_SREV_9300_20_OR_LATER(ah)) {
534 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
535 if ((regdmn & 0xF0) == CTL_FCC) {
536 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
537 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
544 static int ath9k_hw_attach_ops(struct ath_hw *ah)
546 if (!AR_SREV_9300_20_OR_LATER(ah))
547 return ar9002_hw_attach_ops(ah);
549 ar9003_hw_attach_ops(ah);
553 /* Called for all hardware families */
554 static int __ath9k_hw_init(struct ath_hw *ah)
556 struct ath_common *common = ath9k_hw_common(ah);
559 ath9k_hw_read_revisions(ah);
561 switch (ah->hw_version.macVersion) {
562 case AR_SREV_VERSION_5416_PCI:
563 case AR_SREV_VERSION_5416_PCIE:
564 case AR_SREV_VERSION_9160:
565 case AR_SREV_VERSION_9100:
566 case AR_SREV_VERSION_9280:
567 case AR_SREV_VERSION_9285:
568 case AR_SREV_VERSION_9287:
569 case AR_SREV_VERSION_9271:
570 case AR_SREV_VERSION_9300:
571 case AR_SREV_VERSION_9330:
572 case AR_SREV_VERSION_9485:
573 case AR_SREV_VERSION_9340:
574 case AR_SREV_VERSION_9462:
575 case AR_SREV_VERSION_9550:
576 case AR_SREV_VERSION_9565:
577 case AR_SREV_VERSION_9531:
578 case AR_SREV_VERSION_9561:
582 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
583 ah->hw_version.macVersion, ah->hw_version.macRev);
588 * Read back AR_WA into a permanent copy and set bits 14 and 17.
589 * We need to do this to avoid RMW of this register. We cannot
590 * read the reg when chip is asleep.
592 if (AR_SREV_9300_20_OR_LATER(ah)) {
593 ah->WARegVal = REG_READ(ah, AR_WA);
594 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
595 AR_WA_ASPM_TIMER_BASED_DISABLE);
598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
599 ath_err(common, "Couldn't reset chip\n");
603 if (AR_SREV_9565(ah)) {
604 ah->WARegVal |= AR_WA_BIT22;
605 REG_WRITE(ah, AR_WA, ah->WARegVal);
608 ath9k_hw_init_defaults(ah);
609 ath9k_hw_init_config(ah);
611 r = ath9k_hw_attach_ops(ah);
615 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
616 ath_err(common, "Couldn't wakeup chip\n");
620 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
621 AR_SREV_9330(ah) || AR_SREV_9550(ah))
622 ah->is_pciexpress = false;
624 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
625 ath9k_hw_init_cal_settings(ah);
627 if (!ah->is_pciexpress)
628 ath9k_hw_disablepcie(ah);
630 r = ath9k_hw_post_init(ah);
634 ath9k_hw_init_mode_gain_regs(ah);
635 r = ath9k_hw_fill_cap_info(ah);
639 r = ath9k_hw_init_macaddr(ah);
641 ath_err(common, "Failed to initialize MAC address\n");
645 ath9k_hw_init_hang_checks(ah);
647 common->state = ATH_HW_INITIALIZED;
652 int ath9k_hw_init(struct ath_hw *ah)
655 struct ath_common *common = ath9k_hw_common(ah);
657 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
658 switch (ah->hw_version.devid) {
659 case AR5416_DEVID_PCI:
660 case AR5416_DEVID_PCIE:
661 case AR5416_AR9100_DEVID:
662 case AR9160_DEVID_PCI:
663 case AR9280_DEVID_PCI:
664 case AR9280_DEVID_PCIE:
665 case AR9285_DEVID_PCIE:
666 case AR9287_DEVID_PCI:
667 case AR9287_DEVID_PCIE:
668 case AR2427_DEVID_PCIE:
669 case AR9300_DEVID_PCIE:
670 case AR9300_DEVID_AR9485_PCIE:
671 case AR9300_DEVID_AR9330:
672 case AR9300_DEVID_AR9340:
673 case AR9300_DEVID_QCA955X:
674 case AR9300_DEVID_AR9580:
675 case AR9300_DEVID_AR9462:
676 case AR9485_DEVID_AR1111:
677 case AR9300_DEVID_AR9565:
678 case AR9300_DEVID_AR953X:
679 case AR9300_DEVID_QCA956X:
682 if (common->bus_ops->ath_bus_type == ATH_USB)
684 ath_err(common, "Hardware device ID 0x%04x not supported\n",
685 ah->hw_version.devid);
689 ret = __ath9k_hw_init(ah);
692 "Unable to initialize hardware; initialization status: %d\n",
701 EXPORT_SYMBOL(ath9k_hw_init);
703 static void ath9k_hw_init_qos(struct ath_hw *ah)
705 ENABLE_REGWRITE_BUFFER(ah);
707 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
708 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
710 REG_WRITE(ah, AR_QOS_NO_ACK,
711 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
712 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
713 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
715 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
716 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
718 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
719 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
721 REGWRITE_BUFFER_FLUSH(ah);
724 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
726 struct ath_common *common = ath9k_hw_common(ah);
729 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
731 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
733 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
737 if (WARN_ON_ONCE(i >= 100)) {
738 ath_err(common, "PLL4 meaurement not done\n");
745 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
747 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
749 static void ath9k_hw_init_pll(struct ath_hw *ah,
750 struct ath9k_channel *chan)
754 pll = ath9k_hw_compute_pll_control(ah, chan);
756 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
757 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
761 AR_CH0_DPLL2_KD, 0x40);
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
763 AR_CH0_DPLL2_KI, 0x4);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
766 AR_CH0_BB_DPLL1_REFDIV, 0x5);
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
768 AR_CH0_BB_DPLL1_NINI, 0x58);
769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
770 AR_CH0_BB_DPLL1_NFRAC, 0x0);
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
775 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
777 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
779 /* program BB PLL phase_shift to 0x6 */
780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
781 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
784 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
786 } else if (AR_SREV_9330(ah)) {
787 u32 ddr_dpll2, pll_control2, kd;
789 if (ah->is_clk_25mhz) {
790 ddr_dpll2 = 0x18e82f01;
791 pll_control2 = 0xe04a3d;
794 ddr_dpll2 = 0x19e82f01;
795 pll_control2 = 0x886666;
799 /* program DDR PLL ki and kd value */
800 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
802 /* program DDR PLL phase_shift */
803 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
804 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
806 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
807 pll | AR_RTC_9300_PLL_BYPASS);
810 /* program refdiv, nint, frac to RTC register */
811 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
813 /* program BB PLL kd and ki value */
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
817 /* program BB PLL phase_shift */
818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
819 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
820 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
822 u32 regval, pll2_divint, pll2_divfrac, refdiv;
824 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
825 pll | AR_RTC_9300_SOC_PLL_BYPASS);
828 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
831 if (ah->is_clk_25mhz) {
832 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
834 pll2_divfrac = 0xa3d2;
838 pll2_divfrac = 0x1eb85;
842 if (AR_SREV_9340(ah)) {
848 pll2_divfrac = (AR_SREV_9531(ah) ||
855 regval = REG_READ(ah, AR_PHY_PLL_MODE);
856 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
857 regval |= (0x1 << 22);
859 regval |= (0x1 << 16);
860 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
863 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
864 (pll2_divint << 18) | pll2_divfrac);
867 regval = REG_READ(ah, AR_PHY_PLL_MODE);
868 if (AR_SREV_9340(ah))
869 regval = (regval & 0x80071fff) |
874 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
875 regval = (regval & 0x01c00fff) |
881 if (AR_SREV_9531(ah))
882 regval |= (0x6 << 12);
884 regval = (regval & 0x80071fff) |
889 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
891 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
892 REG_WRITE(ah, AR_PHY_PLL_MODE,
893 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
895 REG_WRITE(ah, AR_PHY_PLL_MODE,
896 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
901 if (AR_SREV_9565(ah))
903 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
905 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
909 /* Switch the core clock for ar9271 to 117Mhz */
910 if (AR_SREV_9271(ah)) {
912 REG_WRITE(ah, 0x50040, 0x304);
915 udelay(RTC_PLL_SETTLE_DELAY);
917 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
920 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
921 enum nl80211_iftype opmode)
923 u32 sync_default = AR_INTR_SYNC_DEFAULT;
924 u32 imr_reg = AR_IMR_TXERR |
930 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
932 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
934 if (AR_SREV_9300_20_OR_LATER(ah)) {
935 imr_reg |= AR_IMR_RXOK_HP;
936 if (ah->config.rx_intr_mitigation)
937 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
939 imr_reg |= AR_IMR_RXOK_LP;
942 if (ah->config.rx_intr_mitigation)
943 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
945 imr_reg |= AR_IMR_RXOK;
948 if (ah->config.tx_intr_mitigation)
949 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
951 imr_reg |= AR_IMR_TXOK;
953 ENABLE_REGWRITE_BUFFER(ah);
955 REG_WRITE(ah, AR_IMR, imr_reg);
956 ah->imrs2_reg |= AR_IMR_S2_GTT;
957 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
959 if (!AR_SREV_9100(ah)) {
960 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
961 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
962 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
965 REGWRITE_BUFFER_FLUSH(ah);
967 if (AR_SREV_9300_20_OR_LATER(ah)) {
968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
969 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
971 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
975 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
977 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
978 val = min(val, (u32) 0xFFFF);
979 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
982 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
984 u32 val = ath9k_hw_mac_to_clks(ah, us);
985 val = min(val, (u32) 0xFFFF);
986 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
989 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
991 u32 val = ath9k_hw_mac_to_clks(ah, us);
992 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
993 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
996 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
998 u32 val = ath9k_hw_mac_to_clks(ah, us);
999 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1000 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1003 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1006 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1008 ah->globaltxtimeout = (u32) -1;
1011 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1012 ah->globaltxtimeout = tu;
1017 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1019 struct ath_common *common = ath9k_hw_common(ah);
1020 const struct ath9k_channel *chan = ah->curchan;
1021 int acktimeout, ctstimeout, ack_offset = 0;
1024 int rx_lat = 0, tx_lat = 0, eifs = 0;
1027 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1033 if (ah->misc_mode != 0)
1034 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1036 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1042 if (IS_CHAN_5GHZ(chan))
1047 if (IS_CHAN_HALF_RATE(chan)) {
1051 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1057 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1059 rx_lat = (rx_lat * 4) - 1;
1061 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1068 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1069 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1070 reg = AR_USEC_ASYNC_FIFO;
1072 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1074 reg = REG_READ(ah, AR_USEC);
1076 rx_lat = MS(reg, AR_USEC_RX_LAT);
1077 tx_lat = MS(reg, AR_USEC_TX_LAT);
1079 slottime = ah->slottime;
1082 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1083 slottime += 3 * ah->coverage_class;
1084 acktimeout = slottime + sifstime + ack_offset;
1085 ctstimeout = acktimeout;
1088 * Workaround for early ACK timeouts, add an offset to match the
1089 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1090 * This was initially only meant to work around an issue with delayed
1091 * BA frames in some implementations, but it has been found to fix ACK
1092 * timeout issues in other cases as well.
1094 if (IS_CHAN_2GHZ(chan) &&
1095 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1096 acktimeout += 64 - sifstime - ah->slottime;
1097 ctstimeout += 48 - sifstime - ah->slottime;
1100 if (ah->dynack.enabled) {
1101 acktimeout = ah->dynack.ackto;
1102 ctstimeout = acktimeout;
1103 slottime = (acktimeout - 3) / 2;
1105 ah->dynack.ackto = acktimeout;
1108 ath9k_hw_set_sifs_time(ah, sifstime);
1109 ath9k_hw_setslottime(ah, slottime);
1110 ath9k_hw_set_ack_timeout(ah, acktimeout);
1111 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1112 if (ah->globaltxtimeout != (u32) -1)
1113 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1115 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1116 REG_RMW(ah, AR_USEC,
1117 (common->clockrate - 1) |
1118 SM(rx_lat, AR_USEC_RX_LAT) |
1119 SM(tx_lat, AR_USEC_TX_LAT),
1120 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1123 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1125 void ath9k_hw_deinit(struct ath_hw *ah)
1127 struct ath_common *common = ath9k_hw_common(ah);
1129 if (common->state < ATH_HW_INITIALIZED)
1132 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1134 EXPORT_SYMBOL(ath9k_hw_deinit);
1140 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1142 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1144 if (IS_CHAN_2GHZ(chan))
1152 /****************************************/
1153 /* Reset and Channel Switching Routines */
1154 /****************************************/
1156 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1158 struct ath_common *common = ath9k_hw_common(ah);
1161 ENABLE_REGWRITE_BUFFER(ah);
1164 * set AHB_MODE not to do cacheline prefetches
1166 if (!AR_SREV_9300_20_OR_LATER(ah))
1167 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1170 * let mac dma reads be in 128 byte chunks
1172 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1174 REGWRITE_BUFFER_FLUSH(ah);
1177 * Restore TX Trigger Level to its pre-reset value.
1178 * The initial value depends on whether aggregation is enabled, and is
1179 * adjusted whenever underruns are detected.
1181 if (!AR_SREV_9300_20_OR_LATER(ah))
1182 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1184 ENABLE_REGWRITE_BUFFER(ah);
1187 * let mac dma writes be in 128 byte chunks
1189 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1192 * Setup receive FIFO threshold to hold off TX activities
1194 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1196 if (AR_SREV_9300_20_OR_LATER(ah)) {
1197 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1198 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1200 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1201 ah->caps.rx_status_len);
1205 * reduce the number of usable entries in PCU TXBUF to avoid
1206 * wrap around issues.
1208 if (AR_SREV_9285(ah)) {
1209 /* For AR9285 the number of Fifos are reduced to half.
1210 * So set the usable tx buf size also to half to
1211 * avoid data/delimiter underruns
1213 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1214 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1215 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1216 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1218 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1221 if (!AR_SREV_9271(ah))
1222 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1224 REGWRITE_BUFFER_FLUSH(ah);
1226 if (AR_SREV_9300_20_OR_LATER(ah))
1227 ath9k_hw_reset_txstatus_ring(ah);
1230 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1232 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1233 u32 set = AR_STA_ID1_KSRCH_MODE;
1235 ENABLE_REG_RMW_BUFFER(ah);
1237 case NL80211_IFTYPE_ADHOC:
1238 if (!AR_SREV_9340_13(ah)) {
1239 set |= AR_STA_ID1_ADHOC;
1240 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1244 case NL80211_IFTYPE_OCB:
1245 case NL80211_IFTYPE_MESH_POINT:
1246 case NL80211_IFTYPE_AP:
1247 set |= AR_STA_ID1_STA_AP;
1249 case NL80211_IFTYPE_STATION:
1250 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1253 if (!ah->is_monitoring)
1257 REG_RMW(ah, AR_STA_ID1, set, mask);
1258 REG_RMW_BUFFER_FLUSH(ah);
1261 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1262 u32 *coef_mantissa, u32 *coef_exponent)
1264 u32 coef_exp, coef_man;
1266 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1267 if ((coef_scaled >> coef_exp) & 0x1)
1270 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1272 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1274 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1275 *coef_exponent = coef_exp - 16;
1279 * call external reset function to reset WMAC if:
1280 * - doing a cold reset
1281 * - we have pending frames in the TX queues.
1283 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1287 for (i = 0; i < AR_NUM_QCU; i++) {
1288 npend = ath9k_hw_numtxpending(ah, i);
1293 if (ah->external_reset &&
1294 (npend || type == ATH9K_RESET_COLD)) {
1297 ath_dbg(ath9k_hw_common(ah), RESET,
1298 "reset MAC via external reset\n");
1300 reset_err = ah->external_reset();
1302 ath_err(ath9k_hw_common(ah),
1303 "External reset failed, err=%d\n",
1308 REG_WRITE(ah, AR_RTC_RESET, 1);
1314 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1319 if (AR_SREV_9100(ah)) {
1320 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1321 AR_RTC_DERIVED_CLK_PERIOD, 1);
1322 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1325 ENABLE_REGWRITE_BUFFER(ah);
1327 if (AR_SREV_9300_20_OR_LATER(ah)) {
1328 REG_WRITE(ah, AR_WA, ah->WARegVal);
1332 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1333 AR_RTC_FORCE_WAKE_ON_INT);
1335 if (AR_SREV_9100(ah)) {
1336 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1337 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1339 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1340 if (AR_SREV_9340(ah))
1341 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1343 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1344 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1348 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1351 if (!AR_SREV_9300_20_OR_LATER(ah))
1353 REG_WRITE(ah, AR_RC, val);
1355 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1356 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1358 rst_flags = AR_RTC_RC_MAC_WARM;
1359 if (type == ATH9K_RESET_COLD)
1360 rst_flags |= AR_RTC_RC_MAC_COLD;
1363 if (AR_SREV_9330(ah)) {
1364 if (!ath9k_hw_ar9330_reset_war(ah, type))
1368 if (ath9k_hw_mci_is_enabled(ah))
1369 ar9003_mci_check_gpm_offset(ah);
1371 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1373 REGWRITE_BUFFER_FLUSH(ah);
1375 if (AR_SREV_9300_20_OR_LATER(ah))
1377 else if (AR_SREV_9100(ah))
1382 REG_WRITE(ah, AR_RTC_RC, 0);
1383 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1384 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1388 if (!AR_SREV_9100(ah))
1389 REG_WRITE(ah, AR_RC, 0);
1391 if (AR_SREV_9100(ah))
1397 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1399 ENABLE_REGWRITE_BUFFER(ah);
1401 if (AR_SREV_9300_20_OR_LATER(ah)) {
1402 REG_WRITE(ah, AR_WA, ah->WARegVal);
1406 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1407 AR_RTC_FORCE_WAKE_ON_INT);
1409 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1410 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1412 REG_WRITE(ah, AR_RTC_RESET, 0);
1414 REGWRITE_BUFFER_FLUSH(ah);
1418 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1419 REG_WRITE(ah, AR_RC, 0);
1421 REG_WRITE(ah, AR_RTC_RESET, 1);
1423 if (!ath9k_hw_wait(ah,
1428 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1432 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1435 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1439 if (AR_SREV_9300_20_OR_LATER(ah)) {
1440 REG_WRITE(ah, AR_WA, ah->WARegVal);
1444 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1445 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1447 if (!ah->reset_power_on)
1448 type = ATH9K_RESET_POWER_ON;
1451 case ATH9K_RESET_POWER_ON:
1452 ret = ath9k_hw_set_reset_power_on(ah);
1454 ah->reset_power_on = true;
1456 case ATH9K_RESET_WARM:
1457 case ATH9K_RESET_COLD:
1458 ret = ath9k_hw_set_reset(ah, type);
1467 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1468 struct ath9k_channel *chan)
1470 int reset_type = ATH9K_RESET_WARM;
1472 if (AR_SREV_9280(ah)) {
1473 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1474 reset_type = ATH9K_RESET_POWER_ON;
1476 reset_type = ATH9K_RESET_COLD;
1477 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1478 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1479 reset_type = ATH9K_RESET_COLD;
1481 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1484 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1487 ah->chip_fullsleep = false;
1489 if (AR_SREV_9330(ah))
1490 ar9003_hw_internal_regulator_apply(ah);
1491 ath9k_hw_init_pll(ah, chan);
1496 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1497 struct ath9k_channel *chan)
1499 struct ath_common *common = ath9k_hw_common(ah);
1500 struct ath9k_hw_capabilities *pCap = &ah->caps;
1501 bool band_switch = false, mode_diff = false;
1502 u8 ini_reloaded = 0;
1506 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1507 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1508 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1509 mode_diff = !!(flags_diff & ~CHANNEL_HT);
1512 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1513 if (ath9k_hw_numtxpending(ah, qnum)) {
1514 ath_dbg(common, QUEUE,
1515 "Transmit frames pending on queue %d\n", qnum);
1520 if (!ath9k_hw_rfbus_req(ah)) {
1521 ath_err(common, "Could not kill baseband RX\n");
1525 if (band_switch || mode_diff) {
1526 ath9k_hw_mark_phy_inactive(ah);
1530 ath9k_hw_init_pll(ah, chan);
1532 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1533 ath_err(common, "Failed to do fast channel change\n");
1538 ath9k_hw_set_channel_regs(ah, chan);
1540 r = ath9k_hw_rf_set_freq(ah, chan);
1542 ath_err(common, "Failed to set channel\n");
1545 ath9k_hw_set_clockrate(ah);
1546 ath9k_hw_apply_txpower(ah, chan, false);
1548 ath9k_hw_set_delta_slope(ah, chan);
1549 ath9k_hw_spur_mitigate_freq(ah, chan);
1551 if (band_switch || ini_reloaded)
1552 ah->eep_ops->set_board_values(ah, chan);
1554 ath9k_hw_init_bb(ah, chan);
1555 ath9k_hw_rfbus_done(ah);
1557 if (band_switch || ini_reloaded) {
1558 ah->ah_flags |= AH_FASTCC;
1559 ath9k_hw_init_cal(ah, chan);
1560 ah->ah_flags &= ~AH_FASTCC;
1566 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1568 u32 gpio_mask = ah->gpio_mask;
1571 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1572 if (!(gpio_mask & 1))
1575 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1576 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1580 void ath9k_hw_check_nav(struct ath_hw *ah)
1582 struct ath_common *common = ath9k_hw_common(ah);
1585 val = REG_READ(ah, AR_NAV);
1586 if (val != 0xdeadbeef && val > 0x7fff) {
1587 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1588 REG_WRITE(ah, AR_NAV, 0);
1591 EXPORT_SYMBOL(ath9k_hw_check_nav);
1593 bool ath9k_hw_check_alive(struct ath_hw *ah)
1598 if (AR_SREV_9300(ah))
1599 return !ath9k_hw_detect_mac_hang(ah);
1601 if (AR_SREV_9285_12_OR_LATER(ah))
1604 last_val = REG_READ(ah, AR_OBS_BUS_1);
1606 reg = REG_READ(ah, AR_OBS_BUS_1);
1607 if (reg != last_val)
1612 if ((reg & 0x7E7FFFEF) == 0x00702400)
1615 switch (reg & 0x7E000B00) {
1623 } while (count-- > 0);
1627 EXPORT_SYMBOL(ath9k_hw_check_alive);
1629 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1631 /* Setup MFP options for CCMP */
1632 if (AR_SREV_9280_20_OR_LATER(ah)) {
1633 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1634 * frames when constructing CCMP AAD. */
1635 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1637 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1638 ah->sw_mgmt_crypto_tx = true;
1640 ah->sw_mgmt_crypto_tx = false;
1641 ah->sw_mgmt_crypto_rx = false;
1642 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1643 /* Disable hardware crypto for management frames */
1644 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1645 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1646 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1647 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1648 ah->sw_mgmt_crypto_tx = true;
1649 ah->sw_mgmt_crypto_rx = true;
1651 ah->sw_mgmt_crypto_tx = true;
1652 ah->sw_mgmt_crypto_rx = true;
1656 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1657 u32 macStaId1, u32 saveDefAntenna)
1659 struct ath_common *common = ath9k_hw_common(ah);
1661 ENABLE_REGWRITE_BUFFER(ah);
1663 REG_RMW(ah, AR_STA_ID1, macStaId1
1664 | AR_STA_ID1_RTS_USE_DEF
1665 | ah->sta_id1_defaults,
1666 ~AR_STA_ID1_SADH_MASK);
1667 ath_hw_setbssidmask(common);
1668 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1669 ath9k_hw_write_associd(ah);
1670 REG_WRITE(ah, AR_ISR, ~0);
1671 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1673 REGWRITE_BUFFER_FLUSH(ah);
1675 ath9k_hw_set_operating_mode(ah, ah->opmode);
1678 static void ath9k_hw_init_queues(struct ath_hw *ah)
1682 ENABLE_REGWRITE_BUFFER(ah);
1684 for (i = 0; i < AR_NUM_DCU; i++)
1685 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1687 REGWRITE_BUFFER_FLUSH(ah);
1690 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1691 ath9k_hw_resettxqueue(ah, i);
1695 * For big endian systems turn on swapping for descriptors
1697 static void ath9k_hw_init_desc(struct ath_hw *ah)
1699 struct ath_common *common = ath9k_hw_common(ah);
1701 if (AR_SREV_9100(ah)) {
1703 mask = REG_READ(ah, AR_CFG);
1704 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1705 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1708 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1709 REG_WRITE(ah, AR_CFG, mask);
1710 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1711 REG_READ(ah, AR_CFG));
1714 if (common->bus_ops->ath_bus_type == ATH_USB) {
1715 /* Configure AR9271 target WLAN */
1716 if (AR_SREV_9271(ah))
1717 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1719 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1722 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1723 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1725 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1727 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1733 * Fast channel change:
1734 * (Change synthesizer based on channel freq without resetting chip)
1736 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1738 struct ath_common *common = ath9k_hw_common(ah);
1739 struct ath9k_hw_capabilities *pCap = &ah->caps;
1742 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1745 if (ah->chip_fullsleep)
1751 if (chan->channel == ah->curchan->channel)
1754 if ((ah->curchan->channelFlags | chan->channelFlags) &
1755 (CHANNEL_HALF | CHANNEL_QUARTER))
1759 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1761 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1762 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1765 if (!ath9k_hw_check_alive(ah))
1769 * For AR9462, make sure that calibration data for
1770 * re-using are present.
1772 if (AR_SREV_9462(ah) && (ah->caldata &&
1773 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1774 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1775 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1778 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1779 ah->curchan->channel, chan->channel);
1781 ret = ath9k_hw_channel_change(ah, chan);
1785 if (ath9k_hw_mci_is_enabled(ah))
1786 ar9003_mci_2g5g_switch(ah, false);
1788 ath9k_hw_loadnf(ah, ah->curchan);
1789 ath9k_hw_start_nfcal(ah, true);
1791 if (AR_SREV_9271(ah))
1792 ar9002_hw_load_ani_reg(ah, chan);
1799 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1805 getrawmonotonic(&ts);
1809 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1810 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1814 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1816 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1817 struct ath9k_hw_cal_data *caldata, bool fastcc)
1819 struct ath_common *common = ath9k_hw_common(ah);
1826 bool start_mci_reset = false;
1827 bool save_fullsleep = ah->chip_fullsleep;
1829 if (ath9k_hw_mci_is_enabled(ah)) {
1830 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1831 if (start_mci_reset)
1835 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1838 if (ah->curchan && !ah->chip_fullsleep)
1839 ath9k_hw_getnf(ah, ah->curchan);
1841 ah->caldata = caldata;
1842 if (caldata && (chan->channel != caldata->channel ||
1843 chan->channelFlags != caldata->channelFlags)) {
1844 /* Operating channel changed, reset channel calibration data */
1845 memset(caldata, 0, sizeof(*caldata));
1846 ath9k_init_nfcal_hist_buffer(ah, chan);
1847 } else if (caldata) {
1848 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1850 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1853 r = ath9k_hw_do_fastcc(ah, chan);
1858 if (ath9k_hw_mci_is_enabled(ah))
1859 ar9003_mci_stop_bt(ah, save_fullsleep);
1861 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1862 if (saveDefAntenna == 0)
1865 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1867 /* Save TSF before chip reset, a cold reset clears it */
1868 tsf = ath9k_hw_gettsf64(ah);
1869 usec = ktime_to_us(ktime_get_raw());
1871 saveLedState = REG_READ(ah, AR_CFG_LED) &
1872 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1873 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1875 ath9k_hw_mark_phy_inactive(ah);
1877 ah->paprd_table_write_done = false;
1879 /* Only required on the first reset */
1880 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1882 AR9271_RESET_POWER_DOWN_CONTROL,
1883 AR9271_RADIO_RF_RST);
1887 if (!ath9k_hw_chip_reset(ah, chan)) {
1888 ath_err(common, "Chip reset failed\n");
1892 /* Only required on the first reset */
1893 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1894 ah->htc_reset_init = false;
1896 AR9271_RESET_POWER_DOWN_CONTROL,
1897 AR9271_GATE_MAC_CTL);
1902 usec = ktime_to_us(ktime_get_raw()) - usec;
1903 ath9k_hw_settsf64(ah, tsf + usec);
1905 if (AR_SREV_9280_20_OR_LATER(ah))
1906 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1908 if (!AR_SREV_9300_20_OR_LATER(ah))
1909 ar9002_hw_enable_async_fifo(ah);
1911 r = ath9k_hw_process_ini(ah, chan);
1915 ath9k_hw_set_rfmode(ah, chan);
1917 if (ath9k_hw_mci_is_enabled(ah))
1918 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1921 * Some AR91xx SoC devices frequently fail to accept TSF writes
1922 * right after the chip reset. When that happens, write a new
1923 * value after the initvals have been applied, with an offset
1924 * based on measured time difference
1926 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1928 ath9k_hw_settsf64(ah, tsf);
1931 ath9k_hw_init_mfp(ah);
1933 ath9k_hw_set_delta_slope(ah, chan);
1934 ath9k_hw_spur_mitigate_freq(ah, chan);
1935 ah->eep_ops->set_board_values(ah, chan);
1937 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1939 r = ath9k_hw_rf_set_freq(ah, chan);
1943 ath9k_hw_set_clockrate(ah);
1945 ath9k_hw_init_queues(ah);
1946 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1947 ath9k_hw_ani_cache_ini_regs(ah);
1948 ath9k_hw_init_qos(ah);
1950 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1951 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1953 ath9k_hw_init_global_settings(ah);
1955 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1956 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1957 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1958 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1959 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1960 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1961 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1964 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1966 ath9k_hw_set_dma(ah);
1968 if (!ath9k_hw_mci_is_enabled(ah))
1969 REG_WRITE(ah, AR_OBS, 8);
1971 ENABLE_REG_RMW_BUFFER(ah);
1972 if (ah->config.rx_intr_mitigation) {
1973 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1974 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
1977 if (ah->config.tx_intr_mitigation) {
1978 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1979 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1981 REG_RMW_BUFFER_FLUSH(ah);
1983 ath9k_hw_init_bb(ah, chan);
1986 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1987 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
1989 if (!ath9k_hw_init_cal(ah, chan))
1992 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1995 ENABLE_REGWRITE_BUFFER(ah);
1997 ath9k_hw_restore_chainmask(ah);
1998 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2000 REGWRITE_BUFFER_FLUSH(ah);
2002 ath9k_hw_gen_timer_start_tsf2(ah);
2004 ath9k_hw_init_desc(ah);
2006 if (ath9k_hw_btcoex_is_enabled(ah))
2007 ath9k_hw_btcoex_enable(ah);
2009 if (ath9k_hw_mci_is_enabled(ah))
2010 ar9003_mci_check_bt(ah);
2012 if (AR_SREV_9300_20_OR_LATER(ah)) {
2013 ath9k_hw_loadnf(ah, chan);
2014 ath9k_hw_start_nfcal(ah, true);
2017 if (AR_SREV_9300_20_OR_LATER(ah))
2018 ar9003_hw_bb_watchdog_config(ah);
2020 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
2021 ar9003_hw_disable_phy_restart(ah);
2023 ath9k_hw_apply_gpio_override(ah);
2025 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2026 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2028 if (ah->hw->conf.radar_enabled) {
2029 /* set HW specific DFS configuration */
2030 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
2031 ath9k_hw_set_radar_params(ah);
2036 EXPORT_SYMBOL(ath9k_hw_reset);
2038 /******************************/
2039 /* Power Management (Chipset) */
2040 /******************************/
2043 * Notify Power Mgt is disabled in self-generated frames.
2044 * If requested, force chip to sleep.
2046 static void ath9k_set_power_sleep(struct ath_hw *ah)
2048 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2050 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2051 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2052 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2053 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2054 /* xxx Required for WLAN only case ? */
2055 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2060 * Clear the RTC force wake bit to allow the
2061 * mac to go to sleep.
2063 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2065 if (ath9k_hw_mci_is_enabled(ah))
2068 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2069 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2071 /* Shutdown chip. Active low */
2072 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2073 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2077 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
2078 if (AR_SREV_9300_20_OR_LATER(ah))
2079 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2083 * Notify Power Management is enabled in self-generating
2084 * frames. If request, set power mode of chip to
2085 * auto/normal. Duration in units of 128us (1/8 TU).
2087 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2089 struct ath9k_hw_capabilities *pCap = &ah->caps;
2091 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2093 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2094 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2095 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2096 AR_RTC_FORCE_WAKE_ON_INT);
2099 /* When chip goes into network sleep, it could be waken
2100 * up by MCI_INT interrupt caused by BT's HW messages
2101 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2102 * rate (~100us). This will cause chip to leave and
2103 * re-enter network sleep mode frequently, which in
2104 * consequence will have WLAN MCI HW to generate lots of
2105 * SYS_WAKING and SYS_SLEEPING messages which will make
2106 * BT CPU to busy to process.
2108 if (ath9k_hw_mci_is_enabled(ah))
2109 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2110 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2112 * Clear the RTC force wake bit to allow the
2113 * mac to go to sleep.
2115 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2117 if (ath9k_hw_mci_is_enabled(ah))
2121 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2122 if (AR_SREV_9300_20_OR_LATER(ah))
2123 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2126 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2131 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2132 if (AR_SREV_9300_20_OR_LATER(ah)) {
2133 REG_WRITE(ah, AR_WA, ah->WARegVal);
2137 if ((REG_READ(ah, AR_RTC_STATUS) &
2138 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2139 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2142 if (!AR_SREV_9300_20_OR_LATER(ah))
2143 ath9k_hw_init_pll(ah, NULL);
2145 if (AR_SREV_9100(ah))
2146 REG_SET_BIT(ah, AR_RTC_RESET,
2149 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2150 AR_RTC_FORCE_WAKE_EN);
2151 if (AR_SREV_9100(ah))
2156 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2157 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2158 if (val == AR_RTC_STATUS_ON)
2161 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2162 AR_RTC_FORCE_WAKE_EN);
2165 ath_err(ath9k_hw_common(ah),
2166 "Failed to wakeup in %uus\n",
2167 POWER_UP_TIME / 20);
2171 if (ath9k_hw_mci_is_enabled(ah))
2172 ar9003_mci_set_power_awake(ah);
2174 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2179 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2181 struct ath_common *common = ath9k_hw_common(ah);
2183 static const char *modes[] = {
2190 if (ah->power_mode == mode)
2193 ath_dbg(common, RESET, "%s -> %s\n",
2194 modes[ah->power_mode], modes[mode]);
2197 case ATH9K_PM_AWAKE:
2198 status = ath9k_hw_set_power_awake(ah);
2200 case ATH9K_PM_FULL_SLEEP:
2201 if (ath9k_hw_mci_is_enabled(ah))
2202 ar9003_mci_set_full_sleep(ah);
2204 ath9k_set_power_sleep(ah);
2205 ah->chip_fullsleep = true;
2207 case ATH9K_PM_NETWORK_SLEEP:
2208 ath9k_set_power_network_sleep(ah);
2211 ath_err(common, "Unknown power mode %u\n", mode);
2214 ah->power_mode = mode;
2217 * XXX: If this warning never comes up after a while then
2218 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2219 * ath9k_hw_setpower() return type void.
2222 if (!(ah->ah_flags & AH_UNPLUGGED))
2223 ATH_DBG_WARN_ON_ONCE(!status);
2227 EXPORT_SYMBOL(ath9k_hw_setpower);
2229 /*******************/
2230 /* Beacon Handling */
2231 /*******************/
2233 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2237 ENABLE_REGWRITE_BUFFER(ah);
2239 switch (ah->opmode) {
2240 case NL80211_IFTYPE_ADHOC:
2241 REG_SET_BIT(ah, AR_TXCFG,
2242 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2243 case NL80211_IFTYPE_MESH_POINT:
2244 case NL80211_IFTYPE_AP:
2245 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2246 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2247 TU_TO_USEC(ah->config.dma_beacon_response_time));
2248 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2249 TU_TO_USEC(ah->config.sw_beacon_response_time));
2251 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2254 ath_dbg(ath9k_hw_common(ah), BEACON,
2255 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2260 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2261 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2262 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2264 REGWRITE_BUFFER_FLUSH(ah);
2266 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2268 EXPORT_SYMBOL(ath9k_hw_beaconinit);
2270 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2271 const struct ath9k_beacon_state *bs)
2273 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2274 struct ath9k_hw_capabilities *pCap = &ah->caps;
2275 struct ath_common *common = ath9k_hw_common(ah);
2277 ENABLE_REGWRITE_BUFFER(ah);
2279 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2280 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2281 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2283 REGWRITE_BUFFER_FLUSH(ah);
2285 REG_RMW_FIELD(ah, AR_RSSI_THR,
2286 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2288 beaconintval = bs->bs_intval;
2290 if (bs->bs_sleepduration > beaconintval)
2291 beaconintval = bs->bs_sleepduration;
2293 dtimperiod = bs->bs_dtimperiod;
2294 if (bs->bs_sleepduration > dtimperiod)
2295 dtimperiod = bs->bs_sleepduration;
2297 if (beaconintval == dtimperiod)
2298 nextTbtt = bs->bs_nextdtim;
2300 nextTbtt = bs->bs_nexttbtt;
2302 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2303 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2304 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2305 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
2307 ENABLE_REGWRITE_BUFFER(ah);
2309 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2310 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2312 REG_WRITE(ah, AR_SLEEP1,
2313 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2314 | AR_SLEEP1_ASSUME_DTIM);
2316 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2317 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2319 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2321 REG_WRITE(ah, AR_SLEEP2,
2322 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2324 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2325 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2327 REGWRITE_BUFFER_FLUSH(ah);
2329 REG_SET_BIT(ah, AR_TIMER_MODE,
2330 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2333 /* TSF Out of Range Threshold */
2334 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2336 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2338 /*******************/
2339 /* HW Capabilities */
2340 /*******************/
2342 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2344 eeprom_chainmask &= chip_chainmask;
2345 if (eeprom_chainmask)
2346 return eeprom_chainmask;
2348 return chip_chainmask;
2352 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2353 * @ah: the atheros hardware data structure
2355 * We enable DFS support upstream on chipsets which have passed a series
2356 * of tests. The testing requirements are going to be documented. Desired
2357 * test requirements are documented at:
2359 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2361 * Once a new chipset gets properly tested an individual commit can be used
2362 * to document the testing for DFS for that chipset.
2364 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2367 switch (ah->hw_version.macVersion) {
2368 /* for temporary testing DFS with 9280 */
2369 case AR_SREV_VERSION_9280:
2370 /* AR9580 will likely be our first target to get testing on */
2371 case AR_SREV_VERSION_9580:
2378 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2380 struct ath9k_hw_capabilities *pCap = &ah->caps;
2381 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2382 struct ath_common *common = ath9k_hw_common(ah);
2385 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2387 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2388 regulatory->current_rd = eeval;
2390 if (ah->opmode != NL80211_IFTYPE_AP &&
2391 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2392 if (regulatory->current_rd == 0x64 ||
2393 regulatory->current_rd == 0x65)
2394 regulatory->current_rd += 5;
2395 else if (regulatory->current_rd == 0x41)
2396 regulatory->current_rd = 0x43;
2397 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2398 regulatory->current_rd);
2401 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2403 if (eeval & AR5416_OPFLAGS_11A) {
2404 if (ah->disable_5ghz)
2405 ath_warn(common, "disabling 5GHz band\n");
2407 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2410 if (eeval & AR5416_OPFLAGS_11G) {
2411 if (ah->disable_2ghz)
2412 ath_warn(common, "disabling 2GHz band\n");
2414 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2417 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2418 ath_err(common, "both bands are disabled\n");
2422 if (AR_SREV_9485(ah) ||
2426 pCap->chip_chainmask = 1;
2427 else if (!AR_SREV_9280_20_OR_LATER(ah))
2428 pCap->chip_chainmask = 7;
2429 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2433 pCap->chip_chainmask = 3;
2435 pCap->chip_chainmask = 7;
2437 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2439 * For AR9271 we will temporarilly uses the rx chainmax as read from
2442 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2443 !(eeval & AR5416_OPFLAGS_11A) &&
2444 !(AR_SREV_9271(ah)))
2445 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2446 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2447 else if (AR_SREV_9100(ah))
2448 pCap->rx_chainmask = 0x7;
2450 /* Use rx_chainmask from EEPROM. */
2451 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2453 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2454 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2455 ah->txchainmask = pCap->tx_chainmask;
2456 ah->rxchainmask = pCap->rx_chainmask;
2458 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2460 /* enable key search for every frame in an aggregate */
2461 if (AR_SREV_9300_20_OR_LATER(ah))
2462 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2464 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2466 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2467 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2469 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2471 if (AR_SREV_9271(ah))
2472 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2473 else if (AR_DEVID_7010(ah))
2474 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2475 else if (AR_SREV_9300_20_OR_LATER(ah))
2476 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2477 else if (AR_SREV_9287_11_OR_LATER(ah))
2478 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2479 else if (AR_SREV_9285_12_OR_LATER(ah))
2480 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2481 else if (AR_SREV_9280_20_OR_LATER(ah))
2482 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2484 pCap->num_gpio_pins = AR_NUM_GPIO;
2486 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2487 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2489 pCap->rts_aggr_limit = (8 * 1024);
2491 #ifdef CONFIG_ATH9K_RFKILL
2492 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2493 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2495 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2496 ah->rfkill_polarity =
2497 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2499 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2502 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2503 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2505 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2507 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2508 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2510 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2512 if (AR_SREV_9300_20_OR_LATER(ah)) {
2513 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2514 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2515 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
2516 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2518 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2519 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2520 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2521 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2522 pCap->txs_len = sizeof(struct ar9003_txs);
2524 pCap->tx_desc_len = sizeof(struct ath_desc);
2525 if (AR_SREV_9280_20(ah))
2526 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2529 if (AR_SREV_9300_20_OR_LATER(ah))
2530 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2532 if (AR_SREV_9561(ah))
2533 ah->ent_mode = 0x3BDA000;
2534 else if (AR_SREV_9300_20_OR_LATER(ah))
2535 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2537 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2538 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2540 if (AR_SREV_9285(ah)) {
2541 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2543 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2544 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2545 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2546 ath_info(common, "Enable LNA combining\n");
2551 if (AR_SREV_9300_20_OR_LATER(ah)) {
2552 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2553 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2556 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2557 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2558 if ((ant_div_ctl1 >> 0x6) == 0x3) {
2559 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2560 ath_info(common, "Enable LNA combining\n");
2564 if (ath9k_hw_dfs_tested(ah))
2565 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2567 tx_chainmask = pCap->tx_chainmask;
2568 rx_chainmask = pCap->rx_chainmask;
2569 while (tx_chainmask || rx_chainmask) {
2570 if (tx_chainmask & BIT(0))
2571 pCap->max_txchains++;
2572 if (rx_chainmask & BIT(0))
2573 pCap->max_rxchains++;
2579 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2580 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2581 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2583 if (AR_SREV_9462_20_OR_LATER(ah))
2584 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2587 if (AR_SREV_9300_20_OR_LATER(ah) &&
2588 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2589 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2591 #ifdef CONFIG_ATH9K_WOW
2592 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2593 ah->wow.max_patterns = MAX_NUM_PATTERN;
2595 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2601 /****************************/
2602 /* GPIO / RFKILL / Antennae */
2603 /****************************/
2605 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2609 u32 gpio_shift, tmp;
2612 addr = AR_GPIO_OUTPUT_MUX3;
2614 addr = AR_GPIO_OUTPUT_MUX2;
2616 addr = AR_GPIO_OUTPUT_MUX1;
2618 gpio_shift = (gpio % 6) * 5;
2620 if (AR_SREV_9280_20_OR_LATER(ah)
2621 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2622 REG_RMW(ah, addr, (type << gpio_shift),
2623 (0x1f << gpio_shift));
2625 tmp = REG_READ(ah, addr);
2626 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2627 tmp &= ~(0x1f << gpio_shift);
2628 tmp |= (type << gpio_shift);
2629 REG_WRITE(ah, addr, tmp);
2633 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2637 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2639 if (AR_DEVID_7010(ah)) {
2641 REG_RMW(ah, AR7010_GPIO_OE,
2642 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2643 (AR7010_GPIO_OE_MASK << gpio_shift));
2647 gpio_shift = gpio << 1;
2650 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2651 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2653 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2655 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2657 #define MS_REG_READ(x, y) \
2658 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2660 if (gpio >= ah->caps.num_gpio_pins)
2663 if (AR_DEVID_7010(ah)) {
2665 val = REG_READ(ah, AR7010_GPIO_IN);
2666 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2667 } else if (AR_SREV_9300_20_OR_LATER(ah))
2668 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2669 AR_GPIO_BIT(gpio)) != 0;
2670 else if (AR_SREV_9271(ah))
2671 return MS_REG_READ(AR9271, gpio) != 0;
2672 else if (AR_SREV_9287_11_OR_LATER(ah))
2673 return MS_REG_READ(AR9287, gpio) != 0;
2674 else if (AR_SREV_9285_12_OR_LATER(ah))
2675 return MS_REG_READ(AR9285, gpio) != 0;
2676 else if (AR_SREV_9280_20_OR_LATER(ah))
2677 return MS_REG_READ(AR928X, gpio) != 0;
2679 return MS_REG_READ(AR, gpio) != 0;
2681 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2683 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2688 if (AR_DEVID_7010(ah)) {
2690 REG_RMW(ah, AR7010_GPIO_OE,
2691 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2692 (AR7010_GPIO_OE_MASK << gpio_shift));
2696 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2697 gpio_shift = 2 * gpio;
2700 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2701 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2703 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2705 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2707 if (AR_DEVID_7010(ah)) {
2709 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2714 if (AR_SREV_9271(ah))
2717 if ((1 << gpio) & AR_GPIO_OE_OUT_MASK)
2718 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2721 gpio_set_value(gpio, val & 1);
2723 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2725 void ath9k_hw_request_gpio(struct ath_hw *ah, u32 gpio, const char *label)
2727 if (gpio >= ah->caps.num_gpio_pins)
2730 gpio_request_one(gpio, GPIOF_DIR_OUT | GPIOF_INIT_LOW, label);
2732 EXPORT_SYMBOL(ath9k_hw_request_gpio);
2734 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2736 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2738 EXPORT_SYMBOL(ath9k_hw_setantenna);
2740 /*********************/
2741 /* General Operation */
2742 /*********************/
2744 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2746 u32 bits = REG_READ(ah, AR_RX_FILTER);
2747 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2749 if (phybits & AR_PHY_ERR_RADAR)
2750 bits |= ATH9K_RX_FILTER_PHYRADAR;
2751 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2752 bits |= ATH9K_RX_FILTER_PHYERR;
2756 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2758 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2762 ENABLE_REGWRITE_BUFFER(ah);
2764 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2765 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2767 REG_WRITE(ah, AR_RX_FILTER, bits);
2770 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2771 phybits |= AR_PHY_ERR_RADAR;
2772 if (bits & ATH9K_RX_FILTER_PHYERR)
2773 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2774 REG_WRITE(ah, AR_PHY_ERR, phybits);
2777 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2779 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2781 REGWRITE_BUFFER_FLUSH(ah);
2783 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2785 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2787 if (ath9k_hw_mci_is_enabled(ah))
2788 ar9003_mci_bt_gain_ctrl(ah);
2790 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2793 ath9k_hw_init_pll(ah, NULL);
2794 ah->htc_reset_init = true;
2797 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2799 bool ath9k_hw_disable(struct ath_hw *ah)
2801 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2804 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2807 ath9k_hw_init_pll(ah, NULL);
2810 EXPORT_SYMBOL(ath9k_hw_disable);
2812 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2814 enum eeprom_param gain_param;
2816 if (IS_CHAN_2GHZ(chan))
2817 gain_param = EEP_ANTENNA_GAIN_2G;
2819 gain_param = EEP_ANTENNA_GAIN_5G;
2821 return ah->eep_ops->get_eeprom(ah, gain_param);
2824 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2827 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2828 struct ieee80211_channel *channel;
2829 int chan_pwr, new_pwr, max_gain;
2830 int ant_gain, ant_reduction = 0;
2835 channel = chan->chan;
2836 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2837 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2838 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2840 ant_gain = get_antenna_gain(ah, chan);
2841 if (ant_gain > max_gain)
2842 ant_reduction = ant_gain - max_gain;
2844 ah->eep_ops->set_txpower(ah, chan,
2845 ath9k_regd_get_ctl(reg, chan),
2846 ant_reduction, new_pwr, test);
2849 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2851 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2852 struct ath9k_channel *chan = ah->curchan;
2853 struct ieee80211_channel *channel = chan->chan;
2855 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
2857 channel->max_power = MAX_RATE_POWER / 2;
2859 ath9k_hw_apply_txpower(ah, chan, test);
2862 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2864 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2866 void ath9k_hw_setopmode(struct ath_hw *ah)
2868 ath9k_hw_set_operating_mode(ah, ah->opmode);
2870 EXPORT_SYMBOL(ath9k_hw_setopmode);
2872 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2874 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2875 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2877 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2879 void ath9k_hw_write_associd(struct ath_hw *ah)
2881 struct ath_common *common = ath9k_hw_common(ah);
2883 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2884 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2885 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2887 EXPORT_SYMBOL(ath9k_hw_write_associd);
2889 #define ATH9K_MAX_TSF_READ 10
2891 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2893 u32 tsf_lower, tsf_upper1, tsf_upper2;
2896 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2897 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2898 tsf_lower = REG_READ(ah, AR_TSF_L32);
2899 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2900 if (tsf_upper2 == tsf_upper1)
2902 tsf_upper1 = tsf_upper2;
2905 WARN_ON( i == ATH9K_MAX_TSF_READ );
2907 return (((u64)tsf_upper1 << 32) | tsf_lower);
2909 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2911 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2913 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2914 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2916 EXPORT_SYMBOL(ath9k_hw_settsf64);
2918 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2920 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2921 AH_TSF_WRITE_TIMEOUT))
2922 ath_dbg(ath9k_hw_common(ah), RESET,
2923 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2925 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2927 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2929 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
2932 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2934 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2936 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2938 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
2942 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
2943 macmode = AR_2040_JOINED_RX_CLEAR;
2947 REG_WRITE(ah, AR_2040_MODE, macmode);
2950 /* HW Generic timers configuration */
2952 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2954 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2955 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2956 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2957 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2958 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2959 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2960 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2961 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2962 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2963 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2964 AR_NDP2_TIMER_MODE, 0x0002},
2965 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2966 AR_NDP2_TIMER_MODE, 0x0004},
2967 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2968 AR_NDP2_TIMER_MODE, 0x0008},
2969 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2970 AR_NDP2_TIMER_MODE, 0x0010},
2971 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2972 AR_NDP2_TIMER_MODE, 0x0020},
2973 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2974 AR_NDP2_TIMER_MODE, 0x0040},
2975 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2976 AR_NDP2_TIMER_MODE, 0x0080}
2979 /* HW generic timer primitives */
2981 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2983 return REG_READ(ah, AR_TSF_L32);
2985 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2987 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
2989 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2991 if (timer_table->tsf2_enabled) {
2992 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
2993 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
2997 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2998 void (*trigger)(void *),
2999 void (*overflow)(void *),
3003 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3004 struct ath_gen_timer *timer;
3006 if ((timer_index < AR_FIRST_NDP_TIMER) ||
3007 (timer_index >= ATH_MAX_GEN_TIMER))
3010 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3011 !AR_SREV_9300_20_OR_LATER(ah))
3014 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3018 /* allocate a hardware generic timer slot */
3019 timer_table->timers[timer_index] = timer;
3020 timer->index = timer_index;
3021 timer->trigger = trigger;
3022 timer->overflow = overflow;
3025 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3026 timer_table->tsf2_enabled = true;
3027 ath9k_hw_gen_timer_start_tsf2(ah);
3032 EXPORT_SYMBOL(ath_gen_timer_alloc);
3034 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3035 struct ath_gen_timer *timer,
3039 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3042 timer_table->timer_mask |= BIT(timer->index);
3045 * Program generic timer registers
3047 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3049 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3051 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3052 gen_tmr_configuration[timer->index].mode_mask);
3054 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3056 * Starting from AR9462, each generic timer can select which tsf
3057 * to use. But we still follow the old rule, 0 - 7 use tsf and
3060 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3061 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3062 (1 << timer->index));
3064 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3065 (1 << timer->index));
3069 mask |= SM(AR_GENTMR_BIT(timer->index),
3070 AR_IMR_S5_GENTIMER_TRIG);
3071 if (timer->overflow)
3072 mask |= SM(AR_GENTMR_BIT(timer->index),
3073 AR_IMR_S5_GENTIMER_THRESH);
3075 REG_SET_BIT(ah, AR_IMR_S5, mask);
3077 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3078 ah->imask |= ATH9K_INT_GENTIMER;
3079 ath9k_hw_set_interrupts(ah);
3082 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3084 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3086 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3088 /* Clear generic timer enable bits. */
3089 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3090 gen_tmr_configuration[timer->index].mode_mask);
3092 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3094 * Need to switch back to TSF if it was using TSF2.
3096 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3097 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3098 (1 << timer->index));
3102 /* Disable both trigger and thresh interrupt masks */
3103 REG_CLR_BIT(ah, AR_IMR_S5,
3104 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3105 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3107 timer_table->timer_mask &= ~BIT(timer->index);
3109 if (timer_table->timer_mask == 0) {
3110 ah->imask &= ~ATH9K_INT_GENTIMER;
3111 ath9k_hw_set_interrupts(ah);
3114 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3116 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3118 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3120 /* free the hardware generic timer slot */
3121 timer_table->timers[timer->index] = NULL;
3124 EXPORT_SYMBOL(ath_gen_timer_free);
3127 * Generic Timer Interrupts handling
3129 void ath_gen_timer_isr(struct ath_hw *ah)
3131 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3132 struct ath_gen_timer *timer;
3133 unsigned long trigger_mask, thresh_mask;
3136 /* get hardware generic timer interrupt status */
3137 trigger_mask = ah->intr_gen_timer_trigger;
3138 thresh_mask = ah->intr_gen_timer_thresh;
3139 trigger_mask &= timer_table->timer_mask;
3140 thresh_mask &= timer_table->timer_mask;
3142 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
3143 timer = timer_table->timers[index];
3146 if (!timer->overflow)
3149 trigger_mask &= ~BIT(index);
3150 timer->overflow(timer->arg);
3153 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
3154 timer = timer_table->timers[index];
3157 if (!timer->trigger)
3159 timer->trigger(timer->arg);
3162 EXPORT_SYMBOL(ath_gen_timer_isr);
3171 } ath_mac_bb_names[] = {
3172 /* Devices with external radios */
3173 { AR_SREV_VERSION_5416_PCI, "5416" },
3174 { AR_SREV_VERSION_5416_PCIE, "5418" },
3175 { AR_SREV_VERSION_9100, "9100" },
3176 { AR_SREV_VERSION_9160, "9160" },
3177 /* Single-chip solutions */
3178 { AR_SREV_VERSION_9280, "9280" },
3179 { AR_SREV_VERSION_9285, "9285" },
3180 { AR_SREV_VERSION_9287, "9287" },
3181 { AR_SREV_VERSION_9271, "9271" },
3182 { AR_SREV_VERSION_9300, "9300" },
3183 { AR_SREV_VERSION_9330, "9330" },
3184 { AR_SREV_VERSION_9340, "9340" },
3185 { AR_SREV_VERSION_9485, "9485" },
3186 { AR_SREV_VERSION_9462, "9462" },
3187 { AR_SREV_VERSION_9550, "9550" },
3188 { AR_SREV_VERSION_9565, "9565" },
3189 { AR_SREV_VERSION_9531, "9531" },
3190 { AR_SREV_VERSION_9561, "9561" },
3193 /* For devices with external radios */
3197 } ath_rf_names[] = {
3199 { AR_RAD5133_SREV_MAJOR, "5133" },
3200 { AR_RAD5122_SREV_MAJOR, "5122" },
3201 { AR_RAD2133_SREV_MAJOR, "2133" },
3202 { AR_RAD2122_SREV_MAJOR, "2122" }
3206 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3208 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3212 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3213 if (ath_mac_bb_names[i].version == mac_bb_version) {
3214 return ath_mac_bb_names[i].name;
3222 * Return the RF name. "????" is returned if the RF is unknown.
3223 * Used for devices with external radios.
3225 static const char *ath9k_hw_rf_name(u16 rf_version)
3229 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3230 if (ath_rf_names[i].version == rf_version) {
3231 return ath_rf_names[i].name;
3238 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3242 /* chipsets >= AR9280 are single-chip */
3243 if (AR_SREV_9280_20_OR_LATER(ah)) {
3244 used = scnprintf(hw_name, len,
3245 "Atheros AR%s Rev:%x",
3246 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3247 ah->hw_version.macRev);
3250 used = scnprintf(hw_name, len,
3251 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3252 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3253 ah->hw_version.macRev,
3254 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3255 & AR_RADIO_SREV_MAJOR)),
3256 ah->hw_version.phyRev);
3259 hw_name[used] = '\0';
3261 EXPORT_SYMBOL(ath9k_hw_name);