2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
34 #define ATHEROS_VENDOR_ID 0x168c
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR9300_DEVID_AR9580 0x0033
49 #define AR9300_DEVID_AR9462 0x0034
50 #define AR9300_DEVID_AR9330 0x0035
52 #define AR5416_AR9100_DEVID 0x000b
54 #define AR_SUBVENDOR_ID_NOG 0x0e11
55 #define AR_SUBVENDOR_ID_NEW_A 0x7065
56 #define AR5416_MAGIC 0x19641014
58 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
59 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
60 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
62 #define AR9300_NUM_BT_WEIGHTS 4
63 #define AR9300_NUM_WLAN_WEIGHTS 4
65 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
67 #define ATH_DEFAULT_NOISE_FLOOR -95
69 #define ATH9K_RSSI_BAD -128
71 #define ATH9K_NUM_CHANNELS 38
73 /* Register read/write primitives */
74 #define REG_WRITE(_ah, _reg, _val) \
75 (_ah)->reg_ops.write((_ah), (_val), (_reg))
77 #define REG_READ(_ah, _reg) \
78 (_ah)->reg_ops.read((_ah), (_reg))
80 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
81 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
83 #define REG_RMW(_ah, _reg, _set, _clr) \
84 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
86 #define ENABLE_REGWRITE_BUFFER(_ah) \
88 if ((_ah)->reg_ops.enable_write_buffer) \
89 (_ah)->reg_ops.enable_write_buffer((_ah)); \
92 #define REGWRITE_BUFFER_FLUSH(_ah) \
94 if ((_ah)->reg_ops.write_flush) \
95 (_ah)->reg_ops.write_flush((_ah)); \
98 #define PR_EEP(_s, _val) \
100 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
104 #define SM(_v, _f) (((_v) << _f##_S) & _f)
105 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
106 #define REG_RMW_FIELD(_a, _r, _f, _v) \
107 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
108 #define REG_READ_FIELD(_a, _r, _f) \
109 (((REG_READ(_a, _r) & _f) >> _f##_S))
110 #define REG_SET_BIT(_a, _r, _f) \
111 REG_RMW(_a, _r, (_f), 0)
112 #define REG_CLR_BIT(_a, _r, _f) \
113 REG_RMW(_a, _r, 0, (_f))
115 #define DO_DELAY(x) do { \
116 if (((++(x) % 64) == 0) && \
117 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
122 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
123 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
125 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
126 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
128 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
129 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
130 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
133 #define AR_GPIOD_MASK 0x00001FFF
134 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
136 #define BASE_ACTIVATE_DELAY 100
137 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
138 #define COEF_SCALE_S 24
139 #define HT40_CHANNEL_CENTER_SHIFT 10
141 #define ATH9K_ANTENNA0_CHAINMASK 0x1
142 #define ATH9K_ANTENNA1_CHAINMASK 0x2
144 #define ATH9K_NUM_DMA_DEBUG_REGS 8
145 #define ATH9K_NUM_QUEUES 10
147 #define MAX_RATE_POWER 63
148 #define AH_WAIT_TIMEOUT 100000 /* (us) */
149 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
150 #define AH_TIME_QUANTUM 10
151 #define AR_KEYTABLE_SIZE 128
152 #define POWER_UP_TIME 10000
153 #define SPUR_RSSI_THRESH 40
154 #define UPPER_5G_SUB_BAND_START 5700
155 #define MID_5G_SUB_BAND_START 5400
157 #define CAB_TIMEOUT_VAL 10
158 #define BEACON_TIMEOUT_VAL 10
159 #define MIN_BEACON_TIMEOUT_VAL 1
162 #define INIT_CONFIG_STATUS 0x00000000
163 #define INIT_RSSI_THR 0x00000700
164 #define INIT_BCON_CNTRL_REG 0x00000000
166 #define TU_TO_USEC(_tu) ((_tu) << 10)
168 #define ATH9K_HW_RX_HP_QDEPTH 16
169 #define ATH9K_HW_RX_LP_QDEPTH 128
171 #define PAPRD_GAIN_TABLE_ENTRIES 32
172 #define PAPRD_TABLE_SZ 24
173 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
175 enum ath_hw_txq_subtype {
182 enum ath_ini_subsys {
190 ATH9K_HW_CAP_HT = BIT(0),
191 ATH9K_HW_CAP_RFSILENT = BIT(1),
192 ATH9K_HW_CAP_CST = BIT(2),
193 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
194 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
195 ATH9K_HW_CAP_EDMA = BIT(6),
196 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
197 ATH9K_HW_CAP_LDPC = BIT(8),
198 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
199 ATH9K_HW_CAP_SGI_20 = BIT(10),
200 ATH9K_HW_CAP_PAPRD = BIT(11),
201 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
202 ATH9K_HW_CAP_2GHZ = BIT(13),
203 ATH9K_HW_CAP_5GHZ = BIT(14),
204 ATH9K_HW_CAP_APM = BIT(15),
205 ATH9K_HW_CAP_RTT = BIT(16),
208 struct ath9k_hw_capabilities {
209 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
222 bool pcie_lcr_extsync_en;
225 struct ath9k_ops_config {
226 int dma_beacon_response_time;
227 int sw_beacon_response_time;
228 int additional_swba_backoff;
230 u32 cwm_ignore_extcca;
231 bool pcieSerDesWrite;
241 int serialize_regmode;
242 bool rx_intr_mitigation;
243 bool tx_intr_mitigation;
244 #define SPUR_DISABLE 0
245 #define SPUR_ENABLE_IOCTL 1
246 #define SPUR_ENABLE_EEPROM 2
247 #define AR_SPUR_5413_1 1640
248 #define AR_SPUR_5413_2 1200
249 #define AR_NO_SPUR 0x8000
250 #define AR_BASE_FREQ_2GHZ 2300
251 #define AR_BASE_FREQ_5GHZ 4900
252 #define AR_SPUR_FEEQ_BOUND_HT40 19
253 #define AR_SPUR_FEEQ_BOUND_HT20 10
255 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
257 u16 ani_poll_interval; /* ANI poll interval in ms */
261 ATH9K_INT_RX = 0x00000001,
262 ATH9K_INT_RXDESC = 0x00000002,
263 ATH9K_INT_RXHP = 0x00000001,
264 ATH9K_INT_RXLP = 0x00000002,
265 ATH9K_INT_RXNOFRM = 0x00000008,
266 ATH9K_INT_RXEOL = 0x00000010,
267 ATH9K_INT_RXORN = 0x00000020,
268 ATH9K_INT_TX = 0x00000040,
269 ATH9K_INT_TXDESC = 0x00000080,
270 ATH9K_INT_TIM_TIMER = 0x00000100,
271 ATH9K_INT_BB_WATCHDOG = 0x00000400,
272 ATH9K_INT_TXURN = 0x00000800,
273 ATH9K_INT_MIB = 0x00001000,
274 ATH9K_INT_RXPHY = 0x00004000,
275 ATH9K_INT_RXKCM = 0x00008000,
276 ATH9K_INT_SWBA = 0x00010000,
277 ATH9K_INT_BMISS = 0x00040000,
278 ATH9K_INT_BNR = 0x00100000,
279 ATH9K_INT_TIM = 0x00200000,
280 ATH9K_INT_DTIM = 0x00400000,
281 ATH9K_INT_DTIMSYNC = 0x00800000,
282 ATH9K_INT_GPIO = 0x01000000,
283 ATH9K_INT_CABEND = 0x02000000,
284 ATH9K_INT_TSFOOR = 0x04000000,
285 ATH9K_INT_GENTIMER = 0x08000000,
286 ATH9K_INT_CST = 0x10000000,
287 ATH9K_INT_GTT = 0x20000000,
288 ATH9K_INT_FATAL = 0x40000000,
289 ATH9K_INT_GLOBAL = 0x80000000,
290 ATH9K_INT_BMISC = ATH9K_INT_TIM |
295 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
307 ATH9K_INT_NOCARD = 0xffffffff
310 #define CHANNEL_CW_INT 0x00002
311 #define CHANNEL_CCK 0x00020
312 #define CHANNEL_OFDM 0x00040
313 #define CHANNEL_2GHZ 0x00080
314 #define CHANNEL_5GHZ 0x00100
315 #define CHANNEL_PASSIVE 0x00200
316 #define CHANNEL_DYN 0x00400
317 #define CHANNEL_HALF 0x04000
318 #define CHANNEL_QUARTER 0x08000
319 #define CHANNEL_HT20 0x10000
320 #define CHANNEL_HT40PLUS 0x20000
321 #define CHANNEL_HT40MINUS 0x40000
323 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
324 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
325 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
326 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
327 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
328 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
329 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
330 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
331 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
332 #define CHANNEL_ALL \
341 #define MAX_RTT_TABLE_ENTRY 6
342 #define RTT_HIST_MAX 3
343 struct ath9k_rtt_hist {
344 u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
348 #define MAX_IQCAL_MEASUREMENT 8
349 #define MAX_CL_TAB_ENTRY 16
351 struct ath9k_hw_cal_data {
359 bool nfcal_interference;
360 bool done_txiqcal_once;
361 bool done_txclcal_once;
362 u16 small_signal_gain[AR9300_MAX_CHAINS];
363 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
364 u32 num_measures[AR9300_MAX_CHAINS];
365 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
366 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
367 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
368 struct ath9k_rtt_hist rtt_hist;
371 struct ath9k_channel {
372 struct ieee80211_channel *chan;
373 struct ar5416AniState ani;
380 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
381 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
382 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
383 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
384 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
385 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
386 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
387 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
388 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
389 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
390 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
391 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
393 /* These macros check chanmode and not channelFlags */
394 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
395 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
396 ((_c)->chanmode == CHANNEL_G_HT20))
397 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
398 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
399 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
400 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
401 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
403 enum ath9k_power_mode {
406 ATH9K_PM_NETWORK_SLEEP,
411 SER_REG_MODE_OFF = 0,
413 SER_REG_MODE_AUTO = 2,
416 enum ath9k_rx_qtype {
422 struct ath9k_beacon_state {
426 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
429 u16 bs_cfpmaxduration;
432 u16 bs_bmissthreshold;
433 u32 bs_sleepduration;
434 u32 bs_tsfoor_threshold;
437 struct chan_centers {
444 ATH9K_RESET_POWER_ON,
449 struct ath9k_hw_version {
458 enum ath_usb_dev usbdev;
461 /* Generic TSF timer definitions */
463 #define ATH_MAX_GEN_TIMER 16
465 #define AR_GENTMR_BIT(_index) (1 << (_index))
468 * Using de Bruijin sequence to look up 1's index in a 32 bit number
469 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
471 #define debruijn32 0x077CB531U
473 struct ath_gen_timer_configuration {
480 struct ath_gen_timer {
481 void (*trigger)(void *arg);
482 void (*overflow)(void *arg);
487 struct ath_gen_timer_table {
488 u32 gen_timer_index[32];
489 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
491 unsigned long timer_bits;
496 struct ath_hw_antcomb_conf {
507 * struct ath_hw_radar_conf - radar detection initialization parameters
509 * @pulse_inband: threshold for checking the ratio of in-band power
510 * to total power for short radar pulses (half dB steps)
511 * @pulse_inband_step: threshold for checking an in-band power to total
512 * power ratio increase for short radar pulses (half dB steps)
513 * @pulse_height: threshold for detecting the beginning of a short
514 * radar pulse (dB step)
515 * @pulse_rssi: threshold for detecting if a short radar pulse is
517 * @pulse_maxlen: maximum pulse length (0.8 us steps)
519 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
520 * @radar_inband: threshold for checking the ratio of in-band power
521 * to total power for long radar pulses (half dB steps)
522 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
524 * @ext_channel: enable extension channel radar detection
526 struct ath_hw_radar_conf {
527 unsigned int pulse_inband;
528 unsigned int pulse_inband_step;
529 unsigned int pulse_height;
530 unsigned int pulse_rssi;
531 unsigned int pulse_maxlen;
533 unsigned int radar_rssi;
534 unsigned int radar_inband;
541 * struct ath_hw_private_ops - callbacks used internally by hardware code
543 * This structure contains private callbacks designed to only be used internally
544 * by the hardware core.
546 * @init_cal_settings: setup types of calibrations supported
547 * @init_cal: starts actual calibration
549 * @init_mode_regs: Initializes mode registers
550 * @init_mode_gain_regs: Initialize TX/RX gain registers
552 * @rf_set_freq: change frequency
553 * @spur_mitigate_freq: spur mitigation
554 * @rf_alloc_ext_banks:
555 * @rf_free_ext_banks:
557 * @compute_pll_control: compute the PLL control value to use for
558 * AR_RTC_PLL_CONTROL for a given channel
559 * @setup_calibration: set up calibration
560 * @iscal_supported: used to query if a type of calibration is supported
562 * @ani_cache_ini_regs: cache the values for ANI from the initial
563 * register settings through the register initialization.
565 struct ath_hw_private_ops {
566 /* Calibration ops */
567 void (*init_cal_settings)(struct ath_hw *ah);
568 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
570 void (*init_mode_regs)(struct ath_hw *ah);
571 void (*init_mode_gain_regs)(struct ath_hw *ah);
572 void (*setup_calibration)(struct ath_hw *ah,
573 struct ath9k_cal_list *currCal);
576 int (*rf_set_freq)(struct ath_hw *ah,
577 struct ath9k_channel *chan);
578 void (*spur_mitigate_freq)(struct ath_hw *ah,
579 struct ath9k_channel *chan);
580 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
581 void (*rf_free_ext_banks)(struct ath_hw *ah);
582 bool (*set_rf_regs)(struct ath_hw *ah,
583 struct ath9k_channel *chan,
585 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
586 void (*init_bb)(struct ath_hw *ah,
587 struct ath9k_channel *chan);
588 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
589 void (*olc_init)(struct ath_hw *ah);
590 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
591 void (*mark_phy_inactive)(struct ath_hw *ah);
592 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
593 bool (*rfbus_req)(struct ath_hw *ah);
594 void (*rfbus_done)(struct ath_hw *ah);
595 void (*restore_chainmask)(struct ath_hw *ah);
596 u32 (*compute_pll_control)(struct ath_hw *ah,
597 struct ath9k_channel *chan);
598 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
600 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
601 void (*set_radar_params)(struct ath_hw *ah,
602 struct ath_hw_radar_conf *conf);
603 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
607 void (*ani_cache_ini_regs)(struct ath_hw *ah);
611 * struct ath_hw_ops - callbacks used by hardware code and driver code
613 * This structure contains callbacks designed to to be used internally by
614 * hardware code and also by the lower level driver.
616 * @config_pci_powersave:
617 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
620 void (*config_pci_powersave)(struct ath_hw *ah,
622 void (*rx_enable)(struct ath_hw *ah);
623 void (*set_desc_link)(void *ds, u32 link);
624 bool (*calibrate)(struct ath_hw *ah,
625 struct ath9k_channel *chan,
628 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
629 void (*set_txdesc)(struct ath_hw *ah, void *ds,
630 struct ath_tx_info *i);
631 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
632 struct ath_tx_status *ts);
633 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
634 struct ath_hw_antcomb_conf *antconf);
635 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
636 struct ath_hw_antcomb_conf *antconf);
640 struct ath_nf_limits {
648 TX_IQ_ON_AGC_CAL = BIT(1),
653 #define AH_USE_EEPROM 0x1
654 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
655 #define AH_FASTCC 0x4
658 struct ath_ops reg_ops;
660 struct ieee80211_hw *hw;
661 struct ath_common common;
662 struct ath9k_hw_version hw_version;
663 struct ath9k_ops_config config;
664 struct ath9k_hw_capabilities caps;
665 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
666 struct ath9k_channel *curchan;
669 struct ar5416_eeprom_def def;
670 struct ar5416_eeprom_4k map4k;
671 struct ar9287_eeprom map9287;
672 struct ar9300_eeprom ar9300_eep;
674 const struct eeprom_ops *eep_ops;
680 bool need_an_top2_fixup;
684 struct ath_nf_limits nf_2g;
685 struct ath_nf_limits nf_5g;
693 enum nl80211_iftype opmode;
694 enum ath9k_power_mode power_mode;
697 struct ath9k_hw_cal_data *caldata;
698 struct ath9k_pacal_info pacal_info;
699 struct ar5416Stats stats;
700 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
702 int16_t curchan_rad_index;
703 enum ath9k_int imask;
705 u32 txok_interrupt_mask;
706 u32 txerr_interrupt_mask;
707 u32 txdesc_interrupt_mask;
708 u32 txeol_interrupt_mask;
709 u32 txurn_interrupt_mask;
710 atomic_t intr_ref_cnt;
717 struct ath9k_cal_list iq_caldata;
718 struct ath9k_cal_list adcgain_caldata;
719 struct ath9k_cal_list adcdc_caldata;
720 struct ath9k_cal_list tempCompCalData;
721 struct ath9k_cal_list *cal_list;
722 struct ath9k_cal_list *cal_list_last;
723 struct ath9k_cal_list *cal_list_curr;
724 #define totalPowerMeasI meas0.unsign
725 #define totalPowerMeasQ meas1.unsign
726 #define totalIqCorrMeas meas2.sign
727 #define totalAdcIOddPhase meas0.unsign
728 #define totalAdcIEvenPhase meas1.unsign
729 #define totalAdcQOddPhase meas2.unsign
730 #define totalAdcQEvenPhase meas3.unsign
731 #define totalAdcDcOffsetIOddPhase meas0.sign
732 #define totalAdcDcOffsetIEvenPhase meas1.sign
733 #define totalAdcDcOffsetQOddPhase meas2.sign
734 #define totalAdcDcOffsetQEvenPhase meas3.sign
736 u32 unsign[AR5416_MAX_CHAINS];
737 int32_t sign[AR5416_MAX_CHAINS];
740 u32 unsign[AR5416_MAX_CHAINS];
741 int32_t sign[AR5416_MAX_CHAINS];
744 u32 unsign[AR5416_MAX_CHAINS];
745 int32_t sign[AR5416_MAX_CHAINS];
748 u32 unsign[AR5416_MAX_CHAINS];
749 int32_t sign[AR5416_MAX_CHAINS];
754 u32 sta_id1_defaults;
760 } enable_32kHz_clock;
762 /* Private to hardware code */
763 struct ath_hw_private_ops private_ops;
764 /* Accessed by the lower level driver */
765 struct ath_hw_ops ops;
767 /* Used to program the radio on non single-chip devices */
768 u32 *analogBank0Data;
769 u32 *analogBank1Data;
770 u32 *analogBank2Data;
771 u32 *analogBank3Data;
772 u32 *analogBank6Data;
773 u32 *analogBank6TPCData;
774 u32 *analogBank7Data;
786 int totalSizeDesired[5];
790 enum ath9k_ani_cmd ani_function;
792 /* Bluetooth coexistance */
793 struct ath_btcoex_hw btcoex_hw;
794 u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
795 u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
801 struct ath_hw_radar_conf radar_conf;
803 u32 originalGain[22];
810 struct ar5416IniArray iniModes;
811 struct ar5416IniArray iniCommon;
812 struct ar5416IniArray iniBank0;
813 struct ar5416IniArray iniBB_RfGain;
814 struct ar5416IniArray iniBank1;
815 struct ar5416IniArray iniBank2;
816 struct ar5416IniArray iniBank3;
817 struct ar5416IniArray iniBank6;
818 struct ar5416IniArray iniBank6TPC;
819 struct ar5416IniArray iniBank7;
820 struct ar5416IniArray iniAddac;
821 struct ar5416IniArray iniPcieSerdes;
822 struct ar5416IniArray iniPcieSerdesLowPower;
823 struct ar5416IniArray iniModesAdditional;
824 struct ar5416IniArray iniModesAdditional_40M;
825 struct ar5416IniArray iniModesRxGain;
826 struct ar5416IniArray iniModesTxGain;
827 struct ar5416IniArray iniModes_9271_1_0_only;
828 struct ar5416IniArray iniCckfirNormal;
829 struct ar5416IniArray iniCckfirJapan2484;
830 struct ar5416IniArray ini_japan2484;
831 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
832 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
833 struct ar5416IniArray iniModes_9271_ANI_reg;
834 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
835 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
836 struct ar5416IniArray ini_radio_post_sys2ant;
837 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
839 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
840 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
841 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
842 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
844 u32 intr_gen_timer_trigger;
845 u32 intr_gen_timer_thresh;
846 struct ath_gen_timer_table hw_gen_timers;
848 struct ar9003_txs *ts_ring;
855 u32 bb_watchdog_last_status;
856 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
857 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
859 unsigned int paprd_target_power;
860 unsigned int paprd_training_power;
861 unsigned int paprd_ratemask;
862 unsigned int paprd_ratemask_ht40;
863 bool paprd_table_write_done;
864 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
865 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
867 * Store the permanent value of Reg 0x4004in WARegVal
868 * so we dont have to R/M/W. We should not be reading
869 * this register when in sleep states.
873 /* Enterprise mode cap */
877 int (*get_mac_revision)(void);
878 int (*external_reset)(void);
882 enum ath_bus_type ath_bus_type;
883 void (*read_cachesize)(struct ath_common *common, int *csz);
884 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
885 void (*bt_coex_prep)(struct ath_common *common);
886 void (*extn_synch_en)(struct ath_common *common);
887 void (*aspm_init)(struct ath_common *common);
890 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
895 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
897 return &(ath9k_hw_common(ah)->regulatory);
900 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
902 return &ah->private_ops;
905 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
910 static inline u8 get_streams(int mask)
912 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
915 /* Initialization, Detach, Reset */
916 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
917 void ath9k_hw_deinit(struct ath_hw *ah);
918 int ath9k_hw_init(struct ath_hw *ah);
919 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
920 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
921 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
922 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
924 /* GPIO / RFKILL / Antennae */
925 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
926 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
927 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
929 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
930 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
931 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
933 /* General Operation */
934 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
935 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
936 int column, unsigned int *writecnt);
937 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
938 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
940 u32 frameLen, u16 rateix, bool shortPreamble);
941 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
942 struct ath9k_channel *chan,
943 struct chan_centers *centers);
944 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
945 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
946 bool ath9k_hw_phy_disable(struct ath_hw *ah);
947 bool ath9k_hw_disable(struct ath_hw *ah);
948 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
949 void ath9k_hw_setopmode(struct ath_hw *ah);
950 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
951 void ath9k_hw_setbssidmask(struct ath_hw *ah);
952 void ath9k_hw_write_associd(struct ath_hw *ah);
953 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
954 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
955 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
956 void ath9k_hw_reset_tsf(struct ath_hw *ah);
957 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
958 void ath9k_hw_init_global_settings(struct ath_hw *ah);
959 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
960 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
961 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
962 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
963 const struct ath9k_beacon_state *bs);
964 bool ath9k_hw_check_alive(struct ath_hw *ah);
966 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
968 /* Generic hw timer primitives */
969 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
970 void (*trigger)(void *),
971 void (*overflow)(void *),
974 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
975 struct ath_gen_timer *timer,
978 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
980 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
981 void ath_gen_timer_isr(struct ath_hw *hw);
983 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
986 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
989 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
990 u32 *coef_mantissa, u32 *coef_exponent);
991 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
994 * Code Specific to AR5008, AR9001 or AR9002,
995 * we stuff these here to avoid callbacks for AR9003.
997 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
998 int ar9002_hw_rf_claim(struct ath_hw *ah);
999 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1002 * Code specific to AR9003, we stuff these here to avoid callbacks
1003 * for older families
1005 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1006 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1007 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1008 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1009 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1010 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1011 struct ath9k_hw_cal_data *caldata,
1013 int ar9003_paprd_create_curve(struct ath_hw *ah,
1014 struct ath9k_hw_cal_data *caldata, int chain);
1015 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1016 int ar9003_paprd_init_table(struct ath_hw *ah);
1017 bool ar9003_paprd_is_done(struct ath_hw *ah);
1018 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
1020 /* Hardware family op attach helpers */
1021 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1022 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1023 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1025 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1026 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1028 void ar9002_hw_attach_ops(struct ath_hw *ah);
1029 void ar9003_hw_attach_ops(struct ath_hw *ah);
1031 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1033 * ANI work can be shared between all families but a next
1034 * generation implementation of ANI will be used only for AR9003 only
1035 * for now as the other families still need to be tested with the same
1036 * next generation ANI. Feel free to start testing it though for the
1037 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1039 extern int modparam_force_new_ani;
1040 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1041 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1042 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1044 #define ATH9K_CLOCK_RATE_CCK 22
1045 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1046 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1047 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44