2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb))
23 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
25 return sc->ps_enabled &&
26 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
30 * Setup and link descriptors.
32 * 11N: we can no longer afford to self link the last descriptor.
33 * MAC acknowledges BA status as long as it copies frames to host
34 * buffer (or rx fifo). This can incorrectly acknowledge packets
35 * to a sender if last desc is self-linked.
37 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_rxbuf *bf)
39 struct ath_hw *ah = sc->sc_ah;
40 struct ath_common *common = ath9k_hw_common(ah);
45 ds->ds_link = 0; /* link to null */
46 ds->ds_data = bf->bf_buf_addr;
48 /* virtual addr of the beginning of the buffer. */
51 ds->ds_vdata = skb->data;
54 * setup rx descriptors. The rx_bufsize here tells the hardware
55 * how much data it can DMA to us and that we are prepared
58 ath9k_hw_setuprxdesc(ah, ds,
62 if (sc->rx.rxlink == NULL)
63 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
65 *sc->rx.rxlink = bf->bf_daddr;
67 sc->rx.rxlink = &ds->ds_link;
70 static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_rxbuf *bf)
73 ath_rx_buf_link(sc, sc->rx.buf_hold);
78 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
80 /* XXX block beacon interrupts */
81 ath9k_hw_setantenna(sc->sc_ah, antenna);
82 sc->rx.defant = antenna;
83 sc->rx.rxotherant = 0;
86 static void ath_opmode_init(struct ath_softc *sc)
88 struct ath_hw *ah = sc->sc_ah;
89 struct ath_common *common = ath9k_hw_common(ah);
93 /* configure rx filter */
94 rfilt = ath_calcrxfilter(sc);
95 ath9k_hw_setrxfilter(ah, rfilt);
97 /* configure bssid mask */
98 ath_hw_setbssidmask(common);
100 /* configure operational mode */
101 ath9k_hw_setopmode(ah);
103 /* calculate and install multicast filter */
104 mfilt[0] = mfilt[1] = ~0;
105 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
108 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
109 enum ath9k_rx_qtype qtype)
111 struct ath_hw *ah = sc->sc_ah;
112 struct ath_rx_edma *rx_edma;
114 struct ath_rxbuf *bf;
116 rx_edma = &sc->rx.rx_edma[qtype];
117 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
120 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
121 list_del_init(&bf->list);
125 memset(skb->data, 0, ah->caps.rx_status_len);
126 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
127 ah->caps.rx_status_len, DMA_TO_DEVICE);
129 SKB_CB_ATHBUF(skb) = bf;
130 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
131 __skb_queue_tail(&rx_edma->rx_fifo, skb);
136 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
137 enum ath9k_rx_qtype qtype)
139 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
140 struct ath_rxbuf *bf, *tbf;
142 if (list_empty(&sc->rx.rxbuf)) {
143 ath_dbg(common, QUEUE, "No free rx buf available\n");
147 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
148 if (!ath_rx_edma_buf_link(sc, qtype))
153 static void ath_rx_remove_buffer(struct ath_softc *sc,
154 enum ath9k_rx_qtype qtype)
156 struct ath_rxbuf *bf;
157 struct ath_rx_edma *rx_edma;
160 rx_edma = &sc->rx.rx_edma[qtype];
162 while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
163 bf = SKB_CB_ATHBUF(skb);
165 list_add_tail(&bf->list, &sc->rx.rxbuf);
169 static void ath_rx_edma_cleanup(struct ath_softc *sc)
171 struct ath_hw *ah = sc->sc_ah;
172 struct ath_common *common = ath9k_hw_common(ah);
173 struct ath_rxbuf *bf;
175 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
176 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
178 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
180 dma_unmap_single(sc->dev, bf->bf_buf_addr,
183 dev_kfree_skb_any(bf->bf_mpdu);
190 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
192 __skb_queue_head_init(&rx_edma->rx_fifo);
193 rx_edma->rx_fifo_hwsize = size;
196 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
198 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
199 struct ath_hw *ah = sc->sc_ah;
201 struct ath_rxbuf *bf;
205 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
206 ah->caps.rx_status_len);
208 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
209 ah->caps.rx_lp_qdepth);
210 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
211 ah->caps.rx_hp_qdepth);
213 size = sizeof(struct ath_rxbuf) * nbufs;
214 bf = devm_kzalloc(sc->dev, size, GFP_KERNEL);
218 INIT_LIST_HEAD(&sc->rx.rxbuf);
220 for (i = 0; i < nbufs; i++, bf++) {
221 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
227 memset(skb->data, 0, common->rx_bufsize);
230 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
233 if (unlikely(dma_mapping_error(sc->dev,
235 dev_kfree_skb_any(skb);
239 "dma_mapping_error() on RX init\n");
244 list_add_tail(&bf->list, &sc->rx.rxbuf);
250 ath_rx_edma_cleanup(sc);
254 static void ath_edma_start_recv(struct ath_softc *sc)
256 ath9k_hw_rxena(sc->sc_ah);
257 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP);
258 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP);
260 ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
263 static void ath_edma_stop_recv(struct ath_softc *sc)
265 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
266 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
269 int ath_rx_init(struct ath_softc *sc, int nbufs)
271 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
273 struct ath_rxbuf *bf;
276 spin_lock_init(&sc->sc_pcu_lock);
278 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
279 sc->sc_ah->caps.rx_status_len;
281 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
282 return ath_rx_edma_init(sc, nbufs);
284 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
285 common->cachelsz, common->rx_bufsize);
287 /* Initialize rx descriptors */
289 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
293 "failed to allocate rx descriptors: %d\n",
298 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
299 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
307 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
310 if (unlikely(dma_mapping_error(sc->dev,
312 dev_kfree_skb_any(skb);
316 "dma_mapping_error() on RX init\n");
321 sc->rx.rxlink = NULL;
329 void ath_rx_cleanup(struct ath_softc *sc)
331 struct ath_hw *ah = sc->sc_ah;
332 struct ath_common *common = ath9k_hw_common(ah);
334 struct ath_rxbuf *bf;
336 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
337 ath_rx_edma_cleanup(sc);
341 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
344 dma_unmap_single(sc->dev, bf->bf_buf_addr,
355 * Calculate the receive filter according to the
356 * operating mode and state:
358 * o always accept unicast, broadcast, and multicast traffic
359 * o maintain current state of phy error reception (the hal
360 * may enable phy error frames for noise immunity work)
361 * o probe request frames are accepted only when operating in
362 * hostap, adhoc, or monitor modes
363 * o enable promiscuous mode according to the interface state
365 * - when operating in adhoc mode so the 802.11 layer creates
366 * node table entries for peers,
367 * - when operating in station mode for collecting rssi data when
368 * the station is otherwise quiet, or
369 * - when operating as a repeater so we see repeater-sta beacons
373 u32 ath_calcrxfilter(struct ath_softc *sc)
377 if (config_enabled(CONFIG_ATH9K_TX99))
380 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
381 | ATH9K_RX_FILTER_MCAST;
383 /* if operating on a DFS channel, enable radar pulse detection */
384 if (sc->hw->conf.radar_enabled)
385 rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR;
387 if (sc->rx.rxfilter & FIF_PROBE_REQ)
388 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
391 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
392 * mode interface or when in monitor mode. AP mode does not need this
393 * since it receives all in-BSS frames anyway.
395 if (sc->sc_ah->is_monitoring)
396 rfilt |= ATH9K_RX_FILTER_PROM;
398 if (sc->rx.rxfilter & FIF_CONTROL)
399 rfilt |= ATH9K_RX_FILTER_CONTROL;
401 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
403 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
404 rfilt |= ATH9K_RX_FILTER_MYBEACON;
406 rfilt |= ATH9K_RX_FILTER_BEACON;
408 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
409 (sc->rx.rxfilter & FIF_PSPOLL))
410 rfilt |= ATH9K_RX_FILTER_PSPOLL;
412 if (conf_is_ht(&sc->hw->conf))
413 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
415 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
416 /* This is needed for older chips */
417 if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160)
418 rfilt |= ATH9K_RX_FILTER_PROM;
419 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
422 if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah))
423 rfilt |= ATH9K_RX_FILTER_4ADDRESS;
429 int ath_startrecv(struct ath_softc *sc)
431 struct ath_hw *ah = sc->sc_ah;
432 struct ath_rxbuf *bf, *tbf;
434 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
435 ath_edma_start_recv(sc);
439 if (list_empty(&sc->rx.rxbuf))
442 sc->rx.buf_hold = NULL;
443 sc->rx.rxlink = NULL;
444 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
445 ath_rx_buf_link(sc, bf);
448 /* We could have deleted elements so the list may be empty now */
449 if (list_empty(&sc->rx.rxbuf))
452 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
453 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
458 ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
463 static void ath_flushrecv(struct ath_softc *sc)
465 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
466 ath_rx_tasklet(sc, 1, true);
467 ath_rx_tasklet(sc, 1, false);
470 bool ath_stoprecv(struct ath_softc *sc)
472 struct ath_hw *ah = sc->sc_ah;
473 bool stopped, reset = false;
475 ath9k_hw_abortpcurecv(ah);
476 ath9k_hw_setrxfilter(ah, 0);
477 stopped = ath9k_hw_stopdmarecv(ah, &reset);
481 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
482 ath_edma_stop_recv(sc);
484 sc->rx.rxlink = NULL;
486 if (!(ah->ah_flags & AH_UNPLUGGED) &&
487 unlikely(!stopped)) {
488 ath_err(ath9k_hw_common(sc->sc_ah),
489 "Could not stop RX, we could be "
490 "confusing the DMA engine when we start RX up\n");
491 ATH_DBG_WARN_ON_ONCE(!stopped);
493 return stopped && !reset;
496 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
498 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
499 struct ieee80211_mgmt *mgmt;
500 u8 *pos, *end, id, elen;
501 struct ieee80211_tim_ie *tim;
503 mgmt = (struct ieee80211_mgmt *)skb->data;
504 pos = mgmt->u.beacon.variable;
505 end = skb->data + skb->len;
507 while (pos + 2 < end) {
510 if (pos + elen > end)
513 if (id == WLAN_EID_TIM) {
514 if (elen < sizeof(*tim))
516 tim = (struct ieee80211_tim_ie *) pos;
517 if (tim->dtim_count != 0)
519 return tim->bitmap_ctrl & 0x01;
528 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
530 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
532 if (skb->len < 24 + 8 + 2 + 2)
535 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
537 if (sc->ps_flags & PS_BEACON_SYNC) {
538 sc->ps_flags &= ~PS_BEACON_SYNC;
540 "Reconfigure beacon timers based on synchronized timestamp\n");
541 if (!(WARN_ON_ONCE(sc->cur_beacon_conf.beacon_interval == 0)))
542 ath9k_set_beacon(sc);
544 ath9k_update_p2p_ps(sc, sc->p2p_ps_vif->vif);
547 if (ath_beacon_dtim_pending_cab(skb)) {
549 * Remain awake waiting for buffered broadcast/multicast
550 * frames. If the last broadcast/multicast frame is not
551 * received properly, the next beacon frame will work as
552 * a backup trigger for returning into NETWORK SLEEP state,
553 * so we are waiting for it as well.
556 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
557 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
561 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
563 * This can happen if a broadcast frame is dropped or the AP
564 * fails to send a frame indicating that all CAB frames have
567 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
568 ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
572 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
574 struct ieee80211_hdr *hdr;
575 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
577 hdr = (struct ieee80211_hdr *)skb->data;
579 /* Process Beacon and CAB receive in PS state */
580 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
582 ath_rx_ps_beacon(sc, skb);
583 } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
584 (ieee80211_is_data(hdr->frame_control) ||
585 ieee80211_is_action(hdr->frame_control)) &&
586 is_multicast_ether_addr(hdr->addr1) &&
587 !ieee80211_has_moredata(hdr->frame_control)) {
589 * No more broadcast/multicast frames to be received at this
592 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
594 "All PS CAB frames received, back to sleep\n");
595 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
596 !is_multicast_ether_addr(hdr->addr1) &&
597 !ieee80211_has_morefrags(hdr->frame_control)) {
598 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
600 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
601 sc->ps_flags & (PS_WAIT_FOR_BEACON |
603 PS_WAIT_FOR_PSPOLL_DATA |
604 PS_WAIT_FOR_TX_ACK));
608 static bool ath_edma_get_buffers(struct ath_softc *sc,
609 enum ath9k_rx_qtype qtype,
610 struct ath_rx_status *rs,
611 struct ath_rxbuf **dest)
613 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
614 struct ath_hw *ah = sc->sc_ah;
615 struct ath_common *common = ath9k_hw_common(ah);
617 struct ath_rxbuf *bf;
620 skb = skb_peek(&rx_edma->rx_fifo);
624 bf = SKB_CB_ATHBUF(skb);
627 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
628 common->rx_bufsize, DMA_FROM_DEVICE);
630 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
631 if (ret == -EINPROGRESS) {
632 /*let device gain the buffer again*/
633 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
634 common->rx_bufsize, DMA_FROM_DEVICE);
638 __skb_unlink(skb, &rx_edma->rx_fifo);
639 if (ret == -EINVAL) {
640 /* corrupt descriptor, skip this one and the following one */
641 list_add_tail(&bf->list, &sc->rx.rxbuf);
642 ath_rx_edma_buf_link(sc, qtype);
644 skb = skb_peek(&rx_edma->rx_fifo);
646 bf = SKB_CB_ATHBUF(skb);
649 __skb_unlink(skb, &rx_edma->rx_fifo);
650 list_add_tail(&bf->list, &sc->rx.rxbuf);
651 ath_rx_edma_buf_link(sc, qtype);
661 static struct ath_rxbuf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
662 struct ath_rx_status *rs,
663 enum ath9k_rx_qtype qtype)
665 struct ath_rxbuf *bf = NULL;
667 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
676 static struct ath_rxbuf *ath_get_next_rx_buf(struct ath_softc *sc,
677 struct ath_rx_status *rs)
679 struct ath_hw *ah = sc->sc_ah;
680 struct ath_common *common = ath9k_hw_common(ah);
682 struct ath_rxbuf *bf;
685 if (list_empty(&sc->rx.rxbuf)) {
686 sc->rx.rxlink = NULL;
690 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
691 if (bf == sc->rx.buf_hold)
697 * Must provide the virtual address of the current
698 * descriptor, the physical address, and the virtual
699 * address of the next descriptor in the h/w chain.
700 * This allows the HAL to look ahead to see if the
701 * hardware is done with a descriptor by checking the
702 * done bit in the following descriptor and the address
703 * of the current descriptor the DMA engine is working
704 * on. All this is necessary because of our use of
705 * a self-linked list to avoid rx overruns.
707 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
708 if (ret == -EINPROGRESS) {
709 struct ath_rx_status trs;
710 struct ath_rxbuf *tbf;
711 struct ath_desc *tds;
713 memset(&trs, 0, sizeof(trs));
714 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
715 sc->rx.rxlink = NULL;
719 tbf = list_entry(bf->list.next, struct ath_rxbuf, list);
722 * On some hardware the descriptor status words could
723 * get corrupted, including the done bit. Because of
724 * this, check if the next descriptor's done bit is
727 * If the next descriptor's done bit is set, the current
728 * descriptor has been corrupted. Force s/w to discard
729 * this descriptor and continue...
733 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
734 if (ret == -EINPROGRESS)
738 * Re-check previous descriptor, in case it has been filled
741 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
742 if (ret == -EINPROGRESS) {
744 * mark descriptor as zero-length and set the 'more'
745 * flag to ensure that both buffers get discarded
757 * Synchronize the DMA transfer with CPU before
758 * 1. accessing the frame
759 * 2. requeueing the same buffer to h/w
761 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
768 static void ath9k_process_tsf(struct ath_rx_status *rs,
769 struct ieee80211_rx_status *rxs,
772 u32 tsf_lower = tsf & 0xffffffff;
774 rxs->mactime = (tsf & ~0xffffffffULL) | rs->rs_tstamp;
775 if (rs->rs_tstamp > tsf_lower &&
776 unlikely(rs->rs_tstamp - tsf_lower > 0x10000000))
777 rxs->mactime -= 0x100000000ULL;
779 if (rs->rs_tstamp < tsf_lower &&
780 unlikely(tsf_lower - rs->rs_tstamp > 0x10000000))
781 rxs->mactime += 0x100000000ULL;
785 * For Decrypt or Demic errors, we only mark packet status here and always push
786 * up the frame up to let mac80211 handle the actual error case, be it no
787 * decryption key or real decryption error. This let us keep statistics there.
789 static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
791 struct ath_rx_status *rx_stats,
792 struct ieee80211_rx_status *rx_status,
793 bool *decrypt_error, u64 tsf)
795 struct ieee80211_hw *hw = sc->hw;
796 struct ath_hw *ah = sc->sc_ah;
797 struct ath_common *common = ath9k_hw_common(ah);
798 struct ieee80211_hdr *hdr;
799 bool discard_current = sc->rx.discard_next;
802 * Discard corrupt descriptors which are marked in
803 * ath_get_next_rx_buf().
808 sc->rx.discard_next = false;
811 * Discard zero-length packets.
813 if (!rx_stats->rs_datalen) {
814 RX_STAT_INC(rx_len_err);
819 * rs_status follows rs_datalen so if rs_datalen is too large
820 * we can take a hint that hardware corrupted it, so ignore
823 if (rx_stats->rs_datalen > (common->rx_bufsize - ah->caps.rx_status_len)) {
824 RX_STAT_INC(rx_len_err);
828 /* Only use status info from the last fragment */
829 if (rx_stats->rs_more)
833 * Return immediately if the RX descriptor has been marked
834 * as corrupt based on the various error bits.
836 * This is different from the other corrupt descriptor
837 * condition handled above.
839 if (rx_stats->rs_status & ATH9K_RXERR_CORRUPT_DESC)
842 hdr = (struct ieee80211_hdr *) (skb->data + ah->caps.rx_status_len);
844 ath9k_process_tsf(rx_stats, rx_status, tsf);
845 ath_debug_stat_rx(sc, rx_stats);
848 * Process PHY errors and return so that the packet
851 if (rx_stats->rs_status & ATH9K_RXERR_PHY) {
852 ath9k_dfs_process_phyerr(sc, hdr, rx_stats, rx_status->mactime);
853 if (ath_process_fft(sc, hdr, rx_stats, rx_status->mactime))
854 RX_STAT_INC(rx_spectral);
860 * everything but the rate is checked here, the rate check is done
861 * separately to avoid doing two lookups for a rate for each frame.
863 if (!ath9k_cmn_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error, sc->rx.rxfilter))
866 if (ath_is_mybeacon(common, hdr)) {
867 RX_STAT_INC(rx_beacons);
868 rx_stats->is_mybeacon = true;
872 * This shouldn't happen, but have a safety check anyway.
874 if (WARN_ON(!ah->curchan))
877 if (ath9k_cmn_process_rate(common, hw, rx_stats, rx_status)) {
879 * No valid hardware bitrate found -- we should not get here
880 * because hardware has already validated this frame as OK.
882 ath_dbg(common, ANY, "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
884 RX_STAT_INC(rx_rate_err);
888 ath9k_cmn_process_rssi(common, hw, rx_stats, rx_status);
890 rx_status->band = ah->curchan->chan->band;
891 rx_status->freq = ah->curchan->chan->center_freq;
892 rx_status->antenna = rx_stats->rs_antenna;
893 rx_status->flag |= RX_FLAG_MACTIME_END;
895 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
896 if (ieee80211_is_data_present(hdr->frame_control) &&
897 !ieee80211_is_qos_nullfunc(hdr->frame_control))
904 sc->rx.discard_next = rx_stats->rs_more;
909 * Run the LNA combining algorithm only in these cases:
911 * Standalone WLAN cards with both LNA/Antenna diversity
912 * enabled in the EEPROM.
914 * WLAN+BT cards which are in the supported card list
915 * in ath_pci_id_table and the user has loaded the
916 * driver with "bt_ant_diversity" set to true.
918 static void ath9k_antenna_check(struct ath_softc *sc,
919 struct ath_rx_status *rs)
921 struct ath_hw *ah = sc->sc_ah;
922 struct ath9k_hw_capabilities *pCap = &ah->caps;
923 struct ath_common *common = ath9k_hw_common(ah);
925 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB))
929 * Change the default rx antenna if rx diversity
930 * chooses the other antenna 3 times in a row.
932 if (sc->rx.defant != rs->rs_antenna) {
933 if (++sc->rx.rxotherant >= 3)
934 ath_setdefantenna(sc, rs->rs_antenna);
936 sc->rx.rxotherant = 0;
939 if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) {
940 if (common->bt_ant_diversity)
941 ath_ant_comb_scan(sc, rs);
943 ath_ant_comb_scan(sc, rs);
947 static void ath9k_apply_ampdu_details(struct ath_softc *sc,
948 struct ath_rx_status *rs, struct ieee80211_rx_status *rxs)
951 rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN;
953 rxs->ampdu_reference = sc->rx.ampdu_ref;
955 if (!rs->rs_moreaggr) {
956 rxs->flag |= RX_FLAG_AMPDU_IS_LAST;
960 if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE)
961 rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR;
965 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
967 struct ath_rxbuf *bf;
968 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
969 struct ieee80211_rx_status *rxs;
970 struct ath_hw *ah = sc->sc_ah;
971 struct ath_common *common = ath9k_hw_common(ah);
972 struct ieee80211_hw *hw = sc->hw;
974 struct ath_rx_status rs;
975 enum ath9k_rx_qtype qtype;
976 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
980 dma_addr_t new_buf_addr;
981 unsigned int budget = 512;
984 dma_type = DMA_BIDIRECTIONAL;
986 dma_type = DMA_FROM_DEVICE;
988 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
990 tsf = ath9k_hw_gettsf64(ah);
993 bool decrypt_error = false;
995 memset(&rs, 0, sizeof(rs));
997 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
999 bf = ath_get_next_rx_buf(sc, &rs);
1009 * Take frame header from the first fragment and RX status from
1013 hdr_skb = sc->rx.frag;
1017 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1018 memset(rxs, 0, sizeof(struct ieee80211_rx_status));
1020 retval = ath9k_rx_skb_preprocess(sc, hdr_skb, &rs, rxs,
1021 &decrypt_error, tsf);
1023 goto requeue_drop_frag;
1025 /* Ensure we always have an skb to requeue once we are done
1026 * processing the current buffer's skb */
1027 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1029 /* If there is no memory we ignore the current RX'd frame,
1030 * tell hardware it can give us a new frame using the old
1031 * skb and put it at the tail of the sc->rx.rxbuf list for
1034 RX_STAT_INC(rx_oom_err);
1035 goto requeue_drop_frag;
1038 /* We will now give hardware our shiny new allocated skb */
1039 new_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1040 common->rx_bufsize, dma_type);
1041 if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) {
1042 dev_kfree_skb_any(requeue_skb);
1043 goto requeue_drop_frag;
1046 /* Unmap the frame */
1047 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1048 common->rx_bufsize, dma_type);
1050 bf->bf_mpdu = requeue_skb;
1051 bf->bf_buf_addr = new_buf_addr;
1053 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1054 if (ah->caps.rx_status_len)
1055 skb_pull(skb, ah->caps.rx_status_len);
1058 ath9k_cmn_rx_skb_postprocess(common, hdr_skb, &rs,
1059 rxs, decrypt_error);
1062 RX_STAT_INC(rx_frags);
1064 * rs_more indicates chained descriptors which can be
1065 * used to link buffers together for a sort of
1066 * scatter-gather operation.
1069 /* too many fragments - cannot handle frame */
1070 dev_kfree_skb_any(sc->rx.frag);
1071 dev_kfree_skb_any(skb);
1072 RX_STAT_INC(rx_too_many_frags_err);
1080 int space = skb->len - skb_tailroom(hdr_skb);
1082 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1084 RX_STAT_INC(rx_oom_err);
1085 goto requeue_drop_frag;
1090 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1092 dev_kfree_skb_any(skb);
1096 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1097 skb_trim(skb, skb->len - 8);
1099 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1100 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1102 PS_WAIT_FOR_PSPOLL_DATA)) ||
1103 ath9k_check_auto_sleep(sc))
1104 ath_rx_ps(sc, skb, rs.is_mybeacon);
1105 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1107 ath9k_antenna_check(sc, &rs);
1108 ath9k_apply_ampdu_details(sc, &rs, rxs);
1109 ath_debug_rate_stats(sc, &rs, skb);
1111 ieee80211_rx(hw, skb);
1115 dev_kfree_skb_any(sc->rx.frag);
1119 list_add_tail(&bf->list, &sc->rx.rxbuf);
1122 ath_rx_edma_buf_link(sc, qtype);
1124 ath_rx_buf_relink(sc, bf);
1133 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1134 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1135 ath9k_hw_set_interrupts(ah);