2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/interrupt.h>
23 * Theory of operation:
25 * There is ISR pseudo-cause register,
26 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
27 * Its bits represents OR'ed bits from 3 real ISR registers:
30 * Registers may be configured to either "write 1 to clear" or
31 * "clear on read" mode
33 * When handling interrupt, one have to mask/unmask interrupts for the
34 * real ISR registers, or hardware may malfunction.
38 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
39 #define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE
40 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
41 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
42 #define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \
46 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
47 BIT_DMA_PSEUDO_CAUSE_TX | \
48 BIT_DMA_PSEUDO_CAUSE_MISC))
50 #if defined(CONFIG_WIL6210_ISR_COR)
51 /* configure to Clear-On-Read mode */
52 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
54 static inline void wil_icr_clear(u32 x, void __iomem *addr)
57 #else /* defined(CONFIG_WIL6210_ISR_COR) */
58 /* configure to Write-1-to-Clear mode */
59 #define WIL_ICR_ICC_VALUE (0UL)
61 static inline void wil_icr_clear(u32 x, void __iomem *addr)
65 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
67 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
69 u32 x = ioread32(addr);
71 wil_icr_clear(x, addr);
76 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
78 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
79 HOSTADDR(RGF_DMA_EP_TX_ICR) +
80 offsetof(struct RGF_ICR, IMS));
83 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
85 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
86 HOSTADDR(RGF_DMA_EP_RX_ICR) +
87 offsetof(struct RGF_ICR, IMS));
90 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
92 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
93 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
94 offsetof(struct RGF_ICR, IMS));
97 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
99 wil_dbg_irq(wil, "%s()\n", __func__);
101 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
102 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
104 clear_bit(wil_status_irqen, &wil->status);
107 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
109 iowrite32(WIL6210_IMC_TX, wil->csr +
110 HOSTADDR(RGF_DMA_EP_TX_ICR) +
111 offsetof(struct RGF_ICR, IMC));
114 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
116 iowrite32(WIL6210_IMC_RX, wil->csr +
117 HOSTADDR(RGF_DMA_EP_RX_ICR) +
118 offsetof(struct RGF_ICR, IMC));
121 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
123 iowrite32(WIL6210_IMC_MISC, wil->csr +
124 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
125 offsetof(struct RGF_ICR, IMC));
128 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
130 wil_dbg_irq(wil, "%s()\n", __func__);
132 set_bit(wil_status_irqen, &wil->status);
134 iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
135 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
138 void wil6210_disable_irq(struct wil6210_priv *wil)
140 wil_dbg_irq(wil, "%s()\n", __func__);
142 wil6210_mask_irq_tx(wil);
143 wil6210_mask_irq_rx(wil);
144 wil6210_mask_irq_misc(wil);
145 wil6210_mask_irq_pseudo(wil);
148 void wil6210_enable_irq(struct wil6210_priv *wil)
150 wil_dbg_irq(wil, "%s()\n", __func__);
152 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
153 offsetof(struct RGF_ICR, ICC));
154 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
155 offsetof(struct RGF_ICR, ICC));
156 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
157 offsetof(struct RGF_ICR, ICC));
159 wil6210_unmask_irq_pseudo(wil);
160 wil6210_unmask_irq_tx(wil);
161 wil6210_unmask_irq_rx(wil);
162 wil6210_unmask_irq_misc(wil);
165 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
167 struct wil6210_priv *wil = cookie;
168 u32 isr = wil_ioread32_and_clear(wil->csr +
169 HOSTADDR(RGF_DMA_EP_RX_ICR) +
170 offsetof(struct RGF_ICR, ICR));
172 trace_wil6210_irq_rx(isr);
173 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
176 wil_err(wil, "spurious IRQ: RX\n");
180 wil6210_mask_irq_rx(wil);
182 if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
183 wil_dbg_irq(wil, "RX done\n");
184 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
185 wil_dbg_txrx(wil, "NAPI schedule\n");
186 napi_schedule(&wil->napi_rx);
190 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
192 /* Rx IRQ will be enabled when NAPI processing finished */
197 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
199 struct wil6210_priv *wil = cookie;
200 u32 isr = wil_ioread32_and_clear(wil->csr +
201 HOSTADDR(RGF_DMA_EP_TX_ICR) +
202 offsetof(struct RGF_ICR, ICR));
204 trace_wil6210_irq_tx(isr);
205 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
208 wil_err(wil, "spurious IRQ: TX\n");
212 wil6210_mask_irq_tx(wil);
214 if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
215 wil_dbg_irq(wil, "TX done\n");
216 napi_schedule(&wil->napi_tx);
217 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
218 /* clear also all VRING interrupts */
219 isr &= ~(BIT(25) - 1UL);
223 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
225 /* Tx IRQ will be enabled when NAPI processing finished */
230 static void wil_notify_fw_error(struct wil6210_priv *wil)
232 struct device *dev = &wil_to_ndev(wil)->dev;
234 [0] = "SOURCE=wil6210",
235 [1] = "EVENT=FW_ERROR",
238 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
241 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
243 /* make shadow copy of registers that should not change on run time */
244 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
245 sizeof(struct wil6210_mbox_ctl));
246 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
247 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
250 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
252 struct wil6210_priv *wil = cookie;
253 u32 isr = wil_ioread32_and_clear(wil->csr +
254 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
255 offsetof(struct RGF_ICR, ICR));
257 trace_wil6210_irq_misc(isr);
258 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
261 wil_err(wil, "spurious IRQ: MISC\n");
265 wil6210_mask_irq_misc(wil);
267 if (isr & ISR_MISC_FW_ERROR) {
268 wil_err(wil, "Firmware error detected\n");
269 clear_bit(wil_status_fwready, &wil->status);
271 * do not clear @isr here - we do 2-nd part in thread
272 * there, user space get notified, and it should be done
273 * in non-atomic context
277 if (isr & ISR_MISC_FW_READY) {
278 wil_dbg_irq(wil, "IRQ: FW ready\n");
279 wil_cache_mbox_regs(wil);
280 set_bit(wil_status_reset_done, &wil->status);
282 * Actual FW ready indicated by the
283 * WMI_FW_READY_EVENTID
285 isr &= ~ISR_MISC_FW_READY;
291 return IRQ_WAKE_THREAD;
293 wil6210_unmask_irq_misc(wil);
298 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
300 struct wil6210_priv *wil = cookie;
301 u32 isr = wil->isr_misc;
303 trace_wil6210_irq_misc_thread(isr);
304 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
306 if (isr & ISR_MISC_FW_ERROR) {
307 wil_notify_fw_error(wil);
308 isr &= ~ISR_MISC_FW_ERROR;
311 if (isr & ISR_MISC_MBOX_EVT) {
312 wil_dbg_irq(wil, "MBOX event\n");
314 isr &= ~ISR_MISC_MBOX_EVT;
318 wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
322 wil6210_unmask_irq_misc(wil);
330 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
332 struct wil6210_priv *wil = cookie;
334 wil_dbg_irq(wil, "Thread IRQ\n");
335 /* Discover real IRQ cause */
337 wil6210_irq_misc_thread(irq, cookie);
339 wil6210_unmask_irq_pseudo(wil);
345 * There is subtle bug in hardware that causes IRQ to raise when it should be
346 * masked. It is quite rare and hard to debug.
348 * Catch irq issue if it happens and print all I can.
350 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
352 if (!test_bit(wil_status_irqen, &wil->status)) {
353 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
354 HOSTADDR(RGF_DMA_EP_RX_ICR) +
355 offsetof(struct RGF_ICR, ICM));
356 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
357 HOSTADDR(RGF_DMA_EP_RX_ICR) +
358 offsetof(struct RGF_ICR, ICR));
359 u32 imv_rx = ioread32(wil->csr +
360 HOSTADDR(RGF_DMA_EP_RX_ICR) +
361 offsetof(struct RGF_ICR, IMV));
362 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
363 HOSTADDR(RGF_DMA_EP_TX_ICR) +
364 offsetof(struct RGF_ICR, ICM));
365 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
366 HOSTADDR(RGF_DMA_EP_TX_ICR) +
367 offsetof(struct RGF_ICR, ICR));
368 u32 imv_tx = ioread32(wil->csr +
369 HOSTADDR(RGF_DMA_EP_TX_ICR) +
370 offsetof(struct RGF_ICR, IMV));
371 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
372 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
373 offsetof(struct RGF_ICR, ICM));
374 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
375 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
376 offsetof(struct RGF_ICR, ICR));
377 u32 imv_misc = ioread32(wil->csr +
378 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
379 offsetof(struct RGF_ICR, IMV));
380 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
381 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
382 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
383 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
385 icm_rx, icr_rx, imv_rx,
386 icm_tx, icr_tx, imv_tx,
387 icm_misc, icr_misc, imv_misc);
395 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
397 irqreturn_t rc = IRQ_HANDLED;
398 struct wil6210_priv *wil = cookie;
399 u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
402 * pseudo_cause is Clear-On-Read, no need to ACK
404 if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
407 /* FIXME: IRQ mask debug */
408 if (wil6210_debug_irq_mask(wil, pseudo_cause))
411 trace_wil6210_irq_pseudo(pseudo_cause);
412 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
414 wil6210_mask_irq_pseudo(wil);
416 /* Discover real IRQ cause
417 * There are 2 possible phases for every IRQ:
418 * - hard IRQ handler called right here
419 * - threaded handler called later
421 * Hard IRQ handler reads and clears ISR.
423 * If threaded handler requested, hard IRQ handler
424 * returns IRQ_WAKE_THREAD and saves ISR register value
425 * for the threaded handler use.
427 * voting for wake thread - need at least 1 vote
429 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
430 (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
431 rc = IRQ_WAKE_THREAD;
433 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
434 (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
435 rc = IRQ_WAKE_THREAD;
437 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
438 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
439 rc = IRQ_WAKE_THREAD;
441 /* if thread is requested, it will unmask IRQ */
442 if (rc != IRQ_WAKE_THREAD)
443 wil6210_unmask_irq_pseudo(wil);
448 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
452 * IRQ's are in the following order:
458 rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
463 rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
468 rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
469 wil6210_irq_misc_thread,
470 IRQF_SHARED, WIL_NAME"_misc", wil);
477 free_irq(irq + 1, wil);
484 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
488 rc = wil6210_request_3msi(wil, irq);
490 rc = request_threaded_irq(irq, wil6210_hardirq,
492 wil->n_msi ? 0 : IRQF_SHARED,
497 wil6210_enable_irq(wil);
502 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
504 wil6210_disable_irq(wil);
506 if (wil->n_msi == 3) {
507 free_irq(irq + 1, wil);
508 free_irq(irq + 2, wil);