drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "main.h"
  36
  37 struct nphy_txgains {
  38         u16 txgm[2];
  39         u16 pga[2];
  40         u16 pad[2];
  41         u16 ipa[2];
  42 };
  43
  44 struct nphy_iqcal_params {
  45         u16 txgm;
  46         u16 pga;
  47         u16 pad;
  48         u16 ipa;
  49         u16 cal_gain;
  50         u16 ncorr[5];
  51 };
  52
  53 struct nphy_iq_est {
  54         s32 iq0_prod;
  55         u32 i0_pwr;
  56         u32 q0_pwr;
  57         s32 iq1_prod;
  58         u32 i1_pwr;
  59         u32 q1_pwr;
  60 };
  61
  62 enum b43_nphy_rf_sequence {
  63         B43_RFSEQ_RX2TX,
  64         B43_RFSEQ_TX2RX,
  65         B43_RFSEQ_RESET2RX,
  66         B43_RFSEQ_UPDATE_GAINH,
  67         B43_RFSEQ_UPDATE_GAINL,
  68         B43_RFSEQ_UPDATE_GAINU,
  69 };
  70
  71 enum b43_nphy_rssi_type {
  72         B43_NPHY_RSSI_X = 0,
  73         B43_NPHY_RSSI_Y,
  74         B43_NPHY_RSSI_Z,
  75         B43_NPHY_RSSI_PWRDET,
  76         B43_NPHY_RSSI_TSSI_I,
  77         B43_NPHY_RSSI_TSSI_Q,
  78         B43_NPHY_RSSI_TBD,
  79 };
  80
  81 /* TODO: reorder functions */
  82 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
  83                                                 bool enable);
  84 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  85                                         u8 *events, u8 *delays, u8 length);
  86 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  87                                        enum b43_nphy_rf_sequence seq);
  88 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  89                                                 u16 value, u8 core, bool off);
  90 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  91                                                 u16 value, u8 core);
  92 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev);
  93
  94 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  95 {
  96         enum ieee80211_band band = b43_current_band(dev->wl);
  97         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  98                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
  99 }
 100
 101 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
 102 {//TODO
 103 }
 104
 105 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
 106 {//TODO
 107 }
 108
 109 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
 110                                                         bool ignore_tssi)
 111 {//TODO
 112         return B43_TXPWR_RES_DONE;
 113 }
 114
 115 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 116                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 117 {
 118         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 119         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 120         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 121         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 122         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 123
 124         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 125         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 126         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 127         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 128         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 129
 130         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 131         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 132         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 133         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 134         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 135
 136         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 137         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 138         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 139         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 140         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 141
 142         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 143         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 144         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 145         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 146         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 147
 148         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 149         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 150 }
 151
 152 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 153                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 154 {
 155         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 156         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 157         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 158         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 159         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 160         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 161                                         e->radio_syn_pll_loopfilter1);
 162         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 163                                         e->radio_syn_pll_loopfilter2);
 164         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 165                                         e->radio_syn_pll_loopfilter3);
 166         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 167                                         e->radio_syn_pll_loopfilter4);
 168         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 169                                         e->radio_syn_pll_loopfilter5);
 170         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 171                                         e->radio_syn_reserved_addr27);
 172         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 173                                         e->radio_syn_reserved_addr28);
 174         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 175                                         e->radio_syn_reserved_addr29);
 176         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 177                                         e->radio_syn_logen_vcobuf1);
 178         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 179         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 180         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 181
 182         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 183                                         e->radio_rx0_lnaa_tune);
 184         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 185                                         e->radio_rx0_lnag_tune);
 186
 187         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 188                                         e->radio_tx0_intpaa_boost_tune);
 189         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 190                                         e->radio_tx0_intpag_boost_tune);
 191         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 192                                         e->radio_tx0_pada_boost_tune);
 193         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 194                                         e->radio_tx0_padg_boost_tune);
 195         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 196                                         e->radio_tx0_pgaa_boost_tune);
 197         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 198                                         e->radio_tx0_pgag_boost_tune);
 199         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 200                                         e->radio_tx0_mixa_boost_tune);
 201         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 202                                         e->radio_tx0_mixg_boost_tune);
 203
 204         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 205                                         e->radio_rx1_lnaa_tune);
 206         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 207                                         e->radio_rx1_lnag_tune);
 208
 209         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 210                                         e->radio_tx1_intpaa_boost_tune);
 211         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 212                                         e->radio_tx1_intpag_boost_tune);
 213         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 214                                         e->radio_tx1_pada_boost_tune);
 215         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 216                                         e->radio_tx1_padg_boost_tune);
 217         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 218                                         e->radio_tx1_pgaa_boost_tune);
 219         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 220                                         e->radio_tx1_pgag_boost_tune);
 221         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 222                                         e->radio_tx1_mixa_boost_tune);
 223         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 224                                         e->radio_tx1_mixg_boost_tune);
 225 }
 226
 227 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 228 static void b43_radio_2056_setup(struct b43_wldev *dev,
 229                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 230 {
 231         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 232         enum ieee80211_band band = b43_current_band(dev->wl);
 233         u16 offset;
 234         u8 i;
 235         u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
 236
 237         B43_WARN_ON(dev->phy.rev < 3);
 238
 239         b43_chantab_radio_2056_upload(dev, e);
 240         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
 241
 242         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
 243             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 244                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 245                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 246                 if (dev->dev->chip_id == 0x4716) {
 247                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
 248                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
 249                 } else {
 250                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
 251                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
 252                 }
 253         }
 254         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
 255             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 256                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
 257                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
 258                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
 259                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
 260         }
 261
 262         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
 263                 for (i = 0; i < 2; i++) {
 264                         offset = i ? B2056_TX1 : B2056_TX0;
 265                         if (dev->phy.rev >= 5) {
 266                                 b43_radio_write(dev,
 267                                         offset | B2056_TX_PADG_IDAC, 0xcc);
 268
 269                                 if (dev->dev->chip_id == 0x4716) {
 270                                         bias = 0x40;
 271                                         cbias = 0x45;
 272                                         pag_boost = 0x5;
 273                                         pgag_boost = 0x33;
 274                                         mixg_boost = 0x55;
 275                                 } else {
 276                                         bias = 0x25;
 277                                         cbias = 0x20;
 278                                         pag_boost = 0x4;
 279                                         pgag_boost = 0x03;
 280                                         mixg_boost = 0x65;
 281                                 }
 282                                 padg_boost = 0x77;
 283
 284                                 b43_radio_write(dev,
 285                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 286                                         bias);
 287                                 b43_radio_write(dev,
 288                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 289                                         bias);
 290                                 b43_radio_write(dev,
 291                                         offset | B2056_TX_INTPAG_CASCBIAS,
 292                                         cbias);
 293                                 b43_radio_write(dev,
 294                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
 295                                         pag_boost);
 296                                 b43_radio_write(dev,
 297                                         offset | B2056_TX_PGAG_BOOST_TUNE,
 298                                         pgag_boost);
 299                                 b43_radio_write(dev,
 300                                         offset | B2056_TX_PADG_BOOST_TUNE,
 301                                         padg_boost);
 302                                 b43_radio_write(dev,
 303                                         offset | B2056_TX_MIXG_BOOST_TUNE,
 304                                         mixg_boost);
 305                         } else {
 306                                 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
 307                                 b43_radio_write(dev,
 308                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
 309                                         bias);
 310                                 b43_radio_write(dev,
 311                                         offset | B2056_TX_INTPAG_IAUX_STAT,
 312                                         bias);
 313                                 b43_radio_write(dev,
 314                                         offset | B2056_TX_INTPAG_CASCBIAS,
 315                                         0x30);
 316                         }
 317                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
 318                 }
 319         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
 320                 /* TODO */
 321         }
 322
 323         udelay(50);
 324         /* VCO calibration */
 325         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 326         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 327         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 328         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 329         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 330         udelay(300);
 331 }
 332
 333 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 334                                    const struct b43_phy_n_sfo_cfg *e)
 335 {
 336         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 337         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 338         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 339         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 340         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 341         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 342 }
 343
 344 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
 345 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
 346 {
 347         struct b43_phy_n *nphy = dev->phy.n;
 348         u8 i;
 349         u16 bmask, val, tmp;
 350         enum ieee80211_band band = b43_current_band(dev->wl);
 351
 352         if (nphy->hang_avoid)
 353                 b43_nphy_stay_in_carrier_search(dev, 1);
 354
 355         nphy->txpwrctrl = enable;
 356         if (!enable) {
 357                 if (dev->phy.rev >= 3 &&
 358                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
 359                      (B43_NPHY_TXPCTL_CMD_COEFF |
 360                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
 361                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
 362                         /* We disable enabled TX pwr ctl, save it's state */
 363                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
 364                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
 365                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
 366                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
 367                 }
 368
 369                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
 370                 for (i = 0; i < 84; i++)
 371                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 372
 373                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
 374                 for (i = 0; i < 84; i++)
 375                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 376
 377                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 378                 if (dev->phy.rev >= 3)
 379                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 380                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
 381
 382                 if (dev->phy.rev >= 3) {
 383                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 384                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 385                 } else {
 386                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 387                 }
 388
 389                 if (dev->phy.rev == 2)
 390                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 391                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
 392                 else if (dev->phy.rev < 2)
 393                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 394                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
 395
 396                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
 397                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
 398         } else {
 399                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
 400                                     nphy->adj_pwr_tbl);
 401                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
 402                                     nphy->adj_pwr_tbl);
 403
 404                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
 405                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 406                 /* wl does useless check for "enable" param here */
 407                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 408                 if (dev->phy.rev >= 3) {
 409                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 410                         if (val)
 411                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 412                 }
 413                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
 414
 415                 if (band == IEEE80211_BAND_5GHZ) {
 416                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
 417                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
 418                         if (dev->phy.rev > 1)
 419                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
 420                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
 421                                                 0x64);
 422                 }
 423
 424                 if (dev->phy.rev >= 3) {
 425                         if (nphy->tx_pwr_idx[0] != 128 &&
 426                             nphy->tx_pwr_idx[1] != 128) {
 427                                 /* Recover TX pwr ctl state */
 428                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
 429                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
 430                                                 nphy->tx_pwr_idx[0]);
 431                                 if (dev->phy.rev > 1)
 432                                         b43_phy_maskset(dev,
 433                                                 B43_NPHY_TXPCTL_INIT,
 434                                                 ~0xff, nphy->tx_pwr_idx[1]);
 435                         }
 436                 }
 437
 438                 if (dev->phy.rev >= 3) {
 439                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
 440                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
 441                 } else {
 442                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
 443                 }
 444
 445                 if (dev->phy.rev == 2)
 446                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
 447                 else if (dev->phy.rev < 2)
 448                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
 449
 450                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
 451                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
 452
 453                 if (b43_nphy_ipa(dev)) {
 454                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
 455                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
 456                 }
 457         }
 458
 459         if (nphy->hang_avoid)
 460                 b43_nphy_stay_in_carrier_search(dev, 0);
 461 }
 462
 463 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
 464 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 465 {
 466         struct b43_phy_n *nphy = dev->phy.n;
 467         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 468
 469         u8 txpi[2], bbmult, i;
 470         u16 tmp, radio_gain, dac_gain;
 471         u16 freq = dev->phy.channel_freq;
 472         u32 txgain;
 473         /* u32 gaintbl; rev3+ */
 474
 475         if (nphy->hang_avoid)
 476                 b43_nphy_stay_in_carrier_search(dev, 1);
 477
 478         if (dev->phy.rev >= 7) {
 479                 txpi[0] = txpi[1] = 30;
 480         } else if (dev->phy.rev >= 3) {
 481                 txpi[0] = 40;
 482                 txpi[1] = 40;
 483         } else if (sprom->revision < 4) {
 484                 txpi[0] = 72;
 485                 txpi[1] = 72;
 486         } else {
 487                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 488                         txpi[0] = sprom->txpid2g[0];
 489                         txpi[1] = sprom->txpid2g[1];
 490                 } else if (freq >= 4900 && freq < 5100) {
 491                         txpi[0] = sprom->txpid5gl[0];
 492                         txpi[1] = sprom->txpid5gl[1];
 493                 } else if (freq >= 5100 && freq < 5500) {
 494                         txpi[0] = sprom->txpid5g[0];
 495                         txpi[1] = sprom->txpid5g[1];
 496                 } else if (freq >= 5500) {
 497                         txpi[0] = sprom->txpid5gh[0];
 498                         txpi[1] = sprom->txpid5gh[1];
 499                 } else {
 500                         txpi[0] = 91;
 501                         txpi[1] = 91;
 502                 }
 503         }
 504         if (dev->phy.rev < 7 &&
 505             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
 506                 txpi[0] = txpi[1] = 91;
 507
 508         /*
 509         for (i = 0; i < 2; i++) {
 510                 nphy->txpwrindex[i].index_internal = txpi[i];
 511                 nphy->txpwrindex[i].index_internal_save = txpi[i];
 512         }
 513         */
 514
 515         for (i = 0; i < 2; i++) {
 516                 if (dev->phy.rev >= 3) {
 517                         if (b43_nphy_ipa(dev)) {
 518                                 txgain = *(b43_nphy_get_ipa_gain_table(dev) +
 519                                                 txpi[i]);
 520                         } else if (b43_current_band(dev->wl) ==
 521                                    IEEE80211_BAND_5GHZ) {
 522                                 /* FIXME: use 5GHz tables */
 523                                 txgain =
 524                                         b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
 525                         } else {
 526                                 if (dev->phy.rev >= 5 &&
 527                                     sprom->fem.ghz5.extpa_gain == 3)
 528                                         ; /* FIXME: 5GHz_txgain_HiPwrEPA */
 529                                 txgain =
 530                                         b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
 531                         }
 532                         radio_gain = (txgain >> 16) & 0x1FFFF;
 533                 } else {
 534                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
 535                         radio_gain = (txgain >> 16) & 0x1FFF;
 536                 }
 537
 538                 if (dev->phy.rev >= 7)
 539                         dac_gain = (txgain >> 8) & 0x7;
 540                 else
 541                         dac_gain = (txgain >> 8) & 0x3F;
 542                 bbmult = txgain & 0xFF;
 543
 544                 if (dev->phy.rev >= 3) {
 545                         if (i == 0)
 546                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 547                         else
 548                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 549                 } else {
 550                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 551                 }
 552
 553                 if (i == 0)
 554                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
 555                 else
 556                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
 557
 558                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
 559
 560                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
 561                 if (i == 0)
 562                         tmp = (tmp & 0x00FF) | (bbmult << 8);
 563                 else
 564                         tmp = (tmp & 0xFF00) | bbmult;
 565                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
 566
 567                 if (b43_nphy_ipa(dev)) {
 568                         u32 tmp32;
 569                         u16 reg = (i == 0) ?
 570                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
 571                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
 572                                                               576 + txpi[i]));
 573                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
 574                         b43_phy_set(dev, reg, 0x4);
 575                 }
 576         }
 577
 578         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
 579
 580         if (nphy->hang_avoid)
 581                 b43_nphy_stay_in_carrier_search(dev, 0);
 582 }
 583
 584 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
 585 {
 586         struct b43_phy *phy = &dev->phy;
 587
 588         const u32 *table = NULL;
 589 #if 0
 590         TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
 591         u32 rfpwr_offset;
 592         u8 pga_gain;
 593         int i;
 594 #endif
 595
 596         if (phy->rev >= 3) {
 597                 if (b43_nphy_ipa(dev)) {
 598                         table = b43_nphy_get_ipa_gain_table(dev);
 599                 } else {
 600                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 601                                 if (phy->rev == 3)
 602                                         table = b43_ntab_tx_gain_rev3_5ghz;
 603                                 if (phy->rev == 4)
 604                                         table = b43_ntab_tx_gain_rev4_5ghz;
 605                                 else
 606                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
 607                         } else {
 608                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
 609                         }
 610                 }
 611         } else {
 612                 table = b43_ntab_tx_gain_rev0_1_2;
 613         }
 614         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
 615         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
 616
 617         if (phy->rev >= 3) {
 618 #if 0
 619                 nphy->gmval = (table[0] >> 16) & 0x7000;
 620
 621                 for (i = 0; i < 128; i++) {
 622                         pga_gain = (table[i] >> 24) & 0xF;
 623                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 624                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
 625                         else
 626                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
 627                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
 628                                        rfpwr_offset);
 629                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
 630                                        rfpwr_offset);
 631                 }
 632 #endif
 633         }
 634 }
 635
 636 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 637 static void b43_radio_2055_setup(struct b43_wldev *dev,
 638                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 639 {
 640         B43_WARN_ON(dev->phy.rev >= 3);
 641
 642         b43_chantab_radio_upload(dev, e);
 643         udelay(50);
 644         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 645         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 646         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 647         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 648         udelay(300);
 649 }
 650
 651 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 652 {
 653         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 654                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 655         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 656                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 657                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 658         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 659                     B43_NPHY_RFCTL_CMD_PORFORCE);
 660 }
 661
 662 static void b43_radio_init2055_post(struct b43_wldev *dev)
 663 {
 664         struct b43_phy_n *nphy = dev->phy.n;
 665         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 666         int i;
 667         u16 val;
 668         bool workaround = false;
 669
 670         if (sprom->revision < 4)
 671                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
 672                               && dev->dev->board_type == 0x46D
 673                               && dev->dev->board_rev >= 0x41);
 674         else
 675                 workaround =
 676                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 677
 678         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 679         if (workaround) {
 680                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 681                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 682         }
 683         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 684         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 685         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 686         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 687         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 688         msleep(1);
 689         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 690         for (i = 0; i < 200; i++) {
 691                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 692                 if (val & 0x80) {
 693                         i = 0;
 694                         break;
 695                 }
 696                 udelay(10);
 697         }
 698         if (i)
 699                 b43err(dev->wl, "radio post init timeout\n");
 700         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 701         b43_switch_channel(dev, dev->phy.channel);
 702         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 703         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 704         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 705         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 706         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 707         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 708         if (!nphy->gain_boost) {
 709                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 710                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 711         } else {
 712                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 713                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 714         }
 715         udelay(2);
 716 }
 717
 718 /*
 719  * Initialize a Broadcom 2055 N-radio
 720  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 721  */
 722 static void b43_radio_init2055(struct b43_wldev *dev)
 723 {
 724         b43_radio_init2055_pre(dev);
 725         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 726                 /* Follow wl, not specs. Do not force uploading all regs */
 727                 b2055_upload_inittab(dev, 0, 0);
 728         } else {
 729                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 730                 b2055_upload_inittab(dev, ghz5, 0);
 731         }
 732         b43_radio_init2055_post(dev);
 733 }
 734
 735 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 736 {
 737         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 738                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 739         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 740         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 741                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 742         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 743                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 744         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 745                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 746 }
 747
 748 static void b43_radio_init2056_post(struct b43_wldev *dev)
 749 {
 750         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 751         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 752         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 753         msleep(1);
 754         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 755         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 756         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 757         /*
 758         if (nphy->init_por)
 759                 Call Radio 2056 Recalibrate
 760         */
 761 }
 762
 763 /*
 764  * Initialize a Broadcom 2056 N-radio
 765  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 766  */
 767 static void b43_radio_init2056(struct b43_wldev *dev)
 768 {
 769         b43_radio_init2056_pre(dev);
 770         b2056_upload_inittabs(dev, 0, 0);
 771         b43_radio_init2056_post(dev);
 772 }
 773
 774 /*
 775  * Upload the N-PHY tables.
 776  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 777  */
 778 static void b43_nphy_tables_init(struct b43_wldev *dev)
 779 {
 780         if (dev->phy.rev < 3)
 781                 b43_nphy_rev0_1_2_tables_init(dev);
 782         else
 783                 b43_nphy_rev3plus_tables_init(dev);
 784 }
 785
 786 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 787 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 788 {
 789         struct b43_phy_n *nphy = dev->phy.n;
 790         enum ieee80211_band band;
 791         u16 tmp;
 792
 793         if (!enable) {
 794                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 795                                                        B43_NPHY_RFCTL_INTC1);
 796                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 797                                                        B43_NPHY_RFCTL_INTC2);
 798                 band = b43_current_band(dev->wl);
 799                 if (dev->phy.rev >= 3) {
 800                         if (band == IEEE80211_BAND_5GHZ)
 801                                 tmp = 0x600;
 802                         else
 803                                 tmp = 0x480;
 804                 } else {
 805                         if (band == IEEE80211_BAND_5GHZ)
 806                                 tmp = 0x180;
 807                         else
 808                                 tmp = 0x120;
 809                 }
 810                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 811                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 812         } else {
 813                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 814                                 nphy->rfctrl_intc1_save);
 815                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 816                                 nphy->rfctrl_intc2_save);
 817         }
 818 }
 819
 820 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 821 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 822 {
 823         u16 tmp;
 824
 825         if (dev->phy.rev >= 3) {
 826                 if (b43_nphy_ipa(dev)) {
 827                         tmp = 4;
 828                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 829                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 830                 }
 831
 832                 tmp = 1;
 833                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 834                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 835         }
 836 }
 837
 838 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 839 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 840 {
 841         u16 bbcfg;
 842
 843         b43_phy_force_clock(dev, 1);
 844         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 845         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 846         udelay(1);
 847         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 848         b43_phy_force_clock(dev, 0);
 849         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 850 }
 851
 852 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 853 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 854 {
 855         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 856
 857         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 858         if (preamble == 1)
 859                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 860         else
 861                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 862
 863         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 864 }
 865
 866 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 867 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 868 {
 869         struct b43_phy_n *nphy = dev->phy.n;
 870
 871         bool override = false;
 872         u16 chain = 0x33;
 873
 874         if (nphy->txrx_chain == 0) {
 875                 chain = 0x11;
 876                 override = true;
 877         } else if (nphy->txrx_chain == 1) {
 878                 chain = 0x22;
 879                 override = true;
 880         }
 881
 882         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 883                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 884                         chain);
 885
 886         if (override)
 887                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 888                                 B43_NPHY_RFSEQMODE_CAOVER);
 889         else
 890                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 891                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 892 }
 893
 894 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 895 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 896                                 u16 samps, u8 time, bool wait)
 897 {
 898         int i;
 899         u16 tmp;
 900
 901         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 902         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 903         if (wait)
 904                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 905         else
 906                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 907
 908         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 909
 910         for (i = 1000; i; i--) {
 911                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 912                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 913                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 914                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 915                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 916                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 917                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 918                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 919
 920                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 921                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 922                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 923                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 924                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 925                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 926                         return;
 927                 }
 928                 udelay(10);
 929         }
 930         memset(est, 0, sizeof(*est));
 931 }
 932
 933 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 934 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 935                                         struct b43_phy_n_iq_comp *pcomp)
 936 {
 937         if (write) {
 938                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 939                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 940                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 941                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 942         } else {
 943                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 944                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 945                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 946                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 947         }
 948 }
 949
 950 #if 0
 951 /* Ready but not used anywhere */
 952 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 953 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 954 {
 955         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 956
 957         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 958         if (core == 0) {
 959                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 960                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 961         } else {
 962                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 963                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 964         }
 965         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 966         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 967         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 968         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 969         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 970         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 971         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 972         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 973 }
 974
 975 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 976 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 977 {
 978         u8 rxval, txval;
 979         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 980
 981         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 982         if (core == 0) {
 983                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 984                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 985         } else {
 986                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 987                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 988         }
 989         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 990         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 991         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 992         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 993         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 994         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 995         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 996         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 997
 998         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 999         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1000
1001         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
1002                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
1003                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
1004         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
1005                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
1006         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
1007                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
1008         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
1009                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
1010
1011         if (core == 0) {
1012                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
1013                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
1014         } else {
1015                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
1016                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
1017         }
1018
1019         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
1020         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
1021         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1022
1023         if (core == 0) {
1024                 rxval = 1;
1025                 txval = 8;
1026         } else {
1027                 rxval = 4;
1028                 txval = 2;
1029         }
1030         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
1031         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
1032 }
1033 #endif
1034
1035 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
1036 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
1037 {
1038         int i;
1039         s32 iq;
1040         u32 ii;
1041         u32 qq;
1042         int iq_nbits, qq_nbits;
1043         int arsh, brsh;
1044         u16 tmp, a, b;
1045
1046         struct nphy_iq_est est;
1047         struct b43_phy_n_iq_comp old;
1048         struct b43_phy_n_iq_comp new = { };
1049         bool error = false;
1050
1051         if (mask == 0)
1052                 return;
1053
1054         b43_nphy_rx_iq_coeffs(dev, false, &old);
1055         b43_nphy_rx_iq_coeffs(dev, true, &new);
1056         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
1057         new = old;
1058
1059         for (i = 0; i < 2; i++) {
1060                 if (i == 0 && (mask & 1)) {
1061                         iq = est.iq0_prod;
1062                         ii = est.i0_pwr;
1063                         qq = est.q0_pwr;
1064                 } else if (i == 1 && (mask & 2)) {
1065                         iq = est.iq1_prod;
1066                         ii = est.i1_pwr;
1067                         qq = est.q1_pwr;
1068                 } else {
1069                         continue;
1070                 }
1071
1072                 if (ii + qq < 2) {
1073                         error = true;
1074                         break;
1075                 }
1076
1077                 iq_nbits = fls(abs(iq));
1078                 qq_nbits = fls(qq);
1079
1080                 arsh = iq_nbits - 20;
1081                 if (arsh >= 0) {
1082                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
1083                         tmp = ii >> arsh;
1084                 } else {
1085                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
1086                         tmp = ii << -arsh;
1087                 }
1088                 if (tmp == 0) {
1089                         error = true;
1090                         break;
1091                 }
1092                 a /= tmp;
1093
1094                 brsh = qq_nbits - 11;
1095                 if (brsh >= 0) {
1096                         b = (qq << (31 - qq_nbits));
1097                         tmp = ii >> brsh;
1098                 } else {
1099                         b = (qq << (31 - qq_nbits));
1100                         tmp = ii << -brsh;
1101                 }
1102                 if (tmp == 0) {
1103                         error = true;
1104                         break;
1105                 }
1106                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
1107
1108                 if (i == 0 && (mask & 0x1)) {
1109                         if (dev->phy.rev >= 3) {
1110                                 new.a0 = a & 0x3FF;
1111                                 new.b0 = b & 0x3FF;
1112                         } else {
1113                                 new.a0 = b & 0x3FF;
1114                                 new.b0 = a & 0x3FF;
1115                         }
1116                 } else if (i == 1 && (mask & 0x2)) {
1117                         if (dev->phy.rev >= 3) {
1118                                 new.a1 = a & 0x3FF;
1119                                 new.b1 = b & 0x3FF;
1120                         } else {
1121                                 new.a1 = b & 0x3FF;
1122                                 new.b1 = a & 0x3FF;
1123                         }
1124                 }
1125         }
1126
1127         if (error)
1128                 new = old;
1129
1130         b43_nphy_rx_iq_coeffs(dev, true, &new);
1131 }
1132
1133 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
1134 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
1135 {
1136         u16 array[4];
1137         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
1138
1139         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
1140         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
1141         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
1142         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
1143 }
1144
1145 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
1146 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
1147                                           const u16 *clip_st)
1148 {
1149         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
1150         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
1151 }
1152
1153 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
1154 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
1155 {
1156         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
1157         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
1158 }
1159
1160 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
1161 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
1162 {
1163         if (dev->phy.rev >= 3) {
1164                 if (!init)
1165                         return;
1166                 if (0 /* FIXME */) {
1167                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
1168                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1169                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1170                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1171                 }
1172         } else {
1173                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1174                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1175
1176                 switch (dev->dev->bus_type) {
1177 #ifdef CONFIG_B43_BCMA
1178                 case B43_BUS_BCMA:
1179                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1180                                                  0xFC00, 0xFC00);
1181                         break;
1182 #endif
1183 #ifdef CONFIG_B43_SSB
1184                 case B43_BUS_SSB:
1185                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1186                                                 0xFC00, 0xFC00);
1187                         break;
1188 #endif
1189                 }
1190
1191                 b43_write32(dev, B43_MMIO_MACCTL,
1192                         b43_read32(dev, B43_MMIO_MACCTL) &
1193                         ~B43_MACCTL_GPOUTSMSK);
1194                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1195                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1196                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1197                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1198
1199                 if (init) {
1200                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1201                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1202                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1203                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1204                 }
1205         }
1206 }
1207
1208 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
1209 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
1210 {
1211         u16 tmp;
1212
1213         if (dev->dev->core_rev == 16)
1214                 b43_mac_suspend(dev);
1215
1216         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
1217         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
1218                 B43_NPHY_CLASSCTL_WAITEDEN);
1219         tmp &= ~mask;
1220         tmp |= (val & mask);
1221         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
1222
1223         if (dev->dev->core_rev == 16)
1224                 b43_mac_enable(dev);
1225
1226         return tmp;
1227 }
1228
1229 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1230 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1231 {
1232         struct b43_phy *phy = &dev->phy;
1233         struct b43_phy_n *nphy = phy->n;
1234
1235         if (enable) {
1236                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1237                 if (nphy->deaf_count++ == 0) {
1238                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1239                         b43_nphy_classifier(dev, 0x7, 0);
1240                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
1241                         b43_nphy_write_clip_detection(dev, clip);
1242                 }
1243                 b43_nphy_reset_cca(dev);
1244         } else {
1245                 if (--nphy->deaf_count == 0) {
1246                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1247                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
1248                 }
1249         }
1250 }
1251
1252 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1253 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1254 {
1255         struct b43_phy_n *nphy = dev->phy.n;
1256         u16 tmp;
1257
1258         if (nphy->hang_avoid)
1259                 b43_nphy_stay_in_carrier_search(dev, 1);
1260
1261         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1262         if (tmp & 0x1)
1263                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1264         else if (tmp & 0x2)
1265                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1266
1267         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1268
1269         if (nphy->bb_mult_save & 0x80000000) {
1270                 tmp = nphy->bb_mult_save & 0xFFFF;
1271                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1272                 nphy->bb_mult_save = 0;
1273         }
1274
1275         if (nphy->hang_avoid)
1276                 b43_nphy_stay_in_carrier_search(dev, 0);
1277 }
1278
1279 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1280 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1281 {
1282         struct b43_phy_n *nphy = dev->phy.n;
1283
1284         u8 channel = dev->phy.channel;
1285         int tone[2] = { 57, 58 };
1286         u32 noise[2] = { 0x3FF, 0x3FF };
1287
1288         B43_WARN_ON(dev->phy.rev < 3);
1289
1290         if (nphy->hang_avoid)
1291                 b43_nphy_stay_in_carrier_search(dev, 1);
1292
1293         if (nphy->gband_spurwar_en) {
1294                 /* TODO: N PHY Adjust Analog Pfbw (7) */
1295                 if (channel == 11 && dev->phy.is_40mhz)
1296                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1297                 else
1298                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1299                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1300         }
1301
1302         if (nphy->aband_spurwar_en) {
1303                 if (channel == 54) {
1304                         tone[0] = 0x20;
1305                         noise[0] = 0x25F;
1306                 } else if (channel == 38 || channel == 102 || channel == 118) {
1307                         if (0 /* FIXME */) {
1308                                 tone[0] = 0x20;
1309                                 noise[0] = 0x21F;
1310                         } else {
1311                                 tone[0] = 0;
1312                                 noise[0] = 0;
1313                         }
1314                 } else if (channel == 134) {
1315                         tone[0] = 0x20;
1316                         noise[0] = 0x21F;
1317                 } else if (channel == 151) {
1318                         tone[0] = 0x10;
1319                         noise[0] = 0x23F;
1320                 } else if (channel == 153 || channel == 161) {
1321                         tone[0] = 0x30;
1322                         noise[0] = 0x23F;
1323                 } else {
1324                         tone[0] = 0;
1325                         noise[0] = 0;
1326                 }
1327
1328                 if (!tone[0] && !noise[0])
1329                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1330                 else
1331                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1332         }
1333
1334         if (nphy->hang_avoid)
1335                 b43_nphy_stay_in_carrier_search(dev, 0);
1336 }
1337
1338 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1339 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1340 {
1341         struct b43_phy_n *nphy = dev->phy.n;
1342
1343         u8 i;
1344         s16 tmp;
1345         u16 data[4];
1346         s16 gain[2];
1347         u16 minmax[2];
1348         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1349
1350         if (nphy->hang_avoid)
1351                 b43_nphy_stay_in_carrier_search(dev, 1);
1352
1353         if (nphy->gain_boost) {
1354                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1355                         gain[0] = 6;
1356                         gain[1] = 6;
1357                 } else {
1358                         tmp = 40370 - 315 * dev->phy.channel;
1359                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1360                         tmp = 23242 - 224 * dev->phy.channel;
1361                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1362                 }
1363         } else {
1364                 gain[0] = 0;
1365                 gain[1] = 0;
1366         }
1367
1368         for (i = 0; i < 2; i++) {
1369                 if (nphy->elna_gain_config) {
1370                         data[0] = 19 + gain[i];
1371                         data[1] = 25 + gain[i];
1372                         data[2] = 25 + gain[i];
1373                         data[3] = 25 + gain[i];
1374                 } else {
1375                         data[0] = lna_gain[0] + gain[i];
1376                         data[1] = lna_gain[1] + gain[i];
1377                         data[2] = lna_gain[2] + gain[i];
1378                         data[3] = lna_gain[3] + gain[i];
1379                 }
1380                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1381
1382                 minmax[i] = 23 + gain[i];
1383         }
1384
1385         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1386                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1387         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1388                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1389
1390         if (nphy->hang_avoid)
1391                 b43_nphy_stay_in_carrier_search(dev, 0);
1392 }
1393
1394 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1395 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1396 {
1397         struct b43_phy_n *nphy = dev->phy.n;
1398         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1399
1400         /* PHY rev 0, 1, 2 */
1401         u8 i, j;
1402         u8 code;
1403         u16 tmp;
1404         u8 rfseq_events[3] = { 6, 8, 7 };
1405         u8 rfseq_delays[3] = { 10, 30, 1 };
1406
1407         /* PHY rev >= 3 */
1408         bool ghz5;
1409         bool ext_lna;
1410         u16 rssi_gain;
1411         struct nphy_gain_ctl_workaround_entry *e;
1412         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1413         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1414
1415         if (dev->phy.rev >= 3) {
1416                 /* Prepare values */
1417                 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1418                         & B43_NPHY_BANDCTL_5GHZ;
1419                 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1420                 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1421                 if (ghz5 && dev->phy.rev >= 5)
1422                         rssi_gain = 0x90;
1423                 else
1424                         rssi_gain = 0x50;
1425
1426                 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1427
1428                 /* Set Clip 2 detect */
1429                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1430                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1431                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1432                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1433
1434                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1435                                 0x17);
1436                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1437                                 0x17);
1438                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1439                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1440                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1441                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1442                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1443                                 rssi_gain);
1444                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1445                                 rssi_gain);
1446                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1447                                 0x17);
1448                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1449                                 0x17);
1450                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1451                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1452
1453                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1454                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1455                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1456                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1457                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1458                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1459                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1460                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1461                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1462                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1463                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1464                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1465
1466                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1467                 b43_phy_write(dev, 0x2A7, e->init_gain);
1468                 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1469                                         e->rfseq_init);
1470                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1471
1472                 /* TODO: check defines. Do not match variables names */
1473                 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1474                 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1475                 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1476                 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1477                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1478                 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1479
1480                 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1481                 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1482                 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1483                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1484                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1485                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1486                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1487                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1488                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1489                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1490         } else {
1491                 /* Set Clip 2 detect */
1492                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1493                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1494                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1495                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1496
1497                 /* Set narrowband clip threshold */
1498                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1499                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1500
1501                 if (!dev->phy.is_40mhz) {
1502                         /* Set dwell lengths */
1503                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1504                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1505                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1506                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1507                 }
1508
1509                 /* Set wideband clip 2 threshold */
1510                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1511                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1512                                 21);
1513                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1514                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1515                                 21);
1516
1517                 if (!dev->phy.is_40mhz) {
1518                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1519                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1520                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1521                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1522                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1523                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1524                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1525                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1526                 }
1527
1528                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1529
1530                 if (nphy->gain_boost) {
1531                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1532                             dev->phy.is_40mhz)
1533                                 code = 4;
1534                         else
1535                                 code = 5;
1536                 } else {
1537                         code = dev->phy.is_40mhz ? 6 : 7;
1538                 }
1539
1540                 /* Set HPVGA2 index */
1541                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1542                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1543                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1544                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1545                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1546                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1547
1548                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1549                 /* specs say about 2 loops, but wl does 4 */
1550                 for (i = 0; i < 4; i++)
1551                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1552                                                         (code << 8 | 0x7C));
1553
1554                 b43_nphy_adjust_lna_gain_table(dev);
1555
1556                 if (nphy->elna_gain_config) {
1557                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1558                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1559                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1560                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1561                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1562
1563                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1564                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1565                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1566                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1567                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1568
1569                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1570                         /* specs say about 2 loops, but wl does 4 */
1571                         for (i = 0; i < 4; i++)
1572                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1573                                                         (code << 8 | 0x74));
1574                 }
1575
1576                 if (dev->phy.rev == 2) {
1577                         for (i = 0; i < 4; i++) {
1578                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1579                                                 (0x0400 * i) + 0x0020);
1580                                 for (j = 0; j < 21; j++) {
1581                                         tmp = j * (i < 2 ? 3 : 1);
1582                                         b43_phy_write(dev,
1583                                                 B43_NPHY_TABLE_DATALO, tmp);
1584                                 }
1585                         }
1586                 }
1587
1588                 b43_nphy_set_rf_sequence(dev, 5,
1589                                 rfseq_events, rfseq_delays, 3);
1590                 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1591                         ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1592                         0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1593
1594                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1595                         b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1596                                         0xFF80, 4);
1597         }
1598 }
1599
1600 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1601 {
1602         struct b43_phy_n *nphy = dev->phy.n;
1603         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1604
1605         /* TX to RX */
1606         u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1607         u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
1608         /* RX to TX */
1609         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1610                                         0x1F };
1611         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
1612         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
1613         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
1614
1615         u16 tmp16;
1616         u32 tmp32;
1617
1618         b43_phy_write(dev, 0x23f, 0x1f8);
1619         b43_phy_write(dev, 0x240, 0x1f8);
1620
1621         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1622         tmp32 &= 0xffffff;
1623         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1624
1625         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1626         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1627         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1628         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1629         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1630         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1631
1632         b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1633         b43_phy_write(dev, 0x2AE, 0x000C);
1634
1635         /* TX to RX */
1636         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
1637                                  ARRAY_SIZE(tx2rx_events));
1638
1639         /* RX to TX */
1640         if (b43_nphy_ipa(dev))
1641                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
1642                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
1643         if (nphy->hw_phyrxchain != 3 &&
1644             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
1645                 if (b43_nphy_ipa(dev)) {
1646                         rx2tx_delays[5] = 59;
1647                         rx2tx_delays[6] = 1;
1648                         rx2tx_events[7] = 0x1F;
1649                 }
1650                 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
1651                                          ARRAY_SIZE(rx2tx_events));
1652         }
1653
1654         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1655                 0x2 : 0x9C40;
1656         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1657
1658         b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1659
1660         b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1661         b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1662
1663         b43_nphy_gain_ctrl_workarounds(dev);
1664
1665         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
1666         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
1667
1668         /* TODO */
1669
1670         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1671         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1672         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1673         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1674         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1675         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1676         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1677         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1678         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1679         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1680         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1681         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1682
1683         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1684
1685         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1686              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1687             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1688              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1689                 tmp32 = 0x00088888;
1690         else
1691                 tmp32 = 0x88888888;
1692         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1693         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1694         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1695
1696         if (dev->phy.rev == 4 &&
1697                 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1698                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1699                                 0x70);
1700                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1701                                 0x70);
1702         }
1703
1704         b43_phy_write(dev, 0x224, 0x03eb);
1705         b43_phy_write(dev, 0x225, 0x03eb);
1706         b43_phy_write(dev, 0x226, 0x0341);
1707         b43_phy_write(dev, 0x227, 0x0341);
1708         b43_phy_write(dev, 0x228, 0x042b);
1709         b43_phy_write(dev, 0x229, 0x042b);
1710         b43_phy_write(dev, 0x22a, 0x0381);
1711         b43_phy_write(dev, 0x22b, 0x0381);
1712         b43_phy_write(dev, 0x22c, 0x042b);
1713         b43_phy_write(dev, 0x22d, 0x042b);
1714         b43_phy_write(dev, 0x22e, 0x0381);
1715         b43_phy_write(dev, 0x22f, 0x0381);
1716 }
1717
1718 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1719 {
1720         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1721         struct b43_phy *phy = &dev->phy;
1722         struct b43_phy_n *nphy = phy->n;
1723
1724         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1725         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1726
1727         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1728         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1729
1730         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1731             nphy->band5g_pwrgain) {
1732                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1733                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1734         } else {
1735                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1736                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1737         }
1738
1739         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1740         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1741         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1742         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1743
1744         if (dev->phy.rev < 2) {
1745                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1746                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1747                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1748                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1749                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1750                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1751         }
1752
1753         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1754         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1755         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1756         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1757
1758         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
1759             dev->dev->board_type == 0x8B) {
1760                 delays1[0] = 0x1;
1761                 delays1[5] = 0x14;
1762         }
1763         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1764         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1765
1766         b43_nphy_gain_ctrl_workarounds(dev);
1767
1768         if (dev->phy.rev < 2) {
1769                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1770                         b43_hf_write(dev, b43_hf_read(dev) |
1771                                         B43_HF_MLADVW);
1772         } else if (dev->phy.rev == 2) {
1773                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1774                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1775         }
1776
1777         if (dev->phy.rev < 2)
1778                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1779                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1780
1781         /* Set phase track alpha and beta */
1782         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1783         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1784         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1785         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1786         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1787         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1788
1789         b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1790                         ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1791         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1792         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1793         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1794
1795         if (dev->phy.rev == 2)
1796                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1797                                 B43_NPHY_FINERX2_CGC_DECGC);
1798 }
1799
1800 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1801 static void b43_nphy_workarounds(struct b43_wldev *dev)
1802 {
1803         struct b43_phy *phy = &dev->phy;
1804         struct b43_phy_n *nphy = phy->n;
1805
1806         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1807                 b43_nphy_classifier(dev, 1, 0);
1808         else
1809                 b43_nphy_classifier(dev, 1, 1);
1810
1811         if (nphy->hang_avoid)
1812                 b43_nphy_stay_in_carrier_search(dev, 1);
1813
1814         b43_phy_set(dev, B43_NPHY_IQFLIP,
1815                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1816
1817         if (dev->phy.rev >= 3)
1818                 b43_nphy_workarounds_rev3plus(dev);
1819         else
1820                 b43_nphy_workarounds_rev1_2(dev);
1821
1822         if (nphy->hang_avoid)
1823                 b43_nphy_stay_in_carrier_search(dev, 0);
1824 }
1825
1826 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1827 static int b43_nphy_load_samples(struct b43_wldev *dev,
1828                                         struct b43_c32 *samples, u16 len) {
1829         struct b43_phy_n *nphy = dev->phy.n;
1830         u16 i;
1831         u32 *data;
1832
1833         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1834         if (!data) {
1835                 b43err(dev->wl, "allocation for samples loading failed\n");
1836                 return -ENOMEM;
1837         }
1838         if (nphy->hang_avoid)
1839                 b43_nphy_stay_in_carrier_search(dev, 1);
1840
1841         for (i = 0; i < len; i++) {
1842                 data[i] = (samples[i].i & 0x3FF << 10);
1843                 data[i] |= samples[i].q & 0x3FF;
1844         }
1845         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1846
1847         kfree(data);
1848         if (nphy->hang_avoid)
1849                 b43_nphy_stay_in_carrier_search(dev, 0);
1850         return 0;
1851 }
1852
1853 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1854 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1855                                         bool test)
1856 {
1857         int i;
1858         u16 bw, len, rot, angle;
1859         struct b43_c32 *samples;
1860
1861
1862         bw = (dev->phy.is_40mhz) ? 40 : 20;
1863         len = bw << 3;
1864
1865         if (test) {
1866                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1867                         bw = 82;
1868                 else
1869                         bw = 80;
1870
1871                 if (dev->phy.is_40mhz)
1872                         bw <<= 1;
1873
1874                 len = bw << 1;
1875         }
1876
1877         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1878         if (!samples) {
1879                 b43err(dev->wl, "allocation for samples generation failed\n");
1880                 return 0;
1881         }
1882         rot = (((freq * 36) / bw) << 16) / 100;
1883         angle = 0;
1884
1885         for (i = 0; i < len; i++) {
1886                 samples[i] = b43_cordic(angle);
1887                 angle += rot;
1888                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1889                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1890         }
1891
1892         i = b43_nphy_load_samples(dev, samples, len);
1893         kfree(samples);
1894         return (i < 0) ? 0 : len;
1895 }
1896
1897 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1898 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1899                                         u16 wait, bool iqmode, bool dac_test)
1900 {
1901         struct b43_phy_n *nphy = dev->phy.n;
1902         int i;
1903         u16 seq_mode;
1904         u32 tmp;
1905
1906         if (nphy->hang_avoid)
1907                 b43_nphy_stay_in_carrier_search(dev, true);
1908
1909         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1910                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1911                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1912         }
1913
1914         if (!dev->phy.is_40mhz)
1915                 tmp = 0x6464;
1916         else
1917                 tmp = 0x4747;
1918         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1919
1920         if (nphy->hang_avoid)
1921                 b43_nphy_stay_in_carrier_search(dev, false);
1922
1923         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1924
1925         if (loops != 0xFFFF)
1926                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1927         else
1928                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1929
1930         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1931
1932         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1933
1934         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1935         if (iqmode) {
1936                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1937                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1938         } else {
1939                 if (dac_test)
1940                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1941                 else
1942                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1943         }
1944         for (i = 0; i < 100; i++) {
1945                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1946                         i = 0;
1947                         break;
1948                 }
1949                 udelay(10);
1950         }
1951         if (i)
1952                 b43err(dev->wl, "run samples timeout\n");
1953
1954         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1955 }
1956
1957 /*
1958  * Transmits a known value for LO calibration
1959  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1960  */
1961 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1962                                 bool iqmode, bool dac_test)
1963 {
1964         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1965         if (samp == 0)
1966                 return -1;
1967         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1968         return 0;
1969 }
1970
1971 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1972 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1973 {
1974         struct b43_phy_n *nphy = dev->phy.n;
1975         int i, j;
1976         u32 tmp;
1977         u32 cur_real, cur_imag, real_part, imag_part;
1978
1979         u16 buffer[7];
1980
1981         if (nphy->hang_avoid)
1982                 b43_nphy_stay_in_carrier_search(dev, true);
1983
1984         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1985
1986         for (i = 0; i < 2; i++) {
1987                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1988                         (buffer[i * 2 + 1] & 0x3FF);
1989                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1990                                 (((i + 26) << 10) | 320));
1991                 for (j = 0; j < 128; j++) {
1992                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1993                                         ((tmp >> 16) & 0xFFFF));
1994                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1995                                         (tmp & 0xFFFF));
1996                 }
1997         }
1998
1999         for (i = 0; i < 2; i++) {
2000                 tmp = buffer[5 + i];
2001                 real_part = (tmp >> 8) & 0xFF;
2002                 imag_part = (tmp & 0xFF);
2003                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2004                                 (((i + 26) << 10) | 448));
2005
2006                 if (dev->phy.rev >= 3) {
2007                         cur_real = real_part;
2008                         cur_imag = imag_part;
2009                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
2010                 }
2011
2012                 for (j = 0; j < 128; j++) {
2013                         if (dev->phy.rev < 3) {
2014                                 cur_real = (real_part * loscale[j] + 128) >> 8;
2015                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
2016                                 tmp = ((cur_real & 0xFF) << 8) |
2017                                         (cur_imag & 0xFF);
2018                         }
2019                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2020                                         ((tmp >> 16) & 0xFFFF));
2021                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2022                                         (tmp & 0xFFFF));
2023                 }
2024         }
2025
2026         if (dev->phy.rev >= 3) {
2027                 b43_shm_write16(dev, B43_SHM_SHARED,
2028                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
2029                 b43_shm_write16(dev, B43_SHM_SHARED,
2030                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
2031         }
2032
2033         if (nphy->hang_avoid)
2034                 b43_nphy_stay_in_carrier_search(dev, false);
2035 }
2036
2037 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
2038 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
2039                                         u8 *events, u8 *delays, u8 length)
2040 {
2041         struct b43_phy_n *nphy = dev->phy.n;
2042         u8 i;
2043         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
2044         u16 offset1 = cmd << 4;
2045         u16 offset2 = offset1 + 0x80;
2046
2047         if (nphy->hang_avoid)
2048                 b43_nphy_stay_in_carrier_search(dev, true);
2049
2050         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
2051         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
2052
2053         for (i = length; i < 16; i++) {
2054                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
2055                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
2056         }
2057
2058         if (nphy->hang_avoid)
2059                 b43_nphy_stay_in_carrier_search(dev, false);
2060 }
2061
2062 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
2063 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
2064                                        enum b43_nphy_rf_sequence seq)
2065 {
2066         static const u16 trigger[] = {
2067                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
2068                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
2069                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
2070                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
2071                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
2072                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
2073         };
2074         int i;
2075         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
2076
2077         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
2078
2079         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2080                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
2081         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
2082         for (i = 0; i < 200; i++) {
2083                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
2084                         goto ok;
2085                 msleep(1);
2086         }
2087         b43err(dev->wl, "RF sequence status timeout\n");
2088 ok:
2089         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
2090 }
2091
2092 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
2093 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
2094                                                 u16 value, u8 core, bool off)
2095 {
2096         int i;
2097         u8 index = fls(field);
2098         u8 addr, en_addr, val_addr;
2099         /* we expect only one bit set */
2100         B43_WARN_ON(field & (~(1 << (index - 1))));
2101
2102         if (dev->phy.rev >= 3) {
2103                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
2104                 for (i = 0; i < 2; i++) {
2105                         if (index == 0 || index == 16) {
2106                                 b43err(dev->wl,
2107                                         "Unsupported RF Ctrl Override call\n");
2108                                 return;
2109                         }
2110
2111                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
2112                         en_addr = B43_PHY_N((i == 0) ?
2113                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
2114                         val_addr = B43_PHY_N((i == 0) ?
2115                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
2116
2117                         if (off) {
2118                                 b43_phy_mask(dev, en_addr, ~(field));
2119                                 b43_phy_mask(dev, val_addr,
2120                                                 ~(rf_ctrl->val_mask));
2121                         } else {
2122                                 if (core == 0 || ((1 << core) & i) != 0) {
2123                                         b43_phy_set(dev, en_addr, field);
2124                                         b43_phy_maskset(dev, val_addr,
2125                                                 ~(rf_ctrl->val_mask),
2126                                                 (value << rf_ctrl->val_shift));
2127                                 }
2128                         }
2129                 }
2130         } else {
2131                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
2132                 if (off) {
2133                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
2134                         value = 0;
2135                 } else {
2136                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
2137                 }
2138
2139                 for (i = 0; i < 2; i++) {
2140                         if (index <= 1 || index == 16) {
2141                                 b43err(dev->wl,
2142                                         "Unsupported RF Ctrl Override call\n");
2143                                 return;
2144                         }
2145
2146                         if (index == 2 || index == 10 ||
2147                             (index >= 13 && index <= 15)) {
2148                                 core = 1;
2149                         }
2150
2151                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
2152                         addr = B43_PHY_N((i == 0) ?
2153                                 rf_ctrl->addr0 : rf_ctrl->addr1);
2154
2155                         if ((core & (1 << i)) != 0)
2156                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
2157                                                 (value << rf_ctrl->shift));
2158
2159                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
2160                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2161                                         B43_NPHY_RFCTL_CMD_START);
2162                         udelay(1);
2163                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
2164                 }
2165         }
2166 }
2167
2168 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
2169 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
2170                                                 u16 value, u8 core)
2171 {
2172         u8 i, j;
2173         u16 reg, tmp, val;
2174
2175         B43_WARN_ON(dev->phy.rev < 3);
2176         B43_WARN_ON(field > 4);
2177
2178         for (i = 0; i < 2; i++) {
2179                 if ((core == 1 && i == 1) || (core == 2 && !i))
2180                         continue;
2181
2182                 reg = (i == 0) ?
2183                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
2184                 b43_phy_mask(dev, reg, 0xFBFF);
2185
2186                 switch (field) {
2187                 case 0:
2188                         b43_phy_write(dev, reg, 0);
2189                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2190                         break;
2191                 case 1:
2192                         if (!i) {
2193                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
2194                                                 0xFC3F, (value << 6));
2195                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
2196                                                 0xFFFE, 1);
2197                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2198                                                 B43_NPHY_RFCTL_CMD_START);
2199                                 for (j = 0; j < 100; j++) {
2200                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
2201                                                 j = 0;
2202                                                 break;
2203                                         }
2204                                         udelay(10);
2205                                 }
2206                                 if (j)
2207                                         b43err(dev->wl,
2208                                                 "intc override timeout\n");
2209                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
2210                                                 0xFFFE);
2211                         } else {
2212                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
2213                                                 0xFC3F, (value << 6));
2214                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
2215                                                 0xFFFE, 1);
2216                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2217                                                 B43_NPHY_RFCTL_CMD_RXTX);
2218                                 for (j = 0; j < 100; j++) {
2219                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
2220                                                 j = 0;
2221                                                 break;
2222                                         }
2223                                         udelay(10);
2224                                 }
2225                                 if (j)
2226                                         b43err(dev->wl,
2227                                                 "intc override timeout\n");
2228                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2229                                                 0xFFFE);
2230                         }
2231                         break;
2232                 case 2:
2233                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2234                                 tmp = 0x0020;
2235                                 val = value << 5;
2236                         } else {
2237                                 tmp = 0x0010;
2238                                 val = value << 4;
2239                         }
2240                         b43_phy_maskset(dev, reg, ~tmp, val);
2241                         break;
2242                 case 3:
2243                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2244                                 tmp = 0x0001;
2245                                 val = value;
2246                         } else {
2247                                 tmp = 0x0004;
2248                                 val = value << 2;
2249                         }
2250                         b43_phy_maskset(dev, reg, ~tmp, val);
2251                         break;
2252                 case 4:
2253                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2254                                 tmp = 0x0002;
2255                                 val = value << 1;
2256                         } else {
2257                                 tmp = 0x0008;
2258                                 val = value << 3;
2259                         }
2260                         b43_phy_maskset(dev, reg, ~tmp, val);
2261                         break;
2262                 }
2263         }
2264 }
2265
2266 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
2267 static void b43_nphy_bphy_init(struct b43_wldev *dev)
2268 {
2269         unsigned int i;
2270         u16 val;
2271
2272         val = 0x1E1F;
2273         for (i = 0; i < 16; i++) {
2274                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2275                 val -= 0x202;
2276         }
2277         val = 0x3E3F;
2278         for (i = 0; i < 16; i++) {
2279                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2280                 val -= 0x202;
2281         }
2282         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2283 }
2284
2285 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2286 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2287                                         s8 offset, u8 core, u8 rail,
2288                                         enum b43_nphy_rssi_type type)
2289 {
2290         u16 tmp;
2291         bool core1or5 = (core == 1) || (core == 5);
2292         bool core2or5 = (core == 2) || (core == 5);
2293
2294         offset = clamp_val(offset, -32, 31);
2295         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2296
2297         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2298                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2299         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2300                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2301         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2302                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2303         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2304                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2305
2306         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2307                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2308         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2309                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2310         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2311                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2312         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2313                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2314
2315         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2316                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2317         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2318                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2319         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2320                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2321         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2322                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2323
2324         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2325                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2326         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2327                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2328         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2329                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2330         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2331                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2332
2333         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2334                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2335         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2336                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2337         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2338                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2339         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2340                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2341
2342         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2343                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2344         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2345                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2346
2347         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2348                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2349         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2350                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2351 }
2352
2353 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2354 {
2355         u16 val;
2356
2357         if (type < 3)
2358                 val = 0;
2359         else if (type == 6)
2360                 val = 1;
2361         else if (type == 3)
2362                 val = 2;
2363         else
2364                 val = 3;
2365
2366         val = (val << 12) | (val << 14);
2367         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2368         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2369
2370         if (type < 3) {
2371                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2372                                 (type + 1) << 4);
2373                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2374                                 (type + 1) << 4);
2375         }
2376
2377         if (code == 0) {
2378                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2379                 if (type < 3) {
2380                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2381                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2382                                   B43_NPHY_RFCTL_CMD_CORESEL));
2383                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2384                                 ~(0x1 << 12 |
2385                                   0x1 << 5 |
2386                                   0x1 << 1 |
2387                                   0x1));
2388                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2389                                 ~B43_NPHY_RFCTL_CMD_START);
2390                         udelay(20);
2391                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2392                 }
2393         } else {
2394                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2395                 if (type < 3) {
2396                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2397                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2398                                   B43_NPHY_RFCTL_CMD_CORESEL),
2399                                 (B43_NPHY_RFCTL_CMD_RXEN |
2400                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2401                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2402                                 (0x1 << 12 |
2403                                   0x1 << 5 |
2404                                   0x1 << 1 |
2405                                   0x1));
2406                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2407                                 B43_NPHY_RFCTL_CMD_START);
2408                         udelay(20);
2409                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2410                 }
2411         }
2412 }
2413
2414 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2415 {
2416         u8 i;
2417         u16 reg, val;
2418
2419         if (code == 0) {
2420                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2421                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2422                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2423                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2424                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2425                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2426                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2427                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2428         } else {
2429                 for (i = 0; i < 2; i++) {
2430                         if ((code == 1 && i == 1) || (code == 2 && !i))
2431                                 continue;
2432
2433                         reg = (i == 0) ?
2434                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2435                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2436
2437                         if (type < 3) {
2438                                 reg = (i == 0) ?
2439                                         B43_NPHY_AFECTL_C1 :
2440                                         B43_NPHY_AFECTL_C2;
2441                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2442
2443                                 reg = (i == 0) ?
2444                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2445                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
2446                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2447
2448                                 if (type == 0)
2449                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2450                                 else if (type == 1)
2451                                         val = 16;
2452                                 else
2453                                         val = 32;
2454                                 b43_phy_set(dev, reg, val);
2455
2456                                 reg = (i == 0) ?
2457                                         B43_NPHY_TXF_40CO_B1S0 :
2458                                         B43_NPHY_TXF_40CO_B32S1;
2459                                 b43_phy_set(dev, reg, 0x0020);
2460                         } else {
2461                                 if (type == 6)
2462                                         val = 0x0100;
2463                                 else if (type == 3)
2464                                         val = 0x0200;
2465                                 else
2466                                         val = 0x0300;
2467
2468                                 reg = (i == 0) ?
2469                                         B43_NPHY_AFECTL_C1 :
2470                                         B43_NPHY_AFECTL_C2;
2471
2472                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
2473                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2474
2475                                 if (type != 3 && type != 6) {
2476                                         enum ieee80211_band band =
2477                                                 b43_current_band(dev->wl);
2478
2479                                         if (b43_nphy_ipa(dev))
2480                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2481                                         else
2482                                                 val = 0x11;
2483                                         reg = (i == 0) ? 0x2000 : 0x3000;
2484                                         reg |= B2055_PADDRV;
2485                                         b43_radio_write16(dev, reg, val);
2486
2487                                         reg = (i == 0) ?
2488                                                 B43_NPHY_AFECTL_OVER1 :
2489                                                 B43_NPHY_AFECTL_OVER;
2490                                         b43_phy_set(dev, reg, 0x0200);
2491                                 }
2492                         }
2493                 }
2494         }
2495 }
2496
2497 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2498 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2499 {
2500         if (dev->phy.rev >= 3)
2501                 b43_nphy_rev3_rssi_select(dev, code, type);
2502         else
2503                 b43_nphy_rev2_rssi_select(dev, code, type);
2504 }
2505
2506 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2507 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2508 {
2509         int i;
2510         for (i = 0; i < 2; i++) {
2511                 if (type == 2) {
2512                         if (i == 0) {
2513                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2514                                                   0xFC, buf[0]);
2515                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2516                                                   0xFC, buf[1]);
2517                         } else {
2518                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2519                                                   0xFC, buf[2 * i]);
2520                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2521                                                   0xFC, buf[2 * i + 1]);
2522                         }
2523                 } else {
2524                         if (i == 0)
2525                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2526                                                   0xF3, buf[0] << 2);
2527                         else
2528                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2529                                                   0xF3, buf[2 * i + 1] << 2);
2530                 }
2531         }
2532 }
2533
2534 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2535 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2536                                 u8 nsamp)
2537 {
2538         int i;
2539         int out;
2540         u16 save_regs_phy[9];
2541         u16 s[2];
2542
2543         if (dev->phy.rev >= 3) {
2544                 save_regs_phy[0] = b43_phy_read(dev,
2545                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2546                 save_regs_phy[1] = b43_phy_read(dev,
2547                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2548                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2549                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2550                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2551                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2552                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2553                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2554                 save_regs_phy[8] = 0;
2555         } else {
2556                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2557                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2558                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2559                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2560                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2561                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2562                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2563                 save_regs_phy[7] = 0;
2564                 save_regs_phy[8] = 0;
2565         }
2566
2567         b43_nphy_rssi_select(dev, 5, type);
2568
2569         if (dev->phy.rev < 2) {
2570                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2571                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2572         }
2573
2574         for (i = 0; i < 4; i++)
2575                 buf[i] = 0;
2576
2577         for (i = 0; i < nsamp; i++) {
2578                 if (dev->phy.rev < 2) {
2579                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2580                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2581                 } else {
2582                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2583                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2584                 }
2585
2586                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2587                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2588                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2589                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2590         }
2591         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2592                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2593
2594         if (dev->phy.rev < 2)
2595                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2596
2597         if (dev->phy.rev >= 3) {
2598                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2599                                 save_regs_phy[0]);
2600                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2601                                 save_regs_phy[1]);
2602                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2603                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2604                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2605                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2606                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2607                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2608         } else {
2609                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2610                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2611                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2612                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2613                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2614                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2615                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2616         }
2617
2618         return out;
2619 }
2620
2621 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2622 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2623 {
2624         int i, j;
2625         u8 state[4];
2626         u8 code, val;
2627         u16 class, override;
2628         u8 regs_save_radio[2];
2629         u16 regs_save_phy[2];
2630
2631         s8 offset[4];
2632         u8 core;
2633         u8 rail;
2634
2635         u16 clip_state[2];
2636         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2637         s32 results_min[4] = { };
2638         u8 vcm_final[4] = { };
2639         s32 results[4][4] = { };
2640         s32 miniq[4][2] = { };
2641
2642         if (type == 2) {
2643                 code = 0;
2644                 val = 6;
2645         } else if (type < 2) {
2646                 code = 25;
2647                 val = 4;
2648         } else {
2649                 B43_WARN_ON(1);
2650                 return;
2651         }
2652
2653         class = b43_nphy_classifier(dev, 0, 0);
2654         b43_nphy_classifier(dev, 7, 4);
2655         b43_nphy_read_clip_detection(dev, clip_state);
2656         b43_nphy_write_clip_detection(dev, clip_off);
2657
2658         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2659                 override = 0x140;
2660         else
2661                 override = 0x110;
2662
2663         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2664         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2665         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2666         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2667
2668         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2669         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2670         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2671         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2672
2673         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2674         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2675         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2676         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2677         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2678         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2679
2680         b43_nphy_rssi_select(dev, 5, type);
2681         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2682         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2683
2684         for (i = 0; i < 4; i++) {
2685                 u8 tmp[4];
2686                 for (j = 0; j < 4; j++)
2687                         tmp[j] = i;
2688                 if (type != 1)
2689                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2690                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2691                 if (type < 2)
2692                         for (j = 0; j < 2; j++)
2693                                 miniq[i][j] = min(results[i][2 * j],
2694                                                 results[i][2 * j + 1]);
2695         }
2696
2697         for (i = 0; i < 4; i++) {
2698                 s32 mind = 40;
2699                 u8 minvcm = 0;
2700                 s32 minpoll = 249;
2701                 s32 curr;
2702                 for (j = 0; j < 4; j++) {
2703                         if (type == 2)
2704                                 curr = abs(results[j][i]);
2705                         else
2706                                 curr = abs(miniq[j][i / 2] - code * 8);
2707
2708                         if (curr < mind) {
2709                                 mind = curr;
2710                                 minvcm = j;
2711                         }
2712
2713                         if (results[j][i] < minpoll)
2714                                 minpoll = results[j][i];
2715                 }
2716                 results_min[i] = minpoll;
2717                 vcm_final[i] = minvcm;
2718         }
2719
2720         if (type != 1)
2721                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2722
2723         for (i = 0; i < 4; i++) {
2724                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2725
2726                 if (offset[i] < 0)
2727                         offset[i] = -((abs(offset[i]) + 4) / 8);
2728                 else
2729                         offset[i] = (offset[i] + 4) / 8;
2730
2731                 if (results_min[i] == 248)
2732                         offset[i] = code - 32;
2733
2734                 core = (i / 2) ? 2 : 1;
2735                 rail = (i % 2) ? 1 : 0;
2736
2737                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2738                                                 type);
2739         }
2740
2741         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2742         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2743
2744         switch (state[2]) {
2745         case 1:
2746                 b43_nphy_rssi_select(dev, 1, 2);
2747                 break;
2748         case 4:
2749                 b43_nphy_rssi_select(dev, 1, 0);
2750                 break;
2751         case 2:
2752                 b43_nphy_rssi_select(dev, 1, 1);
2753                 break;
2754         default:
2755                 b43_nphy_rssi_select(dev, 1, 1);
2756                 break;
2757         }
2758
2759         switch (state[3]) {
2760         case 1:
2761                 b43_nphy_rssi_select(dev, 2, 2);
2762                 break;
2763         case 4:
2764                 b43_nphy_rssi_select(dev, 2, 0);
2765                 break;
2766         default:
2767                 b43_nphy_rssi_select(dev, 2, 1);
2768                 break;
2769         }
2770
2771         b43_nphy_rssi_select(dev, 0, type);
2772
2773         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2774         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2775         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2776         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2777
2778         b43_nphy_classifier(dev, 7, class);
2779         b43_nphy_write_clip_detection(dev, clip_state);
2780         /* Specs don't say about reset here, but it makes wl and b43 dumps
2781            identical, it really seems wl performs this */
2782         b43_nphy_reset_cca(dev);
2783 }
2784
2785 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2786 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2787 {
2788         /* TODO */
2789 }
2790
2791 /*
2792  * RSSI Calibration
2793  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2794  */
2795 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2796 {
2797         if (dev->phy.rev >= 3) {
2798                 b43_nphy_rev3_rssi_cal(dev);
2799         } else {
2800                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2801                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2802                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2803         }
2804 }
2805
2806 /*
2807  * Restore RSSI Calibration
2808  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2809  */
2810 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2811 {
2812         struct b43_phy_n *nphy = dev->phy.n;
2813
2814         u16 *rssical_radio_regs = NULL;
2815         u16 *rssical_phy_regs = NULL;
2816
2817         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2818                 if (!nphy->rssical_chanspec_2G.center_freq)
2819                         return;
2820                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2821                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2822         } else {
2823                 if (!nphy->rssical_chanspec_5G.center_freq)
2824                         return;
2825                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2826                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2827         }
2828
2829         /* TODO use some definitions */
2830         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2831         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2832
2833         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2834         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2835         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2836         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2837
2838         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2839         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2840         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2841         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2842
2843         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2844         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2845         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2846         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2847 }
2848
2849 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2850 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2851 {
2852         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2853                 if (dev->phy.rev >= 6) {
2854                         if (dev->dev->chip_id == 47162)
2855                                 return txpwrctrl_tx_gain_ipa_rev5;
2856                         return txpwrctrl_tx_gain_ipa_rev6;
2857                 } else if (dev->phy.rev >= 5) {
2858                         return txpwrctrl_tx_gain_ipa_rev5;
2859                 } else {
2860                         return txpwrctrl_tx_gain_ipa;
2861                 }
2862         } else {
2863                 return txpwrctrl_tx_gain_ipa_5g;
2864         }
2865 }
2866
2867 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2868 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2869 {
2870         struct b43_phy_n *nphy = dev->phy.n;
2871         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2872         u16 tmp;
2873         u8 offset, i;
2874
2875         if (dev->phy.rev >= 3) {
2876             for (i = 0; i < 2; i++) {
2877                 tmp = (i == 0) ? 0x2000 : 0x3000;
2878                 offset = i * 11;
2879
2880                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2881                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2882                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2883                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2884                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2885                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2886                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2887                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2888                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2889                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2890                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2891
2892                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2893                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2894                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2895                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2896                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2897                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2898                         if (nphy->ipa5g_on) {
2899                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2900                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2901                         } else {
2902                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2903                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2904                         }
2905                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2906                 } else {
2907                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2908                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2909                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2910                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2911                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2912                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2913                         if (nphy->ipa2g_on) {
2914                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2915                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2916                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2917                         } else {
2918                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2919                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2920                         }
2921                 }
2922                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2923                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2924                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2925             }
2926         } else {
2927                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2928                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2929
2930                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2931                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2932
2933                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2934                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2935
2936                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2937                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2938
2939                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2940                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2941
2942                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2943                     B43_NPHY_BANDCTL_5GHZ)) {
2944                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2945                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2946                 } else {
2947                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2948                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2949                 }
2950
2951                 if (dev->phy.rev < 2) {
2952                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2953                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2954                 } else {
2955                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2956                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2957                 }
2958         }
2959 }
2960
2961 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2962 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2963                                         struct nphy_txgains target,
2964                                         struct nphy_iqcal_params *params)
2965 {
2966         int i, j, indx;
2967         u16 gain;
2968
2969         if (dev->phy.rev >= 3) {
2970                 params->txgm = target.txgm[core];
2971                 params->pga = target.pga[core];
2972                 params->pad = target.pad[core];
2973                 params->ipa = target.ipa[core];
2974                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2975                                         (params->pad << 4) | (params->ipa);
2976                 for (j = 0; j < 5; j++)
2977                         params->ncorr[j] = 0x79;
2978         } else {
2979                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2980                         (target.txgm[core] << 8);
2981
2982                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2983                         1 : 0;
2984                 for (i = 0; i < 9; i++)
2985                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2986                                 break;
2987                 i = min(i, 8);
2988
2989                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2990                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2991                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2992                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2993                                         (params->pad << 2);
2994                 for (j = 0; j < 4; j++)
2995                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2996         }
2997 }
2998
2999 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3000 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3001 {
3002         struct b43_phy_n *nphy = dev->phy.n;
3003         int i;
3004         u16 scale, entry;
3005
3006         u16 tmp = nphy->txcal_bbmult;
3007         if (core == 0)
3008                 tmp >>= 8;
3009         tmp &= 0xff;
3010
3011         for (i = 0; i < 18; i++) {
3012                 scale = (ladder_lo[i].percent * tmp) / 100;
3013                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
3014                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
3015
3016                 scale = (ladder_iq[i].percent * tmp) / 100;
3017                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
3018                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
3019         }
3020 }
3021
3022 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3023 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3024 {
3025         int i;
3026         for (i = 0; i < 15; i++)
3027                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
3028                                 tbl_tx_filter_coef_rev4[2][i]);
3029 }
3030
3031 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
3032 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
3033 {
3034         int i, j;
3035         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
3036         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
3037
3038         for (i = 0; i < 3; i++)
3039                 for (j = 0; j < 15; j++)
3040                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
3041                                         tbl_tx_filter_coef_rev4[i][j]);
3042
3043         if (dev->phy.is_40mhz) {
3044                 for (j = 0; j < 15; j++)
3045                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3046                                         tbl_tx_filter_coef_rev4[3][j]);
3047         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3048                 for (j = 0; j < 15; j++)
3049                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3050                                         tbl_tx_filter_coef_rev4[5][j]);
3051         }
3052
3053         if (dev->phy.channel == 14)
3054                 for (j = 0; j < 15; j++)
3055                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3056                                         tbl_tx_filter_coef_rev4[6][j]);
3057 }
3058
3059 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
3060 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
3061 {
3062         struct b43_phy_n *nphy = dev->phy.n;
3063
3064         u16 curr_gain[2];
3065         struct nphy_txgains target;
3066         const u32 *table = NULL;
3067
3068         if (!nphy->txpwrctrl) {
3069                 int i;
3070
3071                 if (nphy->hang_avoid)
3072                         b43_nphy_stay_in_carrier_search(dev, true);
3073                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
3074                 if (nphy->hang_avoid)
3075                         b43_nphy_stay_in_carrier_search(dev, false);
3076
3077                 for (i = 0; i < 2; ++i) {
3078                         if (dev->phy.rev >= 3) {
3079                                 target.ipa[i] = curr_gain[i] & 0x000F;
3080                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
3081                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
3082                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
3083                         } else {
3084                                 target.ipa[i] = curr_gain[i] & 0x0003;
3085                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
3086                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
3087                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
3088                         }
3089                 }
3090         } else {
3091                 int i;
3092                 u16 index[2];
3093                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
3094                         B43_NPHY_TXPCTL_STAT_BIDX) >>
3095                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3096                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
3097                         B43_NPHY_TXPCTL_STAT_BIDX) >>
3098                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3099
3100                 for (i = 0; i < 2; ++i) {
3101                         if (dev->phy.rev >= 3) {
3102                                 enum ieee80211_band band =
3103                                         b43_current_band(dev->wl);
3104
3105                                 if (b43_nphy_ipa(dev)) {
3106                                         table = b43_nphy_get_ipa_gain_table(dev);
3107                                 } else {
3108                                         if (band == IEEE80211_BAND_5GHZ) {
3109                                                 if (dev->phy.rev == 3)
3110                                                         table = b43_ntab_tx_gain_rev3_5ghz;
3111                                                 else if (dev->phy.rev == 4)
3112                                                         table = b43_ntab_tx_gain_rev4_5ghz;
3113                                                 else
3114                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
3115                                         } else {
3116                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
3117                                         }
3118                                 }
3119
3120                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3121                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3122                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3123                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3124                         } else {
3125                                 table = b43_ntab_tx_gain_rev0_1_2;
3126
3127                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3128                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3129                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3130                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3131                         }
3132                 }
3133         }
3134
3135         return target;
3136 }
3137
3138 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3139 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3140 {
3141         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3142
3143         if (dev->phy.rev >= 3) {
3144                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3145                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3146                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3147                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3148                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
3149                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3150                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
3151                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3152                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3153                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3154                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3155                 b43_nphy_reset_cca(dev);
3156         } else {
3157                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3158                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3159                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3160                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3161                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
3162                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3163                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3164         }
3165 }
3166
3167 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3168 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3169 {
3170         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3171         u16 tmp;
3172
3173         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3174         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3175         if (dev->phy.rev >= 3) {
3176                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3177                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3178
3179                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3180                 regs[2] = tmp;
3181                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3182
3183                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3184                 regs[3] = tmp;
3185                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3186
3187                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
3188                 b43_phy_mask(dev, B43_NPHY_BBCFG,
3189                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
3190
3191                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
3192                 regs[5] = tmp;
3193                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
3194
3195                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
3196                 regs[6] = tmp;
3197                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
3198                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3199                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3200
3201                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3202                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3203                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3204
3205                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3206                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3207                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3208                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3209         } else {
3210                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3211                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3212                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3213                 regs[2] = tmp;
3214                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3215                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3216                 regs[3] = tmp;
3217                 tmp |= 0x2000;
3218                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3219                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3220                 regs[4] = tmp;
3221                 tmp |= 0x2000;
3222                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3223                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3224                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3225                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3226                         tmp = 0x0180;
3227                 else
3228                         tmp = 0x0120;
3229                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3230                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3231         }
3232 }
3233
3234 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3235 static void b43_nphy_save_cal(struct b43_wldev *dev)
3236 {
3237         struct b43_phy_n *nphy = dev->phy.n;
3238
3239         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3240         u16 *txcal_radio_regs = NULL;
3241         struct b43_chanspec *iqcal_chanspec;
3242         u16 *table = NULL;
3243
3244         if (nphy->hang_avoid)
3245                 b43_nphy_stay_in_carrier_search(dev, 1);
3246
3247         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3248                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3249                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3250                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3251                 table = nphy->cal_cache.txcal_coeffs_2G;
3252         } else {
3253                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3254                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3255                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3256                 table = nphy->cal_cache.txcal_coeffs_5G;
3257         }
3258
3259         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3260         /* TODO use some definitions */
3261         if (dev->phy.rev >= 3) {
3262                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3263                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3264                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3265                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3266                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3267                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3268                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3269                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3270         } else {
3271                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3272                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3273                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3274                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3275         }
3276         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3277         iqcal_chanspec->channel_type = dev->phy.channel_type;
3278         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3279
3280         if (nphy->hang_avoid)
3281                 b43_nphy_stay_in_carrier_search(dev, 0);
3282 }
3283
3284 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3285 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3286 {
3287         struct b43_phy_n *nphy = dev->phy.n;
3288
3289         u16 coef[4];
3290         u16 *loft = NULL;
3291         u16 *table = NULL;
3292
3293         int i;
3294         u16 *txcal_radio_regs = NULL;
3295         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3296
3297         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3298                 if (!nphy->iqcal_chanspec_2G.center_freq)
3299                         return;
3300                 table = nphy->cal_cache.txcal_coeffs_2G;
3301                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3302         } else {
3303                 if (!nphy->iqcal_chanspec_5G.center_freq)
3304                         return;
3305                 table = nphy->cal_cache.txcal_coeffs_5G;
3306                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3307         }
3308
3309         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3310
3311         for (i = 0; i < 4; i++) {
3312                 if (dev->phy.rev >= 3)
3313                         table[i] = coef[i];
3314                 else
3315                         coef[i] = 0;
3316         }
3317
3318         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3319         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3320         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3321
3322         if (dev->phy.rev < 2)
3323                 b43_nphy_tx_iq_workaround(dev);
3324
3325         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3326                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3327                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3328         } else {
3329                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3330                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3331         }
3332
3333         /* TODO use some definitions */
3334         if (dev->phy.rev >= 3) {
3335                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3336                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3337                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3338                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3339                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3340                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3341                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3342                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3343         } else {
3344                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3345                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3346                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3347                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3348         }
3349         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3350 }
3351
3352 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3353 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3354                                 struct nphy_txgains target,
3355                                 bool full, bool mphase)
3356 {
3357         struct b43_phy_n *nphy = dev->phy.n;
3358         int i;
3359         int error = 0;
3360         int freq;
3361         bool avoid = false;
3362         u8 length;
3363         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3364         const u16 *table;
3365         bool phy6or5x;
3366
3367         u16 buffer[11];
3368         u16 diq_start = 0;
3369         u16 save[2];
3370         u16 gain[2];
3371         struct nphy_iqcal_params params[2];
3372         bool updated[2] = { };
3373
3374         b43_nphy_stay_in_carrier_search(dev, true);
3375
3376         if (dev->phy.rev >= 4) {
3377                 avoid = nphy->hang_avoid;
3378                 nphy->hang_avoid = 0;
3379         }
3380
3381         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3382
3383         for (i = 0; i < 2; i++) {
3384                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3385                 gain[i] = params[i].cal_gain;
3386         }
3387
3388         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3389
3390         b43_nphy_tx_cal_radio_setup(dev);
3391         b43_nphy_tx_cal_phy_setup(dev);
3392
3393         phy6or5x = dev->phy.rev >= 6 ||
3394                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3395                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3396         if (phy6or5x) {
3397                 if (dev->phy.is_40mhz) {
3398                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3399                                         tbl_tx_iqlo_cal_loft_ladder_40);
3400                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3401                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3402                 } else {
3403                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3404                                         tbl_tx_iqlo_cal_loft_ladder_20);
3405                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3406                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3407                 }
3408         }
3409
3410         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3411
3412         if (!dev->phy.is_40mhz)
3413                 freq = 2500;
3414         else
3415                 freq = 5000;
3416
3417         if (nphy->mphase_cal_phase_id > 2)
3418                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3419                                         0xFFFF, 0, true, false);
3420         else
3421                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3422
3423         if (error == 0) {
3424                 if (nphy->mphase_cal_phase_id > 2) {
3425                         table = nphy->mphase_txcal_bestcoeffs;
3426                         length = 11;
3427                         if (dev->phy.rev < 3)
3428                                 length -= 2;
3429                 } else {
3430                         if (!full && nphy->txiqlocal_coeffsvalid) {
3431                                 table = nphy->txiqlocal_bestc;
3432                                 length = 11;
3433                                 if (dev->phy.rev < 3)
3434                                         length -= 2;
3435                         } else {
3436                                 full = true;
3437                                 if (dev->phy.rev >= 3) {
3438                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3439                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3440                                 } else {
3441                                         table = tbl_tx_iqlo_cal_startcoefs;
3442                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3443                                 }
3444                         }
3445                 }
3446
3447                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3448
3449                 if (full) {
3450                         if (dev->phy.rev >= 3)
3451                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3452                         else
3453                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3454                 } else {
3455                         if (dev->phy.rev >= 3)
3456                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3457                         else
3458                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3459                 }
3460
3461                 if (mphase) {
3462                         count = nphy->mphase_txcal_cmdidx;
3463                         numb = min(max,
3464                                 (u16)(count + nphy->mphase_txcal_numcmds));
3465                 } else {
3466                         count = 0;
3467                         numb = max;
3468                 }
3469
3470                 for (; count < numb; count++) {
3471                         if (full) {
3472                                 if (dev->phy.rev >= 3)
3473                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3474                                 else
3475                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3476                         } else {
3477                                 if (dev->phy.rev >= 3)
3478                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3479                                 else
3480                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3481                         }
3482
3483                         core = (cmd & 0x3000) >> 12;
3484                         type = (cmd & 0x0F00) >> 8;
3485
3486                         if (phy6or5x && updated[core] == 0) {
3487                                 b43_nphy_update_tx_cal_ladder(dev, core);
3488                                 updated[core] = 1;
3489                         }
3490
3491                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3492                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3493
3494                         if (type == 1 || type == 3 || type == 4) {
3495                                 buffer[0] = b43_ntab_read(dev,
3496                                                 B43_NTAB16(15, 69 + core));
3497                                 diq_start = buffer[0];
3498                                 buffer[0] = 0;
3499                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3500                                                 0);
3501                         }
3502
3503                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3504                         for (i = 0; i < 2000; i++) {
3505                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3506                                 if (tmp & 0xC000)
3507                                         break;
3508                                 udelay(10);
3509                         }
3510
3511                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3512                                                 buffer);
3513                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3514                                                 buffer);
3515
3516                         if (type == 1 || type == 3 || type == 4)
3517                                 buffer[0] = diq_start;
3518                 }
3519
3520                 if (mphase)
3521                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3522
3523                 last = (dev->phy.rev < 3) ? 6 : 7;
3524
3525                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3526                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3527                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3528                         if (dev->phy.rev < 3) {
3529                                 buffer[0] = 0;
3530                                 buffer[1] = 0;
3531                                 buffer[2] = 0;
3532                                 buffer[3] = 0;
3533                         }
3534                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3535                                                 buffer);
3536                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3537                                                 buffer);
3538                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3539                                                 buffer);
3540                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3541                                                 buffer);
3542                         length = 11;
3543                         if (dev->phy.rev < 3)
3544                                 length -= 2;
3545                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3546                                                 nphy->txiqlocal_bestc);
3547                         nphy->txiqlocal_coeffsvalid = true;
3548                         nphy->txiqlocal_chanspec.center_freq =
3549                                                         dev->phy.channel_freq;
3550                         nphy->txiqlocal_chanspec.channel_type =
3551                                                         dev->phy.channel_type;
3552                 } else {
3553                         length = 11;
3554                         if (dev->phy.rev < 3)
3555                                 length -= 2;
3556                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3557                                                 nphy->mphase_txcal_bestcoeffs);
3558                 }
3559
3560                 b43_nphy_stop_playback(dev);
3561                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3562         }
3563
3564         b43_nphy_tx_cal_phy_cleanup(dev);
3565         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3566
3567         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3568                 b43_nphy_tx_iq_workaround(dev);
3569
3570         if (dev->phy.rev >= 4)
3571                 nphy->hang_avoid = avoid;
3572
3573         b43_nphy_stay_in_carrier_search(dev, false);
3574
3575         return error;
3576 }
3577
3578 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3579 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3580 {
3581         struct b43_phy_n *nphy = dev->phy.n;
3582         u8 i;
3583         u16 buffer[7];
3584         bool equal = true;
3585
3586         if (!nphy->txiqlocal_coeffsvalid ||
3587             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3588             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3589                 return;
3590
3591         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3592         for (i = 0; i < 4; i++) {
3593                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3594                         equal = false;
3595                         break;
3596                 }
3597         }
3598
3599         if (!equal) {
3600                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3601                                         nphy->txiqlocal_bestc);
3602                 for (i = 0; i < 4; i++)
3603                         buffer[i] = 0;
3604                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3605                                         buffer);
3606                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3607                                         &nphy->txiqlocal_bestc[5]);
3608                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3609                                         &nphy->txiqlocal_bestc[5]);
3610         }
3611 }
3612
3613 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3614 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3615                         struct nphy_txgains target, u8 type, bool debug)
3616 {
3617         struct b43_phy_n *nphy = dev->phy.n;
3618         int i, j, index;
3619         u8 rfctl[2];
3620         u8 afectl_core;
3621         u16 tmp[6];
3622         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3623         u32 real, imag;
3624         enum ieee80211_band band;
3625
3626         u8 use;
3627         u16 cur_hpf;
3628         u16 lna[3] = { 3, 3, 1 };
3629         u16 hpf1[3] = { 7, 2, 0 };
3630         u16 hpf2[3] = { 2, 0, 0 };
3631         u32 power[3] = { };
3632         u16 gain_save[2];
3633         u16 cal_gain[2];
3634         struct nphy_iqcal_params cal_params[2];
3635         struct nphy_iq_est est;
3636         int ret = 0;
3637         bool playtone = true;
3638         int desired = 13;
3639
3640         b43_nphy_stay_in_carrier_search(dev, 1);
3641
3642         if (dev->phy.rev < 2)
3643                 b43_nphy_reapply_tx_cal_coeffs(dev);
3644         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3645         for (i = 0; i < 2; i++) {
3646                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3647                 cal_gain[i] = cal_params[i].cal_gain;
3648         }
3649         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3650
3651         for (i = 0; i < 2; i++) {
3652                 if (i == 0) {
3653                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3654                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3655                         afectl_core = B43_NPHY_AFECTL_C1;
3656                 } else {
3657                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3658                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3659                         afectl_core = B43_NPHY_AFECTL_C2;
3660                 }
3661
3662                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3663                 tmp[2] = b43_phy_read(dev, afectl_core);
3664                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3665                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3666                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3667
3668                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3669                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3670                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3671                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3672                                 (1 - i));
3673                 b43_phy_set(dev, afectl_core, 0x0006);
3674                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3675
3676                 band = b43_current_band(dev->wl);
3677
3678                 if (nphy->rxcalparams & 0xFF000000) {
3679                         if (band == IEEE80211_BAND_5GHZ)
3680                                 b43_phy_write(dev, rfctl[0], 0x140);
3681                         else
3682                                 b43_phy_write(dev, rfctl[0], 0x110);
3683                 } else {
3684                         if (band == IEEE80211_BAND_5GHZ)
3685                                 b43_phy_write(dev, rfctl[0], 0x180);
3686                         else
3687                                 b43_phy_write(dev, rfctl[0], 0x120);
3688                 }
3689
3690                 if (band == IEEE80211_BAND_5GHZ)
3691                         b43_phy_write(dev, rfctl[1], 0x148);
3692                 else
3693                         b43_phy_write(dev, rfctl[1], 0x114);
3694
3695                 if (nphy->rxcalparams & 0x10000) {
3696                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3697                                         (i + 1));
3698                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3699                                         (2 - i));
3700                 }
3701
3702                 for (j = 0; j < 4; j++) {
3703                         if (j < 3) {
3704                                 cur_lna = lna[j];
3705                                 cur_hpf1 = hpf1[j];
3706                                 cur_hpf2 = hpf2[j];
3707                         } else {
3708                                 if (power[1] > 10000) {
3709                                         use = 1;
3710                                         cur_hpf = cur_hpf1;
3711                                         index = 2;
3712                                 } else {
3713                                         if (power[0] > 10000) {
3714                                                 use = 1;
3715                                                 cur_hpf = cur_hpf1;
3716                                                 index = 1;
3717                                         } else {
3718                                                 index = 0;
3719                                                 use = 2;
3720                                                 cur_hpf = cur_hpf2;
3721                                         }
3722                                 }
3723                                 cur_lna = lna[index];
3724                                 cur_hpf1 = hpf1[index];
3725                                 cur_hpf2 = hpf2[index];
3726                                 cur_hpf += desired - hweight32(power[index]);
3727                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3728                                 if (use == 1)
3729                                         cur_hpf1 = cur_hpf;
3730                                 else
3731                                         cur_hpf2 = cur_hpf;
3732                         }
3733
3734                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3735                                         (cur_lna << 2));
3736                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3737                                                                         false);
3738                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3739                         b43_nphy_stop_playback(dev);
3740
3741                         if (playtone) {
3742                                 ret = b43_nphy_tx_tone(dev, 4000,
3743                                                 (nphy->rxcalparams & 0xFFFF),
3744                                                 false, false);
3745                                 playtone = false;
3746                         } else {
3747                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3748                                                         false, false);
3749                         }
3750
3751                         if (ret == 0) {
3752                                 if (j < 3) {
3753                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3754                                                                         false);
3755                                         if (i == 0) {
3756                                                 real = est.i0_pwr;
3757                                                 imag = est.q0_pwr;
3758                                         } else {
3759                                                 real = est.i1_pwr;
3760                                                 imag = est.q1_pwr;
3761                                         }
3762                                         power[i] = ((real + imag) / 1024) + 1;
3763                                 } else {
3764                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3765                                 }
3766                                 b43_nphy_stop_playback(dev);
3767                         }
3768
3769                         if (ret != 0)
3770                                 break;
3771                 }
3772
3773                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3774                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3775                 b43_phy_write(dev, rfctl[1], tmp[5]);
3776                 b43_phy_write(dev, rfctl[0], tmp[4]);
3777                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3778                 b43_phy_write(dev, afectl_core, tmp[2]);
3779                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3780
3781                 if (ret != 0)
3782                         break;
3783         }
3784
3785         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3786         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3787         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3788
3789         b43_nphy_stay_in_carrier_search(dev, 0);
3790
3791         return ret;
3792 }
3793
3794 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3795                         struct nphy_txgains target, u8 type, bool debug)
3796 {
3797         return -1;
3798 }
3799
3800 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3801 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3802                         struct nphy_txgains target, u8 type, bool debug)
3803 {
3804         if (dev->phy.rev >= 3)
3805                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3806         else
3807                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3808 }
3809
3810 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3811 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3812 {
3813         struct b43_phy *phy = &dev->phy;
3814         struct b43_phy_n *nphy = phy->n;
3815         /* u16 buf[16]; it's rev3+ */
3816
3817         nphy->phyrxchain = mask;
3818
3819         if (0 /* FIXME clk */)
3820                 return;
3821
3822         b43_mac_suspend(dev);
3823
3824         if (nphy->hang_avoid)
3825                 b43_nphy_stay_in_carrier_search(dev, true);
3826
3827         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3828                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3829
3830         if ((mask & 0x3) != 0x3) {
3831                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3832                 if (dev->phy.rev >= 3) {
3833                         /* TODO */
3834                 }
3835         } else {
3836                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3837                 if (dev->phy.rev >= 3) {
3838                         /* TODO */
3839                 }
3840         }
3841
3842         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3843
3844         if (nphy->hang_avoid)
3845                 b43_nphy_stay_in_carrier_search(dev, false);
3846
3847         b43_mac_enable(dev);
3848 }
3849
3850 /*
3851  * Init N-PHY
3852  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3853  */
3854 int b43_phy_initn(struct b43_wldev *dev)
3855 {
3856         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3857         struct b43_phy *phy = &dev->phy;
3858         struct b43_phy_n *nphy = phy->n;
3859         u8 tx_pwr_state;
3860         struct nphy_txgains target;
3861         u16 tmp;
3862         enum ieee80211_band tmp2;
3863         bool do_rssi_cal;
3864
3865         u16 clip[2];
3866         bool do_cal = false;
3867
3868         if ((dev->phy.rev >= 3) &&
3869            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3870            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3871                 switch (dev->dev->bus_type) {
3872 #ifdef CONFIG_B43_BCMA
3873                 case B43_BUS_BCMA:
3874                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3875                                       BCMA_CC_CHIPCTL, 0x40);
3876                         break;
3877 #endif
3878 #ifdef CONFIG_B43_SSB
3879                 case B43_BUS_SSB:
3880                         chipco_set32(&dev->dev->sdev->bus->chipco,
3881                                      SSB_CHIPCO_CHIPCTL, 0x40);
3882                         break;
3883 #endif
3884                 }
3885         }
3886         nphy->deaf_count = 0;
3887         b43_nphy_tables_init(dev);
3888         nphy->crsminpwr_adjusted = false;
3889         nphy->noisevars_adjusted = false;
3890
3891         /* Clear all overrides */
3892         if (dev->phy.rev >= 3) {
3893                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3894                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3895                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3896                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3897         } else {
3898                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3899         }
3900         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3901         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3902         if (dev->phy.rev < 6) {
3903                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3904                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3905         }
3906         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3907                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3908                        B43_NPHY_RFSEQMODE_TROVER));
3909         if (dev->phy.rev >= 3)
3910                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3911         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3912
3913         if (dev->phy.rev <= 2) {
3914                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3915                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3916                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3917                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3918         }
3919         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3920         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3921
3922         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
3923             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3924              dev->dev->board_type == 0x8B))
3925                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3926         else
3927                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3928         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3929         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3930         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3931
3932         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3933         b43_nphy_update_txrx_chain(dev);
3934
3935         if (phy->rev < 2) {
3936                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3937                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3938         }
3939
3940         tmp2 = b43_current_band(dev->wl);
3941         if (b43_nphy_ipa(dev)) {
3942                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3943                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3944                                 nphy->papd_epsilon_offset[0] << 7);
3945                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3946                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3947                                 nphy->papd_epsilon_offset[1] << 7);
3948                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3949         } else if (phy->rev >= 5) {
3950                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3951         }
3952
3953         b43_nphy_workarounds(dev);
3954
3955         /* Reset CCA, in init code it differs a little from standard way */
3956         b43_phy_force_clock(dev, 1);
3957         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3958         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3959         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3960         b43_phy_force_clock(dev, 0);
3961
3962         b43_mac_phy_clock_set(dev, true);
3963
3964         b43_nphy_pa_override(dev, false);
3965         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3966         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3967         b43_nphy_pa_override(dev, true);
3968
3969         b43_nphy_classifier(dev, 0, 0);
3970         b43_nphy_read_clip_detection(dev, clip);
3971         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3972                 b43_nphy_bphy_init(dev);
3973
3974         tx_pwr_state = nphy->txpwrctrl;
3975         b43_nphy_tx_power_ctrl(dev, false);
3976         b43_nphy_tx_power_fix(dev);
3977         /* TODO N PHY TX Power Control Idle TSSI */
3978         /* TODO N PHY TX Power Control Setup */
3979         b43_nphy_tx_gain_table_upload(dev);
3980
3981         if (nphy->phyrxchain != 3)
3982                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3983         if (nphy->mphase_cal_phase_id > 0)
3984                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3985
3986         do_rssi_cal = false;
3987         if (phy->rev >= 3) {
3988                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3989                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3990                 else
3991                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3992
3993                 if (do_rssi_cal)
3994                         b43_nphy_rssi_cal(dev);
3995                 else
3996                         b43_nphy_restore_rssi_cal(dev);
3997         } else {
3998                 b43_nphy_rssi_cal(dev);
3999         }
4000
4001         if (!((nphy->measure_hold & 0x6) != 0)) {
4002                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4003                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
4004                 else
4005                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
4006
4007                 if (nphy->mute)
4008                         do_cal = false;
4009
4010                 if (do_cal) {
4011                         target = b43_nphy_get_tx_gains(dev);
4012
4013                         if (nphy->antsel_type == 2)
4014                                 b43_nphy_superswitch_init(dev, true);
4015                         if (nphy->perical != 2) {
4016                                 b43_nphy_rssi_cal(dev);
4017                                 if (phy->rev >= 3) {
4018                                         nphy->cal_orig_pwr_idx[0] =
4019                                             nphy->txpwrindex[0].index_internal;
4020                                         nphy->cal_orig_pwr_idx[1] =
4021                                             nphy->txpwrindex[1].index_internal;
4022                                         /* TODO N PHY Pre Calibrate TX Gain */
4023                                         target = b43_nphy_get_tx_gains(dev);
4024                                 }
4025                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
4026                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
4027                                                 b43_nphy_save_cal(dev);
4028                         } else if (nphy->mphase_cal_phase_id == 0)
4029                                 ;/* N PHY Periodic Calibration with arg 3 */
4030                 } else {
4031                         b43_nphy_restore_cal(dev);
4032                 }
4033         }
4034
4035         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
4036         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
4037         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
4038         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
4039         if (phy->rev >= 3 && phy->rev <= 6)
4040                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
4041         b43_nphy_tx_lp_fbw(dev);
4042         if (phy->rev >= 3)
4043                 b43_nphy_spur_workaround(dev);
4044
4045         return 0;
4046 }
4047
4048 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
4049 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
4050 {
4051 #ifdef CONFIG_B43_BCMA
4052         struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc;
4053         u32 pmu_ctl;
4054         if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
4055                 if (avoid) {
4056                         bcma_chipco_pll_write(cc, 0x0, 0x11500010);
4057                         bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
4058                         bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
4059                         bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4060                         bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
4061                         bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4062                 } else {
4063                         bcma_chipco_pll_write(cc, 0x0, 0x11100010);
4064                         bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
4065                         bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
4066                         bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4067                         bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4068                         bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4069                 }
4070                 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4071         } else if (dev->dev->chip_id == 0x4716) {
4072                 if (avoid) {
4073                         bcma_chipco_pll_write(cc, 0x0, 0x11500060);
4074                         bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
4075                         bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
4076                         bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4077                         bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
4078                         bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4079                 } else {
4080                         bcma_chipco_pll_write(cc, 0x0, 0x11100060);
4081                         bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
4082                         bcma_chipco_pll_write(cc, 0x2, 0x03000000);
4083                         bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4084                         bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4085                         bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4086                 }
4087                 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
4088         } else if (dev->dev->chip_id == 0x4322 || dev->dev->chip_id == 0x4340 ||
4089                    dev->dev->chip_id == 0x4341) {
4090                 bcma_chipco_pll_write(cc, 0x0, 0x11100070);
4091                 bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
4092                 bcma_chipco_pll_write(cc, 0x5, 0x88888854);
4093                 if (avoid)
4094                         bcma_chipco_pll_write(cc, 0x2, 0x05201828);
4095                 else
4096                         bcma_chipco_pll_write(cc, 0x2, 0x05001828);
4097                 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4098         } else {
4099                 return;
4100         }
4101         bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
4102 #else
4103         return;
4104 #endif
4105 }
4106
4107 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
4108 static void b43_nphy_channel_setup(struct b43_wldev *dev,
4109                                 const struct b43_phy_n_sfo_cfg *e,
4110                                 struct ieee80211_channel *new_channel)
4111 {
4112         struct b43_phy *phy = &dev->phy;
4113         struct b43_phy_n *nphy = dev->phy.n;
4114         int ch = new_channel->hw_value;
4115
4116         u16 old_band_5ghz;
4117         u32 tmp32;
4118
4119         old_band_5ghz =
4120                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
4121         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
4122                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4123                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4124                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
4125                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4126                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
4127         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
4128                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
4129                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4130                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4131                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
4132                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4133         }
4134
4135         b43_chantab_phy_upload(dev, e);
4136
4137         if (new_channel->hw_value == 14) {
4138                 b43_nphy_classifier(dev, 2, 0);
4139                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
4140         } else {
4141                 b43_nphy_classifier(dev, 2, 2);
4142                 if (new_channel->band == IEEE80211_BAND_2GHZ)
4143                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
4144         }
4145
4146         if (!nphy->txpwrctrl)
4147                 b43_nphy_tx_power_fix(dev);
4148
4149         if (dev->phy.rev < 3)
4150                 b43_nphy_adjust_lna_gain_table(dev);
4151
4152         b43_nphy_tx_lp_fbw(dev);
4153
4154         if (dev->phy.rev >= 3 &&
4155             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
4156                 bool avoid = false;
4157                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
4158                         avoid = true;
4159                 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
4160                         if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
4161                                 avoid = true;
4162                 } else { /* 40MHz */
4163                         if (nphy->aband_spurwar_en &&
4164                             (ch == 38 || ch == 102 || ch == 118))
4165                                 avoid = dev->dev->chip_id == 0x4716;
4166                 }
4167
4168                 b43_nphy_pmu_spur_avoid(dev, avoid);
4169
4170                 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
4171                     dev->dev->chip_id == 43225) {
4172                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
4173                                     avoid ? 0x5341 : 0x8889);
4174                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
4175                 }
4176
4177                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
4178                         ; /* TODO: reset PLL */
4179
4180                 if (avoid)
4181                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
4182                 else
4183                         b43_phy_mask(dev, B43_NPHY_BBCFG,
4184                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4185
4186                 b43_nphy_reset_cca(dev);
4187
4188                 /* wl sets useless phy_isspuravoid here */
4189         }
4190
4191         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
4192
4193         if (phy->rev >= 3)
4194                 b43_nphy_spur_workaround(dev);
4195 }
4196
4197 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
4198 static int b43_nphy_set_channel(struct b43_wldev *dev,
4199                                 struct ieee80211_channel *channel,
4200                                 enum nl80211_channel_type channel_type)
4201 {
4202         struct b43_phy *phy = &dev->phy;
4203
4204         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4205         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
4206
4207         u8 tmp;
4208
4209         if (dev->phy.rev >= 3) {
4210                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4211                                                         channel->center_freq);
4212                 if (!tabent_r3)
4213                         return -ESRCH;
4214         } else {
4215                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4216                                                         channel->hw_value);
4217                 if (!tabent_r2)
4218                         return -ESRCH;
4219         }
4220
4221         /* Channel is set later in common code, but we need to set it on our
4222            own to let this function's subcalls work properly. */
4223         phy->channel = channel->hw_value;
4224         phy->channel_freq = channel->center_freq;
4225
4226         if (b43_channel_type_is_40mhz(phy->channel_type) !=
4227                 b43_channel_type_is_40mhz(channel_type))
4228                 ; /* TODO: BMAC BW Set (channel_type) */
4229
4230         if (channel_type == NL80211_CHAN_HT40PLUS)
4231                 b43_phy_set(dev, B43_NPHY_RXCTL,
4232                                 B43_NPHY_RXCTL_BSELU20);
4233         else if (channel_type == NL80211_CHAN_HT40MINUS)
4234                 b43_phy_mask(dev, B43_NPHY_RXCTL,
4235                                 ~B43_NPHY_RXCTL_BSELU20);
4236
4237         if (dev->phy.rev >= 3) {
4238                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
4239                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
4240                 b43_radio_2056_setup(dev, tabent_r3);
4241                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
4242         } else {
4243                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
4244                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
4245                 b43_radio_2055_setup(dev, tabent_r2);
4246                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
4247         }
4248
4249         return 0;
4250 }
4251
4252 static int b43_nphy_op_allocate(struct b43_wldev *dev)
4253 {
4254         struct b43_phy_n *nphy;
4255
4256         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4257         if (!nphy)
4258                 return -ENOMEM;
4259         dev->phy.n = nphy;
4260
4261         return 0;
4262 }
4263
4264 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4265 {
4266         struct b43_phy *phy = &dev->phy;
4267         struct b43_phy_n *nphy = phy->n;
4268         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4269
4270         memset(nphy, 0, sizeof(*nphy));
4271
4272         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
4273         nphy->spur_avoid = (phy->rev >= 3) ?
4274                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
4275         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4276         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4277         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
4278         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
4279         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4280          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4281         nphy->tx_pwr_idx[0] = 128;
4282         nphy->tx_pwr_idx[1] = 128;
4283
4284         /* Hardware TX power control and 5GHz power gain */
4285         nphy->txpwrctrl = false;
4286         nphy->pwg_gain_5ghz = false;
4287         if (dev->phy.rev >= 3 ||
4288             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4289              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4290                 nphy->txpwrctrl = true;
4291                 nphy->pwg_gain_5ghz = true;
4292         } else if (sprom->revision >= 4) {
4293                 if (dev->phy.rev >= 2 &&
4294                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4295                         nphy->txpwrctrl = true;
4296 #ifdef CONFIG_B43_SSB
4297                         if (dev->dev->bus_type == B43_BUS_SSB &&
4298                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4299                                 struct pci_dev *pdev =
4300                                         dev->dev->sdev->bus->host_pci;
4301                                 if (pdev->device == 0x4328 ||
4302                                     pdev->device == 0x432a)
4303                                         nphy->pwg_gain_5ghz = true;
4304                         }
4305 #endif
4306                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4307                         nphy->pwg_gain_5ghz = true;
4308                 }
4309         }
4310
4311         if (dev->phy.rev >= 3) {
4312                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4313                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4314         }
4315 }
4316
4317 static void b43_nphy_op_free(struct b43_wldev *dev)
4318 {
4319         struct b43_phy *phy = &dev->phy;
4320         struct b43_phy_n *nphy = phy->n;
4321
4322         kfree(nphy);
4323         phy->n = NULL;
4324 }
4325
4326 static int b43_nphy_op_init(struct b43_wldev *dev)
4327 {
4328         return b43_phy_initn(dev);
4329 }
4330
4331 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4332 {
4333 #if B43_DEBUG
4334         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4335                 /* OFDM registers are onnly available on A/G-PHYs */
4336                 b43err(dev->wl, "Invalid OFDM PHY access at "
4337                        "0x%04X on N-PHY\n", offset);
4338                 dump_stack();
4339         }
4340         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4341                 /* Ext-G registers are only available on G-PHYs */
4342                 b43err(dev->wl, "Invalid EXT-G PHY access at "
4343                        "0x%04X on N-PHY\n", offset);
4344                 dump_stack();
4345         }
4346 #endif /* B43_DEBUG */
4347 }
4348
4349 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4350 {
4351         check_phyreg(dev, reg);
4352         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4353         return b43_read16(dev, B43_MMIO_PHY_DATA);
4354 }
4355
4356 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4357 {
4358         check_phyreg(dev, reg);
4359         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4360         b43_write16(dev, B43_MMIO_PHY_DATA, value);
4361 }
4362
4363 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4364                                  u16 set)
4365 {
4366         check_phyreg(dev, reg);
4367         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4368         b43_write16(dev, B43_MMIO_PHY_DATA,
4369                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4370 }
4371
4372 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4373 {
4374         /* Register 1 is a 32-bit register. */
4375         B43_WARN_ON(reg == 1);
4376         /* N-PHY needs 0x100 for read access */
4377         reg |= 0x100;
4378
4379         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4380         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4381 }
4382
4383 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4384 {
4385         /* Register 1 is a 32-bit register. */
4386         B43_WARN_ON(reg == 1);
4387
4388         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4389         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4390 }
4391
4392 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4393 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4394                                         bool blocked)
4395 {
4396         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4397                 b43err(dev->wl, "MAC not suspended\n");
4398
4399         if (blocked) {
4400                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4401                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4402                 if (dev->phy.rev >= 3) {
4403                         b43_radio_mask(dev, 0x09, ~0x2);
4404
4405                         b43_radio_write(dev, 0x204D, 0);
4406                         b43_radio_write(dev, 0x2053, 0);
4407                         b43_radio_write(dev, 0x2058, 0);
4408                         b43_radio_write(dev, 0x205E, 0);
4409                         b43_radio_mask(dev, 0x2062, ~0xF0);
4410                         b43_radio_write(dev, 0x2064, 0);
4411
4412                         b43_radio_write(dev, 0x304D, 0);
4413                         b43_radio_write(dev, 0x3053, 0);
4414                         b43_radio_write(dev, 0x3058, 0);
4415                         b43_radio_write(dev, 0x305E, 0);
4416                         b43_radio_mask(dev, 0x3062, ~0xF0);
4417                         b43_radio_write(dev, 0x3064, 0);
4418                 }
4419         } else {
4420                 if (dev->phy.rev >= 3) {
4421                         b43_radio_init2056(dev);
4422                         b43_switch_channel(dev, dev->phy.channel);
4423                 } else {
4424                         b43_radio_init2055(dev);
4425                 }
4426         }
4427 }
4428
4429 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4430 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4431 {
4432         u16 override = on ? 0x0 : 0x7FFF;
4433         u16 core = on ? 0xD : 0x00FD;
4434
4435         if (dev->phy.rev >= 3) {
4436                 if (on) {
4437                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4438                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4439                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4440                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4441                 } else {
4442                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4443                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4444                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4445                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4446                 }
4447         } else {
4448                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4449         }
4450 }
4451
4452 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4453                                       unsigned int new_channel)
4454 {
4455         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4456         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4457
4458         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4459                 if ((new_channel < 1) || (new_channel > 14))
4460                         return -EINVAL;
4461         } else {
4462                 if (new_channel > 200)
4463                         return -EINVAL;
4464         }
4465
4466         return b43_nphy_set_channel(dev, channel, channel_type);
4467 }
4468
4469 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4470 {
4471         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4472                 return 1;
4473         return 36;
4474 }
4475
4476 const struct b43_phy_operations b43_phyops_n = {
4477         .allocate               = b43_nphy_op_allocate,
4478         .free                   = b43_nphy_op_free,
4479         .prepare_structs        = b43_nphy_op_prepare_structs,
4480         .init                   = b43_nphy_op_init,
4481         .phy_read               = b43_nphy_op_read,
4482         .phy_write              = b43_nphy_op_write,
4483         .phy_maskset            = b43_nphy_op_maskset,
4484         .radio_read             = b43_nphy_op_radio_read,
4485         .radio_write            = b43_nphy_op_radio_write,
4486         .software_rfkill        = b43_nphy_op_software_rfkill,
4487         .switch_analog          = b43_nphy_op_switch_analog,
4488         .switch_channel         = b43_nphy_op_switch_channel,
4489         .get_default_chan       = b43_nphy_op_get_default_chan,
4490         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4491         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4492 };