drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
   7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
   8
   9   This program is free software; you can redistribute it and/or modify
  10   it under the terms of the GNU General Public License as published by
  11   the Free Software Foundation; either version 2 of the License, or
  12   (at your option) any later version.
  13
  14   This program is distributed in the hope that it will be useful,
  15   but WITHOUT ANY WARRANTY; without even the implied warranty of
  16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17   GNU General Public License for more details.
  18
  19   You should have received a copy of the GNU General Public License
  20   along with this program; see the file COPYING.  If not, write to
  21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  22   Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/types.h>
  29
  30 #include "b43.h"
  31 #include "phy_n.h"
  32 #include "tables_nphy.h"
  33 #include "radio_2055.h"
  34 #include "radio_2056.h"
  35 #include "main.h"
  36
  37 struct nphy_txgains {
  38         u16 txgm[2];
  39         u16 pga[2];
  40         u16 pad[2];
  41         u16 ipa[2];
  42 };
  43
  44 struct nphy_iqcal_params {
  45         u16 txgm;
  46         u16 pga;
  47         u16 pad;
  48         u16 ipa;
  49         u16 cal_gain;
  50         u16 ncorr[5];
  51 };
  52
  53 struct nphy_iq_est {
  54         s32 iq0_prod;
  55         u32 i0_pwr;
  56         u32 q0_pwr;
  57         s32 iq1_prod;
  58         u32 i1_pwr;
  59         u32 q1_pwr;
  60 };
  61
  62 enum b43_nphy_rf_sequence {
  63         B43_RFSEQ_RX2TX,
  64         B43_RFSEQ_TX2RX,
  65         B43_RFSEQ_RESET2RX,
  66         B43_RFSEQ_UPDATE_GAINH,
  67         B43_RFSEQ_UPDATE_GAINL,
  68         B43_RFSEQ_UPDATE_GAINU,
  69 };
  70
  71 enum b43_nphy_rssi_type {
  72         B43_NPHY_RSSI_X = 0,
  73         B43_NPHY_RSSI_Y,
  74         B43_NPHY_RSSI_Z,
  75         B43_NPHY_RSSI_PWRDET,
  76         B43_NPHY_RSSI_TSSI_I,
  77         B43_NPHY_RSSI_TSSI_Q,
  78         B43_NPHY_RSSI_TBD,
  79 };
  80
  81 /* TODO: reorder functions */
  82 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
  83                                                 bool enable);
  84 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  85                                         u8 *events, u8 *delays, u8 length);
  86 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  87                                        enum b43_nphy_rf_sequence seq);
  88 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  89                                                 u16 value, u8 core, bool off);
  90 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  91                                                 u16 value, u8 core);
  92 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev);
  93
  94 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
  95 {
  96         enum ieee80211_band band = b43_current_band(dev->wl);
  97         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
  98                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
  99 }
 100
 101 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
 102 {//TODO
 103 }
 104
 105 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
 106 {//TODO
 107 }
 108
 109 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
 110                                                         bool ignore_tssi)
 111 {//TODO
 112         return B43_TXPWR_RES_DONE;
 113 }
 114
 115 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 116                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 117 {
 118         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 119         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 120         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 121         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 122         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 123
 124         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 125         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 126         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 127         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 128         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 129
 130         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 131         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 132         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 133         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 134         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 135
 136         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 137         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 138         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 139         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 140         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 141
 142         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 143         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 144         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 145         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 146         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 147
 148         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 149         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 150 }
 151
 152 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
 153                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 154 {
 155         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
 156         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
 157         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
 158         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
 159         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
 160         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
 161                                         e->radio_syn_pll_loopfilter1);
 162         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
 163                                         e->radio_syn_pll_loopfilter2);
 164         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
 165                                         e->radio_syn_pll_loopfilter3);
 166         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
 167                                         e->radio_syn_pll_loopfilter4);
 168         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
 169                                         e->radio_syn_pll_loopfilter5);
 170         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
 171                                         e->radio_syn_reserved_addr27);
 172         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
 173                                         e->radio_syn_reserved_addr28);
 174         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
 175                                         e->radio_syn_reserved_addr29);
 176         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
 177                                         e->radio_syn_logen_vcobuf1);
 178         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
 179         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
 180         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
 181
 182         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
 183                                         e->radio_rx0_lnaa_tune);
 184         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
 185                                         e->radio_rx0_lnag_tune);
 186
 187         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
 188                                         e->radio_tx0_intpaa_boost_tune);
 189         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
 190                                         e->radio_tx0_intpag_boost_tune);
 191         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
 192                                         e->radio_tx0_pada_boost_tune);
 193         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
 194                                         e->radio_tx0_padg_boost_tune);
 195         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
 196                                         e->radio_tx0_pgaa_boost_tune);
 197         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
 198                                         e->radio_tx0_pgag_boost_tune);
 199         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
 200                                         e->radio_tx0_mixa_boost_tune);
 201         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
 202                                         e->radio_tx0_mixg_boost_tune);
 203
 204         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
 205                                         e->radio_rx1_lnaa_tune);
 206         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
 207                                         e->radio_rx1_lnag_tune);
 208
 209         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
 210                                         e->radio_tx1_intpaa_boost_tune);
 211         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
 212                                         e->radio_tx1_intpag_boost_tune);
 213         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
 214                                         e->radio_tx1_pada_boost_tune);
 215         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
 216                                         e->radio_tx1_padg_boost_tune);
 217         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
 218                                         e->radio_tx1_pgaa_boost_tune);
 219         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
 220                                         e->radio_tx1_pgag_boost_tune);
 221         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
 222                                         e->radio_tx1_mixa_boost_tune);
 223         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
 224                                         e->radio_tx1_mixg_boost_tune);
 225 }
 226
 227 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
 228 static void b43_radio_2056_setup(struct b43_wldev *dev,
 229                                 const struct b43_nphy_channeltab_entry_rev3 *e)
 230 {
 231         B43_WARN_ON(dev->phy.rev < 3);
 232
 233         b43_chantab_radio_2056_upload(dev, e);
 234         /* TODO */
 235         udelay(50);
 236         /* VCO calibration */
 237         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
 238         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 239         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
 240         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
 241         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
 242         udelay(300);
 243 }
 244
 245 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 246                                    const struct b43_phy_n_sfo_cfg *e)
 247 {
 248         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 249         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 250         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 251         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 252         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 253         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 254 }
 255
 256 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
 257 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
 258 {
 259         struct b43_phy_n *nphy = dev->phy.n;
 260         u8 i;
 261         u16 bmask, val, tmp;
 262         enum ieee80211_band band = b43_current_band(dev->wl);
 263
 264         if (nphy->hang_avoid)
 265                 b43_nphy_stay_in_carrier_search(dev, 1);
 266
 267         nphy->txpwrctrl = enable;
 268         if (!enable) {
 269                 if (dev->phy.rev >= 3 &&
 270                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
 271                      (B43_NPHY_TXPCTL_CMD_COEFF |
 272                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
 273                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
 274                         /* We disable enabled TX pwr ctl, save it's state */
 275                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
 276                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
 277                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
 278                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
 279                 }
 280
 281                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
 282                 for (i = 0; i < 84; i++)
 283                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 284
 285                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
 286                 for (i = 0; i < 84; i++)
 287                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
 288
 289                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 290                 if (dev->phy.rev >= 3)
 291                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 292                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
 293
 294                 if (dev->phy.rev >= 3) {
 295                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 296                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 297                 } else {
 298                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 299                 }
 300
 301                 if (dev->phy.rev == 2)
 302                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 303                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
 304                 else if (dev->phy.rev < 2)
 305                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 306                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
 307
 308                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
 309                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
 310         } else {
 311                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
 312                                     nphy->adj_pwr_tbl);
 313                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
 314                                     nphy->adj_pwr_tbl);
 315
 316                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
 317                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 318                 /* wl does useless check for "enable" param here */
 319                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
 320                 if (dev->phy.rev >= 3) {
 321                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 322                         if (val)
 323                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
 324                 }
 325                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
 326
 327                 if (band == IEEE80211_BAND_5GHZ) {
 328                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
 329                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
 330                         if (dev->phy.rev > 1)
 331                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
 332                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
 333                                                 0x64);
 334                 }
 335
 336                 if (dev->phy.rev >= 3) {
 337                         if (nphy->tx_pwr_idx[0] != 128 &&
 338                             nphy->tx_pwr_idx[1] != 128) {
 339                                 /* Recover TX pwr ctl state */
 340                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
 341                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
 342                                                 nphy->tx_pwr_idx[0]);
 343                                 if (dev->phy.rev > 1)
 344                                         b43_phy_maskset(dev,
 345                                                 B43_NPHY_TXPCTL_INIT,
 346                                                 ~0xff, nphy->tx_pwr_idx[1]);
 347                         }
 348                 }
 349
 350                 if (dev->phy.rev >= 3) {
 351                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
 352                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
 353                 } else {
 354                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
 355                 }
 356
 357                 if (dev->phy.rev == 2)
 358                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
 359                 else if (dev->phy.rev < 2)
 360                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
 361
 362                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
 363                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
 364
 365                 if (b43_nphy_ipa(dev)) {
 366                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
 367                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
 368                 }
 369         }
 370
 371         if (nphy->hang_avoid)
 372                 b43_nphy_stay_in_carrier_search(dev, 0);
 373 }
 374
 375 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
 376 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 377 {
 378         struct b43_phy_n *nphy = dev->phy.n;
 379         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 380
 381         u8 txpi[2], bbmult, i;
 382         u16 tmp, radio_gain, dac_gain;
 383         u16 freq = dev->phy.channel_freq;
 384         u32 txgain;
 385         /* u32 gaintbl; rev3+ */
 386
 387         if (nphy->hang_avoid)
 388                 b43_nphy_stay_in_carrier_search(dev, 1);
 389
 390         if (dev->phy.rev >= 3) {
 391                 txpi[0] = 40;
 392                 txpi[1] = 40;
 393         } else if (sprom->revision < 4) {
 394                 txpi[0] = 72;
 395                 txpi[1] = 72;
 396         } else {
 397                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 398                         txpi[0] = sprom->txpid2g[0];
 399                         txpi[1] = sprom->txpid2g[1];
 400                 } else if (freq >= 4900 && freq < 5100) {
 401                         txpi[0] = sprom->txpid5gl[0];
 402                         txpi[1] = sprom->txpid5gl[1];
 403                 } else if (freq >= 5100 && freq < 5500) {
 404                         txpi[0] = sprom->txpid5g[0];
 405                         txpi[1] = sprom->txpid5g[1];
 406                 } else if (freq >= 5500) {
 407                         txpi[0] = sprom->txpid5gh[0];
 408                         txpi[1] = sprom->txpid5gh[1];
 409                 } else {
 410                         txpi[0] = 91;
 411                         txpi[1] = 91;
 412                 }
 413         }
 414
 415         /*
 416         for (i = 0; i < 2; i++) {
 417                 nphy->txpwrindex[i].index_internal = txpi[i];
 418                 nphy->txpwrindex[i].index_internal_save = txpi[i];
 419         }
 420         */
 421
 422         for (i = 0; i < 2; i++) {
 423                 if (dev->phy.rev >= 3) {
 424                         /* FIXME: support 5GHz */
 425                         txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
 426                         radio_gain = (txgain >> 16) & 0x1FFFF;
 427                 } else {
 428                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
 429                         radio_gain = (txgain >> 16) & 0x1FFF;
 430                 }
 431
 432                 dac_gain = (txgain >> 8) & 0x3F;
 433                 bbmult = txgain & 0xFF;
 434
 435                 if (dev->phy.rev >= 3) {
 436                         if (i == 0)
 437                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
 438                         else
 439                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
 440                 } else {
 441                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
 442                 }
 443
 444                 if (i == 0)
 445                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
 446                 else
 447                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
 448
 449                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
 450
 451                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
 452                 if (i == 0)
 453                         tmp = (tmp & 0x00FF) | (bbmult << 8);
 454                 else
 455                         tmp = (tmp & 0xFF00) | bbmult;
 456                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
 457
 458                 if (b43_nphy_ipa(dev)) {
 459                         u32 tmp32;
 460                         u16 reg = (i == 0) ?
 461                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
 462                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, txpi[i]));
 463                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
 464                         b43_phy_set(dev, reg, 0x4);
 465                 }
 466         }
 467
 468         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
 469
 470         if (nphy->hang_avoid)
 471                 b43_nphy_stay_in_carrier_search(dev, 0);
 472 }
 473
 474 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
 475 {
 476         struct b43_phy *phy = &dev->phy;
 477
 478         const u32 *table = NULL;
 479 #if 0
 480         TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
 481         u32 rfpwr_offset;
 482         u8 pga_gain;
 483         int i;
 484 #endif
 485
 486         if (phy->rev >= 3) {
 487                 if (b43_nphy_ipa(dev)) {
 488                         table = b43_nphy_get_ipa_gain_table(dev);
 489                 } else {
 490                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
 491                                 if (phy->rev == 3)
 492                                         table = b43_ntab_tx_gain_rev3_5ghz;
 493                                 if (phy->rev == 4)
 494                                         table = b43_ntab_tx_gain_rev4_5ghz;
 495                                 else
 496                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
 497                         } else {
 498                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
 499                         }
 500                 }
 501         } else {
 502                 table = b43_ntab_tx_gain_rev0_1_2;
 503         }
 504         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
 505         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
 506
 507         if (phy->rev >= 3) {
 508 #if 0
 509                 nphy->gmval = (table[0] >> 16) & 0x7000;
 510
 511                 for (i = 0; i < 128; i++) {
 512                         pga_gain = (table[i] >> 24) & 0xF;
 513                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 514                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
 515                         else
 516                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
 517                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
 518                                        rfpwr_offset);
 519                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
 520                                        rfpwr_offset);
 521                 }
 522 #endif
 523         }
 524 }
 525
 526 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 527 static void b43_radio_2055_setup(struct b43_wldev *dev,
 528                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 529 {
 530         B43_WARN_ON(dev->phy.rev >= 3);
 531
 532         b43_chantab_radio_upload(dev, e);
 533         udelay(50);
 534         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 535         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 536         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 537         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 538         udelay(300);
 539 }
 540
 541 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 542 {
 543         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 544                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 545         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 546                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 547                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 548         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 549                     B43_NPHY_RFCTL_CMD_PORFORCE);
 550 }
 551
 552 static void b43_radio_init2055_post(struct b43_wldev *dev)
 553 {
 554         struct b43_phy_n *nphy = dev->phy.n;
 555         struct ssb_sprom *sprom = dev->dev->bus_sprom;
 556         int i;
 557         u16 val;
 558         bool workaround = false;
 559
 560         if (sprom->revision < 4)
 561                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
 562                               && dev->dev->board_type == 0x46D
 563                               && dev->dev->board_rev >= 0x41);
 564         else
 565                 workaround =
 566                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 567
 568         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 569         if (workaround) {
 570                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 571                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 572         }
 573         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 574         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 575         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 576         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 577         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 578         msleep(1);
 579         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 580         for (i = 0; i < 200; i++) {
 581                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 582                 if (val & 0x80) {
 583                         i = 0;
 584                         break;
 585                 }
 586                 udelay(10);
 587         }
 588         if (i)
 589                 b43err(dev->wl, "radio post init timeout\n");
 590         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 591         b43_switch_channel(dev, dev->phy.channel);
 592         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 593         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 594         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 595         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 596         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 597         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 598         if (!nphy->gain_boost) {
 599                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 600                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 601         } else {
 602                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 603                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 604         }
 605         udelay(2);
 606 }
 607
 608 /*
 609  * Initialize a Broadcom 2055 N-radio
 610  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 611  */
 612 static void b43_radio_init2055(struct b43_wldev *dev)
 613 {
 614         b43_radio_init2055_pre(dev);
 615         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 616                 /* Follow wl, not specs. Do not force uploading all regs */
 617                 b2055_upload_inittab(dev, 0, 0);
 618         } else {
 619                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 620                 b2055_upload_inittab(dev, ghz5, 0);
 621         }
 622         b43_radio_init2055_post(dev);
 623 }
 624
 625 static void b43_radio_init2056_pre(struct b43_wldev *dev)
 626 {
 627         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 628                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
 629         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
 630         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 631                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
 632         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 633                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
 634         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 635                     B43_NPHY_RFCTL_CMD_CHIP0PU);
 636 }
 637
 638 static void b43_radio_init2056_post(struct b43_wldev *dev)
 639 {
 640         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
 641         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
 642         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
 643         msleep(1);
 644         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
 645         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
 646         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
 647         /*
 648         if (nphy->init_por)
 649                 Call Radio 2056 Recalibrate
 650         */
 651 }
 652
 653 /*
 654  * Initialize a Broadcom 2056 N-radio
 655  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 656  */
 657 static void b43_radio_init2056(struct b43_wldev *dev)
 658 {
 659         b43_radio_init2056_pre(dev);
 660         b2056_upload_inittabs(dev, 0, 0);
 661         b43_radio_init2056_post(dev);
 662 }
 663
 664 /*
 665  * Upload the N-PHY tables.
 666  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 667  */
 668 static void b43_nphy_tables_init(struct b43_wldev *dev)
 669 {
 670         if (dev->phy.rev < 3)
 671                 b43_nphy_rev0_1_2_tables_init(dev);
 672         else
 673                 b43_nphy_rev3plus_tables_init(dev);
 674 }
 675
 676 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 677 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 678 {
 679         struct b43_phy_n *nphy = dev->phy.n;
 680         enum ieee80211_band band;
 681         u16 tmp;
 682
 683         if (!enable) {
 684                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 685                                                        B43_NPHY_RFCTL_INTC1);
 686                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 687                                                        B43_NPHY_RFCTL_INTC2);
 688                 band = b43_current_band(dev->wl);
 689                 if (dev->phy.rev >= 3) {
 690                         if (band == IEEE80211_BAND_5GHZ)
 691                                 tmp = 0x600;
 692                         else
 693                                 tmp = 0x480;
 694                 } else {
 695                         if (band == IEEE80211_BAND_5GHZ)
 696                                 tmp = 0x180;
 697                         else
 698                                 tmp = 0x120;
 699                 }
 700                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 701                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 702         } else {
 703                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 704                                 nphy->rfctrl_intc1_save);
 705                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 706                                 nphy->rfctrl_intc2_save);
 707         }
 708 }
 709
 710 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 711 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 712 {
 713         u16 tmp;
 714
 715         if (dev->phy.rev >= 3) {
 716                 if (b43_nphy_ipa(dev)) {
 717                         tmp = 4;
 718                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 719                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 720                 }
 721
 722                 tmp = 1;
 723                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 724                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 725         }
 726 }
 727
 728 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 729 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 730 {
 731         u16 bbcfg;
 732
 733         b43_phy_force_clock(dev, 1);
 734         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 735         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 736         udelay(1);
 737         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 738         b43_phy_force_clock(dev, 0);
 739         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 740 }
 741
 742 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 743 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 744 {
 745         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 746
 747         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 748         if (preamble == 1)
 749                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 750         else
 751                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 752
 753         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 754 }
 755
 756 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 757 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 758 {
 759         struct b43_phy_n *nphy = dev->phy.n;
 760
 761         bool override = false;
 762         u16 chain = 0x33;
 763
 764         if (nphy->txrx_chain == 0) {
 765                 chain = 0x11;
 766                 override = true;
 767         } else if (nphy->txrx_chain == 1) {
 768                 chain = 0x22;
 769                 override = true;
 770         }
 771
 772         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 773                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 774                         chain);
 775
 776         if (override)
 777                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 778                                 B43_NPHY_RFSEQMODE_CAOVER);
 779         else
 780                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 781                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 782 }
 783
 784 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 785 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 786                                 u16 samps, u8 time, bool wait)
 787 {
 788         int i;
 789         u16 tmp;
 790
 791         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 792         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 793         if (wait)
 794                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 795         else
 796                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 797
 798         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 799
 800         for (i = 1000; i; i--) {
 801                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 802                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 803                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 804                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 805                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 806                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 807                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 808                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 809
 810                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 811                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 812                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 813                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 814                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 815                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 816                         return;
 817                 }
 818                 udelay(10);
 819         }
 820         memset(est, 0, sizeof(*est));
 821 }
 822
 823 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 824 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 825                                         struct b43_phy_n_iq_comp *pcomp)
 826 {
 827         if (write) {
 828                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 829                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 830                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 831                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 832         } else {
 833                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 834                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 835                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 836                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 837         }
 838 }
 839
 840 #if 0
 841 /* Ready but not used anywhere */
 842 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 843 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 844 {
 845         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 846
 847         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 848         if (core == 0) {
 849                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 850                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 851         } else {
 852                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 853                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 854         }
 855         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 856         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 857         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 858         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 859         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 860         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 861         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 862         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 863 }
 864
 865 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 866 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 867 {
 868         u8 rxval, txval;
 869         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 870
 871         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 872         if (core == 0) {
 873                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 874                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 875         } else {
 876                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 877                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 878         }
 879         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 880         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 881         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 882         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 883         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 884         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 885         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 886         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 887
 888         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 889         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 890
 891         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 892                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 893                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 894         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 895                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 896         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 897                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 898         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 899                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 900
 901         if (core == 0) {
 902                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 903                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 904         } else {
 905                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 906                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 907         }
 908
 909         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 910         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 911         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 912
 913         if (core == 0) {
 914                 rxval = 1;
 915                 txval = 8;
 916         } else {
 917                 rxval = 4;
 918                 txval = 2;
 919         }
 920         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 921         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 922 }
 923 #endif
 924
 925 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 926 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 927 {
 928         int i;
 929         s32 iq;
 930         u32 ii;
 931         u32 qq;
 932         int iq_nbits, qq_nbits;
 933         int arsh, brsh;
 934         u16 tmp, a, b;
 935
 936         struct nphy_iq_est est;
 937         struct b43_phy_n_iq_comp old;
 938         struct b43_phy_n_iq_comp new = { };
 939         bool error = false;
 940
 941         if (mask == 0)
 942                 return;
 943
 944         b43_nphy_rx_iq_coeffs(dev, false, &old);
 945         b43_nphy_rx_iq_coeffs(dev, true, &new);
 946         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 947         new = old;
 948
 949         for (i = 0; i < 2; i++) {
 950                 if (i == 0 && (mask & 1)) {
 951                         iq = est.iq0_prod;
 952                         ii = est.i0_pwr;
 953                         qq = est.q0_pwr;
 954                 } else if (i == 1 && (mask & 2)) {
 955                         iq = est.iq1_prod;
 956                         ii = est.i1_pwr;
 957                         qq = est.q1_pwr;
 958                 } else {
 959                         continue;
 960                 }
 961
 962                 if (ii + qq < 2) {
 963                         error = true;
 964                         break;
 965                 }
 966
 967                 iq_nbits = fls(abs(iq));
 968                 qq_nbits = fls(qq);
 969
 970                 arsh = iq_nbits - 20;
 971                 if (arsh >= 0) {
 972                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 973                         tmp = ii >> arsh;
 974                 } else {
 975                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 976                         tmp = ii << -arsh;
 977                 }
 978                 if (tmp == 0) {
 979                         error = true;
 980                         break;
 981                 }
 982                 a /= tmp;
 983
 984                 brsh = qq_nbits - 11;
 985                 if (brsh >= 0) {
 986                         b = (qq << (31 - qq_nbits));
 987                         tmp = ii >> brsh;
 988                 } else {
 989                         b = (qq << (31 - qq_nbits));
 990                         tmp = ii << -brsh;
 991                 }
 992                 if (tmp == 0) {
 993                         error = true;
 994                         break;
 995                 }
 996                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 997
 998                 if (i == 0 && (mask & 0x1)) {
 999                         if (dev->phy.rev >= 3) {
1000                                 new.a0 = a & 0x3FF;
1001                                 new.b0 = b & 0x3FF;
1002                         } else {
1003                                 new.a0 = b & 0x3FF;
1004                                 new.b0 = a & 0x3FF;
1005                         }
1006                 } else if (i == 1 && (mask & 0x2)) {
1007                         if (dev->phy.rev >= 3) {
1008                                 new.a1 = a & 0x3FF;
1009                                 new.b1 = b & 0x3FF;
1010                         } else {
1011                                 new.a1 = b & 0x3FF;
1012                                 new.b1 = a & 0x3FF;
1013                         }
1014                 }
1015         }
1016
1017         if (error)
1018                 new = old;
1019
1020         b43_nphy_rx_iq_coeffs(dev, true, &new);
1021 }
1022
1023 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
1024 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
1025 {
1026         u16 array[4];
1027         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
1028
1029         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
1030         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
1031         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
1032         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
1033 }
1034
1035 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
1036 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
1037                                           const u16 *clip_st)
1038 {
1039         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
1040         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
1041 }
1042
1043 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
1044 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
1045 {
1046         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
1047         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
1048 }
1049
1050 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
1051 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
1052 {
1053         if (dev->phy.rev >= 3) {
1054                 if (!init)
1055                         return;
1056                 if (0 /* FIXME */) {
1057                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
1058                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
1059                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
1060                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
1061                 }
1062         } else {
1063                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
1064                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
1065
1066                 switch (dev->dev->bus_type) {
1067 #ifdef CONFIG_B43_BCMA
1068                 case B43_BUS_BCMA:
1069                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
1070                                                  0xFC00, 0xFC00);
1071                         break;
1072 #endif
1073 #ifdef CONFIG_B43_SSB
1074                 case B43_BUS_SSB:
1075                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
1076                                                 0xFC00, 0xFC00);
1077                         break;
1078 #endif
1079                 }
1080
1081                 b43_write32(dev, B43_MMIO_MACCTL,
1082                         b43_read32(dev, B43_MMIO_MACCTL) &
1083                         ~B43_MACCTL_GPOUTSMSK);
1084                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1085                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
1086                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
1087                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
1088
1089                 if (init) {
1090                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1091                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1092                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1093                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1094                 }
1095         }
1096 }
1097
1098 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
1099 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
1100 {
1101         u16 tmp;
1102
1103         if (dev->dev->core_rev == 16)
1104                 b43_mac_suspend(dev);
1105
1106         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
1107         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
1108                 B43_NPHY_CLASSCTL_WAITEDEN);
1109         tmp &= ~mask;
1110         tmp |= (val & mask);
1111         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
1112
1113         if (dev->dev->core_rev == 16)
1114                 b43_mac_enable(dev);
1115
1116         return tmp;
1117 }
1118
1119 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1120 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1121 {
1122         struct b43_phy *phy = &dev->phy;
1123         struct b43_phy_n *nphy = phy->n;
1124
1125         if (enable) {
1126                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1127                 if (nphy->deaf_count++ == 0) {
1128                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1129                         b43_nphy_classifier(dev, 0x7, 0);
1130                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
1131                         b43_nphy_write_clip_detection(dev, clip);
1132                 }
1133                 b43_nphy_reset_cca(dev);
1134         } else {
1135                 if (--nphy->deaf_count == 0) {
1136                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1137                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
1138                 }
1139         }
1140 }
1141
1142 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1143 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1144 {
1145         struct b43_phy_n *nphy = dev->phy.n;
1146         u16 tmp;
1147
1148         if (nphy->hang_avoid)
1149                 b43_nphy_stay_in_carrier_search(dev, 1);
1150
1151         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1152         if (tmp & 0x1)
1153                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1154         else if (tmp & 0x2)
1155                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1156
1157         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1158
1159         if (nphy->bb_mult_save & 0x80000000) {
1160                 tmp = nphy->bb_mult_save & 0xFFFF;
1161                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1162                 nphy->bb_mult_save = 0;
1163         }
1164
1165         if (nphy->hang_avoid)
1166                 b43_nphy_stay_in_carrier_search(dev, 0);
1167 }
1168
1169 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1170 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1171 {
1172         struct b43_phy_n *nphy = dev->phy.n;
1173
1174         u8 channel = dev->phy.channel;
1175         int tone[2] = { 57, 58 };
1176         u32 noise[2] = { 0x3FF, 0x3FF };
1177
1178         B43_WARN_ON(dev->phy.rev < 3);
1179
1180         if (nphy->hang_avoid)
1181                 b43_nphy_stay_in_carrier_search(dev, 1);
1182
1183         if (nphy->gband_spurwar_en) {
1184                 /* TODO: N PHY Adjust Analog Pfbw (7) */
1185                 if (channel == 11 && dev->phy.is_40mhz)
1186                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1187                 else
1188                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1189                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1190         }
1191
1192         if (nphy->aband_spurwar_en) {
1193                 if (channel == 54) {
1194                         tone[0] = 0x20;
1195                         noise[0] = 0x25F;
1196                 } else if (channel == 38 || channel == 102 || channel == 118) {
1197                         if (0 /* FIXME */) {
1198                                 tone[0] = 0x20;
1199                                 noise[0] = 0x21F;
1200                         } else {
1201                                 tone[0] = 0;
1202                                 noise[0] = 0;
1203                         }
1204                 } else if (channel == 134) {
1205                         tone[0] = 0x20;
1206                         noise[0] = 0x21F;
1207                 } else if (channel == 151) {
1208                         tone[0] = 0x10;
1209                         noise[0] = 0x23F;
1210                 } else if (channel == 153 || channel == 161) {
1211                         tone[0] = 0x30;
1212                         noise[0] = 0x23F;
1213                 } else {
1214                         tone[0] = 0;
1215                         noise[0] = 0;
1216                 }
1217
1218                 if (!tone[0] && !noise[0])
1219                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1220                 else
1221                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1222         }
1223
1224         if (nphy->hang_avoid)
1225                 b43_nphy_stay_in_carrier_search(dev, 0);
1226 }
1227
1228 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1229 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1230 {
1231         struct b43_phy_n *nphy = dev->phy.n;
1232
1233         u8 i;
1234         s16 tmp;
1235         u16 data[4];
1236         s16 gain[2];
1237         u16 minmax[2];
1238         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1239
1240         if (nphy->hang_avoid)
1241                 b43_nphy_stay_in_carrier_search(dev, 1);
1242
1243         if (nphy->gain_boost) {
1244                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1245                         gain[0] = 6;
1246                         gain[1] = 6;
1247                 } else {
1248                         tmp = 40370 - 315 * dev->phy.channel;
1249                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1250                         tmp = 23242 - 224 * dev->phy.channel;
1251                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1252                 }
1253         } else {
1254                 gain[0] = 0;
1255                 gain[1] = 0;
1256         }
1257
1258         for (i = 0; i < 2; i++) {
1259                 if (nphy->elna_gain_config) {
1260                         data[0] = 19 + gain[i];
1261                         data[1] = 25 + gain[i];
1262                         data[2] = 25 + gain[i];
1263                         data[3] = 25 + gain[i];
1264                 } else {
1265                         data[0] = lna_gain[0] + gain[i];
1266                         data[1] = lna_gain[1] + gain[i];
1267                         data[2] = lna_gain[2] + gain[i];
1268                         data[3] = lna_gain[3] + gain[i];
1269                 }
1270                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1271
1272                 minmax[i] = 23 + gain[i];
1273         }
1274
1275         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1276                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1277         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1278                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1279
1280         if (nphy->hang_avoid)
1281                 b43_nphy_stay_in_carrier_search(dev, 0);
1282 }
1283
1284 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1285 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1286 {
1287         struct b43_phy_n *nphy = dev->phy.n;
1288         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1289
1290         /* PHY rev 0, 1, 2 */
1291         u8 i, j;
1292         u8 code;
1293         u16 tmp;
1294         u8 rfseq_events[3] = { 6, 8, 7 };
1295         u8 rfseq_delays[3] = { 10, 30, 1 };
1296
1297         /* PHY rev >= 3 */
1298         bool ghz5;
1299         bool ext_lna;
1300         u16 rssi_gain;
1301         struct nphy_gain_ctl_workaround_entry *e;
1302         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1303         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1304
1305         if (dev->phy.rev >= 3) {
1306                 /* Prepare values */
1307                 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1308                         & B43_NPHY_BANDCTL_5GHZ;
1309                 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1310                 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1311                 if (ghz5 && dev->phy.rev >= 5)
1312                         rssi_gain = 0x90;
1313                 else
1314                         rssi_gain = 0x50;
1315
1316                 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1317
1318                 /* Set Clip 2 detect */
1319                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1320                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1321                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1322                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1323
1324                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1325                                 0x17);
1326                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1327                                 0x17);
1328                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1329                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1330                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1331                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1332                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1333                                 rssi_gain);
1334                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1335                                 rssi_gain);
1336                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1337                                 0x17);
1338                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1339                                 0x17);
1340                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1341                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1342
1343                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1344                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1345                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1346                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1347                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1348                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1349                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1350                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1351                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1352                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1353                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1354                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1355
1356                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1357                 b43_phy_write(dev, 0x2A7, e->init_gain);
1358                 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1359                                         e->rfseq_init);
1360                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1361
1362                 /* TODO: check defines. Do not match variables names */
1363                 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1364                 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1365                 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1366                 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1367                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1368                 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1369
1370                 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1371                 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1372                 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1373                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1374                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1375                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1376                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1377                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1378                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1379                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1380         } else {
1381                 /* Set Clip 2 detect */
1382                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1383                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1384                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1385                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1386
1387                 /* Set narrowband clip threshold */
1388                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1389                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1390
1391                 if (!dev->phy.is_40mhz) {
1392                         /* Set dwell lengths */
1393                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1394                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1395                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1396                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1397                 }
1398
1399                 /* Set wideband clip 2 threshold */
1400                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1401                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1402                                 21);
1403                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1404                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1405                                 21);
1406
1407                 if (!dev->phy.is_40mhz) {
1408                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1409                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1410                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1411                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1412                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1413                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1414                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1415                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1416                 }
1417
1418                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1419
1420                 if (nphy->gain_boost) {
1421                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1422                             dev->phy.is_40mhz)
1423                                 code = 4;
1424                         else
1425                                 code = 5;
1426                 } else {
1427                         code = dev->phy.is_40mhz ? 6 : 7;
1428                 }
1429
1430                 /* Set HPVGA2 index */
1431                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1432                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1433                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1434                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1435                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1436                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1437
1438                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1439                 /* specs say about 2 loops, but wl does 4 */
1440                 for (i = 0; i < 4; i++)
1441                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1442                                                         (code << 8 | 0x7C));
1443
1444                 b43_nphy_adjust_lna_gain_table(dev);
1445
1446                 if (nphy->elna_gain_config) {
1447                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1448                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1449                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1450                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1451                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1452
1453                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1454                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1455                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1456                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1457                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1458
1459                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1460                         /* specs say about 2 loops, but wl does 4 */
1461                         for (i = 0; i < 4; i++)
1462                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1463                                                         (code << 8 | 0x74));
1464                 }
1465
1466                 if (dev->phy.rev == 2) {
1467                         for (i = 0; i < 4; i++) {
1468                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1469                                                 (0x0400 * i) + 0x0020);
1470                                 for (j = 0; j < 21; j++) {
1471                                         tmp = j * (i < 2 ? 3 : 1);
1472                                         b43_phy_write(dev,
1473                                                 B43_NPHY_TABLE_DATALO, tmp);
1474                                 }
1475                         }
1476                 }
1477
1478                 b43_nphy_set_rf_sequence(dev, 5,
1479                                 rfseq_events, rfseq_delays, 3);
1480                 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1481                         ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1482                         0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1483
1484                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1485                         b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1486                                         0xFF80, 4);
1487         }
1488 }
1489
1490 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1491 {
1492         struct b43_phy_n *nphy = dev->phy.n;
1493         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1494
1495         /* TX to RX */
1496         u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1497         u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
1498         /* RX to TX */
1499         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1500                                         0x1F };
1501         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
1502         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
1503         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
1504
1505         u16 tmp16;
1506         u32 tmp32;
1507
1508         b43_phy_write(dev, 0x23f, 0x1f8);
1509         b43_phy_write(dev, 0x240, 0x1f8);
1510
1511         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1512         tmp32 &= 0xffffff;
1513         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1514
1515         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1516         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1517         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1518         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1519         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1520         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1521
1522         b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1523         b43_phy_write(dev, 0x2AE, 0x000C);
1524
1525         /* TX to RX */
1526         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
1527                                  ARRAY_SIZE(tx2rx_events));
1528
1529         /* RX to TX */
1530         if (b43_nphy_ipa(dev))
1531                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
1532                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
1533         if (nphy->hw_phyrxchain != 3 &&
1534             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
1535                 if (b43_nphy_ipa(dev)) {
1536                         rx2tx_delays[5] = 59;
1537                         rx2tx_delays[6] = 1;
1538                         rx2tx_events[7] = 0x1F;
1539                 }
1540                 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
1541                                          ARRAY_SIZE(rx2tx_events));
1542         }
1543
1544         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1545                 0x2 : 0x9C40;
1546         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1547
1548         b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1549
1550         b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1551         b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1552
1553         b43_nphy_gain_ctrl_workarounds(dev);
1554
1555         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
1556         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
1557
1558         /* TODO */
1559
1560         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1561         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1562         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1563         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1564         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1565         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1566         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1567         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1568         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1569         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1570         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1571         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1572
1573         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1574
1575         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1576              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1577             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1578              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1579                 tmp32 = 0x00088888;
1580         else
1581                 tmp32 = 0x88888888;
1582         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1583         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1584         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1585
1586         if (dev->phy.rev == 4 &&
1587                 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1588                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1589                                 0x70);
1590                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1591                                 0x70);
1592         }
1593
1594         b43_phy_write(dev, 0x224, 0x03eb);
1595         b43_phy_write(dev, 0x225, 0x03eb);
1596         b43_phy_write(dev, 0x226, 0x0341);
1597         b43_phy_write(dev, 0x227, 0x0341);
1598         b43_phy_write(dev, 0x228, 0x042b);
1599         b43_phy_write(dev, 0x229, 0x042b);
1600         b43_phy_write(dev, 0x22a, 0x0381);
1601         b43_phy_write(dev, 0x22b, 0x0381);
1602         b43_phy_write(dev, 0x22c, 0x042b);
1603         b43_phy_write(dev, 0x22d, 0x042b);
1604         b43_phy_write(dev, 0x22e, 0x0381);
1605         b43_phy_write(dev, 0x22f, 0x0381);
1606 }
1607
1608 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1609 {
1610         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1611         struct b43_phy *phy = &dev->phy;
1612         struct b43_phy_n *nphy = phy->n;
1613
1614         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1615         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1616
1617         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1618         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1619
1620         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1621             nphy->band5g_pwrgain) {
1622                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1623                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1624         } else {
1625                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1626                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1627         }
1628
1629         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1630         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1631         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1632         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1633
1634         if (dev->phy.rev < 2) {
1635                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1636                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1637                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1638                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1639                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1640                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1641         }
1642
1643         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1644         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1645         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1646         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1647
1648         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
1649             dev->dev->board_type == 0x8B) {
1650                 delays1[0] = 0x1;
1651                 delays1[5] = 0x14;
1652         }
1653         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1654         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1655
1656         b43_nphy_gain_ctrl_workarounds(dev);
1657
1658         if (dev->phy.rev < 2) {
1659                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1660                         b43_hf_write(dev, b43_hf_read(dev) |
1661                                         B43_HF_MLADVW);
1662         } else if (dev->phy.rev == 2) {
1663                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1664                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1665         }
1666
1667         if (dev->phy.rev < 2)
1668                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1669                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1670
1671         /* Set phase track alpha and beta */
1672         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1673         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1674         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1675         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1676         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1677         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1678
1679         b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1680                         ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1681         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1682         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1683         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1684
1685         if (dev->phy.rev == 2)
1686                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1687                                 B43_NPHY_FINERX2_CGC_DECGC);
1688 }
1689
1690 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1691 static void b43_nphy_workarounds(struct b43_wldev *dev)
1692 {
1693         struct b43_phy *phy = &dev->phy;
1694         struct b43_phy_n *nphy = phy->n;
1695
1696         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1697                 b43_nphy_classifier(dev, 1, 0);
1698         else
1699                 b43_nphy_classifier(dev, 1, 1);
1700
1701         if (nphy->hang_avoid)
1702                 b43_nphy_stay_in_carrier_search(dev, 1);
1703
1704         b43_phy_set(dev, B43_NPHY_IQFLIP,
1705                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1706
1707         if (dev->phy.rev >= 3)
1708                 b43_nphy_workarounds_rev3plus(dev);
1709         else
1710                 b43_nphy_workarounds_rev1_2(dev);
1711
1712         if (nphy->hang_avoid)
1713                 b43_nphy_stay_in_carrier_search(dev, 0);
1714 }
1715
1716 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1717 static int b43_nphy_load_samples(struct b43_wldev *dev,
1718                                         struct b43_c32 *samples, u16 len) {
1719         struct b43_phy_n *nphy = dev->phy.n;
1720         u16 i;
1721         u32 *data;
1722
1723         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1724         if (!data) {
1725                 b43err(dev->wl, "allocation for samples loading failed\n");
1726                 return -ENOMEM;
1727         }
1728         if (nphy->hang_avoid)
1729                 b43_nphy_stay_in_carrier_search(dev, 1);
1730
1731         for (i = 0; i < len; i++) {
1732                 data[i] = (samples[i].i & 0x3FF << 10);
1733                 data[i] |= samples[i].q & 0x3FF;
1734         }
1735         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1736
1737         kfree(data);
1738         if (nphy->hang_avoid)
1739                 b43_nphy_stay_in_carrier_search(dev, 0);
1740         return 0;
1741 }
1742
1743 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1744 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1745                                         bool test)
1746 {
1747         int i;
1748         u16 bw, len, rot, angle;
1749         struct b43_c32 *samples;
1750
1751
1752         bw = (dev->phy.is_40mhz) ? 40 : 20;
1753         len = bw << 3;
1754
1755         if (test) {
1756                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1757                         bw = 82;
1758                 else
1759                         bw = 80;
1760
1761                 if (dev->phy.is_40mhz)
1762                         bw <<= 1;
1763
1764                 len = bw << 1;
1765         }
1766
1767         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1768         if (!samples) {
1769                 b43err(dev->wl, "allocation for samples generation failed\n");
1770                 return 0;
1771         }
1772         rot = (((freq * 36) / bw) << 16) / 100;
1773         angle = 0;
1774
1775         for (i = 0; i < len; i++) {
1776                 samples[i] = b43_cordic(angle);
1777                 angle += rot;
1778                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1779                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1780         }
1781
1782         i = b43_nphy_load_samples(dev, samples, len);
1783         kfree(samples);
1784         return (i < 0) ? 0 : len;
1785 }
1786
1787 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1788 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1789                                         u16 wait, bool iqmode, bool dac_test)
1790 {
1791         struct b43_phy_n *nphy = dev->phy.n;
1792         int i;
1793         u16 seq_mode;
1794         u32 tmp;
1795
1796         if (nphy->hang_avoid)
1797                 b43_nphy_stay_in_carrier_search(dev, true);
1798
1799         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1800                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1801                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1802         }
1803
1804         if (!dev->phy.is_40mhz)
1805                 tmp = 0x6464;
1806         else
1807                 tmp = 0x4747;
1808         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1809
1810         if (nphy->hang_avoid)
1811                 b43_nphy_stay_in_carrier_search(dev, false);
1812
1813         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1814
1815         if (loops != 0xFFFF)
1816                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1817         else
1818                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1819
1820         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1821
1822         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1823
1824         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1825         if (iqmode) {
1826                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1827                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1828         } else {
1829                 if (dac_test)
1830                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1831                 else
1832                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1833         }
1834         for (i = 0; i < 100; i++) {
1835                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1836                         i = 0;
1837                         break;
1838                 }
1839                 udelay(10);
1840         }
1841         if (i)
1842                 b43err(dev->wl, "run samples timeout\n");
1843
1844         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1845 }
1846
1847 /*
1848  * Transmits a known value for LO calibration
1849  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1850  */
1851 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1852                                 bool iqmode, bool dac_test)
1853 {
1854         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1855         if (samp == 0)
1856                 return -1;
1857         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1858         return 0;
1859 }
1860
1861 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1862 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1863 {
1864         struct b43_phy_n *nphy = dev->phy.n;
1865         int i, j;
1866         u32 tmp;
1867         u32 cur_real, cur_imag, real_part, imag_part;
1868
1869         u16 buffer[7];
1870
1871         if (nphy->hang_avoid)
1872                 b43_nphy_stay_in_carrier_search(dev, true);
1873
1874         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1875
1876         for (i = 0; i < 2; i++) {
1877                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1878                         (buffer[i * 2 + 1] & 0x3FF);
1879                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1880                                 (((i + 26) << 10) | 320));
1881                 for (j = 0; j < 128; j++) {
1882                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1883                                         ((tmp >> 16) & 0xFFFF));
1884                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1885                                         (tmp & 0xFFFF));
1886                 }
1887         }
1888
1889         for (i = 0; i < 2; i++) {
1890                 tmp = buffer[5 + i];
1891                 real_part = (tmp >> 8) & 0xFF;
1892                 imag_part = (tmp & 0xFF);
1893                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1894                                 (((i + 26) << 10) | 448));
1895
1896                 if (dev->phy.rev >= 3) {
1897                         cur_real = real_part;
1898                         cur_imag = imag_part;
1899                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1900                 }
1901
1902                 for (j = 0; j < 128; j++) {
1903                         if (dev->phy.rev < 3) {
1904                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1905                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1906                                 tmp = ((cur_real & 0xFF) << 8) |
1907                                         (cur_imag & 0xFF);
1908                         }
1909                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1910                                         ((tmp >> 16) & 0xFFFF));
1911                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1912                                         (tmp & 0xFFFF));
1913                 }
1914         }
1915
1916         if (dev->phy.rev >= 3) {
1917                 b43_shm_write16(dev, B43_SHM_SHARED,
1918                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1919                 b43_shm_write16(dev, B43_SHM_SHARED,
1920                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1921         }
1922
1923         if (nphy->hang_avoid)
1924                 b43_nphy_stay_in_carrier_search(dev, false);
1925 }
1926
1927 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1928 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1929                                         u8 *events, u8 *delays, u8 length)
1930 {
1931         struct b43_phy_n *nphy = dev->phy.n;
1932         u8 i;
1933         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1934         u16 offset1 = cmd << 4;
1935         u16 offset2 = offset1 + 0x80;
1936
1937         if (nphy->hang_avoid)
1938                 b43_nphy_stay_in_carrier_search(dev, true);
1939
1940         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1941         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1942
1943         for (i = length; i < 16; i++) {
1944                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1945                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1946         }
1947
1948         if (nphy->hang_avoid)
1949                 b43_nphy_stay_in_carrier_search(dev, false);
1950 }
1951
1952 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1953 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1954                                        enum b43_nphy_rf_sequence seq)
1955 {
1956         static const u16 trigger[] = {
1957                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1958                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1959                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1960                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1961                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1962                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1963         };
1964         int i;
1965         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1966
1967         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1968
1969         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1970                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1971         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1972         for (i = 0; i < 200; i++) {
1973                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1974                         goto ok;
1975                 msleep(1);
1976         }
1977         b43err(dev->wl, "RF sequence status timeout\n");
1978 ok:
1979         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1980 }
1981
1982 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1983 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1984                                                 u16 value, u8 core, bool off)
1985 {
1986         int i;
1987         u8 index = fls(field);
1988         u8 addr, en_addr, val_addr;
1989         /* we expect only one bit set */
1990         B43_WARN_ON(field & (~(1 << (index - 1))));
1991
1992         if (dev->phy.rev >= 3) {
1993                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1994                 for (i = 0; i < 2; i++) {
1995                         if (index == 0 || index == 16) {
1996                                 b43err(dev->wl,
1997                                         "Unsupported RF Ctrl Override call\n");
1998                                 return;
1999                         }
2000
2001                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
2002                         en_addr = B43_PHY_N((i == 0) ?
2003                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
2004                         val_addr = B43_PHY_N((i == 0) ?
2005                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
2006
2007                         if (off) {
2008                                 b43_phy_mask(dev, en_addr, ~(field));
2009                                 b43_phy_mask(dev, val_addr,
2010                                                 ~(rf_ctrl->val_mask));
2011                         } else {
2012                                 if (core == 0 || ((1 << core) & i) != 0) {
2013                                         b43_phy_set(dev, en_addr, field);
2014                                         b43_phy_maskset(dev, val_addr,
2015                                                 ~(rf_ctrl->val_mask),
2016                                                 (value << rf_ctrl->val_shift));
2017                                 }
2018                         }
2019                 }
2020         } else {
2021                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
2022                 if (off) {
2023                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
2024                         value = 0;
2025                 } else {
2026                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
2027                 }
2028
2029                 for (i = 0; i < 2; i++) {
2030                         if (index <= 1 || index == 16) {
2031                                 b43err(dev->wl,
2032                                         "Unsupported RF Ctrl Override call\n");
2033                                 return;
2034                         }
2035
2036                         if (index == 2 || index == 10 ||
2037                             (index >= 13 && index <= 15)) {
2038                                 core = 1;
2039                         }
2040
2041                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
2042                         addr = B43_PHY_N((i == 0) ?
2043                                 rf_ctrl->addr0 : rf_ctrl->addr1);
2044
2045                         if ((core & (1 << i)) != 0)
2046                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
2047                                                 (value << rf_ctrl->shift));
2048
2049                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
2050                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2051                                         B43_NPHY_RFCTL_CMD_START);
2052                         udelay(1);
2053                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
2054                 }
2055         }
2056 }
2057
2058 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
2059 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
2060                                                 u16 value, u8 core)
2061 {
2062         u8 i, j;
2063         u16 reg, tmp, val;
2064
2065         B43_WARN_ON(dev->phy.rev < 3);
2066         B43_WARN_ON(field > 4);
2067
2068         for (i = 0; i < 2; i++) {
2069                 if ((core == 1 && i == 1) || (core == 2 && !i))
2070                         continue;
2071
2072                 reg = (i == 0) ?
2073                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
2074                 b43_phy_mask(dev, reg, 0xFBFF);
2075
2076                 switch (field) {
2077                 case 0:
2078                         b43_phy_write(dev, reg, 0);
2079                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2080                         break;
2081                 case 1:
2082                         if (!i) {
2083                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
2084                                                 0xFC3F, (value << 6));
2085                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
2086                                                 0xFFFE, 1);
2087                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2088                                                 B43_NPHY_RFCTL_CMD_START);
2089                                 for (j = 0; j < 100; j++) {
2090                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
2091                                                 j = 0;
2092                                                 break;
2093                                         }
2094                                         udelay(10);
2095                                 }
2096                                 if (j)
2097                                         b43err(dev->wl,
2098                                                 "intc override timeout\n");
2099                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
2100                                                 0xFFFE);
2101                         } else {
2102                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
2103                                                 0xFC3F, (value << 6));
2104                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
2105                                                 0xFFFE, 1);
2106                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2107                                                 B43_NPHY_RFCTL_CMD_RXTX);
2108                                 for (j = 0; j < 100; j++) {
2109                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
2110                                                 j = 0;
2111                                                 break;
2112                                         }
2113                                         udelay(10);
2114                                 }
2115                                 if (j)
2116                                         b43err(dev->wl,
2117                                                 "intc override timeout\n");
2118                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2119                                                 0xFFFE);
2120                         }
2121                         break;
2122                 case 2:
2123                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2124                                 tmp = 0x0020;
2125                                 val = value << 5;
2126                         } else {
2127                                 tmp = 0x0010;
2128                                 val = value << 4;
2129                         }
2130                         b43_phy_maskset(dev, reg, ~tmp, val);
2131                         break;
2132                 case 3:
2133                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2134                                 tmp = 0x0001;
2135                                 val = value;
2136                         } else {
2137                                 tmp = 0x0004;
2138                                 val = value << 2;
2139                         }
2140                         b43_phy_maskset(dev, reg, ~tmp, val);
2141                         break;
2142                 case 4:
2143                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2144                                 tmp = 0x0002;
2145                                 val = value << 1;
2146                         } else {
2147                                 tmp = 0x0008;
2148                                 val = value << 3;
2149                         }
2150                         b43_phy_maskset(dev, reg, ~tmp, val);
2151                         break;
2152                 }
2153         }
2154 }
2155
2156 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
2157 static void b43_nphy_bphy_init(struct b43_wldev *dev)
2158 {
2159         unsigned int i;
2160         u16 val;
2161
2162         val = 0x1E1F;
2163         for (i = 0; i < 16; i++) {
2164                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2165                 val -= 0x202;
2166         }
2167         val = 0x3E3F;
2168         for (i = 0; i < 16; i++) {
2169                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2170                 val -= 0x202;
2171         }
2172         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2173 }
2174
2175 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2176 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2177                                         s8 offset, u8 core, u8 rail,
2178                                         enum b43_nphy_rssi_type type)
2179 {
2180         u16 tmp;
2181         bool core1or5 = (core == 1) || (core == 5);
2182         bool core2or5 = (core == 2) || (core == 5);
2183
2184         offset = clamp_val(offset, -32, 31);
2185         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2186
2187         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2188                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2189         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2190                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2191         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2192                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2193         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2194                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2195
2196         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2197                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2198         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2199                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2200         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2201                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2202         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2203                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2204
2205         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2206                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2207         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2208                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2209         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2210                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2211         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2212                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2213
2214         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2215                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2216         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2217                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2218         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2219                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2220         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2221                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2222
2223         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2224                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2225         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2226                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2227         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2228                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2229         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2230                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2231
2232         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2233                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2234         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2235                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2236
2237         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2238                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2239         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2240                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2241 }
2242
2243 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2244 {
2245         u16 val;
2246
2247         if (type < 3)
2248                 val = 0;
2249         else if (type == 6)
2250                 val = 1;
2251         else if (type == 3)
2252                 val = 2;
2253         else
2254                 val = 3;
2255
2256         val = (val << 12) | (val << 14);
2257         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2258         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2259
2260         if (type < 3) {
2261                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2262                                 (type + 1) << 4);
2263                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2264                                 (type + 1) << 4);
2265         }
2266
2267         if (code == 0) {
2268                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2269                 if (type < 3) {
2270                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2271                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2272                                   B43_NPHY_RFCTL_CMD_CORESEL));
2273                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2274                                 ~(0x1 << 12 |
2275                                   0x1 << 5 |
2276                                   0x1 << 1 |
2277                                   0x1));
2278                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2279                                 ~B43_NPHY_RFCTL_CMD_START);
2280                         udelay(20);
2281                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2282                 }
2283         } else {
2284                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2285                 if (type < 3) {
2286                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2287                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2288                                   B43_NPHY_RFCTL_CMD_CORESEL),
2289                                 (B43_NPHY_RFCTL_CMD_RXEN |
2290                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2291                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2292                                 (0x1 << 12 |
2293                                   0x1 << 5 |
2294                                   0x1 << 1 |
2295                                   0x1));
2296                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2297                                 B43_NPHY_RFCTL_CMD_START);
2298                         udelay(20);
2299                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2300                 }
2301         }
2302 }
2303
2304 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2305 {
2306         u8 i;
2307         u16 reg, val;
2308
2309         if (code == 0) {
2310                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2311                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2312                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2313                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2314                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2315                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2316                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2317                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2318         } else {
2319                 for (i = 0; i < 2; i++) {
2320                         if ((code == 1 && i == 1) || (code == 2 && !i))
2321                                 continue;
2322
2323                         reg = (i == 0) ?
2324                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2325                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2326
2327                         if (type < 3) {
2328                                 reg = (i == 0) ?
2329                                         B43_NPHY_AFECTL_C1 :
2330                                         B43_NPHY_AFECTL_C2;
2331                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2332
2333                                 reg = (i == 0) ?
2334                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2335                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
2336                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2337
2338                                 if (type == 0)
2339                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2340                                 else if (type == 1)
2341                                         val = 16;
2342                                 else
2343                                         val = 32;
2344                                 b43_phy_set(dev, reg, val);
2345
2346                                 reg = (i == 0) ?
2347                                         B43_NPHY_TXF_40CO_B1S0 :
2348                                         B43_NPHY_TXF_40CO_B32S1;
2349                                 b43_phy_set(dev, reg, 0x0020);
2350                         } else {
2351                                 if (type == 6)
2352                                         val = 0x0100;
2353                                 else if (type == 3)
2354                                         val = 0x0200;
2355                                 else
2356                                         val = 0x0300;
2357
2358                                 reg = (i == 0) ?
2359                                         B43_NPHY_AFECTL_C1 :
2360                                         B43_NPHY_AFECTL_C2;
2361
2362                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
2363                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2364
2365                                 if (type != 3 && type != 6) {
2366                                         enum ieee80211_band band =
2367                                                 b43_current_band(dev->wl);
2368
2369                                         if (b43_nphy_ipa(dev))
2370                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2371                                         else
2372                                                 val = 0x11;
2373                                         reg = (i == 0) ? 0x2000 : 0x3000;
2374                                         reg |= B2055_PADDRV;
2375                                         b43_radio_write16(dev, reg, val);
2376
2377                                         reg = (i == 0) ?
2378                                                 B43_NPHY_AFECTL_OVER1 :
2379                                                 B43_NPHY_AFECTL_OVER;
2380                                         b43_phy_set(dev, reg, 0x0200);
2381                                 }
2382                         }
2383                 }
2384         }
2385 }
2386
2387 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2388 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2389 {
2390         if (dev->phy.rev >= 3)
2391                 b43_nphy_rev3_rssi_select(dev, code, type);
2392         else
2393                 b43_nphy_rev2_rssi_select(dev, code, type);
2394 }
2395
2396 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2397 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2398 {
2399         int i;
2400         for (i = 0; i < 2; i++) {
2401                 if (type == 2) {
2402                         if (i == 0) {
2403                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2404                                                   0xFC, buf[0]);
2405                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2406                                                   0xFC, buf[1]);
2407                         } else {
2408                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2409                                                   0xFC, buf[2 * i]);
2410                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2411                                                   0xFC, buf[2 * i + 1]);
2412                         }
2413                 } else {
2414                         if (i == 0)
2415                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2416                                                   0xF3, buf[0] << 2);
2417                         else
2418                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2419                                                   0xF3, buf[2 * i + 1] << 2);
2420                 }
2421         }
2422 }
2423
2424 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2425 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2426                                 u8 nsamp)
2427 {
2428         int i;
2429         int out;
2430         u16 save_regs_phy[9];
2431         u16 s[2];
2432
2433         if (dev->phy.rev >= 3) {
2434                 save_regs_phy[0] = b43_phy_read(dev,
2435                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2436                 save_regs_phy[1] = b43_phy_read(dev,
2437                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2438                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2439                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2440                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2441                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2442                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2443                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2444                 save_regs_phy[8] = 0;
2445         } else {
2446                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2447                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2448                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2449                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2450                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2451                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2452                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2453                 save_regs_phy[7] = 0;
2454                 save_regs_phy[8] = 0;
2455         }
2456
2457         b43_nphy_rssi_select(dev, 5, type);
2458
2459         if (dev->phy.rev < 2) {
2460                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2461                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2462         }
2463
2464         for (i = 0; i < 4; i++)
2465                 buf[i] = 0;
2466
2467         for (i = 0; i < nsamp; i++) {
2468                 if (dev->phy.rev < 2) {
2469                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2470                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2471                 } else {
2472                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2473                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2474                 }
2475
2476                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2477                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2478                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2479                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2480         }
2481         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2482                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2483
2484         if (dev->phy.rev < 2)
2485                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2486
2487         if (dev->phy.rev >= 3) {
2488                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2489                                 save_regs_phy[0]);
2490                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2491                                 save_regs_phy[1]);
2492                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2493                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2494                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2495                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2496                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2497                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2498         } else {
2499                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2500                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2501                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2502                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2503                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2504                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2505                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2506         }
2507
2508         return out;
2509 }
2510
2511 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2512 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2513 {
2514         int i, j;
2515         u8 state[4];
2516         u8 code, val;
2517         u16 class, override;
2518         u8 regs_save_radio[2];
2519         u16 regs_save_phy[2];
2520
2521         s8 offset[4];
2522         u8 core;
2523         u8 rail;
2524
2525         u16 clip_state[2];
2526         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2527         s32 results_min[4] = { };
2528         u8 vcm_final[4] = { };
2529         s32 results[4][4] = { };
2530         s32 miniq[4][2] = { };
2531
2532         if (type == 2) {
2533                 code = 0;
2534                 val = 6;
2535         } else if (type < 2) {
2536                 code = 25;
2537                 val = 4;
2538         } else {
2539                 B43_WARN_ON(1);
2540                 return;
2541         }
2542
2543         class = b43_nphy_classifier(dev, 0, 0);
2544         b43_nphy_classifier(dev, 7, 4);
2545         b43_nphy_read_clip_detection(dev, clip_state);
2546         b43_nphy_write_clip_detection(dev, clip_off);
2547
2548         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2549                 override = 0x140;
2550         else
2551                 override = 0x110;
2552
2553         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2554         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2555         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2556         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2557
2558         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2559         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2560         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2561         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2562
2563         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2564         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2565         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2566         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2567         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2568         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2569
2570         b43_nphy_rssi_select(dev, 5, type);
2571         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2572         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2573
2574         for (i = 0; i < 4; i++) {
2575                 u8 tmp[4];
2576                 for (j = 0; j < 4; j++)
2577                         tmp[j] = i;
2578                 if (type != 1)
2579                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2580                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2581                 if (type < 2)
2582                         for (j = 0; j < 2; j++)
2583                                 miniq[i][j] = min(results[i][2 * j],
2584                                                 results[i][2 * j + 1]);
2585         }
2586
2587         for (i = 0; i < 4; i++) {
2588                 s32 mind = 40;
2589                 u8 minvcm = 0;
2590                 s32 minpoll = 249;
2591                 s32 curr;
2592                 for (j = 0; j < 4; j++) {
2593                         if (type == 2)
2594                                 curr = abs(results[j][i]);
2595                         else
2596                                 curr = abs(miniq[j][i / 2] - code * 8);
2597
2598                         if (curr < mind) {
2599                                 mind = curr;
2600                                 minvcm = j;
2601                         }
2602
2603                         if (results[j][i] < minpoll)
2604                                 minpoll = results[j][i];
2605                 }
2606                 results_min[i] = minpoll;
2607                 vcm_final[i] = minvcm;
2608         }
2609
2610         if (type != 1)
2611                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2612
2613         for (i = 0; i < 4; i++) {
2614                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2615
2616                 if (offset[i] < 0)
2617                         offset[i] = -((abs(offset[i]) + 4) / 8);
2618                 else
2619                         offset[i] = (offset[i] + 4) / 8;
2620
2621                 if (results_min[i] == 248)
2622                         offset[i] = code - 32;
2623
2624                 core = (i / 2) ? 2 : 1;
2625                 rail = (i % 2) ? 1 : 0;
2626
2627                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2628                                                 type);
2629         }
2630
2631         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2632         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2633
2634         switch (state[2]) {
2635         case 1:
2636                 b43_nphy_rssi_select(dev, 1, 2);
2637                 break;
2638         case 4:
2639                 b43_nphy_rssi_select(dev, 1, 0);
2640                 break;
2641         case 2:
2642                 b43_nphy_rssi_select(dev, 1, 1);
2643                 break;
2644         default:
2645                 b43_nphy_rssi_select(dev, 1, 1);
2646                 break;
2647         }
2648
2649         switch (state[3]) {
2650         case 1:
2651                 b43_nphy_rssi_select(dev, 2, 2);
2652                 break;
2653         case 4:
2654                 b43_nphy_rssi_select(dev, 2, 0);
2655                 break;
2656         default:
2657                 b43_nphy_rssi_select(dev, 2, 1);
2658                 break;
2659         }
2660
2661         b43_nphy_rssi_select(dev, 0, type);
2662
2663         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2664         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2665         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2666         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2667
2668         b43_nphy_classifier(dev, 7, class);
2669         b43_nphy_write_clip_detection(dev, clip_state);
2670         /* Specs don't say about reset here, but it makes wl and b43 dumps
2671            identical, it really seems wl performs this */
2672         b43_nphy_reset_cca(dev);
2673 }
2674
2675 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2676 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2677 {
2678         /* TODO */
2679 }
2680
2681 /*
2682  * RSSI Calibration
2683  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2684  */
2685 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2686 {
2687         if (dev->phy.rev >= 3) {
2688                 b43_nphy_rev3_rssi_cal(dev);
2689         } else {
2690                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2691                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2692                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2693         }
2694 }
2695
2696 /*
2697  * Restore RSSI Calibration
2698  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2699  */
2700 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2701 {
2702         struct b43_phy_n *nphy = dev->phy.n;
2703
2704         u16 *rssical_radio_regs = NULL;
2705         u16 *rssical_phy_regs = NULL;
2706
2707         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2708                 if (!nphy->rssical_chanspec_2G.center_freq)
2709                         return;
2710                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2711                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2712         } else {
2713                 if (!nphy->rssical_chanspec_5G.center_freq)
2714                         return;
2715                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2716                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2717         }
2718
2719         /* TODO use some definitions */
2720         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2721         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2722
2723         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2724         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2725         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2726         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2727
2728         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2729         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2730         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2731         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2732
2733         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2734         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2735         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2736         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2737 }
2738
2739 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2740 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2741 {
2742         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2743                 if (dev->phy.rev >= 6) {
2744                         if (dev->dev->chip_id == 47162)
2745                                 return txpwrctrl_tx_gain_ipa_rev5;
2746                         return txpwrctrl_tx_gain_ipa_rev6;
2747                 } else if (dev->phy.rev >= 5) {
2748                         return txpwrctrl_tx_gain_ipa_rev5;
2749                 } else {
2750                         return txpwrctrl_tx_gain_ipa;
2751                 }
2752         } else {
2753                 return txpwrctrl_tx_gain_ipa_5g;
2754         }
2755 }
2756
2757 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2758 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2759 {
2760         struct b43_phy_n *nphy = dev->phy.n;
2761         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2762         u16 tmp;
2763         u8 offset, i;
2764
2765         if (dev->phy.rev >= 3) {
2766             for (i = 0; i < 2; i++) {
2767                 tmp = (i == 0) ? 0x2000 : 0x3000;
2768                 offset = i * 11;
2769
2770                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2771                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2772                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2773                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2774                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2775                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2776                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2777                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2778                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2779                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2780                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2781
2782                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2783                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2784                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2785                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2786                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2787                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2788                         if (nphy->ipa5g_on) {
2789                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2790                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2791                         } else {
2792                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2793                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2794                         }
2795                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2796                 } else {
2797                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2798                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2799                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2800                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2801                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2802                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2803                         if (nphy->ipa2g_on) {
2804                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2805                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2806                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2807                         } else {
2808                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2809                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2810                         }
2811                 }
2812                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2813                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2814                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2815             }
2816         } else {
2817                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2818                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2819
2820                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2821                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2822
2823                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2824                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2825
2826                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2827                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2828
2829                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2830                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2831
2832                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2833                     B43_NPHY_BANDCTL_5GHZ)) {
2834                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2835                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2836                 } else {
2837                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2838                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2839                 }
2840
2841                 if (dev->phy.rev < 2) {
2842                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2843                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2844                 } else {
2845                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2846                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2847                 }
2848         }
2849 }
2850
2851 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2852 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2853                                         struct nphy_txgains target,
2854                                         struct nphy_iqcal_params *params)
2855 {
2856         int i, j, indx;
2857         u16 gain;
2858
2859         if (dev->phy.rev >= 3) {
2860                 params->txgm = target.txgm[core];
2861                 params->pga = target.pga[core];
2862                 params->pad = target.pad[core];
2863                 params->ipa = target.ipa[core];
2864                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2865                                         (params->pad << 4) | (params->ipa);
2866                 for (j = 0; j < 5; j++)
2867                         params->ncorr[j] = 0x79;
2868         } else {
2869                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2870                         (target.txgm[core] << 8);
2871
2872                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2873                         1 : 0;
2874                 for (i = 0; i < 9; i++)
2875                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2876                                 break;
2877                 i = min(i, 8);
2878
2879                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2880                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2881                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2882                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2883                                         (params->pad << 2);
2884                 for (j = 0; j < 4; j++)
2885                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2886         }
2887 }
2888
2889 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2890 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2891 {
2892         struct b43_phy_n *nphy = dev->phy.n;
2893         int i;
2894         u16 scale, entry;
2895
2896         u16 tmp = nphy->txcal_bbmult;
2897         if (core == 0)
2898                 tmp >>= 8;
2899         tmp &= 0xff;
2900
2901         for (i = 0; i < 18; i++) {
2902                 scale = (ladder_lo[i].percent * tmp) / 100;
2903                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2904                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2905
2906                 scale = (ladder_iq[i].percent * tmp) / 100;
2907                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2908                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2909         }
2910 }
2911
2912 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2913 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2914 {
2915         int i;
2916         for (i = 0; i < 15; i++)
2917                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2918                                 tbl_tx_filter_coef_rev4[2][i]);
2919 }
2920
2921 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2922 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2923 {
2924         int i, j;
2925         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2926         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2927
2928         for (i = 0; i < 3; i++)
2929                 for (j = 0; j < 15; j++)
2930                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2931                                         tbl_tx_filter_coef_rev4[i][j]);
2932
2933         if (dev->phy.is_40mhz) {
2934                 for (j = 0; j < 15; j++)
2935                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2936                                         tbl_tx_filter_coef_rev4[3][j]);
2937         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2938                 for (j = 0; j < 15; j++)
2939                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2940                                         tbl_tx_filter_coef_rev4[5][j]);
2941         }
2942
2943         if (dev->phy.channel == 14)
2944                 for (j = 0; j < 15; j++)
2945                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2946                                         tbl_tx_filter_coef_rev4[6][j]);
2947 }
2948
2949 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2950 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2951 {
2952         struct b43_phy_n *nphy = dev->phy.n;
2953
2954         u16 curr_gain[2];
2955         struct nphy_txgains target;
2956         const u32 *table = NULL;
2957
2958         if (!nphy->txpwrctrl) {
2959                 int i;
2960
2961                 if (nphy->hang_avoid)
2962                         b43_nphy_stay_in_carrier_search(dev, true);
2963                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2964                 if (nphy->hang_avoid)
2965                         b43_nphy_stay_in_carrier_search(dev, false);
2966
2967                 for (i = 0; i < 2; ++i) {
2968                         if (dev->phy.rev >= 3) {
2969                                 target.ipa[i] = curr_gain[i] & 0x000F;
2970                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2971                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2972                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2973                         } else {
2974                                 target.ipa[i] = curr_gain[i] & 0x0003;
2975                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2976                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2977                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2978                         }
2979                 }
2980         } else {
2981                 int i;
2982                 u16 index[2];
2983                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2984                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2985                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2986                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2987                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2988                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2989
2990                 for (i = 0; i < 2; ++i) {
2991                         if (dev->phy.rev >= 3) {
2992                                 enum ieee80211_band band =
2993                                         b43_current_band(dev->wl);
2994
2995                                 if (b43_nphy_ipa(dev)) {
2996                                         table = b43_nphy_get_ipa_gain_table(dev);
2997                                 } else {
2998                                         if (band == IEEE80211_BAND_5GHZ) {
2999                                                 if (dev->phy.rev == 3)
3000                                                         table = b43_ntab_tx_gain_rev3_5ghz;
3001                                                 else if (dev->phy.rev == 4)
3002                                                         table = b43_ntab_tx_gain_rev4_5ghz;
3003                                                 else
3004                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
3005                                         } else {
3006                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
3007                                         }
3008                                 }
3009
3010                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3011                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3012                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3013                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3014                         } else {
3015                                 table = b43_ntab_tx_gain_rev0_1_2;
3016
3017                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3018                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3019                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3020                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3021                         }
3022                 }
3023         }
3024
3025         return target;
3026 }
3027
3028 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3029 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3030 {
3031         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3032
3033         if (dev->phy.rev >= 3) {
3034                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3035                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3036                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3037                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3038                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
3039                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3040                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
3041                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3042                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3043                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3044                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3045                 b43_nphy_reset_cca(dev);
3046         } else {
3047                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3048                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3049                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3050                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3051                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
3052                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3053                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3054         }
3055 }
3056
3057 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3058 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3059 {
3060         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3061         u16 tmp;
3062
3063         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3064         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3065         if (dev->phy.rev >= 3) {
3066                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3067                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3068
3069                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3070                 regs[2] = tmp;
3071                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3072
3073                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3074                 regs[3] = tmp;
3075                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3076
3077                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
3078                 b43_phy_mask(dev, B43_NPHY_BBCFG,
3079                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
3080
3081                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
3082                 regs[5] = tmp;
3083                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
3084
3085                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
3086                 regs[6] = tmp;
3087                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
3088                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3089                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3090
3091                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3092                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3093                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3094
3095                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3096                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3097                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3098                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3099         } else {
3100                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3101                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3102                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3103                 regs[2] = tmp;
3104                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3105                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3106                 regs[3] = tmp;
3107                 tmp |= 0x2000;
3108                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3109                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3110                 regs[4] = tmp;
3111                 tmp |= 0x2000;
3112                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3113                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3114                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3115                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3116                         tmp = 0x0180;
3117                 else
3118                         tmp = 0x0120;
3119                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3120                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3121         }
3122 }
3123
3124 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3125 static void b43_nphy_save_cal(struct b43_wldev *dev)
3126 {
3127         struct b43_phy_n *nphy = dev->phy.n;
3128
3129         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3130         u16 *txcal_radio_regs = NULL;
3131         struct b43_chanspec *iqcal_chanspec;
3132         u16 *table = NULL;
3133
3134         if (nphy->hang_avoid)
3135                 b43_nphy_stay_in_carrier_search(dev, 1);
3136
3137         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3138                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3139                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3140                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3141                 table = nphy->cal_cache.txcal_coeffs_2G;
3142         } else {
3143                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3144                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3145                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3146                 table = nphy->cal_cache.txcal_coeffs_5G;
3147         }
3148
3149         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3150         /* TODO use some definitions */
3151         if (dev->phy.rev >= 3) {
3152                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3153                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3154                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3155                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3156                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3157                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3158                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3159                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3160         } else {
3161                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3162                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3163                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3164                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3165         }
3166         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3167         iqcal_chanspec->channel_type = dev->phy.channel_type;
3168         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3169
3170         if (nphy->hang_avoid)
3171                 b43_nphy_stay_in_carrier_search(dev, 0);
3172 }
3173
3174 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3175 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3176 {
3177         struct b43_phy_n *nphy = dev->phy.n;
3178
3179         u16 coef[4];
3180         u16 *loft = NULL;
3181         u16 *table = NULL;
3182
3183         int i;
3184         u16 *txcal_radio_regs = NULL;
3185         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3186
3187         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3188                 if (!nphy->iqcal_chanspec_2G.center_freq)
3189                         return;
3190                 table = nphy->cal_cache.txcal_coeffs_2G;
3191                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3192         } else {
3193                 if (!nphy->iqcal_chanspec_5G.center_freq)
3194                         return;
3195                 table = nphy->cal_cache.txcal_coeffs_5G;
3196                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3197         }
3198
3199         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3200
3201         for (i = 0; i < 4; i++) {
3202                 if (dev->phy.rev >= 3)
3203                         table[i] = coef[i];
3204                 else
3205                         coef[i] = 0;
3206         }
3207
3208         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3209         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3210         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3211
3212         if (dev->phy.rev < 2)
3213                 b43_nphy_tx_iq_workaround(dev);
3214
3215         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3216                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3217                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3218         } else {
3219                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3220                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3221         }
3222
3223         /* TODO use some definitions */
3224         if (dev->phy.rev >= 3) {
3225                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3226                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3227                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3228                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3229                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3230                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3231                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3232                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3233         } else {
3234                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3235                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3236                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3237                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3238         }
3239         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3240 }
3241
3242 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3243 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3244                                 struct nphy_txgains target,
3245                                 bool full, bool mphase)
3246 {
3247         struct b43_phy_n *nphy = dev->phy.n;
3248         int i;
3249         int error = 0;
3250         int freq;
3251         bool avoid = false;
3252         u8 length;
3253         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3254         const u16 *table;
3255         bool phy6or5x;
3256
3257         u16 buffer[11];
3258         u16 diq_start = 0;
3259         u16 save[2];
3260         u16 gain[2];
3261         struct nphy_iqcal_params params[2];
3262         bool updated[2] = { };
3263
3264         b43_nphy_stay_in_carrier_search(dev, true);
3265
3266         if (dev->phy.rev >= 4) {
3267                 avoid = nphy->hang_avoid;
3268                 nphy->hang_avoid = 0;
3269         }
3270
3271         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3272
3273         for (i = 0; i < 2; i++) {
3274                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3275                 gain[i] = params[i].cal_gain;
3276         }
3277
3278         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3279
3280         b43_nphy_tx_cal_radio_setup(dev);
3281         b43_nphy_tx_cal_phy_setup(dev);
3282
3283         phy6or5x = dev->phy.rev >= 6 ||
3284                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3285                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3286         if (phy6or5x) {
3287                 if (dev->phy.is_40mhz) {
3288                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3289                                         tbl_tx_iqlo_cal_loft_ladder_40);
3290                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3291                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3292                 } else {
3293                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3294                                         tbl_tx_iqlo_cal_loft_ladder_20);
3295                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3296                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3297                 }
3298         }
3299
3300         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3301
3302         if (!dev->phy.is_40mhz)
3303                 freq = 2500;
3304         else
3305                 freq = 5000;
3306
3307         if (nphy->mphase_cal_phase_id > 2)
3308                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3309                                         0xFFFF, 0, true, false);
3310         else
3311                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3312
3313         if (error == 0) {
3314                 if (nphy->mphase_cal_phase_id > 2) {
3315                         table = nphy->mphase_txcal_bestcoeffs;
3316                         length = 11;
3317                         if (dev->phy.rev < 3)
3318                                 length -= 2;
3319                 } else {
3320                         if (!full && nphy->txiqlocal_coeffsvalid) {
3321                                 table = nphy->txiqlocal_bestc;
3322                                 length = 11;
3323                                 if (dev->phy.rev < 3)
3324                                         length -= 2;
3325                         } else {
3326                                 full = true;
3327                                 if (dev->phy.rev >= 3) {
3328                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3329                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3330                                 } else {
3331                                         table = tbl_tx_iqlo_cal_startcoefs;
3332                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3333                                 }
3334                         }
3335                 }
3336
3337                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3338
3339                 if (full) {
3340                         if (dev->phy.rev >= 3)
3341                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3342                         else
3343                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3344                 } else {
3345                         if (dev->phy.rev >= 3)
3346                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3347                         else
3348                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3349                 }
3350
3351                 if (mphase) {
3352                         count = nphy->mphase_txcal_cmdidx;
3353                         numb = min(max,
3354                                 (u16)(count + nphy->mphase_txcal_numcmds));
3355                 } else {
3356                         count = 0;
3357                         numb = max;
3358                 }
3359
3360                 for (; count < numb; count++) {
3361                         if (full) {
3362                                 if (dev->phy.rev >= 3)
3363                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3364                                 else
3365                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3366                         } else {
3367                                 if (dev->phy.rev >= 3)
3368                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3369                                 else
3370                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3371                         }
3372
3373                         core = (cmd & 0x3000) >> 12;
3374                         type = (cmd & 0x0F00) >> 8;
3375
3376                         if (phy6or5x && updated[core] == 0) {
3377                                 b43_nphy_update_tx_cal_ladder(dev, core);
3378                                 updated[core] = 1;
3379                         }
3380
3381                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3382                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3383
3384                         if (type == 1 || type == 3 || type == 4) {
3385                                 buffer[0] = b43_ntab_read(dev,
3386                                                 B43_NTAB16(15, 69 + core));
3387                                 diq_start = buffer[0];
3388                                 buffer[0] = 0;
3389                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3390                                                 0);
3391                         }
3392
3393                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3394                         for (i = 0; i < 2000; i++) {
3395                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3396                                 if (tmp & 0xC000)
3397                                         break;
3398                                 udelay(10);
3399                         }
3400
3401                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3402                                                 buffer);
3403                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3404                                                 buffer);
3405
3406                         if (type == 1 || type == 3 || type == 4)
3407                                 buffer[0] = diq_start;
3408                 }
3409
3410                 if (mphase)
3411                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3412
3413                 last = (dev->phy.rev < 3) ? 6 : 7;
3414
3415                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3416                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3417                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3418                         if (dev->phy.rev < 3) {
3419                                 buffer[0] = 0;
3420                                 buffer[1] = 0;
3421                                 buffer[2] = 0;
3422                                 buffer[3] = 0;
3423                         }
3424                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3425                                                 buffer);
3426                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3427                                                 buffer);
3428                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3429                                                 buffer);
3430                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3431                                                 buffer);
3432                         length = 11;
3433                         if (dev->phy.rev < 3)
3434                                 length -= 2;
3435                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3436                                                 nphy->txiqlocal_bestc);
3437                         nphy->txiqlocal_coeffsvalid = true;
3438                         nphy->txiqlocal_chanspec.center_freq =
3439                                                         dev->phy.channel_freq;
3440                         nphy->txiqlocal_chanspec.channel_type =
3441                                                         dev->phy.channel_type;
3442                 } else {
3443                         length = 11;
3444                         if (dev->phy.rev < 3)
3445                                 length -= 2;
3446                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3447                                                 nphy->mphase_txcal_bestcoeffs);
3448                 }
3449
3450                 b43_nphy_stop_playback(dev);
3451                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3452         }
3453
3454         b43_nphy_tx_cal_phy_cleanup(dev);
3455         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3456
3457         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3458                 b43_nphy_tx_iq_workaround(dev);
3459
3460         if (dev->phy.rev >= 4)
3461                 nphy->hang_avoid = avoid;
3462
3463         b43_nphy_stay_in_carrier_search(dev, false);
3464
3465         return error;
3466 }
3467
3468 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3469 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3470 {
3471         struct b43_phy_n *nphy = dev->phy.n;
3472         u8 i;
3473         u16 buffer[7];
3474         bool equal = true;
3475
3476         if (!nphy->txiqlocal_coeffsvalid ||
3477             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3478             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3479                 return;
3480
3481         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3482         for (i = 0; i < 4; i++) {
3483                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3484                         equal = false;
3485                         break;
3486                 }
3487         }
3488
3489         if (!equal) {
3490                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3491                                         nphy->txiqlocal_bestc);
3492                 for (i = 0; i < 4; i++)
3493                         buffer[i] = 0;
3494                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3495                                         buffer);
3496                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3497                                         &nphy->txiqlocal_bestc[5]);
3498                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3499                                         &nphy->txiqlocal_bestc[5]);
3500         }
3501 }
3502
3503 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3504 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3505                         struct nphy_txgains target, u8 type, bool debug)
3506 {
3507         struct b43_phy_n *nphy = dev->phy.n;
3508         int i, j, index;
3509         u8 rfctl[2];
3510         u8 afectl_core;
3511         u16 tmp[6];
3512         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3513         u32 real, imag;
3514         enum ieee80211_band band;
3515
3516         u8 use;
3517         u16 cur_hpf;
3518         u16 lna[3] = { 3, 3, 1 };
3519         u16 hpf1[3] = { 7, 2, 0 };
3520         u16 hpf2[3] = { 2, 0, 0 };
3521         u32 power[3] = { };
3522         u16 gain_save[2];
3523         u16 cal_gain[2];
3524         struct nphy_iqcal_params cal_params[2];
3525         struct nphy_iq_est est;
3526         int ret = 0;
3527         bool playtone = true;
3528         int desired = 13;
3529
3530         b43_nphy_stay_in_carrier_search(dev, 1);
3531
3532         if (dev->phy.rev < 2)
3533                 b43_nphy_reapply_tx_cal_coeffs(dev);
3534         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3535         for (i = 0; i < 2; i++) {
3536                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3537                 cal_gain[i] = cal_params[i].cal_gain;
3538         }
3539         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3540
3541         for (i = 0; i < 2; i++) {
3542                 if (i == 0) {
3543                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3544                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3545                         afectl_core = B43_NPHY_AFECTL_C1;
3546                 } else {
3547                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3548                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3549                         afectl_core = B43_NPHY_AFECTL_C2;
3550                 }
3551
3552                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3553                 tmp[2] = b43_phy_read(dev, afectl_core);
3554                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3555                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3556                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3557
3558                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3559                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3560                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3561                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3562                                 (1 - i));
3563                 b43_phy_set(dev, afectl_core, 0x0006);
3564                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3565
3566                 band = b43_current_band(dev->wl);
3567
3568                 if (nphy->rxcalparams & 0xFF000000) {
3569                         if (band == IEEE80211_BAND_5GHZ)
3570                                 b43_phy_write(dev, rfctl[0], 0x140);
3571                         else
3572                                 b43_phy_write(dev, rfctl[0], 0x110);
3573                 } else {
3574                         if (band == IEEE80211_BAND_5GHZ)
3575                                 b43_phy_write(dev, rfctl[0], 0x180);
3576                         else
3577                                 b43_phy_write(dev, rfctl[0], 0x120);
3578                 }
3579
3580                 if (band == IEEE80211_BAND_5GHZ)
3581                         b43_phy_write(dev, rfctl[1], 0x148);
3582                 else
3583                         b43_phy_write(dev, rfctl[1], 0x114);
3584
3585                 if (nphy->rxcalparams & 0x10000) {
3586                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3587                                         (i + 1));
3588                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3589                                         (2 - i));
3590                 }
3591
3592                 for (j = 0; j < 4; j++) {
3593                         if (j < 3) {
3594                                 cur_lna = lna[j];
3595                                 cur_hpf1 = hpf1[j];
3596                                 cur_hpf2 = hpf2[j];
3597                         } else {
3598                                 if (power[1] > 10000) {
3599                                         use = 1;
3600                                         cur_hpf = cur_hpf1;
3601                                         index = 2;
3602                                 } else {
3603                                         if (power[0] > 10000) {
3604                                                 use = 1;
3605                                                 cur_hpf = cur_hpf1;
3606                                                 index = 1;
3607                                         } else {
3608                                                 index = 0;
3609                                                 use = 2;
3610                                                 cur_hpf = cur_hpf2;
3611                                         }
3612                                 }
3613                                 cur_lna = lna[index];
3614                                 cur_hpf1 = hpf1[index];
3615                                 cur_hpf2 = hpf2[index];
3616                                 cur_hpf += desired - hweight32(power[index]);
3617                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3618                                 if (use == 1)
3619                                         cur_hpf1 = cur_hpf;
3620                                 else
3621                                         cur_hpf2 = cur_hpf;
3622                         }
3623
3624                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3625                                         (cur_lna << 2));
3626                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3627                                                                         false);
3628                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3629                         b43_nphy_stop_playback(dev);
3630
3631                         if (playtone) {
3632                                 ret = b43_nphy_tx_tone(dev, 4000,
3633                                                 (nphy->rxcalparams & 0xFFFF),
3634                                                 false, false);
3635                                 playtone = false;
3636                         } else {
3637                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3638                                                         false, false);
3639                         }
3640
3641                         if (ret == 0) {
3642                                 if (j < 3) {
3643                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3644                                                                         false);
3645                                         if (i == 0) {
3646                                                 real = est.i0_pwr;
3647                                                 imag = est.q0_pwr;
3648                                         } else {
3649                                                 real = est.i1_pwr;
3650                                                 imag = est.q1_pwr;
3651                                         }
3652                                         power[i] = ((real + imag) / 1024) + 1;
3653                                 } else {
3654                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3655                                 }
3656                                 b43_nphy_stop_playback(dev);
3657                         }
3658
3659                         if (ret != 0)
3660                                 break;
3661                 }
3662
3663                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3664                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3665                 b43_phy_write(dev, rfctl[1], tmp[5]);
3666                 b43_phy_write(dev, rfctl[0], tmp[4]);
3667                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3668                 b43_phy_write(dev, afectl_core, tmp[2]);
3669                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3670
3671                 if (ret != 0)
3672                         break;
3673         }
3674
3675         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3676         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3677         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3678
3679         b43_nphy_stay_in_carrier_search(dev, 0);
3680
3681         return ret;
3682 }
3683
3684 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3685                         struct nphy_txgains target, u8 type, bool debug)
3686 {
3687         return -1;
3688 }
3689
3690 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3691 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3692                         struct nphy_txgains target, u8 type, bool debug)
3693 {
3694         if (dev->phy.rev >= 3)
3695                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3696         else
3697                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3698 }
3699
3700 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3701 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3702 {
3703         struct b43_phy *phy = &dev->phy;
3704         struct b43_phy_n *nphy = phy->n;
3705         /* u16 buf[16]; it's rev3+ */
3706
3707         nphy->phyrxchain = mask;
3708
3709         if (0 /* FIXME clk */)
3710                 return;
3711
3712         b43_mac_suspend(dev);
3713
3714         if (nphy->hang_avoid)
3715                 b43_nphy_stay_in_carrier_search(dev, true);
3716
3717         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3718                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3719
3720         if ((mask & 0x3) != 0x3) {
3721                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3722                 if (dev->phy.rev >= 3) {
3723                         /* TODO */
3724                 }
3725         } else {
3726                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3727                 if (dev->phy.rev >= 3) {
3728                         /* TODO */
3729                 }
3730         }
3731
3732         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3733
3734         if (nphy->hang_avoid)
3735                 b43_nphy_stay_in_carrier_search(dev, false);
3736
3737         b43_mac_enable(dev);
3738 }
3739
3740 /*
3741  * Init N-PHY
3742  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3743  */
3744 int b43_phy_initn(struct b43_wldev *dev)
3745 {
3746         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3747         struct b43_phy *phy = &dev->phy;
3748         struct b43_phy_n *nphy = phy->n;
3749         u8 tx_pwr_state;
3750         struct nphy_txgains target;
3751         u16 tmp;
3752         enum ieee80211_band tmp2;
3753         bool do_rssi_cal;
3754
3755         u16 clip[2];
3756         bool do_cal = false;
3757
3758         if ((dev->phy.rev >= 3) &&
3759            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3760            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3761                 switch (dev->dev->bus_type) {
3762 #ifdef CONFIG_B43_BCMA
3763                 case B43_BUS_BCMA:
3764                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3765                                       BCMA_CC_CHIPCTL, 0x40);
3766                         break;
3767 #endif
3768 #ifdef CONFIG_B43_SSB
3769                 case B43_BUS_SSB:
3770                         chipco_set32(&dev->dev->sdev->bus->chipco,
3771                                      SSB_CHIPCO_CHIPCTL, 0x40);
3772                         break;
3773 #endif
3774                 }
3775         }
3776         nphy->deaf_count = 0;
3777         b43_nphy_tables_init(dev);
3778         nphy->crsminpwr_adjusted = false;
3779         nphy->noisevars_adjusted = false;
3780
3781         /* Clear all overrides */
3782         if (dev->phy.rev >= 3) {
3783                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3784                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3785                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3786                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3787         } else {
3788                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3789         }
3790         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3791         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3792         if (dev->phy.rev < 6) {
3793                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3794                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3795         }
3796         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3797                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3798                        B43_NPHY_RFSEQMODE_TROVER));
3799         if (dev->phy.rev >= 3)
3800                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3801         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3802
3803         if (dev->phy.rev <= 2) {
3804                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3805                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3806                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3807                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3808         }
3809         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3810         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3811
3812         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
3813             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3814              dev->dev->board_type == 0x8B))
3815                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3816         else
3817                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3818         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3819         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3820         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3821
3822         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3823         b43_nphy_update_txrx_chain(dev);
3824
3825         if (phy->rev < 2) {
3826                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3827                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3828         }
3829
3830         tmp2 = b43_current_band(dev->wl);
3831         if (b43_nphy_ipa(dev)) {
3832                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3833                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3834                                 nphy->papd_epsilon_offset[0] << 7);
3835                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3836                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3837                                 nphy->papd_epsilon_offset[1] << 7);
3838                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3839         } else if (phy->rev >= 5) {
3840                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3841         }
3842
3843         b43_nphy_workarounds(dev);
3844
3845         /* Reset CCA, in init code it differs a little from standard way */
3846         b43_phy_force_clock(dev, 1);
3847         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3848         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3849         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3850         b43_phy_force_clock(dev, 0);
3851
3852         b43_mac_phy_clock_set(dev, true);
3853
3854         b43_nphy_pa_override(dev, false);
3855         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3856         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3857         b43_nphy_pa_override(dev, true);
3858
3859         b43_nphy_classifier(dev, 0, 0);
3860         b43_nphy_read_clip_detection(dev, clip);
3861         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3862                 b43_nphy_bphy_init(dev);
3863
3864         tx_pwr_state = nphy->txpwrctrl;
3865         b43_nphy_tx_power_ctrl(dev, false);
3866         b43_nphy_tx_power_fix(dev);
3867         /* TODO N PHY TX Power Control Idle TSSI */
3868         /* TODO N PHY TX Power Control Setup */
3869         b43_nphy_tx_gain_table_upload(dev);
3870
3871         if (nphy->phyrxchain != 3)
3872                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3873         if (nphy->mphase_cal_phase_id > 0)
3874                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3875
3876         do_rssi_cal = false;
3877         if (phy->rev >= 3) {
3878                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3879                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3880                 else
3881                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3882
3883                 if (do_rssi_cal)
3884                         b43_nphy_rssi_cal(dev);
3885                 else
3886                         b43_nphy_restore_rssi_cal(dev);
3887         } else {
3888                 b43_nphy_rssi_cal(dev);
3889         }
3890
3891         if (!((nphy->measure_hold & 0x6) != 0)) {
3892                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3893                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3894                 else
3895                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3896
3897                 if (nphy->mute)
3898                         do_cal = false;
3899
3900                 if (do_cal) {
3901                         target = b43_nphy_get_tx_gains(dev);
3902
3903                         if (nphy->antsel_type == 2)
3904                                 b43_nphy_superswitch_init(dev, true);
3905                         if (nphy->perical != 2) {
3906                                 b43_nphy_rssi_cal(dev);
3907                                 if (phy->rev >= 3) {
3908                                         nphy->cal_orig_pwr_idx[0] =
3909                                             nphy->txpwrindex[0].index_internal;
3910                                         nphy->cal_orig_pwr_idx[1] =
3911                                             nphy->txpwrindex[1].index_internal;
3912                                         /* TODO N PHY Pre Calibrate TX Gain */
3913                                         target = b43_nphy_get_tx_gains(dev);
3914                                 }
3915                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3916                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3917                                                 b43_nphy_save_cal(dev);
3918                         } else if (nphy->mphase_cal_phase_id == 0)
3919                                 ;/* N PHY Periodic Calibration with arg 3 */
3920                 } else {
3921                         b43_nphy_restore_cal(dev);
3922                 }
3923         }
3924
3925         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3926         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3927         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3928         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3929         if (phy->rev >= 3 && phy->rev <= 6)
3930                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3931         b43_nphy_tx_lp_fbw(dev);
3932         if (phy->rev >= 3)
3933                 b43_nphy_spur_workaround(dev);
3934
3935         return 0;
3936 }
3937
3938 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3939 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3940                                 const struct b43_phy_n_sfo_cfg *e,
3941                                 struct ieee80211_channel *new_channel)
3942 {
3943         struct b43_phy *phy = &dev->phy;
3944         struct b43_phy_n *nphy = dev->phy.n;
3945
3946         u16 old_band_5ghz;
3947         u32 tmp32;
3948
3949         old_band_5ghz =
3950                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3951         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3952                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3953                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3954                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3955                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3956                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3957         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3958                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3959                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3960                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3961                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3962                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3963         }
3964
3965         b43_chantab_phy_upload(dev, e);
3966
3967         if (new_channel->hw_value == 14) {
3968                 b43_nphy_classifier(dev, 2, 0);
3969                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3970         } else {
3971                 b43_nphy_classifier(dev, 2, 2);
3972                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3973                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3974         }
3975
3976         if (!nphy->txpwrctrl)
3977                 b43_nphy_tx_power_fix(dev);
3978
3979         if (dev->phy.rev < 3)
3980                 b43_nphy_adjust_lna_gain_table(dev);
3981
3982         b43_nphy_tx_lp_fbw(dev);
3983
3984         if (dev->phy.rev >= 3 && 0) {
3985                 /* TODO */
3986         }
3987
3988         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3989
3990         if (phy->rev >= 3)
3991                 b43_nphy_spur_workaround(dev);
3992 }
3993
3994 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3995 static int b43_nphy_set_channel(struct b43_wldev *dev,
3996                                 struct ieee80211_channel *channel,
3997                                 enum nl80211_channel_type channel_type)
3998 {
3999         struct b43_phy *phy = &dev->phy;
4000
4001         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4002         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
4003
4004         u8 tmp;
4005
4006         if (dev->phy.rev >= 3) {
4007                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4008                                                         channel->center_freq);
4009                 if (!tabent_r3)
4010                         return -ESRCH;
4011         } else {
4012                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4013                                                         channel->hw_value);
4014                 if (!tabent_r2)
4015                         return -ESRCH;
4016         }
4017
4018         /* Channel is set later in common code, but we need to set it on our
4019            own to let this function's subcalls work properly. */
4020         phy->channel = channel->hw_value;
4021         phy->channel_freq = channel->center_freq;
4022
4023         if (b43_channel_type_is_40mhz(phy->channel_type) !=
4024                 b43_channel_type_is_40mhz(channel_type))
4025                 ; /* TODO: BMAC BW Set (channel_type) */
4026
4027         if (channel_type == NL80211_CHAN_HT40PLUS)
4028                 b43_phy_set(dev, B43_NPHY_RXCTL,
4029                                 B43_NPHY_RXCTL_BSELU20);
4030         else if (channel_type == NL80211_CHAN_HT40MINUS)
4031                 b43_phy_mask(dev, B43_NPHY_RXCTL,
4032                                 ~B43_NPHY_RXCTL_BSELU20);
4033
4034         if (dev->phy.rev >= 3) {
4035                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
4036                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
4037                 b43_radio_2056_setup(dev, tabent_r3);
4038                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
4039         } else {
4040                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
4041                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
4042                 b43_radio_2055_setup(dev, tabent_r2);
4043                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
4044         }
4045
4046         return 0;
4047 }
4048
4049 static int b43_nphy_op_allocate(struct b43_wldev *dev)
4050 {
4051         struct b43_phy_n *nphy;
4052
4053         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4054         if (!nphy)
4055                 return -ENOMEM;
4056         dev->phy.n = nphy;
4057
4058         return 0;
4059 }
4060
4061 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4062 {
4063         struct b43_phy *phy = &dev->phy;
4064         struct b43_phy_n *nphy = phy->n;
4065         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4066
4067         memset(nphy, 0, sizeof(*nphy));
4068
4069         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
4070         nphy->spur_avoid = (phy->rev >= 3) ?
4071                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
4072         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4073         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4074         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
4075         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
4076         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4077          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4078         nphy->tx_pwr_idx[0] = 128;
4079         nphy->tx_pwr_idx[1] = 128;
4080
4081         /* Hardware TX power control and 5GHz power gain */
4082         nphy->txpwrctrl = false;
4083         nphy->pwg_gain_5ghz = false;
4084         if (dev->phy.rev >= 3 ||
4085             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4086              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4087                 nphy->txpwrctrl = true;
4088                 nphy->pwg_gain_5ghz = true;
4089         } else if (sprom->revision >= 4) {
4090                 if (dev->phy.rev >= 2 &&
4091                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4092                         nphy->txpwrctrl = true;
4093 #ifdef CONFIG_B43_SSB
4094                         if (dev->dev->bus_type == B43_BUS_SSB &&
4095                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4096                                 struct pci_dev *pdev =
4097                                         dev->dev->sdev->bus->host_pci;
4098                                 if (pdev->device == 0x4328 ||
4099                                     pdev->device == 0x432a)
4100                                         nphy->pwg_gain_5ghz = true;
4101                         }
4102 #endif
4103                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4104                         nphy->pwg_gain_5ghz = true;
4105                 }
4106         }
4107
4108         if (dev->phy.rev >= 3) {
4109                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4110                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4111         }
4112 }
4113
4114 static void b43_nphy_op_free(struct b43_wldev *dev)
4115 {
4116         struct b43_phy *phy = &dev->phy;
4117         struct b43_phy_n *nphy = phy->n;
4118
4119         kfree(nphy);
4120         phy->n = NULL;
4121 }
4122
4123 static int b43_nphy_op_init(struct b43_wldev *dev)
4124 {
4125         return b43_phy_initn(dev);
4126 }
4127
4128 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4129 {
4130 #if B43_DEBUG
4131         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4132                 /* OFDM registers are onnly available on A/G-PHYs */
4133                 b43err(dev->wl, "Invalid OFDM PHY access at "
4134                        "0x%04X on N-PHY\n", offset);
4135                 dump_stack();
4136         }
4137         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4138                 /* Ext-G registers are only available on G-PHYs */
4139                 b43err(dev->wl, "Invalid EXT-G PHY access at "
4140                        "0x%04X on N-PHY\n", offset);
4141                 dump_stack();
4142         }
4143 #endif /* B43_DEBUG */
4144 }
4145
4146 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4147 {
4148         check_phyreg(dev, reg);
4149         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4150         return b43_read16(dev, B43_MMIO_PHY_DATA);
4151 }
4152
4153 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4154 {
4155         check_phyreg(dev, reg);
4156         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4157         b43_write16(dev, B43_MMIO_PHY_DATA, value);
4158 }
4159
4160 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4161                                  u16 set)
4162 {
4163         check_phyreg(dev, reg);
4164         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4165         b43_write16(dev, B43_MMIO_PHY_DATA,
4166                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4167 }
4168
4169 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4170 {
4171         /* Register 1 is a 32-bit register. */
4172         B43_WARN_ON(reg == 1);
4173         /* N-PHY needs 0x100 for read access */
4174         reg |= 0x100;
4175
4176         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4177         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4178 }
4179
4180 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4181 {
4182         /* Register 1 is a 32-bit register. */
4183         B43_WARN_ON(reg == 1);
4184
4185         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4186         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4187 }
4188
4189 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4190 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4191                                         bool blocked)
4192 {
4193         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4194                 b43err(dev->wl, "MAC not suspended\n");
4195
4196         if (blocked) {
4197                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4198                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4199                 if (dev->phy.rev >= 3) {
4200                         b43_radio_mask(dev, 0x09, ~0x2);
4201
4202                         b43_radio_write(dev, 0x204D, 0);
4203                         b43_radio_write(dev, 0x2053, 0);
4204                         b43_radio_write(dev, 0x2058, 0);
4205                         b43_radio_write(dev, 0x205E, 0);
4206                         b43_radio_mask(dev, 0x2062, ~0xF0);
4207                         b43_radio_write(dev, 0x2064, 0);
4208
4209                         b43_radio_write(dev, 0x304D, 0);
4210                         b43_radio_write(dev, 0x3053, 0);
4211                         b43_radio_write(dev, 0x3058, 0);
4212                         b43_radio_write(dev, 0x305E, 0);
4213                         b43_radio_mask(dev, 0x3062, ~0xF0);
4214                         b43_radio_write(dev, 0x3064, 0);
4215                 }
4216         } else {
4217                 if (dev->phy.rev >= 3) {
4218                         b43_radio_init2056(dev);
4219                         b43_switch_channel(dev, dev->phy.channel);
4220                 } else {
4221                         b43_radio_init2055(dev);
4222                 }
4223         }
4224 }
4225
4226 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4227 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4228 {
4229         u16 override = on ? 0x0 : 0x7FFF;
4230         u16 core = on ? 0xD : 0x00FD;
4231
4232         if (dev->phy.rev >= 3) {
4233                 if (on) {
4234                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4235                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4236                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4237                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4238                 } else {
4239                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4240                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4241                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4242                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4243                 }
4244         } else {
4245                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4246         }
4247 }
4248
4249 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4250                                       unsigned int new_channel)
4251 {
4252         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4253         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4254
4255         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4256                 if ((new_channel < 1) || (new_channel > 14))
4257                         return -EINVAL;
4258         } else {
4259                 if (new_channel > 200)
4260                         return -EINVAL;
4261         }
4262
4263         return b43_nphy_set_channel(dev, channel, channel_type);
4264 }
4265
4266 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4267 {
4268         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4269                 return 1;
4270         return 36;
4271 }
4272
4273 const struct b43_phy_operations b43_phyops_n = {
4274         .allocate               = b43_nphy_op_allocate,
4275         .free                   = b43_nphy_op_free,
4276         .prepare_structs        = b43_nphy_op_prepare_structs,
4277         .init                   = b43_nphy_op_init,
4278         .phy_read               = b43_nphy_op_read,
4279         .phy_write              = b43_nphy_op_write,
4280         .phy_maskset            = b43_nphy_op_maskset,
4281         .radio_read             = b43_nphy_op_radio_read,
4282         .radio_write            = b43_nphy_op_radio_write,
4283         .software_rfkill        = b43_nphy_op_software_rfkill,
4284         .switch_analog          = b43_nphy_op_switch_analog,
4285         .switch_channel         = b43_nphy_op_switch_channel,
4286         .get_default_chan       = b43_nphy_op_get_default_chan,
4287         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4288         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4289 };