3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/pci.h>
33 #include <linux/types.h>
36 #include "bcm43xx_phy.h"
37 #include "bcm43xx_main.h"
38 #include "bcm43xx_radio.h"
39 #include "bcm43xx_ilt.h"
40 #include "bcm43xx_power.h"
43 static const s8 bcm43xx_tssi2dbm_b_table[] = {
44 0x4D, 0x4C, 0x4B, 0x4A,
45 0x4A, 0x49, 0x48, 0x47,
46 0x47, 0x46, 0x45, 0x45,
47 0x44, 0x43, 0x42, 0x42,
48 0x41, 0x40, 0x3F, 0x3E,
49 0x3D, 0x3C, 0x3B, 0x3A,
50 0x39, 0x38, 0x37, 0x36,
51 0x35, 0x34, 0x32, 0x31,
52 0x30, 0x2F, 0x2D, 0x2C,
53 0x2B, 0x29, 0x28, 0x26,
54 0x25, 0x23, 0x21, 0x1F,
55 0x1D, 0x1A, 0x17, 0x14,
56 0x10, 0x0C, 0x06, 0x00,
62 static const s8 bcm43xx_tssi2dbm_g_table[] = {
81 static void bcm43xx_phy_initg(struct bcm43xx_private *bcm);
84 void bcm43xx_raw_phy_lock(struct bcm43xx_private *bcm)
86 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
88 assert(irqs_disabled());
89 if (bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD) == 0x00000000) {
93 if (bcm->current_core->rev < 3) {
94 bcm43xx_mac_suspend(bcm);
95 spin_lock(&phy->lock);
97 if (bcm->ieee->iw_mode != IW_MODE_MASTER)
98 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
103 void bcm43xx_raw_phy_unlock(struct bcm43xx_private *bcm)
105 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
107 assert(irqs_disabled());
108 if (bcm->current_core->rev < 3) {
109 if (phy->is_locked) {
110 spin_unlock(&phy->lock);
111 bcm43xx_mac_enable(bcm);
114 if (bcm->ieee->iw_mode != IW_MODE_MASTER)
115 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
120 u16 bcm43xx_phy_read(struct bcm43xx_private *bcm, u16 offset)
122 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_CONTROL, offset);
123 return bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_DATA);
126 void bcm43xx_phy_write(struct bcm43xx_private *bcm, u16 offset, u16 val)
128 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_CONTROL, offset);
129 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_DATA, val);
132 void bcm43xx_phy_calibrate(struct bcm43xx_private *bcm)
134 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
137 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* Dummy read. */
140 if (phy->type == BCM43xx_PHYTYPE_G && phy->rev == 1) {
141 /* We do not want to be preempted while calibrating
144 local_irq_save(flags);
146 bcm43xx_wireless_core_reset(bcm, 0);
147 bcm43xx_phy_initg(bcm);
148 bcm43xx_wireless_core_reset(bcm, 1);
150 local_irq_restore(flags);
156 * http://bcm-specs.sipsolutions.net/SetPHY
158 int bcm43xx_phy_connect(struct bcm43xx_private *bcm, int connect)
162 if (bcm->current_core->rev < 5) {
164 bcm->current_core->phy->connected = 1;
165 dprintk(KERN_INFO PFX "PHY connected\n");
167 bcm->current_core->phy->connected = 0;
168 dprintk(KERN_INFO PFX "PHY disconnected\n");
173 flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
175 if (!(flags & 0x00010000))
177 bcm->current_core->phy->connected = 1;
179 flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
180 flags |= (0x800 << 18);
181 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, flags);
182 dprintk(KERN_INFO PFX "PHY connected\n");
184 if (!(flags & 0x00020000))
186 bcm->current_core->phy->connected = 0;
188 flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
189 flags &= ~(0x800 << 18);
190 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, flags);
191 dprintk(KERN_INFO PFX "PHY disconnected\n");
197 /* intialize B PHY power control
198 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
200 static void bcm43xx_phy_init_pctl(struct bcm43xx_private *bcm)
202 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
203 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
204 u16 saved_batt = 0, saved_ratt = 0, saved_txctl1 = 0;
205 int must_reset_txpower = 0;
207 assert(phy->type != BCM43xx_PHYTYPE_A);
208 if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM) &&
209 (bcm->board_type == 0x0416))
212 bcm43xx_write16(bcm, 0x03E6, bcm43xx_read16(bcm, 0x03E6) & 0xFFDF);
213 bcm43xx_phy_write(bcm, 0x0028, 0x8018);
215 if (phy->type == BCM43xx_PHYTYPE_G) {
218 bcm43xx_phy_write(bcm, 0x047A, 0xC111);
220 if (phy->savedpctlreg != 0xFFFF)
223 if (phy->type == BCM43xx_PHYTYPE_B &&
225 radio->version == 0x2050) {
226 bcm43xx_radio_write16(bcm, 0x0076,
227 bcm43xx_radio_read16(bcm, 0x0076) | 0x0084);
229 saved_batt = radio->txpower[0];
230 saved_ratt = radio->txpower[1];
231 saved_txctl1 = radio->txpower[2];
232 if ((radio->revision >= 6) && (radio->revision <= 8)
233 && /*FIXME: incomplete specs for 5 < revision < 9 */ 0)
234 bcm43xx_radio_set_txpower_bg(bcm, 0xB, 0x1F, 0);
236 bcm43xx_radio_set_txpower_bg(bcm, 0xB, 9, 0);
237 must_reset_txpower = 1;
239 bcm43xx_dummy_transmission(bcm);
241 phy->savedpctlreg = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_PCTL);
243 if (must_reset_txpower)
244 bcm43xx_radio_set_txpower_bg(bcm, saved_batt, saved_ratt, saved_txctl1);
246 bcm43xx_radio_write16(bcm, 0x0076, bcm43xx_radio_read16(bcm, 0x0076) & 0xFF7B);
247 bcm43xx_radio_clear_tssi(bcm);
250 static void bcm43xx_phy_agcsetup(struct bcm43xx_private *bcm)
252 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
258 bcm43xx_ilt_write16(bcm, offset, 0x00FE);
259 bcm43xx_ilt_write16(bcm, offset + 1, 0x000D);
260 bcm43xx_ilt_write16(bcm, offset + 2, 0x0013);
261 bcm43xx_ilt_write16(bcm, offset + 3, 0x0019);
264 bcm43xx_ilt_write16(bcm, 0x1800, 0x2710);
265 bcm43xx_ilt_write16(bcm, 0x1801, 0x9B83);
266 bcm43xx_ilt_write16(bcm, 0x1802, 0x9B83);
267 bcm43xx_ilt_write16(bcm, 0x1803, 0x0F8D);
268 bcm43xx_phy_write(bcm, 0x0455, 0x0004);
271 bcm43xx_phy_write(bcm, 0x04A5, (bcm43xx_phy_read(bcm, 0x04A5) & 0x00FF) | 0x5700);
272 bcm43xx_phy_write(bcm, 0x041A, (bcm43xx_phy_read(bcm, 0x041A) & 0xFF80) | 0x000F);
273 bcm43xx_phy_write(bcm, 0x041A, (bcm43xx_phy_read(bcm, 0x041A) & 0xC07F) | 0x2B80);
274 bcm43xx_phy_write(bcm, 0x048C, (bcm43xx_phy_read(bcm, 0x048C) & 0xF0FF) | 0x0300);
276 bcm43xx_radio_write16(bcm, 0x007A, bcm43xx_radio_read16(bcm, 0x007A) | 0x0008);
278 bcm43xx_phy_write(bcm, 0x04A0, (bcm43xx_phy_read(bcm, 0x04A0) & 0xFFF0) | 0x0008);
279 bcm43xx_phy_write(bcm, 0x04A1, (bcm43xx_phy_read(bcm, 0x04A1) & 0xF0FF) | 0x0600);
280 bcm43xx_phy_write(bcm, 0x04A2, (bcm43xx_phy_read(bcm, 0x04A2) & 0xF0FF) | 0x0700);
281 bcm43xx_phy_write(bcm, 0x04A0, (bcm43xx_phy_read(bcm, 0x04A0) & 0xF0FF) | 0x0100);
284 bcm43xx_phy_write(bcm, 0x04A2, (bcm43xx_phy_read(bcm, 0x04A2) & 0xFFF0) | 0x0007);
286 bcm43xx_phy_write(bcm, 0x0488, (bcm43xx_phy_read(bcm, 0x0488) & 0xFF00) | 0x001C);
287 bcm43xx_phy_write(bcm, 0x0488, (bcm43xx_phy_read(bcm, 0x0488) & 0xC0FF) | 0x0200);
288 bcm43xx_phy_write(bcm, 0x0496, (bcm43xx_phy_read(bcm, 0x0496) & 0xFF00) | 0x001C);
289 bcm43xx_phy_write(bcm, 0x0489, (bcm43xx_phy_read(bcm, 0x0489) & 0xFF00) | 0x0020);
290 bcm43xx_phy_write(bcm, 0x0489, (bcm43xx_phy_read(bcm, 0x0489) & 0xC0FF) | 0x0200);
291 bcm43xx_phy_write(bcm, 0x0482, (bcm43xx_phy_read(bcm, 0x0482) & 0xFF00) | 0x002E);
292 bcm43xx_phy_write(bcm, 0x0496, (bcm43xx_phy_read(bcm, 0x0496) & 0x00FF) | 0x1A00);
293 bcm43xx_phy_write(bcm, 0x0481, (bcm43xx_phy_read(bcm, 0x0481) & 0xFF00) | 0x0028);
294 bcm43xx_phy_write(bcm, 0x0481, (bcm43xx_phy_read(bcm, 0x0481) & 0x00FF) | 0x2C00);
297 bcm43xx_phy_write(bcm, 0x0430, 0x092B);
298 bcm43xx_phy_write(bcm, 0x041B, (bcm43xx_phy_read(bcm, 0x041B) & 0xFFE1) | 0x0002);
300 bcm43xx_phy_write(bcm, 0x041B, bcm43xx_phy_read(bcm, 0x041B) & 0xFFE1);
301 bcm43xx_phy_write(bcm, 0x041F, 0x287A);
302 bcm43xx_phy_write(bcm, 0x0420, (bcm43xx_phy_read(bcm, 0x0420) & 0xFFF0) | 0x0004);
306 bcm43xx_phy_write(bcm, 0x0422, 0x287A);
307 bcm43xx_phy_write(bcm, 0x0420, (bcm43xx_phy_read(bcm, 0x0420) & 0x0FFF) | 0x3000);
310 bcm43xx_phy_write(bcm, 0x04A8, (bcm43xx_phy_read(bcm, 0x04A8) & 0x8080) | 0x7874);
311 bcm43xx_phy_write(bcm, 0x048E, 0x1C00);
314 bcm43xx_phy_write(bcm, 0x04AB, (bcm43xx_phy_read(bcm, 0x04AB) & 0xF0FF) | 0x0600);
315 bcm43xx_phy_write(bcm, 0x048B, 0x005E);
316 bcm43xx_phy_write(bcm, 0x048C, (bcm43xx_phy_read(bcm, 0x048C) & 0xFF00) | 0x001E);
317 bcm43xx_phy_write(bcm, 0x048D, 0x0002);
320 bcm43xx_ilt_write16(bcm, offset + 0x0800, 0);
321 bcm43xx_ilt_write16(bcm, offset + 0x0801, 7);
322 bcm43xx_ilt_write16(bcm, offset + 0x0802, 16);
323 bcm43xx_ilt_write16(bcm, offset + 0x0803, 28);
326 static void bcm43xx_phy_setupg(struct bcm43xx_private *bcm)
328 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
331 assert(phy->type == BCM43xx_PHYTYPE_G);
333 bcm43xx_phy_write(bcm, 0x0406, 0x4F19);
334 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
335 (bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & 0xFC3F) | 0x0340);
336 bcm43xx_phy_write(bcm, 0x042C, 0x005A);
337 bcm43xx_phy_write(bcm, 0x0427, 0x001A);
339 for (i = 0; i < BCM43xx_ILT_FINEFREQG_SIZE; i++)
340 bcm43xx_ilt_write16(bcm, 0x5800 + i, bcm43xx_ilt_finefreqg[i]);
341 for (i = 0; i < BCM43xx_ILT_NOISEG1_SIZE; i++)
342 bcm43xx_ilt_write16(bcm, 0x1800 + i, bcm43xx_ilt_noiseg1[i]);
343 for (i = 0; i < BCM43xx_ILT_ROTOR_SIZE; i++)
344 bcm43xx_ilt_write16(bcm, 0x2000 + i, bcm43xx_ilt_rotor[i]);
346 /* nrssi values are signed 6-bit values. Not sure why we write 0x7654 here... */
347 bcm43xx_nrssi_hw_write(bcm, 0xBA98, (s16)0x7654);
350 bcm43xx_phy_write(bcm, 0x04C0, 0x1861);
351 bcm43xx_phy_write(bcm, 0x04C1, 0x0271);
352 } else if (phy->rev > 2) {
353 bcm43xx_phy_write(bcm, 0x04C0, 0x0098);
354 bcm43xx_phy_write(bcm, 0x04C1, 0x0070);
355 bcm43xx_phy_write(bcm, 0x04C9, 0x0080);
357 bcm43xx_phy_write(bcm, 0x042B, bcm43xx_phy_read(bcm, 0x042B) | 0x800);
359 for (i = 0; i < 64; i++)
360 bcm43xx_ilt_write16(bcm, 0x4000 + i, i);
361 for (i = 0; i < BCM43xx_ILT_NOISEG2_SIZE; i++)
362 bcm43xx_ilt_write16(bcm, 0x1800 + i, bcm43xx_ilt_noiseg2[i]);
366 for (i = 0; i < BCM43xx_ILT_NOISESCALEG_SIZE; i++)
367 bcm43xx_ilt_write16(bcm, 0x1400 + i, bcm43xx_ilt_noisescaleg1[i]);
368 else if ((phy->rev == 7) && (bcm43xx_phy_read(bcm, 0x0449) & 0x0200))
369 for (i = 0; i < BCM43xx_ILT_NOISESCALEG_SIZE; i++)
370 bcm43xx_ilt_write16(bcm, 0x1400 + i, bcm43xx_ilt_noisescaleg3[i]);
372 for (i = 0; i < BCM43xx_ILT_NOISESCALEG_SIZE; i++)
373 bcm43xx_ilt_write16(bcm, 0x1400 + i, bcm43xx_ilt_noisescaleg2[i]);
376 for (i = 0; i < BCM43xx_ILT_SIGMASQR_SIZE; i++)
377 bcm43xx_ilt_write16(bcm, 0x5000 + i, bcm43xx_ilt_sigmasqr1[i]);
378 else if ((phy->rev > 2) && (phy->rev <= 7))
379 for (i = 0; i < BCM43xx_ILT_SIGMASQR_SIZE; i++)
380 bcm43xx_ilt_write16(bcm, 0x5000 + i, bcm43xx_ilt_sigmasqr2[i]);
383 for (i = 0; i < BCM43xx_ILT_RETARD_SIZE; i++)
384 bcm43xx_ilt_write16(bcm, 0x2400 + i, bcm43xx_ilt_retard[i]);
385 for (i = 0; i < 4; i++) {
386 bcm43xx_ilt_write16(bcm, 0x5404 + i, 0x0020);
387 bcm43xx_ilt_write16(bcm, 0x5408 + i, 0x0020);
388 bcm43xx_ilt_write16(bcm, 0x540C + i, 0x0020);
389 bcm43xx_ilt_write16(bcm, 0x5410 + i, 0x0020);
391 bcm43xx_phy_agcsetup(bcm);
393 if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM) &&
394 (bcm->board_type == 0x0416) &&
395 (bcm->board_revision == 0x0017))
398 bcm43xx_ilt_write16(bcm, 0x5001, 0x0002);
399 bcm43xx_ilt_write16(bcm, 0x5002, 0x0001);
401 for (i = 0; i <= 0x2F; i++)
402 bcm43xx_ilt_write16(bcm, 0x1000 + i, 0x0820);
403 bcm43xx_phy_agcsetup(bcm);
404 bcm43xx_phy_read(bcm, 0x0400); /* dummy read */
405 bcm43xx_phy_write(bcm, 0x0403, 0x1000);
406 bcm43xx_ilt_write16(bcm, 0x3C02, 0x000F);
407 bcm43xx_ilt_write16(bcm, 0x3C03, 0x0014);
409 if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM) &&
410 (bcm->board_type == 0x0416) &&
411 (bcm->board_revision == 0x0017))
414 bcm43xx_ilt_write16(bcm, 0x0401, 0x0002);
415 bcm43xx_ilt_write16(bcm, 0x0402, 0x0001);
419 /* Initialize the noisescaletable for APHY */
420 static void bcm43xx_phy_init_noisescaletbl(struct bcm43xx_private *bcm)
422 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
425 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_CTRL, 0x1400);
426 for (i = 0; i < 12; i++) {
428 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x6767);
430 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x2323);
433 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x6700);
435 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x2300);
436 for (i = 0; i < 11; i++) {
438 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x6767);
440 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x2323);
443 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x0067);
445 bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, 0x0023);
448 static void bcm43xx_phy_setupa(struct bcm43xx_private *bcm)
452 assert(bcm->current_core->phy->type == BCM43xx_PHYTYPE_A);
453 switch (bcm->current_core->phy->rev) {
455 bcm43xx_phy_write(bcm, 0x008E, 0x3800);
456 bcm43xx_phy_write(bcm, 0x0035, 0x03FF);
457 bcm43xx_phy_write(bcm, 0x0036, 0x0400);
459 bcm43xx_ilt_write16(bcm, 0x3807, 0x0051);
461 bcm43xx_phy_write(bcm, 0x001C, 0x0FF9);
462 bcm43xx_phy_write(bcm, 0x0020, bcm43xx_phy_read(bcm, 0x0020) & 0xFF0F);
463 bcm43xx_ilt_write16(bcm, 0x3C0C, 0x07BF);
464 bcm43xx_radio_write16(bcm, 0x0002, 0x07BF);
466 bcm43xx_phy_write(bcm, 0x0024, 0x4680);
467 bcm43xx_phy_write(bcm, 0x0020, 0x0003);
468 bcm43xx_phy_write(bcm, 0x001D, 0x0F40);
469 bcm43xx_phy_write(bcm, 0x001F, 0x1C00);
471 bcm43xx_phy_write(bcm, 0x002A, (bcm43xx_phy_read(bcm, 0x002A) & 0x00FF) | 0x0400);
472 bcm43xx_phy_write(bcm, 0x002B, bcm43xx_phy_read(bcm, 0x002B) & 0xFBFF);
473 bcm43xx_phy_write(bcm, 0x008E, 0x58C1);
475 bcm43xx_ilt_write16(bcm, 0x0803, 0x000F);
476 bcm43xx_ilt_write16(bcm, 0x0804, 0x001F);
477 bcm43xx_ilt_write16(bcm, 0x0805, 0x002A);
478 bcm43xx_ilt_write16(bcm, 0x0805, 0x0030);
479 bcm43xx_ilt_write16(bcm, 0x0807, 0x003A);
481 bcm43xx_ilt_write16(bcm, 0x0000, 0x0013);
482 bcm43xx_ilt_write16(bcm, 0x0001, 0x0013);
483 bcm43xx_ilt_write16(bcm, 0x0002, 0x0013);
484 bcm43xx_ilt_write16(bcm, 0x0003, 0x0013);
485 bcm43xx_ilt_write16(bcm, 0x0004, 0x0015);
486 bcm43xx_ilt_write16(bcm, 0x0005, 0x0015);
487 bcm43xx_ilt_write16(bcm, 0x0006, 0x0019);
489 bcm43xx_ilt_write16(bcm, 0x0404, 0x0003);
490 bcm43xx_ilt_write16(bcm, 0x0405, 0x0003);
491 bcm43xx_ilt_write16(bcm, 0x0406, 0x0007);
493 for (i = 0; i < 16; i++)
494 bcm43xx_ilt_write16(bcm, 0x4000 + i, (0x8 + i) & 0x000F);
496 bcm43xx_ilt_write16(bcm, 0x3003, 0x1044);
497 bcm43xx_ilt_write16(bcm, 0x3004, 0x7201);
498 bcm43xx_ilt_write16(bcm, 0x3006, 0x0040);
499 bcm43xx_ilt_write16(bcm, 0x3001, (bcm43xx_ilt_read16(bcm, 0x3001) & 0x0010) | 0x0008);
501 for (i = 0; i < BCM43xx_ILT_FINEFREQA_SIZE; i++)
502 bcm43xx_ilt_write16(bcm, 0x5800 + i, bcm43xx_ilt_finefreqa[i]);
503 for (i = 0; i < BCM43xx_ILT_NOISEA2_SIZE; i++)
504 bcm43xx_ilt_write16(bcm, 0x1800 + i, bcm43xx_ilt_noisea2[i]);
505 for (i = 0; i < BCM43xx_ILT_ROTOR_SIZE; i++)
506 bcm43xx_ilt_write16(bcm, 0x2000 + i, bcm43xx_ilt_rotor[i]);
507 bcm43xx_phy_init_noisescaletbl(bcm);
508 for (i = 0; i < BCM43xx_ILT_RETARD_SIZE; i++)
509 bcm43xx_ilt_write16(bcm, 0x2400 + i, bcm43xx_ilt_retard[i]);
512 for (i = 0; i < 64; i++)
513 bcm43xx_ilt_write16(bcm, 0x4000 + i, i);
515 bcm43xx_ilt_write16(bcm, 0x3807, 0x0051);
517 bcm43xx_phy_write(bcm, 0x001C, 0x0FF9);
518 bcm43xx_phy_write(bcm, 0x0020, bcm43xx_phy_read(bcm, 0x0020) & 0xFF0F);
519 bcm43xx_radio_write16(bcm, 0x0002, 0x07BF);
521 bcm43xx_phy_write(bcm, 0x0024, 0x4680);
522 bcm43xx_phy_write(bcm, 0x0020, 0x0003);
523 bcm43xx_phy_write(bcm, 0x001D, 0x0F40);
524 bcm43xx_phy_write(bcm, 0x001F, 0x1C00);
525 bcm43xx_phy_write(bcm, 0x002A, (bcm43xx_phy_read(bcm, 0x002A) & 0x00FF) | 0x0400);
527 bcm43xx_ilt_write16(bcm, 0x3001, (bcm43xx_ilt_read16(bcm, 0x3001) & 0x0010) | 0x0008);
528 for (i = 0; i < BCM43xx_ILT_NOISEA3_SIZE; i++)
529 bcm43xx_ilt_write16(bcm, 0x1800 + i, bcm43xx_ilt_noisea3[i]);
530 bcm43xx_phy_init_noisescaletbl(bcm);
531 for (i = 0; i < BCM43xx_ILT_SIGMASQR_SIZE; i++)
532 bcm43xx_ilt_write16(bcm, 0x5000 + i, bcm43xx_ilt_sigmasqr1[i]);
534 bcm43xx_phy_write(bcm, 0x0003, 0x1808);
536 bcm43xx_ilt_write16(bcm, 0x0803, 0x000F);
537 bcm43xx_ilt_write16(bcm, 0x0804, 0x001F);
538 bcm43xx_ilt_write16(bcm, 0x0805, 0x002A);
539 bcm43xx_ilt_write16(bcm, 0x0805, 0x0030);
540 bcm43xx_ilt_write16(bcm, 0x0807, 0x003A);
542 bcm43xx_ilt_write16(bcm, 0x0000, 0x0013);
543 bcm43xx_ilt_write16(bcm, 0x0001, 0x0013);
544 bcm43xx_ilt_write16(bcm, 0x0002, 0x0013);
545 bcm43xx_ilt_write16(bcm, 0x0003, 0x0013);
546 bcm43xx_ilt_write16(bcm, 0x0004, 0x0015);
547 bcm43xx_ilt_write16(bcm, 0x0005, 0x0015);
548 bcm43xx_ilt_write16(bcm, 0x0006, 0x0019);
550 bcm43xx_ilt_write16(bcm, 0x0404, 0x0003);
551 bcm43xx_ilt_write16(bcm, 0x0405, 0x0003);
552 bcm43xx_ilt_write16(bcm, 0x0406, 0x0007);
554 bcm43xx_ilt_write16(bcm, 0x3C02, 0x000F);
555 bcm43xx_ilt_write16(bcm, 0x3C03, 0x0014);
562 /* Initialize APHY. This is also called for the GPHY in some cases. */
563 static void bcm43xx_phy_inita(struct bcm43xx_private *bcm)
565 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
568 if (phy->type == BCM43xx_PHYTYPE_A) {
569 bcm43xx_phy_setupa(bcm);
571 bcm43xx_phy_setupg(bcm);
572 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
573 bcm43xx_phy_write(bcm, 0x046E, 0x03CF);
577 bcm43xx_phy_write(bcm, BCM43xx_PHY_A_CRS,
578 (bcm43xx_phy_read(bcm, BCM43xx_PHY_A_CRS) & 0xF83C) | 0x0340);
579 bcm43xx_phy_write(bcm, 0x0034, 0x0001);
581 TODO();//TODO: RSSI AGC
582 bcm43xx_phy_write(bcm, BCM43xx_PHY_A_CRS,
583 bcm43xx_phy_read(bcm, BCM43xx_PHY_A_CRS) | (1 << 14));
584 bcm43xx_radio_init2060(bcm);
586 if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM)
587 && ((bcm->board_type == 0x0416) || (bcm->board_type == 0x040A))) {
588 if (bcm->current_core->radio->lofcal == 0xFFFF) {
589 TODO();//TODO: LOF Cal
590 bcm43xx_radio_set_tx_iq(bcm);
592 bcm43xx_radio_write16(bcm, 0x001E, bcm->current_core->radio->lofcal);
595 bcm43xx_phy_write(bcm, 0x007A, 0xF111);
597 if (phy->savedpctlreg == 0xFFFF) {
598 bcm43xx_radio_write16(bcm, 0x0019, 0x0000);
599 bcm43xx_radio_write16(bcm, 0x0017, 0x0020);
601 tval = bcm43xx_ilt_read16(bcm, 0x3001);
603 bcm43xx_ilt_write16(bcm, 0x3001,
604 (bcm43xx_ilt_read16(bcm, 0x3001) & 0xFF87)
607 bcm43xx_ilt_write16(bcm, 0x3001,
608 (bcm43xx_ilt_read16(bcm, 0x3001) & 0xFFC3)
611 bcm43xx_dummy_transmission(bcm);
612 phy->savedpctlreg = bcm43xx_phy_read(bcm, BCM43xx_PHY_A_PCTL);
613 bcm43xx_ilt_write16(bcm, 0x3001, tval);
615 bcm43xx_radio_set_txpower_a(bcm, 0x0018);
617 bcm43xx_radio_clear_tssi(bcm);
620 static void bcm43xx_phy_initb2(struct bcm43xx_private *bcm)
622 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
625 bcm43xx_write16(bcm, 0x03EC, 0x3F22);
626 bcm43xx_phy_write(bcm, 0x0020, 0x301C);
627 bcm43xx_phy_write(bcm, 0x0026, 0x0000);
628 bcm43xx_phy_write(bcm, 0x0030, 0x00C6);
629 bcm43xx_phy_write(bcm, 0x0088, 0x3E00);
631 for (offset = 0x0089; offset < 0x00A7; offset++) {
632 bcm43xx_phy_write(bcm, offset, val);
635 bcm43xx_phy_write(bcm, 0x03E4, 0x3000);
636 if (radio->channel == 0xFF)
637 bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_BG, 0);
639 bcm43xx_radio_selectchannel(bcm, radio->channel, 0);
640 if (radio->version != 0x2050) {
641 bcm43xx_radio_write16(bcm, 0x0075, 0x0080);
642 bcm43xx_radio_write16(bcm, 0x0079, 0x0081);
644 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
645 bcm43xx_radio_write16(bcm, 0x0050, 0x0023);
646 if (radio->version == 0x2050) {
647 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
648 bcm43xx_radio_write16(bcm, 0x005A, 0x0070);
649 bcm43xx_radio_write16(bcm, 0x005B, 0x007B);
650 bcm43xx_radio_write16(bcm, 0x005C, 0x00B0);
651 bcm43xx_radio_write16(bcm, 0x007A, 0x000F);
652 bcm43xx_phy_write(bcm, 0x0038, 0x0677);
653 bcm43xx_radio_init2050(bcm);
655 bcm43xx_phy_write(bcm, 0x0014, 0x0080);
656 bcm43xx_phy_write(bcm, 0x0032, 0x00CA);
657 bcm43xx_phy_write(bcm, 0x0032, 0x00CC);
658 bcm43xx_phy_write(bcm, 0x0035, 0x07C2);
659 bcm43xx_phy_lo_b_measure(bcm);
660 bcm43xx_phy_write(bcm, 0x0026, 0xCC00);
661 if (radio->version != 0x2050)
662 bcm43xx_phy_write(bcm, 0x0026, 0xCE00);
663 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, 0x1000);
664 bcm43xx_phy_write(bcm, 0x002A, 0x88A3);
665 if (radio->version != 0x2050)
666 bcm43xx_phy_write(bcm, 0x002A, 0x88C2);
667 bcm43xx_radio_set_txpower_bg(bcm, 0xFFFF, 0xFFFF, 0xFFFF);
668 bcm43xx_phy_init_pctl(bcm);
671 static void bcm43xx_phy_initb4(struct bcm43xx_private *bcm)
673 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
676 bcm43xx_write16(bcm, 0x03EC, 0x3F22);
677 bcm43xx_phy_write(bcm, 0x0020, 0x301C);
678 bcm43xx_phy_write(bcm, 0x0026, 0x0000);
679 bcm43xx_phy_write(bcm, 0x0030, 0x00C6);
680 bcm43xx_phy_write(bcm, 0x0088, 0x3E00);
682 for (offset = 0x0089; offset < 0x00A7; offset++) {
683 bcm43xx_phy_write(bcm, offset, val);
686 bcm43xx_phy_write(bcm, 0x03E4, 0x3000);
687 if (radio->channel == 0xFF)
688 bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_BG, 0);
690 bcm43xx_radio_selectchannel(bcm, radio->channel, 0);
691 if (radio->version != 0x2050) {
692 bcm43xx_radio_write16(bcm, 0x0075, 0x0080);
693 bcm43xx_radio_write16(bcm, 0x0079, 0x0081);
695 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
696 bcm43xx_radio_write16(bcm, 0x0050, 0x0023);
697 if (radio->version == 0x2050) {
698 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
699 bcm43xx_radio_write16(bcm, 0x005A, 0x0070);
700 bcm43xx_radio_write16(bcm, 0x005B, 0x007B);
701 bcm43xx_radio_write16(bcm, 0x005C, 0x00B0);
702 bcm43xx_radio_write16(bcm, 0x007A, 0x000F);
703 bcm43xx_phy_write(bcm, 0x0038, 0x0677);
704 bcm43xx_radio_init2050(bcm);
706 bcm43xx_phy_write(bcm, 0x0014, 0x0080);
707 bcm43xx_phy_write(bcm, 0x0032, 0x00CA);
708 if (radio->version == 0x2050)
709 bcm43xx_phy_write(bcm, 0x0032, 0x00E0);
710 bcm43xx_phy_write(bcm, 0x0035, 0x07C2);
712 bcm43xx_phy_lo_b_measure(bcm);
714 bcm43xx_phy_write(bcm, 0x0026, 0xCC00);
715 if (radio->version == 0x2050)
716 bcm43xx_phy_write(bcm, 0x0026, 0xCE00);
717 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, 0x1100);
718 bcm43xx_phy_write(bcm, 0x002A, 0x88A3);
719 if (radio->version == 0x2050)
720 bcm43xx_phy_write(bcm, 0x002A, 0x88C2);
721 bcm43xx_radio_set_txpower_bg(bcm, 0xFFFF, 0xFFFF, 0xFFFF);
722 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
723 bcm43xx_calc_nrssi_slope(bcm);
724 bcm43xx_calc_nrssi_threshold(bcm);
726 bcm43xx_phy_init_pctl(bcm);
729 static void bcm43xx_phy_initb5(struct bcm43xx_private *bcm)
731 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
732 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
735 if (phy->version == 1 &&
736 radio->version == 0x2050) {
737 bcm43xx_radio_write16(bcm, 0x007A,
738 bcm43xx_radio_read16(bcm, 0x007A)
741 if ((bcm->board_vendor != PCI_VENDOR_ID_BROADCOM) &&
742 (bcm->board_type != 0x0416)) {
743 for (offset = 0x00A8 ; offset < 0x00C7; offset++) {
744 bcm43xx_phy_write(bcm, offset,
745 (bcm43xx_phy_read(bcm, offset) + 0x2020)
749 bcm43xx_phy_write(bcm, 0x0035,
750 (bcm43xx_phy_read(bcm, 0x0035) & 0xF0FF)
752 if (radio->version == 0x2050)
753 bcm43xx_phy_write(bcm, 0x0038, 0x0667);
755 if (phy->connected) {
756 if (radio->version == 0x2050) {
757 bcm43xx_radio_write16(bcm, 0x007A,
758 bcm43xx_radio_read16(bcm, 0x007A)
760 bcm43xx_radio_write16(bcm, 0x0051,
761 bcm43xx_radio_read16(bcm, 0x0051)
764 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_RADIO, 0x0000);
766 bcm43xx_phy_write(bcm, 0x0802, bcm43xx_phy_read(bcm, 0x0802) | 0x0100);
767 bcm43xx_phy_write(bcm, 0x042B, bcm43xx_phy_read(bcm, 0x042B) | 0x2000);
769 bcm43xx_phy_write(bcm, 0x001C, 0x186A);
771 bcm43xx_phy_write(bcm, 0x0013, (bcm43xx_phy_read(bcm, 0x0013) & 0x00FF) | 0x1900);
772 bcm43xx_phy_write(bcm, 0x0035, (bcm43xx_phy_read(bcm, 0x0035) & 0xFFC0) | 0x0064);
773 bcm43xx_phy_write(bcm, 0x005D, (bcm43xx_phy_read(bcm, 0x005D) & 0xFF80) | 0x000A);
776 if (bcm->bad_frames_preempt) {
777 bcm43xx_phy_write(bcm, BCM43xx_PHY_RADIO_BITFIELD,
778 bcm43xx_phy_read(bcm, BCM43xx_PHY_RADIO_BITFIELD) | (1 << 11));
781 if (phy->version == 1 && radio->version == 0x2050) {
782 bcm43xx_phy_write(bcm, 0x0026, 0xCE00);
783 bcm43xx_phy_write(bcm, 0x0021, 0x3763);
784 bcm43xx_phy_write(bcm, 0x0022, 0x1BC3);
785 bcm43xx_phy_write(bcm, 0x0023, 0x06F9);
786 bcm43xx_phy_write(bcm, 0x0024, 0x037E);
788 bcm43xx_phy_write(bcm, 0x0026, 0xCC00);
789 bcm43xx_phy_write(bcm, 0x0030, 0x00C6);
790 bcm43xx_write16(bcm, 0x03EC, 0x3F22);
792 if (phy->version == 1 && radio->version == 0x2050)
793 bcm43xx_phy_write(bcm, 0x0020, 0x3E1C);
795 bcm43xx_phy_write(bcm, 0x0020, 0x301C);
797 if (phy->version == 0)
798 bcm43xx_write16(bcm, 0x03E4, 0x3000);
800 /* Force to channel 7, even if not supported. */
801 bcm43xx_radio_selectchannel(bcm, 7, 0);
803 if (radio->version != 0x2050) {
804 bcm43xx_radio_write16(bcm, 0x0075, 0x0080);
805 bcm43xx_radio_write16(bcm, 0x0079, 0x0081);
808 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
809 bcm43xx_radio_write16(bcm, 0x0050, 0x0023);
811 if (radio->version == 0x2050) {
812 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
813 bcm43xx_radio_write16(bcm, 0x005A, 0x0070);
816 bcm43xx_radio_write16(bcm, 0x005B, 0x007B);
817 bcm43xx_radio_write16(bcm, 0x005C, 0x00B0);
819 bcm43xx_radio_write16(bcm, 0x007A, bcm43xx_radio_read16(bcm, 0x007A) | 0x0007);
821 bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_BG, 0);
823 bcm43xx_phy_write(bcm, 0x0014, 0x0080);
824 bcm43xx_phy_write(bcm, 0x0032, 0x00CA);
825 bcm43xx_phy_write(bcm, 0x88A3, 0x002A);
827 bcm43xx_radio_set_txpower_bg(bcm, 0xFFFF, 0xFFFF, 0xFFFF);
829 if (radio->version == 0x2050)
830 bcm43xx_radio_write16(bcm, 0x005D, 0x000D);
832 bcm43xx_write16(bcm, 0x03E4, (bcm43xx_read16(bcm, 0x03E4) & 0xFFC0) | 0x0004);
835 static void bcm43xx_phy_initb6(struct bcm43xx_private *bcm)
837 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
838 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
841 bcm43xx_phy_write(bcm, 0x003E, 0x817A);
842 bcm43xx_radio_write16(bcm, 0x007A,
843 (bcm43xx_radio_read16(bcm, 0x007A) | 0x0058));
844 if ((radio->manufact == 0x17F) &&
845 (radio->version == 0x2050) &&
846 (radio->revision == 3 ||
847 radio->revision == 4 ||
848 radio->revision == 5)) {
849 bcm43xx_radio_write16(bcm, 0x0051, 0x001F);
850 bcm43xx_radio_write16(bcm, 0x0052, 0x0040);
851 bcm43xx_radio_write16(bcm, 0x0053, 0x005B);
852 bcm43xx_radio_write16(bcm, 0x0054, 0x0098);
853 bcm43xx_radio_write16(bcm, 0x005A, 0x0088);
854 bcm43xx_radio_write16(bcm, 0x005B, 0x0088);
855 bcm43xx_radio_write16(bcm, 0x005D, 0x0088);
856 bcm43xx_radio_write16(bcm, 0x005E, 0x0088);
857 bcm43xx_radio_write16(bcm, 0x007D, 0x0088);
859 if ((radio->manufact == 0x17F) &&
860 (radio->version == 0x2050) &&
861 (radio->revision == 6)) {
862 bcm43xx_radio_write16(bcm, 0x0051, 0x0000);
863 bcm43xx_radio_write16(bcm, 0x0052, 0x0040);
864 bcm43xx_radio_write16(bcm, 0x0053, 0x00B7);
865 bcm43xx_radio_write16(bcm, 0x0054, 0x0098);
866 bcm43xx_radio_write16(bcm, 0x005A, 0x0088);
867 bcm43xx_radio_write16(bcm, 0x005B, 0x008B);
868 bcm43xx_radio_write16(bcm, 0x005C, 0x00B5);
869 bcm43xx_radio_write16(bcm, 0x005D, 0x0088);
870 bcm43xx_radio_write16(bcm, 0x005E, 0x0088);
871 bcm43xx_radio_write16(bcm, 0x007D, 0x0088);
872 bcm43xx_radio_write16(bcm, 0x007C, 0x0001);
873 bcm43xx_radio_write16(bcm, 0x007E, 0x0008);
875 if ((radio->manufact == 0x17F) &&
876 (radio->version == 0x2050) &&
877 (radio->revision == 7)) {
878 bcm43xx_radio_write16(bcm, 0x0051, 0x0000);
879 bcm43xx_radio_write16(bcm, 0x0052, 0x0040);
880 bcm43xx_radio_write16(bcm, 0x0053, 0x00B7);
881 bcm43xx_radio_write16(bcm, 0x0054, 0x0098);
882 bcm43xx_radio_write16(bcm, 0x005A, 0x0088);
883 bcm43xx_radio_write16(bcm, 0x005B, 0x00A8);
884 bcm43xx_radio_write16(bcm, 0x005C, 0x0075);
885 bcm43xx_radio_write16(bcm, 0x005D, 0x00F5);
886 bcm43xx_radio_write16(bcm, 0x005E, 0x00B8);
887 bcm43xx_radio_write16(bcm, 0x007D, 0x00E8);
888 bcm43xx_radio_write16(bcm, 0x007C, 0x0001);
889 bcm43xx_radio_write16(bcm, 0x007E, 0x0008);
890 bcm43xx_radio_write16(bcm, 0x007B, 0x0000);
892 if ((radio->manufact == 0x17F) &&
893 (radio->version == 0x2050) &&
894 (radio->revision == 8)) {
895 bcm43xx_radio_write16(bcm, 0x0051, 0x0000);
896 bcm43xx_radio_write16(bcm, 0x0052, 0x0040);
897 bcm43xx_radio_write16(bcm, 0x0053, 0x00B7);
898 bcm43xx_radio_write16(bcm, 0x0054, 0x0098);
899 bcm43xx_radio_write16(bcm, 0x005A, 0x0088);
900 bcm43xx_radio_write16(bcm, 0x005B, 0x006B);
901 bcm43xx_radio_write16(bcm, 0x005C, 0x000F);
902 if (bcm->sprom.boardflags & 0x8000) {
903 bcm43xx_radio_write16(bcm, 0x005D, 0x00FA);
904 bcm43xx_radio_write16(bcm, 0x005E, 0x00D8);
906 bcm43xx_radio_write16(bcm, 0x005D, 0x00F5);
907 bcm43xx_radio_write16(bcm, 0x005E, 0x00B8);
909 bcm43xx_radio_write16(bcm, 0x0073, 0x0003);
910 bcm43xx_radio_write16(bcm, 0x007D, 0x00A8);
911 bcm43xx_radio_write16(bcm, 0x007C, 0x0001);
912 bcm43xx_radio_write16(bcm, 0x007E, 0x0008);
915 for (offset = 0x0088; offset < 0x0098; offset++) {
916 bcm43xx_phy_write(bcm, offset, val);
920 for (offset = 0x0098; offset < 0x00A8; offset++) {
921 bcm43xx_phy_write(bcm, offset, val);
925 for (offset = 0x00A8; offset < 0x00C8; offset++) {
926 bcm43xx_phy_write(bcm, offset, (val & 0x3F3F));
929 if (phy->type == BCM43xx_PHYTYPE_G) {
930 bcm43xx_radio_write16(bcm, 0x007A,
931 bcm43xx_radio_read16(bcm, 0x007A) | 0x0020);
932 bcm43xx_radio_write16(bcm, 0x0051,
933 bcm43xx_radio_read16(bcm, 0x0051) | 0x0004);
934 bcm43xx_phy_write(bcm, 0x0802,
935 bcm43xx_phy_read(bcm, 0x0802) | 0x0100);
936 bcm43xx_phy_write(bcm, 0x042B,
937 bcm43xx_phy_read(bcm, 0x042B) | 0x2000);
940 /* Force to channel 7, even if not supported. */
941 bcm43xx_radio_selectchannel(bcm, 7, 0);
943 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
944 bcm43xx_radio_write16(bcm, 0x0050, 0x0023);
946 bcm43xx_radio_write16(bcm, 0x007C, (bcm43xx_radio_read16(bcm, 0x007C) | 0x0002));
947 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
948 if ((bcm->current_core->radio->manufact == 0x17F) &&
949 (bcm->current_core->radio->version == 0x2050) &&
950 (bcm->current_core->radio->revision <= 2)) {
951 bcm43xx_radio_write16(bcm, 0x0050, 0x0020);
952 bcm43xx_radio_write16(bcm, 0x005A, 0x0070);
953 bcm43xx_radio_write16(bcm, 0x005B, 0x007B);
954 bcm43xx_radio_write16(bcm, 0x005C, 0x00B0);
956 bcm43xx_radio_write16(bcm, 0x007A,
957 (bcm43xx_radio_read16(bcm, 0x007A) & 0x00F8) | 0x0007);
959 bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_BG, 0);
961 bcm43xx_phy_write(bcm, 0x0014, 0x0200);
962 if (radio->version == 0x2050){
963 if (radio->revision == 3 ||
964 radio->revision == 4 ||
965 radio->revision == 5)
966 bcm43xx_phy_write(bcm, 0x002A, 0x8AC0);
968 bcm43xx_phy_write(bcm, 0x002A, 0x88C2);
970 bcm43xx_phy_write(bcm, 0x0038, 0x0668);
971 bcm43xx_radio_set_txpower_bg(bcm, 0xFFFF, 0xFFFF, 0xFFFF);
972 if (radio->version == 0x2050) {
973 if (radio->revision == 3 ||
974 radio->revision == 4 ||
975 radio->revision == 5)
976 bcm43xx_phy_write(bcm, 0x005D, bcm43xx_phy_read(bcm, 0x005D) | 0x0003);
977 else if (radio->revision <= 2)
978 bcm43xx_radio_write16(bcm, 0x005D, 0x000D);
982 bcm43xx_phy_write(bcm, 0x0002, (bcm43xx_phy_read(bcm, 0x0002) & 0xFFC0) | 0x0004);
984 bcm43xx_write16(bcm, 0x03E4, 0x0009);
985 if (phy->type == BCM43xx_PHYTYPE_B) {
986 bcm43xx_write16(bcm, 0x03E6, 0x8140);
987 bcm43xx_phy_write(bcm, 0x0016, 0x0410);
988 bcm43xx_phy_write(bcm, 0x0017, 0x0820);
989 bcm43xx_phy_write(bcm, 0x0062, 0x0007);
990 (void) bcm43xx_radio_calibrationvalue(bcm);
991 bcm43xx_phy_lo_b_measure(bcm);
992 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
993 bcm43xx_calc_nrssi_slope(bcm);
994 bcm43xx_calc_nrssi_threshold(bcm);
996 bcm43xx_phy_init_pctl(bcm);
998 bcm43xx_write16(bcm, 0x03E6, 0x0);
1001 static void bcm43xx_phy_initg(struct bcm43xx_private *bcm)
1003 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1004 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
1008 bcm43xx_phy_initb5(bcm);
1009 else if (phy->rev >= 2 && phy->rev <= 7)
1010 bcm43xx_phy_initb6(bcm);
1011 if (phy->rev >= 2 || phy->connected)
1012 bcm43xx_phy_inita(bcm);
1014 if (phy->rev >= 2) {
1015 bcm43xx_phy_write(bcm, 0x0814, 0x0000);
1016 bcm43xx_phy_write(bcm, 0x0815, 0x0000);
1018 bcm43xx_phy_write(bcm, 0x0811, 0x0000);
1019 else if (phy->rev >= 3)
1020 bcm43xx_phy_write(bcm, 0x0811, 0x0400);
1021 bcm43xx_phy_write(bcm, 0x0015, 0x00C0);
1022 tmp = bcm43xx_phy_read(bcm, 0x0400) & 0xFF;
1024 bcm43xx_phy_write(bcm, 0x04C2, 0x1816);
1025 bcm43xx_phy_write(bcm, 0x04C3, 0x8606);
1026 } else if (tmp == 4 || tmp == 5) {
1027 bcm43xx_phy_write(bcm, 0x04C2, 0x1816);
1028 bcm43xx_phy_write(bcm, 0x04C3, 0x8006);
1029 bcm43xx_phy_write(bcm, 0x04CC, (bcm43xx_phy_read(bcm, 0x04CC)
1030 & 0x00FF) | 0x1F00);
1033 if (radio->revision <= 3 && phy->connected)
1034 bcm43xx_phy_write(bcm, 0x047E, 0x0078);
1035 if (radio->revision >= 6 && radio->revision <= 8) {
1036 bcm43xx_phy_write(bcm, 0x0801, bcm43xx_phy_read(bcm, 0x0801) | 0x0080);
1037 bcm43xx_phy_write(bcm, 0x043E, bcm43xx_phy_read(bcm, 0x043E) | 0x0004);
1039 if (radio->initval == 0xFFFF) {
1040 radio->initval = bcm43xx_radio_init2050(bcm);
1041 bcm43xx_phy_lo_g_measure(bcm);
1043 bcm43xx_radio_write16(bcm, 0x0078, radio->initval);
1044 bcm43xx_radio_write16(bcm, 0x0052,
1045 (bcm43xx_radio_read16(bcm, 0x0052) & 0xFFF0)
1046 | radio->txpower[3]);
1049 if (phy->connected) {
1050 bcm43xx_phy_lo_adjust(bcm, 0);
1051 bcm43xx_phy_write(bcm, 0x080F, 0x8078);
1053 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
1054 bcm43xx_phy_write(bcm, 0x002E, 0x807F);
1056 bcm43xx_phy_write(bcm, 0x002E, 0x8075);
1059 bcm43xx_phy_write(bcm, 0x002F, 0x0101);
1061 bcm43xx_phy_write(bcm, 0x002F, 0x0202);
1064 if ((bcm->sprom.boardflags & BCM43xx_BFL_RSSI) == 0) {
1065 FIXME();//FIXME: 0x7FFFFFFF should be 16-bit !
1066 bcm43xx_nrssi_hw_update(bcm, (u16)0x7FFFFFFF);
1067 bcm43xx_calc_nrssi_threshold(bcm);
1068 } else if (phy->connected) {
1069 if (radio->nrssi[0] == -1000) {
1070 assert(radio->nrssi[1] == -1000);
1071 bcm43xx_calc_nrssi_slope(bcm);
1073 bcm43xx_calc_nrssi_threshold(bcm);
1075 bcm43xx_phy_init_pctl(bcm);
1078 static u16 bcm43xx_phy_lo_b_r15_loop(struct bcm43xx_private *bcm)
1083 for (i = 0; i < 10; i++){
1084 bcm43xx_phy_write(bcm, 0x0015, 0xAFA0);
1086 bcm43xx_phy_write(bcm, 0x0015, 0xEFA0);
1088 bcm43xx_phy_write(bcm, 0x0015, 0xFFA0);
1090 ret += bcm43xx_phy_read(bcm, 0x002C);
1096 void bcm43xx_phy_lo_b_measure(struct bcm43xx_private *bcm)
1098 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
1099 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1100 u16 regstack[12] = { 0 };
1105 regstack[0] = bcm43xx_phy_read(bcm, 0x0015);
1106 regstack[1] = bcm43xx_radio_read16(bcm, 0x0052) & 0xFFF0;
1108 if (radio->version == 0x2053) {
1109 regstack[2] = bcm43xx_phy_read(bcm, 0x000A);
1110 regstack[3] = bcm43xx_phy_read(bcm, 0x002A);
1111 regstack[4] = bcm43xx_phy_read(bcm, 0x0035);
1112 regstack[5] = bcm43xx_phy_read(bcm, 0x0003);
1113 regstack[6] = bcm43xx_phy_read(bcm, 0x0001);
1114 regstack[7] = bcm43xx_phy_read(bcm, 0x0030);
1116 regstack[8] = bcm43xx_radio_read16(bcm, 0x0043);
1117 regstack[9] = bcm43xx_radio_read16(bcm, 0x007A);
1118 regstack[10] = bcm43xx_read16(bcm, 0x03EC);
1119 regstack[11] = bcm43xx_radio_read16(bcm, 0x0052) & 0x00F0;
1121 bcm43xx_phy_write(bcm, 0x0030, 0x00FF);
1122 bcm43xx_write16(bcm, 0x03EC, 0x3F3F);
1123 bcm43xx_phy_write(bcm, 0x0035, regstack[4] & 0xFF7F);
1124 bcm43xx_radio_write16(bcm, 0x007A, regstack[9] & 0xFFF0);
1126 bcm43xx_phy_write(bcm, 0x0015, 0xB000);
1127 bcm43xx_phy_write(bcm, 0x002B, 0x0004);
1129 if (radio->version == 0x2053) {
1130 bcm43xx_phy_write(bcm, 0x002B, 0x0203);
1131 bcm43xx_phy_write(bcm, 0x002A, 0x08A3);
1134 phy->minlowsig[0] = 0xFFFF;
1136 for (i = 0; i < 4; i++) {
1137 bcm43xx_radio_write16(bcm, 0x0052, regstack[1] | i);
1138 bcm43xx_phy_lo_b_r15_loop(bcm);
1140 for (i = 0; i < 10; i++) {
1141 bcm43xx_radio_write16(bcm, 0x0052, regstack[1] | i);
1142 mls = bcm43xx_phy_lo_b_r15_loop(bcm) / 10;
1143 if (mls < phy->minlowsig[0]) {
1144 phy->minlowsig[0] = mls;
1145 phy->minlowsigpos[0] = i;
1148 bcm43xx_radio_write16(bcm, 0x0052, regstack[1] | phy->minlowsigpos[0]);
1150 phy->minlowsig[1] = 0xFFFF;
1152 for (i = -4; i < 5; i += 2) {
1153 for (j = -4; j < 5; j += 2) {
1155 fval = (0x0100 * i) + j + 0x0100;
1157 fval = (0x0100 * i) + j;
1158 bcm43xx_phy_write(bcm, 0x002F, fval);
1159 mls = bcm43xx_phy_lo_b_r15_loop(bcm) / 10;
1160 if (mls < phy->minlowsig[1]) {
1161 phy->minlowsig[1] = mls;
1162 phy->minlowsigpos[1] = fval;
1166 phy->minlowsigpos[1] += 0x0101;
1168 bcm43xx_phy_write(bcm, 0x002F, phy->minlowsigpos[1]);
1169 if (radio->version == 0x2053) {
1170 bcm43xx_phy_write(bcm, 0x000A, regstack[2]);
1171 bcm43xx_phy_write(bcm, 0x002A, regstack[3]);
1172 bcm43xx_phy_write(bcm, 0x0035, regstack[4]);
1173 bcm43xx_phy_write(bcm, 0x0003, regstack[5]);
1174 bcm43xx_phy_write(bcm, 0x0001, regstack[6]);
1175 bcm43xx_phy_write(bcm, 0x0030, regstack[7]);
1177 bcm43xx_radio_write16(bcm, 0x0043, regstack[8]);
1178 bcm43xx_radio_write16(bcm, 0x007A, regstack[9]);
1180 bcm43xx_radio_write16(bcm, 0x0052,
1181 (bcm43xx_radio_read16(bcm, 0x0052) & 0x000F)
1184 bcm43xx_write16(bcm, 0x03EC, regstack[10]);
1186 bcm43xx_phy_write(bcm, 0x0015, regstack[0]);
1190 u16 bcm43xx_phy_lo_g_deviation_subval(struct bcm43xx_private *bcm, u16 control)
1192 if (bcm->current_core->phy->connected) {
1193 bcm43xx_phy_write(bcm, 0x15, 0xE300);
1195 bcm43xx_phy_write(bcm, 0x0812, control | 0x00B0);
1197 bcm43xx_phy_write(bcm, 0x0812, control | 0x00B2);
1199 bcm43xx_phy_write(bcm, 0x0812, control | 0x00B3);
1201 bcm43xx_phy_write(bcm, 0x0015, 0xF300);
1204 bcm43xx_phy_write(bcm, 0x0015, control | 0xEFA0);
1206 bcm43xx_phy_write(bcm, 0x0015, control | 0xEFE0);
1208 bcm43xx_phy_write(bcm, 0x0015, control | 0xFFE0);
1212 return bcm43xx_phy_read(bcm, 0x002D);
1215 static u32 bcm43xx_phy_lo_g_singledeviation(struct bcm43xx_private *bcm, u16 control)
1220 for (i = 0; i < 8; i++)
1221 ret += bcm43xx_phy_lo_g_deviation_subval(bcm, control);
1226 /* Write the LocalOscillator CONTROL */
1228 void bcm43xx_lo_write(struct bcm43xx_private *bcm,
1229 struct bcm43xx_lopair *pair)
1233 value = (u8)(pair->low);
1234 value |= ((u8)(pair->high)) << 8;
1236 #ifdef CONFIG_BCM43XX_DEBUG
1238 if (pair->low < -8 || pair->low > 8 ||
1239 pair->high < -8 || pair->high > 8) {
1240 printk(KERN_WARNING PFX
1241 "WARNING: Writing invalid LOpair "
1242 "(low: %d, high: %d, index: %lu)\n",
1243 pair->low, pair->high,
1244 (unsigned long)(pair - bcm->current_core->phy->_lo_pairs));
1249 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_LO_CONTROL, value);
1253 struct bcm43xx_lopair * bcm43xx_find_lopair(struct bcm43xx_private *bcm,
1254 u16 baseband_attenuation,
1255 u16 radio_attenuation,
1258 static const u8 dict[10] = { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
1259 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1261 if (baseband_attenuation > 6)
1262 baseband_attenuation = 6;
1263 assert(radio_attenuation < 10);
1264 assert(tx == 0 || tx == 3);
1267 return bcm43xx_get_lopair(phy,
1269 baseband_attenuation);
1271 return bcm43xx_get_lopair(phy, dict[radio_attenuation], baseband_attenuation);
1275 struct bcm43xx_lopair * bcm43xx_current_lopair(struct bcm43xx_private *bcm)
1277 return bcm43xx_find_lopair(bcm,
1278 bcm->current_core->radio->txpower[0],
1279 bcm->current_core->radio->txpower[1],
1280 bcm->current_core->radio->txpower[2]);
1284 void bcm43xx_phy_lo_adjust(struct bcm43xx_private *bcm, int fixed)
1286 struct bcm43xx_lopair *pair;
1289 /* Use fixed values. Only for initialization. */
1290 pair = bcm43xx_find_lopair(bcm, 2, 3, 0);
1292 pair = bcm43xx_current_lopair(bcm);
1293 bcm43xx_lo_write(bcm, pair);
1297 void bcm43xx_phy_lo_g_measure_txctl2(struct bcm43xx_private *bcm)
1302 bcm43xx_radio_write16(bcm, 0x0052, 0x0000);
1304 smallest = bcm43xx_phy_lo_g_singledeviation(bcm, 0);
1305 for (i = 0; i < 16; i++) {
1306 bcm43xx_radio_write16(bcm, 0x0052, i);
1308 tmp = bcm43xx_phy_lo_g_singledeviation(bcm, 0);
1309 if (tmp < smallest) {
1314 bcm->current_core->radio->txpower[3] = txctl2;
1318 void bcm43xx_phy_lo_g_state(struct bcm43xx_private *bcm,
1319 const struct bcm43xx_lopair *in_pair,
1320 struct bcm43xx_lopair *out_pair,
1323 static const struct bcm43xx_lopair transitions[8] = {
1324 { .high = 1, .low = 1, },
1325 { .high = 1, .low = 0, },
1326 { .high = 1, .low = -1, },
1327 { .high = 0, .low = -1, },
1328 { .high = -1, .low = -1, },
1329 { .high = -1, .low = 0, },
1330 { .high = -1, .low = 1, },
1331 { .high = 0, .low = 1, },
1333 struct bcm43xx_lopair lowest_transition = {
1334 .high = in_pair->high,
1335 .low = in_pair->low,
1337 struct bcm43xx_lopair tmp_pair;
1338 struct bcm43xx_lopair transition;
1343 u32 lowest_deviation;
1346 /* Note that in_pair and out_pair can point to the same pair. Be careful. */
1348 bcm43xx_lo_write(bcm, &lowest_transition);
1349 lowest_deviation = bcm43xx_phy_lo_g_singledeviation(bcm, r27);
1352 assert(state >= 0 && state <= 8);
1356 } else if (state % 2 == 0) {
1369 tmp_pair.high = lowest_transition.high;
1370 tmp_pair.low = lowest_transition.low;
1372 assert(j >= 1 && j <= 8);
1373 transition.high = tmp_pair.high + transitions[j - 1].high;
1374 transition.low = tmp_pair.low + transitions[j - 1].low;
1375 if ((abs(transition.low) < 9) && (abs(transition.high) < 9)) {
1376 bcm43xx_lo_write(bcm, &transition);
1377 tmp = bcm43xx_phy_lo_g_singledeviation(bcm, r27);
1378 if (tmp < lowest_deviation) {
1379 lowest_deviation = tmp;
1383 lowest_transition.high = transition.high;
1384 lowest_transition.low = transition.low;
1394 } while (i-- && found_lower);
1396 out_pair->high = lowest_transition.high;
1397 out_pair->low = lowest_transition.low;
1400 /* Set the baseband attenuation value on chip. */
1401 void bcm43xx_phy_set_baseband_attenuation(struct bcm43xx_private *bcm,
1402 u16 baseband_attenuation)
1406 if (bcm->current_core->phy->version == 0) {
1407 value = (bcm43xx_read16(bcm, 0x03E6) & 0xFFF0);
1408 value |= (baseband_attenuation & 0x000F);
1409 bcm43xx_write16(bcm, 0x03E6, value);
1413 if (bcm->current_core->phy->version > 1) {
1414 value = bcm43xx_phy_read(bcm, 0x0060) & ~0x003C;
1415 value |= (baseband_attenuation << 2) & 0x003C;
1417 value = bcm43xx_phy_read(bcm, 0x0060) & ~0x0078;
1418 value |= (baseband_attenuation << 3) & 0x0078;
1420 bcm43xx_phy_write(bcm, 0x0060, value);
1423 /* http://bcm-specs.sipsolutions.net/LocalOscillator/Measure */
1424 void bcm43xx_phy_lo_g_measure(struct bcm43xx_private *bcm)
1426 static const u8 pairorder[10] = { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8 };
1427 const int is_initializing = bcm43xx_is_initializing(bcm);
1428 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1429 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
1430 u16 h, i, oldi = 0, j;
1431 struct bcm43xx_lopair control;
1432 struct bcm43xx_lopair *tmp_control;
1434 u16 regstack[16] = { 0 };
1437 //XXX: What are these?
1440 oldchannel = radio->channel;
1442 if (phy->connected) {
1443 regstack[0] = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS);
1444 regstack[1] = bcm43xx_phy_read(bcm, 0x0802);
1445 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS, regstack[0] & 0x7FFF);
1446 bcm43xx_phy_write(bcm, 0x0802, regstack[1] & 0xFFFC);
1448 regstack[3] = bcm43xx_read16(bcm, 0x03E2);
1449 bcm43xx_write16(bcm, 0x03E2, regstack[3] | 0x8000);
1450 regstack[4] = bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT);
1451 regstack[5] = bcm43xx_phy_read(bcm, 0x15);
1452 regstack[6] = bcm43xx_phy_read(bcm, 0x2A);
1453 regstack[7] = bcm43xx_phy_read(bcm, 0x35);
1454 regstack[8] = bcm43xx_phy_read(bcm, 0x60);
1455 regstack[9] = bcm43xx_radio_read16(bcm, 0x43);
1456 regstack[10] = bcm43xx_radio_read16(bcm, 0x7A);
1457 regstack[11] = bcm43xx_radio_read16(bcm, 0x52);
1458 if (phy->connected) {
1459 regstack[12] = bcm43xx_phy_read(bcm, 0x0811);
1460 regstack[13] = bcm43xx_phy_read(bcm, 0x0812);
1461 regstack[14] = bcm43xx_phy_read(bcm, 0x0814);
1462 regstack[15] = bcm43xx_phy_read(bcm, 0x0815);
1464 bcm43xx_radio_selectchannel(bcm, 6, 0);
1465 if (phy->connected) {
1466 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS, regstack[0] & 0x7FFF);
1467 bcm43xx_phy_write(bcm, 0x0802, regstack[1] & 0xFFFC);
1468 bcm43xx_dummy_transmission(bcm);
1470 bcm43xx_radio_write16(bcm, 0x0043, 0x0006);
1472 bcm43xx_phy_set_baseband_attenuation(bcm, 2);
1474 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, 0x0000);
1475 bcm43xx_phy_write(bcm, 0x002E, 0x007F);
1476 bcm43xx_phy_write(bcm, 0x080F, 0x0078);
1477 bcm43xx_phy_write(bcm, 0x0035, regstack[7] & ~(1 << 7));
1478 bcm43xx_radio_write16(bcm, 0x007A, regstack[10] & 0xFFF0);
1479 bcm43xx_phy_write(bcm, 0x002B, 0x0203);
1480 bcm43xx_phy_write(bcm, 0x002A, 0x08A3);
1481 if (phy->connected) {
1482 bcm43xx_phy_write(bcm, 0x0814, regstack[14] | 0x0003);
1483 bcm43xx_phy_write(bcm, 0x0815, regstack[15] & 0xFFFC);
1484 bcm43xx_phy_write(bcm, 0x0811, 0x01B3);
1485 bcm43xx_phy_write(bcm, 0x0812, 0x00B2);
1487 if (is_initializing)
1488 bcm43xx_phy_lo_g_measure_txctl2(bcm);
1489 bcm43xx_phy_write(bcm, 0x080F, 0x8078);
1494 for (h = 0; h < 10; h++) {
1495 /* Loop over each possible RadioAttenuation (0-9) */
1497 if (is_initializing) {
1501 } else if (((i % 2 == 1) && (oldi % 2 == 1)) ||
1502 ((i % 2 == 0) && (oldi % 2 == 0))) {
1503 tmp_control = bcm43xx_get_lopair(phy, oldi, 0);
1504 memcpy(&control, tmp_control, sizeof(control));
1506 tmp_control = bcm43xx_get_lopair(phy, 3, 0);
1507 memcpy(&control, tmp_control, sizeof(control));
1510 /* Loop over each possible BasebandAttenuation/2 */
1511 for (j = 0; j < 4; j++) {
1512 if (is_initializing) {
1524 tmp_control = bcm43xx_get_lopair(phy, i, j * 2);
1525 if (!tmp_control->used)
1527 memcpy(&control, tmp_control, sizeof(control));
1531 bcm43xx_radio_write16(bcm, 0x43, i);
1532 bcm43xx_radio_write16(bcm, 0x52,
1536 bcm43xx_phy_set_baseband_attenuation(bcm, j * 2);
1538 tmp = (regstack[10] & 0xFFF0);
1541 bcm43xx_radio_write16(bcm, 0x007A, tmp);
1543 tmp_control = bcm43xx_get_lopair(phy, i, j * 2);
1544 bcm43xx_phy_lo_g_state(bcm, &control, tmp_control, r27);
1548 /* Loop over each possible RadioAttenuation (10-13) */
1549 for (i = 10; i < 14; i++) {
1550 /* Loop over each possible BasebandAttenuation/2 */
1551 for (j = 0; j < 4; j++) {
1552 if (is_initializing) {
1553 tmp_control = bcm43xx_get_lopair(phy, i - 9, j * 2);
1554 memcpy(&control, tmp_control, sizeof(control));
1555 tmp = (i - 9) * 2 + j - 5;//FIXME: This is wrong, as the following if statement can never trigger.
1566 tmp_control = bcm43xx_get_lopair(phy, i - 9, j * 2);
1567 if (!tmp_control->used)
1569 memcpy(&control, tmp_control, sizeof(control));
1573 bcm43xx_radio_write16(bcm, 0x43, i - 9);
1574 bcm43xx_radio_write16(bcm, 0x52,
1576 | (3/*txctl1*/ << 4));//FIXME: shouldn't txctl1 be zero here and 3 in the loop above?
1579 bcm43xx_phy_set_baseband_attenuation(bcm, j * 2);
1581 tmp = (regstack[10] & 0xFFF0);
1584 bcm43xx_radio_write16(bcm, 0x7A, tmp);
1586 tmp_control = bcm43xx_get_lopair(phy, i, j * 2);
1587 bcm43xx_phy_lo_g_state(bcm, &control, tmp_control, r27);
1592 if (phy->connected) {
1593 bcm43xx_phy_write(bcm, 0x0015, 0xE300);
1594 bcm43xx_phy_write(bcm, 0x0812, (r27 << 8) | 0xA0);
1596 bcm43xx_phy_write(bcm, 0x0812, (r27 << 8) | 0xA2);
1598 bcm43xx_phy_write(bcm, 0x0812, (r27 << 8) | 0xA3);
1600 bcm43xx_phy_write(bcm, 0x0015, r27 | 0xEFA0);
1601 bcm43xx_phy_lo_adjust(bcm, is_initializing);
1602 bcm43xx_phy_write(bcm, 0x002E, 0x807F);
1604 bcm43xx_phy_write(bcm, 0x002F, 0x0202);
1606 bcm43xx_phy_write(bcm, 0x002F, 0x0101);
1607 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, regstack[4]);
1608 bcm43xx_phy_write(bcm, 0x0015, regstack[5]);
1609 bcm43xx_phy_write(bcm, 0x002A, regstack[6]);
1610 bcm43xx_phy_write(bcm, 0x0035, regstack[7]);
1611 bcm43xx_phy_write(bcm, 0x0060, regstack[8]);
1612 bcm43xx_radio_write16(bcm, 0x0043, regstack[9]);
1613 bcm43xx_radio_write16(bcm, 0x007A, regstack[10]);
1614 regstack[11] &= 0x00F0;
1615 regstack[11] |= (bcm43xx_radio_read16(bcm, 0x52) & 0x000F);
1616 bcm43xx_radio_write16(bcm, 0x52, regstack[11]);
1617 bcm43xx_write16(bcm, 0x03E2, regstack[3]);
1618 if (phy->connected) {
1619 bcm43xx_phy_write(bcm, 0x0811, regstack[12]);
1620 bcm43xx_phy_write(bcm, 0x0812, regstack[13]);
1621 bcm43xx_phy_write(bcm, 0x0814, regstack[14]);
1622 bcm43xx_phy_write(bcm, 0x0815, regstack[15]);
1623 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS, regstack[0]);
1624 bcm43xx_phy_write(bcm, 0x0802, regstack[1]);
1626 bcm43xx_radio_selectchannel(bcm, oldchannel, 1);
1628 #ifdef CONFIG_BCM43XX_DEBUG
1630 /* Sanity check for all lopairs. */
1631 for (i = 0; i < BCM43xx_LO_COUNT; i++) {
1632 tmp_control = phy->_lo_pairs + i;
1633 if (tmp_control->low < -8 || tmp_control->low > 8 ||
1634 tmp_control->high < -8 || tmp_control->high > 8) {
1635 printk(KERN_WARNING PFX
1636 "WARNING: Invalid LOpair (low: %d, high: %d, index: %d)\n",
1637 tmp_control->low, tmp_control->high, i);
1641 #endif /* CONFIG_BCM43XX_DEBUG */
1645 void bcm43xx_phy_lo_mark_current_used(struct bcm43xx_private *bcm)
1647 struct bcm43xx_lopair *pair;
1649 pair = bcm43xx_current_lopair(bcm);
1653 void bcm43xx_phy_lo_mark_all_unused(struct bcm43xx_private *bcm)
1655 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1656 struct bcm43xx_lopair *pair;
1659 for (i = 0; i < BCM43xx_LO_COUNT; i++) {
1660 pair = phy->_lo_pairs + i;
1665 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1666 * This function converts a TSSI value to dBm in Q5.2
1668 static s8 bcm43xx_phy_estimate_power_out(struct bcm43xx_private *bcm, s8 tssi)
1670 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1674 tmp = phy->idle_tssi;
1676 tmp -= phy->savedpctlreg;
1678 switch (phy->type) {
1679 case BCM43xx_PHYTYPE_A:
1681 tmp = limit_value(tmp, 0x00, 0xFF);
1682 dbm = phy->tssi2dbm[tmp];
1683 TODO(); //TODO: There's a FIXME on the specs
1685 case BCM43xx_PHYTYPE_B:
1686 case BCM43xx_PHYTYPE_G:
1687 tmp = limit_value(tmp, 0x00, 0x3F);
1688 dbm = phy->tssi2dbm[tmp];
1697 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1698 void bcm43xx_phy_xmitpower(struct bcm43xx_private *bcm)
1700 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
1701 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1703 if (phy->savedpctlreg == 0xFFFF)
1705 if ((bcm->board_type == 0x0416) &&
1706 (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM))
1709 switch (phy->type) {
1710 case BCM43xx_PHYTYPE_A: {
1712 TODO(); //TODO: Nothing for A PHYs yet :-/
1716 case BCM43xx_PHYTYPE_B:
1717 case BCM43xx_PHYTYPE_G: {
1723 s16 desired_pwr, estimated_pwr, pwr_adjust;
1724 s16 radio_att_delta, baseband_att_delta;
1725 s16 radio_attenuation, baseband_attenuation;
1726 unsigned long phylock_flags;
1728 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0058);
1729 v0 = (s8)(tmp & 0x00FF);
1730 v1 = (s8)((tmp & 0xFF00) >> 8);
1731 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x005A);
1732 v2 = (s8)(tmp & 0x00FF);
1733 v3 = (s8)((tmp & 0xFF00) >> 8);
1736 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) {
1737 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0070);
1738 v0 = (s8)(tmp & 0x00FF);
1739 v1 = (s8)((tmp & 0xFF00) >> 8);
1740 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0072);
1741 v2 = (s8)(tmp & 0x00FF);
1742 v3 = (s8)((tmp & 0xFF00) >> 8);
1743 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F)
1745 v0 = (v0 + 0x20) & 0x3F;
1746 v1 = (v1 + 0x20) & 0x3F;
1747 v2 = (v2 + 0x20) & 0x3F;
1748 v3 = (v3 + 0x20) & 0x3F;
1751 bcm43xx_radio_clear_tssi(bcm);
1753 average = (v0 + v1 + v2 + v3 + 2) / 4;
1755 if (tmp && (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x005E) & 0x8))
1758 estimated_pwr = bcm43xx_phy_estimate_power_out(bcm, average);
1760 max_pwr = bcm->sprom.maxpower_bgphy;
1762 if ((bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) &&
1763 (phy->type == BCM43xx_PHYTYPE_G))
1767 max_pwr = min(REG - bcm->sprom.antennagain_bgphy - 0x6, max_pwr)
1768 where REG is the max power as per the regulatory domain
1771 desired_pwr = limit_value(radio->txpower_desired, 0, max_pwr);
1772 /* Check if we need to adjust the current power. */
1773 pwr_adjust = desired_pwr - estimated_pwr;
1774 radio_att_delta = -(pwr_adjust + 7) >> 3;
1775 baseband_att_delta = -(pwr_adjust >> 1) - (4 * radio_att_delta);
1776 if ((radio_att_delta == 0) && (baseband_att_delta == 0)) {
1777 bcm43xx_phy_lo_mark_current_used(bcm);
1781 /* Calculate the new attenuation values. */
1782 baseband_attenuation = radio->txpower[0];
1783 baseband_attenuation += baseband_att_delta;
1784 radio_attenuation = radio->txpower[1];
1785 radio_attenuation += radio_att_delta;
1787 /* Get baseband and radio attenuation values into their permitted ranges.
1788 * baseband 0-11, radio 0-9.
1789 * Radio attenuation affects power level 4 times as much as baseband.
1791 if (radio_attenuation < 0) {
1792 baseband_attenuation -= (4 * -radio_attenuation);
1793 radio_attenuation = 0;
1794 } else if (radio_attenuation > 9) {
1795 baseband_attenuation += (4 * (radio_attenuation - 9));
1796 radio_attenuation = 9;
1798 while (baseband_attenuation < 0 && radio_attenuation > 0) {
1799 baseband_attenuation += 4;
1800 radio_attenuation--;
1802 while (baseband_attenuation > 11 && radio_attenuation < 9) {
1803 baseband_attenuation -= 4;
1804 radio_attenuation++;
1807 baseband_attenuation = limit_value(baseband_attenuation, 0, 11);
1809 txpower = radio->txpower[2];
1810 if ((radio->version == 0x2050) && (radio->revision == 2)) {
1811 if (radio_attenuation <= 1) {
1814 radio_attenuation += 2;
1815 baseband_attenuation += 2;
1816 } else if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
1817 baseband_attenuation += 4 * (radio_attenuation - 2);
1818 radio_attenuation = 2;
1820 } else if (radio_attenuation > 4 && txpower != 0) {
1822 if (baseband_attenuation < 3) {
1823 radio_attenuation -= 3;
1824 baseband_attenuation += 2;
1826 radio_attenuation -= 2;
1827 baseband_attenuation -= 2;
1831 radio->txpower[2] = txpower;
1832 baseband_attenuation = limit_value(baseband_attenuation, 0, 11);
1833 radio_attenuation = limit_value(radio_attenuation, 0, 9);
1835 bcm43xx_phy_lock(bcm, phylock_flags);
1836 bcm43xx_radio_lock(bcm);
1837 bcm43xx_radio_set_txpower_bg(bcm, baseband_attenuation,
1838 radio_attenuation, txpower);
1839 bcm43xx_phy_lo_mark_current_used(bcm);
1840 bcm43xx_radio_unlock(bcm);
1841 bcm43xx_phy_unlock(bcm, phylock_flags);
1850 s32 bcm43xx_tssi2dbm_ad(s32 num, s32 den)
1855 return (num+den/2)/den;
1859 s8 bcm43xx_tssi2dbm_entry(s8 entry [], u8 index, s16 pab0, s16 pab1, s16 pab2)
1861 s32 m1, m2, f = 256, q, delta;
1864 m1 = bcm43xx_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
1865 m2 = max(bcm43xx_tssi2dbm_ad(32768 + index * pab2, 256), 1);
1869 q = bcm43xx_tssi2dbm_ad(f * 4096 -
1870 bcm43xx_tssi2dbm_ad(m2 * f, 16) * f, 2048);
1874 } while (delta >= 2);
1875 entry[index] = limit_value(bcm43xx_tssi2dbm_ad(m1 * f, 8192), -127, 128);
1879 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
1880 int bcm43xx_phy_init_tssi2dbm_table(struct bcm43xx_private *bcm)
1882 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1883 struct bcm43xx_radioinfo *radio = bcm->current_core->radio;
1884 s16 pab0, pab1, pab2;
1888 if (phy->type == BCM43xx_PHYTYPE_A) {
1889 pab0 = (s16)(bcm->sprom.pa1b0);
1890 pab1 = (s16)(bcm->sprom.pa1b1);
1891 pab2 = (s16)(bcm->sprom.pa1b2);
1893 pab0 = (s16)(bcm->sprom.pa0b0);
1894 pab1 = (s16)(bcm->sprom.pa0b1);
1895 pab2 = (s16)(bcm->sprom.pa0b2);
1898 if ((bcm->chip_id == 0x4301) && (radio->version != 0x2050)) {
1899 phy->idle_tssi = 0x34;
1900 phy->tssi2dbm = bcm43xx_tssi2dbm_b_table;
1904 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
1905 pab0 != -1 && pab1 != -1 && pab2 != -1) {
1906 /* The pabX values are set in SPROM. Use them. */
1907 if (phy->type == BCM43xx_PHYTYPE_A) {
1908 if ((s8)bcm->sprom.idle_tssi_tgt_aphy != 0 &&
1909 (s8)bcm->sprom.idle_tssi_tgt_aphy != -1)
1910 phy->idle_tssi = (s8)(bcm->sprom.idle_tssi_tgt_aphy);
1912 phy->idle_tssi = 62;
1914 if ((s8)bcm->sprom.idle_tssi_tgt_bgphy != 0 &&
1915 (s8)bcm->sprom.idle_tssi_tgt_bgphy != -1)
1916 phy->idle_tssi = (s8)(bcm->sprom.idle_tssi_tgt_bgphy);
1918 phy->idle_tssi = 62;
1920 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
1921 if (dyn_tssi2dbm == NULL) {
1922 printk(KERN_ERR PFX "Could not allocate memory"
1923 "for tssi2dbm table\n");
1926 for (idx = 0; idx < 64; idx++)
1927 if (bcm43xx_tssi2dbm_entry(dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
1928 phy->tssi2dbm = NULL;
1929 printk(KERN_ERR PFX "Could not generate "
1930 "tssi2dBm table\n");
1933 phy->tssi2dbm = dyn_tssi2dbm;
1934 phy->dyn_tssi_tbl = 1;
1936 /* pabX values not set in SPROM. */
1937 switch (phy->type) {
1938 case BCM43xx_PHYTYPE_A:
1939 /* APHY needs a generated table. */
1940 phy->tssi2dbm = NULL;
1941 printk(KERN_ERR PFX "Could not generate tssi2dBm "
1942 "table (wrong SPROM info)!\n");
1944 case BCM43xx_PHYTYPE_B:
1945 phy->idle_tssi = 0x34;
1946 phy->tssi2dbm = bcm43xx_tssi2dbm_b_table;
1948 case BCM43xx_PHYTYPE_G:
1949 phy->idle_tssi = 0x34;
1950 phy->tssi2dbm = bcm43xx_tssi2dbm_g_table;
1958 int bcm43xx_phy_init(struct bcm43xx_private *bcm)
1960 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
1962 unsigned long flags;
1964 /* We do not want to be preempted while calibrating
1967 local_irq_save(flags);
1969 switch (phy->type) {
1970 case BCM43xx_PHYTYPE_A:
1971 if (phy->rev == 2 || phy->rev == 3) {
1972 bcm43xx_phy_inita(bcm);
1976 case BCM43xx_PHYTYPE_B:
1979 bcm43xx_phy_initb2(bcm);
1983 bcm43xx_phy_initb4(bcm);
1987 bcm43xx_phy_initb5(bcm);
1991 bcm43xx_phy_initb6(bcm);
1996 case BCM43xx_PHYTYPE_G:
1997 bcm43xx_phy_initg(bcm);
2001 local_irq_restore(flags);
2003 printk(KERN_WARNING PFX "Unknown PHYTYPE found!\n");
2008 void bcm43xx_phy_set_antenna_diversity(struct bcm43xx_private *bcm)
2010 struct bcm43xx_phyinfo *phy = bcm->current_core->phy;
2016 antennadiv = phy->antenna_diversity;
2018 if (antennadiv == 0xFFFF)
2020 assert(antennadiv <= 3);
2022 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2023 BCM43xx_UCODEFLAGS_OFFSET);
2024 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2025 BCM43xx_UCODEFLAGS_OFFSET,
2026 ucodeflags & ~BCM43xx_UCODEFLAG_AUTODIV);
2028 switch (phy->type) {
2029 case BCM43xx_PHYTYPE_A:
2030 case BCM43xx_PHYTYPE_G:
2031 if (phy->type == BCM43xx_PHYTYPE_A)
2036 if (antennadiv == 2)
2037 value = (3/*automatic*/ << 7);
2039 value = (antennadiv << 7);
2040 bcm43xx_phy_write(bcm, offset + 1,
2041 (bcm43xx_phy_read(bcm, offset + 1)
2044 if (antennadiv >= 2) {
2045 if (antennadiv == 2)
2046 value = (antennadiv << 7);
2048 value = (0/*force0*/ << 7);
2049 bcm43xx_phy_write(bcm, offset + 0x2B,
2050 (bcm43xx_phy_read(bcm, offset + 0x2B)
2054 if (phy->type == BCM43xx_PHYTYPE_G) {
2055 if (antennadiv >= 2)
2056 bcm43xx_phy_write(bcm, 0x048C,
2057 bcm43xx_phy_read(bcm, 0x048C)
2060 bcm43xx_phy_write(bcm, 0x048C,
2061 bcm43xx_phy_read(bcm, 0x048C)
2063 if (phy->rev >= 2) {
2064 bcm43xx_phy_write(bcm, 0x0461,
2065 bcm43xx_phy_read(bcm, 0x0461)
2067 bcm43xx_phy_write(bcm, 0x04AD,
2068 (bcm43xx_phy_read(bcm, 0x04AD)
2069 & 0x00FF) | 0x0015);
2071 bcm43xx_phy_write(bcm, 0x0427, 0x0008);
2073 bcm43xx_phy_write(bcm, 0x0427,
2074 (bcm43xx_phy_read(bcm, 0x0427)
2075 & 0x00FF) | 0x0008);
2077 else if (phy->rev >= 6)
2078 bcm43xx_phy_write(bcm, 0x049B, 0x00DC);
2081 bcm43xx_phy_write(bcm, 0x002B,
2082 (bcm43xx_phy_read(bcm, 0x002B)
2083 & 0x00FF) | 0x0024);
2085 bcm43xx_phy_write(bcm, 0x0061,
2086 bcm43xx_phy_read(bcm, 0x0061)
2088 if (phy->rev == 3) {
2089 bcm43xx_phy_write(bcm, 0x0093, 0x001D);
2090 bcm43xx_phy_write(bcm, 0x0027, 0x0008);
2092 bcm43xx_phy_write(bcm, 0x0093, 0x003A);
2093 bcm43xx_phy_write(bcm, 0x0027,
2094 (bcm43xx_phy_read(bcm, 0x0027)
2095 & 0x00FF) | 0x0008);
2100 case BCM43xx_PHYTYPE_B:
2101 if (bcm->current_core->rev == 2)
2102 value = (3/*automatic*/ << 7);
2104 value = (antennadiv << 7);
2105 bcm43xx_phy_write(bcm, 0x03E2,
2106 (bcm43xx_phy_read(bcm, 0x03E2)
2113 if (antennadiv >= 2) {
2114 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2115 BCM43xx_UCODEFLAGS_OFFSET);
2116 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2117 BCM43xx_UCODEFLAGS_OFFSET,
2118 ucodeflags | BCM43xx_UCODEFLAG_AUTODIV);
2121 phy->antenna_diversity = antennadiv;