drivers/net/wireless/brcm80211/brcmfmac/pcie.c

   1 /* Copyright (c) 2014 Broadcom Corporation
   2  *
   3  * Permission to use, copy, modify, and/or distribute this software for any
   4  * purpose with or without fee is hereby granted, provided that the above
   5  * copyright notice and this permission notice appear in all copies.
   6  *
   7  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   8  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   9  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  10  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  11  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  12  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  13  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/firmware.h>
  19 #include <linux/pci.h>
  20 #include <linux/vmalloc.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/bcma/bcma.h>
  24 #include <linux/sched.h>
  25 #include <asm/unaligned.h>
  26
  27 #include <soc.h>
  28 #include <chipcommon.h>
  29 #include <brcmu_utils.h>
  30 #include <brcmu_wifi.h>
  31 #include <brcm_hw_ids.h>
  32
  33 #include "debug.h"
  34 #include "bus.h"
  35 #include "commonring.h"
  36 #include "msgbuf.h"
  37 #include "pcie.h"
  38 #include "firmware.h"
  39 #include "chip.h"
  40
  41
  42 enum brcmf_pcie_state {
  43         BRCMFMAC_PCIE_STATE_DOWN,
  44         BRCMFMAC_PCIE_STATE_UP
  45 };
  46
  47
  48 #define BRCMF_PCIE_43602_FW_NAME                "brcm/brcmfmac43602-pcie.bin"
  49 #define BRCMF_PCIE_43602_NVRAM_NAME             "brcm/brcmfmac43602-pcie.txt"
  50 #define BRCMF_PCIE_4350_FW_NAME                 "brcm/brcmfmac4350-pcie.bin"
  51 #define BRCMF_PCIE_4350_NVRAM_NAME              "brcm/brcmfmac4350-pcie.txt"
  52 #define BRCMF_PCIE_4356_FW_NAME                 "brcm/brcmfmac4356-pcie.bin"
  53 #define BRCMF_PCIE_4356_NVRAM_NAME              "brcm/brcmfmac4356-pcie.txt"
  54 #define BRCMF_PCIE_43570_FW_NAME                "brcm/brcmfmac43570-pcie.bin"
  55 #define BRCMF_PCIE_43570_NVRAM_NAME             "brcm/brcmfmac43570-pcie.txt"
  56 #define BRCMF_PCIE_4358_FW_NAME                 "brcm/brcmfmac4358-pcie.bin"
  57 #define BRCMF_PCIE_4358_NVRAM_NAME              "brcm/brcmfmac4358-pcie.txt"
  58 #define BRCMF_PCIE_4365_FW_NAME                 "brcm/brcmfmac4365b-pcie.bin"
  59 #define BRCMF_PCIE_4365_NVRAM_NAME              "brcm/brcmfmac4365b-pcie.txt"
  60 #define BRCMF_PCIE_4366_FW_NAME                 "brcm/brcmfmac4366b-pcie.bin"
  61 #define BRCMF_PCIE_4366_NVRAM_NAME              "brcm/brcmfmac4366b-pcie.txt"
  62
  63 #define BRCMF_PCIE_FW_UP_TIMEOUT                2000 /* msec */
  64
  65 #define BRCMF_PCIE_TCM_MAP_SIZE                 (4096 * 1024)
  66 #define BRCMF_PCIE_REG_MAP_SIZE                 (32 * 1024)
  67
  68 /* backplane addres space accessed by BAR0 */
  69 #define BRCMF_PCIE_BAR0_WINDOW                  0x80
  70 #define BRCMF_PCIE_BAR0_REG_SIZE                0x1000
  71 #define BRCMF_PCIE_BAR0_WRAPPERBASE             0x70
  72
  73 #define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET     0x1000
  74 #define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET        0x2000
  75
  76 #define BRCMF_PCIE_ARMCR4REG_BANKIDX            0x40
  77 #define BRCMF_PCIE_ARMCR4REG_BANKPDA            0x4C
  78
  79 #define BRCMF_PCIE_REG_INTSTATUS                0x90
  80 #define BRCMF_PCIE_REG_INTMASK                  0x94
  81 #define BRCMF_PCIE_REG_SBMBX                    0x98
  82
  83 #define BRCMF_PCIE_REG_LINK_STATUS_CTRL         0xBC
  84
  85 #define BRCMF_PCIE_PCIE2REG_INTMASK             0x24
  86 #define BRCMF_PCIE_PCIE2REG_MAILBOXINT          0x48
  87 #define BRCMF_PCIE_PCIE2REG_MAILBOXMASK         0x4C
  88 #define BRCMF_PCIE_PCIE2REG_CONFIGADDR          0x120
  89 #define BRCMF_PCIE_PCIE2REG_CONFIGDATA          0x124
  90 #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX         0x140
  91
  92 #define BRCMF_PCIE_GENREV1                      1
  93 #define BRCMF_PCIE_GENREV2                      2
  94
  95 #define BRCMF_PCIE2_INTA                        0x01
  96 #define BRCMF_PCIE2_INTB                        0x02
  97
  98 #define BRCMF_PCIE_INT_0                        0x01
  99 #define BRCMF_PCIE_INT_1                        0x02
 100 #define BRCMF_PCIE_INT_DEF                      (BRCMF_PCIE_INT_0 | \
 101                                                  BRCMF_PCIE_INT_1)
 102
 103 #define BRCMF_PCIE_MB_INT_FN0_0                 0x0100
 104 #define BRCMF_PCIE_MB_INT_FN0_1                 0x0200
 105 #define BRCMF_PCIE_MB_INT_D2H0_DB0              0x10000
 106 #define BRCMF_PCIE_MB_INT_D2H0_DB1              0x20000
 107 #define BRCMF_PCIE_MB_INT_D2H1_DB0              0x40000
 108 #define BRCMF_PCIE_MB_INT_D2H1_DB1              0x80000
 109 #define BRCMF_PCIE_MB_INT_D2H2_DB0              0x100000
 110 #define BRCMF_PCIE_MB_INT_D2H2_DB1              0x200000
 111 #define BRCMF_PCIE_MB_INT_D2H3_DB0              0x400000
 112 #define BRCMF_PCIE_MB_INT_D2H3_DB1              0x800000
 113
 114 #define BRCMF_PCIE_MB_INT_D2H_DB                (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 115                                                  BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 116                                                  BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 117                                                  BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 118                                                  BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 119                                                  BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 120                                                  BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 121                                                  BRCMF_PCIE_MB_INT_D2H3_DB1)
 122
 123 #define BRCMF_PCIE_MIN_SHARED_VERSION           5
 124 #define BRCMF_PCIE_MAX_SHARED_VERSION           5
 125 #define BRCMF_PCIE_SHARED_VERSION_MASK          0x00FF
 126 #define BRCMF_PCIE_SHARED_DMA_INDEX             0x10000
 127 #define BRCMF_PCIE_SHARED_DMA_2B_IDX            0x100000
 128
 129 #define BRCMF_PCIE_FLAGS_HTOD_SPLIT             0x4000
 130 #define BRCMF_PCIE_FLAGS_DTOH_SPLIT             0x8000
 131
 132 #define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET       34
 133 #define BRCMF_SHARED_RING_BASE_OFFSET           52
 134 #define BRCMF_SHARED_RX_DATAOFFSET_OFFSET       36
 135 #define BRCMF_SHARED_CONSOLE_ADDR_OFFSET        20
 136 #define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET   40
 137 #define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET   44
 138 #define BRCMF_SHARED_RING_INFO_ADDR_OFFSET      48
 139 #define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET     52
 140 #define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET    56
 141 #define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET     64
 142 #define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET    68
 143
 144 #define BRCMF_RING_H2D_RING_COUNT_OFFSET        0
 145 #define BRCMF_RING_D2H_RING_COUNT_OFFSET        1
 146 #define BRCMF_RING_H2D_RING_MEM_OFFSET          4
 147 #define BRCMF_RING_H2D_RING_STATE_OFFSET        8
 148
 149 #define BRCMF_RING_MEM_BASE_ADDR_OFFSET         8
 150 #define BRCMF_RING_MAX_ITEM_OFFSET              4
 151 #define BRCMF_RING_LEN_ITEMS_OFFSET             6
 152 #define BRCMF_RING_MEM_SZ                       16
 153 #define BRCMF_RING_STATE_SZ                     8
 154
 155 #define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET  4
 156 #define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET  8
 157 #define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET  12
 158 #define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET  16
 159 #define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET   20
 160 #define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET   28
 161 #define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET   36
 162 #define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET   44
 163 #define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET     0
 164 #define BRCMF_SHARED_RING_MAX_SUB_QUEUES        52
 165
 166 #define BRCMF_DEF_MAX_RXBUFPOST                 255
 167
 168 #define BRCMF_CONSOLE_BUFADDR_OFFSET            8
 169 #define BRCMF_CONSOLE_BUFSIZE_OFFSET            12
 170 #define BRCMF_CONSOLE_WRITEIDX_OFFSET           16
 171
 172 #define BRCMF_DMA_D2H_SCRATCH_BUF_LEN           8
 173 #define BRCMF_DMA_D2H_RINGUPD_BUF_LEN           1024
 174
 175 #define BRCMF_D2H_DEV_D3_ACK                    0x00000001
 176 #define BRCMF_D2H_DEV_DS_ENTER_REQ              0x00000002
 177 #define BRCMF_D2H_DEV_DS_EXIT_NOTE              0x00000004
 178
 179 #define BRCMF_H2D_HOST_D3_INFORM                0x00000001
 180 #define BRCMF_H2D_HOST_DS_ACK                   0x00000002
 181 #define BRCMF_H2D_HOST_D0_INFORM_IN_USE         0x00000008
 182 #define BRCMF_H2D_HOST_D0_INFORM                0x00000010
 183
 184 #define BRCMF_PCIE_MBDATA_TIMEOUT               2000
 185
 186 #define BRCMF_PCIE_CFGREG_STATUS_CMD            0x4
 187 #define BRCMF_PCIE_CFGREG_PM_CSR                0x4C
 188 #define BRCMF_PCIE_CFGREG_MSI_CAP               0x58
 189 #define BRCMF_PCIE_CFGREG_MSI_ADDR_L            0x5C
 190 #define BRCMF_PCIE_CFGREG_MSI_ADDR_H            0x60
 191 #define BRCMF_PCIE_CFGREG_MSI_DATA              0x64
 192 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL      0xBC
 193 #define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2     0xDC
 194 #define BRCMF_PCIE_CFGREG_RBAR_CTRL             0x228
 195 #define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1        0x248
 196 #define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG       0x4E0
 197 #define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG       0x4F4
 198 #define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB   3
 199
 200
 201 MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
 202 MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
 203 MODULE_FIRMWARE(BRCMF_PCIE_4350_FW_NAME);
 204 MODULE_FIRMWARE(BRCMF_PCIE_4350_NVRAM_NAME);
 205 MODULE_FIRMWARE(BRCMF_PCIE_4356_FW_NAME);
 206 MODULE_FIRMWARE(BRCMF_PCIE_4356_NVRAM_NAME);
 207 MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
 208 MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
 209 MODULE_FIRMWARE(BRCMF_PCIE_4358_FW_NAME);
 210 MODULE_FIRMWARE(BRCMF_PCIE_4358_NVRAM_NAME);
 211 MODULE_FIRMWARE(BRCMF_PCIE_4365_FW_NAME);
 212 MODULE_FIRMWARE(BRCMF_PCIE_4365_NVRAM_NAME);
 213 MODULE_FIRMWARE(BRCMF_PCIE_4366_FW_NAME);
 214 MODULE_FIRMWARE(BRCMF_PCIE_4366_NVRAM_NAME);
 215
 216
 217 struct brcmf_pcie_console {
 218         u32 base_addr;
 219         u32 buf_addr;
 220         u32 bufsize;
 221         u32 read_idx;
 222         u8 log_str[256];
 223         u8 log_idx;
 224 };
 225
 226 struct brcmf_pcie_shared_info {
 227         u32 tcm_base_address;
 228         u32 flags;
 229         struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 230         struct brcmf_pcie_ringbuf *flowrings;
 231         u16 max_rxbufpost;
 232         u32 nrof_flowrings;
 233         u32 rx_dataoffset;
 234         u32 htod_mb_data_addr;
 235         u32 dtoh_mb_data_addr;
 236         u32 ring_info_addr;
 237         struct brcmf_pcie_console console;
 238         void *scratch;
 239         dma_addr_t scratch_dmahandle;
 240         void *ringupd;
 241         dma_addr_t ringupd_dmahandle;
 242 };
 243
 244 struct brcmf_pcie_core_info {
 245         u32 base;
 246         u32 wrapbase;
 247 };
 248
 249 struct brcmf_pciedev_info {
 250         enum brcmf_pcie_state state;
 251         bool in_irq;
 252         bool irq_requested;
 253         struct pci_dev *pdev;
 254         char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 255         char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
 256         void __iomem *regs;
 257         void __iomem *tcm;
 258         u32 tcm_size;
 259         u32 ram_base;
 260         u32 ram_size;
 261         struct brcmf_chip *ci;
 262         u32 coreid;
 263         u32 generic_corerev;
 264         struct brcmf_pcie_shared_info shared;
 265         void (*ringbell)(struct brcmf_pciedev_info *devinfo);
 266         wait_queue_head_t mbdata_resp_wait;
 267         bool mbdata_completed;
 268         bool irq_allocated;
 269         bool wowl_enabled;
 270         u8 dma_idx_sz;
 271         void *idxbuf;
 272         u32 idxbuf_sz;
 273         dma_addr_t idxbuf_dmahandle;
 274         u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 275         void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 276                           u16 value);
 277 };
 278
 279 struct brcmf_pcie_ringbuf {
 280         struct brcmf_commonring commonring;
 281         dma_addr_t dma_handle;
 282         u32 w_idx_addr;
 283         u32 r_idx_addr;
 284         struct brcmf_pciedev_info *devinfo;
 285         u8 id;
 286 };
 287
 288
 289 static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 290         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 291         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 292         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 293         BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 294         BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 295 };
 296
 297 static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 298         BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 299         BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 300         BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 301         BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 302         BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 303 };
 304
 305
 306 static u32
 307 brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 308 {
 309         void __iomem *address = devinfo->regs + reg_offset;
 310
 311         return (ioread32(address));
 312 }
 313
 314
 315 static void
 316 brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 317                        u32 value)
 318 {
 319         void __iomem *address = devinfo->regs + reg_offset;
 320
 321         iowrite32(value, address);
 322 }
 323
 324
 325 static u8
 326 brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 327 {
 328         void __iomem *address = devinfo->tcm + mem_offset;
 329
 330         return (ioread8(address));
 331 }
 332
 333
 334 static u16
 335 brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 336 {
 337         void __iomem *address = devinfo->tcm + mem_offset;
 338
 339         return (ioread16(address));
 340 }
 341
 342
 343 static void
 344 brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 345                        u16 value)
 346 {
 347         void __iomem *address = devinfo->tcm + mem_offset;
 348
 349         iowrite16(value, address);
 350 }
 351
 352
 353 static u16
 354 brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 355 {
 356         u16 *address = devinfo->idxbuf + mem_offset;
 357
 358         return (*(address));
 359 }
 360
 361
 362 static void
 363 brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 364                      u16 value)
 365 {
 366         u16 *address = devinfo->idxbuf + mem_offset;
 367
 368         *(address) = value;
 369 }
 370
 371
 372 static u32
 373 brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 374 {
 375         void __iomem *address = devinfo->tcm + mem_offset;
 376
 377         return (ioread32(address));
 378 }
 379
 380
 381 static void
 382 brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 383                        u32 value)
 384 {
 385         void __iomem *address = devinfo->tcm + mem_offset;
 386
 387         iowrite32(value, address);
 388 }
 389
 390
 391 static u32
 392 brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 393 {
 394         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 395
 396         return (ioread32(addr));
 397 }
 398
 399
 400 static void
 401 brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 402                        u32 value)
 403 {
 404         void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 405
 406         iowrite32(value, addr);
 407 }
 408
 409
 410 static void
 411 brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 412                           void *srcaddr, u32 len)
 413 {
 414         void __iomem *address = devinfo->tcm + mem_offset;
 415         __le32 *src32;
 416         __le16 *src16;
 417         u8 *src8;
 418
 419         if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
 420                 if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
 421                         src8 = (u8 *)srcaddr;
 422                         while (len) {
 423                                 iowrite8(*src8, address);
 424                                 address++;
 425                                 src8++;
 426                                 len--;
 427                         }
 428                 } else {
 429                         len = len / 2;
 430                         src16 = (__le16 *)srcaddr;
 431                         while (len) {
 432                                 iowrite16(le16_to_cpu(*src16), address);
 433                                 address += 2;
 434                                 src16++;
 435                                 len--;
 436                         }
 437                 }
 438         } else {
 439                 len = len / 4;
 440                 src32 = (__le32 *)srcaddr;
 441                 while (len) {
 442                         iowrite32(le32_to_cpu(*src32), address);
 443                         address += 4;
 444                         src32++;
 445                         len--;
 446                 }
 447         }
 448 }
 449
 450
 451 #define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 452                 CHIPCREGOFFS(reg), value)
 453
 454
 455 static void
 456 brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 457 {
 458         const struct pci_dev *pdev = devinfo->pdev;
 459         struct brcmf_core *core;
 460         u32 bar0_win;
 461
 462         core = brcmf_chip_get_core(devinfo->ci, coreid);
 463         if (core) {
 464                 bar0_win = core->base;
 465                 pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 466                 if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 467                                           &bar0_win) == 0) {
 468                         if (bar0_win != core->base) {
 469                                 bar0_win = core->base;
 470                                 pci_write_config_dword(pdev,
 471                                                        BRCMF_PCIE_BAR0_WINDOW,
 472                                                        bar0_win);
 473                         }
 474                 }
 475         } else {
 476                 brcmf_err("Unsupported core selected %x\n", coreid);
 477         }
 478 }
 479
 480
 481 static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 482 {
 483         struct brcmf_core *core;
 484         u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
 485                              BRCMF_PCIE_CFGREG_PM_CSR,
 486                              BRCMF_PCIE_CFGREG_MSI_CAP,
 487                              BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 488                              BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 489                              BRCMF_PCIE_CFGREG_MSI_DATA,
 490                              BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 491                              BRCMF_PCIE_CFGREG_RBAR_CTRL,
 492                              BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 493                              BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 494                              BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
 495         u32 i;
 496         u32 val;
 497         u32 lsc;
 498
 499         if (!devinfo->ci)
 500                 return;
 501
 502         /* Disable ASPM */
 503         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 504         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 505                               &lsc);
 506         val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 507         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 508                                val);
 509
 510         /* Watchdog reset */
 511         brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 512         WRITECC32(devinfo, watchdog, 4);
 513         msleep(100);
 514
 515         /* Restore ASPM */
 516         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 517         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 518                                lsc);
 519
 520         core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 521         if (core->rev <= 13) {
 522                 for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 523                         brcmf_pcie_write_reg32(devinfo,
 524                                                BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 525                                                cfg_offset[i]);
 526                         val = brcmf_pcie_read_reg32(devinfo,
 527                                 BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 528                         brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 529                                   cfg_offset[i], val);
 530                         brcmf_pcie_write_reg32(devinfo,
 531                                                BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 532                                                val);
 533                 }
 534         }
 535 }
 536
 537
 538 static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 539 {
 540         u32 config;
 541
 542         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 543         /* BAR1 window may not be sized properly */
 544         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 545         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 546         config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 547         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 548
 549         device_wakeup_enable(&devinfo->pdev->dev);
 550 }
 551
 552
 553 static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 554 {
 555         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 556                 brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 557                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 558                                        5);
 559                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 560                                        0);
 561                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 562                                        7);
 563                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 564                                        0);
 565         }
 566         return 0;
 567 }
 568
 569
 570 static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 571                                           u32 resetintr)
 572 {
 573         struct brcmf_core *core;
 574
 575         if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 576                 core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 577                 brcmf_chip_resetcore(core, 0, 0, 0);
 578         }
 579
 580         return !brcmf_chip_set_active(devinfo->ci, resetintr);
 581 }
 582
 583
 584 static int
 585 brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 586 {
 587         struct brcmf_pcie_shared_info *shared;
 588         u32 addr;
 589         u32 cur_htod_mb_data;
 590         u32 i;
 591
 592         shared = &devinfo->shared;
 593         addr = shared->htod_mb_data_addr;
 594         cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 595
 596         if (cur_htod_mb_data != 0)
 597                 brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 598                           cur_htod_mb_data);
 599
 600         i = 0;
 601         while (cur_htod_mb_data != 0) {
 602                 msleep(10);
 603                 i++;
 604                 if (i > 100)
 605                         return -EIO;
 606                 cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 607         }
 608
 609         brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 610         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 611         pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 612
 613         return 0;
 614 }
 615
 616
 617 static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 618 {
 619         struct brcmf_pcie_shared_info *shared;
 620         u32 addr;
 621         u32 dtoh_mb_data;
 622
 623         shared = &devinfo->shared;
 624         addr = shared->dtoh_mb_data_addr;
 625         dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 626
 627         if (!dtoh_mb_data)
 628                 return;
 629
 630         brcmf_pcie_write_tcm32(devinfo, addr, 0);
 631
 632         brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 633         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 634                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 635                 brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 636                 brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 637         }
 638         if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 639                 brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 640         if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 641                 brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 642                 if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
 643                         devinfo->mbdata_completed = true;
 644                         wake_up(&devinfo->mbdata_resp_wait);
 645                 }
 646         }
 647 }
 648
 649
 650 static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 651 {
 652         struct brcmf_pcie_shared_info *shared;
 653         struct brcmf_pcie_console *console;
 654         u32 addr;
 655
 656         shared = &devinfo->shared;
 657         console = &shared->console;
 658         addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 659         console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 660
 661         addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 662         console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 663         addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 664         console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 665
 666         brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 667                   console->base_addr, console->buf_addr, console->bufsize);
 668 }
 669
 670
 671 static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
 672 {
 673         struct brcmf_pcie_console *console;
 674         u32 addr;
 675         u8 ch;
 676         u32 newidx;
 677
 678         if (!BRCMF_FWCON_ON())
 679                 return;
 680
 681         console = &devinfo->shared.console;
 682         addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 683         newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 684         while (newidx != console->read_idx) {
 685                 addr = console->buf_addr + console->read_idx;
 686                 ch = brcmf_pcie_read_tcm8(devinfo, addr);
 687                 console->read_idx++;
 688                 if (console->read_idx == console->bufsize)
 689                         console->read_idx = 0;
 690                 if (ch == '\r')
 691                         continue;
 692                 console->log_str[console->log_idx] = ch;
 693                 console->log_idx++;
 694                 if ((ch != '\n') &&
 695                     (console->log_idx == (sizeof(console->log_str) - 2))) {
 696                         ch = '\n';
 697                         console->log_str[console->log_idx] = ch;
 698                         console->log_idx++;
 699                 }
 700                 if (ch == '\n') {
 701                         console->log_str[console->log_idx] = 0;
 702                         pr_debug("CONSOLE: %s", console->log_str);
 703                         console->log_idx = 0;
 704                 }
 705         }
 706 }
 707
 708
 709 static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
 710 {
 711         u32 reg_value;
 712
 713         brcmf_dbg(PCIE, "RING !\n");
 714         reg_value = brcmf_pcie_read_reg32(devinfo,
 715                                           BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 716         reg_value |= BRCMF_PCIE2_INTB;
 717         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 718                                reg_value);
 719 }
 720
 721
 722 static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
 723 {
 724         brcmf_dbg(PCIE, "RING !\n");
 725         /* Any arbitrary value will do, lets use 1 */
 726         brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 727 }
 728
 729
 730 static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 731 {
 732         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 733                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 734                                        0);
 735         else
 736                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 737                                        0);
 738 }
 739
 740
 741 static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 742 {
 743         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
 744                 pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
 745                                        BRCMF_PCIE_INT_DEF);
 746         else
 747                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 748                                        BRCMF_PCIE_MB_INT_D2H_DB |
 749                                        BRCMF_PCIE_MB_INT_FN0_0 |
 750                                        BRCMF_PCIE_MB_INT_FN0_1);
 751 }
 752
 753
 754 static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
 755 {
 756         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 757         u32 status;
 758
 759         status = 0;
 760         pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 761         if (status) {
 762                 brcmf_pcie_intr_disable(devinfo);
 763                 brcmf_dbg(PCIE, "Enter\n");
 764                 return IRQ_WAKE_THREAD;
 765         }
 766         return IRQ_NONE;
 767 }
 768
 769
 770 static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 771 {
 772         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 773
 774         if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
 775                 brcmf_pcie_intr_disable(devinfo);
 776                 brcmf_dbg(PCIE, "Enter\n");
 777                 return IRQ_WAKE_THREAD;
 778         }
 779         return IRQ_NONE;
 780 }
 781
 782
 783 static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 784 {
 785         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 786         const struct pci_dev *pdev = devinfo->pdev;
 787         u32 status;
 788
 789         devinfo->in_irq = true;
 790         status = 0;
 791         pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 792         brcmf_dbg(PCIE, "Enter %x\n", status);
 793         if (status) {
 794                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 795                 if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 796                         brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 797         }
 798         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 799                 brcmf_pcie_intr_enable(devinfo);
 800         devinfo->in_irq = false;
 801         return IRQ_HANDLED;
 802 }
 803
 804
 805 static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 806 {
 807         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 808         u32 status;
 809
 810         devinfo->in_irq = true;
 811         status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 812         brcmf_dbg(PCIE, "Enter %x\n", status);
 813         if (status) {
 814                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 815                                        status);
 816                 if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
 817                               BRCMF_PCIE_MB_INT_FN0_1))
 818                         brcmf_pcie_handle_mb_data(devinfo);
 819                 if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
 820                         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 821                                 brcmf_proto_msgbuf_rx_trigger(
 822                                                         &devinfo->pdev->dev);
 823                 }
 824         }
 825         brcmf_pcie_bus_console_read(devinfo);
 826         if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 827                 brcmf_pcie_intr_enable(devinfo);
 828         devinfo->in_irq = false;
 829         return IRQ_HANDLED;
 830 }
 831
 832
 833 static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 834 {
 835         struct pci_dev *pdev;
 836
 837         pdev = devinfo->pdev;
 838
 839         brcmf_pcie_intr_disable(devinfo);
 840
 841         brcmf_dbg(PCIE, "Enter\n");
 842         /* is it a v1 or v2 implementation */
 843         devinfo->irq_requested = false;
 844         pci_enable_msi(pdev);
 845         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 846                 if (request_threaded_irq(pdev->irq,
 847                                          brcmf_pcie_quick_check_isr_v1,
 848                                          brcmf_pcie_isr_thread_v1,
 849                                          IRQF_SHARED, "brcmf_pcie_intr",
 850                                          devinfo)) {
 851                         pci_disable_msi(pdev);
 852                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 853                         return -EIO;
 854                 }
 855         } else {
 856                 if (request_threaded_irq(pdev->irq,
 857                                          brcmf_pcie_quick_check_isr_v2,
 858                                          brcmf_pcie_isr_thread_v2,
 859                                          IRQF_SHARED, "brcmf_pcie_intr",
 860                                          devinfo)) {
 861                         pci_disable_msi(pdev);
 862                         brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 863                         return -EIO;
 864                 }
 865         }
 866         devinfo->irq_requested = true;
 867         devinfo->irq_allocated = true;
 868         return 0;
 869 }
 870
 871
 872 static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 873 {
 874         struct pci_dev *pdev;
 875         u32 status;
 876         u32 count;
 877
 878         if (!devinfo->irq_allocated)
 879                 return;
 880
 881         pdev = devinfo->pdev;
 882
 883         brcmf_pcie_intr_disable(devinfo);
 884         if (!devinfo->irq_requested)
 885                 return;
 886         devinfo->irq_requested = false;
 887         free_irq(pdev->irq, devinfo);
 888         pci_disable_msi(pdev);
 889
 890         msleep(50);
 891         count = 0;
 892         while ((devinfo->in_irq) && (count < 20)) {
 893                 msleep(50);
 894                 count++;
 895         }
 896         if (devinfo->in_irq)
 897                 brcmf_err("Still in IRQ (processing) !!!\n");
 898
 899         if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 900                 status = 0;
 901                 pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 902                 pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 903         } else {
 904                 status = brcmf_pcie_read_reg32(devinfo,
 905                                                BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 906                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 907                                        status);
 908         }
 909         devinfo->irq_allocated = false;
 910 }
 911
 912
 913 static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
 914 {
 915         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 916         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 917         struct brcmf_commonring *commonring = &ring->commonring;
 918
 919         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 920                 return -EIO;
 921
 922         brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 923                   commonring->w_ptr, ring->id);
 924
 925         devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
 926
 927         return 0;
 928 }
 929
 930
 931 static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
 932 {
 933         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 934         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 935         struct brcmf_commonring *commonring = &ring->commonring;
 936
 937         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 938                 return -EIO;
 939
 940         brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 941                   commonring->r_ptr, ring->id);
 942
 943         devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
 944
 945         return 0;
 946 }
 947
 948
 949 static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
 950 {
 951         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 952         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 953
 954         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 955                 return -EIO;
 956
 957         devinfo->ringbell(devinfo);
 958
 959         return 0;
 960 }
 961
 962
 963 static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
 964 {
 965         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 966         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 967         struct brcmf_commonring *commonring = &ring->commonring;
 968
 969         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 970                 return -EIO;
 971
 972         commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
 973
 974         brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
 975                   commonring->w_ptr, ring->id);
 976
 977         return 0;
 978 }
 979
 980
 981 static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
 982 {
 983         struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
 984         struct brcmf_pciedev_info *devinfo = ring->devinfo;
 985         struct brcmf_commonring *commonring = &ring->commonring;
 986
 987         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 988                 return -EIO;
 989
 990         commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
 991
 992         brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
 993                   commonring->r_ptr, ring->id);
 994
 995         return 0;
 996 }
 997
 998
 999 static void *
1000 brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1001                                      u32 size, u32 tcm_dma_phys_addr,
1002                                      dma_addr_t *dma_handle)
1003 {
1004         void *ring;
1005         u64 address;
1006
1007         ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1008                                   GFP_KERNEL);
1009         if (!ring)
1010                 return NULL;
1011
1012         address = (u64)*dma_handle;
1013         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1014                                address & 0xffffffff);
1015         brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1016
1017         memset(ring, 0, size);
1018
1019         return (ring);
1020 }
1021
1022
1023 static struct brcmf_pcie_ringbuf *
1024 brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1025                               u32 tcm_ring_phys_addr)
1026 {
1027         void *dma_buf;
1028         dma_addr_t dma_handle;
1029         struct brcmf_pcie_ringbuf *ring;
1030         u32 size;
1031         u32 addr;
1032
1033         size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
1034         dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1035                         tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1036                         &dma_handle);
1037         if (!dma_buf)
1038                 return NULL;
1039
1040         addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1041         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1042         addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1043         brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
1044
1045         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1046         if (!ring) {
1047                 dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1048                                   dma_handle);
1049                 return NULL;
1050         }
1051         brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1052                                 brcmf_ring_itemsize[ring_id], dma_buf);
1053         ring->dma_handle = dma_handle;
1054         ring->devinfo = devinfo;
1055         brcmf_commonring_register_cb(&ring->commonring,
1056                                      brcmf_pcie_ring_mb_ring_bell,
1057                                      brcmf_pcie_ring_mb_update_rptr,
1058                                      brcmf_pcie_ring_mb_update_wptr,
1059                                      brcmf_pcie_ring_mb_write_rptr,
1060                                      brcmf_pcie_ring_mb_write_wptr, ring);
1061
1062         return (ring);
1063 }
1064
1065
1066 static void brcmf_pcie_release_ringbuffer(struct device *dev,
1067                                           struct brcmf_pcie_ringbuf *ring)
1068 {
1069         void *dma_buf;
1070         u32 size;
1071
1072         if (!ring)
1073                 return;
1074
1075         dma_buf = ring->commonring.buf_addr;
1076         if (dma_buf) {
1077                 size = ring->commonring.depth * ring->commonring.item_len;
1078                 dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1079         }
1080         kfree(ring);
1081 }
1082
1083
1084 static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1085 {
1086         u32 i;
1087
1088         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1089                 brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1090                                               devinfo->shared.commonrings[i]);
1091                 devinfo->shared.commonrings[i] = NULL;
1092         }
1093         kfree(devinfo->shared.flowrings);
1094         devinfo->shared.flowrings = NULL;
1095         if (devinfo->idxbuf) {
1096                 dma_free_coherent(&devinfo->pdev->dev,
1097                                   devinfo->idxbuf_sz,
1098                                   devinfo->idxbuf,
1099                                   devinfo->idxbuf_dmahandle);
1100                 devinfo->idxbuf = NULL;
1101         }
1102 }
1103
1104
1105 static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1106 {
1107         struct brcmf_pcie_ringbuf *ring;
1108         struct brcmf_pcie_ringbuf *rings;
1109         u32 ring_addr;
1110         u32 d2h_w_idx_ptr;
1111         u32 d2h_r_idx_ptr;
1112         u32 h2d_w_idx_ptr;
1113         u32 h2d_r_idx_ptr;
1114         u32 addr;
1115         u32 ring_mem_ptr;
1116         u32 i;
1117         u64 address;
1118         u32 bufsz;
1119         u16 max_sub_queues;
1120         u8 idx_offset;
1121
1122         ring_addr = devinfo->shared.ring_info_addr;
1123         brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
1124         addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
1125         max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
1126
1127         if (devinfo->dma_idx_sz != 0) {
1128                 bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
1129                         devinfo->dma_idx_sz * 2;
1130                 devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1131                                                      &devinfo->idxbuf_dmahandle,
1132                                                      GFP_KERNEL);
1133                 if (!devinfo->idxbuf)
1134                         devinfo->dma_idx_sz = 0;
1135         }
1136
1137         if (devinfo->dma_idx_sz == 0) {
1138                 addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
1139                 d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1140                 addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
1141                 d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1142                 addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
1143                 h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1144                 addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
1145                 h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1146                 idx_offset = sizeof(u32);
1147                 devinfo->write_ptr = brcmf_pcie_write_tcm16;
1148                 devinfo->read_ptr = brcmf_pcie_read_tcm16;
1149                 brcmf_dbg(PCIE, "Using TCM indices\n");
1150         } else {
1151                 memset(devinfo->idxbuf, 0, bufsz);
1152                 devinfo->idxbuf_sz = bufsz;
1153                 idx_offset = devinfo->dma_idx_sz;
1154                 devinfo->write_ptr = brcmf_pcie_write_idx;
1155                 devinfo->read_ptr = brcmf_pcie_read_idx;
1156
1157                 h2d_w_idx_ptr = 0;
1158                 addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
1159                 address = (u64)devinfo->idxbuf_dmahandle;
1160                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1161                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1162
1163                 h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
1164                 addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
1165                 address += max_sub_queues * idx_offset;
1166                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1167                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1168
1169                 d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
1170                 addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
1171                 address += max_sub_queues * idx_offset;
1172                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1173                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1174
1175                 d2h_r_idx_ptr = d2h_w_idx_ptr +
1176                                 BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1177                 addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
1178                 address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
1179                 brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1180                 brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1181                 brcmf_dbg(PCIE, "Using host memory indices\n");
1182         }
1183
1184         addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
1185         ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
1186
1187         for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1188                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1189                 if (!ring)
1190                         goto fail;
1191                 ring->w_idx_addr = h2d_w_idx_ptr;
1192                 ring->r_idx_addr = h2d_r_idx_ptr;
1193                 ring->id = i;
1194                 devinfo->shared.commonrings[i] = ring;
1195
1196                 h2d_w_idx_ptr += idx_offset;
1197                 h2d_r_idx_ptr += idx_offset;
1198                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1199         }
1200
1201         for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1202              i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1203                 ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1204                 if (!ring)
1205                         goto fail;
1206                 ring->w_idx_addr = d2h_w_idx_ptr;
1207                 ring->r_idx_addr = d2h_r_idx_ptr;
1208                 ring->id = i;
1209                 devinfo->shared.commonrings[i] = ring;
1210
1211                 d2h_w_idx_ptr += idx_offset;
1212                 d2h_r_idx_ptr += idx_offset;
1213                 ring_mem_ptr += BRCMF_RING_MEM_SZ;
1214         }
1215
1216         devinfo->shared.nrof_flowrings =
1217                         max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
1218         rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
1219                         GFP_KERNEL);
1220         if (!rings)
1221                 goto fail;
1222
1223         brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
1224                   devinfo->shared.nrof_flowrings);
1225
1226         for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
1227                 ring = &rings[i];
1228                 ring->devinfo = devinfo;
1229                 ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
1230                 brcmf_commonring_register_cb(&ring->commonring,
1231                                              brcmf_pcie_ring_mb_ring_bell,
1232                                              brcmf_pcie_ring_mb_update_rptr,
1233                                              brcmf_pcie_ring_mb_update_wptr,
1234                                              brcmf_pcie_ring_mb_write_rptr,
1235                                              brcmf_pcie_ring_mb_write_wptr,
1236                                              ring);
1237                 ring->w_idx_addr = h2d_w_idx_ptr;
1238                 ring->r_idx_addr = h2d_r_idx_ptr;
1239                 h2d_w_idx_ptr += idx_offset;
1240                 h2d_r_idx_ptr += idx_offset;
1241         }
1242         devinfo->shared.flowrings = rings;
1243
1244         return 0;
1245
1246 fail:
1247         brcmf_err("Allocating ring buffers failed\n");
1248         brcmf_pcie_release_ringbuffers(devinfo);
1249         return -ENOMEM;
1250 }
1251
1252
1253 static void
1254 brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1255 {
1256         if (devinfo->shared.scratch)
1257                 dma_free_coherent(&devinfo->pdev->dev,
1258                                   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1259                                   devinfo->shared.scratch,
1260                                   devinfo->shared.scratch_dmahandle);
1261         if (devinfo->shared.ringupd)
1262                 dma_free_coherent(&devinfo->pdev->dev,
1263                                   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1264                                   devinfo->shared.ringupd,
1265                                   devinfo->shared.ringupd_dmahandle);
1266 }
1267
1268 static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1269 {
1270         u64 address;
1271         u32 addr;
1272
1273         devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
1274                 BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1275                 &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
1276         if (!devinfo->shared.scratch)
1277                 goto fail;
1278
1279         memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1280
1281         addr = devinfo->shared.tcm_base_address +
1282                BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1283         address = (u64)devinfo->shared.scratch_dmahandle;
1284         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1285         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1286         addr = devinfo->shared.tcm_base_address +
1287                BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1288         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1289
1290         devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
1291                 BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1292                 &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
1293         if (!devinfo->shared.ringupd)
1294                 goto fail;
1295
1296         memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1297
1298         addr = devinfo->shared.tcm_base_address +
1299                BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1300         address = (u64)devinfo->shared.ringupd_dmahandle;
1301         brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1302         brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1303         addr = devinfo->shared.tcm_base_address +
1304                BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1305         brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1306         return 0;
1307
1308 fail:
1309         brcmf_err("Allocating scratch buffers failed\n");
1310         brcmf_pcie_release_scratchbuffers(devinfo);
1311         return -ENOMEM;
1312 }
1313
1314
1315 static void brcmf_pcie_down(struct device *dev)
1316 {
1317 }
1318
1319
1320 static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1321 {
1322         return 0;
1323 }
1324
1325
1326 static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1327                                 uint len)
1328 {
1329         return 0;
1330 }
1331
1332
1333 static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1334                                 uint len)
1335 {
1336         return 0;
1337 }
1338
1339
1340 static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1341 {
1342         struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1343         struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1344         struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1345
1346         brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1347         devinfo->wowl_enabled = enabled;
1348         if (enabled)
1349                 device_set_wakeup_enable(&devinfo->pdev->dev, true);
1350         else
1351                 device_set_wakeup_enable(&devinfo->pdev->dev, false);
1352 }
1353
1354
1355 static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1356         .txdata = brcmf_pcie_tx,
1357         .stop = brcmf_pcie_down,
1358         .txctl = brcmf_pcie_tx_ctlpkt,
1359         .rxctl = brcmf_pcie_rx_ctlpkt,
1360         .wowl_config = brcmf_pcie_wowl_config,
1361 };
1362
1363
1364 static int
1365 brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1366                                u32 sharedram_addr)
1367 {
1368         struct brcmf_pcie_shared_info *shared;
1369         u32 addr;
1370         u32 version;
1371
1372         shared = &devinfo->shared;
1373         shared->tcm_base_address = sharedram_addr;
1374
1375         shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1376         version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
1377         brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
1378         if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1379             (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1380                 brcmf_err("Unsupported PCIE version %d\n", version);
1381                 return -EINVAL;
1382         }
1383
1384         /* check firmware support dma indicies */
1385         if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1386                 if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1387                         devinfo->dma_idx_sz = sizeof(u16);
1388                 else
1389                         devinfo->dma_idx_sz = sizeof(u32);
1390         }
1391
1392         addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1393         shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1394         if (shared->max_rxbufpost == 0)
1395                 shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1396
1397         addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1398         shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1399
1400         addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1401         shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1402
1403         addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1404         shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1405
1406         addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1407         shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1408
1409         brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1410                   shared->max_rxbufpost, shared->rx_dataoffset);
1411
1412         brcmf_pcie_bus_console_init(devinfo);
1413
1414         return 0;
1415 }
1416
1417
1418 static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
1419 {
1420         char *fw_name;
1421         char *nvram_name;
1422         uint fw_len, nv_len;
1423         char end;
1424
1425         brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
1426                   devinfo->ci->chiprev);
1427
1428         switch (devinfo->ci->chip) {
1429         case BRCM_CC_43602_CHIP_ID:
1430                 fw_name = BRCMF_PCIE_43602_FW_NAME;
1431                 nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
1432                 break;
1433         case BRCM_CC_4350_CHIP_ID:
1434                 fw_name = BRCMF_PCIE_4350_FW_NAME;
1435                 nvram_name = BRCMF_PCIE_4350_NVRAM_NAME;
1436                 break;
1437         case BRCM_CC_4356_CHIP_ID:
1438                 fw_name = BRCMF_PCIE_4356_FW_NAME;
1439                 nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
1440                 break;
1441         case BRCM_CC_43567_CHIP_ID:
1442         case BRCM_CC_43569_CHIP_ID:
1443         case BRCM_CC_43570_CHIP_ID:
1444                 fw_name = BRCMF_PCIE_43570_FW_NAME;
1445                 nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
1446                 break;
1447         case BRCM_CC_4358_CHIP_ID:
1448                 fw_name = BRCMF_PCIE_4358_FW_NAME;
1449                 nvram_name = BRCMF_PCIE_4358_NVRAM_NAME;
1450                 break;
1451         case BRCM_CC_4365_CHIP_ID:
1452                 fw_name = BRCMF_PCIE_4365_FW_NAME;
1453                 nvram_name = BRCMF_PCIE_4365_NVRAM_NAME;
1454                 break;
1455         case BRCM_CC_4366_CHIP_ID:
1456                 fw_name = BRCMF_PCIE_4366_FW_NAME;
1457                 nvram_name = BRCMF_PCIE_4366_NVRAM_NAME;
1458                 break;
1459         default:
1460                 brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
1461                 return -ENODEV;
1462         }
1463
1464         fw_len = sizeof(devinfo->fw_name) - 1;
1465         nv_len = sizeof(devinfo->nvram_name) - 1;
1466         /* check if firmware path is provided by module parameter */
1467         if (brcmf_firmware_path[0] != '\0') {
1468                 strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
1469                 strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
1470                 fw_len -= strlen(devinfo->fw_name);
1471                 nv_len -= strlen(devinfo->nvram_name);
1472
1473                 end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
1474                 if (end != '/') {
1475                         strncat(devinfo->fw_name, "/", fw_len);
1476                         strncat(devinfo->nvram_name, "/", nv_len);
1477                         fw_len--;
1478                         nv_len--;
1479                 }
1480         }
1481         strncat(devinfo->fw_name, fw_name, fw_len);
1482         strncat(devinfo->nvram_name, nvram_name, nv_len);
1483
1484         return 0;
1485 }
1486
1487
1488 static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1489                                         const struct firmware *fw, void *nvram,
1490                                         u32 nvram_len)
1491 {
1492         u32 sharedram_addr;
1493         u32 sharedram_addr_written;
1494         u32 loop_counter;
1495         int err;
1496         u32 address;
1497         u32 resetintr;
1498
1499         devinfo->ringbell = brcmf_pcie_ringbell_v2;
1500         devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1501
1502         brcmf_dbg(PCIE, "Halt ARM.\n");
1503         err = brcmf_pcie_enter_download_state(devinfo);
1504         if (err)
1505                 return err;
1506
1507         brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1508         brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
1509                                   (void *)fw->data, fw->size);
1510
1511         resetintr = get_unaligned_le32(fw->data);
1512         release_firmware(fw);
1513
1514         /* reset last 4 bytes of RAM address. to be used for shared
1515          * area. This identifies when FW is running
1516          */
1517         brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1518
1519         if (nvram) {
1520                 brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1521                 address = devinfo->ci->rambase + devinfo->ci->ramsize -
1522                           nvram_len;
1523                 brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
1524                 brcmf_fw_nvram_free(nvram);
1525         } else {
1526                 brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1527                           devinfo->nvram_name);
1528         }
1529
1530         sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1531                                                        devinfo->ci->ramsize -
1532                                                        4);
1533         brcmf_dbg(PCIE, "Bring ARM in running state\n");
1534         err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1535         if (err)
1536                 return err;
1537
1538         brcmf_dbg(PCIE, "Wait for FW init\n");
1539         sharedram_addr = sharedram_addr_written;
1540         loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1541         while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1542                 msleep(50);
1543                 sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1544                                                        devinfo->ci->ramsize -
1545                                                        4);
1546                 loop_counter--;
1547         }
1548         if (sharedram_addr == sharedram_addr_written) {
1549                 brcmf_err("FW failed to initialize\n");
1550                 return -ENODEV;
1551         }
1552         brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1553
1554         return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1555 }
1556
1557
1558 static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1559 {
1560         struct pci_dev *pdev;
1561         int err;
1562         phys_addr_t  bar0_addr, bar1_addr;
1563         ulong bar1_size;
1564
1565         pdev = devinfo->pdev;
1566
1567         err = pci_enable_device(pdev);
1568         if (err) {
1569                 brcmf_err("pci_enable_device failed err=%d\n", err);
1570                 return err;
1571         }
1572
1573         pci_set_master(pdev);
1574
1575         /* Bar-0 mapped address */
1576         bar0_addr = pci_resource_start(pdev, 0);
1577         /* Bar-1 mapped address */
1578         bar1_addr = pci_resource_start(pdev, 2);
1579         /* read Bar-1 mapped memory range */
1580         bar1_size = pci_resource_len(pdev, 2);
1581         if ((bar1_size == 0) || (bar1_addr == 0)) {
1582                 brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1583                           bar1_size, (unsigned long long)bar1_addr);
1584                 return -EINVAL;
1585         }
1586
1587         devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1588         devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
1589         devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
1590
1591         if (!devinfo->regs || !devinfo->tcm) {
1592                 brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
1593                           devinfo->tcm);
1594                 return -EINVAL;
1595         }
1596         brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1597                   devinfo->regs, (unsigned long long)bar0_addr);
1598         brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
1599                   devinfo->tcm, (unsigned long long)bar1_addr);
1600
1601         return 0;
1602 }
1603
1604
1605 static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1606 {
1607         if (devinfo->tcm)
1608                 iounmap(devinfo->tcm);
1609         if (devinfo->regs)
1610                 iounmap(devinfo->regs);
1611
1612         pci_disable_device(devinfo->pdev);
1613 }
1614
1615
1616 static int brcmf_pcie_attach_bus(struct device *dev)
1617 {
1618         int ret;
1619
1620         /* Attach to the common driver interface */
1621         ret = brcmf_attach(dev);
1622         if (ret) {
1623                 brcmf_err("brcmf_attach failed\n");
1624         } else {
1625                 ret = brcmf_bus_start(dev);
1626                 if (ret)
1627                         brcmf_err("dongle is not responding\n");
1628         }
1629
1630         return ret;
1631 }
1632
1633
1634 static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1635 {
1636         u32 ret_addr;
1637
1638         ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1639         addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1640         pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1641
1642         return ret_addr;
1643 }
1644
1645
1646 static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1647 {
1648         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1649
1650         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1651         return brcmf_pcie_read_reg32(devinfo, addr);
1652 }
1653
1654
1655 static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1656 {
1657         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1658
1659         addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1660         brcmf_pcie_write_reg32(devinfo, addr, value);
1661 }
1662
1663
1664 static int brcmf_pcie_buscoreprep(void *ctx)
1665 {
1666         return brcmf_pcie_get_resource(ctx);
1667 }
1668
1669
1670 static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1671 {
1672         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1673         u32 val;
1674
1675         devinfo->ci = chip;
1676         brcmf_pcie_reset_device(devinfo);
1677
1678         val = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
1679         if (val != 0xffffffff)
1680                 brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
1681                                        val);
1682
1683         return 0;
1684 }
1685
1686
1687 static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1688                                         u32 rstvec)
1689 {
1690         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1691
1692         brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1693 }
1694
1695
1696 static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1697         .prepare = brcmf_pcie_buscoreprep,
1698         .reset = brcmf_pcie_buscore_reset,
1699         .activate = brcmf_pcie_buscore_activate,
1700         .read32 = brcmf_pcie_buscore_read32,
1701         .write32 = brcmf_pcie_buscore_write32,
1702 };
1703
1704 static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
1705                              void *nvram, u32 nvram_len)
1706 {
1707         struct brcmf_bus *bus = dev_get_drvdata(dev);
1708         struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
1709         struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1710         struct brcmf_commonring **flowrings;
1711         int ret;
1712         u32 i;
1713
1714         brcmf_pcie_attach(devinfo);
1715
1716         ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
1717         if (ret)
1718                 goto fail;
1719
1720         devinfo->state = BRCMFMAC_PCIE_STATE_UP;
1721
1722         ret = brcmf_pcie_init_ringbuffers(devinfo);
1723         if (ret)
1724                 goto fail;
1725
1726         ret = brcmf_pcie_init_scratchbuffers(devinfo);
1727         if (ret)
1728                 goto fail;
1729
1730         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1731         ret = brcmf_pcie_request_irq(devinfo);
1732         if (ret)
1733                 goto fail;
1734
1735         /* hook the commonrings in the bus structure. */
1736         for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
1737                 bus->msgbuf->commonrings[i] =
1738                                 &devinfo->shared.commonrings[i]->commonring;
1739
1740         flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
1741                             GFP_KERNEL);
1742         if (!flowrings)
1743                 goto fail;
1744
1745         for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
1746                 flowrings[i] = &devinfo->shared.flowrings[i].commonring;
1747         bus->msgbuf->flowrings = flowrings;
1748
1749         bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
1750         bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
1751         bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
1752
1753         init_waitqueue_head(&devinfo->mbdata_resp_wait);
1754
1755         brcmf_pcie_intr_enable(devinfo);
1756         if (brcmf_pcie_attach_bus(bus->dev) == 0)
1757                 return;
1758
1759         brcmf_pcie_bus_console_read(devinfo);
1760
1761 fail:
1762         device_release_driver(dev);
1763 }
1764
1765 static int
1766 brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1767 {
1768         int ret;
1769         struct brcmf_pciedev_info *devinfo;
1770         struct brcmf_pciedev *pcie_bus_dev;
1771         struct brcmf_bus *bus;
1772         u16 domain_nr;
1773         u16 bus_nr;
1774
1775         domain_nr = pci_domain_nr(pdev->bus) + 1;
1776         bus_nr = pdev->bus->number;
1777         brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
1778                   domain_nr, bus_nr);
1779
1780         ret = -ENOMEM;
1781         devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
1782         if (devinfo == NULL)
1783                 return ret;
1784
1785         devinfo->pdev = pdev;
1786         pcie_bus_dev = NULL;
1787         devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
1788         if (IS_ERR(devinfo->ci)) {
1789                 ret = PTR_ERR(devinfo->ci);
1790                 devinfo->ci = NULL;
1791                 goto fail;
1792         }
1793
1794         pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
1795         if (pcie_bus_dev == NULL) {
1796                 ret = -ENOMEM;
1797                 goto fail;
1798         }
1799
1800         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
1801         if (!bus) {
1802                 ret = -ENOMEM;
1803                 goto fail;
1804         }
1805         bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
1806         if (!bus->msgbuf) {
1807                 ret = -ENOMEM;
1808                 kfree(bus);
1809                 goto fail;
1810         }
1811
1812         /* hook it all together. */
1813         pcie_bus_dev->devinfo = devinfo;
1814         pcie_bus_dev->bus = bus;
1815         bus->dev = &pdev->dev;
1816         bus->bus_priv.pcie = pcie_bus_dev;
1817         bus->ops = &brcmf_pcie_bus_ops;
1818         bus->proto_type = BRCMF_PROTO_MSGBUF;
1819         bus->chip = devinfo->coreid;
1820         bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
1821         dev_set_drvdata(&pdev->dev, bus);
1822
1823         ret = brcmf_pcie_get_fwnames(devinfo);
1824         if (ret)
1825                 goto fail_bus;
1826
1827         ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
1828                                                     BRCMF_FW_REQ_NV_OPTIONAL,
1829                                           devinfo->fw_name, devinfo->nvram_name,
1830                                           brcmf_pcie_setup, domain_nr, bus_nr);
1831         if (ret == 0)
1832                 return 0;
1833 fail_bus:
1834         kfree(bus->msgbuf);
1835         kfree(bus);
1836 fail:
1837         brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
1838         brcmf_pcie_release_resource(devinfo);
1839         if (devinfo->ci)
1840                 brcmf_chip_detach(devinfo->ci);
1841         kfree(pcie_bus_dev);
1842         kfree(devinfo);
1843         return ret;
1844 }
1845
1846
1847 static void
1848 brcmf_pcie_remove(struct pci_dev *pdev)
1849 {
1850         struct brcmf_pciedev_info *devinfo;
1851         struct brcmf_bus *bus;
1852
1853         brcmf_dbg(PCIE, "Enter\n");
1854
1855         bus = dev_get_drvdata(&pdev->dev);
1856         if (bus == NULL)
1857                 return;
1858
1859         devinfo = bus->bus_priv.pcie->devinfo;
1860
1861         devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
1862         if (devinfo->ci)
1863                 brcmf_pcie_intr_disable(devinfo);
1864
1865         brcmf_detach(&pdev->dev);
1866
1867         kfree(bus->bus_priv.pcie);
1868         kfree(bus->msgbuf->flowrings);
1869         kfree(bus->msgbuf);
1870         kfree(bus);
1871
1872         brcmf_pcie_release_irq(devinfo);
1873         brcmf_pcie_release_scratchbuffers(devinfo);
1874         brcmf_pcie_release_ringbuffers(devinfo);
1875         brcmf_pcie_reset_device(devinfo);
1876         brcmf_pcie_release_resource(devinfo);
1877
1878         if (devinfo->ci)
1879                 brcmf_chip_detach(devinfo->ci);
1880
1881         kfree(devinfo);
1882         dev_set_drvdata(&pdev->dev, NULL);
1883 }
1884
1885
1886 #ifdef CONFIG_PM
1887
1888
1889 static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
1890 {
1891         struct brcmf_pciedev_info *devinfo;
1892         struct brcmf_bus *bus;
1893         int err;
1894
1895         brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
1896
1897         bus = dev_get_drvdata(&pdev->dev);
1898         devinfo = bus->bus_priv.pcie->devinfo;
1899
1900         brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
1901
1902         devinfo->mbdata_completed = false;
1903         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
1904
1905         wait_event_timeout(devinfo->mbdata_resp_wait,
1906                            devinfo->mbdata_completed,
1907                            msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
1908         if (!devinfo->mbdata_completed) {
1909                 brcmf_err("Timeout on response for entering D3 substate\n");
1910                 return -EIO;
1911         }
1912         brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
1913
1914         err = pci_save_state(pdev);
1915         if (err)
1916                 brcmf_err("pci_save_state failed, err=%d\n", err);
1917         if ((err) || (!devinfo->wowl_enabled)) {
1918                 brcmf_chip_detach(devinfo->ci);
1919                 devinfo->ci = NULL;
1920                 brcmf_pcie_remove(pdev);
1921                 return 0;
1922         }
1923
1924         return pci_prepare_to_sleep(pdev);
1925 }
1926
1927 static int brcmf_pcie_resume(struct pci_dev *pdev)
1928 {
1929         struct brcmf_pciedev_info *devinfo;
1930         struct brcmf_bus *bus;
1931         int err;
1932
1933         bus = dev_get_drvdata(&pdev->dev);
1934         brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
1935
1936         err = pci_set_power_state(pdev, PCI_D0);
1937         if (err) {
1938                 brcmf_err("pci_set_power_state failed, err=%d\n", err);
1939                 goto cleanup;
1940         }
1941         pci_restore_state(pdev);
1942         pci_enable_wake(pdev, PCI_D3hot, false);
1943         pci_enable_wake(pdev, PCI_D3cold, false);
1944
1945         /* Check if device is still up and running, if so we are ready */
1946         if (bus) {
1947                 devinfo = bus->bus_priv.pcie->devinfo;
1948                 if (brcmf_pcie_read_reg32(devinfo,
1949                                           BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
1950                         if (brcmf_pcie_send_mb_data(devinfo,
1951                                                     BRCMF_H2D_HOST_D0_INFORM))
1952                                 goto cleanup;
1953                         brcmf_dbg(PCIE, "Hot resume, continue....\n");
1954                         brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
1955                         brcmf_bus_change_state(bus, BRCMF_BUS_UP);
1956                         brcmf_pcie_intr_enable(devinfo);
1957                         return 0;
1958                 }
1959         }
1960
1961 cleanup:
1962         if (bus) {
1963                 devinfo = bus->bus_priv.pcie->devinfo;
1964                 brcmf_chip_detach(devinfo->ci);
1965                 devinfo->ci = NULL;
1966                 brcmf_pcie_remove(pdev);
1967         }
1968         err = brcmf_pcie_probe(pdev, NULL);
1969         if (err)
1970                 brcmf_err("probe after resume failed, err=%d\n", err);
1971
1972         return err;
1973 }
1974
1975
1976 #endif /* CONFIG_PM */
1977
1978
1979 #define BRCMF_PCIE_DEVICE(dev_id)       { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
1980         PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
1981
1982 static struct pci_device_id brcmf_pcie_devid_table[] = {
1983         BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID),
1984         BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
1985         BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
1986         BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
1987         BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID),
1988         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
1989         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
1990         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
1991         BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID),
1992         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID),
1993         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID),
1994         BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID),
1995         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID),
1996         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID),
1997         BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID),
1998         { /* end: all zeroes */ }
1999 };
2000
2001
2002 MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2003
2004
2005 static struct pci_driver brcmf_pciedrvr = {
2006         .node = {},
2007         .name = KBUILD_MODNAME,
2008         .id_table = brcmf_pcie_devid_table,
2009         .probe = brcmf_pcie_probe,
2010         .remove = brcmf_pcie_remove,
2011 #ifdef CONFIG_PM
2012         .suspend = brcmf_pcie_suspend,
2013         .resume = brcmf_pcie_resume
2014 #endif /* CONFIG_PM */
2015 };
2016
2017
2018 void brcmf_pcie_register(void)
2019 {
2020         int err;
2021
2022         brcmf_dbg(PCIE, "Enter\n");
2023         err = pci_register_driver(&brcmf_pciedrvr);
2024         if (err)
2025                 brcmf_err("PCIE driver registration failed, err=%d\n", err);
2026 }
2027
2028
2029 void brcmf_pcie_exit(void)
2030 {
2031         brcmf_dbg(PCIE, "Enter\n");
2032         pci_unregister_driver(&brcmf_pciedrvr);
2033 }