2 * Copyright (c) 2011 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _BRCM_AIUTILS_H_
18 #define _BRCM_AIUTILS_H_
23 * SOC Interconnect Address Map.
24 * All regions may not exist on all chips.
26 /* each core gets 4Kbytes for registers */
27 #define SI_CORE_SIZE 0x1000
29 * Max cores (this is arbitrary, for software
30 * convenience and could be changed if we
31 * make any larger chips
33 #define SI_MAXCORES 16
35 /* Client Mode sb2pcitranslation2 size in bytes */
36 #define SI_PCI_DMA_SZ 0x40000000
38 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
39 #define SI_PCIE_DMA_H32 0x80000000
41 /* chipcommon being the first core: */
44 /* SOC Interconnect types (aka chip types) */
47 /* A register that is common to all cores to
48 * communicate w/PMU regarding clock control.
50 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
52 /* clk_ctl_st register */
53 #define CCS_FORCEALP 0x00000001 /* force ALP request */
54 #define CCS_FORCEHT 0x00000002 /* force HT request */
55 #define CCS_FORCEILP 0x00000004 /* force ILP request */
56 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
57 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
58 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
59 #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
60 #define CCS_ERSRC_REQ_SHIFT 8
61 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */
62 #define CCS_HTAVAIL 0x00020000 /* HT is available */
63 #define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
64 #define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
65 #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
66 #define CCS_ERSRC_STS_SHIFT 24
68 /* HT avail in chipc and pcmcia on 4328a0 */
69 #define CCS0_HTAVAIL 0x00010000
70 /* ALP avail in chipc and pcmcia on 4328a0 */
71 #define CCS0_ALPAVAIL 0x00020000
73 /* Not really related to SOC Interconnect, but a couple of software
74 * conventions for the use the flash space:
77 /* Minumum amount of flash we support */
78 #define FLASH_MIN 0x00020000 /* Minimum flash size */
80 #define CC_SROM_OTP 0x800 /* SROM/OTP address space */
83 #define GPIO_ONTIME_SHIFT 16
85 /* Fields in clkdiv */
86 #define CLKD_OTP 0x000f0000
87 #define CLKD_OTP_SHIFT 16
90 #define BCM4717_PKG_ID 9 /* 4717 package id */
91 #define BCM4718_PKG_ID 10 /* 4718 package id */
92 #define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
94 /* these are router chips */
95 #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
96 #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
97 #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
99 /* dynamic clock control defines */
100 #define LPOMINFREQ 25000 /* low power oscillator min */
101 #define LPOMAXFREQ 43000 /* low power oscillator max */
102 #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
103 #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
104 #define PCIMINFREQ 25000000 /* 25 MHz */
105 #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
107 #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
108 #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
110 /* clkctl xtal what flags */
111 #define XTAL 0x1 /* primary crystal oscillator (2050) */
112 #define PLL 0x2 /* main chip pll */
114 /* clkctl clk mode */
115 #define CLK_FAST 0 /* force fast (pll) clock */
116 #define CLK_DYNAMIC 2 /* enable dynamic clock control */
118 /* GPIO usage priorities */
119 #define GPIO_DRV_PRIORITY 0 /* Driver */
120 #define GPIO_APP_PRIORITY 1 /* Application */
121 #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
125 /* GPIO pull up/down */
126 #define GPIO_PULLUP 0
127 #define GPIO_PULLDN 1
129 /* GPIO event regtype */
130 #define GPIO_REGEVT 0 /* GPIO register event */
131 #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
132 #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
135 #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
137 /* SI routine enumeration: to be used by update function with multiple hooks */
138 #define SI_DOATTACH 1
143 * Data structure to export all chip specific common variables
144 * public (read-only) portion of aiutils handle returned by si_attach()
147 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
148 uint buscorerev; /* buscore rev */
149 int ccrev; /* chip common core rev */
150 u32 cccaps; /* chip common capabilities */
151 int pmurev; /* pmu core rev */
152 u32 pmucaps; /* pmu capabilities */
153 uint boardtype; /* board type */
154 uint boardvendor; /* board vendor */
155 uint chip; /* chip number */
156 uint chiprev; /* chip revision */
157 uint chippkg; /* chip package option */
165 void (*handler) (u32 stat, void *arg);
167 struct gpioh_item *next;
170 /* misc si info needed by some of the routines */
172 struct si_pub pub; /* back plane public state (must be first) */
173 struct pci_dev *pbus; /* handle to pci bus */
174 uint dev_coreid; /* the core provides driver functions */
175 void *intr_arg; /* interrupt callback function arg */
176 u32 (*intrsoff_fn) (void *intr_arg); /* turns chip interrupts off */
177 /* restore chip interrupts */
178 void (*intrsrestore_fn) (void *intr_arg, u32 arg);
179 /* check if interrupts are enabled */
180 bool (*intrsenabled_fn) (void *intr_arg);
182 struct pcicore_info *pch; /* PCI/E core handle */
184 struct list_head var_list; /* list of srom variables */
186 void __iomem *curmap; /* current regs va */
187 void __iomem *regs[SI_MAXCORES]; /* other regs va */
189 u32 chipst; /* chip status */
190 uint curidx; /* current core index */
191 uint buscoreidx; /* buscore index */
192 uint numcores; /* # discovered cores */
193 uint coreid[SI_MAXCORES]; /* id of each core */
194 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
195 void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
196 u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
197 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
198 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
200 void *curwrap; /* current wrapper va */
201 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
202 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
204 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
205 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
206 u32 oob_router; /* oob router registers for axi */
210 * Many of the routines below take an 'sih' handle as their first arg.
211 * Allocate this by calling si_attach(). Free it by calling si_detach().
212 * At any one time, the sih is logically focused on one particular si core
213 * (the "current core").
214 * Use si_setcore() or si_setcoreidx() to change the association to another core
218 /* AMBA Interconnect exported externs */
219 extern uint ai_flag(struct si_pub *sih);
220 extern void ai_setint(struct si_pub *sih, int siflag);
221 extern uint ai_coreidx(struct si_pub *sih);
222 extern uint ai_corevendor(struct si_pub *sih);
223 extern uint ai_corerev(struct si_pub *sih);
224 extern bool ai_iscoreup(struct si_pub *sih);
225 extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
226 extern void ai_core_cflags_wo(struct si_pub *sih, u32 mask, u32 val);
227 extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
228 extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
230 extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
231 extern void ai_core_disable(struct si_pub *sih, u32 bits);
232 extern int ai_numaddrspaces(struct si_pub *sih);
233 extern u32 ai_addrspace(struct si_pub *sih, uint asidx);
234 extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
235 extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
237 /* === exported functions === */
238 extern struct si_pub *ai_attach(void __iomem *regs, struct pci_dev *sdh);
239 extern void ai_detach(struct si_pub *sih);
240 extern uint ai_coreid(struct si_pub *sih);
241 extern uint ai_corerev(struct si_pub *sih);
242 extern uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
244 extern void ai_write_wrapperreg(struct si_pub *sih, u32 offset, u32 val);
245 extern u32 ai_core_cflags(struct si_pub *sih, u32 mask, u32 val);
246 extern u32 ai_core_sflags(struct si_pub *sih, u32 mask, u32 val);
247 extern bool ai_iscoreup(struct si_pub *sih);
248 extern uint ai_findcoreidx(struct si_pub *sih, uint coreid, uint coreunit);
249 extern void __iomem *ai_setcoreidx(struct si_pub *sih, uint coreidx);
250 extern void __iomem *ai_setcore(struct si_pub *sih, uint coreid, uint coreunit);
251 extern void __iomem *ai_switch_core(struct si_pub *sih, uint coreid,
252 uint *origidx, uint *intr_val);
253 extern void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val);
254 extern void ai_core_reset(struct si_pub *sih, u32 bits, u32 resetbits);
255 extern void ai_core_disable(struct si_pub *sih, u32 bits);
256 extern u32 ai_alp_clock(struct si_pub *sih);
257 extern u32 ai_ilp_clock(struct si_pub *sih);
258 extern void ai_pci_setup(struct si_pub *sih, uint coremask);
259 extern void ai_setint(struct si_pub *sih, int siflag);
260 extern bool ai_backplane64(struct si_pub *sih);
261 extern void ai_register_intr_callback(struct si_pub *sih, void *intrsoff_fn,
262 void *intrsrestore_fn,
263 void *intrsenabled_fn, void *intr_arg);
264 extern void ai_deregister_intr_callback(struct si_pub *sih);
265 extern void ai_clkctl_init(struct si_pub *sih);
266 extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
267 extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
268 extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
269 extern bool ai_deviceremoved(struct si_pub *sih);
270 extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
274 extern bool ai_is_otp_disabled(struct si_pub *sih);
276 /* SPROM availability */
277 extern bool ai_is_sprom_available(struct si_pub *sih);
280 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
281 * The returned path is NULL terminated and has trailing '/'.
282 * Return 0 on success, nonzero otherwise.
284 extern int ai_devpath(struct si_pub *sih, char *path, int size);
286 extern void ai_pci_sleep(struct si_pub *sih);
287 extern void ai_pci_down(struct si_pub *sih);
288 extern void ai_pci_up(struct si_pub *sih);
289 extern int ai_pci_fixcfg(struct si_pub *sih);
291 extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
292 /* Enable Ex-PA for 4313 */
293 extern void ai_epa_4313war(struct si_pub *sih);
295 #endif /* _BRCM_AIUTILS_H_ */