2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
25 #include <chipcommon.h>
28 #include "phy/phy_hal.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
39 #include "brcms_trace_events.h"
41 /* watchdog timer, in unit of ms */
42 #define TIMER_INTERVAL_WATCHDOG 1000
43 /* radio monitor timer, in unit of ms */
44 #define TIMER_INTERVAL_RADIOCHK 800
46 /* beacon interval, in unit of 1024TU */
47 #define BEACON_INTERVAL_DEFAULT 100
49 /* n-mode support capability */
50 /* 2x2 includes both 1x1 & 2x2 devices
51 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
52 * control it independently
58 #define EDCF_ACI_MASK 0x60
59 #define EDCF_ACI_SHIFT 5
60 #define EDCF_ECWMIN_MASK 0x0f
61 #define EDCF_ECWMAX_SHIFT 4
62 #define EDCF_AIFSN_MASK 0x0f
63 #define EDCF_AIFSN_MAX 15
64 #define EDCF_ECWMAX_MASK 0xf0
66 #define EDCF_AC_BE_TXOP_STA 0x0000
67 #define EDCF_AC_BK_TXOP_STA 0x0000
68 #define EDCF_AC_VO_ACI_STA 0x62
69 #define EDCF_AC_VO_ECW_STA 0x32
70 #define EDCF_AC_VI_ACI_STA 0x42
71 #define EDCF_AC_VI_ECW_STA 0x43
72 #define EDCF_AC_BK_ECW_STA 0xA4
73 #define EDCF_AC_VI_TXOP_STA 0x005e
74 #define EDCF_AC_VO_TXOP_STA 0x002f
75 #define EDCF_AC_BE_ACI_STA 0x03
76 #define EDCF_AC_BE_ECW_STA 0xA4
77 #define EDCF_AC_BK_ACI_STA 0x27
78 #define EDCF_AC_VO_TXOP_AP 0x002f
80 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
81 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
83 #define APHY_SYMBOL_TIME 4
84 #define APHY_PREAMBLE_TIME 16
85 #define APHY_SIGNAL_TIME 4
86 #define APHY_SIFS_TIME 16
87 #define APHY_SERVICE_NBITS 16
88 #define APHY_TAIL_NBITS 6
89 #define BPHY_SIFS_TIME 10
90 #define BPHY_PLCP_SHORT_TIME 96
92 #define PREN_PREAMBLE 24
93 #define PREN_MM_EXT 12
94 #define PREN_PREAMBLE_EXT 4
96 #define DOT11_MAC_HDR_LEN 24
97 #define DOT11_ACK_LEN 10
98 #define DOT11_BA_LEN 4
99 #define DOT11_OFDM_SIGNAL_EXTENSION 6
100 #define DOT11_MIN_FRAG_LEN 256
101 #define DOT11_RTS_LEN 16
102 #define DOT11_CTS_LEN 10
103 #define DOT11_BA_BITMAP_LEN 128
104 #define DOT11_MIN_BEACON_PERIOD 1
105 #define DOT11_MAX_BEACON_PERIOD 0xFFFF
106 #define DOT11_MAXNUMFRAGS 16
107 #define DOT11_MAX_FRAG_LEN 2346
109 #define BPHY_PLCP_TIME 192
110 #define RIFS_11N_TIME 2
112 /* length of the BCN template area */
113 #define BCN_TMPL_LEN 512
115 /* brcms_bss_info flag bit values */
116 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
118 /* chip rx buffer offset */
119 #define BRCMS_HWRXOFF 38
121 /* rfdisable delay timer 500 ms, runs of ALP clock */
122 #define RFDISABLE_DEFAULT 10000000
124 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
126 /* synthpu_dly times in us */
127 #define SYNTHPU_DLY_APHY_US 3700
128 #define SYNTHPU_DLY_BPHY_US 1050
129 #define SYNTHPU_DLY_NPHY_US 2048
130 #define SYNTHPU_DLY_LPPHY_US 300
132 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
134 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
135 #define EDCF_SHORT_S 0
137 #define EDCF_LONG_S 8
138 #define EDCF_LFB_S 12
139 #define EDCF_SHORT_M BITFIELD_MASK(4)
140 #define EDCF_SFB_M BITFIELD_MASK(4)
141 #define EDCF_LONG_M BITFIELD_MASK(4)
142 #define EDCF_LFB_M BITFIELD_MASK(4)
144 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
145 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
146 #define RETRY_LONG_DEF 4 /* Default Long retry count */
147 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
148 #define RETRY_LONG_FB 2 /* Long count for fb rate */
150 #define APHY_CWMIN 15
151 #define PHY_CWMAX 1023
153 #define EDCF_AIFSN_MIN 1
155 #define FRAGNUM_MASK 0xF
157 #define APHY_SLOT_TIME 9
158 #define BPHY_SLOT_TIME 20
160 #define WL_SPURAVOID_OFF 0
161 #define WL_SPURAVOID_ON1 1
162 #define WL_SPURAVOID_ON2 2
164 /* invalid core flags, use the saved coreflags */
165 #define BRCMS_USE_COREFLAGS 0xffffffff
167 /* values for PLCPHdr_override */
168 #define BRCMS_PLCP_AUTO -1
169 #define BRCMS_PLCP_SHORT 0
170 #define BRCMS_PLCP_LONG 1
172 /* values for g_protection_override and n_protection_override */
173 #define BRCMS_PROTECTION_AUTO -1
174 #define BRCMS_PROTECTION_OFF 0
175 #define BRCMS_PROTECTION_ON 1
176 #define BRCMS_PROTECTION_MMHDR_ONLY 2
177 #define BRCMS_PROTECTION_CTS_ONLY 3
179 /* values for g_protection_control and n_protection_control */
180 #define BRCMS_PROTECTION_CTL_OFF 0
181 #define BRCMS_PROTECTION_CTL_LOCAL 1
182 #define BRCMS_PROTECTION_CTL_OVERLAP 2
184 /* values for n_protection */
185 #define BRCMS_N_PROTECTION_OFF 0
186 #define BRCMS_N_PROTECTION_OPTIONAL 1
187 #define BRCMS_N_PROTECTION_20IN40 2
188 #define BRCMS_N_PROTECTION_MIXEDMODE 3
190 /* values for band specific 40MHz capabilities */
191 #define BRCMS_N_BW_20ALL 0
192 #define BRCMS_N_BW_40ALL 1
193 #define BRCMS_N_BW_20IN2G_40IN5G 2
195 /* bitflags for SGI support (sgi_rx iovar) */
196 #define BRCMS_N_SGI_20 0x01
197 #define BRCMS_N_SGI_40 0x02
199 /* defines used by the nrate iovar */
200 /* MSC in use,indicates b0-6 holds an mcs */
201 #define NRATE_MCS_INUSE 0x00000080
203 #define NRATE_RATE_MASK 0x0000007f
204 /* stf mode mask: siso, cdd, stbc, sdm */
205 #define NRATE_STF_MASK 0x0000ff00
207 #define NRATE_STF_SHIFT 8
208 /* bit indicate to override mcs only */
209 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
210 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
211 #define NRATE_SGI_SHIFT 23 /* sgi mode */
212 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
213 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
215 #define NRATE_STF_SISO 0 /* stf mode SISO */
216 #define NRATE_STF_CDD 1 /* stf mode CDD */
217 #define NRATE_STF_STBC 2 /* stf mode STBC */
218 #define NRATE_STF_SDM 3 /* stf mode SDM */
220 #define MAX_DMA_SEGS 4
222 /* # of entries in Tx FIFO */
224 /* Max # of entries in Rx FIFO based on 4kb page size */
227 /* Amount of headroom to leave in Tx FIFO */
228 #define TX_HEADROOM 4
230 /* try to keep this # rbufs posted to the chip */
231 #define NRXBUFPOST 32
233 /* max # frames to process in brcms_c_recv() */
235 /* max # tx status to process in wlc_txstatus() */
238 /* brcmu_format_flags() bit description structure */
239 struct brcms_c_bit_desc {
245 * The following table lists the buffer memory allocated to xmt fifos in HW.
246 * the size is in units of 256bytes(one block), total size is HW dependent
247 * ucode has default fifo partition, sw can overwrite if necessary
249 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
250 * the twiki is updated before making changes.
253 /* Starting corerev for the fifo size table */
254 #define XMTFIFOTBL_STARTREV 17
262 struct edcf_acparam {
271 /* TX FIFO number to WME/802.1E Access Category */
272 static const u8 wme_fifo2ac[] = {
281 /* ieee80211 Access Category to TX FIFO number */
282 static const u8 wme_ac2fifo[] = {
289 static const u16 xmtfifo_sz[][NFIFO] = {
290 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
291 {20, 192, 192, 21, 17, 5},
296 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
297 {20, 192, 192, 21, 17, 5},
298 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
299 {9, 58, 22, 14, 14, 5},
300 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
301 {20, 192, 192, 21, 17, 5},
302 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
303 {20, 192, 192, 21, 17, 5},
304 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
305 {9, 58, 22, 14, 14, 5},
312 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
313 {9, 58, 22, 14, 14, 5},
317 static const char * const fifo_names[] = {
318 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
320 static const char fifo_names[6][0];
324 /* pointer to most recently allocated wl/wlc */
325 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
328 /* Mapping of ieee80211 AC numbers to tx fifos */
329 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
330 [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
331 [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
332 [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
333 [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
336 /* Mapping of tx fifos to ieee80211 AC numbers */
337 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
338 [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
339 [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
340 [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
341 [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
344 static u8 brcms_ac_to_fifo(u8 ac)
346 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
347 return TX_AC_BE_FIFO;
348 return ac_to_fifo_mapping[ac];
351 static u8 brcms_fifo_to_ac(u8 fifo)
353 if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
354 return IEEE80211_AC_BE;
355 return fifo_to_ac_mapping[fifo];
358 /* Find basic rate for a given rate */
359 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
361 if (is_mcs_rate(rspec))
362 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
364 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
367 static u16 frametype(u32 rspec, u8 mimoframe)
369 if (is_mcs_rate(rspec))
371 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
374 /* currently the best mechanism for determining SIFS is the band in use */
375 static u16 get_sifs(struct brcms_band *band)
377 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
382 * Detect Card removed.
383 * Even checking an sbconfig register read will not false trigger when the core
384 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
385 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
386 * reg with fixed 0/1 pattern (some platforms return all 0).
387 * If clocks are present, call the sb routine which will figure out if the
390 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
395 return ai_deviceremoved(wlc->hw->sih);
396 macctrl = bcma_read32(wlc->hw->d11core,
397 D11REGOFFS(maccontrol));
398 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
401 /* sum the individual fifo tx pending packet counts */
402 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
407 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
409 pending += dma_txpending(wlc->hw->di[i]);
413 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
415 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
418 static int brcms_chspec_bw(u16 chanspec)
420 if (CHSPEC_IS40(chanspec))
422 if (CHSPEC_IS20(chanspec))
428 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
433 kfree(cfg->current_bss);
437 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
442 brcms_c_bsscfg_mfree(wlc->bsscfg);
444 kfree(wlc->modulecb);
445 kfree(wlc->default_bss);
446 kfree(wlc->protection);
448 kfree(wlc->bandstate[0]);
449 kfree(wlc->corestate->macstat_snapshot);
450 kfree(wlc->corestate);
451 kfree(wlc->hw->bandstate[0]);
459 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
461 struct brcms_bss_cfg *cfg;
463 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
467 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
468 if (cfg->current_bss == NULL)
474 brcms_c_bsscfg_mfree(cfg);
478 static struct brcms_c_info *
479 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
481 struct brcms_c_info *wlc;
483 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
489 /* allocate struct brcms_c_pub state structure */
490 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
491 if (wlc->pub == NULL) {
497 /* allocate struct brcms_hardware state structure */
499 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
500 if (wlc->hw == NULL) {
506 wlc->hw->bandstate[0] =
507 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
508 if (wlc->hw->bandstate[0] == NULL) {
514 for (i = 1; i < MAXBANDS; i++)
515 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
516 ((unsigned long)wlc->hw->bandstate[0] +
517 (sizeof(struct brcms_hw_band) * i));
521 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
522 if (wlc->modulecb == NULL) {
527 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
528 if (wlc->default_bss == NULL) {
533 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
534 if (wlc->bsscfg == NULL) {
539 wlc->protection = kzalloc(sizeof(struct brcms_protection),
541 if (wlc->protection == NULL) {
546 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
547 if (wlc->stf == NULL) {
553 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
554 if (wlc->bandstate[0] == NULL) {
560 for (i = 1; i < MAXBANDS; i++)
561 wlc->bandstate[i] = (struct brcms_band *)
562 ((unsigned long)wlc->bandstate[0]
563 + (sizeof(struct brcms_band)*i));
566 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
567 if (wlc->corestate == NULL) {
572 wlc->corestate->macstat_snapshot =
573 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
574 if (wlc->corestate->macstat_snapshot == NULL) {
582 brcms_c_detach_mfree(wlc);
587 * Update the slot timing for standard 11b/g (20us slots)
588 * or shortslot 11g (9us slots)
589 * The PSM needs to be suspended for this call.
591 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
594 struct bcma_device *core = wlc_hw->d11core;
597 /* 11g short slot: 11a timing */
598 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
599 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
601 /* 11g long slot: 11b timing */
602 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
603 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
608 * calculate frame duration of a given rate and length, return
611 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
612 u8 preamble_type, uint mac_len)
614 uint nsyms, dur = 0, Ndps, kNdps;
615 uint rate = rspec2rate(ratespec);
618 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
623 if (is_mcs_rate(ratespec)) {
624 uint mcs = ratespec & RSPEC_RATE_MASK;
625 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
627 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
628 if (preamble_type == BRCMS_MM_PREAMBLE)
630 /* 1000Ndbps = kbps * 4 */
631 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
632 rspec_issgi(ratespec)) * 4;
634 if (rspec_stc(ratespec) == 0)
636 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
637 APHY_TAIL_NBITS) * 1000, kNdps);
639 /* STBC needs to have even number of symbols */
642 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
643 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
645 dur += APHY_SYMBOL_TIME * nsyms;
646 if (wlc->band->bandtype == BRCM_BAND_2G)
647 dur += DOT11_OFDM_SIGNAL_EXTENSION;
648 } else if (is_ofdm_rate(rate)) {
649 dur = APHY_PREAMBLE_TIME;
650 dur += APHY_SIGNAL_TIME;
651 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
653 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
655 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
657 dur += APHY_SYMBOL_TIME * nsyms;
658 if (wlc->band->bandtype == BRCM_BAND_2G)
659 dur += DOT11_OFDM_SIGNAL_EXTENSION;
662 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
665 mac_len = mac_len * 8 * 2;
666 /* calc ceiling of bits/rate = microseconds of air time */
667 dur = (mac_len + rate - 1) / rate;
668 if (preamble_type & BRCMS_SHORT_PREAMBLE)
669 dur += BPHY_PLCP_SHORT_TIME;
671 dur += BPHY_PLCP_TIME;
676 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
677 const struct d11init *inits)
679 struct bcma_device *core = wlc_hw->d11core;
685 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
687 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
688 size = le16_to_cpu(inits[i].size);
689 offset = le16_to_cpu(inits[i].addr);
690 value = le32_to_cpu(inits[i].value);
692 bcma_write16(core, offset, value);
694 bcma_write32(core, offset, value);
700 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
704 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
708 for (idx = 0; idx < MHFMAX; idx++)
709 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
712 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
714 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
716 /* init microcode host flags */
717 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
719 /* do band-specific ucode IHR, SHM, and SCR inits */
720 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
721 if (BRCMS_ISNPHY(wlc_hw->band))
722 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
724 brcms_err(wlc_hw->d11core,
725 "%s: wl%d: unsupported phy in corerev %d\n",
726 __func__, wlc_hw->unit,
729 if (D11REV_IS(wlc_hw->corerev, 24)) {
730 if (BRCMS_ISLCNPHY(wlc_hw->band))
731 brcms_c_write_inits(wlc_hw,
732 ucode->d11lcn0bsinitvals24);
734 brcms_err(wlc_hw->d11core,
735 "%s: wl%d: unsupported phy in core rev %d\n",
736 __func__, wlc_hw->unit,
739 brcms_err(wlc_hw->d11core,
740 "%s: wl%d: unsupported corerev %d\n",
741 __func__, wlc_hw->unit, wlc_hw->corerev);
746 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
748 struct bcma_device *core = wlc_hw->d11core;
749 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
751 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
754 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
756 brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
758 wlc_hw->phyclk = clk;
760 if (OFF == clk) { /* clear gmode bit, put phy into reset */
762 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
763 (SICF_PRST | SICF_FGC));
765 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
768 } else { /* take phy out of reset */
770 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
772 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
778 /* low-level band switch utility routine */
779 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
781 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
784 wlc_hw->band = wlc_hw->bandstate[bandunit];
788 * until we eliminate need for wlc->band refs in low level code
790 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
792 /* set gmode core flag */
793 if (wlc_hw->sbclk && !wlc_hw->noreset) {
799 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
803 /* switch to new band but leave it inactive */
804 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
806 struct brcms_hardware *wlc_hw = wlc->hw;
810 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
811 macctrl = bcma_read32(wlc_hw->d11core,
812 D11REGOFFS(maccontrol));
813 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
815 /* disable interrupts */
816 macintmask = brcms_intrsoff(wlc->wl);
819 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
821 brcms_b_core_phy_clk(wlc_hw, OFF);
823 brcms_c_setxband(wlc_hw, bandunit);
828 /* process an individual struct tx_status */
830 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
832 struct sk_buff *p = NULL;
834 struct dma_pub *dma = NULL;
835 struct d11txh *txh = NULL;
836 struct scb *scb = NULL;
838 int tx_rts, tx_frame_count, tx_rts_count;
839 uint totlen, supr_status;
841 struct ieee80211_hdr *h;
843 struct ieee80211_tx_info *tx_info;
844 struct ieee80211_tx_rate *txrate;
848 trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
849 txs->frameid, txs->status, txs->lasttxtime,
850 txs->sequence, txs->phyerr, txs->ackphyrxsh);
852 /* discard intermediate indications for ucode with one legitimate case:
853 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
854 * but the subsequent tx of DATA failed. so it will start rts/cts
855 * from the beginning (resetting the rts transmission count)
857 if (!(txs->status & TX_STATUS_AMPDU)
858 && (txs->status & TX_STATUS_INTERMEDIATE)) {
859 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
864 queue = txs->frameid & TXFID_QUEUE_MASK;
865 if (queue >= NFIFO) {
866 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
870 dma = wlc->hw->di[queue];
872 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
874 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
878 txh = (struct d11txh *) (p->data);
879 mcl = le16_to_cpu(txh->MacTxControlLow);
882 brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
883 txs->phyerr, txh->MainRates);
885 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
886 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
889 tx_info = IEEE80211_SKB_CB(p);
890 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
892 if (tx_info->rate_driver_data[0])
895 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
896 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
902 * brcms_c_ampdu_dotxstatus() will trace tx descriptors for AMPDU
903 * frames; this traces them for the rest.
905 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
907 supr_status = txs->status & TX_STATUS_SUPR_MASK;
908 if (supr_status == TX_STATUS_SUPR_BADCH) {
909 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
910 brcms_dbg_tx(wlc->hw->d11core,
911 "Pkt tx suppressed, dest chan %u, current %d\n",
912 (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
913 CHSPEC_CHANNEL(wlc->default_bss->chanspec));
916 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
918 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
920 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
922 lastframe = !ieee80211_has_morefrags(h->frame_control);
925 brcms_err(wlc->hw->d11core, "Not last frame!\n");
928 * Set information to be consumed by Minstrel ht.
930 * The "fallback limit" is the number of tx attempts a given
931 * MPDU is sent at the "primary" rate. Tx attempts beyond that
932 * limit are sent at the "secondary" rate.
933 * A 'short frame' does not exceed RTS treshold.
935 u16 sfbl, /* Short Frame Rate Fallback Limit */
936 lfbl, /* Long Frame Rate Fallback Limit */
939 if (queue < IEEE80211_NUM_ACS) {
940 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
942 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
949 txrate = tx_info->status.rates;
950 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
955 ieee80211_tx_info_clear_status(tx_info);
957 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
959 * rate selection requested a fallback rate
962 txrate[0].count = fbl;
963 txrate[1].count = tx_frame_count - fbl;
966 * rate selection did not request fallback rate, or
969 txrate[0].count = tx_frame_count;
971 * rc80211_minstrel.c:minstrel_tx_status() expects
972 * unused rates to be marked with idx = -1
978 /* clear the rest of the rates */
979 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
984 if (txs->status & TX_STATUS_ACK_RCV)
985 tx_info->flags |= IEEE80211_TX_STAT_ACK;
992 /* remove PLCP & Broadcom tx descriptor header */
993 skb_pull(p, D11_PHY_HDR_LEN);
994 skb_pull(p, D11_TXH_LEN);
995 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
997 brcms_err(wlc->hw->d11core,
998 "%s: Not last frame => not calling tx_status\n",
1007 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1010 brcmu_pkt_buf_free_skb(p);
1013 if (dma && queue < NFIFO) {
1014 u16 ac_queue = brcms_fifo_to_ac(queue);
1015 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1016 ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1017 ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1024 /* process tx completion events in BMAC
1025 * Return true if more tx status need to be processed. false otherwise.
1028 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1030 bool morepending = false;
1031 struct bcma_device *core;
1032 struct tx_status txstatus, *txs;
1036 * Param 'max_tx_num' indicates max. # tx status to process before
1039 uint max_tx_num = bound ? TXSBND : -1;
1042 core = wlc_hw->d11core;
1044 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1047 /* !give others some time to run! */
1048 if (n >= max_tx_num) {
1053 if (s1 == 0xffffffff) {
1054 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1059 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1061 txs->status = s1 & TXS_STATUS_MASK;
1062 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1063 txs->sequence = s2 & TXS_SEQ_MASK;
1064 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1065 txs->lasttxtime = 0;
1067 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1069 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1079 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1081 if (!wlc->bsscfg->BSS)
1083 * DirFrmQ is now valid...defer setting until end
1086 wlc->qvalid |= MCMD_DIRFRMQVAL;
1089 /* set initial host flags value */
1091 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1093 struct brcms_hardware *wlc_hw = wlc->hw;
1095 memset(mhfs, 0, MHFMAX * sizeof(u16));
1097 mhfs[MHF2] |= mhf2_init;
1099 /* prohibit use of slowclock on multifunction boards */
1100 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1101 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1103 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1104 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1105 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1110 dmareg(uint direction, uint fifonum)
1112 if (direction == DMA_TX)
1113 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1114 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1117 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1122 * ucode host flag 2 needed for pio mode, independent of band and fifo
1125 struct brcms_hardware *wlc_hw = wlc->hw;
1126 uint unit = wlc_hw->unit;
1128 /* name and offsets for dma_attach */
1129 snprintf(name, sizeof(name), "wl%d", unit);
1131 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1132 int dma_attach_err = 0;
1136 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1137 * RX: RX_FIFO (RX data packets)
1139 wlc_hw->di[0] = dma_attach(name, wlc,
1140 (wme ? dmareg(DMA_TX, 0) : 0),
1142 (wme ? NTXD : 0), NRXD,
1143 RXBUFSZ, -1, NRXBUFPOST,
1145 dma_attach_err |= (NULL == wlc_hw->di[0]);
1149 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1150 * (legacy) TX_DATA_FIFO (TX data packets)
1153 wlc_hw->di[1] = dma_attach(name, wlc,
1154 dmareg(DMA_TX, 1), 0,
1155 NTXD, 0, 0, -1, 0, 0);
1156 dma_attach_err |= (NULL == wlc_hw->di[1]);
1160 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1163 wlc_hw->di[2] = dma_attach(name, wlc,
1164 dmareg(DMA_TX, 2), 0,
1165 NTXD, 0, 0, -1, 0, 0);
1166 dma_attach_err |= (NULL == wlc_hw->di[2]);
1169 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1170 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1172 wlc_hw->di[3] = dma_attach(name, wlc,
1176 dma_attach_err |= (NULL == wlc_hw->di[3]);
1177 /* Cleaner to leave this as if with AP defined */
1179 if (dma_attach_err) {
1180 brcms_err(wlc_hw->d11core,
1181 "wl%d: wlc_attach: dma_attach failed\n",
1186 /* get pointer to dma engine tx flow control variable */
1187 for (i = 0; i < NFIFO; i++)
1189 wlc_hw->txavail[i] =
1190 (uint *) dma_getvar(wlc_hw->di[i],
1194 /* initial ucode host flags */
1195 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1200 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1204 for (j = 0; j < NFIFO; j++) {
1205 if (wlc_hw->di[j]) {
1206 dma_detach(wlc_hw->di[j]);
1207 wlc_hw->di[j] = NULL;
1213 * Initialize brcms_c_info default values ...
1214 * may get overrides later in this function
1215 * BMAC_NOTES, move low out and resolve the dangling ones
1217 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1219 struct brcms_c_info *wlc = wlc_hw->wlc;
1221 /* set default sw macintmask value */
1222 wlc->defmacintmask = DEF_MACINTMASK;
1224 /* various 802.11g modes */
1225 wlc_hw->shortslot = false;
1227 wlc_hw->SFBL = RETRY_SHORT_FB;
1228 wlc_hw->LFBL = RETRY_LONG_FB;
1230 /* default mac retry limits */
1231 wlc_hw->SRL = RETRY_SHORT_DEF;
1232 wlc_hw->LRL = RETRY_LONG_DEF;
1233 wlc_hw->chanspec = ch20mhz_chspec(1);
1236 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1238 /* delay before first read of ucode state */
1241 /* wait until ucode is no longer asleep */
1242 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1243 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1246 /* control chip clock to save power, enable dynamic clock or force fast clock */
1247 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1249 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1250 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1251 * on backplane, but mac core will still run on ALP(not HT) when
1252 * it enters powersave mode, which means the FCA bit may not be
1253 * set. Should wakeup mac if driver wants it to run on HT.
1257 if (mode == BCMA_CLKMODE_FAST) {
1258 bcma_set32(wlc_hw->d11core,
1259 D11REGOFFS(clk_ctl_st),
1265 ((bcma_read32(wlc_hw->d11core,
1266 D11REGOFFS(clk_ctl_st)) &
1268 PMU_MAX_TRANSITION_DLY);
1269 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1270 D11REGOFFS(clk_ctl_st)) &
1273 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1274 (bcma_read32(wlc_hw->d11core,
1275 D11REGOFFS(clk_ctl_st)) &
1276 (CCS_FORCEHT | CCS_HTAREQ)))
1278 ((bcma_read32(wlc_hw->d11core,
1279 offsetof(struct d11regs,
1282 PMU_MAX_TRANSITION_DLY);
1283 bcma_mask32(wlc_hw->d11core,
1284 D11REGOFFS(clk_ctl_st),
1288 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1291 /* old chips w/o PMU, force HT through cc,
1292 * then use FCA to verify mac is running fast clock
1295 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1297 /* check fast clock is available (if core is not in reset) */
1298 if (wlc_hw->forcefastclk && wlc_hw->clk)
1299 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1303 * keep the ucode wake bit on if forcefastclk is on since we
1304 * do not want ucode to put us back to slow clock when it dozes
1305 * for PM mode. Code below matches the wake override bit with
1306 * current forcefastclk state. Only setting bit in wake_override
1307 * instead of waking ucode immediately since old code had this
1308 * behavior. Older code set wlc->forcefastclk but only had the
1309 * wake happen if the wakup_ucode work (protected by an up
1310 * check) was executed just below.
1312 if (wlc_hw->forcefastclk)
1313 mboolset(wlc_hw->wake_override,
1314 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1316 mboolclr(wlc_hw->wake_override,
1317 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1321 /* set or clear ucode host flag bits
1322 * it has an optimization for no-change write
1323 * it only writes through shared memory when the core has clock;
1324 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1327 * bands values are: BRCM_BAND_AUTO <--- Current band only
1328 * BRCM_BAND_5G <--- 5G band only
1329 * BRCM_BAND_2G <--- 2G band only
1330 * BRCM_BAND_ALL <--- All bands
1333 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1337 u16 addr[MHFMAX] = {
1338 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1341 struct brcms_hw_band *band;
1343 if ((val & ~mask) || idx >= MHFMAX)
1344 return; /* error condition */
1347 /* Current band only or all bands,
1348 * then set the band to current band
1350 case BRCM_BAND_AUTO:
1352 band = wlc_hw->band;
1355 band = wlc_hw->bandstate[BAND_5G_INDEX];
1358 band = wlc_hw->bandstate[BAND_2G_INDEX];
1361 band = NULL; /* error condition */
1365 save = band->mhfs[idx];
1366 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1368 /* optimization: only write through if changed, and
1369 * changed band is the current band
1371 if (wlc_hw->clk && (band->mhfs[idx] != save)
1372 && (band == wlc_hw->band))
1373 brcms_b_write_shm(wlc_hw, addr[idx],
1374 (u16) band->mhfs[idx]);
1377 if (bands == BRCM_BAND_ALL) {
1378 wlc_hw->bandstate[0]->mhfs[idx] =
1379 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1380 wlc_hw->bandstate[1]->mhfs[idx] =
1381 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1385 /* set the maccontrol register to desired reset state and
1386 * initialize the sw cache of the register
1388 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1390 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1391 wlc_hw->maccontrol = 0;
1392 wlc_hw->suspended_fifos = 0;
1393 wlc_hw->wake_override = 0;
1394 wlc_hw->mute_override = 0;
1395 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1399 * write the software state of maccontrol and
1400 * overrides to the maccontrol register
1402 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1404 u32 maccontrol = wlc_hw->maccontrol;
1406 /* OR in the wake bit if overridden */
1407 if (wlc_hw->wake_override)
1408 maccontrol |= MCTL_WAKE;
1410 /* set AP and INFRA bits for mute if needed */
1411 if (wlc_hw->mute_override) {
1412 maccontrol &= ~(MCTL_AP);
1413 maccontrol |= MCTL_INFRA;
1416 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1420 /* set or clear maccontrol bits */
1421 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1427 return; /* error condition */
1428 maccontrol = wlc_hw->maccontrol;
1429 new_maccontrol = (maccontrol & ~mask) | val;
1431 /* if the new maccontrol value is the same as the old, nothing to do */
1432 if (new_maccontrol == maccontrol)
1435 /* something changed, cache the new value */
1436 wlc_hw->maccontrol = new_maccontrol;
1438 /* write the new values with overrides applied */
1439 brcms_c_mctrl_write(wlc_hw);
1442 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1445 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1446 mboolset(wlc_hw->wake_override, override_bit);
1450 mboolset(wlc_hw->wake_override, override_bit);
1452 brcms_c_mctrl_write(wlc_hw);
1453 brcms_b_wait_for_wake(wlc_hw);
1456 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1459 mboolclr(wlc_hw->wake_override, override_bit);
1461 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1464 brcms_c_mctrl_write(wlc_hw);
1467 /* When driver needs ucode to stop beaconing, it has to make sure that
1468 * MCTL_AP is clear and MCTL_INFRA is set
1469 * Mode MCTL_AP MCTL_INFRA
1471 * STA 0 1 <--- This will ensure no beacons
1474 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1476 wlc_hw->mute_override = 1;
1478 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1479 * override, then there is no change to write
1481 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1484 brcms_c_mctrl_write(wlc_hw);
1487 /* Clear the override on AP and INFRA bits */
1488 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1490 if (wlc_hw->mute_override == 0)
1493 wlc_hw->mute_override = 0;
1495 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1496 * override, then there is no change to write
1498 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1501 brcms_c_mctrl_write(wlc_hw);
1505 * Write a MAC address to the given match reg offset in the RXE match engine.
1508 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1511 struct bcma_device *core = wlc_hw->d11core;
1516 brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1518 mac_l = addr[0] | (addr[1] << 8);
1519 mac_m = addr[2] | (addr[3] << 8);
1520 mac_h = addr[4] | (addr[5] << 8);
1522 /* enter the MAC addr into the RXE match registers */
1523 bcma_write16(core, D11REGOFFS(rcm_ctl),
1524 RCM_INC_DATA | match_reg_offset);
1525 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1526 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1527 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1531 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1534 struct bcma_device *core = wlc_hw->d11core;
1539 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1541 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1543 /* if MCTL_BIGEND bit set in mac control register,
1544 * the chip swaps data in fifo, as well as data in
1547 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1550 memcpy(&word, buf, sizeof(u32));
1553 word_be = cpu_to_be32(word);
1554 word = *(u32 *)&word_be;
1556 word_le = cpu_to_le32(word);
1557 word = *(u32 *)&word_le;
1560 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1562 buf = (u8 *) buf + sizeof(u32);
1567 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1569 wlc_hw->band->CWmin = newmin;
1571 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1572 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1573 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1574 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1577 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1579 wlc_hw->band->CWmax = newmax;
1581 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1582 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1583 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1584 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1587 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1591 /* request FAST clock if not on */
1592 fastclk = wlc_hw->forcefastclk;
1594 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1596 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1598 brcms_b_phy_reset(wlc_hw);
1599 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1601 /* restore the clk */
1603 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1606 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1609 struct brcms_c_info *wlc = wlc_hw->wlc;
1610 /* update SYNTHPU_DLY */
1612 if (BRCMS_ISLCNPHY(wlc->band))
1613 v = SYNTHPU_DLY_LPPHY_US;
1614 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1615 v = SYNTHPU_DLY_NPHY_US;
1617 v = SYNTHPU_DLY_BPHY_US;
1619 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1622 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1625 u16 phytxant = wlc_hw->bmac_phytxant;
1626 u16 mask = PHY_TXC_ANT_MASK;
1628 /* set the Probe Response frame phy control word */
1629 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1630 phyctl = (phyctl & ~mask) | phytxant;
1631 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1633 /* set the Response (ACK/CTS) frame phy control word */
1634 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1635 phyctl = (phyctl & ~mask) | phytxant;
1636 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1639 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1644 struct plcp_signal_rate_lookup {
1648 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1649 const struct plcp_signal_rate_lookup rate_lookup[] = {
1650 {BRCM_RATE_6M, 0xB},
1651 {BRCM_RATE_9M, 0xF},
1652 {BRCM_RATE_12M, 0xA},
1653 {BRCM_RATE_18M, 0xE},
1654 {BRCM_RATE_24M, 0x9},
1655 {BRCM_RATE_36M, 0xD},
1656 {BRCM_RATE_48M, 0x8},
1657 {BRCM_RATE_54M, 0xC}
1660 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1661 if (rate == rate_lookup[i].rate) {
1662 plcp_rate = rate_lookup[i].signal_rate;
1667 /* Find the SHM pointer to the rate table entry by looking in the
1670 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1673 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1677 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1678 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1684 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1687 /* walk the phy rate table and update the entries */
1688 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1691 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1693 /* read the SHM Rate Table entry OFDM PCTL1 values */
1695 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1697 /* modify the value */
1698 pctl1 &= ~PHY_TXC1_MODE_MASK;
1699 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1701 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1702 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1707 /* band-specific init */
1708 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1710 struct brcms_hardware *wlc_hw = wlc->hw;
1712 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1713 wlc_hw->band->bandunit);
1715 brcms_c_ucode_bsinit(wlc_hw);
1717 wlc_phy_init(wlc_hw->band->pi, chanspec);
1719 brcms_c_ucode_txant_set(wlc_hw);
1722 * cwmin is band-specific, update hardware
1723 * with value for current band
1725 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1726 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1728 brcms_b_update_slot_timing(wlc_hw,
1729 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1730 true : wlc_hw->shortslot);
1732 /* write phytype and phyvers */
1733 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1734 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1737 * initialize the txphyctl1 rate table since
1738 * shmem is shared between bands
1740 brcms_upd_ofdm_pctl1_table(wlc_hw);
1742 brcms_b_upd_synthpu(wlc_hw);
1745 /* Perform a soft reset of the PHY PLL */
1746 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1748 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1751 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1754 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1757 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1762 /* light way to turn on phy clock without reset for NPHY only
1763 * refer to brcms_b_core_phy_clk for full version
1765 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1767 /* support(necessary for NPHY and HYPHY) only */
1768 if (!BRCMS_ISNPHY(wlc_hw->band))
1772 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1774 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1778 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1781 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1783 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1786 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1788 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1790 bool phy_in_reset = false;
1792 brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1797 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1799 /* Specific reset sequence required for NPHY rev 3 and 4 */
1800 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1801 NREV_LE(wlc_hw->band->phyrev, 4)) {
1802 /* Set the PHY bandwidth */
1803 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1807 /* Perform a soft reset of the PHY PLL */
1808 brcms_b_core_phypll_reset(wlc_hw);
1811 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1812 (SICF_PRST | SICF_PCLKE));
1813 phy_in_reset = true;
1815 brcms_b_core_ioctl(wlc_hw,
1816 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1817 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1821 brcms_b_core_phy_clk(wlc_hw, ON);
1824 wlc_phy_anacore(pih, ON);
1827 /* switch to and initialize new band */
1828 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1830 struct brcms_c_info *wlc = wlc_hw->wlc;
1833 /* Enable the d11 core before accessing it */
1834 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1835 bcma_core_enable(wlc_hw->d11core, 0);
1836 brcms_c_mctrl_reset(wlc_hw);
1839 macintmask = brcms_c_setband_inact(wlc, bandunit);
1844 brcms_b_core_phy_clk(wlc_hw, ON);
1846 /* band-specific initializations */
1847 brcms_b_bsinit(wlc, chanspec);
1850 * If there are any pending software interrupt bits,
1851 * then replace these with a harmless nonzero value
1852 * so brcms_c_dpc() will re-enable interrupts when done.
1854 if (wlc->macintstatus)
1855 wlc->macintstatus = MI_DMAINT;
1857 /* restore macintmask */
1858 brcms_intrsrestore(wlc->wl, macintmask);
1860 /* ucode should still be suspended.. */
1861 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1865 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1868 /* reject unsupported corerev */
1869 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1870 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1878 /* Validate some board info parameters */
1879 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1881 uint boardrev = wlc_hw->boardrev;
1883 /* 4 bits each for board type, major, minor, and tiny version */
1884 uint brt = (boardrev & 0xf000) >> 12;
1885 uint b0 = (boardrev & 0xf00) >> 8;
1886 uint b1 = (boardrev & 0xf0) >> 4;
1887 uint b2 = boardrev & 0xf;
1889 /* voards from other vendors are always considered valid */
1890 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1893 /* do some boardrev sanity checks when boardvendor is Broadcom */
1897 if (boardrev <= 0xff)
1900 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1907 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1909 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1911 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1912 if (!is_zero_ether_addr(sprom->il0mac)) {
1913 memcpy(etheraddr, sprom->il0mac, 6);
1917 if (wlc_hw->_nbands > 1)
1918 memcpy(etheraddr, sprom->et1mac, 6);
1920 memcpy(etheraddr, sprom->il0mac, 6);
1923 /* power both the pll and external oscillator on/off */
1924 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1926 brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1929 * dont power down if plldown is false or
1930 * we must poll hw radio disable
1932 if (!want && wlc_hw->pllreq)
1935 wlc_hw->sbclk = want;
1936 if (!wlc_hw->sbclk) {
1937 wlc_hw->clk = false;
1938 if (wlc_hw->band && wlc_hw->band->pi)
1939 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1944 * Return true if radio is disabled, otherwise false.
1945 * hw radio disable signal is an external pin, users activate it asynchronously
1946 * this function could be called when driver is down and w/o clock
1947 * it operates on different registers depending on corerev and boardflag.
1949 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1954 xtal = wlc_hw->sbclk;
1956 brcms_b_xtal(wlc_hw, ON);
1958 /* may need to take core out of reset first */
1962 * mac no longer enables phyclk automatically when driver
1963 * accesses phyreg throughput mac. This can be skipped since
1964 * only mac reg is accessed below
1966 if (D11REV_GE(wlc_hw->corerev, 18))
1967 flags |= SICF_PCLKE;
1970 * TODO: test suspend/resume
1972 * AI chip doesn't restore bar0win2 on
1973 * hibernation/resume, need sw fixup
1976 bcma_core_enable(wlc_hw->d11core, flags);
1977 brcms_c_mctrl_reset(wlc_hw);
1980 v = ((bcma_read32(wlc_hw->d11core,
1981 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1983 /* put core back into reset */
1985 bcma_core_disable(wlc_hw->d11core, 0);
1988 brcms_b_xtal(wlc_hw, OFF);
1993 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1995 struct dma_pub *di = wlc_hw->di[fifo];
1996 return dma_rxreset(di);
2000 * ensure fask clock during reset
2002 * reset d11(out of reset)
2003 * reset phy(out of reset)
2004 * clear software macintstatus for fresh new start
2005 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2007 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2012 if (flags == BRCMS_USE_COREFLAGS)
2013 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2015 brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2017 /* request FAST clock if not on */
2018 fastclk = wlc_hw->forcefastclk;
2020 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2022 /* reset the dma engines except first time thru */
2023 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2024 for (i = 0; i < NFIFO; i++)
2025 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2026 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2027 "dma_txreset[%d]: cannot stop dma\n",
2028 wlc_hw->unit, __func__, i);
2030 if ((wlc_hw->di[RX_FIFO])
2031 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2032 brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2033 "[%d]: cannot stop dma\n",
2034 wlc_hw->unit, __func__, RX_FIFO);
2036 /* if noreset, just stop the psm and return */
2037 if (wlc_hw->noreset) {
2038 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2039 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2044 * mac no longer enables phyclk automatically when driver accesses
2045 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2046 * band->pi is invalid. need to enable PHY CLK
2048 if (D11REV_GE(wlc_hw->corerev, 18))
2049 flags |= SICF_PCLKE;
2053 * In chips with PMU, the fastclk request goes through d11 core
2054 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2056 * This adds some delay and we can optimize it by also requesting
2057 * fastclk through chipcommon during this period if necessary. But
2058 * that has to work coordinate with other driver like mips/arm since
2059 * they may touch chipcommon as well.
2061 wlc_hw->clk = false;
2062 bcma_core_enable(wlc_hw->d11core, flags);
2064 if (wlc_hw->band && wlc_hw->band->pi)
2065 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2067 brcms_c_mctrl_reset(wlc_hw);
2069 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2070 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2072 brcms_b_phy_reset(wlc_hw);
2074 /* turn on PHY_PLL */
2075 brcms_b_core_phypll_ctl(wlc_hw, true);
2077 /* clear sw intstatus */
2078 wlc_hw->wlc->macintstatus = 0;
2080 /* restore the clk setting */
2082 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2085 /* txfifo sizes needs to be modified(increased) since the newer cores
2088 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2090 struct bcma_device *core = wlc_hw->d11core;
2092 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2093 u16 txfifo_def, txfifo_def1;
2096 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2097 txfifo_startblk = TXFIFO_START_BLK;
2099 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2100 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2102 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2103 txfifo_def = (txfifo_startblk & 0xff) |
2104 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2105 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2107 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2109 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2111 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2112 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2113 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2115 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2117 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2120 * need to propagate to shm location to be in sync since ucode/hw won't
2123 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2124 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2125 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2126 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2127 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2128 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2129 xmtfifo_sz[TX_AC_BK_FIFO]));
2130 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2131 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2132 xmtfifo_sz[TX_BCMC_FIFO]));
2135 /* This function is used for changing the tsf frac register
2136 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2137 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2138 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2139 * HTPHY Formula is 2^26/freq(MHz) e.g.
2140 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2141 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2142 * For spuron: 123MHz -> 2^26/123 = 545600.5
2143 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2144 * For spur off: 120MHz -> 2^26/120 = 559240.5
2145 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2148 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2150 struct bcma_device *core = wlc_hw->d11core;
2152 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2153 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2154 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2155 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2156 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2157 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2158 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2159 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2160 } else { /* 120Mhz */
2161 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2162 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2164 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2165 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2166 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2167 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2168 } else { /* 80Mhz */
2169 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2170 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2175 /* Initialize GPIOs that are controlled by D11 core */
2176 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2178 struct brcms_hardware *wlc_hw = wlc->hw;
2181 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2182 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2185 * Common GPIO setup:
2186 * G0 = LED 0 = WLAN Activity
2187 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2188 * G2 = LED 2 = WLAN 5 GHz Radio State
2189 * G4 = radio disable input (HI enabled, LO disabled)
2194 /* Allocate GPIOs for mimo antenna diversity feature */
2195 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2196 /* Enable antenna diversity, use 2x3 mode */
2197 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2198 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2199 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2200 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2202 /* init superswitch control */
2203 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2205 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2206 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2208 * The board itself is powered by these GPIOs
2209 * (when not sending pattern) so set them high
2211 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2212 (BOARD_GPIO_12 | BOARD_GPIO_13));
2213 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2214 (BOARD_GPIO_12 | BOARD_GPIO_13));
2216 /* Enable antenna diversity, use 2x4 mode */
2217 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2218 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2219 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2222 /* Configure the desired clock to be 4Mhz */
2223 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2224 ANTSEL_CLKDIV_4MHZ);
2228 * gpio 9 controls the PA. ucode is responsible
2229 * for wiggling out and oe
2231 if (wlc_hw->boardflags & BFL_PACTRL)
2232 gm |= gc |= BOARD_GPIO_PACTRL;
2234 /* apply to gpiocontrol register */
2235 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2238 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2239 const __le32 ucode[], const size_t nbytes)
2241 struct bcma_device *core = wlc_hw->d11core;
2245 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2247 count = (nbytes / sizeof(u32));
2249 bcma_write32(core, D11REGOFFS(objaddr),
2250 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2251 (void)bcma_read32(core, D11REGOFFS(objaddr));
2252 for (i = 0; i < count; i++)
2253 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2257 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2259 struct brcms_c_info *wlc;
2260 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2264 if (wlc_hw->ucode_loaded)
2267 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2268 if (BRCMS_ISNPHY(wlc_hw->band)) {
2269 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2270 ucode->bcm43xx_16_mimosz);
2271 wlc_hw->ucode_loaded = true;
2273 brcms_err(wlc_hw->d11core,
2274 "%s: wl%d: unsupported phy in corerev %d\n",
2275 __func__, wlc_hw->unit, wlc_hw->corerev);
2276 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2277 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2278 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2279 ucode->bcm43xx_24_lcnsz);
2280 wlc_hw->ucode_loaded = true;
2282 brcms_err(wlc_hw->d11core,
2283 "%s: wl%d: unsupported phy in corerev %d\n",
2284 __func__, wlc_hw->unit, wlc_hw->corerev);
2289 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2291 /* update sw state */
2292 wlc_hw->bmac_phytxant = phytxant;
2294 /* push to ucode if up */
2297 brcms_c_ucode_txant_set(wlc_hw);
2301 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2303 return (u16) wlc_hw->wlc->stf->txant;
2306 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2308 wlc_hw->antsel_type = antsel_type;
2310 /* Update the antsel type for phy module to use */
2311 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2314 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2318 uint intstatus, idx;
2319 struct bcma_device *core = wlc_hw->d11core;
2321 unit = wlc_hw->unit;
2323 for (idx = 0; idx < NFIFO; idx++) {
2324 /* read intstatus register and ignore any non-error bits */
2327 D11REGOFFS(intctrlregs[idx].intstatus)) &
2332 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2333 unit, idx, intstatus);
2335 if (intstatus & I_RO) {
2336 brcms_err(core, "wl%d: fifo %d: receive fifo "
2337 "overflow\n", unit, idx);
2341 if (intstatus & I_PC) {
2342 brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2347 if (intstatus & I_PD) {
2348 brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2353 if (intstatus & I_DE) {
2354 brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2355 "error\n", unit, idx);
2359 if (intstatus & I_RU)
2360 brcms_err(core, "wl%d: fifo %d: receive descriptor "
2361 "underflow\n", idx, unit);
2363 if (intstatus & I_XU) {
2364 brcms_err(core, "wl%d: fifo %d: transmit fifo "
2365 "underflow\n", idx, unit);
2370 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2374 D11REGOFFS(intctrlregs[idx].intstatus),
2379 void brcms_c_intrson(struct brcms_c_info *wlc)
2381 struct brcms_hardware *wlc_hw = wlc->hw;
2382 wlc->macintmask = wlc->defmacintmask;
2383 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2386 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2388 struct brcms_hardware *wlc_hw = wlc->hw;
2394 macintmask = wlc->macintmask; /* isr can still happen */
2396 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2397 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2398 udelay(1); /* ensure int line is no longer driven */
2399 wlc->macintmask = 0;
2401 /* return previous macintmask; resolve race between us and our isr */
2402 return wlc->macintstatus ? 0 : macintmask;
2405 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2407 struct brcms_hardware *wlc_hw = wlc->hw;
2411 wlc->macintmask = macintmask;
2412 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2415 /* assumes that the d11 MAC is enabled */
2416 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2419 u8 fifo = 1 << tx_fifo;
2421 /* Two clients of this code, 11h Quiet period and scanning. */
2423 /* only suspend if not already suspended */
2424 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2427 /* force the core awake only if not already */
2428 if (wlc_hw->suspended_fifos == 0)
2429 brcms_c_ucode_wake_override_set(wlc_hw,
2430 BRCMS_WAKE_OVERRIDE_TXFIFO);
2432 wlc_hw->suspended_fifos |= fifo;
2434 if (wlc_hw->di[tx_fifo]) {
2436 * Suspending AMPDU transmissions in the middle can cause
2437 * underflow which may result in mismatch between ucode and
2438 * driver so suspend the mac before suspending the FIFO
2440 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2441 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2443 dma_txsuspend(wlc_hw->di[tx_fifo]);
2445 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2446 brcms_c_enable_mac(wlc_hw->wlc);
2450 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2453 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2454 * but need to be done here for PIO otherwise the watchdog will catch
2455 * the inconsistency and fire
2457 /* Two clients of this code, 11h Quiet period and scanning. */
2458 if (wlc_hw->di[tx_fifo])
2459 dma_txresume(wlc_hw->di[tx_fifo]);
2461 /* allow core to sleep again */
2462 if (wlc_hw->suspended_fifos == 0)
2465 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2466 if (wlc_hw->suspended_fifos == 0)
2467 brcms_c_ucode_wake_override_clear(wlc_hw,
2468 BRCMS_WAKE_OVERRIDE_TXFIFO);
2472 /* precondition: requires the mac core to be enabled */
2473 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2475 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2478 /* suspend tx fifos */
2479 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2480 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2481 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2482 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2484 /* zero the address match register so we do not send ACKs */
2485 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2488 /* resume tx fifos */
2489 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2490 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2491 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2492 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2494 /* Restore address */
2495 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2499 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2502 brcms_c_ucode_mute_override_set(wlc_hw);
2504 brcms_c_ucode_mute_override_clear(wlc_hw);
2508 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2510 brcms_b_mute(wlc->hw, mute_tx);
2514 * Read and clear macintmask and macintstatus and intstatus registers.
2515 * This routine should be called with interrupts off
2517 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2518 * 0 if the interrupt is not for us, or we are in some special cases;
2519 * device interrupt status bits otherwise.
2521 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2523 struct brcms_hardware *wlc_hw = wlc->hw;
2524 struct bcma_device *core = wlc_hw->d11core;
2525 u32 macintstatus, mask;
2527 /* macintstatus includes a DMA interrupt summary bit */
2528 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2529 mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2531 trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2533 /* detect cardbus removed, in power down(suspend) and in reset */
2534 if (brcms_deviceremoved(wlc))
2537 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2538 * handle that case here.
2540 if (macintstatus == 0xffffffff)
2543 /* defer unsolicited interrupts */
2544 macintstatus &= mask;
2547 if (macintstatus == 0)
2550 /* turn off the interrupts */
2551 bcma_write32(core, D11REGOFFS(macintmask), 0);
2552 (void)bcma_read32(core, D11REGOFFS(macintmask));
2553 wlc->macintmask = 0;
2555 /* clear device interrupts */
2556 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2558 /* MI_DMAINT is indication of non-zero intstatus */
2559 if (macintstatus & MI_DMAINT)
2561 * only fifo interrupt enabled is I_RI in
2562 * RX_FIFO. If MI_DMAINT is set, assume it
2563 * is set and clear the interrupt.
2565 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2568 return macintstatus;
2571 /* Update wlc->macintstatus and wlc->intstatus[]. */
2572 /* Return true if they are updated successfully. false otherwise */
2573 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2577 /* read and clear macintstatus and intstatus registers */
2578 macintstatus = wlc_intstatus(wlc, false);
2580 /* device is removed */
2581 if (macintstatus == 0xffffffff)
2584 /* update interrupt status in software */
2585 wlc->macintstatus |= macintstatus;
2591 * First-level interrupt processing.
2592 * Return true if this was our interrupt
2593 * and if further brcms_c_dpc() processing is required,
2596 bool brcms_c_isr(struct brcms_c_info *wlc)
2598 struct brcms_hardware *wlc_hw = wlc->hw;
2601 if (!wlc_hw->up || !wlc->macintmask)
2604 /* read and clear macintstatus and intstatus registers */
2605 macintstatus = wlc_intstatus(wlc, true);
2607 if (macintstatus == 0xffffffff) {
2608 brcms_err(wlc_hw->d11core,
2609 "DEVICEREMOVED detected in the ISR code path\n");
2613 /* it is not for us */
2614 if (macintstatus == 0)
2617 /* save interrupt status bits */
2618 wlc->macintstatus = macintstatus;
2624 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2626 struct brcms_hardware *wlc_hw = wlc->hw;
2627 struct bcma_device *core = wlc_hw->d11core;
2630 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2631 wlc_hw->band->bandunit);
2634 * Track overlapping suspend requests
2636 wlc_hw->mac_suspend_depth++;
2637 if (wlc_hw->mac_suspend_depth > 1)
2640 /* force the core awake */
2641 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2643 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2645 if (mc == 0xffffffff) {
2646 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2648 brcms_down(wlc->wl);
2651 WARN_ON(mc & MCTL_PSM_JMP_0);
2652 WARN_ON(!(mc & MCTL_PSM_RUN));
2653 WARN_ON(!(mc & MCTL_EN_MAC));
2655 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2656 if (mi == 0xffffffff) {
2657 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2659 brcms_down(wlc->wl);
2662 WARN_ON(mi & MI_MACSSPNDD);
2664 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2666 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2667 BRCMS_MAX_MAC_SUSPEND);
2669 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2670 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2671 " and MI_MACSSPNDD is still not on.\n",
2672 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2673 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2674 "psm_brc 0x%04x\n", wlc_hw->unit,
2675 bcma_read32(core, D11REGOFFS(psmdebug)),
2676 bcma_read32(core, D11REGOFFS(phydebug)),
2677 bcma_read16(core, D11REGOFFS(psm_brc)));
2680 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2681 if (mc == 0xffffffff) {
2682 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2684 brcms_down(wlc->wl);
2687 WARN_ON(mc & MCTL_PSM_JMP_0);
2688 WARN_ON(!(mc & MCTL_PSM_RUN));
2689 WARN_ON(mc & MCTL_EN_MAC);
2692 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2694 struct brcms_hardware *wlc_hw = wlc->hw;
2695 struct bcma_device *core = wlc_hw->d11core;
2698 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2699 wlc->band->bandunit);
2702 * Track overlapping suspend requests
2704 wlc_hw->mac_suspend_depth--;
2705 if (wlc_hw->mac_suspend_depth > 0)
2708 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2709 WARN_ON(mc & MCTL_PSM_JMP_0);
2710 WARN_ON(mc & MCTL_EN_MAC);
2711 WARN_ON(!(mc & MCTL_PSM_RUN));
2713 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2714 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2716 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2717 WARN_ON(mc & MCTL_PSM_JMP_0);
2718 WARN_ON(!(mc & MCTL_EN_MAC));
2719 WARN_ON(!(mc & MCTL_PSM_RUN));
2721 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2722 WARN_ON(mi & MI_MACSSPNDD);
2724 brcms_c_ucode_wake_override_clear(wlc_hw,
2725 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2728 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2730 wlc_hw->hw_stf_ss_opmode = stf_mode;
2733 brcms_upd_ofdm_pctl1_table(wlc_hw);
2736 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2738 struct bcma_device *core = wlc_hw->d11core;
2740 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2742 /* Validate dchip register access */
2744 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2745 (void)bcma_read32(core, D11REGOFFS(objaddr));
2746 w = bcma_read32(core, D11REGOFFS(objdata));
2748 /* Can we write and read back a 32bit register? */
2749 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2750 (void)bcma_read32(core, D11REGOFFS(objaddr));
2751 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2753 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2754 (void)bcma_read32(core, D11REGOFFS(objaddr));
2755 val = bcma_read32(core, D11REGOFFS(objdata));
2756 if (val != (u32) 0xaa5555aa) {
2757 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2758 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2762 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2763 (void)bcma_read32(core, D11REGOFFS(objaddr));
2764 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2766 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2767 (void)bcma_read32(core, D11REGOFFS(objaddr));
2768 val = bcma_read32(core, D11REGOFFS(objdata));
2769 if (val != (u32) 0x55aaaa55) {
2770 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2771 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2775 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2776 (void)bcma_read32(core, D11REGOFFS(objaddr));
2777 bcma_write32(core, D11REGOFFS(objdata), w);
2779 /* clear CFPStart */
2780 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2782 w = bcma_read32(core, D11REGOFFS(maccontrol));
2783 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2784 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2785 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2786 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2787 (MCTL_IHR_EN | MCTL_WAKE),
2788 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2795 #define PHYPLL_WAIT_US 100000
2797 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2799 struct bcma_device *core = wlc_hw->d11core;
2802 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2807 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2808 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2810 CCS_ERSRC_REQ_D11PLL |
2811 CCS_ERSRC_REQ_PHYPLL);
2812 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2813 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2816 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2817 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2818 brcms_err(core, "%s: turn on PHY PLL failed\n",
2821 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2822 tmp | CCS_ERSRC_REQ_D11PLL |
2823 CCS_ERSRC_REQ_PHYPLL);
2824 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2825 (CCS_ERSRC_AVAIL_D11PLL |
2826 CCS_ERSRC_AVAIL_PHYPLL)) !=
2827 (CCS_ERSRC_AVAIL_D11PLL |
2828 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2830 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2832 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2834 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2835 brcms_err(core, "%s: turn on PHY PLL failed\n",
2840 * Since the PLL may be shared, other cores can still
2841 * be requesting it; so we'll deassert the request but
2842 * not wait for status to comply.
2844 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2845 ~CCS_ERSRC_REQ_PHYPLL);
2846 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2850 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2854 brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2856 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2861 if (wlc_hw->noreset)
2865 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2867 /* turn off analog core */
2868 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2870 /* turn off PHYPLL to save power */
2871 brcms_b_core_phypll_ctl(wlc_hw, false);
2873 wlc_hw->clk = false;
2874 bcma_core_disable(wlc_hw->d11core, 0);
2875 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2878 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2880 struct brcms_hardware *wlc_hw = wlc->hw;
2883 /* free any posted tx packets */
2884 for (i = 0; i < NFIFO; i++) {
2885 if (wlc_hw->di[i]) {
2886 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2887 if (i < TX_BCMC_FIFO)
2888 ieee80211_wake_queue(wlc->pub->ieee_hw,
2889 brcms_fifo_to_ac(i));
2893 /* free any posted rx packets */
2894 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2898 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2900 struct bcma_device *core = wlc_hw->d11core;
2901 u16 objoff = D11REGOFFS(objdata);
2903 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2904 (void)bcma_read32(core, D11REGOFFS(objaddr));
2908 return bcma_read16(core, objoff);
2912 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2915 struct bcma_device *core = wlc_hw->d11core;
2916 u16 objoff = D11REGOFFS(objdata);
2918 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2919 (void)bcma_read32(core, D11REGOFFS(objaddr));
2923 bcma_wflush16(core, objoff, v);
2927 * Read a single u16 from shared memory.
2928 * SHM 'offset' needs to be an even address
2930 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2932 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2936 * Write a single u16 to shared memory.
2937 * SHM 'offset' needs to be an even address
2939 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2941 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2945 * Copy a buffer to shared memory of specified type .
2946 * SHM 'offset' needs to be an even address and
2947 * Buffer length 'len' must be an even number of bytes
2948 * 'sel' selects the type of memory
2951 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2952 const void *buf, int len, u32 sel)
2955 const u8 *p = (const u8 *)buf;
2958 if (len <= 0 || (offset & 1) || (len & 1))
2961 for (i = 0; i < len; i += 2) {
2962 v = p[i] | (p[i + 1] << 8);
2963 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2968 * Copy a piece of shared memory of specified type to a buffer .
2969 * SHM 'offset' needs to be an even address and
2970 * Buffer length 'len' must be an even number of bytes
2971 * 'sel' selects the type of memory
2974 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2981 if (len <= 0 || (offset & 1) || (len & 1))
2984 for (i = 0; i < len; i += 2) {
2985 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2987 p[i + 1] = (v >> 8) & 0xFF;
2991 /* Copy a buffer to shared memory.
2992 * SHM 'offset' needs to be an even address and
2993 * Buffer length 'len' must be an even number of bytes
2995 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2996 const void *buf, int len)
2998 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
3001 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3007 /* write retry limit to SCR, shouldn't need to suspend */
3009 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3010 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3011 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3012 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3013 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3014 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3015 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3016 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3020 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3023 if (mboolisset(wlc_hw->pllreq, req_bit))
3026 mboolset(wlc_hw->pllreq, req_bit);
3028 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3030 brcms_b_xtal(wlc_hw, ON);
3033 if (!mboolisset(wlc_hw->pllreq, req_bit))
3036 mboolclr(wlc_hw->pllreq, req_bit);
3038 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3040 brcms_b_xtal(wlc_hw, OFF);
3045 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3047 wlc_hw->antsel_avail = antsel_avail;
3051 * conditions under which the PM bit should be set in outgoing frames
3052 * and STAY_AWAKE is meaningful
3054 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3056 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3058 /* disallow PS when one of the following global conditions meets */
3059 if (!wlc->pub->associated)
3062 /* disallow PS when one of these meets when not scanning */
3063 if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3066 if (cfg->associated) {
3068 * disallow PS when one of the following
3069 * bsscfg specific conditions meets
3080 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3083 struct macstat macstats;
3090 /* if driver down, make no sense to update stats */
3095 /* save last rx fifo 0 overflow count */
3096 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3098 /* save last tx fifo underflow count */
3099 for (i = 0; i < NFIFO; i++)
3100 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3103 /* Read mac stats from contiguous shared memory */
3104 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3105 sizeof(struct macstat), OBJADDR_SHM_SEL);
3108 /* check for rx fifo 0 overflow */
3109 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3111 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3112 wlc->pub->unit, delta);
3114 /* check for tx fifo underflows */
3115 for (i = 0; i < NFIFO; i++) {
3117 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3120 brcms_err(wlc->hw->d11core,
3121 "wl%d: %u tx fifo %d underflows!\n",
3122 wlc->pub->unit, delta, i);
3126 /* merge counters from dma module */
3127 for (i = 0; i < NFIFO; i++) {
3129 dma_counterreset(wlc->hw->di[i]);
3133 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3135 /* reset the core */
3136 if (!brcms_deviceremoved(wlc_hw->wlc))
3137 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3139 /* purge the dma rings */
3140 brcms_c_flushqueues(wlc_hw->wlc);
3143 void brcms_c_reset(struct brcms_c_info *wlc)
3145 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3147 /* slurp up hw mac counters before core reset */
3148 brcms_c_statsupd(wlc);
3150 /* reset our snapshot of macstat counters */
3151 memset((char *)wlc->core->macstat_snapshot, 0,
3152 sizeof(struct macstat));
3154 brcms_b_reset(wlc->hw);
3157 void brcms_c_init_scb(struct scb *scb)
3161 memset(scb, 0, sizeof(struct scb));
3162 scb->flags = SCB_WMECAP | SCB_HTCAP;
3163 for (i = 0; i < NUMPRIO; i++) {
3165 scb->seqctl[i] = 0xFFFF;
3168 scb->seqctl_nonqos = 0xFFFF;
3169 scb->magic = SCB_MAGIC;
3174 * download ucode/PCM
3175 * let ucode run to suspended
3176 * download ucode inits
3177 * config other core registers
3180 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3182 struct brcms_hardware *wlc_hw = wlc->hw;
3183 struct bcma_device *core = wlc_hw->d11core;
3187 bool fifosz_fixup = false;
3190 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3192 brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3195 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3197 brcms_ucode_download(wlc_hw);
3199 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3201 fifosz_fixup = true;
3203 /* let the PSM run to the suspended state, set mode to BSS STA */
3204 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3205 brcms_b_mctrl(wlc_hw, ~0,
3206 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3208 /* wait for ucode to self-suspend after auto-init */
3209 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3210 MI_MACSSPNDD) == 0), 1000 * 1000);
3211 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3212 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3213 "suspend!\n", wlc_hw->unit);
3215 brcms_c_gpio_init(wlc);
3217 sflags = bcma_aread32(core, BCMA_IOST);
3219 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3220 if (BRCMS_ISNPHY(wlc_hw->band))
3221 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3223 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3224 " %d\n", __func__, wlc_hw->unit,
3226 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3227 if (BRCMS_ISLCNPHY(wlc_hw->band))
3228 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3230 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3231 " %d\n", __func__, wlc_hw->unit,
3234 brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3235 __func__, wlc_hw->unit, wlc_hw->corerev);
3238 /* For old ucode, txfifo sizes needs to be modified(increased) */
3240 brcms_b_corerev_fifofixup(wlc_hw);
3242 /* check txfifo allocations match between ucode and driver */
3243 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3244 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3248 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3249 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3253 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3254 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3255 buf[TX_AC_BK_FIFO] &= 0xff;
3256 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3260 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3264 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3265 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3266 buf[TX_BCMC_FIFO] &= 0xff;
3267 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3271 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3276 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3277 " driver size %d index %d\n", buf[i],
3278 wlc_hw->xmtfifo_sz[i], i);
3280 /* make sure we can still talk to the mac */
3281 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3283 /* band-specific inits done by wlc_bsinit() */
3285 /* Set up frame burst size and antenna swap threshold init values */
3286 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3287 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3289 /* enable one rx interrupt per received frame */
3290 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3292 /* set the station mode (BSS STA) */
3293 brcms_b_mctrl(wlc_hw,
3294 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3295 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3297 /* set up Beacon interval */
3298 bcnint_us = 0x8000 << 10;
3299 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3300 (bcnint_us << CFPREP_CBI_SHIFT));
3301 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3302 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3304 /* write interrupt mask */
3305 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3308 /* allow the MAC to control the PHY clock (dynamic on/off) */
3309 brcms_b_macphyclk_set(wlc_hw, ON);
3311 /* program dynamic clock control fast powerup delay register */
3312 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3313 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3315 /* tell the ucode the corerev */
3316 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3318 /* tell the ucode MAC capabilities */
3319 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3320 (u16) (wlc_hw->machwcap & 0xffff));
3321 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3323 machwcap >> 16) & 0xffff));
3325 /* write retry limits to SCR, this done after PSM init */
3326 bcma_write32(core, D11REGOFFS(objaddr),
3327 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3328 (void)bcma_read32(core, D11REGOFFS(objaddr));
3329 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3330 bcma_write32(core, D11REGOFFS(objaddr),
3331 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3332 (void)bcma_read32(core, D11REGOFFS(objaddr));
3333 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3335 /* write rate fallback retry limits */
3336 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3337 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3339 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3340 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3342 /* init the tx dma engines */
3343 for (i = 0; i < NFIFO; i++) {
3345 dma_txinit(wlc_hw->di[i]);
3348 /* init the rx dma engine(s) and post receive buffers */
3349 dma_rxinit(wlc_hw->di[RX_FIFO]);
3350 dma_rxfill(wlc_hw->di[RX_FIFO]);
3354 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3357 struct brcms_c_info *wlc = wlc_hw->wlc;
3359 /* request FAST clock if not on */
3360 fastclk = wlc_hw->forcefastclk;
3362 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3364 /* disable interrupts */
3365 macintmask = brcms_intrsoff(wlc->wl);
3367 /* set up the specified band and chanspec */
3368 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3369 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3371 /* do one-time phy inits and calibration */
3372 wlc_phy_cal_init(wlc_hw->band->pi);
3374 /* core-specific initialization */
3375 brcms_b_coreinit(wlc);
3377 /* band-specific inits */
3378 brcms_b_bsinit(wlc, chanspec);
3380 /* restore macintmask */
3381 brcms_intrsrestore(wlc->wl, macintmask);
3383 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3384 * is suspended and brcms_c_enable_mac() will clear this override bit.
3386 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3389 * initialize mac_suspend_depth to 1 to match ucode
3390 * initial suspended state
3392 wlc_hw->mac_suspend_depth = 1;
3394 /* restore the clk */
3396 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3399 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3402 /* Save our copy of the chanspec */
3403 wlc->chanspec = chanspec;
3405 /* Set the chanspec and power limits for this locale */
3406 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3408 if (wlc->stf->ss_algosel_auto)
3409 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3412 brcms_c_stf_ss_update(wlc, wlc->band);
3416 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3418 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3419 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3420 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3421 brcms_chspec_bw(wlc->default_bss->chanspec),
3422 wlc->stf->txstreams);
3425 /* derive wlc->band->basic_rate[] table from 'rateset' */
3426 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3427 struct brcms_c_rateset *rateset)
3433 u8 *br = wlc->band->basic_rate;
3436 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3437 memset(br, 0, BRCM_MAXRATE + 1);
3439 /* For each basic rate in the rates list, make an entry in the
3440 * best basic lookup.
3442 for (i = 0; i < rateset->count; i++) {
3443 /* only make an entry for a basic rate */
3444 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3447 /* mask off basic bit */
3448 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3450 if (rate > BRCM_MAXRATE) {
3451 brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3452 "invalid rate 0x%X in rate set\n",
3460 /* The rate lookup table now has non-zero entries for each
3461 * basic rate, equal to the basic rate: br[basicN] = basicN
3463 * To look up the best basic rate corresponding to any
3464 * particular rate, code can use the basic_rate table
3467 * basic_rate = wlc->band->basic_rate[tx_rate]
3469 * Make sure there is a best basic rate entry for
3470 * every rate by walking up the table from low rates
3471 * to high, filling in holes in the lookup table
3474 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3475 rate = wlc->band->hw_rateset.rates[i];
3477 if (br[rate] != 0) {
3478 /* This rate is a basic rate.
3479 * Keep track of the best basic rate so far by
3482 if (is_ofdm_rate(rate))
3490 /* This rate is not a basic rate so figure out the
3491 * best basic rate less than this rate and fill in
3492 * the hole in the table
3495 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3500 if (is_ofdm_rate(rate)) {
3502 * In 11g and 11a, the OFDM mandatory rates
3503 * are 6, 12, and 24 Mbps
3505 if (rate >= BRCM_RATE_24M)
3506 mandatory = BRCM_RATE_24M;
3507 else if (rate >= BRCM_RATE_12M)
3508 mandatory = BRCM_RATE_12M;
3510 mandatory = BRCM_RATE_6M;
3512 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3516 br[rate] = mandatory;
3520 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3523 struct brcms_c_rateset default_rateset;
3525 uint i, band_order[2];
3528 * We might have been bandlocked during down and the chip
3529 * power-cycled (hibernate). Figure out the right band to park on
3531 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3532 /* updated in brcms_c_bandlock() */
3533 parkband = wlc->band->bandunit;
3534 band_order[0] = band_order[1] = parkband;
3536 /* park on the band of the specified chanspec */
3537 parkband = chspec_bandunit(chanspec);
3539 /* order so that parkband initialize last */
3540 band_order[0] = parkband ^ 1;
3541 band_order[1] = parkband;
3544 /* make each band operational, software state init */
3545 for (i = 0; i < wlc->pub->_nbands; i++) {
3546 uint j = band_order[i];
3548 wlc->band = wlc->bandstate[j];
3550 brcms_default_rateset(wlc, &default_rateset);
3552 /* fill in hw_rate */
3553 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3554 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3555 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3557 /* init basic rate lookup */
3558 brcms_c_rate_lookup_init(wlc, &default_rateset);
3561 /* sync up phy/radio chanspec */
3562 brcms_c_set_phy_chanspec(wlc, chanspec);
3566 * Set or clear filtering related maccontrol bits based on
3567 * specified filter flags
3569 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3571 u32 promisc_bits = 0;
3573 wlc->filter_flags = filter_flags;
3575 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3576 promisc_bits |= MCTL_PROMISC;
3578 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3579 promisc_bits |= MCTL_BCNS_PROMISC;
3581 if (filter_flags & FIF_FCSFAIL)
3582 promisc_bits |= MCTL_KEEPBADFCS;
3584 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3585 promisc_bits |= MCTL_KEEPCONTROL;
3587 brcms_b_mctrl(wlc->hw,
3588 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3589 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3594 * ucode, hwmac update
3595 * Channel dependent updates for ucode and hw
3597 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3599 /* enable or disable any active IBSSs depending on whether or not
3600 * we are on the home channel
3602 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3603 if (wlc->pub->associated) {
3605 * BMAC_NOTE: This is something that should be fixed
3606 * in ucode inits. I think that the ucode inits set
3607 * up the bcn templates and shm values with a bogus
3608 * beacon. This should not be done in the inits. If
3609 * ucode needs to set up a beacon for testing, the
3610 * test routines should write it down, not expect the
3611 * inits to populate a bogus beacon.
3613 if (BRCMS_PHY_11N_CAP(wlc->band))
3614 brcms_b_write_shm(wlc->hw,
3615 M_BCN_TXTSF_OFFSET, 0);
3618 /* disable an active IBSS if we are not on the home channel */
3622 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3626 u8 basic_phy_rate, basic_index;
3627 u16 dir_table, basic_table;
3630 /* Shared memory address for the table we are reading */
3631 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3633 /* Shared memory address for the table we are writing */
3634 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3637 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3638 * the index into the rate table.
3640 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3641 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3642 index = phy_rate & 0xf;
3643 basic_index = basic_phy_rate & 0xf;
3645 /* Find the SHM pointer to the ACK rate entry by looking in the
3648 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3650 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3651 * to the correct basic rate for the given incoming rate
3653 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3656 static const struct brcms_c_rateset *
3657 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3659 const struct brcms_c_rateset *rs_dflt;
3661 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3662 if (wlc->band->bandtype == BRCM_BAND_5G)
3663 rs_dflt = &ofdm_mimo_rates;
3665 rs_dflt = &cck_ofdm_mimo_rates;
3666 } else if (wlc->band->gmode)
3667 rs_dflt = &cck_ofdm_rates;
3669 rs_dflt = &cck_rates;
3674 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3676 const struct brcms_c_rateset *rs_dflt;
3677 struct brcms_c_rateset rs;
3678 u8 rate, basic_rate;
3681 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3683 brcms_c_rateset_copy(rs_dflt, &rs);
3684 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3686 /* walk the phy rate table and update SHM basic rate lookup table */
3687 for (i = 0; i < rs.count; i++) {
3688 rate = rs.rates[i] & BRCMS_RATE_MASK;
3690 /* for a given rate brcms_basic_rate returns the rate at
3691 * which a response ACK/CTS should be sent.
3693 basic_rate = brcms_basic_rate(wlc, rate);
3694 if (basic_rate == 0)
3695 /* This should only happen if we are using a
3696 * restricted rateset.
3698 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3700 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3704 /* band-specific init */
3705 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3707 brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3708 wlc->pub->unit, wlc->band->bandunit);
3710 /* write ucode ACK/CTS rate table */
3711 brcms_c_set_ratetable(wlc);
3713 /* update some band specific mac configuration */
3714 brcms_c_ucode_mac_upd(wlc);
3716 /* init antenna selection */
3717 brcms_c_antsel_init(wlc->asi);
3721 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3723 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3726 int idle_busy_ratio_x_16 = 0;
3728 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3729 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3730 if (duty_cycle > 100 || duty_cycle < 0) {
3731 brcms_err(wlc->hw->d11core,
3732 "wl%d: duty cycle value off limit\n",
3737 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3738 /* Only write to shared memory when wl is up */
3740 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3743 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3745 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3750 /* push sw hps and wake state through hardware */
3751 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3757 hps = brcms_c_ps_allowed(wlc);
3759 brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3762 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3767 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3769 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3772 brcms_b_wait_for_wake(wlc->hw);
3776 * Write this BSS config's MAC address to core.
3777 * Updates RXE match engine.
3779 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3782 struct brcms_c_info *wlc = bsscfg->wlc;
3784 /* enter the MAC addr into the RXE match registers */
3785 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3787 brcms_c_ampdu_macaddr_upd(wlc);
3792 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3793 * Updates RXE match engine.
3795 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3797 /* we need to update BSSID in RXE match registers */
3798 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3801 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3803 wlc_hw->shortslot = shortslot;
3805 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3806 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3807 brcms_b_update_slot_timing(wlc_hw, shortslot);
3808 brcms_c_enable_mac(wlc_hw->wlc);
3813 * Suspend the the MAC and update the slot timing
3814 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3816 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3818 /* use the override if it is set */
3819 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3820 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3822 if (wlc->shortslot == shortslot)
3825 wlc->shortslot = shortslot;
3827 brcms_b_set_shortslot(wlc->hw, shortslot);
3830 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3832 if (wlc->home_chanspec != chanspec) {
3833 wlc->home_chanspec = chanspec;
3835 if (wlc->bsscfg->associated)
3836 wlc->bsscfg->current_bss->chanspec = chanspec;
3841 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3842 bool mute_tx, struct txpwr_limits *txpwr)
3846 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3849 wlc_hw->chanspec = chanspec;
3851 /* Switch bands if necessary */
3852 if (wlc_hw->_nbands > 1) {
3853 bandunit = chspec_bandunit(chanspec);
3854 if (wlc_hw->band->bandunit != bandunit) {
3855 /* brcms_b_setband disables other bandunit,
3856 * use light band switch if not up yet
3859 wlc_phy_chanspec_radio_set(wlc_hw->
3860 bandstate[bandunit]->
3862 brcms_b_setband(wlc_hw, bandunit, chanspec);
3864 brcms_c_setxband(wlc_hw, bandunit);
3869 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3873 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3875 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3877 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3878 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3880 /* Update muting of the channel */
3881 brcms_b_mute(wlc_hw, mute_tx);
3885 /* switch to and initialize new band */
3886 static void brcms_c_setband(struct brcms_c_info *wlc,
3889 wlc->band = wlc->bandstate[bandunit];
3894 /* wait for at least one beacon before entering sleeping state */
3895 brcms_c_set_ps_ctrl(wlc);
3897 /* band-specific initializations */
3898 brcms_c_bsinit(wlc);
3901 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3904 bool switchband = false;
3905 u16 old_chanspec = wlc->chanspec;
3907 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3908 brcms_err(wlc->hw->d11core, "wl%d: %s: Bad channel %d\n",
3909 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3913 /* Switch bands if necessary */
3914 if (wlc->pub->_nbands > 1) {
3915 bandunit = chspec_bandunit(chanspec);
3916 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3918 if (wlc->bandlocked) {
3919 brcms_err(wlc->hw->d11core,
3920 "wl%d: %s: chspec %d band is locked!\n",
3921 wlc->pub->unit, __func__,
3922 CHSPEC_CHANNEL(chanspec));
3926 * should the setband call come after the
3927 * brcms_b_chanspec() ? if the setband updates
3928 * (brcms_c_bsinit) use low level calls to inspect and
3929 * set state, the state inspected may be from the wrong
3930 * band, or the following brcms_b_set_chanspec() may
3933 brcms_c_setband(wlc, bandunit);
3937 /* sync up phy/radio chanspec */
3938 brcms_c_set_phy_chanspec(wlc, chanspec);
3940 /* init antenna selection */
3941 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3942 brcms_c_antsel_init(wlc->asi);
3944 /* Fix the hardware rateset based on bw.
3945 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3947 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3948 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3951 /* update some mac configuration since chanspec changed */
3952 brcms_c_ucode_mac_upd(wlc);
3956 * This function changes the phytxctl for beacon based on current
3957 * beacon ratespec AND txant setting as per this table:
3958 * ratespec CCK ant = wlc->stf->txant
3961 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3965 u16 phytxant = wlc->stf->phytxant;
3966 u16 mask = PHY_TXC_ANT_MASK;
3968 /* for non-siso rates or default setting, use the available chains */
3969 if (BRCMS_PHY_11N_CAP(wlc->band))
3970 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3972 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3973 phyctl = (phyctl & ~mask) | phytxant;
3974 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3978 * centralized protection config change function to simplify debugging, no
3979 * consistency checking this should be called only on changes to avoid overhead
3980 * in periodic function
3982 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3985 * Cannot use brcms_dbg_* here because this function is called
3986 * before wlc is sufficiently initialized.
3988 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3991 case BRCMS_PROT_G_SPEC:
3992 wlc->protection->_g = (bool) val;
3994 case BRCMS_PROT_G_OVR:
3995 wlc->protection->g_override = (s8) val;
3997 case BRCMS_PROT_G_USER:
3998 wlc->protection->gmode_user = (u8) val;
4000 case BRCMS_PROT_OVERLAP:
4001 wlc->protection->overlap = (s8) val;
4003 case BRCMS_PROT_N_USER:
4004 wlc->protection->nmode_user = (s8) val;
4006 case BRCMS_PROT_N_CFG:
4007 wlc->protection->n_cfg = (s8) val;
4009 case BRCMS_PROT_N_CFG_OVR:
4010 wlc->protection->n_cfg_override = (s8) val;
4012 case BRCMS_PROT_N_NONGF:
4013 wlc->protection->nongf = (bool) val;
4015 case BRCMS_PROT_N_NONGF_OVR:
4016 wlc->protection->nongf_override = (s8) val;
4018 case BRCMS_PROT_N_PAM_OVR:
4019 wlc->protection->n_pam_override = (s8) val;
4021 case BRCMS_PROT_N_OBSS:
4022 wlc->protection->n_obss = (bool) val;
4031 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4034 brcms_c_update_beacon(wlc);
4035 brcms_c_update_probe_resp(wlc, true);
4039 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4041 wlc->stf->ldpc = val;
4044 brcms_c_update_beacon(wlc);
4045 brcms_c_update_probe_resp(wlc, true);
4046 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4050 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4051 const struct ieee80211_tx_queue_params *params,
4055 struct shm_acparams acp_shm;
4058 /* Only apply params if the core is out of reset and has clocks */
4060 brcms_err(wlc->hw->d11core, "wl%d: %s : no-clock\n",
4061 wlc->pub->unit, __func__);
4065 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
4066 /* fill in shm ac params struct */
4067 acp_shm.txop = params->txop;
4068 /* convert from units of 32us to us for ucode */
4069 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4070 EDCF_TXOP2USEC(acp_shm.txop);
4071 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4073 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4074 && acp_shm.aifs < EDCF_AIFSN_MAX)
4077 if (acp_shm.aifs < EDCF_AIFSN_MIN
4078 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4079 brcms_err(wlc->hw->d11core, "wl%d: edcf_setparams: bad "
4080 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4082 acp_shm.cwmin = params->cw_min;
4083 acp_shm.cwmax = params->cw_max;
4084 acp_shm.cwcur = acp_shm.cwmin;
4086 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4088 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4089 /* Indicate the new params to the ucode */
4090 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4093 M_EDCF_STATUS_OFF));
4094 acp_shm.status |= WME_STATUS_NEWAC;
4096 /* Fill in shm acparam table */
4097 shm_entry = (u16 *) &acp_shm;
4098 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4099 brcms_b_write_shm(wlc->hw,
4101 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4106 brcms_c_suspend_mac_and_wait(wlc);
4107 brcms_c_enable_mac(wlc);
4111 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4115 struct ieee80211_tx_queue_params txq_pars;
4116 static const struct edcf_acparam default_edcf_acparams[] = {
4117 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4118 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4119 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4120 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4121 }; /* ucode needs these parameters during its initialization */
4122 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4124 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4125 /* find out which ac this set of params applies to */
4126 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4128 /* fill in shm ac params struct */
4129 txq_pars.txop = edcf_acp->TXOP;
4130 txq_pars.aifs = edcf_acp->ACI;
4132 /* CWmin = 2^(ECWmin) - 1 */
4133 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4134 /* CWmax = 2^(ECWmax) - 1 */
4135 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4136 >> EDCF_ECWMAX_SHIFT);
4137 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4141 brcms_c_suspend_mac_and_wait(wlc);
4142 brcms_c_enable_mac(wlc);
4146 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4148 /* Don't start the timer if HWRADIO feature is disabled */
4149 if (wlc->radio_monitor)
4152 wlc->radio_monitor = true;
4153 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4154 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4157 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4159 if (!wlc->radio_monitor)
4162 wlc->radio_monitor = false;
4163 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4164 return brcms_del_timer(wlc->radio_timer);
4167 /* read hwdisable state and propagate to wlc flag */
4168 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4170 if (wlc->pub->hw_off)
4173 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4174 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4176 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4179 /* update hwradio status and return it */
4180 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4182 brcms_c_radio_hwdisable_upd(wlc);
4184 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4188 /* periodical query hw radio button while driver is "down" */
4189 static void brcms_c_radio_timer(void *arg)
4191 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4193 if (brcms_deviceremoved(wlc)) {
4194 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4195 wlc->pub->unit, __func__);
4196 brcms_down(wlc->wl);
4200 brcms_c_radio_hwdisable_upd(wlc);
4203 /* common low-level watchdog code */
4204 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4206 struct brcms_hardware *wlc_hw = wlc->hw;
4211 /* increment second count */
4214 /* Check for FIFO error interrupts */
4215 brcms_b_fifoerrors(wlc_hw);
4217 /* make sure RX dma has buffers */
4218 dma_rxfill(wlc->hw->di[RX_FIFO]);
4220 wlc_phy_watchdog(wlc_hw->band->pi);
4223 /* common watchdog code */
4224 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4226 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
4231 if (brcms_deviceremoved(wlc)) {
4232 brcms_err(wlc->hw->d11core, "wl%d: %s: dead chip\n",
4233 wlc->pub->unit, __func__);
4234 brcms_down(wlc->wl);
4238 /* increment second count */
4241 brcms_c_radio_hwdisable_upd(wlc);
4242 /* if radio is disable, driver may be down, quit here */
4243 if (wlc->pub->radio_disabled)
4246 brcms_b_watchdog(wlc);
4249 * occasionally sample mac stat counters to
4250 * detect 16-bit counter wrap
4252 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4253 brcms_c_statsupd(wlc);
4255 if (BRCMS_ISNPHY(wlc->band) &&
4256 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4257 BRCMS_TEMPSENSE_PERIOD)) {
4258 wlc->tempsense_lasttime = wlc->pub->now;
4259 brcms_c_tempsense_upd(wlc);
4263 static void brcms_c_watchdog_by_timer(void *arg)
4265 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4267 brcms_c_watchdog(wlc);
4270 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4272 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4274 if (!wlc->wdtimer) {
4275 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4280 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4282 if (!wlc->radio_timer) {
4283 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4295 * Initialize brcms_c_info default values ...
4296 * may get overrides later in this function
4298 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4302 /* Save our copy of the chanspec */
4303 wlc->chanspec = ch20mhz_chspec(1);
4305 /* various 802.11g modes */
4306 wlc->shortslot = false;
4307 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4309 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4310 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4312 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4313 BRCMS_PROTECTION_AUTO);
4314 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4315 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4316 BRCMS_PROTECTION_AUTO);
4317 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4318 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4320 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4321 BRCMS_PROTECTION_CTL_OVERLAP);
4323 /* 802.11g draft 4.0 NonERP elt advertisement */
4324 wlc->include_legacy_erp = true;
4326 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4327 wlc->stf->txant = ANT_TX_DEF;
4329 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4331 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4332 for (i = 0; i < NFIFO; i++)
4333 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4334 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4336 /* default rate fallback retry limits */
4337 wlc->SFBL = RETRY_SHORT_FB;
4338 wlc->LFBL = RETRY_LONG_FB;
4340 /* default mac retry limits */
4341 wlc->SRL = RETRY_SHORT_DEF;
4342 wlc->LRL = RETRY_LONG_DEF;
4344 /* WME QoS mode is Auto by default */
4345 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4346 wlc->pub->bcmerror = 0;
4349 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4353 unit = wlc->pub->unit;
4355 wlc->asi = brcms_c_antsel_attach(wlc);
4356 if (wlc->asi == NULL) {
4357 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4363 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4364 if (wlc->ampdu == NULL) {
4365 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4371 if ((brcms_c_stf_attach(wlc) != 0)) {
4372 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4381 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4387 * run backplane attach, init nvram
4389 * initialize software state for each core and band
4390 * put the whole chip in reset(driver down state), no clock
4392 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4393 uint unit, bool piomode)
4395 struct brcms_hardware *wlc_hw;
4399 struct shared_phy_params sha_params;
4400 struct wiphy *wiphy = wlc->wiphy;
4401 struct pci_dev *pcidev = core->bus->host_pci;
4402 struct ssb_sprom *sprom = &core->bus->sprom;
4404 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4405 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4409 brcms_dbg_info(core, "wl%d: vendor 0x%x device 0x%x\n", unit,
4410 core->bus->boardinfo.vendor,
4411 core->bus->boardinfo.type);
4417 wlc_hw->unit = unit;
4418 wlc_hw->band = wlc_hw->bandstate[0];
4419 wlc_hw->_piomode = piomode;
4421 /* populate struct brcms_hardware with default values */
4422 brcms_b_info_init(wlc_hw);
4425 * Do the hardware portion of the attach. Also initialize software
4426 * state that depends on the particular hardware we are running.
4428 wlc_hw->sih = ai_attach(core->bus);
4429 if (wlc_hw->sih == NULL) {
4430 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4436 /* verify again the device is supported */
4437 if (!brcms_c_chipmatch(core)) {
4438 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4444 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4445 wlc_hw->vendorid = pcidev->vendor;
4446 wlc_hw->deviceid = pcidev->device;
4448 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4449 wlc_hw->deviceid = core->bus->boardinfo.type;
4452 wlc_hw->d11core = core;
4453 wlc_hw->corerev = core->id.rev;
4455 /* validate chip, chiprev and corerev */
4456 if (!brcms_c_isgoodchip(wlc_hw)) {
4461 /* initialize power control registers */
4462 ai_clkctl_init(wlc_hw->sih);
4464 /* request fastclock and force fastclock for the rest of attach
4465 * bring the d11 core out of reset.
4466 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4467 * is still false; But it will be called again inside wlc_corereset,
4468 * after d11 is out of reset.
4470 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4471 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4473 if (!brcms_b_validate_chip_access(wlc_hw)) {
4474 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4480 /* get the board rev, used just below */
4481 j = sprom->board_rev;
4482 /* promote srom boardrev of 0xFF to 1 */
4483 if (j == BOARDREV_PROMOTABLE)
4484 j = BOARDREV_PROMOTED;
4485 wlc_hw->boardrev = (u16) j;
4486 if (!brcms_c_validboardtype(wlc_hw)) {
4487 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4488 "board type (0x%x)" " or revision level (0x%x)\n",
4489 unit, ai_get_boardtype(wlc_hw->sih),
4494 wlc_hw->sromrev = sprom->revision;
4495 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4496 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4498 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4499 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4501 /* check device id(srom, nvram etc.) to set bands */
4502 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4503 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4504 wlc_hw->deviceid == BCM43224_CHIP_ID)
4505 /* Dualband boards */
4506 wlc_hw->_nbands = 2;
4508 wlc_hw->_nbands = 1;
4510 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4511 wlc_hw->_nbands = 1;
4513 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4514 * unconditionally does the init of these values
4516 wlc->vendorid = wlc_hw->vendorid;
4517 wlc->deviceid = wlc_hw->deviceid;
4518 wlc->pub->sih = wlc_hw->sih;
4519 wlc->pub->corerev = wlc_hw->corerev;
4520 wlc->pub->sromrev = wlc_hw->sromrev;
4521 wlc->pub->boardrev = wlc_hw->boardrev;
4522 wlc->pub->boardflags = wlc_hw->boardflags;
4523 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4524 wlc->pub->_nbands = wlc_hw->_nbands;
4526 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4528 if (wlc_hw->physhim == NULL) {
4529 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4535 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4536 sha_params.sih = wlc_hw->sih;
4537 sha_params.physhim = wlc_hw->physhim;
4538 sha_params.unit = unit;
4539 sha_params.corerev = wlc_hw->corerev;
4540 sha_params.vid = wlc_hw->vendorid;
4541 sha_params.did = wlc_hw->deviceid;
4542 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4543 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4544 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4545 sha_params.sromrev = wlc_hw->sromrev;
4546 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4547 sha_params.boardrev = wlc_hw->boardrev;
4548 sha_params.boardflags = wlc_hw->boardflags;
4549 sha_params.boardflags2 = wlc_hw->boardflags2;
4551 /* alloc and save pointer to shared phy state area */
4552 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4553 if (!wlc_hw->phy_sh) {
4558 /* initialize software state for each core and band */
4559 for (j = 0; j < wlc_hw->_nbands; j++) {
4561 * band0 is always 2.4Ghz
4562 * band1, if present, is 5Ghz
4565 brcms_c_setxband(wlc_hw, j);
4567 wlc_hw->band->bandunit = j;
4568 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4569 wlc->band->bandunit = j;
4570 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4571 wlc->core->coreidx = core->core_index;
4573 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4574 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4576 /* init tx fifo size */
4577 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4578 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4579 ARRAY_SIZE(xmtfifo_sz));
4580 wlc_hw->xmtfifo_sz =
4581 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4582 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4584 /* Get a phy for this band */
4586 wlc_phy_attach(wlc_hw->phy_sh, core,
4587 wlc_hw->band->bandtype,
4589 if (wlc_hw->band->pi == NULL) {
4590 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4591 "attach failed\n", unit);
4596 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4598 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4599 &wlc_hw->band->phyrev,
4600 &wlc_hw->band->radioid,
4601 &wlc_hw->band->radiorev);
4602 wlc_hw->band->abgphy_encore =
4603 wlc_phy_get_encore(wlc_hw->band->pi);
4604 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4605 wlc_hw->band->core_flags =
4606 wlc_phy_get_coreflags(wlc_hw->band->pi);
4608 /* verify good phy_type & supported phy revision */
4609 if (BRCMS_ISNPHY(wlc_hw->band)) {
4610 if (NCONF_HAS(wlc_hw->band->phyrev))
4614 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4615 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4621 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4622 "phy type/rev (%d/%d)\n", unit,
4623 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4630 * BMAC_NOTE: wlc->band->pi should not be set below and should
4631 * be done in the high level attach. However we can not make
4632 * that change until all low level access is changed to
4633 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4634 * keeping wlc_hw->band->pi as well for incremental update of
4635 * low level fns, and cut over low only init when all fns
4638 wlc->band->pi = wlc_hw->band->pi;
4639 wlc->band->phytype = wlc_hw->band->phytype;
4640 wlc->band->phyrev = wlc_hw->band->phyrev;
4641 wlc->band->radioid = wlc_hw->band->radioid;
4642 wlc->band->radiorev = wlc_hw->band->radiorev;
4644 /* default contention windows size limits */
4645 wlc_hw->band->CWmin = APHY_CWMIN;
4646 wlc_hw->band->CWmax = PHY_CWMAX;
4648 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4654 /* disable core to match driver "down" state */
4655 brcms_c_coredisable(wlc_hw);
4657 /* Match driver "down" state */
4658 ai_pci_down(wlc_hw->sih);
4660 /* turn off pll and xtal to match driver "down" state */
4661 brcms_b_xtal(wlc_hw, OFF);
4663 /* *******************************************************************
4664 * The hardware is in the DOWN state at this point. D11 core
4665 * or cores are in reset with clocks off, and the board PLLs
4666 * are off if possible.
4668 * Beyond this point, wlc->sbclk == false and chip registers
4669 * should not be touched.
4670 *********************************************************************
4673 /* init etheraddr state variables */
4674 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4676 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4677 is_zero_ether_addr(wlc_hw->etheraddr)) {
4678 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4684 brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4685 wlc_hw->deviceid, wlc_hw->_nbands,
4686 ai_get_boardtype(wlc_hw->sih));
4691 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4696 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4699 unit = wlc->pub->unit;
4701 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4702 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4703 wlc->band->antgain = 8;
4704 } else if (wlc->band->antgain == -1) {
4705 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4706 " srom, using 2dB\n", unit, __func__);
4707 wlc->band->antgain = 8;
4710 /* Older sroms specified gain in whole dbm only. In order
4711 * be able to specify qdbm granularity and remain backward
4712 * compatible the whole dbms are now encoded in only
4713 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4714 * 6 bit signed number ranges from -32 - 31.
4718 * 0xc1 = 1.75 db (1 + 3 quarters),
4719 * 0x3f = -1 (-1 + 0 quarters),
4720 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4721 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4723 gain = wlc->band->antgain & 0x3f;
4724 gain <<= 2; /* Sign extend */
4726 fract = (wlc->band->antgain & 0xc0) >> 6;
4727 wlc->band->antgain = 4 * gain + fract;
4731 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4736 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4738 unit = wlc->pub->unit;
4739 bandtype = wlc->band->bandtype;
4741 /* get antennas available */
4742 if (bandtype == BRCM_BAND_5G)
4743 aa = sprom->ant_available_a;
4745 aa = sprom->ant_available_bg;
4747 if ((aa < 1) || (aa > 15)) {
4748 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4749 " srom (0x%x), using 3\n", unit, __func__, aa);
4753 /* reset the defaults if we have a single antenna */
4755 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4756 wlc->stf->txant = ANT_TX_FORCE_0;
4757 } else if (aa == 2) {
4758 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4759 wlc->stf->txant = ANT_TX_FORCE_1;
4763 /* Compute Antenna Gain */
4764 if (bandtype == BRCM_BAND_5G)
4765 wlc->band->antgain = sprom->antenna_gain.a1;
4767 wlc->band->antgain = sprom->antenna_gain.a0;
4769 brcms_c_attach_antgain_init(wlc);
4774 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4777 struct brcms_band *band;
4778 struct brcms_bss_info *bi = wlc->default_bss;
4780 /* init default and target BSS with some sane initial values */
4781 memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
4782 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4784 /* fill the default channel as the first valid channel
4785 * starting from the 2G channels
4787 chanspec = ch20mhz_chspec(1);
4788 wlc->home_chanspec = bi->chanspec = chanspec;
4790 /* find the band of our default channel */
4792 if (wlc->pub->_nbands > 1 &&
4793 band->bandunit != chspec_bandunit(chanspec))
4794 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4796 /* init bss rates to the band specific default rate set */
4797 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4798 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4799 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4800 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4802 if (wlc->pub->_n_enab & SUPPORT_11N)
4803 bi->flags |= BRCMS_BSS_HT;
4806 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4809 struct brcms_band *band;
4811 for (i = 0; i < wlc->pub->_nbands; i++) {
4812 band = wlc->bandstate[i];
4813 if (band->bandtype == BRCM_BAND_5G) {
4814 if ((bwcap == BRCMS_N_BW_40ALL)
4815 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4816 band->mimo_cap_40 = true;
4818 band->mimo_cap_40 = false;
4820 if (bwcap == BRCMS_N_BW_40ALL)
4821 band->mimo_cap_40 = true;
4823 band->mimo_cap_40 = false;
4828 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4830 /* free timer state */
4832 brcms_free_timer(wlc->wdtimer);
4833 wlc->wdtimer = NULL;
4835 if (wlc->radio_timer) {
4836 brcms_free_timer(wlc->radio_timer);
4837 wlc->radio_timer = NULL;
4841 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4844 brcms_c_antsel_detach(wlc->asi);
4849 brcms_c_ampdu_detach(wlc->ampdu);
4853 brcms_c_stf_detach(wlc);
4859 static int brcms_b_detach(struct brcms_c_info *wlc)
4862 struct brcms_hw_band *band;
4863 struct brcms_hardware *wlc_hw = wlc->hw;
4868 brcms_b_detach_dmapio(wlc_hw);
4870 band = wlc_hw->band;
4871 for (i = 0; i < wlc_hw->_nbands; i++) {
4873 /* Detach this band's phy */
4874 wlc_phy_detach(band->pi);
4877 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4880 /* Free shared phy state */
4881 kfree(wlc_hw->phy_sh);
4883 wlc_phy_shim_detach(wlc_hw->physhim);
4886 ai_detach(wlc_hw->sih);
4895 * Return a count of the number of driver callbacks still pending.
4897 * General policy is that brcms_c_detach can only dealloc/free software states.
4898 * It can NOT touch hardware registers since the d11core may be in reset and
4899 * clock may not be available.
4900 * One exception is sb register access, which is possible if crystal is turned
4901 * on after "down" state, driver should avoid software timer with the exception
4904 uint brcms_c_detach(struct brcms_c_info *wlc)
4911 callbacks += brcms_b_detach(wlc);
4913 /* delete software timers */
4914 if (!brcms_c_radio_monitor_stop(wlc))
4917 brcms_c_channel_mgr_detach(wlc->cmi);
4919 brcms_c_timers_deinit(wlc);
4921 brcms_c_detach_module(wlc);
4923 brcms_c_detach_mfree(wlc);
4927 /* update state that depends on the current value of "ap" */
4928 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4930 /* STA-BSS; short capable */
4931 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4934 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4935 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4937 if (wlc_hw->wlc->pub->hw_up)
4940 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4943 * Enable pll and xtal, initialize the power control registers,
4944 * and force fastclock for the remainder of brcms_c_up().
4946 brcms_b_xtal(wlc_hw, ON);
4947 ai_clkctl_init(wlc_hw->sih);
4948 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4951 * TODO: test suspend/resume
4953 * AI chip doesn't restore bar0win2 on
4954 * hibernation/resume, need sw fixup
4958 * Inform phy that a POR reset has occurred so
4959 * it does a complete phy init
4961 wlc_phy_por_inform(wlc_hw->band->pi);
4963 wlc_hw->ucode_loaded = false;
4964 wlc_hw->wlc->pub->hw_up = true;
4966 if ((wlc_hw->boardflags & BFL_FEM)
4967 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4969 (wlc_hw->boardrev >= 0x1250
4970 && (wlc_hw->boardflags & BFL_FEM_BT)))
4971 ai_epa_4313war(wlc_hw->sih);
4975 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4977 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4980 * Enable pll and xtal, initialize the power control registers,
4981 * and force fastclock for the remainder of brcms_c_up().
4983 brcms_b_xtal(wlc_hw, ON);
4984 ai_clkctl_init(wlc_hw->sih);
4985 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4988 * Configure pci/pcmcia here instead of in brcms_c_attach()
4989 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
4991 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
4995 * Need to read the hwradio status here to cover the case where the
4996 * system is loaded with the hw radio disabled. We do not want to
4997 * bring the driver up in this case.
4999 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
5000 /* put SB PCI in down state again */
5001 ai_pci_down(wlc_hw->sih);
5002 brcms_b_xtal(wlc_hw, OFF);
5006 ai_pci_up(wlc_hw->sih);
5008 /* reset the d11 core */
5009 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5014 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5017 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5019 /* FULLY enable dynamic power control and d11 core interrupt */
5020 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5021 brcms_intrson(wlc_hw->wlc->wl);
5026 * Write WME tunable parameters for retransmit/max rate
5027 * from wlc struct to ucode
5029 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5033 /* Need clock to do this */
5037 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5038 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5039 wlc->wme_retries[ac]);
5042 /* make interface operational */
5043 int brcms_c_up(struct brcms_c_info *wlc)
5045 struct ieee80211_channel *ch;
5047 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5049 /* HW is turned off so don't try to access it */
5050 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5053 if (!wlc->pub->hw_up) {
5054 brcms_b_hw_up(wlc->hw);
5055 wlc->pub->hw_up = true;
5058 if ((wlc->pub->boardflags & BFL_FEM)
5059 && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5060 if (wlc->pub->boardrev >= 0x1250
5061 && (wlc->pub->boardflags & BFL_FEM_BT))
5062 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5063 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5065 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5066 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5070 * Need to read the hwradio status here to cover the case where the
5071 * system is loaded with the hw radio disabled. We do not want to bring
5072 * the driver up in this case. If radio is disabled, abort up, lower
5073 * power, start radio timer and return 0(for NDIS) don't call
5074 * radio_update to avoid looping brcms_c_up.
5076 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5078 if (!wlc->pub->radio_disabled) {
5079 int status = brcms_b_up_prep(wlc->hw);
5080 if (status == -ENOMEDIUM) {
5082 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5083 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5084 mboolset(wlc->pub->radio_disabled,
5085 WL_RADIO_HW_DISABLE);
5087 if (bsscfg->enable && bsscfg->BSS)
5088 brcms_err(wlc->hw->d11core,
5089 "wl%d: up: rfdisable -> "
5090 "bsscfg_disable()\n",
5096 if (wlc->pub->radio_disabled) {
5097 brcms_c_radio_monitor_start(wlc);
5101 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5104 brcms_c_radio_monitor_stop(wlc);
5106 /* Set EDCF hostflags */
5107 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5109 brcms_init(wlc->wl);
5110 wlc->pub->up = true;
5112 if (wlc->bandinit_pending) {
5113 ch = wlc->pub->ieee_hw->conf.channel;
5114 brcms_c_suspend_mac_and_wait(wlc);
5115 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5116 wlc->bandinit_pending = false;
5117 brcms_c_enable_mac(wlc);
5120 brcms_b_up_finish(wlc->hw);
5122 /* Program the TX wme params with the current settings */
5123 brcms_c_wme_retries_write(wlc);
5125 /* start one second watchdog timer */
5126 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5127 wlc->WDarmed = true;
5129 /* ensure antenna config is up to date */
5130 brcms_c_stf_phy_txant_upd(wlc);
5131 /* ensure LDPC config is in sync */
5132 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5137 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5144 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5152 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5154 /* disable interrupts */
5156 wlc_hw->wlc->macintmask = 0;
5158 /* now disable interrupts */
5159 brcms_intrsoff(wlc_hw->wlc->wl);
5161 /* ensure we're running on the pll clock again */
5162 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5164 /* down phy at the last of this stage */
5165 callbacks += wlc_phy_down(wlc_hw->band->pi);
5170 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5179 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5181 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5184 wlc_hw->sbclk = false;
5185 wlc_hw->clk = false;
5186 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5188 /* reclaim any posted packets */
5189 brcms_c_flushqueues(wlc_hw->wlc);
5192 /* Reset and disable the core */
5193 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5194 if (bcma_read32(wlc_hw->d11core,
5195 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5196 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5197 callbacks += brcms_reset(wlc_hw->wlc->wl);
5198 brcms_c_coredisable(wlc_hw);
5201 /* turn off primary xtal and pll */
5202 if (!wlc_hw->noreset) {
5203 ai_pci_down(wlc_hw->sih);
5204 brcms_b_xtal(wlc_hw, OFF);
5212 * Mark the interface nonoperational, stop the software mechanisms,
5213 * disable the hardware, free any transient buffer state.
5214 * Return a count of the number of driver callbacks still pending.
5216 uint brcms_c_down(struct brcms_c_info *wlc)
5221 bool dev_gone = false;
5223 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
5225 /* check if we are already in the going down path */
5226 if (wlc->going_down) {
5227 brcms_err(wlc->hw->d11core,
5228 "wl%d: %s: Driver going down so return\n",
5229 wlc->pub->unit, __func__);
5235 wlc->going_down = true;
5237 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5239 dev_gone = brcms_deviceremoved(wlc);
5241 /* Call any registered down handlers */
5242 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5243 if (wlc->modulecb[i].down_fn)
5245 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5248 /* cancel the watchdog timer */
5250 if (!brcms_del_timer(wlc->wdtimer))
5252 wlc->WDarmed = false;
5254 /* cancel all other timers */
5255 callbacks += brcms_c_down_del_timer(wlc);
5257 wlc->pub->up = false;
5259 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5261 callbacks += brcms_b_down_finish(wlc->hw);
5263 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5266 wlc->going_down = false;
5270 /* Set the current gmode configuration */
5271 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5275 struct brcms_c_rateset rs;
5276 /* Default to 54g Auto */
5277 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5278 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5279 bool shortslot_restrict = false; /* Restrict association to stations
5280 * that support shortslot
5282 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5283 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5284 int preamble = BRCMS_PLCP_LONG;
5285 bool preamble_restrict = false; /* Restrict association to stations
5286 * that support short preambles
5288 struct brcms_band *band;
5290 /* if N-support is enabled, allow Gmode set as long as requested
5291 * Gmode is not GMODE_LEGACY_B
5293 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5296 /* verify that we are dealing with 2G band and grab the band pointer */
5297 if (wlc->band->bandtype == BRCM_BAND_2G)
5299 else if ((wlc->pub->_nbands > 1) &&
5300 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5301 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5305 /* update configuration value */
5307 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5309 /* Clear rateset override */
5310 memset(&rs, 0, sizeof(struct brcms_c_rateset));
5313 case GMODE_LEGACY_B:
5314 shortslot = BRCMS_SHORTSLOT_OFF;
5315 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5323 /* Accept defaults */
5328 preamble = BRCMS_PLCP_SHORT;
5329 preamble_restrict = true;
5332 case GMODE_PERFORMANCE:
5333 shortslot = BRCMS_SHORTSLOT_ON;
5334 shortslot_restrict = true;
5336 preamble = BRCMS_PLCP_SHORT;
5337 preamble_restrict = true;
5342 brcms_err(wlc->hw->d11core, "wl%d: %s: invalid gmode %d\n",
5343 wlc->pub->unit, __func__, gmode);
5347 band->gmode = gmode;
5349 wlc->shortslot_override = shortslot;
5351 /* Use the default 11g rateset */
5353 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5356 for (i = 0; i < rs.count; i++) {
5357 if (rs.rates[i] == BRCM_RATE_6M
5358 || rs.rates[i] == BRCM_RATE_12M
5359 || rs.rates[i] == BRCM_RATE_24M)
5360 rs.rates[i] |= BRCMS_RATE_FLAG;
5364 /* Set default bss rateset */
5365 wlc->default_bss->rateset.count = rs.count;
5366 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5367 sizeof(wlc->default_bss->rateset.rates));
5372 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5377 if (wlc->stf->txstreams == WL_11N_3x3)
5382 /* force GMODE_AUTO if NMODE is ON */
5383 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5384 if (nmode == WL_11N_3x3)
5385 wlc->pub->_n_enab = SUPPORT_HT;
5387 wlc->pub->_n_enab = SUPPORT_11N;
5388 wlc->default_bss->flags |= BRCMS_BSS_HT;
5389 /* add the mcs rates to the default and hw ratesets */
5390 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5391 wlc->stf->txstreams);
5392 for (i = 0; i < wlc->pub->_nbands; i++)
5393 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5394 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5400 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5401 struct brcms_c_rateset *rs_arg)
5403 struct brcms_c_rateset rs, new;
5406 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5408 /* check for bad count value */
5409 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5412 /* try the current band */
5413 bandunit = wlc->band->bandunit;
5414 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5415 if (brcms_c_rate_hwrs_filter_sort_validate
5416 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5417 wlc->stf->txstreams))
5420 /* try the other band */
5421 if (brcms_is_mband_unlocked(wlc)) {
5422 bandunit = OTHERBANDUNIT(wlc);
5423 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5424 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5426 bandstate[bandunit]->
5428 wlc->stf->txstreams))
5435 /* apply new rateset */
5436 memcpy(&wlc->default_bss->rateset, &new,
5437 sizeof(struct brcms_c_rateset));
5438 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5439 sizeof(struct brcms_c_rateset));
5443 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5448 if (wlc->bsscfg->associated)
5449 r = wlc->bsscfg->current_bss->rateset.rates[0];
5451 r = wlc->default_bss->rateset.rates[0];
5453 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5456 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5458 u16 chspec = ch20mhz_chspec(channel);
5460 if (channel < 0 || channel > MAXCHANNEL)
5463 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5467 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5468 if (wlc->band->bandunit != chspec_bandunit(chspec))
5469 wlc->bandinit_pending = true;
5471 wlc->bandinit_pending = false;
5474 wlc->default_bss->chanspec = chspec;
5475 /* brcms_c_BSSinit() will sanitize the rateset before
5477 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5478 brcms_c_set_home_chanspec(wlc, chspec);
5479 brcms_c_suspend_mac_and_wait(wlc);
5480 brcms_c_set_chanspec(wlc, chspec);
5481 brcms_c_enable_mac(wlc);
5486 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5490 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5491 lrl < 1 || lrl > RETRY_SHORT_MAX)
5497 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5499 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5500 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5501 EDCF_SHORT, wlc->SRL);
5502 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5503 EDCF_LONG, wlc->LRL);
5505 brcms_c_wme_retries_write(wlc);
5510 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5511 struct brcm_rateset *currs)
5513 struct brcms_c_rateset *rs;
5515 if (wlc->pub->associated)
5516 rs = &wlc->bsscfg->current_bss->rateset;
5518 rs = &wlc->default_bss->rateset;
5520 /* Copy only legacy rateset section */
5521 currs->count = rs->count;
5522 memcpy(&currs->rates, &rs->rates, rs->count);
5525 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5527 struct brcms_c_rateset internal_rs;
5530 if (rs->count > BRCMS_NUMRATES)
5533 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
5535 /* Copy only legacy rateset section */
5536 internal_rs.count = rs->count;
5537 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5539 /* merge rateset coming in with the current mcsset */
5540 if (wlc->pub->_n_enab & SUPPORT_11N) {
5541 struct brcms_bss_info *mcsset_bss;
5542 if (wlc->bsscfg->associated)
5543 mcsset_bss = wlc->bsscfg->current_bss;
5545 mcsset_bss = wlc->default_bss;
5546 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5550 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5552 brcms_c_ofdm_rateset_war(wlc);
5557 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5559 if (period < DOT11_MIN_BEACON_PERIOD ||
5560 period > DOT11_MAX_BEACON_PERIOD)
5563 wlc->default_bss->beacon_period = period;
5567 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5569 return wlc->band->phytype;
5572 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5574 wlc->shortslot_override = sslot_override;
5577 * shortslot is an 11g feature, so no more work if we are
5578 * currently on the 5G band
5580 if (wlc->band->bandtype == BRCM_BAND_5G)
5583 if (wlc->pub->up && wlc->pub->associated) {
5584 /* let watchdog or beacon processing update shortslot */
5585 } else if (wlc->pub->up) {
5586 /* unassociated shortslot is off */
5587 brcms_c_switch_shortslot(wlc, false);
5589 /* driver is down, so just update the brcms_c_info
5591 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5592 wlc->shortslot = false;
5595 (wlc->shortslot_override ==
5596 BRCMS_SHORTSLOT_ON);
5601 * register watchdog and down handlers.
5603 int brcms_c_module_register(struct brcms_pub *pub,
5604 const char *name, struct brcms_info *hdl,
5605 int (*d_fn)(void *handle))
5607 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5610 /* find an empty entry and just add, no duplication check! */
5611 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5612 if (wlc->modulecb[i].name[0] == '\0') {
5613 strncpy(wlc->modulecb[i].name, name,
5614 sizeof(wlc->modulecb[i].name) - 1);
5615 wlc->modulecb[i].hdl = hdl;
5616 wlc->modulecb[i].down_fn = d_fn;
5624 /* unregister module callbacks */
5625 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5626 struct brcms_info *hdl)
5628 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5634 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5635 if (!strcmp(wlc->modulecb[i].name, name) &&
5636 (wlc->modulecb[i].hdl == hdl)) {
5637 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
5642 /* table not found! */
5646 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5648 struct pci_dev *pcidev = core->bus->host_pci;
5649 u16 vendor = pcidev->vendor;
5650 u16 device = pcidev->device;
5652 if (vendor != PCI_VENDOR_ID_BROADCOM) {
5653 pr_err("unknown vendor id %04x\n", vendor);
5657 if (device == BCM43224_D11N_ID_VEN1 || device == BCM43224_CHIP_ID)
5659 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5661 if (device == BCM4313_D11N2G_ID)
5663 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5666 pr_err("unknown device id %04x\n", device);
5670 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5672 struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5674 if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5677 pr_err("unknown chip id %04x\n", chipinfo->id);
5681 bool brcms_c_chipmatch(struct bcma_device *core)
5683 switch (core->bus->hosttype) {
5684 case BCMA_HOSTTYPE_PCI:
5685 return brcms_c_chipmatch_pci(core);
5686 case BCMA_HOSTTYPE_SOC:
5687 return brcms_c_chipmatch_soc(core);
5689 pr_err("unknown host type: %i\n", core->bus->hosttype);
5694 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5699 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5700 if (is_ofdm_rate(rate))
5701 table_ptr = M_RT_DIRMAP_A;
5703 table_ptr = M_RT_DIRMAP_B;
5705 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5706 * the index into the rate table.
5708 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5709 index = phy_rate & 0xf;
5711 /* Find the SHM pointer to the rate table entry by looking in the
5714 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5718 * bcmc_fid_generate:
5719 * Generate frame ID for a BCMC packet. The frag field is not used
5720 * for MC frames so is used as part of the sequence number.
5723 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5728 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5732 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5739 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5745 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5746 * is less than or equal to the rate of the immediately previous
5749 rspec = brcms_basic_rate(wlc, rspec);
5750 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5752 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5753 (DOT11_ACK_LEN + FCS_LEN));
5758 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
5761 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
5765 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
5769 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5770 * is less than or equal to the rate of the immediately previous
5773 rspec = brcms_basic_rate(wlc, rspec);
5774 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
5775 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
5776 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
5780 /* brcms_c_compute_frame_dur()
5782 * Calculate the 802.11 MAC header DUR field for MPDU
5783 * DUR for a single frame = 1 SIFS + 1 ACK
5784 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
5786 * rate MPDU rate in unit of 500kbps
5787 * next_frag_len next MPDU length in bytes
5788 * preamble_type use short/GF or long/MM PLCP header
5791 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
5792 u8 preamble_type, uint next_frag_len)
5796 sifs = get_sifs(wlc->band);
5799 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
5801 if (next_frag_len) {
5802 /* Double the current DUR to get 2 SIFS + 2 ACKs */
5804 /* add another SIFS and the frag time */
5807 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
5813 /* The opposite of brcms_c_calc_frame_time */
5815 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
5816 u8 preamble_type, uint dur)
5818 uint nsyms, mac_len, Ndps, kNdps;
5819 uint rate = rspec2rate(ratespec);
5821 if (is_mcs_rate(ratespec)) {
5822 uint mcs = ratespec & RSPEC_RATE_MASK;
5823 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
5824 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
5825 /* payload calculation matches that of regular ofdm */
5826 if (wlc->band->bandtype == BRCM_BAND_2G)
5827 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
5828 /* kNdbps = kbps * 4 */
5829 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
5830 rspec_issgi(ratespec)) * 4;
5831 nsyms = dur / APHY_SYMBOL_TIME;
5834 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
5835 } else if (is_ofdm_rate(ratespec)) {
5836 dur -= APHY_PREAMBLE_TIME;
5837 dur -= APHY_SIGNAL_TIME;
5838 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
5840 nsyms = dur / APHY_SYMBOL_TIME;
5843 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
5845 if (preamble_type & BRCMS_SHORT_PREAMBLE)
5846 dur -= BPHY_PLCP_SHORT_TIME;
5848 dur -= BPHY_PLCP_TIME;
5849 mac_len = dur * rate;
5850 /* divide out factor of 2 in rate (1/2 mbps) */
5851 mac_len = mac_len / 8 / 2;
5857 * Return true if the specified rate is supported by the specified band.
5858 * BRCM_BAND_AUTO indicates the current band.
5860 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
5863 struct brcms_c_rateset *hw_rateset;
5866 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
5867 hw_rateset = &wlc->band->hw_rateset;
5868 else if (wlc->pub->_nbands > 1)
5869 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
5871 /* other band specified and we are a single band device */
5874 /* check if this is a mimo rate */
5875 if (is_mcs_rate(rspec)) {
5876 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
5879 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
5882 for (i = 0; i < hw_rateset->count; i++)
5883 if (hw_rateset->rates[i] == rspec2rate(rspec))
5887 brcms_err(wlc->hw->d11core, "wl%d: valid_rate: rate spec 0x%x "
5888 "not in hw_rateset\n", wlc->pub->unit, rspec);
5894 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
5897 struct bcma_device *core = wlc->hw->d11core;
5898 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
5899 u8 rate = int_val & NRATE_RATE_MASK;
5901 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
5902 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
5903 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
5904 == NRATE_OVERRIDE_MCS_ONLY);
5910 /* validate the combination of rate/mcs/stf is allowed */
5911 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
5912 /* mcs only allowed when nmode */
5913 if (stf > PHY_TXC1_MODE_SDM) {
5914 brcms_err(core, "wl%d: %s: Invalid stf\n",
5915 wlc->pub->unit, __func__);
5920 /* mcs 32 is a special case, DUP mode 40 only */
5922 if (!CHSPEC_IS40(wlc->home_chanspec) ||
5923 ((stf != PHY_TXC1_MODE_SISO)
5924 && (stf != PHY_TXC1_MODE_CDD))) {
5925 brcms_err(core, "wl%d: %s: Invalid mcs 32\n",
5926 wlc->pub->unit, __func__);
5930 /* mcs > 7 must use stf SDM */
5931 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
5932 /* mcs > 7 must use stf SDM */
5933 if (stf != PHY_TXC1_MODE_SDM) {
5934 brcms_dbg_mac80211(core, "wl%d: enabling "
5935 "SDM mode for mcs %d\n",
5936 wlc->pub->unit, rate);
5937 stf = PHY_TXC1_MODE_SDM;
5941 * MCS 0-7 may use SISO, CDD, and for
5944 if ((stf > PHY_TXC1_MODE_STBC) ||
5945 (!BRCMS_STBC_CAP_PHY(wlc)
5946 && (stf == PHY_TXC1_MODE_STBC))) {
5947 brcms_err(core, "wl%d: %s: Invalid STBC\n",
5948 wlc->pub->unit, __func__);
5953 } else if (is_ofdm_rate(rate)) {
5954 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
5955 brcms_err(core, "wl%d: %s: Invalid OFDM\n",
5956 wlc->pub->unit, __func__);
5960 } else if (is_cck_rate(rate)) {
5961 if ((cur_band->bandtype != BRCM_BAND_2G)
5962 || (stf != PHY_TXC1_MODE_SISO)) {
5963 brcms_err(core, "wl%d: %s: Invalid CCK\n",
5964 wlc->pub->unit, __func__);
5969 brcms_err(core, "wl%d: %s: Unknown rate type\n",
5970 wlc->pub->unit, __func__);
5974 /* make sure multiple antennae are available for non-siso rates */
5975 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
5976 brcms_err(core, "wl%d: %s: SISO antenna but !SISO "
5977 "request\n", wlc->pub->unit, __func__);
5984 rspec |= RSPEC_MIMORATE;
5985 /* For STBC populate the STC field of the ratespec */
5986 if (stf == PHY_TXC1_MODE_STBC) {
5988 stc = 1; /* Nss for single stream is always 1 */
5989 rspec |= (stc << RSPEC_STC_SHIFT);
5993 rspec |= (stf << RSPEC_STF_SHIFT);
5995 if (override_mcs_only)
5996 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
5999 rspec |= RSPEC_SHORT_GI;
6002 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6011 * Compute PLCP, but only requires actual rate and length of pkt.
6012 * Rate is given in the driver standard multiple of 500 kbps.
6013 * le is set for 11 Mbps rate if necessary.
6014 * Broken out for PRQ.
6017 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6018 uint length, u8 *plcp)
6031 usec = (length << 4) / 11;
6032 if ((length << 4) - (usec * 11) > 0)
6036 usec = (length << 3) / 11;
6037 if ((length << 3) - (usec * 11) > 0) {
6039 if ((usec * 11) - (length << 3) >= 8)
6040 le = D11B_PLCP_SIGNAL_LE;
6045 brcms_err(wlc->hw->d11core,
6046 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6048 rate_500 = BRCM_RATE_1M;
6052 /* PLCP signal byte */
6053 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6054 /* PLCP service byte */
6055 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6056 /* PLCP length u16, little endian */
6057 plcp[2] = usec & 0xff;
6058 plcp[3] = (usec >> 8) & 0xff;
6064 /* Rate: 802.11 rate code, length: PSDU length in octets */
6065 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6067 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6069 if (rspec_is40mhz(rspec) || (mcs == 32))
6070 plcp[0] |= MIMO_PLCP_40MHZ;
6071 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6072 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6073 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6074 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6078 /* Rate: 802.11 rate code, length: PSDU length in octets */
6080 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6084 int rate = rspec2rate(rspec);
6087 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6090 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6091 memset(plcp, 0, D11_PHY_HDR_LEN);
6092 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6094 tmp = (length & 0xfff) << 5;
6095 plcp[2] |= (tmp >> 16) & 0xff;
6096 plcp[1] |= (tmp >> 8) & 0xff;
6097 plcp[0] |= tmp & 0xff;
6100 /* Rate: 802.11 rate code, length: PSDU length in octets */
6101 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6102 uint length, u8 *plcp)
6104 int rate = rspec2rate(rspec);
6106 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6110 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6111 uint length, u8 *plcp)
6113 if (is_mcs_rate(rspec))
6114 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6115 else if (is_ofdm_rate(rspec))
6116 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6118 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6121 /* brcms_c_compute_rtscts_dur()
6123 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6124 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6125 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6127 * cts cts-to-self or rts/cts
6128 * rts_rate rts or cts rate in unit of 500kbps
6129 * rate next MPDU rate in unit of 500kbps
6130 * frame_len next MPDU frame length in bytes
6133 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6135 u32 frame_rate, u8 rts_preamble_type,
6136 u8 frame_preamble_type, uint frame_len, bool ba)
6140 sifs = get_sifs(wlc->band);
6146 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6154 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6158 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6159 BRCMS_SHORT_PREAMBLE);
6162 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6163 frame_preamble_type);
6167 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6172 if (BRCMS_ISLCNPHY(wlc->band)) {
6173 bw = PHY_TXC1_BW_20MHZ;
6175 bw = rspec_get_bw(rspec);
6176 /* 10Mhz is not supported yet */
6177 if (bw < PHY_TXC1_BW_20MHZ) {
6178 brcms_err(wlc->hw->d11core, "phytxctl1_calc: bw %d is "
6179 "not supported yet, set to 20L\n", bw);
6180 bw = PHY_TXC1_BW_20MHZ;
6184 if (is_mcs_rate(rspec)) {
6185 uint mcs = rspec & RSPEC_RATE_MASK;
6187 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6188 phyctl1 = rspec_phytxbyte2(rspec);
6189 /* set the upper byte of phyctl1 */
6190 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6191 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6192 && !BRCMS_ISSSLPNPHY(wlc->band)) {
6194 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6195 * Data Rate. Eventually MIMOPHY would also be converted to
6198 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6199 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6200 } else { /* legacy OFDM/CCK */
6202 /* get the phyctl byte from rate phycfg table */
6203 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6205 brcms_err(wlc->hw->d11core, "phytxctl1_calc: wrong "
6206 "legacy OFDM/CCK rate\n");
6209 /* set the upper byte of phyctl1 */
6211 (bw | (phycfg << 8) |
6212 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6218 * Add struct d11txh, struct cck_phy_hdr.
6220 * 'p' data must start with 802.11 MAC header
6221 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6223 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6227 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6228 struct sk_buff *p, struct scb *scb, uint frag,
6229 uint nfrags, uint queue, uint next_frag_len)
6231 struct ieee80211_hdr *h;
6233 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6234 int len, phylen, rts_phylen;
6235 u16 mch, phyctl, xfts, mainrates;
6236 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6237 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6238 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6239 bool use_rts = false;
6240 bool use_cts = false;
6241 bool use_rifs = false;
6242 bool short_preamble[2] = { false, false };
6243 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6244 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6245 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6246 struct ieee80211_rts *rts = NULL;
6249 bool hwtkmic = false;
6250 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6251 #define ANTCFG_NONE 0xFF
6252 u8 antcfg = ANTCFG_NONE;
6253 u8 fbantcfg = ANTCFG_NONE;
6254 uint phyctl1_stf = 0;
6256 struct ieee80211_tx_rate *txrate[2];
6258 struct ieee80211_tx_info *tx_info;
6261 u8 mimo_preamble_type;
6263 /* locate 802.11 MAC header */
6264 h = (struct ieee80211_hdr *)(p->data);
6265 qos = ieee80211_is_data_qos(h->frame_control);
6267 /* compute length of frame in bytes for use in PLCP computations */
6269 phylen = len + FCS_LEN;
6272 tx_info = IEEE80211_SKB_CB(p);
6275 plcp = skb_push(p, D11_PHY_HDR_LEN);
6277 /* add Broadcom tx descriptor header */
6278 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6279 memset(txh, 0, D11_TXH_LEN);
6282 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6283 /* non-AP STA should never use BCMC queue */
6284 if (queue == TX_BCMC_FIFO) {
6285 brcms_err(wlc->hw->d11core,
6286 "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6287 wlc->pub->unit, __func__);
6288 frameid = bcmc_fid_generate(wlc, NULL, txh);
6290 /* Increment the counter for first fragment */
6291 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6292 scb->seqnum[p->priority]++;
6294 /* extract fragment number from frame first */
6295 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6296 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6297 h->seq_ctrl = cpu_to_le16(seq);
6299 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6300 (queue & TXFID_QUEUE_MASK);
6303 frameid |= queue & TXFID_QUEUE_MASK;
6305 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6306 if (ieee80211_is_beacon(h->frame_control))
6307 mcl |= TXC_IGNOREPMQ;
6309 txrate[0] = tx_info->control.rates;
6310 txrate[1] = txrate[0] + 1;
6313 * if rate control algorithm didn't give us a fallback
6314 * rate, use the primary rate
6316 if (txrate[1]->idx < 0)
6317 txrate[1] = txrate[0];
6319 for (k = 0; k < hw->max_rates; k++) {
6320 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6322 if ((txrate[k]->idx >= 0)
6323 && (txrate[k]->idx <
6324 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6326 hw->wiphy->bands[tx_info->band]->
6327 bitrates[txrate[k]->idx].hw_value;
6330 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6333 rspec[k] = BRCM_RATE_1M;
6336 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6337 NRATE_MCS_INUSE | txrate[k]->idx);
6341 * Currently only support same setting for primay and
6342 * fallback rates. Unify flags for each rate into a
6343 * single value for the frame
6347 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6350 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6355 * determine and validate primary rate
6356 * and fallback rates
6358 if (!rspec_active(rspec[k])) {
6359 rspec[k] = BRCM_RATE_1M;
6361 if (!is_multicast_ether_addr(h->addr1)) {
6362 /* set tx antenna config */
6363 brcms_c_antsel_antcfg_get(wlc->asi, false,
6364 false, 0, 0, &antcfg, &fbantcfg);
6369 phyctl1_stf = wlc->stf->ss_opmode;
6371 if (wlc->pub->_n_enab & SUPPORT_11N) {
6372 for (k = 0; k < hw->max_rates; k++) {
6374 * apply siso/cdd to single stream mcs's or ofdm
6375 * if rspec is auto selected
6377 if (((is_mcs_rate(rspec[k]) &&
6378 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6379 is_ofdm_rate(rspec[k]))
6380 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6381 || !(rspec[k] & RSPEC_OVERRIDE))) {
6382 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6384 /* For SISO MCS use STBC if possible */
6385 if (is_mcs_rate(rspec[k])
6386 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6389 /* Nss for single stream is always 1 */
6391 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6393 (stc << RSPEC_STC_SHIFT);
6396 (phyctl1_stf << RSPEC_STF_SHIFT);
6400 * Is the phy configured to use 40MHZ frames? If
6401 * so then pick the desired txbw
6403 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6404 /* default txbw is 20in40 SB */
6405 mimo_ctlchbw = mimo_txbw =
6406 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6408 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6410 if (is_mcs_rate(rspec[k])) {
6411 /* mcs 32 must be 40b/w DUP */
6412 if ((rspec[k] & RSPEC_RATE_MASK)
6415 PHY_TXC1_BW_40MHZ_DUP;
6417 } else if (wlc->mimo_40txbw != AUTO)
6418 mimo_txbw = wlc->mimo_40txbw;
6419 /* else check if dst is using 40 Mhz */
6420 else if (scb->flags & SCB_IS40)
6421 mimo_txbw = PHY_TXC1_BW_40MHZ;
6422 } else if (is_ofdm_rate(rspec[k])) {
6423 if (wlc->ofdm_40txbw != AUTO)
6424 mimo_txbw = wlc->ofdm_40txbw;
6425 } else if (wlc->cck_40txbw != AUTO) {
6426 mimo_txbw = wlc->cck_40txbw;
6430 * mcs32 is 40 b/w only.
6431 * This is possible for probe packets on
6434 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6436 rspec[k] = RSPEC_MIMORATE;
6438 mimo_txbw = PHY_TXC1_BW_20MHZ;
6441 /* Set channel width */
6442 rspec[k] &= ~RSPEC_BW_MASK;
6443 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6444 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6446 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6448 /* Disable short GI, not supported yet */
6449 rspec[k] &= ~RSPEC_SHORT_GI;
6451 mimo_preamble_type = BRCMS_MM_PREAMBLE;
6452 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6453 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6455 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6456 && (!is_mcs_rate(rspec[k]))) {
6457 brcms_err(wlc->hw->d11core,
6458 "wl%d: %s: IEEE80211_TX_"
6459 "RC_MCS != is_mcs_rate(rspec)\n",
6460 wlc->pub->unit, __func__);
6463 if (is_mcs_rate(rspec[k])) {
6464 preamble_type[k] = mimo_preamble_type;
6467 * if SGI is selected, then forced mm
6470 if ((rspec[k] & RSPEC_SHORT_GI)
6471 && is_single_stream(rspec[k] &
6473 preamble_type[k] = BRCMS_MM_PREAMBLE;
6476 /* should be better conditionalized */
6477 if (!is_mcs_rate(rspec[0])
6478 && (tx_info->control.rates[0].
6479 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6480 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6483 for (k = 0; k < hw->max_rates; k++) {
6484 /* Set ctrlchbw as 20Mhz */
6485 rspec[k] &= ~RSPEC_BW_MASK;
6486 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6488 /* for nphy, stf of ofdm frames must follow policies */
6489 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6490 rspec[k] &= ~RSPEC_STF_MASK;
6491 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6496 /* Reset these for use with AMPDU's */
6497 txrate[0]->count = 0;
6498 txrate[1]->count = 0;
6500 /* (2) PROTECTION, may change rspec */
6501 if ((ieee80211_is_data(h->frame_control) ||
6502 ieee80211_is_mgmt(h->frame_control)) &&
6503 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6506 /* (3) PLCP: determine PLCP header and MAC duration,
6507 * fill struct d11txh */
6508 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6509 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6510 memcpy(&txh->FragPLCPFallback,
6511 plcp_fallback, sizeof(txh->FragPLCPFallback));
6513 /* Length field now put in CCK FBR CRC field */
6514 if (is_cck_rate(rspec[1])) {
6515 txh->FragPLCPFallback[4] = phylen & 0xff;
6516 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6519 /* MIMO-RATE: need validation ?? */
6520 mainrates = is_ofdm_rate(rspec[0]) ?
6521 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6524 /* DUR field for main rate */
6525 if (!ieee80211_is_pspoll(h->frame_control) &&
6526 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6528 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6530 h->duration_id = cpu_to_le16(durid);
6531 } else if (use_rifs) {
6532 /* NAV protect to end of next max packet size */
6534 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6536 DOT11_MAX_FRAG_LEN);
6537 durid += RIFS_11N_TIME;
6538 h->duration_id = cpu_to_le16(durid);
6541 /* DUR field for fallback rate */
6542 if (ieee80211_is_pspoll(h->frame_control))
6543 txh->FragDurFallback = h->duration_id;
6544 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6545 txh->FragDurFallback = 0;
6547 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6548 preamble_type[1], next_frag_len);
6549 txh->FragDurFallback = cpu_to_le16(durid);
6552 /* (4) MAC-HDR: MacTxControlLow */
6554 mcl |= TXC_STARTMSDU;
6556 if (!is_multicast_ether_addr(h->addr1))
6557 mcl |= TXC_IMMEDACK;
6559 if (wlc->band->bandtype == BRCM_BAND_5G)
6560 mcl |= TXC_FREQBAND_5G;
6562 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6565 /* set AMIC bit if using hardware TKIP MIC */
6569 txh->MacTxControlLow = cpu_to_le16(mcl);
6571 /* MacTxControlHigh */
6574 /* Set fallback rate preamble type */
6575 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6576 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6577 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6578 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6581 /* MacFrameControl */
6582 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6583 txh->TxFesTimeNormal = cpu_to_le16(0);
6585 txh->TxFesTimeFallback = cpu_to_le16(0);
6588 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6591 txh->TxFrameID = cpu_to_le16(frameid);
6594 * TxStatus, Note the case of recreating the first frag of a suppressed
6595 * frame then we may need to reset the retry cnt's via the status reg
6597 txh->TxStatus = cpu_to_le16(status);
6600 * extra fields for ucode AMPDU aggregation, the new fields are added to
6601 * the END of previous structure so that it's compatible in driver.
6603 txh->MaxNMpdus = cpu_to_le16(0);
6604 txh->MaxABytes_MRT = cpu_to_le16(0);
6605 txh->MaxABytes_FBR = cpu_to_le16(0);
6606 txh->MinMBytes = cpu_to_le16(0);
6608 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6609 * furnish struct d11txh */
6610 /* RTS PLCP header and RTS frame */
6611 if (use_rts || use_cts) {
6612 if (use_rts && use_cts)
6615 for (k = 0; k < 2; k++) {
6616 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6621 if (!is_ofdm_rate(rts_rspec[0]) &&
6622 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6623 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6624 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6625 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6628 if (!is_ofdm_rate(rts_rspec[1]) &&
6629 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6630 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6631 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6632 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6635 /* RTS/CTS additions to MacTxControlLow */
6637 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6639 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6640 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6643 /* RTS PLCP header */
6644 rts_plcp = txh->RTSPhyHeader;
6646 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6648 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6650 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6652 /* fallback rate version of RTS PLCP header */
6653 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6655 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6656 sizeof(txh->RTSPLCPFallback));
6658 /* RTS frame fields... */
6659 rts = (struct ieee80211_rts *)&txh->rts_frame;
6661 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6662 rspec[0], rts_preamble_type[0],
6663 preamble_type[0], phylen, false);
6664 rts->duration = cpu_to_le16(durid);
6665 /* fallback rate version of RTS DUR field */
6666 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6667 rts_rspec[1], rspec[1],
6668 rts_preamble_type[1],
6669 preamble_type[1], phylen, false);
6670 txh->RTSDurFallback = cpu_to_le16(durid);
6673 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6674 IEEE80211_STYPE_CTS);
6676 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6678 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6679 IEEE80211_STYPE_RTS);
6681 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
6685 * low 8 bits: main frag rate/mcs,
6686 * high 8 bits: rts/cts rate/mcs
6688 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6690 (struct ofdm_phy_hdr *) rts_plcp) :
6693 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6694 memset((char *)&txh->rts_frame, 0,
6695 sizeof(struct ieee80211_rts));
6696 memset((char *)txh->RTSPLCPFallback, 0,
6697 sizeof(txh->RTSPLCPFallback));
6698 txh->RTSDurFallback = 0;
6701 #ifdef SUPPORT_40MHZ
6702 /* add null delimiter count */
6703 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6704 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6705 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6710 * Now that RTS/RTS FB preamble types are updated, write
6713 txh->MacTxControlHigh = cpu_to_le16(mch);
6716 * MainRates (both the rts and frag plcp rates have
6717 * been calculated now)
6719 txh->MainRates = cpu_to_le16(mainrates);
6721 /* XtraFrameTypes */
6722 xfts = frametype(rspec[1], wlc->mimoft);
6723 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6724 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6725 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6727 txh->XtraFrameTypes = cpu_to_le16(xfts);
6729 /* PhyTxControlWord */
6730 phyctl = frametype(rspec[0], wlc->mimoft);
6731 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6732 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6733 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6734 phyctl |= PHY_TXC_SHORT_HDR;
6737 /* phytxant is properly bit shifted */
6738 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6739 txh->PhyTxControlWord = cpu_to_le16(phyctl);
6741 /* PhyTxControlWord_1 */
6742 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6745 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
6746 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
6747 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
6748 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
6750 if (use_rts || use_cts) {
6751 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
6752 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
6753 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
6754 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
6758 * For mcs frames, if mixedmode(overloaded with long preamble)
6759 * is going to be set, fill in non-zero MModeLen and/or
6760 * MModeFbrLen it will be unnecessary if they are separated
6762 if (is_mcs_rate(rspec[0]) &&
6763 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
6765 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
6766 txh->MModeLen = cpu_to_le16(mmodelen);
6769 if (is_mcs_rate(rspec[1]) &&
6770 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
6772 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
6773 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
6777 ac = skb_get_queue_mapping(p);
6778 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
6779 uint frag_dur, dur, dur_fallback;
6781 /* WME: Update TXOP threshold */
6782 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
6784 brcms_c_calc_frame_time(wlc, rspec[0],
6785 preamble_type[0], phylen);
6788 /* 1 RTS or CTS-to-self frame */
6790 brcms_c_calc_cts_time(wlc, rts_rspec[0],
6791 rts_preamble_type[0]);
6793 brcms_c_calc_cts_time(wlc, rts_rspec[1],
6794 rts_preamble_type[1]);
6795 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
6796 dur += le16_to_cpu(rts->duration);
6798 le16_to_cpu(txh->RTSDurFallback);
6799 } else if (use_rifs) {
6803 /* frame + SIFS + ACK */
6806 brcms_c_compute_frame_dur(wlc, rspec[0],
6807 preamble_type[0], 0);
6810 brcms_c_calc_frame_time(wlc, rspec[1],
6814 brcms_c_compute_frame_dur(wlc, rspec[1],
6815 preamble_type[1], 0);
6817 /* NEED to set TxFesTimeNormal (hard) */
6818 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
6820 * NEED to set fallback rate version of
6821 * TxFesTimeNormal (hard)
6823 txh->TxFesTimeFallback =
6824 cpu_to_le16((u16) dur_fallback);
6827 * update txop byte threshold (txop minus intraframe
6830 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
6834 brcms_c_calc_frame_len(wlc,
6835 rspec[0], preamble_type[0],
6836 (wlc->edcf_txop[ac] -
6838 /* range bound the fragthreshold */
6839 if (newfragthresh < DOT11_MIN_FRAG_LEN)
6842 else if (newfragthresh >
6843 wlc->usr_fragthresh)
6845 wlc->usr_fragthresh;
6846 /* update the fragthresh and do txc update */
6847 if (wlc->fragthresh[queue] !=
6848 (u16) newfragthresh)
6849 wlc->fragthresh[queue] =
6850 (u16) newfragthresh;
6852 brcms_err(wlc->hw->d11core,
6853 "wl%d: %s txop invalid "
6855 wlc->pub->unit, fifo_names[queue],
6856 rspec2rate(rspec[0]));
6859 if (dur > wlc->edcf_txop[ac])
6860 brcms_err(wlc->hw->d11core,
6861 "wl%d: %s: %s txop "
6862 "exceeded phylen %d/%d dur %d/%d\n",
6863 wlc->pub->unit, __func__,
6865 phylen, wlc->fragthresh[queue],
6866 dur, wlc->edcf_txop[ac]);
6873 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
6875 struct dma_pub *dma;
6876 int fifo, ret = -ENOSPC;
6878 u16 frameid = INVALIDFID;
6880 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
6881 dma = wlc->hw->di[fifo];
6882 txh = (struct d11txh *)(skb->data);
6884 if (dma->txavail == 0) {
6886 * We sometimes get a frame from mac80211 after stopping
6887 * the queues. This only ever seems to be a single frame
6888 * and is seems likely to be a race. TX_HEADROOM should
6889 * ensure that we have enough space to handle these stray
6890 * packets, so warn if there isn't. If we're out of space
6891 * in the tx ring and the tx queue isn't stopped then
6892 * we've really got a bug; warn loudly if that happens.
6894 brcms_warn(wlc->hw->d11core,
6895 "Received frame for tx with no space in DMA ring\n");
6896 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
6897 skb_get_queue_mapping(skb)));
6901 /* When a BC/MC frame is being committed to the BCMC fifo
6902 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
6904 if (fifo == TX_BCMC_FIFO)
6905 frameid = le16_to_cpu(txh->TxFrameID);
6907 /* Commit BCMC sequence number in the SHM frame ID location */
6908 if (frameid != INVALIDFID) {
6910 * To inform the ucode of the last mcast frame posted
6911 * so that it can clear moredata bit
6913 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
6916 ret = brcms_c_txfifo(wlc, fifo, skb);
6918 * The only reason for brcms_c_txfifo to fail is because
6919 * there weren't any DMA descriptors, but we've already
6920 * checked for that. So if it does fail yell loudly.
6927 bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
6928 struct ieee80211_hw *hw)
6931 struct scb *scb = &wlc->pri_scb;
6933 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6934 brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0);
6935 if (!brcms_c_tx(wlc, sdu))
6938 /* packet discarded */
6939 dev_kfree_skb_any(sdu);
6944 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
6946 struct dma_pub *dma = wlc->hw->di[fifo];
6950 ret = dma_txfast(wlc, dma, p);
6952 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
6955 * Stop queue if DMA ring is full. Reserve some free descriptors,
6956 * as we sometimes receive a frame from mac80211 after the queues
6959 queue = skb_get_queue_mapping(p);
6960 if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
6961 !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
6962 ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
6968 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
6969 bool use_rspec, u16 mimo_ctlchbw)
6974 /* use frame rate as rts rate */
6976 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
6977 /* Use 11Mbps as the g protection RTS target rate and fallback.
6978 * Use the brcms_basic_rate() lookup to find the best basic rate
6979 * under the target in case 11 Mbps is not Basic.
6980 * 6 and 9 Mbps are not usually selected by rate selection, but
6981 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
6984 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
6986 /* calculate RTS rate and fallback rate based on the frame rate
6987 * RTS must be sent at a basic rate since it is a
6988 * control frame, sec 9.6 of 802.11 spec
6990 rts_rspec = brcms_basic_rate(wlc, rspec);
6992 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6993 /* set rts txbw to correct side band */
6994 rts_rspec &= ~RSPEC_BW_MASK;
6997 * if rspec/rspec_fallback is 40MHz, then send RTS on both
6998 * 20MHz channel (DUP), otherwise send RTS on control channel
7000 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
7001 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7003 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7005 /* pick siso/cdd as default for ofdm */
7006 if (is_ofdm_rate(rts_rspec)) {
7007 rts_rspec &= ~RSPEC_STF_MASK;
7008 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7014 /* Update beacon listen interval in shared memory */
7015 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7017 /* wake up every DTIM is the default */
7018 if (wlc->bcn_li_dtim == 1)
7019 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7021 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7022 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7026 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7029 struct bcma_device *core = wlc_hw->d11core;
7031 /* read the tsf timer low, then high to get an atomic read */
7032 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7033 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7037 * recover 64bit TSF value from the 16bit TSF value in the rx header
7038 * given the assumption that the TSF passed in header is within 65ms
7039 * of the current tsf.
7042 * 3.......6.......8.......0.......2.......4.......6.......8......0
7043 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7045 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7046 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7047 * receive call sequence after rx interrupt. Only the higher 16 bits
7048 * are used. Finally, the tsf_h is read from the tsf register.
7050 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7051 struct d11rxhdr *rxh)
7054 u16 rx_tsf_0_15, rx_tsf_16_31;
7056 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7058 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7059 rx_tsf_0_15 = rxh->RxTSFTime;
7062 * a greater tsf time indicates the low 16 bits of
7063 * tsf_l wrapped, so decrement the high 16 bits.
7065 if ((u16)tsf_l < rx_tsf_0_15) {
7067 if (rx_tsf_16_31 == 0xffff)
7071 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7075 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7077 struct ieee80211_rx_status *rx_status)
7082 unsigned char *plcp;
7084 /* fill in TSF and flag its presence */
7085 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7086 rx_status->flag |= RX_FLAG_MACTIME_START;
7088 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7091 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
7093 ieee80211_channel_to_frequency(channel, rx_status->band);
7095 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7099 rx_status->antenna =
7100 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7104 rspec = brcms_c_compute_rspec(rxh, plcp);
7105 if (is_mcs_rate(rspec)) {
7106 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7107 rx_status->flag |= RX_FLAG_HT;
7108 if (rspec_is40mhz(rspec))
7109 rx_status->flag |= RX_FLAG_40MHZ;
7111 switch (rspec2rate(rspec)) {
7113 rx_status->rate_idx = 0;
7116 rx_status->rate_idx = 1;
7119 rx_status->rate_idx = 2;
7122 rx_status->rate_idx = 3;
7125 rx_status->rate_idx = 4;
7128 rx_status->rate_idx = 5;
7131 rx_status->rate_idx = 6;
7134 rx_status->rate_idx = 7;
7137 rx_status->rate_idx = 8;
7140 rx_status->rate_idx = 9;
7143 rx_status->rate_idx = 10;
7146 rx_status->rate_idx = 11;
7149 brcms_err(wlc->hw->d11core,
7150 "%s: Unknown rate\n", __func__);
7154 * For 5GHz, we should decrease the index as it is
7155 * a subset of the 2.4G rates. See bitrates field
7156 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7158 if (rx_status->band == IEEE80211_BAND_5GHZ)
7159 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7161 /* Determine short preamble and rate_idx */
7163 if (is_cck_rate(rspec)) {
7164 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7165 rx_status->flag |= RX_FLAG_SHORTPRE;
7166 } else if (is_ofdm_rate(rspec)) {
7167 rx_status->flag |= RX_FLAG_SHORTPRE;
7169 brcms_err(wlc->hw->d11core, "%s: Unknown modulation\n",
7174 if (plcp3_issgi(plcp[3]))
7175 rx_status->flag |= RX_FLAG_SHORT_GI;
7177 if (rxh->RxStatus1 & RXS_DECERR) {
7178 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7179 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7182 if (rxh->RxStatus1 & RXS_FCSERR) {
7183 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7184 brcms_err(wlc->hw->d11core, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7190 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7194 struct ieee80211_rx_status rx_status;
7195 struct ieee80211_hdr *hdr;
7197 memset(&rx_status, 0, sizeof(rx_status));
7198 prep_mac80211_status(wlc, rxh, p, &rx_status);
7200 /* mac header+body length, exclude CRC and plcp header */
7201 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7202 skb_pull(p, D11_PHY_HDR_LEN);
7203 __skb_trim(p, len_mpdu);
7205 /* unmute transmit */
7206 if (wlc->hw->suspended_fifos) {
7207 hdr = (struct ieee80211_hdr *)p->data;
7208 if (ieee80211_is_beacon(hdr->frame_control))
7209 brcms_b_mute(wlc->hw, false);
7212 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7213 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7216 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7217 * number of bytes goes in the length field
7219 * Formula given by HT PHY Spec v 1.13
7220 * len = 3(nsyms + nstream + 3) - 3
7223 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7226 uint nsyms, len = 0, kNdps;
7228 if (is_mcs_rate(ratespec)) {
7229 uint mcs = ratespec & RSPEC_RATE_MASK;
7230 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7231 rspec_stc(ratespec);
7234 * the payload duration calculation matches that
7237 /* 1000Ndbps = kbps * 4 */
7238 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7239 rspec_issgi(ratespec)) * 4;
7241 if (rspec_stc(ratespec) == 0)
7243 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7244 APHY_TAIL_NBITS) * 1000, kNdps);
7246 /* STBC needs to have even number of symbols */
7249 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7250 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7252 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7253 nsyms += (tot_streams + 3);
7255 * 3 bytes/symbol @ legacy 6Mbps rate
7256 * (-3) excluding service bits and tail bits
7258 len = (3 * nsyms) - 3;
7265 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7267 const struct brcms_c_rateset *rs_dflt;
7268 struct brcms_c_rateset rs;
7271 u8 plcp[D11_PHY_HDR_LEN];
7275 sifs = get_sifs(wlc->band);
7277 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7279 brcms_c_rateset_copy(rs_dflt, &rs);
7280 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7283 * walk the phy rate table and update MAC core SHM
7284 * basic rate table entries
7286 for (i = 0; i < rs.count; i++) {
7287 rate = rs.rates[i] & BRCMS_RATE_MASK;
7289 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7291 /* Calculate the Probe Response PLCP for the given rate */
7292 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7295 * Calculate the duration of the Probe Response
7296 * frame plus SIFS for the MAC
7298 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7299 BRCMS_LONG_PREAMBLE, frame_len);
7302 /* Update the SHM Rate Table entry Probe Response values */
7303 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7304 (u16) (plcp[0] + (plcp[1] << 8)));
7305 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7306 (u16) (plcp[2] + (plcp[3] << 8)));
7307 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7311 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7313 * PLCP header is 6 bytes.
7314 * 802.11 A3 header is 24 bytes.
7315 * Max beacon frame body template length is 112 bytes.
7316 * Max probe resp frame body template length is 110 bytes.
7318 * *len on input contains the max length of the packet available.
7320 * The *len value is set to the number of bytes in buf used, and starts
7321 * with the PLCP and included up to, but not including, the 4 byte FCS.
7324 brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7326 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7328 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7329 struct cck_phy_hdr *plcp;
7330 struct ieee80211_mgmt *h;
7331 int hdr_len, body_len;
7333 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7335 /* calc buffer size provided for frame body */
7336 body_len = *len - hdr_len;
7337 /* return actual size */
7338 *len = hdr_len + body_len;
7340 /* format PHY and MAC headers */
7341 memset((char *)buf, 0, hdr_len);
7343 plcp = (struct cck_phy_hdr *) buf;
7346 * PLCP for Probe Response frames are filled in from
7349 if (type == IEEE80211_STYPE_BEACON)
7351 brcms_c_compute_plcp(wlc, bcn_rspec,
7352 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7355 /* "Regular" and 16 MBSS but not for 4 MBSS */
7356 /* Update the phytxctl for the beacon based on the rspec */
7357 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7359 h = (struct ieee80211_mgmt *)&plcp[1];
7361 /* fill in 802.11 header */
7362 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7364 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7365 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7366 if (type == IEEE80211_STYPE_BEACON)
7367 memcpy(&h->da, ðer_bcast, ETH_ALEN);
7368 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
7369 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7371 /* SEQ filled in by MAC */
7374 int brcms_c_get_header_len(void)
7380 * Update all beacons for the system.
7382 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7384 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7386 if (bsscfg->up && !bsscfg->BSS)
7387 /* Clear the soft intmask */
7388 wlc->defmacintmask &= ~MI_BCNTPL;
7391 /* Write ssid into shared memory */
7393 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7395 u8 *ssidptr = cfg->SSID;
7397 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7399 /* padding the ssid with zero and copy it into shm */
7400 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7401 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7403 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7404 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7408 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7409 struct brcms_bss_cfg *cfg,
7412 u16 prb_resp[BCN_TMPL_LEN / 2];
7413 int len = BCN_TMPL_LEN;
7416 * write the probe response to hardware, or save in
7417 * the config structure
7420 /* create the probe response template */
7421 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7422 cfg, prb_resp, &len);
7425 brcms_c_suspend_mac_and_wait(wlc);
7427 /* write the probe response into the template region */
7428 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7429 (len + 3) & ~3, prb_resp);
7431 /* write the length of the probe response frame (+PLCP/-FCS) */
7432 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7434 /* write the SSID and SSID length */
7435 brcms_c_shm_ssid_upd(wlc, cfg);
7438 * Write PLCP headers and durations for probe response frames
7439 * at all rates. Use the actual frame length covered by the
7440 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7441 * by subtracting the PLCP len and adding the FCS.
7443 len += (-D11_PHY_HDR_LEN + FCS_LEN);
7444 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7447 brcms_c_enable_mac(wlc);
7450 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7452 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7454 /* update AP or IBSS probe responses */
7455 if (bsscfg->up && !bsscfg->BSS)
7456 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7459 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7465 *blocks = wlc_hw->xmtfifo_sz[fifo];
7471 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7474 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7475 if (match_reg_offset == RCM_BSSID_OFFSET)
7476 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7480 * Flag 'scan in progress' to withhold dynamic phy calibration
7482 void brcms_c_scan_start(struct brcms_c_info *wlc)
7484 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7487 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7489 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7492 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7494 wlc->pub->associated = state;
7495 wlc->bsscfg->associated = state;
7499 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7500 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7501 * when later on hardware releases them, they can be handled appropriately.
7503 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7504 struct ieee80211_sta *sta,
7505 void (*dma_callback_fn))
7507 struct dma_pub *dmah;
7509 for (i = 0; i < NFIFO; i++) {
7512 dma_walk_packets(dmah, dma_callback_fn, sta);
7516 int brcms_c_get_curband(struct brcms_c_info *wlc)
7518 return wlc->band->bandunit;
7521 void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
7526 /* Kick DMA to send any pending AMPDU */
7527 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7529 dma_txflush(wlc->hw->di[i]);
7531 /* wait for queue and DMA fifos to run dry */
7532 while (brcms_txpktpendtot(wlc) > 0) {
7533 brcms_msleep(wlc->wl, 1);
7539 WARN_ON_ONCE(timeout == 0);
7542 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7544 wlc->bcn_li_bcn = interval;
7546 brcms_c_bcn_li_upd(wlc);
7549 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7553 /* Remove override bit and clip to max qdbm value */
7554 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7555 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7558 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7563 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7565 /* Return qdbm units */
7566 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7569 /* Process received frames */
7571 * Return true if more frames need to be processed. false otherwise.
7572 * Param 'bound' indicates max. # frames to process before break out.
7574 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7576 struct d11rxhdr *rxh;
7577 struct ieee80211_hdr *h;
7581 /* frame starts with rxhdr */
7582 rxh = (struct d11rxhdr *) (p->data);
7584 /* strip off rxhdr */
7585 skb_pull(p, BRCMS_HWRXOFF);
7587 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7588 if (rxh->RxStatus1 & RXS_PBPRES) {
7590 brcms_err(wlc->hw->d11core,
7591 "wl%d: recv: rcvd runt of len %d\n",
7592 wlc->pub->unit, p->len);
7598 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7601 if (rxh->RxStatus1 & RXS_FCSERR) {
7602 if (!(wlc->filter_flags & FIF_FCSFAIL))
7606 /* check received pkt has at least frame control field */
7607 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7610 /* not supporting A-MSDU */
7611 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7615 brcms_c_recvctl(wlc, rxh, p);
7619 brcmu_pkt_buf_free_skb(p);
7622 /* Process received frames */
7624 * Return true if more frames need to be processed. false otherwise.
7625 * Param 'bound' indicates max. # frames to process before break out.
7628 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7631 struct sk_buff *next = NULL;
7632 struct sk_buff_head recv_frames;
7635 uint bound_limit = bound ? RXBND : -1;
7638 skb_queue_head_init(&recv_frames);
7640 /* gather received frames */
7642 /* !give others some time to run! */
7643 if (n >= bound_limit)
7646 morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
7648 } while (morepending);
7650 /* post more rbufs */
7651 dma_rxfill(wlc_hw->di[fifo]);
7653 /* process each frame */
7654 skb_queue_walk_safe(&recv_frames, p, next) {
7655 struct d11rxhdr_le *rxh_le;
7656 struct d11rxhdr *rxh;
7658 skb_unlink(p, &recv_frames);
7659 rxh_le = (struct d11rxhdr_le *)p->data;
7660 rxh = (struct d11rxhdr *)p->data;
7662 /* fixup rx header endianness */
7663 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7664 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7665 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7666 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7667 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7668 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7669 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7670 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7671 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7672 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7673 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7675 brcms_c_recv(wlc_hw->wlc, p);
7681 /* second-level interrupt processing
7682 * Return true if another dpc needs to be re-scheduled. false otherwise.
7683 * Param 'bounded' indicates if applicable loops should be bounded.
7685 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7688 struct brcms_hardware *wlc_hw = wlc->hw;
7689 struct bcma_device *core = wlc_hw->d11core;
7691 if (brcms_deviceremoved(wlc)) {
7692 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7694 brcms_down(wlc->wl);
7698 /* grab and clear the saved software intstatus bits */
7699 macintstatus = wlc->macintstatus;
7700 wlc->macintstatus = 0;
7702 brcms_dbg_int(core, "wl%d: macintstatus 0x%x\n",
7703 wlc_hw->unit, macintstatus);
7705 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7708 if (macintstatus & MI_TFS) {
7710 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7711 wlc->macintstatus |= MI_TFS;
7713 brcms_err(core, "MI_TFS: fatal\n");
7718 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7721 /* ATIM window end */
7722 if (macintstatus & MI_ATIMWINEND) {
7723 brcms_dbg_info(core, "end of ATIM window\n");
7724 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7729 * received data or control frame, MI_DMAINT is
7730 * indication of RX_FIFO interrupt
7732 if (macintstatus & MI_DMAINT)
7733 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7734 wlc->macintstatus |= MI_DMAINT;
7736 /* noise sample collected */
7737 if (macintstatus & MI_BG_NOISE)
7738 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7740 if (macintstatus & MI_GP0) {
7741 brcms_err(core, "wl%d: PSM microcode watchdog fired at %d "
7742 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7744 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7745 __func__, ai_get_chip_id(wlc_hw->sih),
7746 ai_get_chiprev(wlc_hw->sih));
7747 brcms_fatal_error(wlc_hw->wlc->wl);
7750 /* gptimer timeout */
7751 if (macintstatus & MI_TO)
7752 bcma_write32(core, D11REGOFFS(gptimer), 0);
7754 if (macintstatus & MI_RFDISABLE) {
7755 brcms_dbg_info(core, "wl%d: BMAC Detected a change on the"
7756 " RF Disable Input\n", wlc_hw->unit);
7757 brcms_rfkill_set_hw_state(wlc->wl);
7760 /* it isn't done and needs to be resched if macintstatus is non-zero */
7761 return wlc->macintstatus != 0;
7764 brcms_fatal_error(wlc_hw->wlc->wl);
7765 return wlc->macintstatus != 0;
7768 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
7770 struct bcma_device *core = wlc->hw->d11core;
7771 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
7774 brcms_dbg_info(core, "wl%d\n", wlc->pub->unit);
7776 chanspec = ch20mhz_chspec(ch->hw_value);
7778 brcms_b_init(wlc->hw, chanspec);
7780 /* update beacon listen interval */
7781 brcms_c_bcn_li_upd(wlc);
7783 /* write ethernet address to core */
7784 brcms_c_set_mac(wlc->bsscfg);
7785 brcms_c_set_bssid(wlc->bsscfg);
7787 /* Update tsf_cfprep if associated and up */
7788 if (wlc->pub->associated && wlc->bsscfg->up) {
7791 /* get beacon period and convert to uS */
7792 bi = wlc->bsscfg->current_bss->beacon_period << 10;
7794 * update since init path would reset
7797 bcma_write32(core, D11REGOFFS(tsf_cfprep),
7798 bi << CFPREP_CBI_SHIFT);
7800 /* Update maccontrol PM related bits */
7801 brcms_c_set_ps_ctrl(wlc);
7804 brcms_c_bandinit_ordered(wlc, chanspec);
7806 /* init probe response timeout */
7807 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
7809 /* init max burst txop (framebursting) */
7810 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
7812 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
7814 /* initialize maximum allowed duty cycle */
7815 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
7816 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
7819 * Update some shared memory locations related to
7820 * max AMPDU size allowed to received
7822 brcms_c_ampdu_shm_upd(wlc->ampdu);
7824 /* band-specific inits */
7825 brcms_c_bsinit(wlc);
7827 /* Enable EDCF mode (while the MAC is suspended) */
7828 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
7829 brcms_c_edcf_setparams(wlc, false);
7831 /* read the ucode version if we have not yet done so */
7832 if (wlc->ucode_rev == 0) {
7834 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
7835 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
7838 /* ..now really unleash hell (allow the MAC out of suspend) */
7839 brcms_c_enable_mac(wlc);
7841 /* suspend the tx fifos and mute the phy for preism cac time */
7843 brcms_b_mute(wlc->hw, true);
7845 /* enable the RF Disable Delay timer */
7846 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
7849 * Initialize WME parameters; if they haven't been set by some other
7850 * mechanism (IOVar, etc) then read them from the hardware.
7852 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
7853 /* Uninitialized; read from HW */
7856 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
7857 wlc->wme_retries[ac] =
7858 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
7863 * The common driver entry routine. Error codes should be unique
7865 struct brcms_c_info *
7866 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
7867 bool piomode, uint *perr)
7869 struct brcms_c_info *wlc;
7872 struct brcms_pub *pub;
7874 /* allocate struct brcms_c_info state and its substructures */
7875 wlc = brcms_c_attach_malloc(unit, &err, 0);
7878 wlc->wiphy = wl->wiphy;
7885 wlc->band = wlc->bandstate[0];
7886 wlc->core = wlc->corestate;
7889 pub->_piomode = piomode;
7890 wlc->bandinit_pending = false;
7892 /* populate struct brcms_c_info with default values */
7893 brcms_c_info_init(wlc, unit);
7895 /* update sta/ap related parameters */
7896 brcms_c_ap_upd(wlc);
7899 * low level attach steps(all hw accesses go
7900 * inside, no more in rest of the attach)
7902 err = brcms_b_attach(wlc, core, unit, piomode);
7906 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
7908 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
7910 /* disable allowed duty cycle */
7911 wlc->tx_duty_cycle_ofdm = 0;
7912 wlc->tx_duty_cycle_cck = 0;
7914 brcms_c_stf_phy_chain_calc(wlc);
7916 /* txchain 1: txant 0, txchain 2: txant 1 */
7917 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
7918 wlc->stf->txant = wlc->stf->hw_txchain - 1;
7920 /* push to BMAC driver */
7921 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
7922 wlc->stf->hw_rxchain);
7924 /* pull up some info resulting from the low attach */
7925 for (i = 0; i < NFIFO; i++)
7926 wlc->core->txavail[i] = wlc->hw->txavail[i];
7928 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7929 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
7931 for (j = 0; j < wlc->pub->_nbands; j++) {
7932 wlc->band = wlc->bandstate[j];
7934 if (!brcms_c_attach_stf_ant_init(wlc)) {
7939 /* default contention windows size limits */
7940 wlc->band->CWmin = APHY_CWMIN;
7941 wlc->band->CWmax = PHY_CWMAX;
7943 /* init gmode value */
7944 if (wlc->band->bandtype == BRCM_BAND_2G) {
7945 wlc->band->gmode = GMODE_AUTO;
7946 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
7950 /* init _n_enab supported mode */
7951 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7952 pub->_n_enab = SUPPORT_11N;
7953 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
7955 SUPPORT_11N) ? WL_11N_2x2 :
7959 /* init per-band default rateset, depend on band->gmode */
7960 brcms_default_rateset(wlc, &wlc->band->defrateset);
7962 /* fill in hw_rateset */
7963 brcms_c_rateset_filter(&wlc->band->defrateset,
7964 &wlc->band->hw_rateset, false,
7965 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
7966 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
7970 * update antenna config due to
7971 * wlc->stf->txant/txchain/ant_rx_ovr change
7973 brcms_c_stf_phy_txant_upd(wlc);
7975 /* attach each modules */
7976 err = brcms_c_attach_module(wlc);
7980 if (!brcms_c_timers_init(wlc, unit)) {
7981 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
7987 /* depend on rateset, gmode */
7988 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
7990 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
7991 "\n", unit, __func__);
7996 /* init default when all parameters are ready, i.e. ->rateset */
7997 brcms_c_bss_default_init(wlc);
8000 * Complete the wlc default state initializations..
8003 wlc->bsscfg->wlc = wlc;
8005 wlc->mimoft = FT_HT;
8006 wlc->mimo_40txbw = AUTO;
8007 wlc->ofdm_40txbw = AUTO;
8008 wlc->cck_40txbw = AUTO;
8009 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8011 /* Set default values of SGI */
8012 if (BRCMS_SGI_CAP_PHY(wlc)) {
8013 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8015 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8016 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8019 brcms_c_ht_update_sgi_rx(wlc, 0);
8022 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8030 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8031 unit, __func__, err);
8033 brcms_c_detach(wlc);