drivers/net/wireless/iwlwifi/iwl-4965.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-calib.h"
  46 #include "iwl-sta.h"
  47 #include "iwl-agn-led.h"
  48
  49 static int iwl4965_send_tx_power(struct iwl_priv *priv);
  50 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
  51
  52 /* Highest firmware API version supported */
  53 #define IWL4965_UCODE_API_MAX 2
  54
  55 /* Lowest firmware API version supported */
  56 #define IWL4965_UCODE_API_MIN 2
  57
  58 #define IWL4965_FW_PRE "iwlwifi-4965-"
  59 #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
  60 #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
  61
  62
  63 /* module parameters */
  64 static struct iwl_mod_params iwl4965_mod_params = {
  65         .amsdu_size_8K = 1,
  66         .restart_fw = 1,
  67         /* the rest are 0 by default */
  68 };
  69
  70 /* check contents of special bootstrap uCode SRAM */
  71 static int iwl4965_verify_bsm(struct iwl_priv *priv)
  72 {
  73         __le32 *image = priv->ucode_boot.v_addr;
  74         u32 len = priv->ucode_boot.len;
  75         u32 reg;
  76         u32 val;
  77
  78         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
  79
  80         /* verify BSM SRAM contents */
  81         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  82         for (reg = BSM_SRAM_LOWER_BOUND;
  83              reg < BSM_SRAM_LOWER_BOUND + len;
  84              reg += sizeof(u32), image++) {
  85                 val = iwl_read_prph(priv, reg);
  86                 if (val != le32_to_cpu(*image)) {
  87                         IWL_ERR(priv, "BSM uCode verification failed at "
  88                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  89                                   BSM_SRAM_LOWER_BOUND,
  90                                   reg - BSM_SRAM_LOWER_BOUND, len,
  91                                   val, le32_to_cpu(*image));
  92                         return -EIO;
  93                 }
  94         }
  95
  96         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
  97
  98         return 0;
  99 }
 100
 101 /**
 102  * iwl4965_load_bsm - Load bootstrap instructions
 103  *
 104  * BSM operation:
 105  *
 106  * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
 107  * in special SRAM that does not power down during RFKILL.  When powering back
 108  * up after power-saving sleeps (or during initial uCode load), the BSM loads
 109  * the bootstrap program into the on-board processor, and starts it.
 110  *
 111  * The bootstrap program loads (via DMA) instructions and data for a new
 112  * program from host DRAM locations indicated by the host driver in the
 113  * BSM_DRAM_* registers.  Once the new program is loaded, it starts
 114  * automatically.
 115  *
 116  * When initializing the NIC, the host driver points the BSM to the
 117  * "initialize" uCode image.  This uCode sets up some internal data, then
 118  * notifies host via "initialize alive" that it is complete.
 119  *
 120  * The host then replaces the BSM_DRAM_* pointer values to point to the
 121  * normal runtime uCode instructions and a backup uCode data cache buffer
 122  * (filled initially with starting data values for the on-board processor),
 123  * then triggers the "initialize" uCode to load and launch the runtime uCode,
 124  * which begins normal operation.
 125  *
 126  * When doing a power-save shutdown, runtime uCode saves data SRAM into
 127  * the backup data cache in DRAM before SRAM is powered down.
 128  *
 129  * When powering back up, the BSM loads the bootstrap program.  This reloads
 130  * the runtime uCode instructions and the backup data cache into SRAM,
 131  * and re-launches the runtime uCode from where it left off.
 132  */
 133 static int iwl4965_load_bsm(struct iwl_priv *priv)
 134 {
 135         __le32 *image = priv->ucode_boot.v_addr;
 136         u32 len = priv->ucode_boot.len;
 137         dma_addr_t pinst;
 138         dma_addr_t pdata;
 139         u32 inst_len;
 140         u32 data_len;
 141         int i;
 142         u32 done;
 143         u32 reg_offset;
 144         int ret;
 145
 146         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
 147
 148         priv->ucode_type = UCODE_RT;
 149
 150         /* make sure bootstrap program is no larger than BSM's SRAM size */
 151         if (len > IWL49_MAX_BSM_SIZE)
 152                 return -EINVAL;
 153
 154         /* Tell bootstrap uCode where to find the "Initialize" uCode
 155          *   in host DRAM ... host DRAM physical address bits 35:4 for 4965.
 156          * NOTE:  iwl_init_alive_start() will replace these values,
 157          *        after the "initialize" uCode has run, to point to
 158          *        runtime/protocol instructions and backup data cache.
 159          */
 160         pinst = priv->ucode_init.p_addr >> 4;
 161         pdata = priv->ucode_init_data.p_addr >> 4;
 162         inst_len = priv->ucode_init.len;
 163         data_len = priv->ucode_init_data.len;
 164
 165         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
 166         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
 167         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
 168         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
 169
 170         /* Fill BSM memory with bootstrap instructions */
 171         for (reg_offset = BSM_SRAM_LOWER_BOUND;
 172              reg_offset < BSM_SRAM_LOWER_BOUND + len;
 173              reg_offset += sizeof(u32), image++)
 174                 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
 175
 176         ret = iwl4965_verify_bsm(priv);
 177         if (ret)
 178                 return ret;
 179
 180         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
 181         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
 182         iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
 183         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
 184
 185         /* Load bootstrap code into instruction SRAM now,
 186          *   to prepare to load "initialize" uCode */
 187         iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
 188
 189         /* Wait for load of bootstrap uCode to finish */
 190         for (i = 0; i < 100; i++) {
 191                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
 192                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
 193                         break;
 194                 udelay(10);
 195         }
 196         if (i < 100)
 197                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
 198         else {
 199                 IWL_ERR(priv, "BSM write did not complete!\n");
 200                 return -EIO;
 201         }
 202
 203         /* Enable future boot loads whenever power management unit triggers it
 204          *   (e.g. when powering back up after power-save shutdown) */
 205         iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
 206
 207
 208         return 0;
 209 }
 210
 211 /**
 212  * iwl4965_set_ucode_ptrs - Set uCode address location
 213  *
 214  * Tell initialization uCode where to find runtime uCode.
 215  *
 216  * BSM registers initially contain pointers to initialization uCode.
 217  * We need to replace them to load runtime uCode inst and data,
 218  * and to save runtime data when powering down.
 219  */
 220 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
 221 {
 222         dma_addr_t pinst;
 223         dma_addr_t pdata;
 224         int ret = 0;
 225
 226         /* bits 35:4 for 4965 */
 227         pinst = priv->ucode_code.p_addr >> 4;
 228         pdata = priv->ucode_data_backup.p_addr >> 4;
 229
 230         /* Tell bootstrap uCode where to find image to load */
 231         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
 232         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
 233         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
 234                                  priv->ucode_data.len);
 235
 236         /* Inst byte count must be last to set up, bit 31 signals uCode
 237          *   that all new ptr/size info is in place */
 238         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
 239                                  priv->ucode_code.len | BSM_DRAM_INST_LOAD);
 240         IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
 241
 242         return ret;
 243 }
 244
 245 /**
 246  * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
 247  *
 248  * Called after REPLY_ALIVE notification received from "initialize" uCode.
 249  *
 250  * The 4965 "initialize" ALIVE reply contains calibration data for:
 251  *   Voltage, temperature, and MIMO tx gain correction, now stored in priv
 252  *   (3945 does not contain this data).
 253  *
 254  * Tell "initialize" uCode to go ahead and load the runtime uCode.
 255 */
 256 static void iwl4965_init_alive_start(struct iwl_priv *priv)
 257 {
 258         /* Check alive response for "valid" sign from uCode */
 259         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 260                 /* We had an error bringing up the hardware, so take it
 261                  * all the way back down so we can try again */
 262                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 263                 goto restart;
 264         }
 265
 266         /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
 267          * This is a paranoid check, because we would not have gotten the
 268          * "initialize" alive if code weren't properly loaded.  */
 269         if (iwl_verify_ucode(priv)) {
 270                 /* Runtime instruction load was bad;
 271                  * take it all the way back down so we can try again */
 272                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 273                 goto restart;
 274         }
 275
 276         /* Calculate temperature */
 277         priv->temperature = iwl4965_hw_get_temperature(priv);
 278
 279         /* Send pointers to protocol/runtime uCode image ... init code will
 280          * load and launch runtime uCode, which will send us another "Alive"
 281          * notification. */
 282         IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 283         if (iwl4965_set_ucode_ptrs(priv)) {
 284                 /* Runtime instruction load won't happen;
 285                  * take it all the way back down so we can try again */
 286                 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
 287                 goto restart;
 288         }
 289         return;
 290
 291 restart:
 292         queue_work(priv->workqueue, &priv->restart);
 293 }
 294
 295 static bool is_ht40_channel(__le32 rxon_flags)
 296 {
 297         int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK)
 298                                     >> RXON_FLG_CHANNEL_MODE_POS;
 299         return ((chan_mod == CHANNEL_MODE_PURE_40) ||
 300                   (chan_mod == CHANNEL_MODE_MIXED));
 301 }
 302
 303 /*
 304  * EEPROM handlers
 305  */
 306 static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
 307 {
 308         return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
 309 }
 310
 311 /*
 312  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 313  * must be called under priv->lock and mac access
 314  */
 315 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
 316 {
 317         iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
 318 }
 319
 320 static int iwl4965_apm_init(struct iwl_priv *priv)
 321 {
 322         int ret = 0;
 323
 324         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 325                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 326
 327         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 328         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 329                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 330
 331         /* set "initialization complete" bit to move adapter
 332          * D0U* --> D0A* state */
 333         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 334
 335         /* wait for clock stabilization */
 336         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 337                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 338                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 339         if (ret < 0) {
 340                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
 341                 goto out;
 342         }
 343
 344         /* enable DMA */
 345         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
 346                                                 APMG_CLK_VAL_BSM_CLK_RQT);
 347
 348         udelay(20);
 349
 350         /* disable L1-Active */
 351         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 352                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 353
 354 out:
 355         return ret;
 356 }
 357
 358
 359 static void iwl4965_nic_config(struct iwl_priv *priv)
 360 {
 361         unsigned long flags;
 362         u16 radio_cfg;
 363         u16 lctl;
 364
 365         spin_lock_irqsave(&priv->lock, flags);
 366
 367         lctl = iwl_pcie_link_ctl(priv);
 368
 369         /* HW bug W/A - negligible power consumption */
 370         /* L1-ASPM is enabled by BIOS */
 371         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 372                 /* L1-ASPM enabled: disable L0S  */
 373                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 374         else
 375                 /* L1-ASPM disabled: enable L0S */
 376                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 377
 378         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 379
 380         /* write radio config values to register */
 381         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
 382                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 383                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 384                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 385                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 386
 387         /* set CSR_HW_CONFIG_REG for uCode use */
 388         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 389                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 390                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 391
 392         priv->calib_info = (struct iwl_eeprom_calib_info *)
 393                 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
 394
 395         spin_unlock_irqrestore(&priv->lock, flags);
 396 }
 397
 398 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
 399  * Called after every association, but this runs only once!
 400  *  ... once chain noise is calibrated the first time, it's good forever.  */
 401 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
 402 {
 403         struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
 404
 405         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 406                 struct iwl_calib_diff_gain_cmd cmd;
 407
 408                 memset(&cmd, 0, sizeof(cmd));
 409                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
 410                 cmd.diff_gain_a = 0;
 411                 cmd.diff_gain_b = 0;
 412                 cmd.diff_gain_c = 0;
 413                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 414                                  sizeof(cmd), &cmd))
 415                         IWL_ERR(priv,
 416                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 417                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 418                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
 419         }
 420 }
 421
 422 static void iwl4965_gain_computation(struct iwl_priv *priv,
 423                 u32 *average_noise,
 424                 u16 min_average_noise_antenna_i,
 425                 u32 min_average_noise,
 426                 u8 default_chain)
 427 {
 428         int i, ret;
 429         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 430
 431         data->delta_gain_code[min_average_noise_antenna_i] = 0;
 432
 433         for (i = default_chain; i < NUM_RX_CHAINS; i++) {
 434                 s32 delta_g = 0;
 435
 436                 if (!(data->disconn_array[i]) &&
 437                     (data->delta_gain_code[i] ==
 438                              CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
 439                         delta_g = average_noise[i] - min_average_noise;
 440                         data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
 441                         data->delta_gain_code[i] =
 442                                 min(data->delta_gain_code[i],
 443                                 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 444
 445                         data->delta_gain_code[i] =
 446                                 (data->delta_gain_code[i] | (1 << 2));
 447                 } else {
 448                         data->delta_gain_code[i] = 0;
 449                 }
 450         }
 451         IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
 452                      data->delta_gain_code[0],
 453                      data->delta_gain_code[1],
 454                      data->delta_gain_code[2]);
 455
 456         /* Differential gain gets sent to uCode only once */
 457         if (!data->radio_write) {
 458                 struct iwl_calib_diff_gain_cmd cmd;
 459                 data->radio_write = 1;
 460
 461                 memset(&cmd, 0, sizeof(cmd));
 462                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
 463                 cmd.diff_gain_a = data->delta_gain_code[0];
 464                 cmd.diff_gain_b = data->delta_gain_code[1];
 465                 cmd.diff_gain_c = data->delta_gain_code[2];
 466                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 467                                       sizeof(cmd), &cmd);
 468                 if (ret)
 469                         IWL_DEBUG_CALIB(priv, "fail sending cmd "
 470                                      "REPLY_PHY_CALIBRATION_CMD \n");
 471
 472                 /* TODO we might want recalculate
 473                  * rx_chain in rxon cmd */
 474
 475                 /* Mark so we run this algo only once! */
 476                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 477         }
 478         data->chain_noise_a = 0;
 479         data->chain_noise_b = 0;
 480         data->chain_noise_c = 0;
 481         data->chain_signal_a = 0;
 482         data->chain_signal_b = 0;
 483         data->chain_signal_c = 0;
 484         data->beacon_count = 0;
 485 }
 486
 487 static void iwl4965_bg_txpower_work(struct work_struct *work)
 488 {
 489         struct iwl_priv *priv = container_of(work, struct iwl_priv,
 490                         txpower_work);
 491
 492         /* If a scan happened to start before we got here
 493          * then just return; the statistics notification will
 494          * kick off another scheduled work to compensate for
 495          * any temperature delta we missed here. */
 496         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
 497             test_bit(STATUS_SCANNING, &priv->status))
 498                 return;
 499
 500         mutex_lock(&priv->mutex);
 501
 502         /* Regardless of if we are associated, we must reconfigure the
 503          * TX power since frames can be sent on non-radar channels while
 504          * not associated */
 505         iwl4965_send_tx_power(priv);
 506
 507         /* Update last_temperature to keep is_calib_needed from running
 508          * when it isn't needed... */
 509         priv->last_temperature = priv->temperature;
 510
 511         mutex_unlock(&priv->mutex);
 512 }
 513
 514 /*
 515  * Acquire priv->lock before calling this function !
 516  */
 517 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
 518 {
 519         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 520                              (index & 0xff) | (txq_id << 8));
 521         iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
 522 }
 523
 524 /**
 525  * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
 526  * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
 527  * @scd_retry: (1) Indicates queue will be used in aggregation mode
 528  *
 529  * NOTE:  Acquire priv->lock before calling this function !
 530  */
 531 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
 532                                         struct iwl_tx_queue *txq,
 533                                         int tx_fifo_id, int scd_retry)
 534 {
 535         int txq_id = txq->q.id;
 536
 537         /* Find out whether to activate Tx queue */
 538         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 539
 540         /* Set up and activate */
 541         iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
 542                          (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 543                          (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
 544                          (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
 545                          (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
 546                          IWL49_SCD_QUEUE_STTS_REG_MSK);
 547
 548         txq->sched_retry = scd_retry;
 549
 550         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
 551                        active ? "Activate" : "Deactivate",
 552                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 553 }
 554
 555 static const u16 default_queue_to_tx_fifo[] = {
 556         IWL_TX_FIFO_AC3,
 557         IWL_TX_FIFO_AC2,
 558         IWL_TX_FIFO_AC1,
 559         IWL_TX_FIFO_AC0,
 560         IWL49_CMD_FIFO_NUM,
 561         IWL_TX_FIFO_HCCA_1,
 562         IWL_TX_FIFO_HCCA_2
 563 };
 564
 565 static int iwl4965_alive_notify(struct iwl_priv *priv)
 566 {
 567         u32 a;
 568         unsigned long flags;
 569         int i, chan;
 570         u32 reg_val;
 571
 572         spin_lock_irqsave(&priv->lock, flags);
 573
 574         /* Clear 4965's internal Tx Scheduler data base */
 575         priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
 576         a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
 577         for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
 578                 iwl_write_targ_mem(priv, a, 0);
 579         for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
 580                 iwl_write_targ_mem(priv, a, 0);
 581         for (; a < priv->scd_base_addr +
 582                IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
 583                 iwl_write_targ_mem(priv, a, 0);
 584
 585         /* Tel 4965 where to find Tx byte count tables */
 586         iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
 587                         priv->scd_bc_tbls.dma >> 10);
 588
 589         /* Enable DMA channel */
 590         for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
 591                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 592                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 593                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 594
 595         /* Update FH chicken bits */
 596         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 597         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 598                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 599
 600         /* Disable chain mode for all queues */
 601         iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
 602
 603         /* Initialize each Tx queue (including the command queue) */
 604         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 605
 606                 /* TFD circular buffer read/write indexes */
 607                 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
 608                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 609
 610                 /* Max Tx Window size for Scheduler-ACK mode */
 611                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 612                                 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
 613                                 (SCD_WIN_SIZE <<
 614                                 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
 615                                 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
 616
 617                 /* Frame limit */
 618                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 619                                 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
 620                                 sizeof(u32),
 621                                 (SCD_FRAME_LIMIT <<
 622                                 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 623                                 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
 624
 625         }
 626         iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
 627                                  (1 << priv->hw_params.max_txq_num) - 1);
 628
 629         /* Activate all Tx DMA/FIFO channels */
 630         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
 631
 632         iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 633
 634         /* Map each Tx/cmd queue to its corresponding fifo */
 635         for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
 636                 int ac = default_queue_to_tx_fifo[i];
 637                 iwl_txq_ctx_activate(priv, i);
 638                 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 639         }
 640
 641         spin_unlock_irqrestore(&priv->lock, flags);
 642
 643         return 0;
 644 }
 645
 646 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
 647         .min_nrg_cck = 97,
 648         .max_nrg_cck = 0, /* not used, set to 0 */
 649
 650         .auto_corr_min_ofdm = 85,
 651         .auto_corr_min_ofdm_mrc = 170,
 652         .auto_corr_min_ofdm_x1 = 105,
 653         .auto_corr_min_ofdm_mrc_x1 = 220,
 654
 655         .auto_corr_max_ofdm = 120,
 656         .auto_corr_max_ofdm_mrc = 210,
 657         .auto_corr_max_ofdm_x1 = 140,
 658         .auto_corr_max_ofdm_mrc_x1 = 270,
 659
 660         .auto_corr_min_cck = 125,
 661         .auto_corr_max_cck = 200,
 662         .auto_corr_min_cck_mrc = 200,
 663         .auto_corr_max_cck_mrc = 400,
 664
 665         .nrg_th_cck = 100,
 666         .nrg_th_ofdm = 100,
 667
 668         .barker_corr_th_min = 190,
 669         .barker_corr_th_min_mrc = 390,
 670         .nrg_th_cca = 62,
 671 };
 672
 673 static void iwl4965_set_ct_threshold(struct iwl_priv *priv)
 674 {
 675         /* want Kelvin */
 676         priv->hw_params.ct_kill_threshold =
 677                 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
 678 }
 679
 680 /**
 681  * iwl4965_hw_set_hw_params
 682  *
 683  * Called when initializing driver
 684  */
 685 static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
 686 {
 687         if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
 688             priv->cfg->mod_params->num_of_queues <= IWL49_NUM_QUEUES)
 689                 priv->cfg->num_of_queues =
 690                         priv->cfg->mod_params->num_of_queues;
 691
 692         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
 693         priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
 694         priv->hw_params.scd_bc_tbls_size =
 695                         priv->cfg->num_of_queues *
 696                         sizeof(struct iwl4965_scd_bc_tbl);
 697         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 698         priv->hw_params.max_stations = IWL4965_STATION_COUNT;
 699         priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
 700         priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
 701         priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
 702         priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
 703         priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
 704
 705         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 706
 707         priv->hw_params.tx_chains_num = 2;
 708         priv->hw_params.rx_chains_num = 2;
 709         priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
 710         priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
 711         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
 712                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
 713
 714         priv->hw_params.sens = &iwl4965_sensitivity;
 715
 716         return 0;
 717 }
 718
 719 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
 720 {
 721         s32 sign = 1;
 722
 723         if (num < 0) {
 724                 sign = -sign;
 725                 num = -num;
 726         }
 727         if (denom < 0) {
 728                 sign = -sign;
 729                 denom = -denom;
 730         }
 731         *res = 1;
 732         *res = ((num * 2 + denom) / (denom * 2)) * sign;
 733
 734         return 1;
 735 }
 736
 737 /**
 738  * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
 739  *
 740  * Determines power supply voltage compensation for txpower calculations.
 741  * Returns number of 1/2-dB steps to subtract from gain table index,
 742  * to compensate for difference between power supply voltage during
 743  * factory measurements, vs. current power supply voltage.
 744  *
 745  * Voltage indication is higher for lower voltage.
 746  * Lower voltage requires more gain (lower gain table index).
 747  */
 748 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
 749                                             s32 current_voltage)
 750 {
 751         s32 comp = 0;
 752
 753         if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
 754             (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
 755                 return 0;
 756
 757         iwl4965_math_div_round(current_voltage - eeprom_voltage,
 758                                TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
 759
 760         if (current_voltage > eeprom_voltage)
 761                 comp *= 2;
 762         if ((comp < -2) || (comp > 2))
 763                 comp = 0;
 764
 765         return comp;
 766 }
 767
 768 static s32 iwl4965_get_tx_atten_grp(u16 channel)
 769 {
 770         if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
 771             channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
 772                 return CALIB_CH_GROUP_5;
 773
 774         if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
 775             channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
 776                 return CALIB_CH_GROUP_1;
 777
 778         if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
 779             channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
 780                 return CALIB_CH_GROUP_2;
 781
 782         if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
 783             channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
 784                 return CALIB_CH_GROUP_3;
 785
 786         if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
 787             channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
 788                 return CALIB_CH_GROUP_4;
 789
 790         return -1;
 791 }
 792
 793 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
 794 {
 795         s32 b = -1;
 796
 797         for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
 798                 if (priv->calib_info->band_info[b].ch_from == 0)
 799                         continue;
 800
 801                 if ((channel >= priv->calib_info->band_info[b].ch_from)
 802                     && (channel <= priv->calib_info->band_info[b].ch_to))
 803                         break;
 804         }
 805
 806         return b;
 807 }
 808
 809 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
 810 {
 811         s32 val;
 812
 813         if (x2 == x1)
 814                 return y1;
 815         else {
 816                 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
 817                 return val + y2;
 818         }
 819 }
 820
 821 /**
 822  * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
 823  *
 824  * Interpolates factory measurements from the two sample channels within a
 825  * sub-band, to apply to channel of interest.  Interpolation is proportional to
 826  * differences in channel frequencies, which is proportional to differences
 827  * in channel number.
 828  */
 829 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
 830                                     struct iwl_eeprom_calib_ch_info *chan_info)
 831 {
 832         s32 s = -1;
 833         u32 c;
 834         u32 m;
 835         const struct iwl_eeprom_calib_measure *m1;
 836         const struct iwl_eeprom_calib_measure *m2;
 837         struct iwl_eeprom_calib_measure *omeas;
 838         u32 ch_i1;
 839         u32 ch_i2;
 840
 841         s = iwl4965_get_sub_band(priv, channel);
 842         if (s >= EEPROM_TX_POWER_BANDS) {
 843                 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
 844                 return -1;
 845         }
 846
 847         ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
 848         ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
 849         chan_info->ch_num = (u8) channel;
 850
 851         IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
 852                           channel, s, ch_i1, ch_i2);
 853
 854         for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
 855                 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
 856                         m1 = &(priv->calib_info->band_info[s].ch1.
 857                                measurements[c][m]);
 858                         m2 = &(priv->calib_info->band_info[s].ch2.
 859                                measurements[c][m]);
 860                         omeas = &(chan_info->measurements[c][m]);
 861
 862                         omeas->actual_pow =
 863                             (u8) iwl4965_interpolate_value(channel, ch_i1,
 864                                                            m1->actual_pow,
 865                                                            ch_i2,
 866                                                            m2->actual_pow);
 867                         omeas->gain_idx =
 868                             (u8) iwl4965_interpolate_value(channel, ch_i1,
 869                                                            m1->gain_idx, ch_i2,
 870                                                            m2->gain_idx);
 871                         omeas->temperature =
 872                             (u8) iwl4965_interpolate_value(channel, ch_i1,
 873                                                            m1->temperature,
 874                                                            ch_i2,
 875                                                            m2->temperature);
 876                         omeas->pa_det =
 877                             (s8) iwl4965_interpolate_value(channel, ch_i1,
 878                                                            m1->pa_det, ch_i2,
 879                                                            m2->pa_det);
 880
 881                         IWL_DEBUG_TXPOWER(priv,
 882                                 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
 883                                 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
 884                         IWL_DEBUG_TXPOWER(priv,
 885                                 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
 886                                 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
 887                         IWL_DEBUG_TXPOWER(priv,
 888                                 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
 889                                 m1->pa_det, m2->pa_det, omeas->pa_det);
 890                         IWL_DEBUG_TXPOWER(priv,
 891                                 "chain %d meas %d  T1=%d  T2=%d  T=%d\n", c, m,
 892                                 m1->temperature, m2->temperature,
 893                                 omeas->temperature);
 894                 }
 895         }
 896
 897         return 0;
 898 }
 899
 900 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
 901  * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
 902 static s32 back_off_table[] = {
 903         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
 904         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
 905         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
 906         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
 907         10                      /* CCK */
 908 };
 909
 910 /* Thermal compensation values for txpower for various frequency ranges ...
 911  *   ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
 912 static struct iwl4965_txpower_comp_entry {
 913         s32 degrees_per_05db_a;
 914         s32 degrees_per_05db_a_denom;
 915 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
 916         {9, 2},                 /* group 0 5.2, ch  34-43 */
 917         {4, 1},                 /* group 1 5.2, ch  44-70 */
 918         {4, 1},                 /* group 2 5.2, ch  71-124 */
 919         {4, 1},                 /* group 3 5.2, ch 125-200 */
 920         {3, 1}                  /* group 4 2.4, ch   all */
 921 };
 922
 923 static s32 get_min_power_index(s32 rate_power_index, u32 band)
 924 {
 925         if (!band) {
 926                 if ((rate_power_index & 7) <= 4)
 927                         return MIN_TX_GAIN_INDEX_52GHZ_EXT;
 928         }
 929         return MIN_TX_GAIN_INDEX;
 930 }
 931
 932 struct gain_entry {
 933         u8 dsp;
 934         u8 radio;
 935 };
 936
 937 static const struct gain_entry gain_table[2][108] = {
 938         /* 5.2GHz power gain index table */
 939         {
 940          {123, 0x3F},           /* highest txpower */
 941          {117, 0x3F},
 942          {110, 0x3F},
 943          {104, 0x3F},
 944          {98, 0x3F},
 945          {110, 0x3E},
 946          {104, 0x3E},
 947          {98, 0x3E},
 948          {110, 0x3D},
 949          {104, 0x3D},
 950          {98, 0x3D},
 951          {110, 0x3C},
 952          {104, 0x3C},
 953          {98, 0x3C},
 954          {110, 0x3B},
 955          {104, 0x3B},
 956          {98, 0x3B},
 957          {110, 0x3A},
 958          {104, 0x3A},
 959          {98, 0x3A},
 960          {110, 0x39},
 961          {104, 0x39},
 962          {98, 0x39},
 963          {110, 0x38},
 964          {104, 0x38},
 965          {98, 0x38},
 966          {110, 0x37},
 967          {104, 0x37},
 968          {98, 0x37},
 969          {110, 0x36},
 970          {104, 0x36},
 971          {98, 0x36},
 972          {110, 0x35},
 973          {104, 0x35},
 974          {98, 0x35},
 975          {110, 0x34},
 976          {104, 0x34},
 977          {98, 0x34},
 978          {110, 0x33},
 979          {104, 0x33},
 980          {98, 0x33},
 981          {110, 0x32},
 982          {104, 0x32},
 983          {98, 0x32},
 984          {110, 0x31},
 985          {104, 0x31},
 986          {98, 0x31},
 987          {110, 0x30},
 988          {104, 0x30},
 989          {98, 0x30},
 990          {110, 0x25},
 991          {104, 0x25},
 992          {98, 0x25},
 993          {110, 0x24},
 994          {104, 0x24},
 995          {98, 0x24},
 996          {110, 0x23},
 997          {104, 0x23},
 998          {98, 0x23},
 999          {110, 0x22},
1000          {104, 0x18},
1001          {98, 0x18},
1002          {110, 0x17},
1003          {104, 0x17},
1004          {98, 0x17},
1005          {110, 0x16},
1006          {104, 0x16},
1007          {98, 0x16},
1008          {110, 0x15},
1009          {104, 0x15},
1010          {98, 0x15},
1011          {110, 0x14},
1012          {104, 0x14},
1013          {98, 0x14},
1014          {110, 0x13},
1015          {104, 0x13},
1016          {98, 0x13},
1017          {110, 0x12},
1018          {104, 0x08},
1019          {98, 0x08},
1020          {110, 0x07},
1021          {104, 0x07},
1022          {98, 0x07},
1023          {110, 0x06},
1024          {104, 0x06},
1025          {98, 0x06},
1026          {110, 0x05},
1027          {104, 0x05},
1028          {98, 0x05},
1029          {110, 0x04},
1030          {104, 0x04},
1031          {98, 0x04},
1032          {110, 0x03},
1033          {104, 0x03},
1034          {98, 0x03},
1035          {110, 0x02},
1036          {104, 0x02},
1037          {98, 0x02},
1038          {110, 0x01},
1039          {104, 0x01},
1040          {98, 0x01},
1041          {110, 0x00},
1042          {104, 0x00},
1043          {98, 0x00},
1044          {93, 0x00},
1045          {88, 0x00},
1046          {83, 0x00},
1047          {78, 0x00},
1048          },
1049         /* 2.4GHz power gain index table */
1050         {
1051          {110, 0x3f},           /* highest txpower */
1052          {104, 0x3f},
1053          {98, 0x3f},
1054          {110, 0x3e},
1055          {104, 0x3e},
1056          {98, 0x3e},
1057          {110, 0x3d},
1058          {104, 0x3d},
1059          {98, 0x3d},
1060          {110, 0x3c},
1061          {104, 0x3c},
1062          {98, 0x3c},
1063          {110, 0x3b},
1064          {104, 0x3b},
1065          {98, 0x3b},
1066          {110, 0x3a},
1067          {104, 0x3a},
1068          {98, 0x3a},
1069          {110, 0x39},
1070          {104, 0x39},
1071          {98, 0x39},
1072          {110, 0x38},
1073          {104, 0x38},
1074          {98, 0x38},
1075          {110, 0x37},
1076          {104, 0x37},
1077          {98, 0x37},
1078          {110, 0x36},
1079          {104, 0x36},
1080          {98, 0x36},
1081          {110, 0x35},
1082          {104, 0x35},
1083          {98, 0x35},
1084          {110, 0x34},
1085          {104, 0x34},
1086          {98, 0x34},
1087          {110, 0x33},
1088          {104, 0x33},
1089          {98, 0x33},
1090          {110, 0x32},
1091          {104, 0x32},
1092          {98, 0x32},
1093          {110, 0x31},
1094          {104, 0x31},
1095          {98, 0x31},
1096          {110, 0x30},
1097          {104, 0x30},
1098          {98, 0x30},
1099          {110, 0x6},
1100          {104, 0x6},
1101          {98, 0x6},
1102          {110, 0x5},
1103          {104, 0x5},
1104          {98, 0x5},
1105          {110, 0x4},
1106          {104, 0x4},
1107          {98, 0x4},
1108          {110, 0x3},
1109          {104, 0x3},
1110          {98, 0x3},
1111          {110, 0x2},
1112          {104, 0x2},
1113          {98, 0x2},
1114          {110, 0x1},
1115          {104, 0x1},
1116          {98, 0x1},
1117          {110, 0x0},
1118          {104, 0x0},
1119          {98, 0x0},
1120          {97, 0},
1121          {96, 0},
1122          {95, 0},
1123          {94, 0},
1124          {93, 0},
1125          {92, 0},
1126          {91, 0},
1127          {90, 0},
1128          {89, 0},
1129          {88, 0},
1130          {87, 0},
1131          {86, 0},
1132          {85, 0},
1133          {84, 0},
1134          {83, 0},
1135          {82, 0},
1136          {81, 0},
1137          {80, 0},
1138          {79, 0},
1139          {78, 0},
1140          {77, 0},
1141          {76, 0},
1142          {75, 0},
1143          {74, 0},
1144          {73, 0},
1145          {72, 0},
1146          {71, 0},
1147          {70, 0},
1148          {69, 0},
1149          {68, 0},
1150          {67, 0},
1151          {66, 0},
1152          {65, 0},
1153          {64, 0},
1154          {63, 0},
1155          {62, 0},
1156          {61, 0},
1157          {60, 0},
1158          {59, 0},
1159          }
1160 };
1161
1162 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1163                                     u8 is_ht40, u8 ctrl_chan_high,
1164                                     struct iwl4965_tx_power_db *tx_power_tbl)
1165 {
1166         u8 saturation_power;
1167         s32 target_power;
1168         s32 user_target_power;
1169         s32 power_limit;
1170         s32 current_temp;
1171         s32 reg_limit;
1172         s32 current_regulatory;
1173         s32 txatten_grp = CALIB_CH_GROUP_MAX;
1174         int i;
1175         int c;
1176         const struct iwl_channel_info *ch_info = NULL;
1177         struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1178         const struct iwl_eeprom_calib_measure *measurement;
1179         s16 voltage;
1180         s32 init_voltage;
1181         s32 voltage_compensation;
1182         s32 degrees_per_05db_num;
1183         s32 degrees_per_05db_denom;
1184         s32 factory_temp;
1185         s32 temperature_comp[2];
1186         s32 factory_gain_index[2];
1187         s32 factory_actual_pwr[2];
1188         s32 power_index;
1189
1190         /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
1191          *   are used for indexing into txpower table) */
1192         user_target_power = 2 * priv->tx_power_user_lmt;
1193
1194         /* Get current (RXON) channel, band, width */
1195         IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_ht40 %d\n", channel, band,
1196                           is_ht40);
1197
1198         ch_info = iwl_get_channel_info(priv, priv->band, channel);
1199
1200         if (!is_channel_valid(ch_info))
1201                 return -EINVAL;
1202
1203         /* get txatten group, used to select 1) thermal txpower adjustment
1204          *   and 2) mimo txpower balance between Tx chains. */
1205         txatten_grp = iwl4965_get_tx_atten_grp(channel);
1206         if (txatten_grp < 0) {
1207                 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
1208                           channel);
1209                 return -EINVAL;
1210         }
1211
1212         IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
1213                           channel, txatten_grp);
1214
1215         if (is_ht40) {
1216                 if (ctrl_chan_high)
1217                         channel -= 2;
1218                 else
1219                         channel += 2;
1220         }
1221
1222         /* hardware txpower limits ...
1223          * saturation (clipping distortion) txpowers are in half-dBm */
1224         if (band)
1225                 saturation_power = priv->calib_info->saturation_power24;
1226         else
1227                 saturation_power = priv->calib_info->saturation_power52;
1228
1229         if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1230             saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1231                 if (band)
1232                         saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1233                 else
1234                         saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1235         }
1236
1237         /* regulatory txpower limits ... reg_limit values are in half-dBm,
1238          *   max_power_avg values are in dBm, convert * 2 */
1239         if (is_ht40)
1240                 reg_limit = ch_info->ht40_max_power_avg * 2;
1241         else
1242                 reg_limit = ch_info->max_power_avg * 2;
1243
1244         if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1245             (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1246                 if (band)
1247                         reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1248                 else
1249                         reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1250         }
1251
1252         /* Interpolate txpower calibration values for this channel,
1253          *   based on factory calibration tests on spaced channels. */
1254         iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1255
1256         /* calculate tx gain adjustment based on power supply voltage */
1257         voltage = priv->calib_info->voltage;
1258         init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1259         voltage_compensation =
1260             iwl4965_get_voltage_compensation(voltage, init_voltage);
1261
1262         IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
1263                           init_voltage,
1264                           voltage, voltage_compensation);
1265
1266         /* get current temperature (Celsius) */
1267         current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1268         current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1269         current_temp = KELVIN_TO_CELSIUS(current_temp);
1270
1271         /* select thermal txpower adjustment params, based on channel group
1272          *   (same frequency group used for mimo txatten adjustment) */
1273         degrees_per_05db_num =
1274             tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1275         degrees_per_05db_denom =
1276             tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1277
1278         /* get per-chain txpower values from factory measurements */
1279         for (c = 0; c < 2; c++) {
1280                 measurement = &ch_eeprom_info.measurements[c][1];
1281
1282                 /* txgain adjustment (in half-dB steps) based on difference
1283                  *   between factory and current temperature */
1284                 factory_temp = measurement->temperature;
1285                 iwl4965_math_div_round((current_temp - factory_temp) *
1286                                        degrees_per_05db_denom,
1287                                        degrees_per_05db_num,
1288                                        &temperature_comp[c]);
1289
1290                 factory_gain_index[c] = measurement->gain_idx;
1291                 factory_actual_pwr[c] = measurement->actual_pow;
1292
1293                 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1294                 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
1295                                   "curr tmp %d, comp %d steps\n",
1296                                   factory_temp, current_temp,
1297                                   temperature_comp[c]);
1298
1299                 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
1300                                   factory_gain_index[c],
1301                                   factory_actual_pwr[c]);
1302         }
1303
1304         /* for each of 33 bit-rates (including 1 for CCK) */
1305         for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1306                 u8 is_mimo_rate;
1307                 union iwl4965_tx_power_dual_stream tx_power;
1308
1309                 /* for mimo, reduce each chain's txpower by half
1310                  * (3dB, 6 steps), so total output power is regulatory
1311                  * compliant. */
1312                 if (i & 0x8) {
1313                         current_regulatory = reg_limit -
1314                             IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1315                         is_mimo_rate = 1;
1316                 } else {
1317                         current_regulatory = reg_limit;
1318                         is_mimo_rate = 0;
1319                 }
1320
1321                 /* find txpower limit, either hardware or regulatory */
1322                 power_limit = saturation_power - back_off_table[i];
1323                 if (power_limit > current_regulatory)
1324                         power_limit = current_regulatory;
1325
1326                 /* reduce user's txpower request if necessary
1327                  * for this rate on this channel */
1328                 target_power = user_target_power;
1329                 if (target_power > power_limit)
1330                         target_power = power_limit;
1331
1332                 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
1333                                   i, saturation_power - back_off_table[i],
1334                                   current_regulatory, user_target_power,
1335                                   target_power);
1336
1337                 /* for each of 2 Tx chains (radio transmitters) */
1338                 for (c = 0; c < 2; c++) {
1339                         s32 atten_value;
1340
1341                         if (is_mimo_rate)
1342                                 atten_value =
1343                                     (s32)le32_to_cpu(priv->card_alive_init.
1344                                     tx_atten[txatten_grp][c]);
1345                         else
1346                                 atten_value = 0;
1347
1348                         /* calculate index; higher index means lower txpower */
1349                         power_index = (u8) (factory_gain_index[c] -
1350                                             (target_power -
1351                                              factory_actual_pwr[c]) -
1352                                             temperature_comp[c] -
1353                                             voltage_compensation +
1354                                             atten_value);
1355
1356 /*                      IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
1357                                                 power_index); */
1358
1359                         if (power_index < get_min_power_index(i, band))
1360                                 power_index = get_min_power_index(i, band);
1361
1362                         /* adjust 5 GHz index to support negative indexes */
1363                         if (!band)
1364                                 power_index += 9;
1365
1366                         /* CCK, rate 32, reduce txpower for CCK */
1367                         if (i == POWER_TABLE_CCK_ENTRY)
1368                                 power_index +=
1369                                     IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1370
1371                         /* stay within the table! */
1372                         if (power_index > 107) {
1373                                 IWL_WARN(priv, "txpower index %d > 107\n",
1374                                             power_index);
1375                                 power_index = 107;
1376                         }
1377                         if (power_index < 0) {
1378                                 IWL_WARN(priv, "txpower index %d < 0\n",
1379                                             power_index);
1380                                 power_index = 0;
1381                         }
1382
1383                         /* fill txpower command for this rate/chain */
1384                         tx_power.s.radio_tx_gain[c] =
1385                                 gain_table[band][power_index].radio;
1386                         tx_power.s.dsp_predis_atten[c] =
1387                                 gain_table[band][power_index].dsp;
1388
1389                         IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
1390                                           "gain 0x%02x dsp %d\n",
1391                                           c, atten_value, power_index,
1392                                         tx_power.s.radio_tx_gain[c],
1393                                         tx_power.s.dsp_predis_atten[c]);
1394                 } /* for each chain */
1395
1396                 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1397
1398         } /* for each rate */
1399
1400         return 0;
1401 }
1402
1403 /**
1404  * iwl4965_send_tx_power - Configure the TXPOWER level user limit
1405  *
1406  * Uses the active RXON for channel, band, and characteristics (ht40, high)
1407  * The power limit is taken from priv->tx_power_user_lmt.
1408  */
1409 static int iwl4965_send_tx_power(struct iwl_priv *priv)
1410 {
1411         struct iwl4965_txpowertable_cmd cmd = { 0 };
1412         int ret;
1413         u8 band = 0;
1414         bool is_ht40 = false;
1415         u8 ctrl_chan_high = 0;
1416
1417         if (test_bit(STATUS_SCANNING, &priv->status)) {
1418                 /* If this gets hit a lot, switch it to a BUG() and catch
1419                  * the stack trace to find out who is calling this during
1420                  * a scan. */
1421                 IWL_WARN(priv, "TX Power requested while scanning!\n");
1422                 return -EAGAIN;
1423         }
1424
1425         band = priv->band == IEEE80211_BAND_2GHZ;
1426
1427         is_ht40 =  is_ht40_channel(priv->active_rxon.flags);
1428
1429         if (is_ht40 &&
1430             (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1431                 ctrl_chan_high = 1;
1432
1433         cmd.band = band;
1434         cmd.channel = priv->active_rxon.channel;
1435
1436         ret = iwl4965_fill_txpower_tbl(priv, band,
1437                                 le16_to_cpu(priv->active_rxon.channel),
1438                                 is_ht40, ctrl_chan_high, &cmd.tx_power);
1439         if (ret)
1440                 goto out;
1441
1442         ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1443
1444 out:
1445         return ret;
1446 }
1447
1448 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1449 {
1450         int ret = 0;
1451         struct iwl4965_rxon_assoc_cmd rxon_assoc;
1452         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1453         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1454
1455         if ((rxon1->flags == rxon2->flags) &&
1456             (rxon1->filter_flags == rxon2->filter_flags) &&
1457             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1458             (rxon1->ofdm_ht_single_stream_basic_rates ==
1459              rxon2->ofdm_ht_single_stream_basic_rates) &&
1460             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1461              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1462             (rxon1->rx_chain == rxon2->rx_chain) &&
1463             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1464                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1465                 return 0;
1466         }
1467
1468         rxon_assoc.flags = priv->staging_rxon.flags;
1469         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1470         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1471         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1472         rxon_assoc.reserved = 0;
1473         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1474             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1475         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1476             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1477         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1478
1479         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1480                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1481         if (ret)
1482                 return ret;
1483
1484         return ret;
1485 }
1486
1487 #ifdef IEEE80211_CONF_CHANNEL_SWITCH
1488 static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1489 {
1490         int rc;
1491         u8 band = 0;
1492         bool is_ht40 = false;
1493         u8 ctrl_chan_high = 0;
1494         struct iwl4965_channel_switch_cmd cmd = { 0 };
1495         const struct iwl_channel_info *ch_info;
1496
1497         band = priv->band == IEEE80211_BAND_2GHZ;
1498
1499         ch_info = iwl_get_channel_info(priv, priv->band, channel);
1500
1501         is_ht40 = is_ht40_channel(priv->staging_rxon.flags);
1502
1503         if (is_ht40 &&
1504             (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1505                 ctrl_chan_high = 1;
1506
1507         cmd.band = band;
1508         cmd.expect_beacon = 0;
1509         cmd.channel = cpu_to_le16(channel);
1510         cmd.rxon_flags = priv->active_rxon.flags;
1511         cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1512         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1513         if (ch_info)
1514                 cmd.expect_beacon = is_channel_radar(ch_info);
1515         else
1516                 cmd.expect_beacon = 1;
1517
1518         rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_ht40,
1519                                       ctrl_chan_high, &cmd.tx_power);
1520         if (rc) {
1521                 IWL_DEBUG_11H(priv, "error:%d  fill txpower_tbl\n", rc);
1522                 return rc;
1523         }
1524
1525         rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1526         return rc;
1527 }
1528 #endif
1529
1530 /**
1531  * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1532  */
1533 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1534                                             struct iwl_tx_queue *txq,
1535                                             u16 byte_cnt)
1536 {
1537         struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
1538         int txq_id = txq->q.id;
1539         int write_ptr = txq->q.write_ptr;
1540         int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1541         __le16 bc_ent;
1542
1543         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
1544
1545         bc_ent = cpu_to_le16(len & 0xFFF);
1546         /* Set up byte count within first 256 entries */
1547         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1548
1549         /* If within first 64 entries, duplicate at end */
1550         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
1551                 scd_bc_tbl[txq_id].
1552                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
1553 }
1554
1555 /**
1556  * sign_extend - Sign extend a value using specified bit as sign-bit
1557  *
1558  * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1559  * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1560  *
1561  * @param oper value to sign extend
1562  * @param index 0 based bit index (0<=index<32) to sign bit
1563  */
1564 static s32 sign_extend(u32 oper, int index)
1565 {
1566         u8 shift = 31 - index;
1567
1568         return (s32)(oper << shift) >> shift;
1569 }
1570
1571 /**
1572  * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
1573  * @statistics: Provides the temperature reading from the uCode
1574  *
1575  * A return of <0 indicates bogus data in the statistics
1576  */
1577 static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1578 {
1579         s32 temperature;
1580         s32 vt;
1581         s32 R1, R2, R3;
1582         u32 R4;
1583
1584         if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1585                 (priv->statistics.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)) {
1586                 IWL_DEBUG_TEMP(priv, "Running HT40 temperature calibration\n");
1587                 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1588                 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1589                 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1590                 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1591         } else {
1592                 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
1593                 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1594                 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1595                 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1596                 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1597         }
1598
1599         /*
1600          * Temperature is only 23 bits, so sign extend out to 32.
1601          *
1602          * NOTE If we haven't received a statistics notification yet
1603          * with an updated temperature, use R4 provided to us in the
1604          * "initialize" ALIVE response.
1605          */
1606         if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1607                 vt = sign_extend(R4, 23);
1608         else
1609                 vt = sign_extend(
1610                         le32_to_cpu(priv->statistics.general.temperature), 23);
1611
1612         IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
1613
1614         if (R3 == R1) {
1615                 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
1616                 return -1;
1617         }
1618
1619         /* Calculate temperature in degrees Kelvin, adjust by 97%.
1620          * Add offset to center the adjustment around 0 degrees Centigrade. */
1621         temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1622         temperature /= (R3 - R1);
1623         temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
1624
1625         IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
1626                         temperature, KELVIN_TO_CELSIUS(temperature));
1627
1628         return temperature;
1629 }
1630
1631 /* Adjust Txpower only if temperature variance is greater than threshold. */
1632 #define IWL_TEMPERATURE_THRESHOLD   3
1633
1634 /**
1635  * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1636  *
1637  * If the temperature changed has changed sufficiently, then a recalibration
1638  * is needed.
1639  *
1640  * Assumes caller will replace priv->last_temperature once calibration
1641  * executed.
1642  */
1643 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
1644 {
1645         int temp_diff;
1646
1647         if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1648                 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
1649                 return 0;
1650         }
1651
1652         temp_diff = priv->temperature - priv->last_temperature;
1653
1654         /* get absolute value */
1655         if (temp_diff < 0) {
1656                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d, \n", temp_diff);
1657                 temp_diff = -temp_diff;
1658         } else if (temp_diff == 0)
1659                 IWL_DEBUG_POWER(priv, "Same temp, \n");
1660         else
1661                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d, \n", temp_diff);
1662
1663         if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1664                 IWL_DEBUG_POWER(priv, "Thermal txpower calib not needed\n");
1665                 return 0;
1666         }
1667
1668         IWL_DEBUG_POWER(priv, "Thermal txpower calib needed\n");
1669
1670         return 1;
1671 }
1672
1673 static void iwl4965_temperature_calib(struct iwl_priv *priv)
1674 {
1675         s32 temp;
1676
1677         temp = iwl4965_hw_get_temperature(priv);
1678         if (temp < 0)
1679                 return;
1680
1681         if (priv->temperature != temp) {
1682                 if (priv->temperature)
1683                         IWL_DEBUG_TEMP(priv, "Temperature changed "
1684                                        "from %dC to %dC\n",
1685                                        KELVIN_TO_CELSIUS(priv->temperature),
1686                                        KELVIN_TO_CELSIUS(temp));
1687                 else
1688                         IWL_DEBUG_TEMP(priv, "Temperature "
1689                                        "initialized to %dC\n",
1690                                        KELVIN_TO_CELSIUS(temp));
1691         }
1692
1693         priv->temperature = temp;
1694         iwl_tt_handler(priv);
1695         set_bit(STATUS_TEMPERATURE, &priv->status);
1696
1697         if (!priv->disable_tx_power_cal &&
1698              unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1699              iwl4965_is_temp_calib_needed(priv))
1700                 queue_work(priv->workqueue, &priv->txpower_work);
1701 }
1702
1703 /**
1704  * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1705  */
1706 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1707                                             u16 txq_id)
1708 {
1709         /* Simply stop the queue, but don't change any configuration;
1710          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1711         iwl_write_prph(priv,
1712                 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1713                 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1714                 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1715 }
1716
1717 /**
1718  * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1719  * priv->lock must be held by the caller
1720  */
1721 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1722                                    u16 ssn_idx, u8 tx_fifo)
1723 {
1724         if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1725             (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1726              <= txq_id)) {
1727                 IWL_WARN(priv,
1728                         "queue number out of range: %d, must be %d to %d\n",
1729                         txq_id, IWL49_FIRST_AMPDU_QUEUE,
1730                         IWL49_FIRST_AMPDU_QUEUE +
1731                         priv->cfg->num_of_ampdu_queues - 1);
1732                 return -EINVAL;
1733         }
1734
1735         iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1736
1737         iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1738
1739         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1740         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1741         /* supposes that ssn_idx is valid (!= 0xFFF) */
1742         iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1743
1744         iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1745         iwl_txq_ctx_deactivate(priv, txq_id);
1746         iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1747
1748         return 0;
1749 }
1750
1751 /**
1752  * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1753  */
1754 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1755                                         u16 txq_id)
1756 {
1757         u32 tbl_dw_addr;
1758         u32 tbl_dw;
1759         u16 scd_q2ratid;
1760
1761         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1762
1763         tbl_dw_addr = priv->scd_base_addr +
1764                         IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1765
1766         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1767
1768         if (txq_id & 0x1)
1769                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1770         else
1771                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1772
1773         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1774
1775         return 0;
1776 }
1777
1778
1779 /**
1780  * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1781  *
1782  * NOTE:  txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1783  *        i.e. it must be one of the higher queues used for aggregation
1784  */
1785 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1786                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1787 {
1788         unsigned long flags;
1789         u16 ra_tid;
1790
1791         if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1792             (IWL49_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
1793              <= txq_id)) {
1794                 IWL_WARN(priv,
1795                         "queue number out of range: %d, must be %d to %d\n",
1796                         txq_id, IWL49_FIRST_AMPDU_QUEUE,
1797                         IWL49_FIRST_AMPDU_QUEUE +
1798                         priv->cfg->num_of_ampdu_queues - 1);
1799                 return -EINVAL;
1800         }
1801
1802         ra_tid = BUILD_RAxTID(sta_id, tid);
1803
1804         /* Modify device's station table to Tx this TID */
1805         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1806
1807         spin_lock_irqsave(&priv->lock, flags);
1808
1809         /* Stop this Tx queue before configuring it */
1810         iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1811
1812         /* Map receiver-address / traffic-ID to this queue */
1813         iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1814
1815         /* Set this queue as a chain-building queue */
1816         iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1817
1818         /* Place first TFD at index corresponding to start sequence number.
1819          * Assumes that ssn_idx is valid (!= 0xFFF) */
1820         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1821         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1822         iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1823
1824         /* Set up Tx window size and frame limit for this queue */
1825         iwl_write_targ_mem(priv,
1826                 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1827                 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1828                 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1829
1830         iwl_write_targ_mem(priv, priv->scd_base_addr +
1831                 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1832                 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1833                 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1834
1835         iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1836
1837         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1838         iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1839
1840         spin_unlock_irqrestore(&priv->lock, flags);
1841
1842         return 0;
1843 }
1844
1845
1846 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1847 {
1848         switch (cmd_id) {
1849         case REPLY_RXON:
1850                 return (u16) sizeof(struct iwl4965_rxon_cmd);
1851         default:
1852                 return len;
1853         }
1854 }
1855
1856 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1857 {
1858         struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1859         addsta->mode = cmd->mode;
1860         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1861         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1862         addsta->station_flags = cmd->station_flags;
1863         addsta->station_flags_msk = cmd->station_flags_msk;
1864         addsta->tid_disable_tx = cmd->tid_disable_tx;
1865         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1866         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1867         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1868         addsta->reserved1 = cpu_to_le16(0);
1869         addsta->reserved2 = cpu_to_le32(0);
1870
1871         return (u16)sizeof(struct iwl4965_addsta_cmd);
1872 }
1873
1874 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1875 {
1876         return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
1877 }
1878
1879 /**
1880  * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
1881  */
1882 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1883                                       struct iwl_ht_agg *agg,
1884                                       struct iwl4965_tx_resp *tx_resp,
1885                                       int txq_id, u16 start_idx)
1886 {
1887         u16 status;
1888         struct agg_tx_status *frame_status = tx_resp->u.agg_status;
1889         struct ieee80211_tx_info *info = NULL;
1890         struct ieee80211_hdr *hdr = NULL;
1891         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1892         int i, sh, idx;
1893         u16 seq;
1894         if (agg->wait_for_ba)
1895                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1896
1897         agg->frame_count = tx_resp->frame_count;
1898         agg->start_idx = start_idx;
1899         agg->rate_n_flags = rate_n_flags;
1900         agg->bitmap = 0;
1901
1902         /* num frames attempted by Tx command */
1903         if (agg->frame_count == 1) {
1904                 /* Only one frame was attempted; no block-ack will arrive */
1905                 status = le16_to_cpu(frame_status[0].status);
1906                 idx = start_idx;
1907
1908                 /* FIXME: code repetition */
1909                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1910                                    agg->frame_count, agg->start_idx, idx);
1911
1912                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1913                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1914                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1915                 info->flags |= iwl_is_tx_success(status) ?
1916                         IEEE80211_TX_STAT_ACK : 0;
1917                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1918                 /* FIXME: code repetition end */
1919
1920                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1921                                     status & 0xff, tx_resp->failure_frame);
1922                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1923
1924                 agg->wait_for_ba = 0;
1925         } else {
1926                 /* Two or more frames were attempted; expect block-ack */
1927                 u64 bitmap = 0;
1928                 int start = agg->start_idx;
1929
1930                 /* Construct bit-map of pending frames within Tx window */
1931                 for (i = 0; i < agg->frame_count; i++) {
1932                         u16 sc;
1933                         status = le16_to_cpu(frame_status[i].status);
1934                         seq  = le16_to_cpu(frame_status[i].sequence);
1935                         idx = SEQ_TO_INDEX(seq);
1936                         txq_id = SEQ_TO_QUEUE(seq);
1937
1938                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1939                                       AGG_TX_STATE_ABORT_MSK))
1940                                 continue;
1941
1942                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1943                                            agg->frame_count, txq_id, idx);
1944
1945                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1946                         if (!hdr) {
1947                                 IWL_ERR(priv,
1948                                         "BUG_ON idx doesn't point to valid skb"
1949                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1950                                 return -1;
1951                         }
1952
1953                         sc = le16_to_cpu(hdr->seq_ctrl);
1954                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1955                                 IWL_ERR(priv,
1956                                         "BUG_ON idx doesn't match seq control"
1957                                         " idx=%d, seq_idx=%d, seq=%d\n",
1958                                         idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
1959                                 return -1;
1960                         }
1961
1962                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1963                                            i, idx, SEQ_TO_SN(sc));
1964
1965                         sh = idx - start;
1966                         if (sh > 64) {
1967                                 sh = (start - idx) + 0xff;
1968                                 bitmap = bitmap << sh;
1969                                 sh = 0;
1970                                 start = idx;
1971                         } else if (sh < -64)
1972                                 sh  = 0xff - (start - idx);
1973                         else if (sh < 0) {
1974                                 sh = start - idx;
1975                                 start = idx;
1976                                 bitmap = bitmap << sh;
1977                                 sh = 0;
1978                         }
1979                         bitmap |= 1ULL << sh;
1980                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1981                                            start, (unsigned long long)bitmap);
1982                 }
1983
1984                 agg->bitmap = bitmap;
1985                 agg->start_idx = start;
1986                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1987                                    agg->frame_count, agg->start_idx,
1988                                    (unsigned long long)agg->bitmap);
1989
1990                 if (bitmap)
1991                         agg->wait_for_ba = 1;
1992         }
1993         return 0;
1994 }
1995
1996 /**
1997  * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
1998  */
1999 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2000                                 struct iwl_rx_mem_buffer *rxb)
2001 {
2002         struct iwl_rx_packet *pkt = rxb_addr(rxb);
2003         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2004         int txq_id = SEQ_TO_QUEUE(sequence);
2005         int index = SEQ_TO_INDEX(sequence);
2006         struct iwl_tx_queue *txq = &priv->txq[txq_id];
2007         struct ieee80211_hdr *hdr;
2008         struct ieee80211_tx_info *info;
2009         struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2010         u32  status = le32_to_cpu(tx_resp->u.status);
2011         int tid = MAX_TID_COUNT;
2012         int sta_id;
2013         int freed;
2014         u8 *qc = NULL;
2015
2016         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2017                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
2018                           "is out of range [0-%d] %d %d\n", txq_id,
2019                           index, txq->q.n_bd, txq->q.write_ptr,
2020                           txq->q.read_ptr);
2021                 return;
2022         }
2023
2024         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2025         memset(&info->status, 0, sizeof(info->status));
2026
2027         hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
2028         if (ieee80211_is_data_qos(hdr->frame_control)) {
2029                 qc = ieee80211_get_qos_ctl(hdr);
2030                 tid = qc[0] & 0xf;
2031         }
2032
2033         sta_id = iwl_get_ra_sta_id(priv, hdr);
2034         if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2035                 IWL_ERR(priv, "Station not known\n");
2036                 return;
2037         }
2038
2039         if (txq->sched_retry) {
2040                 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2041                 struct iwl_ht_agg *agg = NULL;
2042
2043                 WARN_ON(!qc);
2044
2045                 agg = &priv->stations[sta_id].tid[tid].agg;
2046
2047                 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2048
2049                 /* check if BAR is needed */
2050                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2051                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2052
2053                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2054                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2055                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
2056                                            "%d index %d\n", scd_ssn , index);
2057                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2058                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2059
2060                         if (priv->mac80211_registered &&
2061                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2062                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
2063                                 if (agg->state == IWL_AGG_OFF)
2064                                         iwl_wake_queue(priv, txq_id);
2065                                 else
2066                                         iwl_wake_queue(priv, txq->swq_id);
2067                         }
2068                 }
2069         } else {
2070                 info->status.rates[0].count = tx_resp->failure_frame + 1;
2071                 info->flags |= iwl_is_tx_success(status) ?
2072                                         IEEE80211_TX_STAT_ACK : 0;
2073                 iwl_hwrate_to_tx_control(priv,
2074                                         le32_to_cpu(tx_resp->rate_n_flags),
2075                                         info);
2076
2077                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
2078                                    "rate_n_flags 0x%x retries %d\n",
2079                                    txq_id,
2080                                    iwl_get_tx_fail_reason(status), status,
2081                                    le32_to_cpu(tx_resp->rate_n_flags),
2082                                    tx_resp->failure_frame);
2083
2084                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2085                 if (qc && likely(sta_id != IWL_INVALID_STATION))
2086                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2087
2088                 if (priv->mac80211_registered &&
2089                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
2090                         iwl_wake_queue(priv, txq_id);
2091         }
2092
2093         if (qc && likely(sta_id != IWL_INVALID_STATION))
2094                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2095
2096         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2097                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
2098 }
2099
2100 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2101                              struct iwl_rx_phy_res *rx_resp)
2102 {
2103         /* data from PHY/DSP regarding signal strength, etc.,
2104          *   contents are always there, not configurable by host.  */
2105         struct iwl4965_rx_non_cfg_phy *ncphy =
2106             (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2107         u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2108                         >> IWL49_AGC_DB_POS;
2109
2110         u32 valid_antennae =
2111             (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2112                         >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2113         u8 max_rssi = 0;
2114         u32 i;
2115
2116         /* Find max rssi among 3 possible receivers.
2117          * These values are measured by the digital signal processor (DSP).
2118          * They should stay fairly constant even as the signal strength varies,
2119          *   if the radio's automatic gain control (AGC) is working right.
2120          * AGC value (see below) will provide the "interesting" info. */
2121         for (i = 0; i < 3; i++)
2122                 if (valid_antennae & (1 << i))
2123                         max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2124
2125         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2126                 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2127                 max_rssi, agc);
2128
2129         /* dBm = max_rssi dB - agc dB - constant.
2130          * Higher AGC (higher radio gain) means lower signal. */
2131         return max_rssi - agc - IWL49_RSSI_OFFSET;
2132 }
2133
2134
2135 /* Set up 4965-specific Rx frame reply handlers */
2136 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
2137 {
2138         /* Legacy Rx frames */
2139         priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
2140         /* Tx response */
2141         priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
2142 }
2143
2144 static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2145 {
2146         INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2147 }
2148
2149 static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2150 {
2151         cancel_work_sync(&priv->txpower_work);
2152 }
2153
2154 #define IWL4965_UCODE_GET(item)                                         \
2155 static u32 iwl4965_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2156                                     u32 api_ver)                        \
2157 {                                                                       \
2158         return le32_to_cpu(ucode->u.v1.item);                           \
2159 }
2160
2161 static u32 iwl4965_ucode_get_header_size(u32 api_ver)
2162 {
2163         return UCODE_HEADER_SIZE(1);
2164 }
2165 static u32 iwl4965_ucode_get_build(const struct iwl_ucode_header *ucode,
2166                                    u32 api_ver)
2167 {
2168         return 0;
2169 }
2170 static u8 *iwl4965_ucode_get_data(const struct iwl_ucode_header *ucode,
2171                                   u32 api_ver)
2172 {
2173         return (u8 *) ucode->u.v1.data;
2174 }
2175
2176 IWL4965_UCODE_GET(inst_size);
2177 IWL4965_UCODE_GET(data_size);
2178 IWL4965_UCODE_GET(init_size);
2179 IWL4965_UCODE_GET(init_data_size);
2180 IWL4965_UCODE_GET(boot_size);
2181
2182 static struct iwl_hcmd_ops iwl4965_hcmd = {
2183         .rxon_assoc = iwl4965_send_rxon_assoc,
2184         .commit_rxon = iwl_commit_rxon,
2185         .set_rxon_chain = iwl_set_rxon_chain,
2186 };
2187
2188 static struct iwl_ucode_ops iwl4965_ucode = {
2189         .get_header_size = iwl4965_ucode_get_header_size,
2190         .get_build = iwl4965_ucode_get_build,
2191         .get_inst_size = iwl4965_ucode_get_inst_size,
2192         .get_data_size = iwl4965_ucode_get_data_size,
2193         .get_init_size = iwl4965_ucode_get_init_size,
2194         .get_init_data_size = iwl4965_ucode_get_init_data_size,
2195         .get_boot_size = iwl4965_ucode_get_boot_size,
2196         .get_data = iwl4965_ucode_get_data,
2197 };
2198 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
2199         .get_hcmd_size = iwl4965_get_hcmd_size,
2200         .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2201         .chain_noise_reset = iwl4965_chain_noise_reset,
2202         .gain_computation = iwl4965_gain_computation,
2203         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2204         .calc_rssi = iwl4965_calc_rssi,
2205 };
2206
2207 static struct iwl_lib_ops iwl4965_lib = {
2208         .set_hw_params = iwl4965_hw_set_hw_params,
2209         .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
2210         .txq_set_sched = iwl4965_txq_set_sched,
2211         .txq_agg_enable = iwl4965_txq_agg_enable,
2212         .txq_agg_disable = iwl4965_txq_agg_disable,
2213         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2214         .txq_free_tfd = iwl_hw_txq_free_tfd,
2215         .txq_init = iwl_hw_tx_queue_init,
2216         .rx_handler_setup = iwl4965_rx_handler_setup,
2217         .setup_deferred_work = iwl4965_setup_deferred_work,
2218         .cancel_deferred_work = iwl4965_cancel_deferred_work,
2219         .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2220         .alive_notify = iwl4965_alive_notify,
2221         .init_alive_start = iwl4965_init_alive_start,
2222         .load_ucode = iwl4965_load_bsm,
2223         .dump_nic_event_log = iwl_dump_nic_event_log,
2224         .dump_nic_error_log = iwl_dump_nic_error_log,
2225         .apm_ops = {
2226                 .init = iwl4965_apm_init,
2227                 .stop = iwl_apm_stop,
2228                 .config = iwl4965_nic_config,
2229                 .set_pwr_src = iwl_set_pwr_src,
2230         },
2231         .eeprom_ops = {
2232                 .regulatory_bands = {
2233                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2234                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2235                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2236                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2237                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2238                         EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS,
2239                         EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS
2240                 },
2241                 .verify_signature  = iwlcore_eeprom_verify_signature,
2242                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2243                 .release_semaphore = iwlcore_eeprom_release_semaphore,
2244                 .calib_version = iwl4965_eeprom_calib_version,
2245                 .query_addr = iwlcore_eeprom_query_addr,
2246         },
2247         .send_tx_power  = iwl4965_send_tx_power,
2248         .update_chain_flags = iwl_update_chain_flags,
2249         .post_associate = iwl_post_associate,
2250         .config_ap = iwl_config_ap,
2251         .isr = iwl_isr_legacy,
2252         .temp_ops = {
2253                 .temperature = iwl4965_temperature_calib,
2254                 .set_ct_kill = iwl4965_set_ct_threshold,
2255         },
2256 };
2257
2258 static struct iwl_ops iwl4965_ops = {
2259         .ucode = &iwl4965_ucode,
2260         .lib = &iwl4965_lib,
2261         .hcmd = &iwl4965_hcmd,
2262         .utils = &iwl4965_hcmd_utils,
2263         .led = &iwlagn_led_ops,
2264 };
2265
2266 struct iwl_cfg iwl4965_agn_cfg = {
2267         .name = "4965AGN",
2268         .fw_name_pre = IWL4965_FW_PRE,
2269         .ucode_api_max = IWL4965_UCODE_API_MAX,
2270         .ucode_api_min = IWL4965_UCODE_API_MIN,
2271         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2272         .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
2273         .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2274         .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
2275         .ops = &iwl4965_ops,
2276         .num_of_queues = IWL49_NUM_QUEUES,
2277         .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
2278         .mod_params = &iwl4965_mod_params,
2279         .use_isr_legacy = true,
2280         .ht_greenfield_support = false,
2281         .broken_powersave = true,
2282         .led_compensation = 61,
2283         .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
2284 };
2285
2286 /* Module firmware */
2287 MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
2288
2289 module_param_named(antenna, iwl4965_mod_params.antenna, int, S_IRUGO);
2290 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2291 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, S_IRUGO);
2292 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
2293 module_param_named(
2294         disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, S_IRUGO);
2295 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2296
2297 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, S_IRUGO);
2298 MODULE_PARM_DESC(queues_num, "number of hw queues.");
2299 /* 11n */
2300 module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, S_IRUGO);
2301 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
2302 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K,
2303                    int, S_IRUGO);
2304 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
2305
2306 module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, S_IRUGO);
2307 MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");