drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 /*TODO: Remove include to iwl-core.h*/
  34 #include "iwl-core.h"
  35 #include "iwl-io.h"
  36 #include "iwl-helpers.h"
  37 #include "iwl-trans-int-pcie.h"
  38
  39 /******************************************************************************
  40  *
  41  * RX path functions
  42  *
  43  ******************************************************************************/
  44
  45 /*
  46  * Rx theory of operation
  47  *
  48  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  49  * each of which point to Receive Buffers to be filled by the NIC.  These get
  50  * used not only for Rx frames, but for any command response or notification
  51  * from the NIC.  The driver and NIC manage the Rx buffers by means
  52  * of indexes into the circular buffer.
  53  *
  54  * Rx Queue Indexes
  55  * The host/firmware share two index registers for managing the Rx buffers.
  56  *
  57  * The READ index maps to the first position that the firmware may be writing
  58  * to -- the driver can read up to (but not including) this position and get
  59  * good data.
  60  * The READ index is managed by the firmware once the card is enabled.
  61  *
  62  * The WRITE index maps to the last position the driver has read from -- the
  63  * position preceding WRITE is the last slot the firmware can place a packet.
  64  *
  65  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  66  * WRITE = READ.
  67  *
  68  * During initialization, the host sets up the READ queue position to the first
  69  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  70  *
  71  * When the firmware places a packet in a buffer, it will advance the READ index
  72  * and fire the RX interrupt.  The driver can then query the READ index and
  73  * process as many packets as possible, moving the WRITE index forward as it
  74  * resets the Rx queue buffers with new memory.
  75  *
  76  * The management in the driver is as follows:
  77  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  78  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  79  *   to replenish the iwl->rxq->rx_free.
  80  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  81  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  82  *   'processed' and 'read' driver indexes as well)
  83  * + A received packet is processed and handed to the kernel network stack,
  84  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  85  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  86  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  87  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  88  *   were enough free buffers and RX_STALLED is set it is cleared.
  89  *
  90  *
  91  * Driver sequence:
  92  *
  93  * iwl_rx_queue_alloc()   Allocates rx_free
  94  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  95  *                            iwl_rx_queue_restock
  96  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  97  *                            queue, updates firmware pointers, and updates
  98  *                            the WRITE index.  If insufficient rx_free buffers
  99  *                            are available, schedules iwl_rx_replenish
 100  *
 101  * -- enable interrupts --
 102  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 103  *                            READ INDEX, detaching the SKB from the pool.
 104  *                            Moves the packet buffer from queue to rx_used.
 105  *                            Calls iwl_rx_queue_restock to refill any empty
 106  *                            slots.
 107  * ...
 108  *
 109  */
 110
 111 /**
 112  * iwl_rx_queue_space - Return number of free slots available in queue.
 113  */
 114 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 115 {
 116         int s = q->read - q->write;
 117         if (s <= 0)
 118                 s += RX_QUEUE_SIZE;
 119         /* keep some buffer to not confuse full and empty queue */
 120         s -= 2;
 121         if (s < 0)
 122                 s = 0;
 123         return s;
 124 }
 125
 126 /**
 127  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 128  */
 129 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 130                         struct iwl_rx_queue *q)
 131 {
 132         unsigned long flags;
 133         u32 reg;
 134
 135         spin_lock_irqsave(&q->lock, flags);
 136
 137         if (q->need_update == 0)
 138                 goto exit_unlock;
 139
 140         if (hw_params(trans).shadow_reg_enable) {
 141                 /* shadow register enabled */
 142                 /* Device expects a multiple of 8 */
 143                 q->write_actual = (q->write & ~0x7);
 144                 iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
 145         } else {
 146                 /* If power-saving is in use, make sure device is awake */
 147                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 148                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
 149
 150                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 151                                 IWL_DEBUG_INFO(trans,
 152                                         "Rx queue requesting wakeup,"
 153                                         " GP1 = 0x%x\n", reg);
 154                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
 155                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 156                                 goto exit_unlock;
 157                         }
 158
 159                         q->write_actual = (q->write & ~0x7);
 160                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
 161                                         q->write_actual);
 162
 163                 /* Else device is assumed to be awake */
 164                 } else {
 165                         /* Device expects a multiple of 8 */
 166                         q->write_actual = (q->write & ~0x7);
 167                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
 168                                 q->write_actual);
 169                 }
 170         }
 171         q->need_update = 0;
 172
 173  exit_unlock:
 174         spin_unlock_irqrestore(&q->lock, flags);
 175 }
 176
 177 /**
 178  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 179  */
 180 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 181 {
 182         return cpu_to_le32((u32)(dma_addr >> 8));
 183 }
 184
 185 /**
 186  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 187  *
 188  * If there are slots in the RX queue that need to be restocked,
 189  * and we have free pre-allocated buffers, fill the ranks as much
 190  * as we can, pulling from rx_free.
 191  *
 192  * This moves the 'write' index forward to catch up with 'processed', and
 193  * also updates the memory address in the firmware to reference the new
 194  * target buffer.
 195  */
 196 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 197 {
 198         struct iwl_trans_pcie *trans_pcie =
 199                 IWL_TRANS_GET_PCIE_TRANS(trans);
 200
 201         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 202         struct list_head *element;
 203         struct iwl_rx_mem_buffer *rxb;
 204         unsigned long flags;
 205
 206         spin_lock_irqsave(&rxq->lock, flags);
 207         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 208                 /* The overwritten rxb must be a used one */
 209                 rxb = rxq->queue[rxq->write];
 210                 BUG_ON(rxb && rxb->page);
 211
 212                 /* Get next free Rx buffer, remove from free list */
 213                 element = rxq->rx_free.next;
 214                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 215                 list_del(element);
 216
 217                 /* Point to Rx buffer via next RBD in circular buffer */
 218                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 219                 rxq->queue[rxq->write] = rxb;
 220                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 221                 rxq->free_count--;
 222         }
 223         spin_unlock_irqrestore(&rxq->lock, flags);
 224         /* If the pre-allocated buffer pool is dropping low, schedule to
 225          * refill it */
 226         if (rxq->free_count <= RX_LOW_WATERMARK)
 227                 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
 228
 229
 230         /* If we've added more space for the firmware to place data, tell it.
 231          * Increment device's write pointer in multiples of 8. */
 232         if (rxq->write_actual != (rxq->write & ~0x7)) {
 233                 spin_lock_irqsave(&rxq->lock, flags);
 234                 rxq->need_update = 1;
 235                 spin_unlock_irqrestore(&rxq->lock, flags);
 236                 iwl_rx_queue_update_write_ptr(trans, rxq);
 237         }
 238 }
 239
 240 /**
 241  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 242  *
 243  * When moving to rx_free an SKB is allocated for the slot.
 244  *
 245  * Also restock the Rx queue via iwl_rx_queue_restock.
 246  * This is called as a scheduled work item (except for during initialization)
 247  */
 248 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 249 {
 250         struct iwl_trans_pcie *trans_pcie =
 251                 IWL_TRANS_GET_PCIE_TRANS(trans);
 252
 253         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 254         struct list_head *element;
 255         struct iwl_rx_mem_buffer *rxb;
 256         struct page *page;
 257         unsigned long flags;
 258         gfp_t gfp_mask = priority;
 259
 260         while (1) {
 261                 spin_lock_irqsave(&rxq->lock, flags);
 262                 if (list_empty(&rxq->rx_used)) {
 263                         spin_unlock_irqrestore(&rxq->lock, flags);
 264                         return;
 265                 }
 266                 spin_unlock_irqrestore(&rxq->lock, flags);
 267
 268                 if (rxq->free_count > RX_LOW_WATERMARK)
 269                         gfp_mask |= __GFP_NOWARN;
 270
 271                 if (hw_params(trans).rx_page_order > 0)
 272                         gfp_mask |= __GFP_COMP;
 273
 274                 /* Alloc a new receive buffer */
 275                 page = alloc_pages(gfp_mask,
 276                                   hw_params(trans).rx_page_order);
 277                 if (!page) {
 278                         if (net_ratelimit())
 279                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 280                                            "order: %d\n",
 281                                            hw_params(trans).rx_page_order);
 282
 283                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 284                             net_ratelimit())
 285                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 286                                          "Only %u free buffers remaining.\n",
 287                                          priority == GFP_ATOMIC ?
 288                                          "GFP_ATOMIC" : "GFP_KERNEL",
 289                                          rxq->free_count);
 290                         /* We don't reschedule replenish work here -- we will
 291                          * call the restock method and if it still needs
 292                          * more buffers it will schedule replenish */
 293                         return;
 294                 }
 295
 296                 spin_lock_irqsave(&rxq->lock, flags);
 297
 298                 if (list_empty(&rxq->rx_used)) {
 299                         spin_unlock_irqrestore(&rxq->lock, flags);
 300                         __free_pages(page, hw_params(trans).rx_page_order);
 301                         return;
 302                 }
 303                 element = rxq->rx_used.next;
 304                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 305                 list_del(element);
 306
 307                 spin_unlock_irqrestore(&rxq->lock, flags);
 308
 309                 BUG_ON(rxb->page);
 310                 rxb->page = page;
 311                 /* Get physical address of the RB */
 312                 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
 313                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 314                                 DMA_FROM_DEVICE);
 315                 /* dma address must be no more than 36 bits */
 316                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 317                 /* and also 256 byte aligned! */
 318                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 319
 320                 spin_lock_irqsave(&rxq->lock, flags);
 321
 322                 list_add_tail(&rxb->list, &rxq->rx_free);
 323                 rxq->free_count++;
 324
 325                 spin_unlock_irqrestore(&rxq->lock, flags);
 326         }
 327 }
 328
 329 void iwlagn_rx_replenish(struct iwl_trans *trans)
 330 {
 331         unsigned long flags;
 332
 333         iwlagn_rx_allocate(trans, GFP_KERNEL);
 334
 335         spin_lock_irqsave(&trans->shrd->lock, flags);
 336         iwlagn_rx_queue_restock(trans);
 337         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 338 }
 339
 340 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 341 {
 342         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 343
 344         iwlagn_rx_queue_restock(trans);
 345 }
 346
 347 void iwl_bg_rx_replenish(struct work_struct *data)
 348 {
 349         struct iwl_trans_pcie *trans_pcie =
 350             container_of(data, struct iwl_trans_pcie, rx_replenish);
 351         struct iwl_trans *trans = trans_pcie->trans;
 352
 353         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 354                 return;
 355
 356         mutex_lock(&trans->shrd->mutex);
 357         iwlagn_rx_replenish(trans);
 358         mutex_unlock(&trans->shrd->mutex);
 359 }
 360
 361 /**
 362  * iwl_rx_handle - Main entry function for receiving responses from uCode
 363  *
 364  * Uses the priv->rx_handlers callback function array to invoke
 365  * the appropriate handlers, including command responses,
 366  * frame-received notifications, and other notifications.
 367  */
 368 static void iwl_rx_handle(struct iwl_trans *trans)
 369 {
 370         struct iwl_rx_mem_buffer *rxb;
 371         struct iwl_rx_packet *pkt;
 372         struct iwl_trans_pcie *trans_pcie =
 373                 IWL_TRANS_GET_PCIE_TRANS(trans);
 374         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 375         u32 r, i;
 376         int reclaim;
 377         unsigned long flags;
 378         u8 fill_rx = 0;
 379         u32 count = 8;
 380         int total_empty;
 381
 382         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 383          * buffer that the driver may process (last buffer filled by ucode). */
 384         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 385         i = rxq->read;
 386
 387         /* Rx interrupt, but nothing sent from uCode */
 388         if (i == r)
 389                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 390
 391         /* calculate total frames need to be restock after handling RX */
 392         total_empty = r - rxq->write_actual;
 393         if (total_empty < 0)
 394                 total_empty += RX_QUEUE_SIZE;
 395
 396         if (total_empty > (RX_QUEUE_SIZE / 2))
 397                 fill_rx = 1;
 398
 399         while (i != r) {
 400                 int len;
 401
 402                 rxb = rxq->queue[i];
 403
 404                 /* If an RXB doesn't have a Rx queue slot associated with it,
 405                  * then a bug has been introduced in the queue refilling
 406                  * routines -- catch it here */
 407                 if (WARN_ON(rxb == NULL)) {
 408                         i = (i + 1) & RX_QUEUE_MASK;
 409                         continue;
 410                 }
 411
 412                 rxq->queue[i] = NULL;
 413
 414                 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
 415                                PAGE_SIZE << hw_params(trans).rx_page_order,
 416                                DMA_FROM_DEVICE);
 417                 pkt = rxb_addr(rxb);
 418
 419                 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
 420                         i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 421
 422                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 423                 len += sizeof(u32); /* account for status word */
 424                 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
 425
 426                 /* Reclaim a command buffer only if this packet is a response
 427                  *   to a (driver-originated) command.
 428                  * If the packet (e.g. Rx frame) originated from uCode,
 429                  *   there is no command buffer to reclaim.
 430                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 431                  *   but apparently a few don't get set; catch them here. */
 432                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 433                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 434                         (pkt->hdr.cmd != REPLY_RX) &&
 435                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 436                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 437                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 438                         (pkt->hdr.cmd != REPLY_TX);
 439
 440                 iwl_rx_dispatch(priv(trans), rxb);
 441
 442                 /*
 443                  * XXX: After here, we should always check rxb->page
 444                  * against NULL before touching it or its virtual
 445                  * memory (pkt). Because some rx_handler might have
 446                  * already taken or freed the pages.
 447                  */
 448
 449                 if (reclaim) {
 450                         /* Invoke any callbacks, transfer the buffer to caller,
 451                          * and fire off the (possibly) blocking
 452                          * iwl_trans_send_cmd()
 453                          * as we reclaim the driver command queue */
 454                         if (rxb->page)
 455                                 iwl_tx_cmd_complete(trans, rxb);
 456                         else
 457                                 IWL_WARN(trans, "Claim null rxb?\n");
 458                 }
 459
 460                 /* Reuse the page if possible. For notification packets and
 461                  * SKBs that fail to Rx correctly, add them back into the
 462                  * rx_free list for reuse later. */
 463                 spin_lock_irqsave(&rxq->lock, flags);
 464                 if (rxb->page != NULL) {
 465                         rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
 466                                 0, PAGE_SIZE <<
 467                                     hw_params(trans).rx_page_order,
 468                                 DMA_FROM_DEVICE);
 469                         list_add_tail(&rxb->list, &rxq->rx_free);
 470                         rxq->free_count++;
 471                 } else
 472                         list_add_tail(&rxb->list, &rxq->rx_used);
 473
 474                 spin_unlock_irqrestore(&rxq->lock, flags);
 475
 476                 i = (i + 1) & RX_QUEUE_MASK;
 477                 /* If there are a lot of unused frames,
 478                  * restock the Rx queue so ucode wont assert. */
 479                 if (fill_rx) {
 480                         count++;
 481                         if (count >= 8) {
 482                                 rxq->read = i;
 483                                 iwlagn_rx_replenish_now(trans);
 484                                 count = 0;
 485                         }
 486                 }
 487         }
 488
 489         /* Backtrack one entry */
 490         rxq->read = i;
 491         if (fill_rx)
 492                 iwlagn_rx_replenish_now(trans);
 493         else
 494                 iwlagn_rx_queue_restock(trans);
 495 }
 496
 497 static const char * const desc_lookup_text[] = {
 498         "OK",
 499         "FAIL",
 500         "BAD_PARAM",
 501         "BAD_CHECKSUM",
 502         "NMI_INTERRUPT_WDG",
 503         "SYSASSERT",
 504         "FATAL_ERROR",
 505         "BAD_COMMAND",
 506         "HW_ERROR_TUNE_LOCK",
 507         "HW_ERROR_TEMPERATURE",
 508         "ILLEGAL_CHAN_FREQ",
 509         "VCC_NOT_STABLE",
 510         "FH_ERROR",
 511         "NMI_INTERRUPT_HOST",
 512         "NMI_INTERRUPT_ACTION_PT",
 513         "NMI_INTERRUPT_UNKNOWN",
 514         "UCODE_VERSION_MISMATCH",
 515         "HW_ERROR_ABS_LOCK",
 516         "HW_ERROR_CAL_LOCK_FAIL",
 517         "NMI_INTERRUPT_INST_ACTION_PT",
 518         "NMI_INTERRUPT_DATA_ACTION_PT",
 519         "NMI_TRM_HW_ER",
 520         "NMI_INTERRUPT_TRM",
 521         "NMI_INTERRUPT_BREAK_POINT",
 522         "DEBUG_0",
 523         "DEBUG_1",
 524         "DEBUG_2",
 525         "DEBUG_3",
 526 };
 527
 528 static struct { char *name; u8 num; } advanced_lookup[] = {
 529         { "NMI_INTERRUPT_WDG", 0x34 },
 530         { "SYSASSERT", 0x35 },
 531         { "UCODE_VERSION_MISMATCH", 0x37 },
 532         { "BAD_COMMAND", 0x38 },
 533         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
 534         { "FATAL_ERROR", 0x3D },
 535         { "NMI_TRM_HW_ERR", 0x46 },
 536         { "NMI_INTERRUPT_TRM", 0x4C },
 537         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
 538         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
 539         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
 540         { "NMI_INTERRUPT_HOST", 0x66 },
 541         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
 542         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
 543         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
 544         { "ADVANCED_SYSASSERT", 0 },
 545 };
 546
 547 static const char *desc_lookup(u32 num)
 548 {
 549         int i;
 550         int max = ARRAY_SIZE(desc_lookup_text);
 551
 552         if (num < max)
 553                 return desc_lookup_text[num];
 554
 555         max = ARRAY_SIZE(advanced_lookup) - 1;
 556         for (i = 0; i < max; i++) {
 557                 if (advanced_lookup[i].num == num)
 558                         break;
 559         }
 560         return advanced_lookup[i].name;
 561 }
 562
 563 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 564 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 565
 566 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
 567 {
 568         u32 base;
 569         struct iwl_error_event_table table;
 570         struct iwl_priv *priv = priv(trans);
 571         struct iwl_trans_pcie *trans_pcie =
 572                 IWL_TRANS_GET_PCIE_TRANS(trans);
 573
 574         base = priv->device_pointers.error_event_table;
 575         if (priv->ucode_type == IWL_UCODE_INIT) {
 576                 if (!base)
 577                         base = priv->init_errlog_ptr;
 578         } else {
 579                 if (!base)
 580                         base = priv->inst_errlog_ptr;
 581         }
 582
 583         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 584                 IWL_ERR(trans,
 585                         "Not valid error log pointer 0x%08X for %s uCode\n",
 586                         base,
 587                         (priv->ucode_type == IWL_UCODE_INIT)
 588                                         ? "Init" : "RT");
 589                 return;
 590         }
 591
 592         iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table));
 593
 594         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 595                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 596                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
 597                         trans->shrd->status, table.valid);
 598         }
 599
 600         trans_pcie->isr_stats.err_code = table.error_id;
 601
 602         trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
 603                                       table.data1, table.data2, table.line,
 604                                       table.blink1, table.blink2, table.ilink1,
 605                                       table.ilink2, table.bcon_time, table.gp1,
 606                                       table.gp2, table.gp3, table.ucode_ver,
 607                                       table.hw_ver, table.brd_ver);
 608         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
 609                 desc_lookup(table.error_id));
 610         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
 611         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
 612         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
 613         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
 614         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
 615         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
 616         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
 617         IWL_ERR(trans, "0x%08X | line\n", table.line);
 618         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
 619         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
 620         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
 621         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
 622         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
 623         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
 624         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
 625         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
 626         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
 627         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
 628 }
 629
 630 /**
 631  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 632  */
 633 static void iwl_irq_handle_error(struct iwl_trans *trans)
 634 {
 635         struct iwl_priv *priv = priv(trans);
 636         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 637         if (priv->cfg->internal_wimax_coex &&
 638             (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
 639                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 640              (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
 641                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 642                 /*
 643                  * Keep the restart process from trying to send host
 644                  * commands by clearing the ready bit.
 645                  */
 646                 clear_bit(STATUS_READY, &trans->shrd->status);
 647                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 648                 wake_up_interruptible(&priv->shrd->wait_command_queue);
 649                 IWL_ERR(trans, "RF is used by WiMAX\n");
 650                 return;
 651         }
 652
 653         IWL_ERR(trans, "Loaded firmware version: %s\n",
 654                 priv->hw->wiphy->fw_version);
 655
 656         iwl_dump_nic_error_log(trans);
 657         iwl_dump_csr(trans);
 658         iwl_dump_fh(trans, NULL, false);
 659         iwl_dump_nic_event_log(trans, false, NULL, false);
 660 #ifdef CONFIG_IWLWIFI_DEBUG
 661         if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
 662                 iwl_print_rx_config_cmd(priv(trans), IWL_RXON_CTX_BSS);
 663 #endif
 664
 665         iwlagn_fw_error(priv, false);
 666 }
 667
 668 #define EVENT_START_OFFSET  (4 * sizeof(u32))
 669
 670 /**
 671  * iwl_print_event_log - Dump error event log to syslog
 672  *
 673  */
 674 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
 675                                u32 num_events, u32 mode,
 676                                int pos, char **buf, size_t bufsz)
 677 {
 678         u32 i;
 679         u32 base;       /* SRAM byte address of event log header */
 680         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
 681         u32 ptr;        /* SRAM byte address of log data */
 682         u32 ev, time, data; /* event log data */
 683         unsigned long reg_flags;
 684         struct iwl_priv *priv = priv(trans);
 685
 686         if (num_events == 0)
 687                 return pos;
 688
 689         base = priv->device_pointers.log_event_table;
 690         if (priv->ucode_type == IWL_UCODE_INIT) {
 691                 if (!base)
 692                         base = priv->init_evtlog_ptr;
 693         } else {
 694                 if (!base)
 695                         base = priv->inst_evtlog_ptr;
 696         }
 697
 698         if (mode == 0)
 699                 event_size = 2 * sizeof(u32);
 700         else
 701                 event_size = 3 * sizeof(u32);
 702
 703         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
 704
 705         /* Make sure device is powered up for SRAM reads */
 706         spin_lock_irqsave(&bus(trans)->reg_lock, reg_flags);
 707         iwl_grab_nic_access(bus(trans));
 708
 709         /* Set starting address; reads will auto-increment */
 710         iwl_write32(bus(trans), HBUS_TARG_MEM_RADDR, ptr);
 711         rmb();
 712
 713         /* "time" is actually "data" for mode 0 (no timestamp).
 714         * place event id # at far right for easier visual parsing. */
 715         for (i = 0; i < num_events; i++) {
 716                 ev = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 717                 time = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 718                 if (mode == 0) {
 719                         /* data, ev */
 720                         if (bufsz) {
 721                                 pos += scnprintf(*buf + pos, bufsz - pos,
 722                                                 "EVT_LOG:0x%08x:%04u\n",
 723                                                 time, ev);
 724                         } else {
 725                                 trace_iwlwifi_dev_ucode_event(priv, 0,
 726                                         time, ev);
 727                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
 728                                         time, ev);
 729                         }
 730                 } else {
 731                         data = iwl_read32(bus(trans), HBUS_TARG_MEM_RDAT);
 732                         if (bufsz) {
 733                                 pos += scnprintf(*buf + pos, bufsz - pos,
 734                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
 735                                                  time, data, ev);
 736                         } else {
 737                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
 738                                         time, data, ev);
 739                                 trace_iwlwifi_dev_ucode_event(priv, time,
 740                                         data, ev);
 741                         }
 742                 }
 743         }
 744
 745         /* Allow device to power down */
 746         iwl_release_nic_access(bus(trans));
 747         spin_unlock_irqrestore(&bus(trans)->reg_lock, reg_flags);
 748         return pos;
 749 }
 750
 751 /**
 752  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
 753  */
 754 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
 755                                     u32 num_wraps, u32 next_entry,
 756                                     u32 size, u32 mode,
 757                                     int pos, char **buf, size_t bufsz)
 758 {
 759         /*
 760          * display the newest DEFAULT_LOG_ENTRIES entries
 761          * i.e the entries just before the next ont that uCode would fill.
 762          */
 763         if (num_wraps) {
 764                 if (next_entry < size) {
 765                         pos = iwl_print_event_log(trans,
 766                                                 capacity - (size - next_entry),
 767                                                 size - next_entry, mode,
 768                                                 pos, buf, bufsz);
 769                         pos = iwl_print_event_log(trans, 0,
 770                                                   next_entry, mode,
 771                                                   pos, buf, bufsz);
 772                 } else
 773                         pos = iwl_print_event_log(trans, next_entry - size,
 774                                                   size, mode, pos, buf, bufsz);
 775         } else {
 776                 if (next_entry < size) {
 777                         pos = iwl_print_event_log(trans, 0, next_entry,
 778                                                   mode, pos, buf, bufsz);
 779                 } else {
 780                         pos = iwl_print_event_log(trans, next_entry - size,
 781                                                   size, mode, pos, buf, bufsz);
 782                 }
 783         }
 784         return pos;
 785 }
 786
 787 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
 788
 789 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 790                             char **buf, bool display)
 791 {
 792         u32 base;       /* SRAM byte address of event log header */
 793         u32 capacity;   /* event log capacity in # entries */
 794         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 795         u32 num_wraps;  /* # times uCode wrapped to top of log */
 796         u32 next_entry; /* index of next entry to be written by uCode */
 797         u32 size;       /* # entries that we'll print */
 798         u32 logsize;
 799         int pos = 0;
 800         size_t bufsz = 0;
 801         struct iwl_priv *priv = priv(trans);
 802
 803         base = priv->device_pointers.log_event_table;
 804         if (priv->ucode_type == IWL_UCODE_INIT) {
 805                 logsize = priv->init_evtlog_size;
 806                 if (!base)
 807                         base = priv->init_evtlog_ptr;
 808         } else {
 809                 logsize = priv->inst_evtlog_size;
 810                 if (!base)
 811                         base = priv->inst_evtlog_ptr;
 812         }
 813
 814         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 815                 IWL_ERR(trans,
 816                         "Invalid event log pointer 0x%08X for %s uCode\n",
 817                         base,
 818                         (priv->ucode_type == IWL_UCODE_INIT)
 819                                         ? "Init" : "RT");
 820                 return -EINVAL;
 821         }
 822
 823         /* event log header */
 824         capacity = iwl_read_targ_mem(bus(trans), base);
 825         mode = iwl_read_targ_mem(bus(trans), base + (1 * sizeof(u32)));
 826         num_wraps = iwl_read_targ_mem(bus(trans), base + (2 * sizeof(u32)));
 827         next_entry = iwl_read_targ_mem(bus(trans), base + (3 * sizeof(u32)));
 828
 829         if (capacity > logsize) {
 830                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
 831                         "entries\n", capacity, logsize);
 832                 capacity = logsize;
 833         }
 834
 835         if (next_entry > logsize) {
 836                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
 837                         next_entry, logsize);
 838                 next_entry = logsize;
 839         }
 840
 841         size = num_wraps ? capacity : next_entry;
 842
 843         /* bail out if nothing in log */
 844         if (size == 0) {
 845                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
 846                 return pos;
 847         }
 848
 849 #ifdef CONFIG_IWLWIFI_DEBUG
 850         if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
 851                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 852                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 853 #else
 854         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 855                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 856 #endif
 857         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
 858                 size);
 859
 860 #ifdef CONFIG_IWLWIFI_DEBUG
 861         if (display) {
 862                 if (full_log)
 863                         bufsz = capacity * 48;
 864                 else
 865                         bufsz = size * 48;
 866                 *buf = kmalloc(bufsz, GFP_KERNEL);
 867                 if (!*buf)
 868                         return -ENOMEM;
 869         }
 870         if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
 871                 /*
 872                  * if uCode has wrapped back to top of log,
 873                  * start at the oldest entry,
 874                  * i.e the next one that uCode would fill.
 875                  */
 876                 if (num_wraps)
 877                         pos = iwl_print_event_log(trans, next_entry,
 878                                                 capacity - next_entry, mode,
 879                                                 pos, buf, bufsz);
 880                 /* (then/else) start at top of log */
 881                 pos = iwl_print_event_log(trans, 0,
 882                                           next_entry, mode, pos, buf, bufsz);
 883         } else
 884                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 885                                                 next_entry, size, mode,
 886                                                 pos, buf, bufsz);
 887 #else
 888         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 889                                         next_entry, size, mode,
 890                                         pos, buf, bufsz);
 891 #endif
 892         return pos;
 893 }
 894
 895 /* tasklet for iwlagn interrupt */
 896 void iwl_irq_tasklet(struct iwl_trans *trans)
 897 {
 898         u32 inta = 0;
 899         u32 handled = 0;
 900         unsigned long flags;
 901         u32 i;
 902 #ifdef CONFIG_IWLWIFI_DEBUG
 903         u32 inta_mask;
 904 #endif
 905
 906         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 907         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 908
 909
 910         spin_lock_irqsave(&trans->shrd->lock, flags);
 911
 912         /* Ack/clear/reset pending uCode interrupts.
 913          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 914          */
 915         /* There is a hardware bug in the interrupt mask function that some
 916          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 917          * they are disabled in the CSR_INT_MASK register. Furthermore the
 918          * ICT interrupt handling mechanism has another bug that might cause
 919          * these unmasked interrupts fail to be detected. We workaround the
 920          * hardware bugs here by ACKing all the possible interrupts so that
 921          * interrupt coalescing can still be achieved.
 922          */
 923         iwl_write32(bus(trans), CSR_INT,
 924                 trans_pcie->inta | ~trans_pcie->inta_mask);
 925
 926         inta = trans_pcie->inta;
 927
 928 #ifdef CONFIG_IWLWIFI_DEBUG
 929         if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
 930                 /* just for debug */
 931                 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
 932                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 933                                 inta, inta_mask);
 934         }
 935 #endif
 936
 937         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 938
 939         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 940         trans_pcie->inta = 0;
 941
 942         /* Now service all interrupt bits discovered above. */
 943         if (inta & CSR_INT_BIT_HW_ERR) {
 944                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 945
 946                 /* Tell the device to stop sending interrupts */
 947                 iwl_disable_interrupts(trans);
 948
 949                 isr_stats->hw++;
 950                 iwl_irq_handle_error(trans);
 951
 952                 handled |= CSR_INT_BIT_HW_ERR;
 953
 954                 return;
 955         }
 956
 957 #ifdef CONFIG_IWLWIFI_DEBUG
 958         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
 959                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 960                 if (inta & CSR_INT_BIT_SCD) {
 961                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 962                                       "the frame/frames.\n");
 963                         isr_stats->sch++;
 964                 }
 965
 966                 /* Alive notification via Rx interrupt will do the real work */
 967                 if (inta & CSR_INT_BIT_ALIVE) {
 968                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 969                         isr_stats->alive++;
 970                 }
 971         }
 972 #endif
 973         /* Safely ignore these bits for debug checks below */
 974         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 975
 976         /* HW RF KILL switch toggled */
 977         if (inta & CSR_INT_BIT_RF_KILL) {
 978                 int hw_rf_kill = 0;
 979                 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
 980                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 981                         hw_rf_kill = 1;
 982
 983                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 984                                 hw_rf_kill ? "disable radio" : "enable radio");
 985
 986                 isr_stats->rfkill++;
 987
 988                 /* driver only loads ucode once setting the interface up.
 989                  * the driver allows loading the ucode even if the radio
 990                  * is killed. Hence update the killswitch state here. The
 991                  * rfkill handler will care about restarting if needed.
 992                  */
 993                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
 994                         if (hw_rf_kill)
 995                                 set_bit(STATUS_RF_KILL_HW,
 996                                         &trans->shrd->status);
 997                         else
 998                                 clear_bit(STATUS_RF_KILL_HW,
 999                                           &trans->shrd->status);
1000                         iwl_set_hw_rfkill_state(priv(trans), hw_rf_kill);
1001                 }
1002
1003                 handled |= CSR_INT_BIT_RF_KILL;
1004         }
1005
1006         /* Chip got too hot and stopped itself */
1007         if (inta & CSR_INT_BIT_CT_KILL) {
1008                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1009                 isr_stats->ctkill++;
1010                 handled |= CSR_INT_BIT_CT_KILL;
1011         }
1012
1013         /* Error detected by uCode */
1014         if (inta & CSR_INT_BIT_SW_ERR) {
1015                 IWL_ERR(trans, "Microcode SW error detected. "
1016                         " Restarting 0x%X.\n", inta);
1017                 isr_stats->sw++;
1018                 iwl_irq_handle_error(trans);
1019                 handled |= CSR_INT_BIT_SW_ERR;
1020         }
1021
1022         /* uCode wakes up after power-down sleep */
1023         if (inta & CSR_INT_BIT_WAKEUP) {
1024                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1025                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1026                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1027                         iwl_txq_update_write_ptr(trans,
1028                                                  &trans_pcie->txq[i]);
1029
1030                 isr_stats->wakeup++;
1031
1032                 handled |= CSR_INT_BIT_WAKEUP;
1033         }
1034
1035         /* All uCode command responses, including Tx command responses,
1036          * Rx "responses" (frame-received notification), and other
1037          * notifications from uCode come through here*/
1038         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1039                         CSR_INT_BIT_RX_PERIODIC)) {
1040                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1041                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1042                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1043                         iwl_write32(bus(trans), CSR_FH_INT_STATUS,
1044                                         CSR_FH_INT_RX_MASK);
1045                 }
1046                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1047                         handled |= CSR_INT_BIT_RX_PERIODIC;
1048                         iwl_write32(bus(trans),
1049                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1050                 }
1051                 /* Sending RX interrupt require many steps to be done in the
1052                  * the device:
1053                  * 1- write interrupt to current index in ICT table.
1054                  * 2- dma RX frame.
1055                  * 3- update RX shared data to indicate last write index.
1056                  * 4- send interrupt.
1057                  * This could lead to RX race, driver could receive RX interrupt
1058                  * but the shared data changes does not reflect this;
1059                  * periodic interrupt will detect any dangling Rx activity.
1060                  */
1061
1062                 /* Disable periodic interrupt; we use it as just a one-shot. */
1063                 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1064                             CSR_INT_PERIODIC_DIS);
1065                 iwl_rx_handle(trans);
1066
1067                 /*
1068                  * Enable periodic interrupt in 8 msec only if we received
1069                  * real RX interrupt (instead of just periodic int), to catch
1070                  * any dangling Rx interrupt.  If it was just the periodic
1071                  * interrupt, there was no dangling Rx activity, and no need
1072                  * to extend the periodic interrupt; one-shot is enough.
1073                  */
1074                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1075                         iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1076                                     CSR_INT_PERIODIC_ENA);
1077
1078                 isr_stats->rx++;
1079         }
1080
1081         /* This "Tx" DMA channel is used only for loading uCode */
1082         if (inta & CSR_INT_BIT_FH_TX) {
1083                 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1084                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1085                 isr_stats->tx++;
1086                 handled |= CSR_INT_BIT_FH_TX;
1087                 /* Wake up uCode load routine, now that load is complete */
1088                 priv(trans)->ucode_write_complete = 1;
1089                 wake_up_interruptible(&trans->shrd->wait_command_queue);
1090         }
1091
1092         if (inta & ~handled) {
1093                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1094                 isr_stats->unhandled++;
1095         }
1096
1097         if (inta & ~(trans_pcie->inta_mask)) {
1098                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1099                          inta & ~trans_pcie->inta_mask);
1100         }
1101
1102         /* Re-enable all interrupts */
1103         /* only Re-enable if disabled by irq */
1104         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1105                 iwl_enable_interrupts(trans);
1106         /* Re-enable RF_KILL if it occurred */
1107         else if (handled & CSR_INT_BIT_RF_KILL)
1108                 iwl_enable_rfkill_int(priv(trans));
1109 }
1110
1111 /******************************************************************************
1112  *
1113  * ICT functions
1114  *
1115  ******************************************************************************/
1116 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1117
1118 /* Free dram table */
1119 void iwl_free_isr_ict(struct iwl_trans *trans)
1120 {
1121         struct iwl_trans_pcie *trans_pcie =
1122                 IWL_TRANS_GET_PCIE_TRANS(trans);
1123
1124         if (trans_pcie->ict_tbl_vir) {
1125                 dma_free_coherent(bus(trans)->dev,
1126                                   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1127                                   trans_pcie->ict_tbl_vir,
1128                                   trans_pcie->ict_tbl_dma);
1129                 trans_pcie->ict_tbl_vir = NULL;
1130                 memset(&trans_pcie->ict_tbl_dma, 0,
1131                         sizeof(trans_pcie->ict_tbl_dma));
1132                 memset(&trans_pcie->aligned_ict_tbl_dma, 0,
1133                         sizeof(trans_pcie->aligned_ict_tbl_dma));
1134         }
1135 }
1136
1137
1138 /* allocate dram shared table it is a PAGE_SIZE aligned
1139  * also reset all data related to ICT table interrupt.
1140  */
1141 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1142 {
1143         struct iwl_trans_pcie *trans_pcie =
1144                 IWL_TRANS_GET_PCIE_TRANS(trans);
1145
1146         /* allocate shrared data table */
1147         trans_pcie->ict_tbl_vir =
1148                 dma_alloc_coherent(bus(trans)->dev,
1149                                    (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1150                                    &trans_pcie->ict_tbl_dma, GFP_KERNEL);
1151         if (!trans_pcie->ict_tbl_vir)
1152                 return -ENOMEM;
1153
1154         /* align table to PAGE_SIZE boundary */
1155         trans_pcie->aligned_ict_tbl_dma =
1156                 ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
1157
1158         IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1159                            (unsigned long long)trans_pcie->ict_tbl_dma,
1160                            (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
1161                            (int)(trans_pcie->aligned_ict_tbl_dma -
1162                            trans_pcie->ict_tbl_dma));
1163
1164         trans_pcie->ict_tbl =  trans_pcie->ict_tbl_vir +
1165                           (trans_pcie->aligned_ict_tbl_dma -
1166                           trans_pcie->ict_tbl_dma);
1167
1168         IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
1169                              trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
1170                         (int)(trans_pcie->aligned_ict_tbl_dma -
1171                             trans_pcie->ict_tbl_dma));
1172
1173         /* reset table and index to all 0 */
1174         memset(trans_pcie->ict_tbl_vir, 0,
1175                 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1176         trans_pcie->ict_index = 0;
1177
1178         /* add periodic RX interrupt */
1179         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1180         return 0;
1181 }
1182
1183 /* Device is going up inform it about using ICT interrupt table,
1184  * also we need to tell the driver to start using ICT interrupt.
1185  */
1186 int iwl_reset_ict(struct iwl_trans *trans)
1187 {
1188         u32 val;
1189         unsigned long flags;
1190         struct iwl_trans_pcie *trans_pcie =
1191                 IWL_TRANS_GET_PCIE_TRANS(trans);
1192
1193         if (!trans_pcie->ict_tbl_vir)
1194                 return 0;
1195
1196         spin_lock_irqsave(&trans->shrd->lock, flags);
1197         iwl_disable_interrupts(trans);
1198
1199         memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
1200
1201         val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
1202
1203         val |= CSR_DRAM_INT_TBL_ENABLE;
1204         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1205
1206         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
1207                         "aligned dma address %Lx\n",
1208                         val,
1209                         (unsigned long long)trans_pcie->aligned_ict_tbl_dma);
1210
1211         iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
1212         trans_pcie->use_ict = true;
1213         trans_pcie->ict_index = 0;
1214         iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
1215         iwl_enable_interrupts(trans);
1216         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1217
1218         return 0;
1219 }
1220
1221 /* Device is going down disable ict interrupt usage */
1222 void iwl_disable_ict(struct iwl_trans *trans)
1223 {
1224         struct iwl_trans_pcie *trans_pcie =
1225                 IWL_TRANS_GET_PCIE_TRANS(trans);
1226
1227         unsigned long flags;
1228
1229         spin_lock_irqsave(&trans->shrd->lock, flags);
1230         trans_pcie->use_ict = false;
1231         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1232 }
1233
1234 static irqreturn_t iwl_isr(int irq, void *data)
1235 {
1236         struct iwl_trans *trans = data;
1237         struct iwl_trans_pcie *trans_pcie;
1238         u32 inta, inta_mask;
1239         unsigned long flags;
1240 #ifdef CONFIG_IWLWIFI_DEBUG
1241         u32 inta_fh;
1242 #endif
1243         if (!trans)
1244                 return IRQ_NONE;
1245
1246         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1247
1248         spin_lock_irqsave(&trans->shrd->lock, flags);
1249
1250         /* Disable (but don't clear!) interrupts here to avoid
1251          *    back-to-back ISRs and sporadic interrupts from our NIC.
1252          * If we have something to service, the tasklet will re-enable ints.
1253          * If we *don't* have something, we'll re-enable before leaving here. */
1254         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);  /* just for debug */
1255         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1256
1257         /* Discover which interrupts are active/pending */
1258         inta = iwl_read32(bus(trans), CSR_INT);
1259
1260         /* Ignore interrupt if there's nothing in NIC to service.
1261          * This may be due to IRQ shared with another device,
1262          * or due to sporadic interrupts thrown from our NIC. */
1263         if (!inta) {
1264                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1265                 goto none;
1266         }
1267
1268         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1269                 /* Hardware disappeared. It might have already raised
1270                  * an interrupt */
1271                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1272                 goto unplugged;
1273         }
1274
1275 #ifdef CONFIG_IWLWIFI_DEBUG
1276         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1277                 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS);
1278                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1279                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1280         }
1281 #endif
1282
1283         trans_pcie->inta |= inta;
1284         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1285         if (likely(inta))
1286                 tasklet_schedule(&trans_pcie->irq_tasklet);
1287         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1288                         !trans_pcie->inta)
1289                 iwl_enable_interrupts(trans);
1290
1291  unplugged:
1292         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1293         return IRQ_HANDLED;
1294
1295  none:
1296         /* re-enable interrupts here since we don't have anything to service. */
1297         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1298         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1299                 !trans_pcie->inta)
1300                 iwl_enable_interrupts(trans);
1301
1302         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1303         return IRQ_NONE;
1304 }
1305
1306 /* interrupt handler using ict table, with this interrupt driver will
1307  * stop using INTA register to get device's interrupt, reading this register
1308  * is expensive, device will write interrupts in ICT dram table, increment
1309  * index then will fire interrupt to driver, driver will OR all ICT table
1310  * entries from current index up to table entry with 0 value. the result is
1311  * the interrupt we need to service, driver will set the entries back to 0 and
1312  * set index.
1313  */
1314 irqreturn_t iwl_isr_ict(int irq, void *data)
1315 {
1316         struct iwl_trans *trans = data;
1317         struct iwl_trans_pcie *trans_pcie;
1318         u32 inta, inta_mask;
1319         u32 val = 0;
1320         unsigned long flags;
1321
1322         if (!trans)
1323                 return IRQ_NONE;
1324
1325         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1326
1327         /* dram interrupt table not set yet,
1328          * use legacy interrupt.
1329          */
1330         if (!trans_pcie->use_ict)
1331                 return iwl_isr(irq, data);
1332
1333         spin_lock_irqsave(&trans->shrd->lock, flags);
1334
1335         /* Disable (but don't clear!) interrupts here to avoid
1336          * back-to-back ISRs and sporadic interrupts from our NIC.
1337          * If we have something to service, the tasklet will re-enable ints.
1338          * If we *don't* have something, we'll re-enable before leaving here.
1339          */
1340         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);  /* just for debug */
1341         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1342
1343
1344         /* Ignore interrupt if there's nothing in NIC to service.
1345          * This may be due to IRQ shared with another device,
1346          * or due to sporadic interrupts thrown from our NIC. */
1347         if (!trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1348                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1349                 goto none;
1350         }
1351
1352         /* read all entries that not 0 start with ict_index */
1353         while (trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1354
1355                 val |= le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1356                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1357                                 trans_pcie->ict_index,
1358                                 le32_to_cpu(
1359                                   trans_pcie->ict_tbl[trans_pcie->ict_index]));
1360                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1361                 trans_pcie->ict_index =
1362                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1363
1364         }
1365
1366         /* We should not get this value, just ignore it. */
1367         if (val == 0xffffffff)
1368                 val = 0;
1369
1370         /*
1371          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1372          * (bit 15 before shifting it to 31) to clear when using interrupt
1373          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1374          * so we use them to decide on the real state of the Rx bit.
1375          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1376          */
1377         if (val & 0xC0000)
1378                 val |= 0x8000;
1379
1380         inta = (0xff & val) | ((0xff00 & val) << 16);
1381         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1382                         inta, inta_mask, val);
1383
1384         inta &= trans_pcie->inta_mask;
1385         trans_pcie->inta |= inta;
1386
1387         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1388         if (likely(inta))
1389                 tasklet_schedule(&trans_pcie->irq_tasklet);
1390         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1391                         !trans_pcie->inta) {
1392                 /* Allow interrupt if was disabled by this handler and
1393                  * no tasklet was schedules, We should not enable interrupt,
1394                  * tasklet will enable it.
1395                  */
1396                 iwl_enable_interrupts(trans);
1397         }
1398
1399         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1400         return IRQ_HANDLED;
1401
1402  none:
1403         /* re-enable interrupts here since we don't have anything to service.
1404          * only Re-enable if disabled by irq.
1405          */
1406         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1407                 !trans_pcie->inta)
1408                 iwl_enable_interrupts(trans);
1409
1410         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1411         return IRQ_NONE;
1412 }