drivers/net/wireless/rtl818x/rtl8180/dev.c

   1
   2 /*
   3  * Linux device driver for RTL8180 / RTL8185
   4  *
   5  * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
   6  * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
   7  *
   8  * Based on the r8180 driver, which is:
   9  * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
  10  *
  11  * Thanks to Realtek for their support!
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/interrupt.h>
  19 #include <linux/pci.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/eeprom_93cx6.h>
  24 #include <linux/module.h>
  25 #include <net/mac80211.h>
  26
  27 #include "rtl8180.h"
  28 #include "rtl8225.h"
  29 #include "sa2400.h"
  30 #include "max2820.h"
  31 #include "grf5101.h"
  32
  33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  34 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
  35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
  36 MODULE_LICENSE("GPL");
  37
  38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
  39         /* rtl8185 */
  40         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
  41         { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
  42         { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
  43
  44         /* rtl8180 */
  45         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
  46         { PCI_DEVICE(0x1799, 0x6001) },
  47         { PCI_DEVICE(0x1799, 0x6020) },
  48         { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
  49         { PCI_DEVICE(0x1186, 0x3301) },
  50         { PCI_DEVICE(0x1432, 0x7106) },
  51         { }
  52 };
  53
  54 MODULE_DEVICE_TABLE(pci, rtl8180_table);
  55
  56 static const struct ieee80211_rate rtl818x_rates[] = {
  57         { .bitrate = 10, .hw_value = 0, },
  58         { .bitrate = 20, .hw_value = 1, },
  59         { .bitrate = 55, .hw_value = 2, },
  60         { .bitrate = 110, .hw_value = 3, },
  61         { .bitrate = 60, .hw_value = 4, },
  62         { .bitrate = 90, .hw_value = 5, },
  63         { .bitrate = 120, .hw_value = 6, },
  64         { .bitrate = 180, .hw_value = 7, },
  65         { .bitrate = 240, .hw_value = 8, },
  66         { .bitrate = 360, .hw_value = 9, },
  67         { .bitrate = 480, .hw_value = 10, },
  68         { .bitrate = 540, .hw_value = 11, },
  69 };
  70
  71 static const struct ieee80211_channel rtl818x_channels[] = {
  72         { .center_freq = 2412 },
  73         { .center_freq = 2417 },
  74         { .center_freq = 2422 },
  75         { .center_freq = 2427 },
  76         { .center_freq = 2432 },
  77         { .center_freq = 2437 },
  78         { .center_freq = 2442 },
  79         { .center_freq = 2447 },
  80         { .center_freq = 2452 },
  81         { .center_freq = 2457 },
  82         { .center_freq = 2462 },
  83         { .center_freq = 2467 },
  84         { .center_freq = 2472 },
  85         { .center_freq = 2484 },
  86 };
  87
  88
  89 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
  90 {
  91         struct rtl8180_priv *priv = dev->priv;
  92         int i = 10;
  93         u32 buf;
  94
  95         buf = (data << 8) | addr;
  96
  97         rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
  98         while (i--) {
  99                 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
 100                 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
 101                         return;
 102         }
 103 }
 104
 105 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
 106 {
 107         struct rtl8180_priv *priv = dev->priv;
 108         unsigned int count = 32;
 109         u8 signal, agc, sq;
 110         dma_addr_t mapping;
 111
 112         while (count--) {
 113                 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
 114                 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
 115                 u32 flags = le32_to_cpu(entry->flags);
 116
 117                 if (flags & RTL818X_RX_DESC_FLAG_OWN)
 118                         return;
 119
 120                 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
 121                                       RTL818X_RX_DESC_FLAG_FOF |
 122                                       RTL818X_RX_DESC_FLAG_RX_ERR)))
 123                         goto done;
 124                 else {
 125                         u32 flags2 = le32_to_cpu(entry->flags2);
 126                         struct ieee80211_rx_status rx_status = {0};
 127                         struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
 128
 129                         if (unlikely(!new_skb))
 130                                 goto done;
 131
 132                         mapping = pci_map_single(priv->pdev,
 133                                                skb_tail_pointer(new_skb),
 134                                                MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 135
 136                         if (pci_dma_mapping_error(priv->pdev, mapping)) {
 137                                 kfree_skb(new_skb);
 138                                 dev_err(&priv->pdev->dev, "RX DMA map error\n");
 139
 140                                 goto done;
 141                         }
 142
 143                         pci_unmap_single(priv->pdev,
 144                                          *((dma_addr_t *)skb->cb),
 145                                          MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 146                         skb_put(skb, flags & 0xFFF);
 147
 148                         rx_status.antenna = (flags2 >> 15) & 1;
 149                         rx_status.rate_idx = (flags >> 20) & 0xF;
 150                         agc = (flags2 >> 17) & 0x7F;
 151
 152                         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
 153                                 if (rx_status.rate_idx > 3)
 154                                         signal = 90 - clamp_t(u8, agc, 25, 90);
 155                                 else
 156                                         signal = 95 - clamp_t(u8, agc, 30, 95);
 157                         } else {
 158                                 sq = flags2 & 0xff;
 159                                 signal = priv->rf->calc_rssi(agc, sq);
 160                         }
 161                         rx_status.signal = signal;
 162                         rx_status.freq = dev->conf.chandef.chan->center_freq;
 163                         rx_status.band = dev->conf.chandef.chan->band;
 164                         rx_status.mactime = le64_to_cpu(entry->tsft);
 165                         rx_status.flag |= RX_FLAG_MACTIME_START;
 166                         if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
 167                                 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
 168
 169                         memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
 170                         ieee80211_rx_irqsafe(dev, skb);
 171
 172                         skb = new_skb;
 173                         priv->rx_buf[priv->rx_idx] = skb;
 174                         *((dma_addr_t *) skb->cb) = mapping;
 175                 }
 176
 177         done:
 178                 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
 179                 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
 180                                            MAX_RX_SIZE);
 181                 if (priv->rx_idx == 31)
 182                         entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
 183                 priv->rx_idx = (priv->rx_idx + 1) % 32;
 184         }
 185 }
 186
 187 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
 188 {
 189         struct rtl8180_priv *priv = dev->priv;
 190         struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
 191
 192         while (skb_queue_len(&ring->queue)) {
 193                 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
 194                 struct sk_buff *skb;
 195                 struct ieee80211_tx_info *info;
 196                 u32 flags = le32_to_cpu(entry->flags);
 197
 198                 if (flags & RTL818X_TX_DESC_FLAG_OWN)
 199                         return;
 200
 201                 ring->idx = (ring->idx + 1) % ring->entries;
 202                 skb = __skb_dequeue(&ring->queue);
 203                 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
 204                                  skb->len, PCI_DMA_TODEVICE);
 205
 206                 info = IEEE80211_SKB_CB(skb);
 207                 ieee80211_tx_info_clear_status(info);
 208
 209                 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
 210                     (flags & RTL818X_TX_DESC_FLAG_TX_OK))
 211                         info->flags |= IEEE80211_TX_STAT_ACK;
 212
 213                 info->status.rates[0].count = (flags & 0xFF) + 1;
 214                 info->status.rates[1].idx = -1;
 215
 216                 ieee80211_tx_status_irqsafe(dev, skb);
 217                 if (ring->entries - skb_queue_len(&ring->queue) == 2)
 218                         ieee80211_wake_queue(dev, prio);
 219         }
 220 }
 221
 222 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
 223 {
 224         struct ieee80211_hw *dev = dev_id;
 225         struct rtl8180_priv *priv = dev->priv;
 226         u16 reg;
 227
 228         spin_lock(&priv->lock);
 229         reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
 230         if (unlikely(reg == 0xFFFF)) {
 231                 spin_unlock(&priv->lock);
 232                 return IRQ_HANDLED;
 233         }
 234
 235         rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
 236
 237         if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
 238                 rtl8180_handle_tx(dev, 3);
 239
 240         if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
 241                 rtl8180_handle_tx(dev, 2);
 242
 243         if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
 244                 rtl8180_handle_tx(dev, 1);
 245
 246         if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
 247                 rtl8180_handle_tx(dev, 0);
 248
 249         if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
 250                 rtl8180_handle_rx(dev);
 251
 252         spin_unlock(&priv->lock);
 253
 254         return IRQ_HANDLED;
 255 }
 256
 257 static void rtl8180_tx(struct ieee80211_hw *dev,
 258                        struct ieee80211_tx_control *control,
 259                        struct sk_buff *skb)
 260 {
 261         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 262         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
 263         struct rtl8180_priv *priv = dev->priv;
 264         struct rtl8180_tx_ring *ring;
 265         struct rtl8180_tx_desc *entry;
 266         unsigned long flags;
 267         unsigned int idx, prio;
 268         dma_addr_t mapping;
 269         u32 tx_flags;
 270         u8 rc_flags;
 271         u16 plcp_len = 0;
 272         __le16 rts_duration = 0;
 273
 274         prio = skb_get_queue_mapping(skb);
 275         ring = &priv->tx_ring[prio];
 276
 277         mapping = pci_map_single(priv->pdev, skb->data,
 278                                  skb->len, PCI_DMA_TODEVICE);
 279
 280         if (pci_dma_mapping_error(priv->pdev, mapping)) {
 281                 kfree_skb(skb);
 282                 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
 283                 return;
 284
 285         }
 286
 287         tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
 288                    RTL818X_TX_DESC_FLAG_LS |
 289                    (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
 290                    skb->len;
 291
 292         if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
 293                 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
 294                             RTL818X_TX_DESC_FLAG_NO_ENC;
 295
 296         rc_flags = info->control.rates[0].flags;
 297         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
 298                 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
 299                 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
 300         } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
 301                 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
 302                 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
 303         }
 304
 305         if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
 306                 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
 307                                                       info);
 308
 309         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
 310                 unsigned int remainder;
 311
 312                 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
 313                                 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
 314                 remainder = (16 * (skb->len + 4)) %
 315                             ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
 316                 if (remainder <= 6)
 317                         plcp_len |= 1 << 15;
 318         }
 319
 320         spin_lock_irqsave(&priv->lock, flags);
 321
 322         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
 323                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
 324                         priv->seqno += 0x10;
 325                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
 326                 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
 327         }
 328
 329         idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
 330         entry = &ring->desc[idx];
 331
 332         entry->rts_duration = rts_duration;
 333         entry->plcp_len = cpu_to_le16(plcp_len);
 334         entry->tx_buf = cpu_to_le32(mapping);
 335         entry->frame_len = cpu_to_le32(skb->len);
 336         entry->flags2 = info->control.rates[1].idx >= 0 ?
 337                 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
 338         entry->retry_limit = info->control.rates[0].count;
 339
 340         /* We must be sure that tx_flags is written last because the HW
 341          * looks at it to check if the rest of data is valid or not
 342          */
 343         wmb();
 344         entry->flags = cpu_to_le32(tx_flags);
 345         /* We must be sure this has been written before followings HW
 346          * register write, because this write will made the HW attempts
 347          * to DMA the just-written data
 348          */
 349         wmb();
 350
 351         __skb_queue_tail(&ring->queue, skb);
 352         if (ring->entries - skb_queue_len(&ring->queue) < 2)
 353                 ieee80211_stop_queue(dev, prio);
 354
 355         spin_unlock_irqrestore(&priv->lock, flags);
 356
 357         rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
 358 }
 359
 360 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
 361 {
 362         u8 reg;
 363
 364         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 365         reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 366         rtl818x_iowrite8(priv, &priv->map->CONFIG3,
 367                  reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
 368         rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
 369         rtl818x_iowrite8(priv, &priv->map->CONFIG3,
 370                  reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
 371         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 372 }
 373
 374 static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
 375                             u32 rates_mask)
 376 {
 377         struct rtl8180_priv *priv = dev->priv;
 378
 379         u8 max, min;
 380         u16 reg;
 381
 382         max = fls(rates_mask) - 1;
 383         min = ffs(rates_mask) - 1;
 384
 385         switch (priv->chip_family) {
 386
 387         case RTL818X_CHIP_FAMILY_RTL8180:
 388                 /* in 8180 this is NOT a BITMAP */
 389                 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
 390                 reg &= ~3;
 391                 reg |= max;
 392                 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
 393
 394                 break;
 395
 396         case RTL818X_CHIP_FAMILY_RTL8185:
 397                 /* in 8185 this is a BITMAP */
 398                 rtl818x_iowrite16(priv, &priv->map->BRSR, rates_mask);
 399                 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (max << 4) | min);
 400                 break;
 401         }
 402 }
 403
 404 static int rtl8180_init_hw(struct ieee80211_hw *dev)
 405 {
 406         struct rtl8180_priv *priv = dev->priv;
 407         u16 reg;
 408
 409         rtl818x_iowrite8(priv, &priv->map->CMD, 0);
 410         rtl818x_ioread8(priv, &priv->map->CMD);
 411         msleep(10);
 412
 413         /* reset */
 414         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
 415         rtl818x_ioread8(priv, &priv->map->CMD);
 416
 417         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 418         reg &= (1 << 1);
 419         reg |= RTL818X_CMD_RESET;
 420         rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
 421         rtl818x_ioread8(priv, &priv->map->CMD);
 422         msleep(200);
 423
 424         /* check success of reset */
 425         if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
 426                 wiphy_err(dev->wiphy, "reset timeout!\n");
 427                 return -ETIMEDOUT;
 428         }
 429
 430         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
 431         rtl818x_ioread8(priv, &priv->map->CMD);
 432         msleep(200);
 433
 434         if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
 435                 /* For cardbus */
 436                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 437                 reg |= 1 << 1;
 438                 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
 439                 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
 440                 reg |= (1 << 15) | (1 << 14) | (1 << 4);
 441                 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
 442         }
 443
 444         rtl818x_iowrite8(priv, &priv->map->MSR, 0);
 445
 446         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
 447                 rtl8180_set_anaparam(priv, priv->anaparam);
 448
 449         rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
 450         rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
 451         rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
 452         rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
 453         rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
 454
 455         /* TODO: necessary? specs indicate not */
 456         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 457         reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
 458         rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
 459         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
 460                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
 461                 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
 462         }
 463         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 464
 465         /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
 466
 467         /* TODO: turn off hw wep on rtl8180 */
 468
 469         rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
 470
 471         if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
 472                 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
 473                 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
 474
 475                 /* TODO: set ClkRun enable? necessary? */
 476                 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
 477                 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
 478                 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 479                 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
 480                 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
 481                 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 482         } else {
 483                 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
 484
 485                 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
 486                 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
 487         }
 488
 489         priv->rf->init(dev);
 490
 491         /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
 492          * otherwise. bitmask 0x3 and 0x01f3 respectively.
 493          * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
 494          * this after rf init.
 495          * TODO: try to find out whether RF code really needs to do this..
 496          */
 497         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
 498                 rtl8180_conf_basic_rates(dev, 0x3);
 499         else
 500                 rtl8180_conf_basic_rates(dev, 0x1f3);
 501
 502         return 0;
 503 }
 504
 505 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
 506 {
 507         struct rtl8180_priv *priv = dev->priv;
 508         struct rtl8180_rx_desc *entry;
 509         int i;
 510
 511         priv->rx_ring = pci_alloc_consistent(priv->pdev,
 512                                              sizeof(*priv->rx_ring) * 32,
 513                                              &priv->rx_ring_dma);
 514
 515         if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
 516                 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
 517                 return -ENOMEM;
 518         }
 519
 520         memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
 521         priv->rx_idx = 0;
 522
 523         for (i = 0; i < 32; i++) {
 524                 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
 525                 dma_addr_t *mapping;
 526                 entry = &priv->rx_ring[i];
 527                 if (!skb) {
 528                         wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
 529                         return -ENOMEM;
 530                 }
 531                 priv->rx_buf[i] = skb;
 532                 mapping = (dma_addr_t *)skb->cb;
 533                 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
 534                                           MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 535
 536                 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
 537                         kfree_skb(skb);
 538                         wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
 539                         return -ENOMEM;
 540                 }
 541
 542                 entry->rx_buf = cpu_to_le32(*mapping);
 543                 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
 544                                            MAX_RX_SIZE);
 545         }
 546         entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
 547         return 0;
 548 }
 549
 550 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
 551 {
 552         struct rtl8180_priv *priv = dev->priv;
 553         int i;
 554
 555         for (i = 0; i < 32; i++) {
 556                 struct sk_buff *skb = priv->rx_buf[i];
 557                 if (!skb)
 558                         continue;
 559
 560                 pci_unmap_single(priv->pdev,
 561                                  *((dma_addr_t *)skb->cb),
 562                                  MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
 563                 kfree_skb(skb);
 564         }
 565
 566         pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
 567                             priv->rx_ring, priv->rx_ring_dma);
 568         priv->rx_ring = NULL;
 569 }
 570
 571 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
 572                                 unsigned int prio, unsigned int entries)
 573 {
 574         struct rtl8180_priv *priv = dev->priv;
 575         struct rtl8180_tx_desc *ring;
 576         dma_addr_t dma;
 577         int i;
 578
 579         ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
 580         if (!ring || (unsigned long)ring & 0xFF) {
 581                 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
 582                           prio);
 583                 return -ENOMEM;
 584         }
 585
 586         memset(ring, 0, sizeof(*ring)*entries);
 587         priv->tx_ring[prio].desc = ring;
 588         priv->tx_ring[prio].dma = dma;
 589         priv->tx_ring[prio].idx = 0;
 590         priv->tx_ring[prio].entries = entries;
 591         skb_queue_head_init(&priv->tx_ring[prio].queue);
 592
 593         for (i = 0; i < entries; i++)
 594                 ring[i].next_tx_desc =
 595                         cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
 596
 597         return 0;
 598 }
 599
 600 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
 601 {
 602         struct rtl8180_priv *priv = dev->priv;
 603         struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
 604
 605         while (skb_queue_len(&ring->queue)) {
 606                 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
 607                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
 608
 609                 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
 610                                  skb->len, PCI_DMA_TODEVICE);
 611                 kfree_skb(skb);
 612                 ring->idx = (ring->idx + 1) % ring->entries;
 613         }
 614
 615         pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
 616                             ring->desc, ring->dma);
 617         ring->desc = NULL;
 618 }
 619
 620 static int rtl8180_start(struct ieee80211_hw *dev)
 621 {
 622         struct rtl8180_priv *priv = dev->priv;
 623         int ret, i;
 624         u32 reg;
 625
 626         ret = rtl8180_init_rx_ring(dev);
 627         if (ret)
 628                 return ret;
 629
 630         for (i = 0; i < 4; i++)
 631                 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
 632                         goto err_free_rings;
 633
 634         ret = rtl8180_init_hw(dev);
 635         if (ret)
 636                 goto err_free_rings;
 637
 638         rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
 639         rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
 640         rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
 641         rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
 642         rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
 643
 644         ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
 645                           IRQF_SHARED, KBUILD_MODNAME, dev);
 646         if (ret) {
 647                 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
 648                 goto err_free_rings;
 649         }
 650
 651         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
 652
 653         rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
 654         rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
 655
 656         reg = RTL818X_RX_CONF_ONLYERLPKT |
 657               RTL818X_RX_CONF_RX_AUTORESETPHY |
 658               RTL818X_RX_CONF_MGMT |
 659               RTL818X_RX_CONF_DATA |
 660               (7 << 8 /* MAX RX DMA */) |
 661               RTL818X_RX_CONF_BROADCAST |
 662               RTL818X_RX_CONF_NICMAC;
 663
 664         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
 665                 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
 666         else {
 667                 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
 668                         ? RTL818X_RX_CONF_CSDM1 : 0;
 669                 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
 670                         ? RTL818X_RX_CONF_CSDM2 : 0;
 671         }
 672
 673         priv->rx_conf = reg;
 674         rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
 675
 676         if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
 677                 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
 678
 679                 /* CW is not on per-packet basis.
 680                  * in rtl8185 the CW_VALUE reg is used.
 681                  */
 682                 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
 683                 /* retry limit IS on per-packet basis.
 684                  * the short and long retry limit in TX_CONF
 685                  * reg are ignored
 686                  */
 687                 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
 688                 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
 689
 690                 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
 691                 /* TX antenna and TX gain are not on per-packet basis.
 692                  * TX Antenna is selected by ANTSEL reg (RX in BB regs).
 693                  * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
 694                  */
 695                 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
 696                 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
 697                 reg |=  RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
 698                 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
 699
 700                 /* disable early TX */
 701                 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
 702         }
 703
 704         reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
 705         reg |= (6 << 21 /* MAX TX DMA */) |
 706                RTL818X_TX_CONF_NO_ICV;
 707
 708
 709
 710         if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
 711                 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
 712         else
 713                 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
 714
 715         reg &= ~RTL818X_TX_CONF_DISCW;
 716
 717         /* different meaning, same value on both rtl8185 and rtl8180 */
 718         reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
 719
 720         rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
 721
 722         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 723         reg |= RTL818X_CMD_RX_ENABLE;
 724         reg |= RTL818X_CMD_TX_ENABLE;
 725         rtl818x_iowrite8(priv, &priv->map->CMD, reg);
 726
 727         return 0;
 728
 729  err_free_rings:
 730         rtl8180_free_rx_ring(dev);
 731         for (i = 0; i < 4; i++)
 732                 if (priv->tx_ring[i].desc)
 733                         rtl8180_free_tx_ring(dev, i);
 734
 735         return ret;
 736 }
 737
 738 static void rtl8180_stop(struct ieee80211_hw *dev)
 739 {
 740         struct rtl8180_priv *priv = dev->priv;
 741         u8 reg;
 742         int i;
 743
 744         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
 745
 746         reg = rtl818x_ioread8(priv, &priv->map->CMD);
 747         reg &= ~RTL818X_CMD_TX_ENABLE;
 748         reg &= ~RTL818X_CMD_RX_ENABLE;
 749         rtl818x_iowrite8(priv, &priv->map->CMD, reg);
 750
 751         priv->rf->stop(dev);
 752
 753         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 754         reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
 755         rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
 756         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 757
 758         free_irq(priv->pdev->irq, dev);
 759
 760         rtl8180_free_rx_ring(dev);
 761         for (i = 0; i < 4; i++)
 762                 rtl8180_free_tx_ring(dev, i);
 763 }
 764
 765 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
 766                            struct ieee80211_vif *vif)
 767 {
 768         struct rtl8180_priv *priv = dev->priv;
 769
 770         return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
 771                (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
 772 }
 773
 774 static void rtl8180_beacon_work(struct work_struct *work)
 775 {
 776         struct rtl8180_vif *vif_priv =
 777                 container_of(work, struct rtl8180_vif, beacon_work.work);
 778         struct ieee80211_vif *vif =
 779                 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
 780         struct ieee80211_hw *dev = vif_priv->dev;
 781         struct ieee80211_mgmt *mgmt;
 782         struct sk_buff *skb;
 783
 784         /* don't overflow the tx ring */
 785         if (ieee80211_queue_stopped(dev, 0))
 786                 goto resched;
 787
 788         /* grab a fresh beacon */
 789         skb = ieee80211_beacon_get(dev, vif);
 790         if (!skb)
 791                 goto resched;
 792
 793         /*
 794          * update beacon timestamp w/ TSF value
 795          * TODO: make hardware update beacon timestamp
 796          */
 797         mgmt = (struct ieee80211_mgmt *)skb->data;
 798         mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
 799
 800         /* TODO: use actual beacon queue */
 801         skb_set_queue_mapping(skb, 0);
 802
 803         rtl8180_tx(dev, NULL, skb);
 804
 805 resched:
 806         /*
 807          * schedule next beacon
 808          * TODO: use hardware support for beacon timing
 809          */
 810         schedule_delayed_work(&vif_priv->beacon_work,
 811                         usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
 812 }
 813
 814 static int rtl8180_add_interface(struct ieee80211_hw *dev,
 815                                  struct ieee80211_vif *vif)
 816 {
 817         struct rtl8180_priv *priv = dev->priv;
 818         struct rtl8180_vif *vif_priv;
 819
 820         /*
 821          * We only support one active interface at a time.
 822          */
 823         if (priv->vif)
 824                 return -EBUSY;
 825
 826         switch (vif->type) {
 827         case NL80211_IFTYPE_STATION:
 828         case NL80211_IFTYPE_ADHOC:
 829                 break;
 830         default:
 831                 return -EOPNOTSUPP;
 832         }
 833
 834         priv->vif = vif;
 835
 836         /* Initialize driver private area */
 837         vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
 838         vif_priv->dev = dev;
 839         INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
 840         vif_priv->enable_beacon = false;
 841
 842         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
 843         rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
 844                           le32_to_cpu(*(__le32 *)vif->addr));
 845         rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
 846                           le16_to_cpu(*(__le16 *)(vif->addr + 4)));
 847         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 848
 849         return 0;
 850 }
 851
 852 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
 853                                      struct ieee80211_vif *vif)
 854 {
 855         struct rtl8180_priv *priv = dev->priv;
 856         priv->vif = NULL;
 857 }
 858
 859 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
 860 {
 861         struct rtl8180_priv *priv = dev->priv;
 862         struct ieee80211_conf *conf = &dev->conf;
 863
 864         priv->rf->set_chan(dev, conf);
 865
 866         return 0;
 867 }
 868
 869 static int rtl8180_conf_tx(struct ieee80211_hw *dev,
 870                             struct ieee80211_vif *vif, u16 queue,
 871                             const struct ieee80211_tx_queue_params *params)
 872 {
 873         struct rtl8180_priv *priv = dev->priv;
 874         u8 cw_min, cw_max;
 875
 876         /* nothing to do ? */
 877         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
 878                 return 0;
 879
 880         cw_min = fls(params->cw_min);
 881         cw_max = fls(params->cw_max);
 882
 883         rtl818x_iowrite8(priv, &priv->map->CW_VAL, (cw_max << 4) | cw_min);
 884
 885         return 0;
 886 }
 887
 888 static void rtl8180_conf_erp(struct ieee80211_hw *dev,
 889                             struct ieee80211_bss_conf *info)
 890 {
 891         struct rtl8180_priv *priv = dev->priv;
 892         u8 sifs, difs;
 893         int eifs;
 894         u8 hw_eifs;
 895
 896         /* TODO: should we do something ? */
 897         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
 898                 return;
 899
 900         /* I _hope_ this means 10uS for the HW.
 901          * In reference code it is 0x22 for
 902          * both rtl8187L and rtl8187SE
 903          */
 904         sifs = 0x22;
 905
 906         if (info->use_short_slot)
 907                 priv->slot_time = 9;
 908         else
 909                 priv->slot_time = 20;
 910
 911         /* 10 is SIFS time in uS */
 912         difs = 10 + 2 * priv->slot_time;
 913         eifs = 10 + difs + priv->ack_time;
 914
 915         /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
 916         hw_eifs = DIV_ROUND_UP(eifs, 4);
 917
 918
 919         rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
 920         rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
 921         rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
 922
 923         /* from reference code. set ack timeout reg = eifs reg */
 924         rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
 925
 926         /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
 927          * the HW still wait for DIFS.
 928          * HW uses 4uS units for EIFS.
 929          */
 930         hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
 931
 932         rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
 933 }
 934
 935 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
 936                                      struct ieee80211_vif *vif,
 937                                      struct ieee80211_bss_conf *info,
 938                                      u32 changed)
 939 {
 940         struct rtl8180_priv *priv = dev->priv;
 941         struct rtl8180_vif *vif_priv;
 942         int i;
 943         u8 reg;
 944
 945         vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
 946
 947         if (changed & BSS_CHANGED_BSSID) {
 948                 for (i = 0; i < ETH_ALEN; i++)
 949                         rtl818x_iowrite8(priv, &priv->map->BSSID[i],
 950                                          info->bssid[i]);
 951
 952                 if (is_valid_ether_addr(info->bssid)) {
 953                         if (vif->type == NL80211_IFTYPE_ADHOC)
 954                                 reg = RTL818X_MSR_ADHOC;
 955                         else
 956                                 reg = RTL818X_MSR_INFRA;
 957                 } else
 958                         reg = RTL818X_MSR_NO_LINK;
 959                 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
 960         }
 961
 962         if (changed & BSS_CHANGED_BASIC_RATES)
 963                 rtl8180_conf_basic_rates(dev, info->basic_rates);
 964
 965         if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
 966
 967                 /* when preamble changes, acktime duration changes, and erp must
 968                  * be recalculated. ACK time is calculated at lowest rate.
 969                  * Since mac80211 include SIFS time we remove it (-10)
 970                  */
 971                 priv->ack_time =
 972                         le16_to_cpu(ieee80211_generic_frame_duration(dev,
 973                                         priv->vif,
 974                                         IEEE80211_BAND_2GHZ, 10,
 975                                         &priv->rates[0])) - 10;
 976
 977                 rtl8180_conf_erp(dev, info);
 978         }
 979
 980         if (changed & BSS_CHANGED_BEACON_ENABLED)
 981                 vif_priv->enable_beacon = info->enable_beacon;
 982
 983         if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
 984                 cancel_delayed_work_sync(&vif_priv->beacon_work);
 985                 if (vif_priv->enable_beacon)
 986                         schedule_work(&vif_priv->beacon_work.work);
 987         }
 988 }
 989
 990 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
 991                                      struct netdev_hw_addr_list *mc_list)
 992 {
 993         return netdev_hw_addr_list_count(mc_list);
 994 }
 995
 996 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
 997                                      unsigned int changed_flags,
 998                                      unsigned int *total_flags,
 999                                      u64 multicast)
1000 {
1001         struct rtl8180_priv *priv = dev->priv;
1002
1003         if (changed_flags & FIF_FCSFAIL)
1004                 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1005         if (changed_flags & FIF_CONTROL)
1006                 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1007         if (changed_flags & FIF_OTHER_BSS)
1008                 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1009         if (*total_flags & FIF_ALLMULTI || multicast > 0)
1010                 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1011         else
1012                 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1013
1014         *total_flags = 0;
1015
1016         if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1017                 *total_flags |= FIF_FCSFAIL;
1018         if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1019                 *total_flags |= FIF_CONTROL;
1020         if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1021                 *total_flags |= FIF_OTHER_BSS;
1022         if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1023                 *total_flags |= FIF_ALLMULTI;
1024
1025         rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1026 }
1027
1028 static const struct ieee80211_ops rtl8180_ops = {
1029         .tx                     = rtl8180_tx,
1030         .start                  = rtl8180_start,
1031         .stop                   = rtl8180_stop,
1032         .add_interface          = rtl8180_add_interface,
1033         .remove_interface       = rtl8180_remove_interface,
1034         .config                 = rtl8180_config,
1035         .bss_info_changed       = rtl8180_bss_info_changed,
1036         .conf_tx                = rtl8180_conf_tx,
1037         .prepare_multicast      = rtl8180_prepare_multicast,
1038         .configure_filter       = rtl8180_configure_filter,
1039         .get_tsf                = rtl8180_get_tsf,
1040 };
1041
1042 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1043 {
1044         struct rtl8180_priv *priv = eeprom->data;
1045         u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1046
1047         eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1048         eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1049         eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1050         eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1051 }
1052
1053 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1054 {
1055         struct rtl8180_priv *priv = eeprom->data;
1056         u8 reg = 2 << 6;
1057
1058         if (eeprom->reg_data_in)
1059                 reg |= RTL818X_EEPROM_CMD_WRITE;
1060         if (eeprom->reg_data_out)
1061                 reg |= RTL818X_EEPROM_CMD_READ;
1062         if (eeprom->reg_data_clock)
1063                 reg |= RTL818X_EEPROM_CMD_CK;
1064         if (eeprom->reg_chip_select)
1065                 reg |= RTL818X_EEPROM_CMD_CS;
1066
1067         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1068         rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1069         udelay(10);
1070 }
1071
1072 static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1073 {
1074         struct eeprom_93cx6 eeprom;
1075         int eeprom_cck_table_adr;
1076         u16 eeprom_val;
1077         int i;
1078
1079         eeprom.data = priv;
1080         eeprom.register_read = rtl8180_eeprom_register_read;
1081         eeprom.register_write = rtl8180_eeprom_register_write;
1082         if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1083                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1084         else
1085                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1086
1087         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1088                         RTL818X_EEPROM_CMD_PROGRAM);
1089         rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1090         udelay(10);
1091
1092         eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1093         eeprom_val &= 0xFF;
1094         priv->rf_type = eeprom_val;
1095
1096         eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1097         priv->csthreshold = eeprom_val >> 8;
1098
1099         eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1100
1101         eeprom_cck_table_adr = 0x10;
1102
1103         /* CCK TX power */
1104         for (i = 0; i < 14; i += 2) {
1105                 u16 txpwr;
1106                 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1107                                 &txpwr);
1108                 priv->channels[i].hw_value = txpwr & 0xFF;
1109                 priv->channels[i + 1].hw_value = txpwr >> 8;
1110         }
1111
1112         /* OFDM TX power */
1113         if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1114                 for (i = 0; i < 14; i += 2) {
1115                         u16 txpwr;
1116                         eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1117                         priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1118                         priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1119                 }
1120         }
1121
1122         if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1123                 __le32 anaparam;
1124                 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1125                 priv->anaparam = le32_to_cpu(anaparam);
1126                 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1127         }
1128
1129         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1130                         RTL818X_EEPROM_CMD_NORMAL);
1131 }
1132
1133 static int rtl8180_probe(struct pci_dev *pdev,
1134                                    const struct pci_device_id *id)
1135 {
1136         struct ieee80211_hw *dev;
1137         struct rtl8180_priv *priv;
1138         unsigned long mem_addr, mem_len;
1139         unsigned int io_addr, io_len;
1140         int err;
1141         const char *chip_name, *rf_name = NULL;
1142         u32 reg;
1143
1144         err = pci_enable_device(pdev);
1145         if (err) {
1146                 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1147                        pci_name(pdev));
1148                 return err;
1149         }
1150
1151         err = pci_request_regions(pdev, KBUILD_MODNAME);
1152         if (err) {
1153                 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1154                        pci_name(pdev));
1155                 return err;
1156         }
1157
1158         io_addr = pci_resource_start(pdev, 0);
1159         io_len = pci_resource_len(pdev, 0);
1160         mem_addr = pci_resource_start(pdev, 1);
1161         mem_len = pci_resource_len(pdev, 1);
1162
1163         if (mem_len < sizeof(struct rtl818x_csr) ||
1164             io_len < sizeof(struct rtl818x_csr)) {
1165                 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1166                        pci_name(pdev));
1167                 err = -ENOMEM;
1168                 goto err_free_reg;
1169         }
1170
1171         if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1172             (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1173                 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1174                        pci_name(pdev));
1175                 goto err_free_reg;
1176         }
1177
1178         pci_set_master(pdev);
1179
1180         dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1181         if (!dev) {
1182                 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1183                        pci_name(pdev));
1184                 err = -ENOMEM;
1185                 goto err_free_reg;
1186         }
1187
1188         priv = dev->priv;
1189         priv->pdev = pdev;
1190
1191         dev->max_rates = 2;
1192         SET_IEEE80211_DEV(dev, &pdev->dev);
1193         pci_set_drvdata(pdev, dev);
1194
1195         priv->map = pci_iomap(pdev, 1, mem_len);
1196         if (!priv->map)
1197                 priv->map = pci_iomap(pdev, 0, io_len);
1198
1199         if (!priv->map) {
1200                 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
1201                        pci_name(pdev));
1202                 goto err_free_dev;
1203         }
1204
1205         BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1206         BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1207
1208         memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1209         memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1210
1211         priv->band.band = IEEE80211_BAND_2GHZ;
1212         priv->band.channels = priv->channels;
1213         priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1214         priv->band.bitrates = priv->rates;
1215         priv->band.n_bitrates = 4;
1216         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1217
1218         dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1219                      IEEE80211_HW_RX_INCLUDES_FCS |
1220                      IEEE80211_HW_SIGNAL_UNSPEC;
1221         dev->vif_data_size = sizeof(struct rtl8180_vif);
1222         dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1223                                         BIT(NL80211_IFTYPE_ADHOC);
1224         dev->queues = 1;
1225         dev->max_signal = 65;
1226
1227         reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1228         reg &= RTL818X_TX_CONF_HWVER_MASK;
1229         switch (reg) {
1230         case RTL818X_TX_CONF_R8180_ABCD:
1231                 chip_name = "RTL8180";
1232                 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1233                 break;
1234
1235         case RTL818X_TX_CONF_R8180_F:
1236                 chip_name = "RTL8180vF";
1237                 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1238                 break;
1239
1240         case RTL818X_TX_CONF_R8185_ABC:
1241                 chip_name = "RTL8185";
1242                 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1243                 break;
1244
1245         case RTL818X_TX_CONF_R8185_D:
1246                 chip_name = "RTL8185vD";
1247                 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1248                 break;
1249         default:
1250                 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1251                        pci_name(pdev), reg >> 25);
1252                 goto err_iounmap;
1253         }
1254
1255         if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1256                 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1257                 pci_try_set_mwi(pdev);
1258         }
1259
1260         rtl8180_eeprom_read(priv);
1261
1262         switch (priv->rf_type) {
1263         case 1: rf_name = "Intersil";
1264                 break;
1265         case 2: rf_name = "RFMD";
1266                 break;
1267         case 3: priv->rf = &sa2400_rf_ops;
1268                 break;
1269         case 4: priv->rf = &max2820_rf_ops;
1270                 break;
1271         case 5: priv->rf = &grf5101_rf_ops;
1272                 break;
1273         case 9: priv->rf = rtl8180_detect_rf(dev);
1274                 break;
1275         case 10:
1276                 rf_name = "RTL8255";
1277                 break;
1278         default:
1279                 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1280                        pci_name(pdev), priv->rf_type);
1281                 goto err_iounmap;
1282         }
1283
1284         if (!priv->rf) {
1285                 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1286                        pci_name(pdev), rf_name);
1287                 goto err_iounmap;
1288         }
1289
1290         if (!is_valid_ether_addr(priv->mac_addr)) {
1291                 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1292                        " randomly generated MAC addr\n", pci_name(pdev));
1293                 eth_random_addr(priv->mac_addr);
1294         }
1295         SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
1296
1297         spin_lock_init(&priv->lock);
1298
1299         err = ieee80211_register_hw(dev);
1300         if (err) {
1301                 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1302                        pci_name(pdev));
1303                 goto err_iounmap;
1304         }
1305
1306         wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1307                    priv->mac_addr, chip_name, priv->rf->name);
1308
1309         return 0;
1310
1311  err_iounmap:
1312         pci_iounmap(pdev, priv->map);
1313
1314  err_free_dev:
1315         ieee80211_free_hw(dev);
1316
1317  err_free_reg:
1318         pci_release_regions(pdev);
1319         pci_disable_device(pdev);
1320         return err;
1321 }
1322
1323 static void rtl8180_remove(struct pci_dev *pdev)
1324 {
1325         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1326         struct rtl8180_priv *priv;
1327
1328         if (!dev)
1329                 return;
1330
1331         ieee80211_unregister_hw(dev);
1332
1333         priv = dev->priv;
1334
1335         pci_iounmap(pdev, priv->map);
1336         pci_release_regions(pdev);
1337         pci_disable_device(pdev);
1338         ieee80211_free_hw(dev);
1339 }
1340
1341 #ifdef CONFIG_PM
1342 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1343 {
1344         pci_save_state(pdev);
1345         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1346         return 0;
1347 }
1348
1349 static int rtl8180_resume(struct pci_dev *pdev)
1350 {
1351         pci_set_power_state(pdev, PCI_D0);
1352         pci_restore_state(pdev);
1353         return 0;
1354 }
1355
1356 #endif /* CONFIG_PM */
1357
1358 static struct pci_driver rtl8180_driver = {
1359         .name           = KBUILD_MODNAME,
1360         .id_table       = rtl8180_table,
1361         .probe          = rtl8180_probe,
1362         .remove         = rtl8180_remove,
1363 #ifdef CONFIG_PM
1364         .suspend        = rtl8180_suspend,
1365         .resume         = rtl8180_resume,
1366 #endif /* CONFIG_PM */
1367 };
1368
1369 module_pci_driver(rtl8180_driver);