2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/dmi.h>
23 #include <linux/errno.h>
25 #include <linux/genhd.h>
26 #include <linux/hdreg.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/ptrace.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/t10-pi.h>
43 #include <linux/timer.h>
44 #include <linux/types.h>
45 #include <linux/io-64-nonatomic-lo-hi.h>
46 #include <asm/unaligned.h>
47 #include <linux/sed-opal.h>
51 #define NVME_Q_DEPTH 1024
52 #define NVME_AQ_DEPTH 256
53 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
57 * We handle AEN commands ourselves and don't even let the
58 * block layer know about them.
60 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
62 static int use_threaded_interrupts;
63 module_param(use_threaded_interrupts, int, 0);
65 static bool use_cmb_sqes = true;
66 module_param(use_cmb_sqes, bool, 0644);
67 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
69 static struct workqueue_struct *nvme_workq;
74 static int nvme_reset(struct nvme_dev *dev);
75 static void nvme_process_cq(struct nvme_queue *nvmeq);
76 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
79 * Represents an NVM Express device. Each nvme_dev is a PCI function.
82 struct nvme_queue **queues;
83 struct blk_mq_tag_set tagset;
84 struct blk_mq_tag_set admin_tagset;
87 struct dma_pool *prp_page_pool;
88 struct dma_pool *prp_small_pool;
90 unsigned online_queues;
95 struct work_struct reset_work;
96 struct work_struct remove_work;
97 struct timer_list watchdog_timer;
98 struct mutex shutdown_lock;
101 dma_addr_t cmb_dma_addr;
105 struct nvme_ctrl ctrl;
106 struct completion ioq_wait;
108 dma_addr_t dbbuf_dbs_dma_addr;
110 dma_addr_t dbbuf_eis_dma_addr;
113 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
115 return qid * 2 * stride;
118 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
120 return (qid * 2 + 1) * stride;
123 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
125 return container_of(ctrl, struct nvme_dev, ctrl);
129 * An NVM Express queue. Each device has at least two (one for admin
130 * commands and one for I/O commands).
133 struct device *q_dmadev;
134 struct nvme_dev *dev;
135 char irqname[24]; /* nvme4294967295-65535\0 */
137 struct nvme_command *sq_cmds;
138 struct nvme_command __iomem *sq_cmds_io;
139 volatile struct nvme_completion *cqes;
140 struct blk_mq_tags **tags;
141 dma_addr_t sq_dma_addr;
142 dma_addr_t cq_dma_addr;
158 * The nvme_iod describes the data in an I/O, including the list of PRP
159 * entries. You can't see it in this data structure because C doesn't let
160 * me express that. Use nvme_init_iod to ensure there's enough space
161 * allocated to store the PRP list.
164 struct nvme_request req;
165 struct nvme_queue *nvmeq;
167 int npages; /* In the PRP list. 0 means small pool in use */
168 int nents; /* Used in scatterlist */
169 int length; /* Of data, in bytes */
170 dma_addr_t first_dma;
171 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
172 struct scatterlist *sg;
173 struct scatterlist inline_sg[0];
177 * Check we didin't inadvertently grow the command struct
179 static inline void _nvme_check_size(void)
181 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
182 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
186 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
187 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
188 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
189 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
190 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
191 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
192 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
193 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
196 static inline unsigned int nvme_dbbuf_size(u32 stride)
198 return ((num_possible_cpus() + 1) * 8 * stride);
201 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
203 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
208 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
209 &dev->dbbuf_dbs_dma_addr,
213 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
214 &dev->dbbuf_eis_dma_addr,
216 if (!dev->dbbuf_eis) {
217 dma_free_coherent(dev->dev, mem_size,
218 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
219 dev->dbbuf_dbs = NULL;
226 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
228 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
230 if (dev->dbbuf_dbs) {
231 dma_free_coherent(dev->dev, mem_size,
232 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
233 dev->dbbuf_dbs = NULL;
235 if (dev->dbbuf_eis) {
236 dma_free_coherent(dev->dev, mem_size,
237 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
238 dev->dbbuf_eis = NULL;
242 static void nvme_dbbuf_init(struct nvme_dev *dev,
243 struct nvme_queue *nvmeq, int qid)
245 if (!dev->dbbuf_dbs || !qid)
248 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
249 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
250 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
251 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
254 static void nvme_dbbuf_set(struct nvme_dev *dev)
256 struct nvme_command c;
261 memset(&c, 0, sizeof(c));
262 c.dbbuf.opcode = nvme_admin_dbbuf;
263 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
264 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
266 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
267 dev_warn(dev->dev, "unable to set dbbuf\n");
268 /* Free memory and continue on */
269 nvme_dbbuf_dma_free(dev);
273 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
275 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
278 /* Update dbbuf and return true if an MMIO is required */
279 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
280 volatile u32 *dbbuf_ei)
286 * Ensure that the queue is written before updating
287 * the doorbell in memory
291 old_value = *dbbuf_db;
294 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
302 * Max size of iod being embedded in the request payload
304 #define NVME_INT_PAGES 2
305 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
308 * Will slightly overestimate the number of pages needed. This is OK
309 * as it only leads to a small amount of wasted memory for the lifetime of
312 static int nvme_npages(unsigned size, struct nvme_dev *dev)
314 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
315 dev->ctrl.page_size);
316 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
319 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
320 unsigned int size, unsigned int nseg)
322 return sizeof(__le64 *) * nvme_npages(size, dev) +
323 sizeof(struct scatterlist) * nseg;
326 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
328 return sizeof(struct nvme_iod) +
329 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
332 static int nvmeq_irq(struct nvme_queue *nvmeq)
334 return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
337 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
338 unsigned int hctx_idx)
340 struct nvme_dev *dev = data;
341 struct nvme_queue *nvmeq = dev->queues[0];
343 WARN_ON(hctx_idx != 0);
344 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
345 WARN_ON(nvmeq->tags);
347 hctx->driver_data = nvmeq;
348 nvmeq->tags = &dev->admin_tagset.tags[0];
352 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
354 struct nvme_queue *nvmeq = hctx->driver_data;
359 static int nvme_admin_init_request(struct blk_mq_tag_set *set,
360 struct request *req, unsigned int hctx_idx,
361 unsigned int numa_node)
363 struct nvme_dev *dev = set->driver_data;
364 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
365 struct nvme_queue *nvmeq = dev->queues[0];
372 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
373 unsigned int hctx_idx)
375 struct nvme_dev *dev = data;
376 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
379 nvmeq->tags = &dev->tagset.tags[hctx_idx];
381 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
382 hctx->driver_data = nvmeq;
386 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
387 unsigned int hctx_idx, unsigned int numa_node)
389 struct nvme_dev *dev = set->driver_data;
390 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
391 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
398 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
400 struct nvme_dev *dev = set->driver_data;
402 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
406 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
407 * @nvmeq: The queue to use
408 * @cmd: The command to send
410 * Safe to use from interrupt context
412 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
413 struct nvme_command *cmd)
415 u16 tail = nvmeq->sq_tail;
417 if (nvmeq->sq_cmds_io)
418 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
420 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
422 if (++tail == nvmeq->q_depth)
424 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
426 writel(tail, nvmeq->q_db);
427 nvmeq->sq_tail = tail;
430 static __le64 **iod_list(struct request *req)
432 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
433 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
436 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
438 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
439 int nseg = blk_rq_nr_phys_segments(rq);
440 unsigned int size = blk_rq_payload_bytes(rq);
442 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
443 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
445 return BLK_MQ_RQ_QUEUE_BUSY;
447 iod->sg = iod->inline_sg;
455 return BLK_MQ_RQ_QUEUE_OK;
458 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
460 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
461 const int last_prp = dev->ctrl.page_size / 8 - 1;
463 __le64 **list = iod_list(req);
464 dma_addr_t prp_dma = iod->first_dma;
466 if (iod->npages == 0)
467 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
468 for (i = 0; i < iod->npages; i++) {
469 __le64 *prp_list = list[i];
470 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
471 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
472 prp_dma = next_prp_dma;
475 if (iod->sg != iod->inline_sg)
479 #ifdef CONFIG_BLK_DEV_INTEGRITY
480 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
482 if (be32_to_cpu(pi->ref_tag) == v)
483 pi->ref_tag = cpu_to_be32(p);
486 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
488 if (be32_to_cpu(pi->ref_tag) == p)
489 pi->ref_tag = cpu_to_be32(v);
493 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
495 * The virtual start sector is the one that was originally submitted by the
496 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
497 * start sector may be different. Remap protection information to match the
498 * physical LBA on writes, and back to the original seed on reads.
500 * Type 0 and 3 do not have a ref tag, so no remapping required.
502 static void nvme_dif_remap(struct request *req,
503 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
505 struct nvme_ns *ns = req->rq_disk->private_data;
506 struct bio_integrity_payload *bip;
507 struct t10_pi_tuple *pi;
509 u32 i, nlb, ts, phys, virt;
511 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
514 bip = bio_integrity(req->bio);
518 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
521 virt = bip_get_seed(bip);
522 phys = nvme_block_nr(ns, blk_rq_pos(req));
523 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
524 ts = ns->disk->queue->integrity.tuple_size;
526 for (i = 0; i < nlb; i++, virt++, phys++) {
527 pi = (struct t10_pi_tuple *)p;
528 dif_swap(phys, virt, pi);
533 #else /* CONFIG_BLK_DEV_INTEGRITY */
534 static void nvme_dif_remap(struct request *req,
535 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
538 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
541 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
546 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
548 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
549 struct dma_pool *pool;
550 int length = blk_rq_payload_bytes(req);
551 struct scatterlist *sg = iod->sg;
552 int dma_len = sg_dma_len(sg);
553 u64 dma_addr = sg_dma_address(sg);
554 u32 page_size = dev->ctrl.page_size;
555 int offset = dma_addr & (page_size - 1);
557 __le64 **list = iod_list(req);
561 length -= (page_size - offset);
565 dma_len -= (page_size - offset);
567 dma_addr += (page_size - offset);
570 dma_addr = sg_dma_address(sg);
571 dma_len = sg_dma_len(sg);
574 if (length <= page_size) {
575 iod->first_dma = dma_addr;
579 nprps = DIV_ROUND_UP(length, page_size);
580 if (nprps <= (256 / 8)) {
581 pool = dev->prp_small_pool;
584 pool = dev->prp_page_pool;
588 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
590 iod->first_dma = dma_addr;
595 iod->first_dma = prp_dma;
598 if (i == page_size >> 3) {
599 __le64 *old_prp_list = prp_list;
600 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
603 list[iod->npages++] = prp_list;
604 prp_list[0] = old_prp_list[i - 1];
605 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
608 prp_list[i++] = cpu_to_le64(dma_addr);
609 dma_len -= page_size;
610 dma_addr += page_size;
618 dma_addr = sg_dma_address(sg);
619 dma_len = sg_dma_len(sg);
625 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
626 struct nvme_command *cmnd)
628 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
629 struct request_queue *q = req->q;
630 enum dma_data_direction dma_dir = rq_data_dir(req) ?
631 DMA_TO_DEVICE : DMA_FROM_DEVICE;
632 int ret = BLK_MQ_RQ_QUEUE_ERROR;
634 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
635 iod->nents = blk_rq_map_sg(q, req, iod->sg);
639 ret = BLK_MQ_RQ_QUEUE_BUSY;
640 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
644 if (!nvme_setup_prps(dev, req))
647 ret = BLK_MQ_RQ_QUEUE_ERROR;
648 if (blk_integrity_rq(req)) {
649 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
652 sg_init_table(&iod->meta_sg, 1);
653 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
656 if (rq_data_dir(req))
657 nvme_dif_remap(req, nvme_dif_prep);
659 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
663 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
664 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
665 if (blk_integrity_rq(req))
666 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
667 return BLK_MQ_RQ_QUEUE_OK;
670 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
675 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
677 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
678 enum dma_data_direction dma_dir = rq_data_dir(req) ?
679 DMA_TO_DEVICE : DMA_FROM_DEVICE;
682 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
683 if (blk_integrity_rq(req)) {
684 if (!rq_data_dir(req))
685 nvme_dif_remap(req, nvme_dif_complete);
686 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
690 nvme_cleanup_cmd(req);
691 nvme_free_iod(dev, req);
695 * NOTE: ns is NULL when called on the admin queue.
697 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
698 const struct blk_mq_queue_data *bd)
700 struct nvme_ns *ns = hctx->queue->queuedata;
701 struct nvme_queue *nvmeq = hctx->driver_data;
702 struct nvme_dev *dev = nvmeq->dev;
703 struct request *req = bd->rq;
704 struct nvme_command cmnd;
705 int ret = BLK_MQ_RQ_QUEUE_OK;
708 * If formated with metadata, require the block layer provide a buffer
709 * unless this namespace is formated such that the metadata can be
710 * stripped/generated by the controller with PRACT=1.
712 if (ns && ns->ms && !blk_integrity_rq(req)) {
713 if (!(ns->pi_type && ns->ms == 8) &&
714 !blk_rq_is_passthrough(req)) {
715 blk_mq_end_request(req, -EFAULT);
716 return BLK_MQ_RQ_QUEUE_OK;
720 ret = nvme_setup_cmd(ns, req, &cmnd);
721 if (ret != BLK_MQ_RQ_QUEUE_OK)
724 ret = nvme_init_iod(req, dev);
725 if (ret != BLK_MQ_RQ_QUEUE_OK)
728 if (blk_rq_nr_phys_segments(req))
729 ret = nvme_map_data(dev, req, &cmnd);
731 if (ret != BLK_MQ_RQ_QUEUE_OK)
732 goto out_cleanup_iod;
734 blk_mq_start_request(req);
736 spin_lock_irq(&nvmeq->q_lock);
737 if (unlikely(nvmeq->cq_vector < 0)) {
738 ret = BLK_MQ_RQ_QUEUE_ERROR;
739 spin_unlock_irq(&nvmeq->q_lock);
740 goto out_cleanup_iod;
742 __nvme_submit_cmd(nvmeq, &cmnd);
743 nvme_process_cq(nvmeq);
744 spin_unlock_irq(&nvmeq->q_lock);
745 return BLK_MQ_RQ_QUEUE_OK;
747 nvme_free_iod(dev, req);
749 nvme_cleanup_cmd(req);
753 static void nvme_pci_complete_rq(struct request *req)
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
757 nvme_unmap_data(iod->nvmeq->dev, req);
758 nvme_complete_rq(req);
761 /* We read the CQE phase first to check if the rest of the entry is valid */
762 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
765 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
768 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
772 head = nvmeq->cq_head;
773 phase = nvmeq->cq_phase;
775 while (nvme_cqe_valid(nvmeq, head, phase)) {
776 struct nvme_completion cqe = nvmeq->cqes[head];
779 if (++head == nvmeq->q_depth) {
784 if (tag && *tag == cqe.command_id)
787 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
788 dev_warn(nvmeq->dev->ctrl.device,
789 "invalid id %d completed on queue %d\n",
790 cqe.command_id, le16_to_cpu(cqe.sq_id));
795 * AEN requests are special as they don't time out and can
796 * survive any kind of queue freeze and often don't respond to
797 * aborts. We don't even bother to allocate a struct request
798 * for them but rather special case them here.
800 if (unlikely(nvmeq->qid == 0 &&
801 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
802 nvme_complete_async_event(&nvmeq->dev->ctrl,
803 cqe.status, &cqe.result);
807 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
808 nvme_end_request(req, cqe.status, cqe.result);
811 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
814 if (likely(nvmeq->cq_vector >= 0))
815 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
817 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
818 nvmeq->cq_head = head;
819 nvmeq->cq_phase = phase;
824 static void nvme_process_cq(struct nvme_queue *nvmeq)
826 __nvme_process_cq(nvmeq, NULL);
829 static irqreturn_t nvme_irq(int irq, void *data)
832 struct nvme_queue *nvmeq = data;
833 spin_lock(&nvmeq->q_lock);
834 nvme_process_cq(nvmeq);
835 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
837 spin_unlock(&nvmeq->q_lock);
841 static irqreturn_t nvme_irq_check(int irq, void *data)
843 struct nvme_queue *nvmeq = data;
844 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
845 return IRQ_WAKE_THREAD;
849 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
851 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
852 spin_lock_irq(&nvmeq->q_lock);
853 __nvme_process_cq(nvmeq, &tag);
854 spin_unlock_irq(&nvmeq->q_lock);
863 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
865 struct nvme_queue *nvmeq = hctx->driver_data;
867 return __nvme_poll(nvmeq, tag);
870 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
872 struct nvme_dev *dev = to_nvme_dev(ctrl);
873 struct nvme_queue *nvmeq = dev->queues[0];
874 struct nvme_command c;
876 memset(&c, 0, sizeof(c));
877 c.common.opcode = nvme_admin_async_event;
878 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
880 spin_lock_irq(&nvmeq->q_lock);
881 __nvme_submit_cmd(nvmeq, &c);
882 spin_unlock_irq(&nvmeq->q_lock);
885 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
887 struct nvme_command c;
889 memset(&c, 0, sizeof(c));
890 c.delete_queue.opcode = opcode;
891 c.delete_queue.qid = cpu_to_le16(id);
893 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
896 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
897 struct nvme_queue *nvmeq)
899 struct nvme_command c;
900 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
903 * Note: we (ab)use the fact the the prp fields survive if no data
904 * is attached to the request.
906 memset(&c, 0, sizeof(c));
907 c.create_cq.opcode = nvme_admin_create_cq;
908 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
909 c.create_cq.cqid = cpu_to_le16(qid);
910 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
911 c.create_cq.cq_flags = cpu_to_le16(flags);
912 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
914 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
917 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
918 struct nvme_queue *nvmeq)
920 struct nvme_command c;
921 int flags = NVME_QUEUE_PHYS_CONTIG;
924 * Note: we (ab)use the fact the the prp fields survive if no data
925 * is attached to the request.
927 memset(&c, 0, sizeof(c));
928 c.create_sq.opcode = nvme_admin_create_sq;
929 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
930 c.create_sq.sqid = cpu_to_le16(qid);
931 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
932 c.create_sq.sq_flags = cpu_to_le16(flags);
933 c.create_sq.cqid = cpu_to_le16(qid);
935 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
938 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
940 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
943 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
945 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
948 static void abort_endio(struct request *req, int error)
950 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
951 struct nvme_queue *nvmeq = iod->nvmeq;
953 dev_warn(nvmeq->dev->ctrl.device,
954 "Abort status: 0x%x", nvme_req(req)->status);
955 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
956 blk_mq_free_request(req);
959 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
961 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
962 struct nvme_queue *nvmeq = iod->nvmeq;
963 struct nvme_dev *dev = nvmeq->dev;
964 struct request *abort_req;
965 struct nvme_command cmd;
968 * Did we miss an interrupt?
970 if (__nvme_poll(nvmeq, req->tag)) {
971 dev_warn(dev->ctrl.device,
972 "I/O %d QID %d timeout, completion polled\n",
973 req->tag, nvmeq->qid);
974 return BLK_EH_HANDLED;
978 * Shutdown immediately if controller times out while starting. The
979 * reset work will see the pci device disabled when it gets the forced
980 * cancellation error. All outstanding requests are completed on
981 * shutdown, so we return BLK_EH_HANDLED.
983 if (dev->ctrl.state == NVME_CTRL_RESETTING) {
984 dev_warn(dev->ctrl.device,
985 "I/O %d QID %d timeout, disable controller\n",
986 req->tag, nvmeq->qid);
987 nvme_dev_disable(dev, false);
988 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
989 return BLK_EH_HANDLED;
993 * Shutdown the controller immediately and schedule a reset if the
994 * command was already aborted once before and still hasn't been
995 * returned to the driver, or if this is the admin queue.
997 if (!nvmeq->qid || iod->aborted) {
998 dev_warn(dev->ctrl.device,
999 "I/O %d QID %d timeout, reset controller\n",
1000 req->tag, nvmeq->qid);
1001 nvme_dev_disable(dev, false);
1005 * Mark the request as handled, since the inline shutdown
1006 * forces all outstanding requests to complete.
1008 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1009 return BLK_EH_HANDLED;
1012 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1013 atomic_inc(&dev->ctrl.abort_limit);
1014 return BLK_EH_RESET_TIMER;
1018 memset(&cmd, 0, sizeof(cmd));
1019 cmd.abort.opcode = nvme_admin_abort_cmd;
1020 cmd.abort.cid = req->tag;
1021 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1023 dev_warn(nvmeq->dev->ctrl.device,
1024 "I/O %d QID %d timeout, aborting\n",
1025 req->tag, nvmeq->qid);
1027 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1028 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1029 if (IS_ERR(abort_req)) {
1030 atomic_inc(&dev->ctrl.abort_limit);
1031 return BLK_EH_RESET_TIMER;
1034 abort_req->timeout = ADMIN_TIMEOUT;
1035 abort_req->end_io_data = NULL;
1036 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1039 * The aborted req will be completed on receiving the abort req.
1040 * We enable the timer again. If hit twice, it'll cause a device reset,
1041 * as the device then is in a faulty state.
1043 return BLK_EH_RESET_TIMER;
1046 static void nvme_free_queue(struct nvme_queue *nvmeq)
1048 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1049 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1051 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1052 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1056 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1060 for (i = dev->queue_count - 1; i >= lowest; i--) {
1061 struct nvme_queue *nvmeq = dev->queues[i];
1063 dev->queues[i] = NULL;
1064 nvme_free_queue(nvmeq);
1069 * nvme_suspend_queue - put queue into suspended state
1070 * @nvmeq - queue to suspend
1072 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1076 spin_lock_irq(&nvmeq->q_lock);
1077 if (nvmeq->cq_vector == -1) {
1078 spin_unlock_irq(&nvmeq->q_lock);
1081 vector = nvmeq_irq(nvmeq);
1082 nvmeq->dev->online_queues--;
1083 nvmeq->cq_vector = -1;
1084 spin_unlock_irq(&nvmeq->q_lock);
1086 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1087 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1089 free_irq(vector, nvmeq);
1094 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1096 struct nvme_queue *nvmeq = dev->queues[0];
1100 if (nvme_suspend_queue(nvmeq))
1104 nvme_shutdown_ctrl(&dev->ctrl);
1106 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1107 dev->bar + NVME_REG_CAP));
1109 spin_lock_irq(&nvmeq->q_lock);
1110 nvme_process_cq(nvmeq);
1111 spin_unlock_irq(&nvmeq->q_lock);
1114 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1117 int q_depth = dev->q_depth;
1118 unsigned q_size_aligned = roundup(q_depth * entry_size,
1119 dev->ctrl.page_size);
1121 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1122 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1123 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1124 q_depth = div_u64(mem_per_q, entry_size);
1127 * Ensure the reduced q_depth is above some threshold where it
1128 * would be better to map queues in system memory with the
1138 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1141 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1142 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1143 dev->ctrl.page_size);
1144 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1145 nvmeq->sq_cmds_io = dev->cmb + offset;
1147 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1148 &nvmeq->sq_dma_addr, GFP_KERNEL);
1149 if (!nvmeq->sq_cmds)
1156 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1157 int depth, int node)
1159 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1164 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1165 &nvmeq->cq_dma_addr, GFP_KERNEL);
1169 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1172 nvmeq->q_dmadev = dev->dev;
1174 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1175 dev->ctrl.instance, qid);
1176 spin_lock_init(&nvmeq->q_lock);
1178 nvmeq->cq_phase = 1;
1179 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1180 nvmeq->q_depth = depth;
1182 nvmeq->cq_vector = -1;
1183 dev->queues[qid] = nvmeq;
1189 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1190 nvmeq->cq_dma_addr);
1196 static int queue_request_irq(struct nvme_queue *nvmeq)
1198 if (use_threaded_interrupts)
1199 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1200 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1202 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1203 nvmeq->irqname, nvmeq);
1206 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1208 struct nvme_dev *dev = nvmeq->dev;
1210 spin_lock_irq(&nvmeq->q_lock);
1213 nvmeq->cq_phase = 1;
1214 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1215 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1216 nvme_dbbuf_init(dev, nvmeq, qid);
1217 dev->online_queues++;
1218 spin_unlock_irq(&nvmeq->q_lock);
1221 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1223 struct nvme_dev *dev = nvmeq->dev;
1226 nvmeq->cq_vector = qid - 1;
1227 result = adapter_alloc_cq(dev, qid, nvmeq);
1231 result = adapter_alloc_sq(dev, qid, nvmeq);
1235 result = queue_request_irq(nvmeq);
1239 nvme_init_queue(nvmeq, qid);
1243 adapter_delete_sq(dev, qid);
1245 adapter_delete_cq(dev, qid);
1249 static const struct blk_mq_ops nvme_mq_admin_ops = {
1250 .queue_rq = nvme_queue_rq,
1251 .complete = nvme_pci_complete_rq,
1252 .init_hctx = nvme_admin_init_hctx,
1253 .exit_hctx = nvme_admin_exit_hctx,
1254 .init_request = nvme_admin_init_request,
1255 .timeout = nvme_timeout,
1258 static const struct blk_mq_ops nvme_mq_ops = {
1259 .queue_rq = nvme_queue_rq,
1260 .complete = nvme_pci_complete_rq,
1261 .init_hctx = nvme_init_hctx,
1262 .init_request = nvme_init_request,
1263 .map_queues = nvme_pci_map_queues,
1264 .timeout = nvme_timeout,
1268 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1270 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1272 * If the controller was reset during removal, it's possible
1273 * user requests may be waiting on a stopped queue. Start the
1274 * queue to flush these to completion.
1276 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1277 blk_cleanup_queue(dev->ctrl.admin_q);
1278 blk_mq_free_tag_set(&dev->admin_tagset);
1282 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1284 if (!dev->ctrl.admin_q) {
1285 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1286 dev->admin_tagset.nr_hw_queues = 1;
1289 * Subtract one to leave an empty queue entry for 'Full Queue'
1290 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1292 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1293 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1294 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1295 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1296 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1297 dev->admin_tagset.driver_data = dev;
1299 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1302 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1303 if (IS_ERR(dev->ctrl.admin_q)) {
1304 blk_mq_free_tag_set(&dev->admin_tagset);
1307 if (!blk_get_queue(dev->ctrl.admin_q)) {
1308 nvme_dev_remove_admin(dev);
1309 dev->ctrl.admin_q = NULL;
1313 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1318 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1322 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1323 struct nvme_queue *nvmeq;
1325 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1326 NVME_CAP_NSSRC(cap) : 0;
1328 if (dev->subsystem &&
1329 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1330 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1332 result = nvme_disable_ctrl(&dev->ctrl, cap);
1336 nvmeq = dev->queues[0];
1338 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1339 dev_to_node(dev->dev));
1344 aqa = nvmeq->q_depth - 1;
1347 writel(aqa, dev->bar + NVME_REG_AQA);
1348 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1349 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1351 result = nvme_enable_ctrl(&dev->ctrl, cap);
1355 nvmeq->cq_vector = 0;
1356 result = queue_request_irq(nvmeq);
1358 nvmeq->cq_vector = -1;
1365 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1368 /* If true, indicates loss of adapter communication, possibly by a
1369 * NVMe Subsystem reset.
1371 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1373 /* If there is a reset ongoing, we shouldn't reset again. */
1374 if (work_busy(&dev->reset_work))
1377 /* We shouldn't reset unless the controller is on fatal error state
1378 * _or_ if we lost the communication with it.
1380 if (!(csts & NVME_CSTS_CFS) && !nssro)
1383 /* If PCI error recovery process is happening, we cannot reset or
1384 * the recovery mechanism will surely fail.
1386 if (pci_channel_offline(to_pci_dev(dev->dev)))
1392 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1394 /* Read a config register to help see what died. */
1398 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1400 if (result == PCIBIOS_SUCCESSFUL)
1402 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1406 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1410 static void nvme_watchdog_timer(unsigned long data)
1412 struct nvme_dev *dev = (struct nvme_dev *)data;
1413 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1415 /* Skip controllers under certain specific conditions. */
1416 if (nvme_should_reset(dev, csts)) {
1417 if (!nvme_reset(dev))
1418 nvme_warn_reset(dev, csts);
1422 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1425 static int nvme_create_io_queues(struct nvme_dev *dev)
1430 for (i = dev->queue_count; i <= dev->max_qid; i++) {
1431 /* vector == qid - 1, match nvme_create_queue */
1432 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1433 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1439 max = min(dev->max_qid, dev->queue_count - 1);
1440 for (i = dev->online_queues; i <= max; i++) {
1441 ret = nvme_create_queue(dev->queues[i], i);
1447 * Ignore failing Create SQ/CQ commands, we can continue with less
1448 * than the desired aount of queues, and even a controller without
1449 * I/O queues an still be used to issue admin commands. This might
1450 * be useful to upgrade a buggy firmware for example.
1452 return ret >= 0 ? 0 : ret;
1455 static ssize_t nvme_cmb_show(struct device *dev,
1456 struct device_attribute *attr,
1459 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1461 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
1462 ndev->cmbloc, ndev->cmbsz);
1464 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1466 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1468 u64 szu, size, offset;
1469 resource_size_t bar_size;
1470 struct pci_dev *pdev = to_pci_dev(dev->dev);
1472 dma_addr_t dma_addr;
1474 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1475 if (!(NVME_CMB_SZ(dev->cmbsz)))
1477 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1482 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1483 size = szu * NVME_CMB_SZ(dev->cmbsz);
1484 offset = szu * NVME_CMB_OFST(dev->cmbloc);
1485 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1487 if (offset > bar_size)
1491 * Controllers may support a CMB size larger than their BAR,
1492 * for example, due to being behind a bridge. Reduce the CMB to
1493 * the reported size of the BAR
1495 if (size > bar_size - offset)
1496 size = bar_size - offset;
1498 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1499 cmb = ioremap_wc(dma_addr, size);
1503 dev->cmb_dma_addr = dma_addr;
1504 dev->cmb_size = size;
1508 static inline void nvme_release_cmb(struct nvme_dev *dev)
1516 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1518 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1521 static int nvme_setup_io_queues(struct nvme_dev *dev)
1523 struct nvme_queue *adminq = dev->queues[0];
1524 struct pci_dev *pdev = to_pci_dev(dev->dev);
1525 int result, nr_io_queues, size;
1527 nr_io_queues = num_online_cpus();
1528 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1532 if (nr_io_queues == 0)
1535 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1536 result = nvme_cmb_qdepth(dev, nr_io_queues,
1537 sizeof(struct nvme_command));
1539 dev->q_depth = result;
1541 nvme_release_cmb(dev);
1544 size = db_bar_size(dev, nr_io_queues);
1548 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1551 if (!--nr_io_queues)
1553 size = db_bar_size(dev, nr_io_queues);
1555 dev->dbs = dev->bar + 4096;
1556 adminq->q_db = dev->dbs;
1559 /* Deregister the admin queue's interrupt */
1560 free_irq(pci_irq_vector(pdev, 0), adminq);
1563 * If we enable msix early due to not intx, disable it again before
1564 * setting up the full range we need.
1566 pci_free_irq_vectors(pdev);
1567 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1568 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1569 if (nr_io_queues <= 0)
1571 dev->max_qid = nr_io_queues;
1574 * Should investigate if there's a performance win from allocating
1575 * more queues than interrupt vectors; it might allow the submission
1576 * path to scale better, even if the receive path is limited by the
1577 * number of interrupts.
1580 result = queue_request_irq(adminq);
1582 adminq->cq_vector = -1;
1585 return nvme_create_io_queues(dev);
1588 static void nvme_del_queue_end(struct request *req, int error)
1590 struct nvme_queue *nvmeq = req->end_io_data;
1592 blk_mq_free_request(req);
1593 complete(&nvmeq->dev->ioq_wait);
1596 static void nvme_del_cq_end(struct request *req, int error)
1598 struct nvme_queue *nvmeq = req->end_io_data;
1601 unsigned long flags;
1604 * We might be called with the AQ q_lock held
1605 * and the I/O queue q_lock should always
1606 * nest inside the AQ one.
1608 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1609 SINGLE_DEPTH_NESTING);
1610 nvme_process_cq(nvmeq);
1611 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1614 nvme_del_queue_end(req, error);
1617 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1619 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1620 struct request *req;
1621 struct nvme_command cmd;
1623 memset(&cmd, 0, sizeof(cmd));
1624 cmd.delete_queue.opcode = opcode;
1625 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1627 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1629 return PTR_ERR(req);
1631 req->timeout = ADMIN_TIMEOUT;
1632 req->end_io_data = nvmeq;
1634 blk_execute_rq_nowait(q, NULL, req, false,
1635 opcode == nvme_admin_delete_cq ?
1636 nvme_del_cq_end : nvme_del_queue_end);
1640 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1643 unsigned long timeout;
1644 u8 opcode = nvme_admin_delete_sq;
1646 for (pass = 0; pass < 2; pass++) {
1647 int sent = 0, i = queues;
1649 reinit_completion(&dev->ioq_wait);
1651 timeout = ADMIN_TIMEOUT;
1652 for (; i > 0; i--, sent++)
1653 if (nvme_delete_queue(dev->queues[i], opcode))
1657 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1663 opcode = nvme_admin_delete_cq;
1668 * Return: error value if an error occurred setting up the queues or calling
1669 * Identify Device. 0 if these succeeded, even if adding some of the
1670 * namespaces failed. At the moment, these failures are silent. TBD which
1671 * failures should be reported.
1673 static int nvme_dev_add(struct nvme_dev *dev)
1675 if (!dev->ctrl.tagset) {
1676 dev->tagset.ops = &nvme_mq_ops;
1677 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1678 dev->tagset.timeout = NVME_IO_TIMEOUT;
1679 dev->tagset.numa_node = dev_to_node(dev->dev);
1680 dev->tagset.queue_depth =
1681 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1682 dev->tagset.cmd_size = nvme_cmd_size(dev);
1683 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1684 dev->tagset.driver_data = dev;
1686 if (blk_mq_alloc_tag_set(&dev->tagset))
1688 dev->ctrl.tagset = &dev->tagset;
1690 nvme_dbbuf_set(dev);
1692 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1694 /* Free previously allocated queues that are no longer usable */
1695 nvme_free_queues(dev, dev->online_queues);
1701 static int nvme_pci_enable(struct nvme_dev *dev)
1704 int result = -ENOMEM;
1705 struct pci_dev *pdev = to_pci_dev(dev->dev);
1707 if (pci_enable_device_mem(pdev))
1710 pci_set_master(pdev);
1712 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1713 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1716 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1722 * Some devices and/or platforms don't advertise or work with INTx
1723 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1724 * adjust this later.
1726 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1730 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1732 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1733 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1734 dev->dbs = dev->bar + 4096;
1737 * Temporary fix for the Apple controller found in the MacBook8,1 and
1738 * some MacBook7,1 to avoid controller resets and data loss.
1740 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1742 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1743 "queue depth=%u to work around controller resets\n",
1748 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1749 * populate sysfs if a CMB is implemented. Note that we add the
1750 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1751 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1752 * NULL as final argument to sysfs_add_file_to_group.
1755 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1756 dev->cmb = nvme_map_cmb(dev);
1759 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1760 &dev_attr_cmb.attr, NULL))
1762 "failed to add sysfs attribute for CMB\n");
1766 pci_enable_pcie_error_reporting(pdev);
1767 pci_save_state(pdev);
1771 pci_disable_device(pdev);
1775 static void nvme_dev_unmap(struct nvme_dev *dev)
1779 pci_release_mem_regions(to_pci_dev(dev->dev));
1782 static void nvme_pci_disable(struct nvme_dev *dev)
1784 struct pci_dev *pdev = to_pci_dev(dev->dev);
1786 pci_free_irq_vectors(pdev);
1788 if (pci_is_enabled(pdev)) {
1789 pci_disable_pcie_error_reporting(pdev);
1790 pci_disable_device(pdev);
1794 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1798 struct pci_dev *pdev = to_pci_dev(dev->dev);
1800 del_timer_sync(&dev->watchdog_timer);
1802 mutex_lock(&dev->shutdown_lock);
1803 if (pci_is_enabled(pdev)) {
1804 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1806 if (dev->ctrl.state == NVME_CTRL_LIVE)
1807 nvme_start_freeze(&dev->ctrl);
1808 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1809 pdev->error_state != pci_channel_io_normal);
1813 * Give the controller a chance to complete all entered requests if
1814 * doing a safe shutdown.
1816 if (!dead && shutdown)
1817 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1818 nvme_stop_queues(&dev->ctrl);
1820 queues = dev->online_queues - 1;
1821 for (i = dev->queue_count - 1; i > 0; i--)
1822 nvme_suspend_queue(dev->queues[i]);
1825 /* A device might become IO incapable very soon during
1826 * probe, before the admin queue is configured. Thus,
1827 * queue_count can be 0 here.
1829 if (dev->queue_count)
1830 nvme_suspend_queue(dev->queues[0]);
1832 nvme_disable_io_queues(dev, queues);
1833 nvme_disable_admin_queue(dev, shutdown);
1835 nvme_pci_disable(dev);
1837 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1838 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1841 * The driver will not be starting up queues again if shutting down so
1842 * must flush all entered requests to their failed completion to avoid
1843 * deadlocking blk-mq hot-cpu notifier.
1846 nvme_start_queues(&dev->ctrl);
1847 mutex_unlock(&dev->shutdown_lock);
1850 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1852 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1853 PAGE_SIZE, PAGE_SIZE, 0);
1854 if (!dev->prp_page_pool)
1857 /* Optimisation for I/Os between 4k and 128k */
1858 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1860 if (!dev->prp_small_pool) {
1861 dma_pool_destroy(dev->prp_page_pool);
1867 static void nvme_release_prp_pools(struct nvme_dev *dev)
1869 dma_pool_destroy(dev->prp_page_pool);
1870 dma_pool_destroy(dev->prp_small_pool);
1873 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1875 struct nvme_dev *dev = to_nvme_dev(ctrl);
1877 nvme_dbbuf_dma_free(dev);
1878 put_device(dev->dev);
1879 if (dev->tagset.tags)
1880 blk_mq_free_tag_set(&dev->tagset);
1881 if (dev->ctrl.admin_q)
1882 blk_put_queue(dev->ctrl.admin_q);
1884 free_opal_dev(dev->ctrl.opal_dev);
1888 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1890 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1892 kref_get(&dev->ctrl.kref);
1893 nvme_dev_disable(dev, false);
1894 if (!schedule_work(&dev->remove_work))
1895 nvme_put_ctrl(&dev->ctrl);
1898 static void nvme_reset_work(struct work_struct *work)
1900 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1901 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
1902 int result = -ENODEV;
1904 if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1908 * If we're called to reset a live controller first shut it down before
1911 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1912 nvme_dev_disable(dev, false);
1914 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1917 result = nvme_pci_enable(dev);
1921 result = nvme_configure_admin_queue(dev);
1925 nvme_init_queue(dev->queues[0], 0);
1926 result = nvme_alloc_admin_tags(dev);
1930 result = nvme_init_identify(&dev->ctrl);
1934 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
1935 if (!dev->ctrl.opal_dev)
1936 dev->ctrl.opal_dev =
1937 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
1938 else if (was_suspend)
1939 opal_unlock_from_suspend(dev->ctrl.opal_dev);
1941 free_opal_dev(dev->ctrl.opal_dev);
1942 dev->ctrl.opal_dev = NULL;
1945 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
1946 result = nvme_dbbuf_dma_alloc(dev);
1949 "unable to allocate dma for dbbuf\n");
1952 result = nvme_setup_io_queues(dev);
1957 * A controller that can not execute IO typically requires user
1958 * intervention to correct. For such degraded controllers, the driver
1959 * should not submit commands the user did not request, so skip
1960 * registering for asynchronous event notification on this condition.
1962 if (dev->online_queues > 1)
1963 nvme_queue_async_events(&dev->ctrl);
1965 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1968 * Keep the controller around but remove all namespaces if we don't have
1969 * any working I/O queue.
1971 if (dev->online_queues < 2) {
1972 dev_warn(dev->ctrl.device, "IO queues not created\n");
1973 nvme_kill_queues(&dev->ctrl);
1974 nvme_remove_namespaces(&dev->ctrl);
1976 nvme_start_queues(&dev->ctrl);
1977 nvme_wait_freeze(&dev->ctrl);
1979 nvme_unfreeze(&dev->ctrl);
1982 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1983 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1987 if (dev->online_queues > 1)
1988 nvme_queue_scan(&dev->ctrl);
1992 nvme_remove_dead_ctrl(dev, result);
1995 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1997 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1998 struct pci_dev *pdev = to_pci_dev(dev->dev);
2000 nvme_kill_queues(&dev->ctrl);
2001 if (pci_get_drvdata(pdev))
2002 device_release_driver(&pdev->dev);
2003 nvme_put_ctrl(&dev->ctrl);
2006 static int nvme_reset(struct nvme_dev *dev)
2008 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
2010 if (work_busy(&dev->reset_work))
2012 if (!queue_work(nvme_workq, &dev->reset_work))
2017 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2019 *val = readl(to_nvme_dev(ctrl)->bar + off);
2023 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2025 writel(val, to_nvme_dev(ctrl)->bar + off);
2029 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2031 *val = readq(to_nvme_dev(ctrl)->bar + off);
2035 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2037 struct nvme_dev *dev = to_nvme_dev(ctrl);
2038 int ret = nvme_reset(dev);
2041 flush_work(&dev->reset_work);
2045 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2047 .module = THIS_MODULE,
2048 .reg_read32 = nvme_pci_reg_read32,
2049 .reg_write32 = nvme_pci_reg_write32,
2050 .reg_read64 = nvme_pci_reg_read64,
2051 .reset_ctrl = nvme_pci_reset_ctrl,
2052 .free_ctrl = nvme_pci_free_ctrl,
2053 .submit_async_event = nvme_pci_submit_async_event,
2056 static int nvme_dev_map(struct nvme_dev *dev)
2058 struct pci_dev *pdev = to_pci_dev(dev->dev);
2060 if (pci_request_mem_regions(pdev, "nvme"))
2063 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2069 pci_release_mem_regions(pdev);
2073 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2075 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2077 * Several Samsung devices seem to drop off the PCIe bus
2078 * randomly when APST is on and uses the deepest sleep state.
2079 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2080 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2081 * 950 PRO 256GB", but it seems to be restricted to two Dell
2084 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2085 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2086 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2087 return NVME_QUIRK_NO_DEEPEST_PS;
2093 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2095 int node, result = -ENOMEM;
2096 struct nvme_dev *dev;
2097 unsigned long quirks = id->driver_data;
2099 node = dev_to_node(&pdev->dev);
2100 if (node == NUMA_NO_NODE)
2101 set_dev_node(&pdev->dev, first_memory_node);
2103 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2106 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2111 dev->dev = get_device(&pdev->dev);
2112 pci_set_drvdata(pdev, dev);
2114 result = nvme_dev_map(dev);
2118 INIT_WORK(&dev->reset_work, nvme_reset_work);
2119 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2120 setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
2121 (unsigned long)dev);
2122 mutex_init(&dev->shutdown_lock);
2123 init_completion(&dev->ioq_wait);
2125 result = nvme_setup_prp_pools(dev);
2129 quirks |= check_dell_samsung_bug(pdev);
2131 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2136 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2138 queue_work(nvme_workq, &dev->reset_work);
2142 nvme_release_prp_pools(dev);
2144 put_device(dev->dev);
2145 nvme_dev_unmap(dev);
2152 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2154 struct nvme_dev *dev = pci_get_drvdata(pdev);
2157 nvme_dev_disable(dev, false);
2162 static void nvme_shutdown(struct pci_dev *pdev)
2164 struct nvme_dev *dev = pci_get_drvdata(pdev);
2165 nvme_dev_disable(dev, true);
2169 * The driver's remove may be called on a device in a partially initialized
2170 * state. This function must not have any dependencies on the device state in
2173 static void nvme_remove(struct pci_dev *pdev)
2175 struct nvme_dev *dev = pci_get_drvdata(pdev);
2177 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2179 pci_set_drvdata(pdev, NULL);
2181 if (!pci_device_is_present(pdev)) {
2182 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2183 nvme_dev_disable(dev, false);
2186 flush_work(&dev->reset_work);
2187 nvme_uninit_ctrl(&dev->ctrl);
2188 nvme_dev_disable(dev, true);
2189 nvme_dev_remove_admin(dev);
2190 nvme_free_queues(dev, 0);
2191 nvme_release_cmb(dev);
2192 nvme_release_prp_pools(dev);
2193 nvme_dev_unmap(dev);
2194 nvme_put_ctrl(&dev->ctrl);
2197 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2202 if (pci_vfs_assigned(pdev)) {
2203 dev_warn(&pdev->dev,
2204 "Cannot disable SR-IOV VFs while assigned\n");
2207 pci_disable_sriov(pdev);
2211 ret = pci_enable_sriov(pdev, numvfs);
2212 return ret ? ret : numvfs;
2215 #ifdef CONFIG_PM_SLEEP
2216 static int nvme_suspend(struct device *dev)
2218 struct pci_dev *pdev = to_pci_dev(dev);
2219 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2221 nvme_dev_disable(ndev, true);
2225 static int nvme_resume(struct device *dev)
2227 struct pci_dev *pdev = to_pci_dev(dev);
2228 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2235 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2237 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2238 pci_channel_state_t state)
2240 struct nvme_dev *dev = pci_get_drvdata(pdev);
2243 * A frozen channel requires a reset. When detected, this method will
2244 * shutdown the controller to quiesce. The controller will be restarted
2245 * after the slot reset through driver's slot_reset callback.
2248 case pci_channel_io_normal:
2249 return PCI_ERS_RESULT_CAN_RECOVER;
2250 case pci_channel_io_frozen:
2251 dev_warn(dev->ctrl.device,
2252 "frozen state error detected, reset controller\n");
2253 nvme_dev_disable(dev, false);
2254 return PCI_ERS_RESULT_NEED_RESET;
2255 case pci_channel_io_perm_failure:
2256 dev_warn(dev->ctrl.device,
2257 "failure state error detected, request disconnect\n");
2258 return PCI_ERS_RESULT_DISCONNECT;
2260 return PCI_ERS_RESULT_NEED_RESET;
2263 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2265 struct nvme_dev *dev = pci_get_drvdata(pdev);
2267 dev_info(dev->ctrl.device, "restart after slot reset\n");
2268 pci_restore_state(pdev);
2270 return PCI_ERS_RESULT_RECOVERED;
2273 static void nvme_error_resume(struct pci_dev *pdev)
2275 pci_cleanup_aer_uncorrect_error_status(pdev);
2278 static const struct pci_error_handlers nvme_err_handler = {
2279 .error_detected = nvme_error_detected,
2280 .slot_reset = nvme_slot_reset,
2281 .resume = nvme_error_resume,
2282 .reset_notify = nvme_reset_notify,
2285 static const struct pci_device_id nvme_id_table[] = {
2286 { PCI_VDEVICE(INTEL, 0x0953),
2287 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2288 NVME_QUIRK_DEALLOCATE_ZEROES, },
2289 { PCI_VDEVICE(INTEL, 0x0a53),
2290 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2291 NVME_QUIRK_DEALLOCATE_ZEROES, },
2292 { PCI_VDEVICE(INTEL, 0x0a54),
2293 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2294 NVME_QUIRK_DEALLOCATE_ZEROES, },
2295 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2296 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2297 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2298 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2299 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2300 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2301 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2302 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2303 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2306 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2308 static struct pci_driver nvme_driver = {
2310 .id_table = nvme_id_table,
2311 .probe = nvme_probe,
2312 .remove = nvme_remove,
2313 .shutdown = nvme_shutdown,
2315 .pm = &nvme_dev_pm_ops,
2317 .sriov_configure = nvme_pci_sriov_configure,
2318 .err_handler = &nvme_err_handler,
2321 static int __init nvme_init(void)
2325 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2329 result = pci_register_driver(&nvme_driver);
2331 destroy_workqueue(nvme_workq);
2335 static void __exit nvme_exit(void)
2337 pci_unregister_driver(&nvme_driver);
2338 destroy_workqueue(nvme_workq);
2342 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2343 MODULE_LICENSE("GPL");
2344 MODULE_VERSION("1.0");
2345 module_init(nvme_init);
2346 module_exit(nvme_exit);