3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/irqdomain.h>
26 static int pci_msi_enable = 1;
27 int pci_msi_ignore_mask;
29 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
31 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
32 static struct irq_domain *pci_msi_default_domain;
33 static DEFINE_MUTEX(pci_msi_domain_lock);
35 struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
37 return pci_msi_default_domain;
40 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
42 struct irq_domain *domain;
44 domain = arch_get_pci_msi_domain(dev);
46 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
48 return arch_setup_msi_irqs(dev, nvec, type);
51 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
53 struct irq_domain *domain;
55 domain = arch_get_pci_msi_domain(dev);
57 pci_msi_domain_free_irqs(domain, dev);
59 arch_teardown_msi_irqs(dev);
62 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
63 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
68 struct msi_controller * __weak pcibios_msi_controller(struct pci_dev *dev)
73 static struct msi_controller *pci_msi_controller(struct pci_dev *dev)
75 struct msi_controller *msi_ctrl = dev->bus->msi;
80 return pcibios_msi_controller(dev);
83 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
85 struct msi_controller *chip = pci_msi_controller(dev);
88 if (!chip || !chip->setup_irq)
91 err = chip->setup_irq(chip, dev, desc);
95 irq_set_chip_data(desc->irq, chip);
100 void __weak arch_teardown_msi_irq(unsigned int irq)
102 struct msi_controller *chip = irq_get_chip_data(irq);
104 if (!chip || !chip->teardown_irq)
107 chip->teardown_irq(chip, irq);
110 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
112 struct msi_desc *entry;
116 * If an architecture wants to support multiple MSI, it needs to
117 * override arch_setup_msi_irqs()
119 if (type == PCI_CAP_ID_MSI && nvec > 1)
122 list_for_each_entry(entry, &dev->msi_list, list) {
123 ret = arch_setup_msi_irq(dev, entry);
134 * We have a default implementation available as a separate non-weak
135 * function, as it is used by the Xen x86 PCI code
137 void default_teardown_msi_irqs(struct pci_dev *dev)
140 struct msi_desc *entry;
142 list_for_each_entry(entry, &dev->msi_list, list)
144 for (i = 0; i < entry->nvec_used; i++)
145 arch_teardown_msi_irq(entry->irq + i);
148 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
150 return default_teardown_msi_irqs(dev);
153 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
155 struct msi_desc *entry;
158 if (dev->msix_enabled) {
159 list_for_each_entry(entry, &dev->msi_list, list) {
160 if (irq == entry->irq)
163 } else if (dev->msi_enabled) {
164 entry = irq_get_msi_desc(irq);
168 __pci_write_msi_msg(entry, &entry->msg);
171 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
173 return default_restore_msi_irqs(dev);
176 static void msi_set_enable(struct pci_dev *dev, int enable)
180 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
181 control &= ~PCI_MSI_FLAGS_ENABLE;
183 control |= PCI_MSI_FLAGS_ENABLE;
184 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
187 static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
191 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
194 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
197 static inline __attribute_const__ u32 msi_mask(unsigned x)
199 /* Don't shift by >= width of type */
202 return (1 << (1 << x)) - 1;
206 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
207 * mask all MSI interrupts by clearing the MSI enable bit does not work
208 * reliably as devices without an INTx disable bit will then generate a
209 * level IRQ which will never be cleared.
211 u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
213 u32 mask_bits = desc->masked;
215 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
220 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
225 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
227 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
231 * This internal function does not flush PCI writes to the device.
232 * All users must ensure that they read from the device before either
233 * assuming that the device state is up to date, or returning out of this
234 * file. This saves a few milliseconds when initialising devices with lots
235 * of MSI-X interrupts.
237 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
239 u32 mask_bits = desc->masked;
240 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
241 PCI_MSIX_ENTRY_VECTOR_CTRL;
243 if (pci_msi_ignore_mask)
246 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
248 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
249 writel(mask_bits, desc->mask_base + offset);
254 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
256 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
259 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
261 struct msi_desc *desc = irq_data_get_msi(data);
263 if (desc->msi_attrib.is_msix) {
264 msix_mask_irq(desc, flag);
265 readl(desc->mask_base); /* Flush write to device */
267 unsigned offset = data->irq - desc->irq;
268 msi_mask_irq(desc, 1 << offset, flag << offset);
273 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
274 * @data: pointer to irqdata associated to that interrupt
276 void pci_msi_mask_irq(struct irq_data *data)
278 msi_set_mask_bit(data, 1);
282 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
283 * @data: pointer to irqdata associated to that interrupt
285 void pci_msi_unmask_irq(struct irq_data *data)
287 msi_set_mask_bit(data, 0);
290 void default_restore_msi_irqs(struct pci_dev *dev)
292 struct msi_desc *entry;
294 list_for_each_entry(entry, &dev->msi_list, list)
295 default_restore_msi_irq(dev, entry->irq);
298 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
300 BUG_ON(entry->dev->current_state != PCI_D0);
302 if (entry->msi_attrib.is_msix) {
303 void __iomem *base = entry->mask_base +
304 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
306 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
307 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
308 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
310 struct pci_dev *dev = entry->dev;
311 int pos = dev->msi_cap;
314 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
316 if (entry->msi_attrib.is_64) {
317 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
319 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
322 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
328 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
330 if (entry->dev->current_state != PCI_D0) {
331 /* Don't touch the hardware now */
332 } else if (entry->msi_attrib.is_msix) {
334 base = entry->mask_base +
335 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
337 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
338 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
339 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
341 struct pci_dev *dev = entry->dev;
342 int pos = dev->msi_cap;
345 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
346 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
347 msgctl |= entry->msi_attrib.multiple << 4;
348 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
350 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
352 if (entry->msi_attrib.is_64) {
353 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
355 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
358 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
365 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
367 struct msi_desc *entry = irq_get_msi_desc(irq);
369 __pci_write_msi_msg(entry, msg);
371 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
373 static void free_msi_irqs(struct pci_dev *dev)
375 struct msi_desc *entry, *tmp;
376 struct attribute **msi_attrs;
377 struct device_attribute *dev_attr;
380 list_for_each_entry(entry, &dev->msi_list, list)
382 for (i = 0; i < entry->nvec_used; i++)
383 BUG_ON(irq_has_action(entry->irq + i));
385 pci_msi_teardown_msi_irqs(dev);
387 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
388 if (entry->msi_attrib.is_msix) {
389 if (list_is_last(&entry->list, &dev->msi_list))
390 iounmap(entry->mask_base);
393 list_del(&entry->list);
397 if (dev->msi_irq_groups) {
398 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
399 msi_attrs = dev->msi_irq_groups[0]->attrs;
400 while (msi_attrs[count]) {
401 dev_attr = container_of(msi_attrs[count],
402 struct device_attribute, attr);
403 kfree(dev_attr->attr.name);
408 kfree(dev->msi_irq_groups[0]);
409 kfree(dev->msi_irq_groups);
410 dev->msi_irq_groups = NULL;
414 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
416 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
420 INIT_LIST_HEAD(&desc->list);
426 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
428 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
429 pci_intx(dev, enable);
432 static void __pci_restore_msi_state(struct pci_dev *dev)
435 struct msi_desc *entry;
437 if (!dev->msi_enabled)
440 entry = irq_get_msi_desc(dev->irq);
442 pci_intx_for_msi(dev, 0);
443 msi_set_enable(dev, 0);
444 arch_restore_msi_irqs(dev);
446 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
447 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
449 control &= ~PCI_MSI_FLAGS_QSIZE;
450 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
451 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
454 static void __pci_restore_msix_state(struct pci_dev *dev)
456 struct msi_desc *entry;
458 if (!dev->msix_enabled)
460 BUG_ON(list_empty(&dev->msi_list));
462 /* route the table */
463 pci_intx_for_msi(dev, 0);
464 msix_clear_and_set_ctrl(dev, 0,
465 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
467 arch_restore_msi_irqs(dev);
468 list_for_each_entry(entry, &dev->msi_list, list)
469 msix_mask_irq(entry, entry->masked);
471 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
474 void pci_restore_msi_state(struct pci_dev *dev)
476 __pci_restore_msi_state(dev);
477 __pci_restore_msix_state(dev);
479 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
481 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
484 struct msi_desc *entry;
488 retval = kstrtoul(attr->attr.name, 10, &irq);
492 entry = irq_get_msi_desc(irq);
494 return sprintf(buf, "%s\n",
495 entry->msi_attrib.is_msix ? "msix" : "msi");
500 static int populate_msi_sysfs(struct pci_dev *pdev)
502 struct attribute **msi_attrs;
503 struct attribute *msi_attr;
504 struct device_attribute *msi_dev_attr;
505 struct attribute_group *msi_irq_group;
506 const struct attribute_group **msi_irq_groups;
507 struct msi_desc *entry;
512 /* Determine how many msi entries we have */
513 list_for_each_entry(entry, &pdev->msi_list, list)
518 /* Dynamically create the MSI attributes for the PCI device */
519 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
522 list_for_each_entry(entry, &pdev->msi_list, list) {
523 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
526 msi_attrs[count] = &msi_dev_attr->attr;
528 sysfs_attr_init(&msi_dev_attr->attr);
529 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
531 if (!msi_dev_attr->attr.name)
533 msi_dev_attr->attr.mode = S_IRUGO;
534 msi_dev_attr->show = msi_mode_show;
538 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
541 msi_irq_group->name = "msi_irqs";
542 msi_irq_group->attrs = msi_attrs;
544 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
546 goto error_irq_group;
547 msi_irq_groups[0] = msi_irq_group;
549 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
551 goto error_irq_groups;
552 pdev->msi_irq_groups = msi_irq_groups;
557 kfree(msi_irq_groups);
559 kfree(msi_irq_group);
562 msi_attr = msi_attrs[count];
564 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
565 kfree(msi_attr->name);
568 msi_attr = msi_attrs[count];
574 static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
577 struct msi_desc *entry;
579 /* MSI Entry Initialization */
580 entry = alloc_msi_entry(dev);
584 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
586 entry->msi_attrib.is_msix = 0;
587 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
588 entry->msi_attrib.entry_nr = 0;
589 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
590 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
591 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
592 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
593 entry->nvec_used = nvec;
595 if (control & PCI_MSI_FLAGS_64BIT)
596 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
598 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
600 /* Save the initial mask status */
601 if (entry->msi_attrib.maskbit)
602 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
608 * msi_capability_init - configure device's MSI capability structure
609 * @dev: pointer to the pci_dev data structure of MSI device function
610 * @nvec: number of interrupts to allocate
612 * Setup the MSI capability structure of the device with the requested
613 * number of interrupts. A return value of zero indicates the successful
614 * setup of an entry with the new MSI irq. A negative return value indicates
615 * an error, and a positive return value indicates the number of interrupts
616 * which could have been allocated.
618 static int msi_capability_init(struct pci_dev *dev, int nvec)
620 struct msi_desc *entry;
624 msi_set_enable(dev, 0); /* Disable MSI during set up */
626 entry = msi_setup_entry(dev, nvec);
630 /* All MSIs are unmasked by default, Mask them all */
631 mask = msi_mask(entry->msi_attrib.multi_cap);
632 msi_mask_irq(entry, mask, mask);
634 list_add_tail(&entry->list, &dev->msi_list);
636 /* Configure MSI capability structure */
637 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
639 msi_mask_irq(entry, mask, ~mask);
644 ret = populate_msi_sysfs(dev);
646 msi_mask_irq(entry, mask, ~mask);
651 /* Set MSI enabled bits */
652 pci_intx_for_msi(dev, 0);
653 msi_set_enable(dev, 1);
654 dev->msi_enabled = 1;
656 dev->irq = entry->irq;
660 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
662 resource_size_t phys_addr;
666 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
668 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
669 table_offset &= PCI_MSIX_TABLE_OFFSET;
670 phys_addr = pci_resource_start(dev, bir) + table_offset;
672 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
675 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
676 struct msix_entry *entries, int nvec)
678 struct msi_desc *entry;
681 for (i = 0; i < nvec; i++) {
682 entry = alloc_msi_entry(dev);
688 /* No enough memory. Don't try again */
692 entry->msi_attrib.is_msix = 1;
693 entry->msi_attrib.is_64 = 1;
694 entry->msi_attrib.entry_nr = entries[i].entry;
695 entry->msi_attrib.default_irq = dev->irq;
696 entry->mask_base = base;
697 entry->nvec_used = 1;
699 list_add_tail(&entry->list, &dev->msi_list);
705 static void msix_program_entries(struct pci_dev *dev,
706 struct msix_entry *entries)
708 struct msi_desc *entry;
711 list_for_each_entry(entry, &dev->msi_list, list) {
712 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
713 PCI_MSIX_ENTRY_VECTOR_CTRL;
715 entries[i].vector = entry->irq;
716 entry->masked = readl(entry->mask_base + offset);
717 msix_mask_irq(entry, 1);
723 * msix_capability_init - configure device's MSI-X capability
724 * @dev: pointer to the pci_dev data structure of MSI-X device function
725 * @entries: pointer to an array of struct msix_entry entries
726 * @nvec: number of @entries
728 * Setup the MSI-X capability structure of device function with a
729 * single MSI-X irq. A return of zero indicates the successful setup of
730 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
732 static int msix_capability_init(struct pci_dev *dev,
733 struct msix_entry *entries, int nvec)
739 /* Ensure MSI-X is disabled while it is set up */
740 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
742 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
743 /* Request & Map MSI-X table region */
744 base = msix_map_region(dev, msix_table_size(control));
748 ret = msix_setup_entries(dev, base, entries, nvec);
752 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
757 * Some devices require MSI-X to be enabled before we can touch the
758 * MSI-X registers. We need to mask all the vectors to prevent
759 * interrupts coming in before they're fully set up.
761 msix_clear_and_set_ctrl(dev, 0,
762 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
764 msix_program_entries(dev, entries);
766 ret = populate_msi_sysfs(dev);
770 /* Set MSI-X enabled bits and unmask the function */
771 pci_intx_for_msi(dev, 0);
772 dev->msix_enabled = 1;
774 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
781 * If we had some success, report the number of irqs
782 * we succeeded in setting up.
784 struct msi_desc *entry;
787 list_for_each_entry(entry, &dev->msi_list, list) {
802 * pci_msi_supported - check whether MSI may be enabled on a device
803 * @dev: pointer to the pci_dev data structure of MSI device function
804 * @nvec: how many MSIs have been requested ?
806 * Look at global flags, the device itself, and its parent buses
807 * to determine if MSI/-X are supported for the device. If MSI/-X is
808 * supported return 1, else return 0.
810 static int pci_msi_supported(struct pci_dev *dev, int nvec)
814 /* MSI must be globally enabled and supported by the device */
818 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
822 * You can't ask to have 0 or less MSIs configured.
824 * b) the list manipulation code assumes nvec >= 1.
830 * Any bridge which does NOT route MSI transactions from its
831 * secondary bus to its primary bus must set NO_MSI flag on
832 * the secondary pci_bus.
833 * We expect only arch-specific PCI host bus controller driver
834 * or quirks for specific PCI bridges to be setting NO_MSI.
836 for (bus = dev->bus; bus; bus = bus->parent)
837 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
844 * pci_msi_vec_count - Return the number of MSI vectors a device can send
845 * @dev: device to report about
847 * This function returns the number of MSI vectors a device requested via
848 * Multiple Message Capable register. It returns a negative errno if the
849 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
850 * and returns a power of two, up to a maximum of 2^5 (32), according to the
853 int pci_msi_vec_count(struct pci_dev *dev)
861 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
862 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
866 EXPORT_SYMBOL(pci_msi_vec_count);
868 void pci_msi_shutdown(struct pci_dev *dev)
870 struct msi_desc *desc;
873 if (!pci_msi_enable || !dev || !dev->msi_enabled)
876 BUG_ON(list_empty(&dev->msi_list));
877 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
879 msi_set_enable(dev, 0);
880 pci_intx_for_msi(dev, 1);
881 dev->msi_enabled = 0;
883 /* Return the device with MSI unmasked as initial states */
884 mask = msi_mask(desc->msi_attrib.multi_cap);
885 /* Keep cached state to be restored */
886 __pci_msi_desc_mask_irq(desc, mask, ~mask);
888 /* Restore dev->irq to its default pin-assertion irq */
889 dev->irq = desc->msi_attrib.default_irq;
892 void pci_disable_msi(struct pci_dev *dev)
894 if (!pci_msi_enable || !dev || !dev->msi_enabled)
897 pci_msi_shutdown(dev);
900 EXPORT_SYMBOL(pci_disable_msi);
903 * pci_msix_vec_count - return the number of device's MSI-X table entries
904 * @dev: pointer to the pci_dev data structure of MSI-X device function
905 * This function returns the number of device's MSI-X table entries and
906 * therefore the number of MSI-X vectors device is capable of sending.
907 * It returns a negative errno if the device is not capable of sending MSI-X
910 int pci_msix_vec_count(struct pci_dev *dev)
917 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
918 return msix_table_size(control);
920 EXPORT_SYMBOL(pci_msix_vec_count);
923 * pci_enable_msix - configure device's MSI-X capability structure
924 * @dev: pointer to the pci_dev data structure of MSI-X device function
925 * @entries: pointer to an array of MSI-X entries
926 * @nvec: number of MSI-X irqs requested for allocation by device driver
928 * Setup the MSI-X capability structure of device function with the number
929 * of requested irqs upon its software driver call to request for
930 * MSI-X mode enabled on its hardware device function. A return of zero
931 * indicates the successful configuration of MSI-X capability structure
932 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
933 * Or a return of > 0 indicates that driver request is exceeding the number
934 * of irqs or MSI-X vectors available. Driver should use the returned value to
935 * re-send its request.
937 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
942 if (!pci_msi_supported(dev, nvec))
948 nr_entries = pci_msix_vec_count(dev);
951 if (nvec > nr_entries)
954 /* Check for any invalid entries */
955 for (i = 0; i < nvec; i++) {
956 if (entries[i].entry >= nr_entries)
957 return -EINVAL; /* invalid entry */
958 for (j = i + 1; j < nvec; j++) {
959 if (entries[i].entry == entries[j].entry)
960 return -EINVAL; /* duplicate entry */
963 WARN_ON(!!dev->msix_enabled);
965 /* Check whether driver already requested for MSI irq */
966 if (dev->msi_enabled) {
967 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
970 return msix_capability_init(dev, entries, nvec);
972 EXPORT_SYMBOL(pci_enable_msix);
974 void pci_msix_shutdown(struct pci_dev *dev)
976 struct msi_desc *entry;
978 if (!pci_msi_enable || !dev || !dev->msix_enabled)
981 /* Return the device with MSI-X masked as initial states */
982 list_for_each_entry(entry, &dev->msi_list, list) {
983 /* Keep cached states to be restored */
984 __pci_msix_desc_mask_irq(entry, 1);
987 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
988 pci_intx_for_msi(dev, 1);
989 dev->msix_enabled = 0;
992 void pci_disable_msix(struct pci_dev *dev)
994 if (!pci_msi_enable || !dev || !dev->msix_enabled)
997 pci_msix_shutdown(dev);
1000 EXPORT_SYMBOL(pci_disable_msix);
1002 void pci_no_msi(void)
1008 * pci_msi_enabled - is MSI enabled?
1010 * Returns true if MSI has not been disabled by the command-line option
1013 int pci_msi_enabled(void)
1015 return pci_msi_enable;
1017 EXPORT_SYMBOL(pci_msi_enabled);
1019 void pci_msi_init_pci_dev(struct pci_dev *dev)
1021 INIT_LIST_HEAD(&dev->msi_list);
1023 /* Disable the msi hardware to avoid screaming interrupts
1024 * during boot. This is the power on reset default so
1025 * usually this should be a noop.
1027 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1029 msi_set_enable(dev, 0);
1031 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1033 msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1037 * pci_enable_msi_range - configure device's MSI capability structure
1038 * @dev: device to configure
1039 * @minvec: minimal number of interrupts to configure
1040 * @maxvec: maximum number of interrupts to configure
1042 * This function tries to allocate a maximum possible number of interrupts in a
1043 * range between @minvec and @maxvec. It returns a negative errno if an error
1044 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1045 * and updates the @dev's irq member to the lowest new interrupt number;
1046 * the other interrupt numbers allocated to this device are consecutive.
1048 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1053 if (!pci_msi_supported(dev, minvec))
1056 WARN_ON(!!dev->msi_enabled);
1058 /* Check whether driver already requested MSI-X irqs */
1059 if (dev->msix_enabled) {
1061 "can't enable MSI (MSI-X already enabled)\n");
1065 if (maxvec < minvec)
1068 nvec = pci_msi_vec_count(dev);
1071 else if (nvec < minvec)
1073 else if (nvec > maxvec)
1077 rc = msi_capability_init(dev, nvec);
1080 } else if (rc > 0) {
1089 EXPORT_SYMBOL(pci_enable_msi_range);
1092 * pci_enable_msix_range - configure device's MSI-X capability structure
1093 * @dev: pointer to the pci_dev data structure of MSI-X device function
1094 * @entries: pointer to an array of MSI-X entries
1095 * @minvec: minimum number of MSI-X irqs requested
1096 * @maxvec: maximum number of MSI-X irqs requested
1098 * Setup the MSI-X capability structure of device function with a maximum
1099 * possible number of interrupts in the range between @minvec and @maxvec
1100 * upon its software driver call to request for MSI-X mode enabled on its
1101 * hardware device function. It returns a negative errno if an error occurs.
1102 * If it succeeds, it returns the actual number of interrupts allocated and
1103 * indicates the successful configuration of MSI-X capability structure
1104 * with new allocated MSI-X interrupts.
1106 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1107 int minvec, int maxvec)
1112 if (maxvec < minvec)
1116 rc = pci_enable_msix(dev, entries, nvec);
1119 } else if (rc > 0) {
1128 EXPORT_SYMBOL(pci_enable_msix_range);
1130 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1132 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1133 * @irq_data: Pointer to interrupt data of the MSI interrupt
1134 * @msg: Pointer to the message
1136 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1138 struct msi_desc *desc = irq_data->msi_desc;
1141 * For MSI-X desc->irq is always equal to irq_data->irq. For
1142 * MSI only the first interrupt of MULTI MSI passes the test.
1144 if (desc->irq == irq_data->irq)
1145 __pci_write_msi_msg(desc, msg);
1149 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1150 * @dev: Pointer to the PCI device
1151 * @desc: Pointer to the msi descriptor
1153 * The ID number is only used within the irqdomain.
1155 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1156 struct msi_desc *desc)
1158 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1159 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1160 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1163 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1165 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1169 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1170 * @domain: The interrupt domain to check
1171 * @info: The domain info for verification
1172 * @dev: The device to check
1175 * 0 if the functionality is supported
1176 * 1 if Multi MSI is requested, but the domain does not support it
1177 * -ENOTSUPP otherwise
1179 int pci_msi_domain_check_cap(struct irq_domain *domain,
1180 struct msi_domain_info *info, struct device *dev)
1182 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1184 /* Special handling to support pci_enable_msi_range() */
1185 if (pci_msi_desc_is_multi_msi(desc) &&
1186 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1188 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1194 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1195 struct msi_desc *desc, int error)
1197 /* Special handling to support pci_enable_msi_range() */
1198 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1204 #ifdef GENERIC_MSI_DOMAIN_OPS
1205 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1206 struct msi_desc *desc)
1209 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1213 #define pci_msi_domain_set_desc NULL
1216 static struct msi_domain_ops pci_msi_domain_ops_default = {
1217 .set_desc = pci_msi_domain_set_desc,
1218 .msi_check = pci_msi_domain_check_cap,
1219 .handle_error = pci_msi_domain_handle_error,
1222 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1224 struct msi_domain_ops *ops = info->ops;
1227 info->ops = &pci_msi_domain_ops_default;
1229 if (ops->set_desc == NULL)
1230 ops->set_desc = pci_msi_domain_set_desc;
1231 if (ops->msi_check == NULL)
1232 ops->msi_check = pci_msi_domain_check_cap;
1233 if (ops->handle_error == NULL)
1234 ops->handle_error = pci_msi_domain_handle_error;
1238 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1240 struct irq_chip *chip = info->chip;
1243 if (!chip->irq_write_msi_msg)
1244 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1248 * pci_msi_create_irq_domain - Creat a MSI interrupt domain
1249 * @node: Optional device-tree node of the interrupt controller
1250 * @info: MSI domain info
1251 * @parent: Parent irq domain
1253 * Updates the domain and chip ops and creates a MSI interrupt domain.
1256 * A domain pointer or NULL in case of failure.
1258 struct irq_domain *pci_msi_create_irq_domain(struct device_node *node,
1259 struct msi_domain_info *info,
1260 struct irq_domain *parent)
1262 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1263 pci_msi_domain_update_dom_ops(info);
1264 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1265 pci_msi_domain_update_chip_ops(info);
1267 return msi_create_irq_domain(node, info, parent);
1271 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1272 * @domain: The interrupt domain to allocate from
1273 * @dev: The device for which to allocate
1274 * @nvec: The number of interrupts to allocate
1275 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1278 * A virtual interrupt number or an error code in case of failure
1280 int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1283 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1287 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1288 * @domain: The interrupt domain
1289 * @dev: The device for which to free interrupts
1291 void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1293 msi_domain_free_irqs(domain, &dev->dev);
1297 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1298 * @node: Optional device-tree node of the interrupt controller
1299 * @info: MSI domain info
1300 * @parent: Parent irq domain
1302 * Returns: A domain pointer or NULL in case of failure. If successful
1303 * the default PCI/MSI irqdomain pointer is updated.
1305 struct irq_domain *pci_msi_create_default_irq_domain(struct device_node *node,
1306 struct msi_domain_info *info, struct irq_domain *parent)
1308 struct irq_domain *domain;
1310 mutex_lock(&pci_msi_domain_lock);
1311 if (pci_msi_default_domain) {
1312 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1315 domain = pci_msi_create_irq_domain(node, info, parent);
1316 pci_msi_default_domain = domain;
1318 mutex_unlock(&pci_msi_domain_lock);
1322 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */