2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/irqdomain.h>
19 #include <linux/pm_runtime.h>
22 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23 #define CARDBUS_RESERVE_BUSNR 3
25 static struct resource busn_resource = {
29 .flags = IORESOURCE_BUS,
32 /* Ugh. Need to stop exporting this to modules. */
33 LIST_HEAD(pci_root_buses);
34 EXPORT_SYMBOL(pci_root_buses);
36 static LIST_HEAD(pci_domain_busn_res_list);
38 struct pci_domain_busn_res {
39 struct list_head list;
44 static struct resource *get_pci_domain_busn_res(int domain_nr)
46 struct pci_domain_busn_res *r;
48 list_for_each_entry(r, &pci_domain_busn_res_list, list)
49 if (r->domain_nr == domain_nr)
52 r = kzalloc(sizeof(*r), GFP_KERNEL);
56 r->domain_nr = domain_nr;
59 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
61 list_add_tail(&r->list, &pci_domain_busn_res_list);
66 static int find_anything(struct device *dev, void *data)
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
74 * is no device to be found on the pci_bus_type.
76 int no_pci_devices(void)
81 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
82 no_devices = (dev == NULL);
86 EXPORT_SYMBOL(no_pci_devices);
91 static void release_pcibus_dev(struct device *dev)
93 struct pci_bus *pci_bus = to_pci_bus(dev);
95 put_device(pci_bus->bridge);
96 pci_bus_remove_resources(pci_bus);
97 pci_release_bus_of_node(pci_bus);
101 static struct class pcibus_class = {
103 .dev_release = &release_pcibus_dev,
104 .dev_groups = pcibus_groups,
107 static int __init pcibus_class_init(void)
109 return class_register(&pcibus_class);
111 postcore_initcall(pcibus_class_init);
113 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
115 u64 size = mask & maxbase; /* Find the significant bits */
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size = (size & ~(size-1)) - 1;
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base == maxbase && ((base | size) & mask) != mask)
131 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
158 /* mem unknown type treated as 32-bit BAR */
164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
178 u32 l = 0, sz = 0, mask;
179 u64 l64, sz64, mask64;
181 struct pci_bus_region region, inverted_region;
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
194 res->name = pci_name(dev);
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 if (sz == 0xffffffff)
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = PCI_ROM_ADDRESS_MASK;
237 if (res->flags & IORESOURCE_MEM_64) {
238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
245 mask64 |= ((u64)~0 << 32);
248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
254 sz64 = pci_size(l64, sz64, mask64);
256 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
261 if (res->flags & IORESOURCE_MEM_64) {
262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
267 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
273 /* Above 32-bit boundary; try to reallocate */
274 res->flags |= IORESOURCE_UNSET;
277 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
284 region.end = l64 + sz64;
286 pcibios_bus_to_resource(dev->bus, res, ®ion);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
295 * resource_to_bus(bus_to_resource(A)) == A
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
300 if (inverted_region.start != region.start) {
301 res->flags |= IORESOURCE_UNSET;
303 res->end = region.end - region.start;
304 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
315 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
320 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322 unsigned int pos, reg;
324 if (dev->non_compliant_bars)
327 for (pos = 0; pos < howmany; pos++) {
328 struct resource *res = &dev->resource[pos];
329 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
330 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
334 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
335 dev->rom_base_reg = rom;
336 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
337 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
338 __pci_read_base(dev, pci_bar_mem32, res, rom);
342 static void pci_read_bridge_io(struct pci_bus *child)
344 struct pci_dev *dev = child->self;
345 u8 io_base_lo, io_limit_lo;
346 unsigned long io_mask, io_granularity, base, limit;
347 struct pci_bus_region region;
348 struct resource *res;
350 io_mask = PCI_IO_RANGE_MASK;
351 io_granularity = 0x1000;
352 if (dev->io_window_1k) {
353 /* Support 1K I/O space granularity */
354 io_mask = PCI_IO_1K_RANGE_MASK;
355 io_granularity = 0x400;
358 res = child->resource[0];
359 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
360 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
361 base = (io_base_lo & io_mask) << 8;
362 limit = (io_limit_lo & io_mask) << 8;
364 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
365 u16 io_base_hi, io_limit_hi;
367 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
368 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
369 base |= ((unsigned long) io_base_hi << 16);
370 limit |= ((unsigned long) io_limit_hi << 16);
374 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
376 region.end = limit + io_granularity - 1;
377 pcibios_bus_to_resource(dev->bus, res, ®ion);
378 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
382 static void pci_read_bridge_mmio(struct pci_bus *child)
384 struct pci_dev *dev = child->self;
385 u16 mem_base_lo, mem_limit_lo;
386 unsigned long base, limit;
387 struct pci_bus_region region;
388 struct resource *res;
390 res = child->resource[1];
391 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
392 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
393 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
396 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
398 region.end = limit + 0xfffff;
399 pcibios_bus_to_resource(dev->bus, res, ®ion);
400 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
404 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
406 struct pci_dev *dev = child->self;
407 u16 mem_base_lo, mem_limit_lo;
409 pci_bus_addr_t base, limit;
410 struct pci_bus_region region;
411 struct resource *res;
413 res = child->resource[2];
414 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
415 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
416 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
417 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
419 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
420 u32 mem_base_hi, mem_limit_hi;
422 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
423 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
426 * Some bridges set the base > limit by default, and some
427 * (broken) BIOSes do not initialize them. If we find
428 * this, just assume they are not being used.
430 if (mem_base_hi <= mem_limit_hi) {
431 base64 |= (u64) mem_base_hi << 32;
432 limit64 |= (u64) mem_limit_hi << 32;
436 base = (pci_bus_addr_t) base64;
437 limit = (pci_bus_addr_t) limit64;
439 if (base != base64) {
440 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
441 (unsigned long long) base64);
446 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
447 IORESOURCE_MEM | IORESOURCE_PREFETCH;
448 if (res->flags & PCI_PREF_RANGE_TYPE_64)
449 res->flags |= IORESOURCE_MEM_64;
451 region.end = limit + 0xfffff;
452 pcibios_bus_to_resource(dev->bus, res, ®ion);
453 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
457 void pci_read_bridge_bases(struct pci_bus *child)
459 struct pci_dev *dev = child->self;
460 struct resource *res;
463 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
466 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
468 dev->transparent ? " (subtractive decode)" : "");
470 pci_bus_remove_resources(child);
471 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
472 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
474 pci_read_bridge_io(child);
475 pci_read_bridge_mmio(child);
476 pci_read_bridge_mmio_pref(child);
478 if (dev->transparent) {
479 pci_bus_for_each_resource(child->parent, res, i) {
480 if (res && res->flags) {
481 pci_bus_add_resource(child, res,
482 PCI_SUBTRACTIVE_DECODE);
483 dev_printk(KERN_DEBUG, &dev->dev,
484 " bridge window %pR (subtractive decode)\n",
491 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
495 b = kzalloc(sizeof(*b), GFP_KERNEL);
499 INIT_LIST_HEAD(&b->node);
500 INIT_LIST_HEAD(&b->children);
501 INIT_LIST_HEAD(&b->devices);
502 INIT_LIST_HEAD(&b->slots);
503 INIT_LIST_HEAD(&b->resources);
504 b->max_bus_speed = PCI_SPEED_UNKNOWN;
505 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
506 #ifdef CONFIG_PCI_DOMAINS_GENERIC
508 b->domain_nr = parent->domain_nr;
513 static void pci_release_host_bridge_dev(struct device *dev)
515 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
517 if (bridge->release_fn)
518 bridge->release_fn(bridge);
520 pci_free_resource_list(&bridge->windows);
525 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
527 struct pci_host_bridge *bridge;
529 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
533 INIT_LIST_HEAD(&bridge->windows);
537 EXPORT_SYMBOL(pci_alloc_host_bridge);
539 static const unsigned char pcix_bus_speed[] = {
540 PCI_SPEED_UNKNOWN, /* 0 */
541 PCI_SPEED_66MHz_PCIX, /* 1 */
542 PCI_SPEED_100MHz_PCIX, /* 2 */
543 PCI_SPEED_133MHz_PCIX, /* 3 */
544 PCI_SPEED_UNKNOWN, /* 4 */
545 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
546 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
547 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
548 PCI_SPEED_UNKNOWN, /* 8 */
549 PCI_SPEED_66MHz_PCIX_266, /* 9 */
550 PCI_SPEED_100MHz_PCIX_266, /* A */
551 PCI_SPEED_133MHz_PCIX_266, /* B */
552 PCI_SPEED_UNKNOWN, /* C */
553 PCI_SPEED_66MHz_PCIX_533, /* D */
554 PCI_SPEED_100MHz_PCIX_533, /* E */
555 PCI_SPEED_133MHz_PCIX_533 /* F */
558 const unsigned char pcie_link_speed[] = {
559 PCI_SPEED_UNKNOWN, /* 0 */
560 PCIE_SPEED_2_5GT, /* 1 */
561 PCIE_SPEED_5_0GT, /* 2 */
562 PCIE_SPEED_8_0GT, /* 3 */
563 PCI_SPEED_UNKNOWN, /* 4 */
564 PCI_SPEED_UNKNOWN, /* 5 */
565 PCI_SPEED_UNKNOWN, /* 6 */
566 PCI_SPEED_UNKNOWN, /* 7 */
567 PCI_SPEED_UNKNOWN, /* 8 */
568 PCI_SPEED_UNKNOWN, /* 9 */
569 PCI_SPEED_UNKNOWN, /* A */
570 PCI_SPEED_UNKNOWN, /* B */
571 PCI_SPEED_UNKNOWN, /* C */
572 PCI_SPEED_UNKNOWN, /* D */
573 PCI_SPEED_UNKNOWN, /* E */
574 PCI_SPEED_UNKNOWN /* F */
577 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
579 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
581 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
583 static unsigned char agp_speeds[] = {
591 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
597 else if (agpstat & 2)
599 else if (agpstat & 1)
611 return agp_speeds[index];
614 static void pci_set_bus_speed(struct pci_bus *bus)
616 struct pci_dev *bridge = bus->self;
619 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
621 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
625 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
626 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
628 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
629 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
632 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
635 enum pci_bus_speed max;
637 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
640 if (status & PCI_X_SSTATUS_533MHZ) {
641 max = PCI_SPEED_133MHz_PCIX_533;
642 } else if (status & PCI_X_SSTATUS_266MHZ) {
643 max = PCI_SPEED_133MHz_PCIX_266;
644 } else if (status & PCI_X_SSTATUS_133MHZ) {
645 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
646 max = PCI_SPEED_133MHz_PCIX_ECC;
648 max = PCI_SPEED_133MHz_PCIX;
650 max = PCI_SPEED_66MHz_PCIX;
653 bus->max_bus_speed = max;
654 bus->cur_bus_speed = pcix_bus_speed[
655 (status & PCI_X_SSTATUS_FREQ) >> 6];
660 if (pci_is_pcie(bridge)) {
664 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
665 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
667 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
668 pcie_update_link_speed(bus, linksta);
672 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
674 struct irq_domain *d;
677 * Any firmware interface that can resolve the msi_domain
678 * should be called from here.
680 d = pci_host_bridge_of_msi_domain(bus);
682 d = pci_host_bridge_acpi_msi_domain(bus);
684 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
686 * If no IRQ domain was found via the OF tree, try looking it up
687 * directly through the fwnode_handle.
690 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
693 d = irq_find_matching_fwnode(fwnode,
701 static void pci_set_bus_msi_domain(struct pci_bus *bus)
703 struct irq_domain *d;
707 * The bus can be a root bus, a subordinate bus, or a virtual bus
708 * created by an SR-IOV device. Walk up to the first bridge device
709 * found or derive the domain from the host bridge.
711 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
713 d = dev_get_msi_domain(&b->self->dev);
717 d = pci_host_bridge_msi_domain(b);
719 dev_set_msi_domain(&bus->dev, d);
722 int pci_register_host_bridge(struct pci_host_bridge *bridge)
724 struct device *parent = bridge->dev.parent;
725 struct resource_entry *window, *n;
726 struct pci_bus *bus, *b;
727 resource_size_t offset;
728 LIST_HEAD(resources);
729 struct resource *res;
734 bus = pci_alloc_bus(NULL);
740 /* temporarily move resources off the list */
741 list_splice_init(&bridge->windows, &resources);
742 bus->sysdata = bridge->sysdata;
743 bus->msi = bridge->msi;
744 bus->ops = bridge->ops;
745 bus->number = bus->busn_res.start = bridge->busnr;
746 #ifdef CONFIG_PCI_DOMAINS_GENERIC
747 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
750 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
752 /* If we already got to this bus through a different bridge, ignore it */
753 dev_dbg(&b->dev, "bus already known\n");
758 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
761 err = pcibios_root_bridge_prepare(bridge);
765 err = device_register(&bridge->dev);
767 put_device(&bridge->dev);
769 bus->bridge = get_device(&bridge->dev);
770 device_enable_async_suspend(bus->bridge);
771 pci_set_bus_of_node(bus);
772 pci_set_bus_msi_domain(bus);
775 set_dev_node(bus->bridge, pcibus_to_node(bus));
777 bus->dev.class = &pcibus_class;
778 bus->dev.parent = bus->bridge;
780 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
781 name = dev_name(&bus->dev);
783 err = device_register(&bus->dev);
787 pcibios_add_bus(bus);
789 /* Create legacy_io and legacy_mem files for this bus */
790 pci_create_legacy_files(bus);
793 dev_info(parent, "PCI host bridge to bus %s\n", name);
795 pr_info("PCI host bridge to bus %s\n", name);
797 /* Add initial resources to the bus */
798 resource_list_for_each_entry_safe(window, n, &resources) {
799 list_move_tail(&window->node, &bridge->windows);
800 offset = window->offset;
803 if (res->flags & IORESOURCE_BUS)
804 pci_bus_insert_busn_res(bus, bus->number, res->end);
806 pci_bus_add_resource(bus, res, 0);
809 if (resource_type(res) == IORESOURCE_IO)
810 fmt = " (bus address [%#06llx-%#06llx])";
812 fmt = " (bus address [%#010llx-%#010llx])";
814 snprintf(addr, sizeof(addr), fmt,
815 (unsigned long long)(res->start - offset),
816 (unsigned long long)(res->end - offset));
820 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
823 down_write(&pci_bus_sem);
824 list_add_tail(&bus->node, &pci_root_buses);
825 up_write(&pci_bus_sem);
830 put_device(&bridge->dev);
831 device_unregister(&bridge->dev);
837 EXPORT_SYMBOL(pci_register_host_bridge);
839 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
840 struct pci_dev *bridge, int busnr)
842 struct pci_bus *child;
847 * Allocate a new bus, and inherit stuff from the parent..
849 child = pci_alloc_bus(parent);
853 child->parent = parent;
854 child->ops = parent->ops;
855 child->msi = parent->msi;
856 child->sysdata = parent->sysdata;
857 child->bus_flags = parent->bus_flags;
859 /* initialize some portions of the bus device, but don't register it
860 * now as the parent is not properly set up yet.
862 child->dev.class = &pcibus_class;
863 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
866 * Set up the primary, secondary and subordinate
869 child->number = child->busn_res.start = busnr;
870 child->primary = parent->busn_res.start;
871 child->busn_res.end = 0xff;
874 child->dev.parent = parent->bridge;
878 child->self = bridge;
879 child->bridge = get_device(&bridge->dev);
880 child->dev.parent = child->bridge;
881 pci_set_bus_of_node(child);
882 pci_set_bus_speed(child);
884 /* Set up default resource pointers and names.. */
885 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
886 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
887 child->resource[i]->name = child->name;
889 bridge->subordinate = child;
892 pci_set_bus_msi_domain(child);
893 ret = device_register(&child->dev);
896 pcibios_add_bus(child);
898 if (child->ops->add_bus) {
899 ret = child->ops->add_bus(child);
900 if (WARN_ON(ret < 0))
901 dev_err(&child->dev, "failed to add bus: %d\n", ret);
904 /* Create legacy_io and legacy_mem files for this bus */
905 pci_create_legacy_files(child);
910 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
913 struct pci_bus *child;
915 child = pci_alloc_child_bus(parent, dev, busnr);
917 down_write(&pci_bus_sem);
918 list_add_tail(&child->node, &parent->children);
919 up_write(&pci_bus_sem);
923 EXPORT_SYMBOL(pci_add_new_bus);
925 static void pci_enable_crs(struct pci_dev *pdev)
929 /* Enable CRS Software Visibility if supported */
930 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
931 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
932 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
933 PCI_EXP_RTCTL_CRSSVE);
937 * If it's a bridge, configure it and scan the bus behind it.
938 * For CardBus bridges, we don't scan behind as the devices will
939 * be handled by the bridge driver itself.
941 * We need to process bridges in two passes -- first we scan those
942 * already configured by the BIOS and after we are done with all of
943 * them, we proceed to assigning numbers to the remaining buses in
944 * order to avoid overlaps between old and new bus numbers.
946 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
948 struct pci_bus *child;
949 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
952 u8 primary, secondary, subordinate;
956 * Make sure the bridge is powered on to be able to access config
957 * space of devices below it.
959 pm_runtime_get_sync(&dev->dev);
961 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
962 primary = buses & 0xFF;
963 secondary = (buses >> 8) & 0xFF;
964 subordinate = (buses >> 16) & 0xFF;
966 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
967 secondary, subordinate, pass);
969 if (!primary && (primary != bus->number) && secondary && subordinate) {
970 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
971 primary = bus->number;
974 /* Check if setup is sensible at all */
976 (primary != bus->number || secondary <= bus->number ||
977 secondary > subordinate)) {
978 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
979 secondary, subordinate);
983 /* Disable MasterAbortMode during probing to avoid reporting
984 of bus errors (in some architectures) */
985 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
986 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
987 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
991 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
992 !is_cardbus && !broken) {
995 * Bus already configured by firmware, process it in the first
996 * pass and just note the configuration.
1002 * The bus might already exist for two reasons: Either we are
1003 * rescanning the bus or the bus is reachable through more than
1004 * one bridge. The second case can happen with the i450NX
1007 child = pci_find_bus(pci_domain_nr(bus), secondary);
1009 child = pci_add_new_bus(bus, dev, secondary);
1012 child->primary = primary;
1013 pci_bus_insert_busn_res(child, secondary, subordinate);
1014 child->bridge_ctl = bctl;
1017 cmax = pci_scan_child_bus(child);
1018 if (cmax > subordinate)
1019 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
1021 /* subordinate should equal child->busn_res.end */
1022 if (subordinate > max)
1026 * We need to assign a number to this bus which we always
1027 * do in the second pass.
1030 if (pcibios_assign_all_busses() || broken || is_cardbus)
1031 /* Temporarily disable forwarding of the
1032 configuration cycles on all bridges in
1033 this bus segment to avoid possible
1034 conflicts in the second pass between two
1035 bridges programmed with overlapping
1037 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1043 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1045 /* Prevent assigning a bus number that already exists.
1046 * This can happen when a bridge is hot-plugged, so in
1047 * this case we only re-scan this bus. */
1048 child = pci_find_bus(pci_domain_nr(bus), max+1);
1050 child = pci_add_new_bus(bus, dev, max+1);
1053 pci_bus_insert_busn_res(child, max+1, 0xff);
1056 buses = (buses & 0xff000000)
1057 | ((unsigned int)(child->primary) << 0)
1058 | ((unsigned int)(child->busn_res.start) << 8)
1059 | ((unsigned int)(child->busn_res.end) << 16);
1062 * yenta.c forces a secondary latency timer of 176.
1063 * Copy that behaviour here.
1066 buses &= ~0xff000000;
1067 buses |= CARDBUS_LATENCY_TIMER << 24;
1071 * We need to blast all three values with a single write.
1073 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1076 child->bridge_ctl = bctl;
1077 max = pci_scan_child_bus(child);
1080 * For CardBus bridges, we leave 4 bus numbers
1081 * as cards with a PCI-to-PCI bridge can be
1084 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1085 struct pci_bus *parent = bus;
1086 if (pci_find_bus(pci_domain_nr(bus),
1089 while (parent->parent) {
1090 if ((!pcibios_assign_all_busses()) &&
1091 (parent->busn_res.end > max) &&
1092 (parent->busn_res.end <= max+i)) {
1095 parent = parent->parent;
1099 * Often, there are two cardbus bridges
1100 * -- try to leave one valid bus number
1110 * Set the subordinate bus number to its real value.
1112 pci_bus_update_busn_res_end(child, max);
1113 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1116 sprintf(child->name,
1117 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1118 pci_domain_nr(bus), child->number);
1120 /* Has only triggered on CardBus, fixup is in yenta_socket */
1121 while (bus->parent) {
1122 if ((child->busn_res.end > bus->busn_res.end) ||
1123 (child->number > bus->busn_res.end) ||
1124 (child->number < bus->number) ||
1125 (child->busn_res.end < bus->number)) {
1126 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1128 (bus->number > child->busn_res.end &&
1129 bus->busn_res.end < child->number) ?
1130 "wholly" : "partially",
1131 bus->self->transparent ? " transparent" : "",
1132 dev_name(&bus->dev),
1139 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1141 pm_runtime_put(&dev->dev);
1145 EXPORT_SYMBOL(pci_scan_bridge);
1148 * Read interrupt line and base address registers.
1149 * The architecture-dependent code can tweak these, of course.
1151 static void pci_read_irq(struct pci_dev *dev)
1155 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1158 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1162 void set_pcie_port_type(struct pci_dev *pdev)
1167 struct pci_dev *parent;
1169 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1173 pdev->pcie_cap = pos;
1174 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1175 pdev->pcie_flags_reg = reg16;
1176 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1177 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1180 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1181 * of a Link. No PCIe component has two Links. Two Links are
1182 * connected by a Switch that has a Port on each Link and internal
1183 * logic to connect the two Ports.
1185 type = pci_pcie_type(pdev);
1186 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1187 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1188 pdev->has_secondary_link = 1;
1189 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1190 type == PCI_EXP_TYPE_DOWNSTREAM) {
1191 parent = pci_upstream_bridge(pdev);
1194 * Usually there's an upstream device (Root Port or Switch
1195 * Downstream Port), but we can't assume one exists.
1197 if (parent && !parent->has_secondary_link)
1198 pdev->has_secondary_link = 1;
1202 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1206 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1207 if (reg32 & PCI_EXP_SLTCAP_HPC)
1208 pdev->is_hotplug_bridge = 1;
1211 static void set_pcie_thunderbolt(struct pci_dev *dev)
1216 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1217 PCI_EXT_CAP_ID_VNDR))) {
1218 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1220 /* Is the device part of a Thunderbolt controller? */
1221 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1222 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1223 dev->is_thunderbolt = 1;
1230 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1233 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1234 * when forwarding a type1 configuration request the bridge must check that
1235 * the extended register address field is zero. The bridge is not permitted
1236 * to forward the transactions and must handle it as an Unsupported Request.
1237 * Some bridges do not follow this rule and simply drop the extended register
1238 * bits, resulting in the standard config space being aliased, every 256
1239 * bytes across the entire configuration space. Test for this condition by
1240 * comparing the first dword of each potential alias to the vendor/device ID.
1242 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1243 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1245 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1247 #ifdef CONFIG_PCI_QUIRKS
1251 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1253 for (pos = PCI_CFG_SPACE_SIZE;
1254 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1255 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1267 * pci_cfg_space_size - get the configuration space size of the PCI device.
1270 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1271 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1272 * access it. Maybe we don't have a way to generate extended config space
1273 * accesses, or the device is behind a reverse Express bridge. So we try
1274 * reading the dword at 0x100 which must either be 0 or a valid extended
1275 * capability header.
1277 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1280 int pos = PCI_CFG_SPACE_SIZE;
1282 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1283 return PCI_CFG_SPACE_SIZE;
1284 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1285 return PCI_CFG_SPACE_SIZE;
1287 return PCI_CFG_SPACE_EXP_SIZE;
1290 int pci_cfg_space_size(struct pci_dev *dev)
1296 class = dev->class >> 8;
1297 if (class == PCI_CLASS_BRIDGE_HOST)
1298 return pci_cfg_space_size_ext(dev);
1300 if (pci_is_pcie(dev))
1301 return pci_cfg_space_size_ext(dev);
1303 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1305 return PCI_CFG_SPACE_SIZE;
1307 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1308 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1309 return pci_cfg_space_size_ext(dev);
1311 return PCI_CFG_SPACE_SIZE;
1314 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1316 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1319 * Disable the MSI hardware to avoid screaming interrupts
1320 * during boot. This is the power on reset default so
1321 * usually this should be a noop.
1323 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1325 pci_msi_set_enable(dev, 0);
1327 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1329 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1333 * pci_setup_device - fill in class and map information of a device
1334 * @dev: the device structure to fill
1336 * Initialize the device structure with information about the device's
1337 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1338 * Called at initialisation of the PCI subsystem and by CardBus services.
1339 * Returns 0 on success and negative if unknown type of device (not normal,
1340 * bridge or CardBus).
1342 int pci_setup_device(struct pci_dev *dev)
1348 struct pci_bus_region region;
1349 struct resource *res;
1351 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1354 dev->sysdata = dev->bus->sysdata;
1355 dev->dev.parent = dev->bus->bridge;
1356 dev->dev.bus = &pci_bus_type;
1357 dev->hdr_type = hdr_type & 0x7f;
1358 dev->multifunction = !!(hdr_type & 0x80);
1359 dev->error_state = pci_channel_io_normal;
1360 set_pcie_port_type(dev);
1362 pci_dev_assign_slot(dev);
1363 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1364 set this higher, assuming the system even supports it. */
1365 dev->dma_mask = 0xffffffff;
1367 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1368 dev->bus->number, PCI_SLOT(dev->devfn),
1369 PCI_FUNC(dev->devfn));
1371 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1372 dev->revision = class & 0xff;
1373 dev->class = class >> 8; /* upper 3 bytes */
1375 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1376 dev->vendor, dev->device, dev->hdr_type, dev->class);
1378 /* need to have dev->class ready */
1379 dev->cfg_size = pci_cfg_space_size(dev);
1381 /* need to have dev->cfg_size ready */
1382 set_pcie_thunderbolt(dev);
1384 /* "Unknown power state" */
1385 dev->current_state = PCI_UNKNOWN;
1387 /* Early fixups, before probing the BARs */
1388 pci_fixup_device(pci_fixup_early, dev);
1389 /* device class may be changed after fixup */
1390 class = dev->class >> 8;
1392 if (dev->non_compliant_bars) {
1393 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1394 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1395 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1396 cmd &= ~PCI_COMMAND_IO;
1397 cmd &= ~PCI_COMMAND_MEMORY;
1398 pci_write_config_word(dev, PCI_COMMAND, cmd);
1402 switch (dev->hdr_type) { /* header type */
1403 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1404 if (class == PCI_CLASS_BRIDGE_PCI)
1407 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1408 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1409 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1412 * Do the ugly legacy mode stuff here rather than broken chip
1413 * quirk code. Legacy mode ATA controllers have fixed
1414 * addresses. These are not always echoed in BAR0-3, and
1415 * BAR0-3 in a few cases contain junk!
1417 if (class == PCI_CLASS_STORAGE_IDE) {
1419 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1420 if ((progif & 1) == 0) {
1421 region.start = 0x1F0;
1423 res = &dev->resource[0];
1424 res->flags = LEGACY_IO_RESOURCE;
1425 pcibios_bus_to_resource(dev->bus, res, ®ion);
1426 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1428 region.start = 0x3F6;
1430 res = &dev->resource[1];
1431 res->flags = LEGACY_IO_RESOURCE;
1432 pcibios_bus_to_resource(dev->bus, res, ®ion);
1433 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1436 if ((progif & 4) == 0) {
1437 region.start = 0x170;
1439 res = &dev->resource[2];
1440 res->flags = LEGACY_IO_RESOURCE;
1441 pcibios_bus_to_resource(dev->bus, res, ®ion);
1442 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1444 region.start = 0x376;
1446 res = &dev->resource[3];
1447 res->flags = LEGACY_IO_RESOURCE;
1448 pcibios_bus_to_resource(dev->bus, res, ®ion);
1449 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1455 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1456 if (class != PCI_CLASS_BRIDGE_PCI)
1458 /* The PCI-to-PCI bridge spec requires that subtractive
1459 decoding (i.e. transparent) bridge must have programming
1460 interface code of 0x01. */
1462 dev->transparent = ((dev->class & 0xff) == 1);
1463 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1464 set_pcie_hotplug_bridge(dev);
1465 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1467 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1468 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1472 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1473 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1476 pci_read_bases(dev, 1, 0);
1477 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1478 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1481 default: /* unknown header */
1482 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1487 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1488 dev->class, dev->hdr_type);
1489 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1492 /* We found a fine healthy device, go go go... */
1496 static void pci_configure_mps(struct pci_dev *dev)
1498 struct pci_dev *bridge = pci_upstream_bridge(dev);
1501 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1504 mps = pcie_get_mps(dev);
1505 p_mps = pcie_get_mps(bridge);
1510 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1511 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1512 mps, pci_name(bridge), p_mps);
1517 * Fancier MPS configuration is done later by
1518 * pcie_bus_configure_settings()
1520 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1523 rc = pcie_set_mps(dev, p_mps);
1525 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1530 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1531 p_mps, mps, 128 << dev->pcie_mpss);
1534 static struct hpp_type0 pci_default_type0 = {
1536 .cache_line_size = 8,
1537 .latency_timer = 0x40,
1542 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1544 u16 pci_cmd, pci_bctl;
1547 hpp = &pci_default_type0;
1549 if (hpp->revision > 1) {
1551 "PCI settings rev %d not supported; using defaults\n",
1553 hpp = &pci_default_type0;
1556 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1557 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1558 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1559 if (hpp->enable_serr)
1560 pci_cmd |= PCI_COMMAND_SERR;
1561 if (hpp->enable_perr)
1562 pci_cmd |= PCI_COMMAND_PARITY;
1563 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1565 /* Program bridge control value */
1566 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1567 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1568 hpp->latency_timer);
1569 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1570 if (hpp->enable_serr)
1571 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1572 if (hpp->enable_perr)
1573 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1574 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1578 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1585 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1589 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1592 static bool pcie_root_rcb_set(struct pci_dev *dev)
1594 struct pci_dev *rp = pcie_find_root_port(dev);
1600 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1601 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1607 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1615 if (!pci_is_pcie(dev))
1618 if (hpp->revision > 1) {
1619 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1625 * Don't allow _HPX to change MPS or MRRS settings. We manage
1626 * those to make sure they're consistent with the rest of the
1629 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1630 PCI_EXP_DEVCTL_READRQ;
1631 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1632 PCI_EXP_DEVCTL_READRQ);
1634 /* Initialize Device Control Register */
1635 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1636 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1638 /* Initialize Link Control Register */
1639 if (pcie_cap_has_lnkctl(dev)) {
1642 * If the Root Port supports Read Completion Boundary of
1643 * 128, set RCB to 128. Otherwise, clear it.
1645 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1646 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1647 if (pcie_root_rcb_set(dev))
1648 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1650 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1651 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1654 /* Find Advanced Error Reporting Enhanced Capability */
1655 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1659 /* Initialize Uncorrectable Error Mask Register */
1660 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1661 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1662 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1664 /* Initialize Uncorrectable Error Severity Register */
1665 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1666 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1667 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1669 /* Initialize Correctable Error Mask Register */
1670 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1671 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1672 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1674 /* Initialize Advanced Error Capabilities and Control Register */
1675 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1676 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1677 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1680 * FIXME: The following two registers are not supported yet.
1682 * o Secondary Uncorrectable Error Severity Register
1683 * o Secondary Uncorrectable Error Mask Register
1687 static void pci_configure_extended_tags(struct pci_dev *dev)
1692 if (!pci_is_pcie(dev))
1695 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &dev_cap);
1699 if (dev_cap & PCI_EXP_DEVCAP_EXT_TAG)
1700 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1701 PCI_EXP_DEVCTL_EXT_TAG);
1704 static void pci_configure_device(struct pci_dev *dev)
1706 struct hotplug_params hpp;
1709 pci_configure_mps(dev);
1710 pci_configure_extended_tags(dev);
1712 memset(&hpp, 0, sizeof(hpp));
1713 ret = pci_get_hp_params(dev, &hpp);
1717 program_hpp_type2(dev, hpp.t2);
1718 program_hpp_type1(dev, hpp.t1);
1719 program_hpp_type0(dev, hpp.t0);
1722 static void pci_release_capabilities(struct pci_dev *dev)
1724 pci_vpd_release(dev);
1725 pci_iov_release(dev);
1726 pci_free_cap_save_buffers(dev);
1730 * pci_release_dev - free a pci device structure when all users of it are finished.
1731 * @dev: device that's been disconnected
1733 * Will be called only by the device core when all users of this pci device are
1736 static void pci_release_dev(struct device *dev)
1738 struct pci_dev *pci_dev;
1740 pci_dev = to_pci_dev(dev);
1741 pci_release_capabilities(pci_dev);
1742 pci_release_of_node(pci_dev);
1743 pcibios_release_device(pci_dev);
1744 pci_bus_put(pci_dev->bus);
1745 kfree(pci_dev->driver_override);
1746 kfree(pci_dev->dma_alias_mask);
1750 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1752 struct pci_dev *dev;
1754 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1758 INIT_LIST_HEAD(&dev->bus_list);
1759 dev->dev.type = &pci_dev_type;
1760 dev->bus = pci_bus_get(bus);
1764 EXPORT_SYMBOL(pci_alloc_dev);
1766 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1771 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1774 /* some broken boards return 0 or ~0 if a slot is empty: */
1775 if (*l == 0xffffffff || *l == 0x00000000 ||
1776 *l == 0x0000ffff || *l == 0xffff0000)
1780 * Configuration Request Retry Status. Some root ports return the
1781 * actual device ID instead of the synthetic ID (0xFFFF) required
1782 * by the PCIe spec. Ignore the device ID and only check for
1785 while ((*l & 0xffff) == 0x0001) {
1791 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1793 /* Card hasn't responded in 60 seconds? Must be stuck. */
1794 if (delay > crs_timeout) {
1795 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1796 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1804 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1807 * Read the config data for a PCI device, sanity-check it
1808 * and fill in the dev structure...
1810 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1812 struct pci_dev *dev;
1815 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1818 dev = pci_alloc_dev(bus);
1823 dev->vendor = l & 0xffff;
1824 dev->device = (l >> 16) & 0xffff;
1826 pci_set_of_node(dev);
1828 if (pci_setup_device(dev)) {
1829 pci_bus_put(dev->bus);
1837 static void pci_init_capabilities(struct pci_dev *dev)
1839 /* Enhanced Allocation */
1842 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1843 pci_msi_setup_pci_dev(dev);
1845 /* Buffers for saving PCIe and PCI-X capabilities */
1846 pci_allocate_cap_save_buffers(dev);
1848 /* Power Management */
1851 /* Vital Product Data */
1854 /* Alternative Routing-ID Forwarding */
1855 pci_configure_ari(dev);
1857 /* Single Root I/O Virtualization */
1860 /* Address Translation Services */
1863 /* Enable ACS P2P upstream forwarding */
1864 pci_enable_acs(dev);
1866 /* Precision Time Measurement */
1869 /* Advanced Error Reporting */
1874 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1875 * devices. Firmware interfaces that can select the MSI domain on a
1876 * per-device basis should be called from here.
1878 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1880 struct irq_domain *d;
1883 * If a domain has been set through the pcibios_add_device
1884 * callback, then this is the one (platform code knows best).
1886 d = dev_get_msi_domain(&dev->dev);
1891 * Let's see if we have a firmware interface able to provide
1894 d = pci_msi_get_device_domain(dev);
1901 static void pci_set_msi_domain(struct pci_dev *dev)
1903 struct irq_domain *d;
1906 * If the platform or firmware interfaces cannot supply a
1907 * device-specific MSI domain, then inherit the default domain
1908 * from the host bridge itself.
1910 d = pci_dev_msi_domain(dev);
1912 d = dev_get_msi_domain(&dev->bus->dev);
1914 dev_set_msi_domain(&dev->dev, d);
1918 * pci_dma_configure - Setup DMA configuration
1919 * @dev: ptr to pci_dev struct of the PCI device
1921 * Function to update PCI devices's DMA configuration using the same
1922 * info from the OF node or ACPI node of host bridge's parent (if any).
1924 static void pci_dma_configure(struct pci_dev *dev)
1926 struct device *bridge = pci_get_host_bridge_device(dev);
1928 if (IS_ENABLED(CONFIG_OF) &&
1929 bridge->parent && bridge->parent->of_node) {
1930 of_dma_configure(&dev->dev, bridge->parent->of_node);
1931 } else if (has_acpi_companion(bridge)) {
1932 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1933 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1935 if (attr == DEV_DMA_NOT_SUPPORTED)
1936 dev_warn(&dev->dev, "DMA not supported.\n");
1938 acpi_dma_configure(&dev->dev, attr);
1941 pci_put_host_bridge_device(bridge);
1944 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1948 pci_configure_device(dev);
1950 device_initialize(&dev->dev);
1951 dev->dev.release = pci_release_dev;
1953 set_dev_node(&dev->dev, pcibus_to_node(bus));
1954 dev->dev.dma_mask = &dev->dma_mask;
1955 dev->dev.dma_parms = &dev->dma_parms;
1956 dev->dev.coherent_dma_mask = 0xffffffffull;
1957 pci_dma_configure(dev);
1959 pci_set_dma_max_seg_size(dev, 65536);
1960 pci_set_dma_seg_boundary(dev, 0xffffffff);
1962 /* Fix up broken headers */
1963 pci_fixup_device(pci_fixup_header, dev);
1965 /* moved out from quirk header fixup code */
1966 pci_reassigndev_resource_alignment(dev);
1968 /* Clear the state_saved flag. */
1969 dev->state_saved = false;
1971 /* Initialize various capabilities */
1972 pci_init_capabilities(dev);
1975 * Add the device to our list of discovered devices
1976 * and the bus list for fixup functions, etc.
1978 down_write(&pci_bus_sem);
1979 list_add_tail(&dev->bus_list, &bus->devices);
1980 up_write(&pci_bus_sem);
1982 ret = pcibios_add_device(dev);
1985 /* Setup MSI irq domain */
1986 pci_set_msi_domain(dev);
1988 /* Notifier could use PCI capabilities */
1989 dev->match_driver = false;
1990 ret = device_add(&dev->dev);
1994 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1996 struct pci_dev *dev;
1998 dev = pci_get_slot(bus, devfn);
2004 dev = pci_scan_device(bus, devfn);
2008 pci_device_add(dev, bus);
2012 EXPORT_SYMBOL(pci_scan_single_device);
2014 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2020 if (pci_ari_enabled(bus)) {
2023 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2027 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2028 next_fn = PCI_ARI_CAP_NFN(cap);
2030 return 0; /* protect against malformed list */
2035 /* dev may be NULL for non-contiguous multifunction devices */
2036 if (!dev || dev->multifunction)
2037 return (fn + 1) % 8;
2042 static int only_one_child(struct pci_bus *bus)
2044 struct pci_dev *parent = bus->self;
2046 if (!parent || !pci_is_pcie(parent))
2048 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
2052 * PCIe downstream ports are bridges that normally lead to only a
2053 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
2054 * possible devices, not just device 0. See PCIe spec r3.0,
2057 if (parent->has_secondary_link &&
2058 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2064 * pci_scan_slot - scan a PCI slot on a bus for devices.
2065 * @bus: PCI bus to scan
2066 * @devfn: slot number to scan (must have zero function.)
2068 * Scan a PCI slot on the specified PCI bus for devices, adding
2069 * discovered devices to the @bus->devices list. New devices
2070 * will not have is_added set.
2072 * Returns the number of new devices found.
2074 int pci_scan_slot(struct pci_bus *bus, int devfn)
2076 unsigned fn, nr = 0;
2077 struct pci_dev *dev;
2079 if (only_one_child(bus) && (devfn > 0))
2080 return 0; /* Already scanned the entire slot */
2082 dev = pci_scan_single_device(bus, devfn);
2088 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2089 dev = pci_scan_single_device(bus, devfn + fn);
2093 dev->multifunction = 1;
2097 /* only one slot has pcie device */
2098 if (bus->self && nr)
2099 pcie_aspm_init_link_state(bus->self);
2103 EXPORT_SYMBOL(pci_scan_slot);
2105 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2109 if (!pci_is_pcie(dev))
2113 * We don't have a way to change MPS settings on devices that have
2114 * drivers attached. A hot-added device might support only the minimum
2115 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2116 * where devices may be hot-added, we limit the fabric MPS to 128 so
2117 * hot-added devices will work correctly.
2119 * However, if we hot-add a device to a slot directly below a Root
2120 * Port, it's impossible for there to be other existing devices below
2121 * the port. We don't limit the MPS in this case because we can
2122 * reconfigure MPS on both the Root Port and the hot-added device,
2123 * and there are no other devices involved.
2125 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2127 if (dev->is_hotplug_bridge &&
2128 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2131 if (*smpss > dev->pcie_mpss)
2132 *smpss = dev->pcie_mpss;
2137 static void pcie_write_mps(struct pci_dev *dev, int mps)
2141 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2142 mps = 128 << dev->pcie_mpss;
2144 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2146 /* For "Performance", the assumption is made that
2147 * downstream communication will never be larger than
2148 * the MRRS. So, the MPS only needs to be configured
2149 * for the upstream communication. This being the case,
2150 * walk from the top down and set the MPS of the child
2151 * to that of the parent bus.
2153 * Configure the device MPS with the smaller of the
2154 * device MPSS or the bridge MPS (which is assumed to be
2155 * properly configured at this point to the largest
2156 * allowable MPS based on its parent bus).
2158 mps = min(mps, pcie_get_mps(dev->bus->self));
2161 rc = pcie_set_mps(dev, mps);
2163 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
2166 static void pcie_write_mrrs(struct pci_dev *dev)
2170 /* In the "safe" case, do not configure the MRRS. There appear to be
2171 * issues with setting MRRS to 0 on a number of devices.
2173 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2176 /* For Max performance, the MRRS must be set to the largest supported
2177 * value. However, it cannot be configured larger than the MPS the
2178 * device or the bus can support. This should already be properly
2179 * configured by a prior call to pcie_write_mps.
2181 mrrs = pcie_get_mps(dev);
2183 /* MRRS is a R/W register. Invalid values can be written, but a
2184 * subsequent read will verify if the value is acceptable or not.
2185 * If the MRRS value provided is not acceptable (e.g., too large),
2186 * shrink the value until it is acceptable to the HW.
2188 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2189 rc = pcie_set_readrq(dev, mrrs);
2193 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2198 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2201 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2205 if (!pci_is_pcie(dev))
2208 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2209 pcie_bus_config == PCIE_BUS_DEFAULT)
2212 mps = 128 << *(u8 *)data;
2213 orig_mps = pcie_get_mps(dev);
2215 pcie_write_mps(dev, mps);
2216 pcie_write_mrrs(dev);
2218 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2219 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2220 orig_mps, pcie_get_readrq(dev));
2225 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2226 * parents then children fashion. If this changes, then this code will not
2229 void pcie_bus_configure_settings(struct pci_bus *bus)
2236 if (!pci_is_pcie(bus->self))
2239 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2240 * to be aware of the MPS of the destination. To work around this,
2241 * simply force the MPS of the entire system to the smallest possible.
2243 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2246 if (pcie_bus_config == PCIE_BUS_SAFE) {
2247 smpss = bus->self->pcie_mpss;
2249 pcie_find_smpss(bus->self, &smpss);
2250 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2253 pcie_bus_configure_set(bus->self, &smpss);
2254 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2256 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2258 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2260 unsigned int devfn, pass, max = bus->busn_res.start;
2261 struct pci_dev *dev;
2263 dev_dbg(&bus->dev, "scanning bus\n");
2265 /* Go find them, Rover! */
2266 for (devfn = 0; devfn < 0x100; devfn += 8)
2267 pci_scan_slot(bus, devfn);
2269 /* Reserve buses for SR-IOV capability. */
2270 max += pci_iov_bus_range(bus);
2273 * After performing arch-dependent fixup of the bus, look behind
2274 * all PCI-to-PCI bridges on this bus.
2276 if (!bus->is_added) {
2277 dev_dbg(&bus->dev, "fixups for bus\n");
2278 pcibios_fixup_bus(bus);
2282 for (pass = 0; pass < 2; pass++)
2283 list_for_each_entry(dev, &bus->devices, bus_list) {
2284 if (pci_is_bridge(dev))
2285 max = pci_scan_bridge(bus, dev, max, pass);
2289 * Make sure a hotplug bridge has at least the minimum requested
2292 if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
2293 if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
2294 max = bus->busn_res.start + pci_hotplug_bus_size - 1;
2298 * We've scanned the bus and so we know all about what's on
2299 * the other side of any bridges that may be on this bus plus
2302 * Return how far we've got finding sub-buses.
2304 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2307 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2310 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2311 * @bridge: Host bridge to set up.
2313 * Default empty implementation. Replace with an architecture-specific setup
2314 * routine, if necessary.
2316 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2321 void __weak pcibios_add_bus(struct pci_bus *bus)
2325 void __weak pcibios_remove_bus(struct pci_bus *bus)
2329 static struct pci_bus *pci_create_root_bus_msi(struct device *parent,
2330 int bus, struct pci_ops *ops, void *sysdata,
2331 struct list_head *resources, struct msi_controller *msi)
2334 struct pci_host_bridge *bridge;
2336 bridge = pci_alloc_host_bridge(0);
2340 bridge->dev.parent = parent;
2341 bridge->dev.release = pci_release_host_bridge_dev;
2343 list_splice_init(resources, &bridge->windows);
2344 bridge->sysdata = sysdata;
2345 bridge->busnr = bus;
2349 error = pci_register_host_bridge(bridge);
2360 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2361 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2363 return pci_create_root_bus_msi(parent, bus, ops, sysdata, resources,
2366 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2368 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2370 struct resource *res = &b->busn_res;
2371 struct resource *parent_res, *conflict;
2375 res->flags = IORESOURCE_BUS;
2377 if (!pci_is_root_bus(b))
2378 parent_res = &b->parent->busn_res;
2380 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2381 res->flags |= IORESOURCE_PCI_FIXED;
2384 conflict = request_resource_conflict(parent_res, res);
2387 dev_printk(KERN_DEBUG, &b->dev,
2388 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2389 res, pci_is_root_bus(b) ? "domain " : "",
2390 parent_res, conflict->name, conflict);
2392 return conflict == NULL;
2395 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2397 struct resource *res = &b->busn_res;
2398 struct resource old_res = *res;
2399 resource_size_t size;
2402 if (res->start > bus_max)
2405 size = bus_max - res->start + 1;
2406 ret = adjust_resource(res, res->start, size);
2407 dev_printk(KERN_DEBUG, &b->dev,
2408 "busn_res: %pR end %s updated to %02x\n",
2409 &old_res, ret ? "can not be" : "is", bus_max);
2411 if (!ret && !res->parent)
2412 pci_bus_insert_busn_res(b, res->start, res->end);
2417 void pci_bus_release_busn_res(struct pci_bus *b)
2419 struct resource *res = &b->busn_res;
2422 if (!res->flags || !res->parent)
2425 ret = release_resource(res);
2426 dev_printk(KERN_DEBUG, &b->dev,
2427 "busn_res: %pR %s released\n",
2428 res, ret ? "can not be" : "is");
2431 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2432 struct pci_ops *ops, void *sysdata,
2433 struct list_head *resources, struct msi_controller *msi)
2435 struct resource_entry *window;
2440 resource_list_for_each_entry(window, resources)
2441 if (window->res->flags & IORESOURCE_BUS) {
2446 b = pci_create_root_bus_msi(parent, bus, ops, sysdata, resources, msi);
2452 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2454 pci_bus_insert_busn_res(b, bus, 255);
2457 max = pci_scan_child_bus(b);
2460 pci_bus_update_busn_res_end(b, max);
2465 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2466 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2468 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2471 EXPORT_SYMBOL(pci_scan_root_bus);
2473 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2476 LIST_HEAD(resources);
2479 pci_add_resource(&resources, &ioport_resource);
2480 pci_add_resource(&resources, &iomem_resource);
2481 pci_add_resource(&resources, &busn_resource);
2482 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2484 pci_scan_child_bus(b);
2486 pci_free_resource_list(&resources);
2490 EXPORT_SYMBOL(pci_scan_bus);
2493 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2494 * @bridge: PCI bridge for the bus to scan
2496 * Scan a PCI bus and child buses for new devices, add them,
2497 * and enable them, resizing bridge mmio/io resource if necessary
2498 * and possible. The caller must ensure the child devices are already
2499 * removed for resizing to occur.
2501 * Returns the max number of subordinate bus discovered.
2503 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2506 struct pci_bus *bus = bridge->subordinate;
2508 max = pci_scan_child_bus(bus);
2510 pci_assign_unassigned_bridge_resources(bridge);
2512 pci_bus_add_devices(bus);
2518 * pci_rescan_bus - scan a PCI bus for devices.
2519 * @bus: PCI bus to scan
2521 * Scan a PCI bus and child buses for new devices, adds them,
2524 * Returns the max number of subordinate bus discovered.
2526 unsigned int pci_rescan_bus(struct pci_bus *bus)
2530 max = pci_scan_child_bus(bus);
2531 pci_assign_unassigned_bus_resources(bus);
2532 pci_bus_add_devices(bus);
2536 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2539 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2540 * routines should always be executed under this mutex.
2542 static DEFINE_MUTEX(pci_rescan_remove_lock);
2544 void pci_lock_rescan_remove(void)
2546 mutex_lock(&pci_rescan_remove_lock);
2548 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2550 void pci_unlock_rescan_remove(void)
2552 mutex_unlock(&pci_rescan_remove_lock);
2554 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2556 static int __init pci_sort_bf_cmp(const struct device *d_a,
2557 const struct device *d_b)
2559 const struct pci_dev *a = to_pci_dev(d_a);
2560 const struct pci_dev *b = to_pci_dev(d_b);
2562 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2563 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2565 if (a->bus->number < b->bus->number) return -1;
2566 else if (a->bus->number > b->bus->number) return 1;
2568 if (a->devfn < b->devfn) return -1;
2569 else if (a->devfn > b->devfn) return 1;
2574 void __init pci_sort_breadthfirst(void)
2576 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);