drivers/pinctrl/intel/pinctrl-intel.c

   1 /*
   2  * Intel pinctrl/GPIO core driver.
   3  *
   4  * Copyright (C) 2015, Intel Corporation
   5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/acpi.h>
  17 #include <linux/gpio.h>
  18 #include <linux/gpio/driver.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25
  26 #include "pinctrl-intel.h"
  27
  28 /* Maximum number of pads in each group */
  29 #define NPADS_IN_GPP                    24
  30
  31 /* Offset from regs */
  32 #define PADBAR                          0x00c
  33 #define GPI_IS                          0x100
  34 #define GPI_GPE_STS                     0x140
  35 #define GPI_GPE_EN                      0x160
  36
  37 #define PADOWN_BITS                     4
  38 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  39 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  40
  41 /* Offset from pad_regs */
  42 #define PADCFG0                         0x000
  43 #define PADCFG0_RXEVCFG_SHIFT           25
  44 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  45 #define PADCFG0_RXEVCFG_LEVEL           0
  46 #define PADCFG0_RXEVCFG_EDGE            1
  47 #define PADCFG0_RXEVCFG_DISABLED        2
  48 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  49 #define PADCFG0_RXINV                   BIT(23)
  50 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  51 #define PADCFG0_GPIROUTSCI              BIT(19)
  52 #define PADCFG0_GPIROUTSMI              BIT(18)
  53 #define PADCFG0_GPIROUTNMI              BIT(17)
  54 #define PADCFG0_PMODE_SHIFT             10
  55 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  56 #define PADCFG0_GPIORXDIS               BIT(9)
  57 #define PADCFG0_GPIOTXDIS               BIT(8)
  58 #define PADCFG0_GPIORXSTATE             BIT(1)
  59 #define PADCFG0_GPIOTXSTATE             BIT(0)
  60
  61 #define PADCFG1                         0x004
  62 #define PADCFG1_TERM_UP                 BIT(13)
  63 #define PADCFG1_TERM_SHIFT              10
  64 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  65 #define PADCFG1_TERM_20K                4
  66 #define PADCFG1_TERM_2K                 3
  67 #define PADCFG1_TERM_5K                 2
  68 #define PADCFG1_TERM_1K                 1
  69
  70 struct intel_pad_context {
  71         u32 padcfg0;
  72         u32 padcfg1;
  73 };
  74
  75 struct intel_community_context {
  76         u32 *intmask;
  77 };
  78
  79 struct intel_pinctrl_context {
  80         struct intel_pad_context *pads;
  81         struct intel_community_context *communities;
  82 };
  83
  84 /**
  85  * struct intel_pinctrl - Intel pinctrl private structure
  86  * @dev: Pointer to the device structure
  87  * @lock: Lock to serialize register access
  88  * @pctldesc: Pin controller description
  89  * @pctldev: Pointer to the pin controller device
  90  * @chip: GPIO chip in this pin controller
  91  * @soc: SoC/PCH specific pin configuration data
  92  * @communities: All communities in this pin controller
  93  * @ncommunities: Number of communities in this pin controller
  94  * @context: Configuration saved over system sleep
  95  */
  96 struct intel_pinctrl {
  97         struct device *dev;
  98         spinlock_t lock;
  99         struct pinctrl_desc pctldesc;
 100         struct pinctrl_dev *pctldev;
 101         struct gpio_chip chip;
 102         const struct intel_pinctrl_soc_data *soc;
 103         struct intel_community *communities;
 104         size_t ncommunities;
 105         struct intel_pinctrl_context context;
 106 };
 107
 108 #define gpiochip_to_pinctrl(c)  container_of(c, struct intel_pinctrl, chip)
 109 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 110
 111 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 112                                                    unsigned pin)
 113 {
 114         struct intel_community *community;
 115         int i;
 116
 117         for (i = 0; i < pctrl->ncommunities; i++) {
 118                 community = &pctrl->communities[i];
 119                 if (pin >= community->pin_base &&
 120                     pin < community->pin_base + community->npins)
 121                         return community;
 122         }
 123
 124         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 125         return NULL;
 126 }
 127
 128 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
 129                                       unsigned reg)
 130 {
 131         const struct intel_community *community;
 132         unsigned padno;
 133
 134         community = intel_get_community(pctrl, pin);
 135         if (!community)
 136                 return NULL;
 137
 138         padno = pin_to_padno(community, pin);
 139         return community->pad_regs + reg + padno * 8;
 140 }
 141
 142 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 143 {
 144         const struct intel_community *community;
 145         unsigned padno, gpp, gpp_offset, offset;
 146         void __iomem *padown;
 147
 148         community = intel_get_community(pctrl, pin);
 149         if (!community)
 150                 return false;
 151         if (!community->padown_offset)
 152                 return true;
 153
 154         padno = pin_to_padno(community, pin);
 155         gpp = padno / NPADS_IN_GPP;
 156         gpp_offset = padno % NPADS_IN_GPP;
 157         offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4;
 158         padown = community->regs + offset;
 159
 160         return !(readl(padown) & PADOWN_MASK(padno));
 161 }
 162
 163 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
 164 {
 165         const struct intel_community *community;
 166         unsigned padno, gpp, offset;
 167         void __iomem *hostown;
 168
 169         community = intel_get_community(pctrl, pin);
 170         if (!community)
 171                 return true;
 172         if (!community->hostown_offset)
 173                 return false;
 174
 175         padno = pin_to_padno(community, pin);
 176         gpp = padno / NPADS_IN_GPP;
 177         offset = community->hostown_offset + gpp * 4;
 178         hostown = community->regs + offset;
 179
 180         return !(readl(hostown) & BIT(padno % NPADS_IN_GPP));
 181 }
 182
 183 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
 184 {
 185         struct intel_community *community;
 186         unsigned padno, gpp, offset;
 187         u32 value;
 188
 189         community = intel_get_community(pctrl, pin);
 190         if (!community)
 191                 return true;
 192         if (!community->padcfglock_offset)
 193                 return false;
 194
 195         padno = pin_to_padno(community, pin);
 196         gpp = padno / NPADS_IN_GPP;
 197
 198         /*
 199          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 200          * the pad is considered unlocked. Any other case means that it is
 201          * either fully or partially locked and we don't touch it.
 202          */
 203         offset = community->padcfglock_offset + gpp * 8;
 204         value = readl(community->regs + offset);
 205         if (value & BIT(pin % NPADS_IN_GPP))
 206                 return true;
 207
 208         offset = community->padcfglock_offset + 4 + gpp * 8;
 209         value = readl(community->regs + offset);
 210         if (value & BIT(pin % NPADS_IN_GPP))
 211                 return true;
 212
 213         return false;
 214 }
 215
 216 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
 217 {
 218         return intel_pad_owned_by_host(pctrl, pin) &&
 219                 !intel_pad_locked(pctrl, pin);
 220 }
 221
 222 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 223 {
 224         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 225
 226         return pctrl->soc->ngroups;
 227 }
 228
 229 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 230                                       unsigned group)
 231 {
 232         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 233
 234         return pctrl->soc->groups[group].name;
 235 }
 236
 237 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 238                               const unsigned **pins, unsigned *npins)
 239 {
 240         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 241
 242         *pins = pctrl->soc->groups[group].pins;
 243         *npins = pctrl->soc->groups[group].npins;
 244         return 0;
 245 }
 246
 247 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 248                                unsigned pin)
 249 {
 250         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 251         u32 cfg0, cfg1, mode;
 252         bool locked, acpi;
 253
 254         if (!intel_pad_owned_by_host(pctrl, pin)) {
 255                 seq_puts(s, "not available");
 256                 return;
 257         }
 258
 259         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 260         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 261
 262         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 263         if (!mode)
 264                 seq_puts(s, "GPIO ");
 265         else
 266                 seq_printf(s, "mode %d ", mode);
 267
 268         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 269
 270         locked = intel_pad_locked(pctrl, pin);
 271         acpi = intel_pad_acpi_mode(pctrl, pin);
 272
 273         if (locked || acpi) {
 274                 seq_puts(s, " [");
 275                 if (locked) {
 276                         seq_puts(s, "LOCKED");
 277                         if (acpi)
 278                                 seq_puts(s, ", ");
 279                 }
 280                 if (acpi)
 281                         seq_puts(s, "ACPI");
 282                 seq_puts(s, "]");
 283         }
 284 }
 285
 286 static const struct pinctrl_ops intel_pinctrl_ops = {
 287         .get_groups_count = intel_get_groups_count,
 288         .get_group_name = intel_get_group_name,
 289         .get_group_pins = intel_get_group_pins,
 290         .pin_dbg_show = intel_pin_dbg_show,
 291 };
 292
 293 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 294 {
 295         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 296
 297         return pctrl->soc->nfunctions;
 298 }
 299
 300 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 301                                            unsigned function)
 302 {
 303         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 304
 305         return pctrl->soc->functions[function].name;
 306 }
 307
 308 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 309                                      unsigned function,
 310                                      const char * const **groups,
 311                                      unsigned * const ngroups)
 312 {
 313         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 314
 315         *groups = pctrl->soc->functions[function].groups;
 316         *ngroups = pctrl->soc->functions[function].ngroups;
 317         return 0;
 318 }
 319
 320 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 321                                 unsigned group)
 322 {
 323         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 324         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 325         unsigned long flags;
 326         int i;
 327
 328         spin_lock_irqsave(&pctrl->lock, flags);
 329
 330         /*
 331          * All pins in the groups needs to be accessible and writable
 332          * before we can enable the mux for this group.
 333          */
 334         for (i = 0; i < grp->npins; i++) {
 335                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 336                         spin_unlock_irqrestore(&pctrl->lock, flags);
 337                         return -EBUSY;
 338                 }
 339         }
 340
 341         /* Now enable the mux setting for each pin in the group */
 342         for (i = 0; i < grp->npins; i++) {
 343                 void __iomem *padcfg0;
 344                 u32 value;
 345
 346                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 347                 value = readl(padcfg0);
 348
 349                 value &= ~PADCFG0_PMODE_MASK;
 350                 value |= grp->mode << PADCFG0_PMODE_SHIFT;
 351
 352                 writel(value, padcfg0);
 353         }
 354
 355         spin_unlock_irqrestore(&pctrl->lock, flags);
 356
 357         return 0;
 358 }
 359
 360 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 361                                      struct pinctrl_gpio_range *range,
 362                                      unsigned pin)
 363 {
 364         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 365         void __iomem *padcfg0;
 366         unsigned long flags;
 367         u32 value;
 368
 369         spin_lock_irqsave(&pctrl->lock, flags);
 370
 371         if (!intel_pad_usable(pctrl, pin)) {
 372                 spin_unlock_irqrestore(&pctrl->lock, flags);
 373                 return -EBUSY;
 374         }
 375
 376         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 377         /* Put the pad into GPIO mode */
 378         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 379         /* Disable SCI/SMI/NMI generation */
 380         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 381         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 382         /* Disable TX buffer and enable RX (this will be input) */
 383         value &= ~PADCFG0_GPIORXDIS;
 384         value |= PADCFG0_GPIOTXDIS;
 385         writel(value, padcfg0);
 386
 387         spin_unlock_irqrestore(&pctrl->lock, flags);
 388
 389         return 0;
 390 }
 391
 392 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 393                                     struct pinctrl_gpio_range *range,
 394                                     unsigned pin, bool input)
 395 {
 396         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 397         void __iomem *padcfg0;
 398         unsigned long flags;
 399         u32 value;
 400
 401         spin_lock_irqsave(&pctrl->lock, flags);
 402
 403         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 404
 405         value = readl(padcfg0);
 406         if (input)
 407                 value |= PADCFG0_GPIOTXDIS;
 408         else
 409                 value &= ~PADCFG0_GPIOTXDIS;
 410         writel(value, padcfg0);
 411
 412         spin_unlock_irqrestore(&pctrl->lock, flags);
 413
 414         return 0;
 415 }
 416
 417 static const struct pinmux_ops intel_pinmux_ops = {
 418         .get_functions_count = intel_get_functions_count,
 419         .get_function_name = intel_get_function_name,
 420         .get_function_groups = intel_get_function_groups,
 421         .set_mux = intel_pinmux_set_mux,
 422         .gpio_request_enable = intel_gpio_request_enable,
 423         .gpio_set_direction = intel_gpio_set_direction,
 424 };
 425
 426 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 427                             unsigned long *config)
 428 {
 429         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 430         enum pin_config_param param = pinconf_to_config_param(*config);
 431         u32 value, term;
 432         u16 arg = 0;
 433
 434         if (!intel_pad_owned_by_host(pctrl, pin))
 435                 return -ENOTSUPP;
 436
 437         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 438         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 439
 440         switch (param) {
 441         case PIN_CONFIG_BIAS_DISABLE:
 442                 if (term)
 443                         return -EINVAL;
 444                 break;
 445
 446         case PIN_CONFIG_BIAS_PULL_UP:
 447                 if (!term || !(value & PADCFG1_TERM_UP))
 448                         return -EINVAL;
 449
 450                 switch (term) {
 451                 case PADCFG1_TERM_1K:
 452                         arg = 1000;
 453                         break;
 454                 case PADCFG1_TERM_2K:
 455                         arg = 2000;
 456                         break;
 457                 case PADCFG1_TERM_5K:
 458                         arg = 5000;
 459                         break;
 460                 case PADCFG1_TERM_20K:
 461                         arg = 20000;
 462                         break;
 463                 }
 464
 465                 break;
 466
 467         case PIN_CONFIG_BIAS_PULL_DOWN:
 468                 if (!term || value & PADCFG1_TERM_UP)
 469                         return -EINVAL;
 470
 471                 switch (term) {
 472                 case PADCFG1_TERM_5K:
 473                         arg = 5000;
 474                         break;
 475                 case PADCFG1_TERM_20K:
 476                         arg = 20000;
 477                         break;
 478                 }
 479
 480                 break;
 481
 482         default:
 483                 return -ENOTSUPP;
 484         }
 485
 486         *config = pinconf_to_config_packed(param, arg);
 487         return 0;
 488 }
 489
 490 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
 491                                  unsigned long config)
 492 {
 493         unsigned param = pinconf_to_config_param(config);
 494         unsigned arg = pinconf_to_config_argument(config);
 495         void __iomem *padcfg1;
 496         unsigned long flags;
 497         int ret = 0;
 498         u32 value;
 499
 500         spin_lock_irqsave(&pctrl->lock, flags);
 501
 502         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 503         value = readl(padcfg1);
 504
 505         switch (param) {
 506         case PIN_CONFIG_BIAS_DISABLE:
 507                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 508                 break;
 509
 510         case PIN_CONFIG_BIAS_PULL_UP:
 511                 value &= ~PADCFG1_TERM_MASK;
 512
 513                 value |= PADCFG1_TERM_UP;
 514
 515                 switch (arg) {
 516                 case 20000:
 517                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 518                         break;
 519                 case 5000:
 520                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 521                         break;
 522                 case 2000:
 523                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 524                         break;
 525                 case 1000:
 526                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 527                         break;
 528                 default:
 529                         ret = -EINVAL;
 530                 }
 531
 532                 break;
 533
 534         case PIN_CONFIG_BIAS_PULL_DOWN:
 535                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 536
 537                 switch (arg) {
 538                 case 20000:
 539                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 540                         break;
 541                 case 5000:
 542                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 543                         break;
 544                 default:
 545                         ret = -EINVAL;
 546                 }
 547
 548                 break;
 549         }
 550
 551         if (!ret)
 552                 writel(value, padcfg1);
 553
 554         spin_unlock_irqrestore(&pctrl->lock, flags);
 555
 556         return ret;
 557 }
 558
 559 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 560                           unsigned long *configs, unsigned nconfigs)
 561 {
 562         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 563         int i, ret;
 564
 565         if (!intel_pad_usable(pctrl, pin))
 566                 return -ENOTSUPP;
 567
 568         for (i = 0; i < nconfigs; i++) {
 569                 switch (pinconf_to_config_param(configs[i])) {
 570                 case PIN_CONFIG_BIAS_DISABLE:
 571                 case PIN_CONFIG_BIAS_PULL_UP:
 572                 case PIN_CONFIG_BIAS_PULL_DOWN:
 573                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 574                         if (ret)
 575                                 return ret;
 576                         break;
 577
 578                 default:
 579                         return -ENOTSUPP;
 580                 }
 581         }
 582
 583         return 0;
 584 }
 585
 586 static const struct pinconf_ops intel_pinconf_ops = {
 587         .is_generic = true,
 588         .pin_config_get = intel_config_get,
 589         .pin_config_set = intel_config_set,
 590 };
 591
 592 static const struct pinctrl_desc intel_pinctrl_desc = {
 593         .pctlops = &intel_pinctrl_ops,
 594         .pmxops = &intel_pinmux_ops,
 595         .confops = &intel_pinconf_ops,
 596         .owner = THIS_MODULE,
 597 };
 598
 599 static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
 600 {
 601         return pinctrl_request_gpio(chip->base + offset);
 602 }
 603
 604 static void intel_gpio_free(struct gpio_chip *chip, unsigned offset)
 605 {
 606         pinctrl_free_gpio(chip->base + offset);
 607 }
 608
 609 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 610 {
 611         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
 612         void __iomem *reg;
 613
 614         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 615         if (!reg)
 616                 return -EINVAL;
 617
 618         return !!(readl(reg) & PADCFG0_GPIORXSTATE);
 619 }
 620
 621 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 622 {
 623         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
 624         void __iomem *reg;
 625
 626         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 627         if (reg) {
 628                 unsigned long flags;
 629                 u32 padcfg0;
 630
 631                 spin_lock_irqsave(&pctrl->lock, flags);
 632                 padcfg0 = readl(reg);
 633                 if (value)
 634                         padcfg0 |= PADCFG0_GPIOTXSTATE;
 635                 else
 636                         padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 637                 writel(padcfg0, reg);
 638                 spin_unlock_irqrestore(&pctrl->lock, flags);
 639         }
 640 }
 641
 642 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 643 {
 644         return pinctrl_gpio_direction_input(chip->base + offset);
 645 }
 646
 647 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 648                                        int value)
 649 {
 650         intel_gpio_set(chip, offset, value);
 651         return pinctrl_gpio_direction_output(chip->base + offset);
 652 }
 653
 654 static const struct gpio_chip intel_gpio_chip = {
 655         .owner = THIS_MODULE,
 656         .request = intel_gpio_request,
 657         .free = intel_gpio_free,
 658         .direction_input = intel_gpio_direction_input,
 659         .direction_output = intel_gpio_direction_output,
 660         .get = intel_gpio_get,
 661         .set = intel_gpio_set,
 662 };
 663
 664 static void intel_gpio_irq_ack(struct irq_data *d)
 665 {
 666         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 667         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
 668         const struct intel_community *community;
 669         unsigned pin = irqd_to_hwirq(d);
 670
 671         spin_lock(&pctrl->lock);
 672
 673         community = intel_get_community(pctrl, pin);
 674         if (community) {
 675                 unsigned padno = pin_to_padno(community, pin);
 676                 unsigned gpp_offset = padno % NPADS_IN_GPP;
 677                 unsigned gpp = padno / NPADS_IN_GPP;
 678
 679                 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
 680         }
 681
 682         spin_unlock(&pctrl->lock);
 683 }
 684
 685 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 686 {
 687         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 688         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
 689         const struct intel_community *community;
 690         unsigned pin = irqd_to_hwirq(d);
 691         unsigned long flags;
 692
 693         spin_lock_irqsave(&pctrl->lock, flags);
 694
 695         community = intel_get_community(pctrl, pin);
 696         if (community) {
 697                 unsigned padno = pin_to_padno(community, pin);
 698                 unsigned gpp_offset = padno % NPADS_IN_GPP;
 699                 unsigned gpp = padno / NPADS_IN_GPP;
 700                 void __iomem *reg;
 701                 u32 value;
 702
 703                 reg = community->regs + community->ie_offset + gpp * 4;
 704                 value = readl(reg);
 705                 if (mask)
 706                         value &= ~BIT(gpp_offset);
 707                 else
 708                         value |= BIT(gpp_offset);
 709                 writel(value, reg);
 710         }
 711
 712         spin_unlock_irqrestore(&pctrl->lock, flags);
 713 }
 714
 715 static void intel_gpio_irq_mask(struct irq_data *d)
 716 {
 717         intel_gpio_irq_mask_unmask(d, true);
 718 }
 719
 720 static void intel_gpio_irq_unmask(struct irq_data *d)
 721 {
 722         intel_gpio_irq_mask_unmask(d, false);
 723 }
 724
 725 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
 726 {
 727         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 728         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
 729         unsigned pin = irqd_to_hwirq(d);
 730         unsigned long flags;
 731         void __iomem *reg;
 732         u32 value;
 733
 734         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 735         if (!reg)
 736                 return -EINVAL;
 737
 738         /*
 739          * If the pin is in ACPI mode it is still usable as a GPIO but it
 740          * cannot be used as IRQ because GPI_IS status bit will not be
 741          * updated by the host controller hardware.
 742          */
 743         if (intel_pad_acpi_mode(pctrl, pin)) {
 744                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
 745                 return -EPERM;
 746         }
 747
 748         spin_lock_irqsave(&pctrl->lock, flags);
 749
 750         value = readl(reg);
 751
 752         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
 753
 754         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 755                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
 756         } else if (type & IRQ_TYPE_EDGE_FALLING) {
 757                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 758                 value |= PADCFG0_RXINV;
 759         } else if (type & IRQ_TYPE_EDGE_RISING) {
 760                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 761         } else if (type & IRQ_TYPE_LEVEL_LOW) {
 762                 value |= PADCFG0_RXINV;
 763         } else {
 764                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
 765         }
 766
 767         writel(value, reg);
 768
 769         if (type & IRQ_TYPE_EDGE_BOTH)
 770                 irq_set_handler_locked(d, handle_edge_irq);
 771         else if (type & IRQ_TYPE_LEVEL_MASK)
 772                 irq_set_handler_locked(d, handle_level_irq);
 773
 774         spin_unlock_irqrestore(&pctrl->lock, flags);
 775
 776         return 0;
 777 }
 778
 779 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
 780 {
 781         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 782         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
 783         const struct intel_community *community;
 784         unsigned pin = irqd_to_hwirq(d);
 785         unsigned padno, gpp, gpp_offset;
 786         u32 gpe_en;
 787
 788         community = intel_get_community(pctrl, pin);
 789         if (!community)
 790                 return -EINVAL;
 791
 792         padno = pin_to_padno(community, pin);
 793         gpp = padno / NPADS_IN_GPP;
 794         gpp_offset = padno % NPADS_IN_GPP;
 795
 796         /* Clear the existing wake status */
 797         writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
 798
 799         /*
 800          * The controller will generate wake when GPE of the corresponding
 801          * pad is enabled and it is not routed to SCI (GPIROUTSCI is not
 802          * set).
 803          */
 804         gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4);
 805         if (on)
 806                 gpe_en |= BIT(gpp_offset);
 807         else
 808                 gpe_en &= ~BIT(gpp_offset);
 809         writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4);
 810
 811         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
 812         return 0;
 813 }
 814
 815 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
 816         const struct intel_community *community)
 817 {
 818         struct gpio_chip *gc = &pctrl->chip;
 819         irqreturn_t ret = IRQ_NONE;
 820         int gpp;
 821
 822         for (gpp = 0; gpp < community->ngpps; gpp++) {
 823                 unsigned long pending, enabled, gpp_offset;
 824
 825                 pending = readl(community->regs + GPI_IS + gpp * 4);
 826                 enabled = readl(community->regs + community->ie_offset +
 827                                 gpp * 4);
 828
 829                 /* Only interrupts that are enabled */
 830                 pending &= enabled;
 831
 832                 for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) {
 833                         unsigned padno, irq;
 834
 835                         /*
 836                          * The last group in community can have less pins
 837                          * than NPADS_IN_GPP.
 838                          */
 839                         padno = gpp_offset + gpp * NPADS_IN_GPP;
 840                         if (padno >= community->npins)
 841                                 break;
 842
 843                         irq = irq_find_mapping(gc->irqdomain,
 844                                                community->pin_base + padno);
 845                         generic_handle_irq(irq);
 846
 847                         ret |= IRQ_HANDLED;
 848                 }
 849         }
 850
 851         return ret;
 852 }
 853
 854 static irqreturn_t intel_gpio_irq(int irq, void *data)
 855 {
 856         const struct intel_community *community;
 857         struct intel_pinctrl *pctrl = data;
 858         irqreturn_t ret = IRQ_NONE;
 859         int i;
 860
 861         /* Need to check all communities for pending interrupts */
 862         for (i = 0; i < pctrl->ncommunities; i++) {
 863                 community = &pctrl->communities[i];
 864                 ret |= intel_gpio_community_irq_handler(pctrl, community);
 865         }
 866
 867         return ret;
 868 }
 869
 870 static struct irq_chip intel_gpio_irqchip = {
 871         .name = "intel-gpio",
 872         .irq_ack = intel_gpio_irq_ack,
 873         .irq_mask = intel_gpio_irq_mask,
 874         .irq_unmask = intel_gpio_irq_unmask,
 875         .irq_set_type = intel_gpio_irq_type,
 876         .irq_set_wake = intel_gpio_irq_wake,
 877 };
 878
 879 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
 880 {
 881         int ret;
 882
 883         pctrl->chip = intel_gpio_chip;
 884
 885         pctrl->chip.ngpio = pctrl->soc->npins;
 886         pctrl->chip.label = dev_name(pctrl->dev);
 887         pctrl->chip.dev = pctrl->dev;
 888         pctrl->chip.base = -1;
 889
 890         ret = gpiochip_add(&pctrl->chip);
 891         if (ret) {
 892                 dev_err(pctrl->dev, "failed to register gpiochip\n");
 893                 return ret;
 894         }
 895
 896         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
 897                                      0, 0, pctrl->soc->npins);
 898         if (ret) {
 899                 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
 900                 goto fail;
 901         }
 902
 903         /*
 904          * We need to request the interrupt here (instead of providing chip
 905          * to the irq directly) because on some platforms several GPIO
 906          * controllers share the same interrupt line.
 907          */
 908         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
 909                                dev_name(pctrl->dev), pctrl);
 910         if (ret) {
 911                 dev_err(pctrl->dev, "failed to request interrupt\n");
 912                 goto fail;
 913         }
 914
 915         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
 916                                    handle_simple_irq, IRQ_TYPE_NONE);
 917         if (ret) {
 918                 dev_err(pctrl->dev, "failed to add irqchip\n");
 919                 goto fail;
 920         }
 921
 922         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
 923                                      NULL);
 924         return 0;
 925
 926 fail:
 927         gpiochip_remove(&pctrl->chip);
 928
 929         return ret;
 930 }
 931
 932 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
 933 {
 934 #ifdef CONFIG_PM_SLEEP
 935         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
 936         struct intel_community_context *communities;
 937         struct intel_pad_context *pads;
 938         int i;
 939
 940         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
 941         if (!pads)
 942                 return -ENOMEM;
 943
 944         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
 945                                    sizeof(*communities), GFP_KERNEL);
 946         if (!communities)
 947                 return -ENOMEM;
 948
 949
 950         for (i = 0; i < pctrl->ncommunities; i++) {
 951                 struct intel_community *community = &pctrl->communities[i];
 952                 u32 *intmask;
 953
 954                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
 955                                        sizeof(*intmask), GFP_KERNEL);
 956                 if (!intmask)
 957                         return -ENOMEM;
 958
 959                 communities[i].intmask = intmask;
 960         }
 961
 962         pctrl->context.pads = pads;
 963         pctrl->context.communities = communities;
 964 #endif
 965
 966         return 0;
 967 }
 968
 969 int intel_pinctrl_probe(struct platform_device *pdev,
 970                         const struct intel_pinctrl_soc_data *soc_data)
 971 {
 972         struct intel_pinctrl *pctrl;
 973         int i, ret, irq;
 974
 975         if (!soc_data)
 976                 return -EINVAL;
 977
 978         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 979         if (!pctrl)
 980                 return -ENOMEM;
 981
 982         pctrl->dev = &pdev->dev;
 983         pctrl->soc = soc_data;
 984         spin_lock_init(&pctrl->lock);
 985
 986         /*
 987          * Make a copy of the communities which we can use to hold pointers
 988          * to the registers.
 989          */
 990         pctrl->ncommunities = pctrl->soc->ncommunities;
 991         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
 992                                   sizeof(*pctrl->communities), GFP_KERNEL);
 993         if (!pctrl->communities)
 994                 return -ENOMEM;
 995
 996         for (i = 0; i < pctrl->ncommunities; i++) {
 997                 struct intel_community *community = &pctrl->communities[i];
 998                 struct resource *res;
 999                 void __iomem *regs;
1000                 u32 padbar;
1001
1002                 *community = pctrl->soc->communities[i];
1003
1004                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1005                                             community->barno);
1006                 regs = devm_ioremap_resource(&pdev->dev, res);
1007                 if (IS_ERR(regs))
1008                         return PTR_ERR(regs);
1009
1010                 /* Read offset of the pad configuration registers */
1011                 padbar = readl(regs + PADBAR);
1012
1013                 community->regs = regs;
1014                 community->pad_regs = regs + padbar;
1015                 community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP);
1016         }
1017
1018         irq = platform_get_irq(pdev, 0);
1019         if (irq < 0) {
1020                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1021                 return irq;
1022         }
1023
1024         ret = intel_pinctrl_pm_init(pctrl);
1025         if (ret)
1026                 return ret;
1027
1028         pctrl->pctldesc = intel_pinctrl_desc;
1029         pctrl->pctldesc.name = dev_name(&pdev->dev);
1030         pctrl->pctldesc.pins = pctrl->soc->pins;
1031         pctrl->pctldesc.npins = pctrl->soc->npins;
1032
1033         pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
1034         if (IS_ERR(pctrl->pctldev)) {
1035                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1036                 return PTR_ERR(pctrl->pctldev);
1037         }
1038
1039         ret = intel_gpio_probe(pctrl, irq);
1040         if (ret) {
1041                 pinctrl_unregister(pctrl->pctldev);
1042                 return ret;
1043         }
1044
1045         platform_set_drvdata(pdev, pctrl);
1046
1047         return 0;
1048 }
1049 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1050
1051 int intel_pinctrl_remove(struct platform_device *pdev)
1052 {
1053         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1054
1055         gpiochip_remove(&pctrl->chip);
1056         pinctrl_unregister(pctrl->pctldev);
1057
1058         return 0;
1059 }
1060 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1061
1062 #ifdef CONFIG_PM_SLEEP
1063 int intel_pinctrl_suspend(struct device *dev)
1064 {
1065         struct platform_device *pdev = to_platform_device(dev);
1066         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1067         struct intel_community_context *communities;
1068         struct intel_pad_context *pads;
1069         int i;
1070
1071         pads = pctrl->context.pads;
1072         for (i = 0; i < pctrl->soc->npins; i++) {
1073                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1074                 u32 val;
1075
1076                 if (!intel_pad_usable(pctrl, desc->number))
1077                         continue;
1078
1079                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1080                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1081                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1082                 pads[i].padcfg1 = val;
1083         }
1084
1085         communities = pctrl->context.communities;
1086         for (i = 0; i < pctrl->ncommunities; i++) {
1087                 struct intel_community *community = &pctrl->communities[i];
1088                 void __iomem *base;
1089                 unsigned gpp;
1090
1091                 base = community->regs + community->ie_offset;
1092                 for (gpp = 0; gpp < community->ngpps; gpp++)
1093                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1094         }
1095
1096         return 0;
1097 }
1098 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1099
1100 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1101 {
1102         size_t i;
1103
1104         for (i = 0; i < pctrl->ncommunities; i++) {
1105                 const struct intel_community *community;
1106                 void __iomem *base;
1107                 unsigned gpp;
1108
1109                 community = &pctrl->communities[i];
1110                 base = community->regs;
1111
1112                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1113                         /* Mask and clear all interrupts */
1114                         writel(0, base + community->ie_offset + gpp * 4);
1115                         writel(0xffff, base + GPI_IS + gpp * 4);
1116                 }
1117         }
1118 }
1119
1120 int intel_pinctrl_resume(struct device *dev)
1121 {
1122         struct platform_device *pdev = to_platform_device(dev);
1123         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1124         const struct intel_community_context *communities;
1125         const struct intel_pad_context *pads;
1126         int i;
1127
1128         /* Mask all interrupts */
1129         intel_gpio_irq_init(pctrl);
1130
1131         pads = pctrl->context.pads;
1132         for (i = 0; i < pctrl->soc->npins; i++) {
1133                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1134                 void __iomem *padcfg;
1135                 u32 val;
1136
1137                 if (!intel_pad_usable(pctrl, desc->number))
1138                         continue;
1139
1140                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1141                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1142                 if (val != pads[i].padcfg0) {
1143                         writel(pads[i].padcfg0, padcfg);
1144                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1145                                 desc->number, readl(padcfg));
1146                 }
1147
1148                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1149                 val = readl(padcfg);
1150                 if (val != pads[i].padcfg1) {
1151                         writel(pads[i].padcfg1, padcfg);
1152                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1153                                 desc->number, readl(padcfg));
1154                 }
1155         }
1156
1157         communities = pctrl->context.communities;
1158         for (i = 0; i < pctrl->ncommunities; i++) {
1159                 struct intel_community *community = &pctrl->communities[i];
1160                 void __iomem *base;
1161                 unsigned gpp;
1162
1163                 base = community->regs + community->ie_offset;
1164                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1165                         writel(communities[i].intmask[gpp], base + gpp * 4);
1166                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1167                                 readl(base + gpp * 4));
1168                 }
1169         }
1170
1171         return 0;
1172 }
1173 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1174 #endif
1175
1176 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1177 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1178 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1179 MODULE_LICENSE("GPL v2");