2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 /* Since we request GPIOs from ourself */
30 #include <linux/pinctrl/consumer.h>
32 #include <asm/mach/irq.h>
34 #include <plat/pincfg.h>
35 #include <plat/gpio-nomadik.h>
37 #include "pinctrl-nomadik.h"
40 * The GPIO module in the Nomadik family of Systems-on-Chip is an
41 * AMBA device, managing 32 pins and alternate functions. The logic block
42 * is currently used in the Nomadik and ux500.
44 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
47 #define NMK_GPIO_PER_CHIP 32
49 struct nmk_gpio_chip {
50 struct gpio_chip chip;
51 struct irq_domain *domain;
55 unsigned int parent_irq;
56 int secondary_parent_irq;
57 u32 (*get_secondary_status)(unsigned int bank);
58 void (*set_ioforce)(bool enable);
61 /* Keep track of configured edges */
75 struct pinctrl_dev *pctl;
76 const struct nmk_pinctrl_soc_data *soc;
79 static struct nmk_gpio_chip *
80 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
82 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
84 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
86 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
87 unsigned offset, int gpio_mode)
89 u32 bit = 1 << offset;
92 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
93 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
94 if (gpio_mode & NMK_GPIO_ALT_A)
96 if (gpio_mode & NMK_GPIO_ALT_B)
98 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
99 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
102 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
103 unsigned offset, enum nmk_gpio_slpm mode)
105 u32 bit = 1 << offset;
108 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
109 if (mode == NMK_GPIO_SLPM_NOCHANGE)
113 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
116 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
117 unsigned offset, enum nmk_gpio_pull pull)
119 u32 bit = 1 << offset;
122 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
123 if (pull == NMK_GPIO_PULL_NONE) {
125 nmk_chip->pull_up &= ~bit;
130 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
132 if (pull == NMK_GPIO_PULL_UP) {
133 nmk_chip->pull_up |= bit;
134 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
135 } else if (pull == NMK_GPIO_PULL_DOWN) {
136 nmk_chip->pull_up &= ~bit;
137 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
141 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
142 unsigned offset, bool lowemi)
144 u32 bit = BIT(offset);
145 bool enabled = nmk_chip->lowemi & bit;
147 if (lowemi == enabled)
151 nmk_chip->lowemi |= bit;
153 nmk_chip->lowemi &= ~bit;
155 writel_relaxed(nmk_chip->lowemi,
156 nmk_chip->addr + NMK_GPIO_LOWEMI);
159 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
162 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
165 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
166 unsigned offset, int val)
169 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
171 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
174 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
175 unsigned offset, int val)
177 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
178 __nmk_gpio_set_output(nmk_chip, offset, val);
181 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
182 unsigned offset, int gpio_mode,
185 u32 rwimsc = nmk_chip->rwimsc;
186 u32 fwimsc = nmk_chip->fwimsc;
188 if (glitch && nmk_chip->set_ioforce) {
189 u32 bit = BIT(offset);
191 /* Prevent spurious wakeups */
192 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
193 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
195 nmk_chip->set_ioforce(true);
198 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
200 if (glitch && nmk_chip->set_ioforce) {
201 nmk_chip->set_ioforce(false);
203 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
204 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
209 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
211 u32 falling = nmk_chip->fimsc & BIT(offset);
212 u32 rising = nmk_chip->rimsc & BIT(offset);
213 int gpio = nmk_chip->chip.base + offset;
214 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
215 struct irq_data *d = irq_get_irq_data(irq);
217 if (!rising && !falling)
220 if (!d || !irqd_irq_disabled(d))
224 nmk_chip->rimsc &= ~BIT(offset);
225 writel_relaxed(nmk_chip->rimsc,
226 nmk_chip->addr + NMK_GPIO_RIMSC);
230 nmk_chip->fimsc &= ~BIT(offset);
231 writel_relaxed(nmk_chip->fimsc,
232 nmk_chip->addr + NMK_GPIO_FIMSC);
235 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
238 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
239 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
241 static const char *afnames[] = {
242 [NMK_GPIO_ALT_GPIO] = "GPIO",
243 [NMK_GPIO_ALT_A] = "A",
244 [NMK_GPIO_ALT_B] = "B",
245 [NMK_GPIO_ALT_C] = "C"
247 static const char *pullnames[] = {
248 [NMK_GPIO_PULL_NONE] = "none",
249 [NMK_GPIO_PULL_UP] = "up",
250 [NMK_GPIO_PULL_DOWN] = "down",
251 [3] /* illegal */ = "??"
253 static const char *slpmnames[] = {
254 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
255 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
258 int pin = PIN_NUM(cfg);
259 int pull = PIN_PULL(cfg);
260 int af = PIN_ALT(cfg);
261 int slpm = PIN_SLPM(cfg);
262 int output = PIN_DIR(cfg);
263 int val = PIN_VAL(cfg);
264 bool glitch = af == NMK_GPIO_ALT_C;
266 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
267 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
268 output ? "output " : "input",
269 output ? (val ? "high" : "low") : "");
272 int slpm_pull = PIN_SLPM_PULL(cfg);
273 int slpm_output = PIN_SLPM_DIR(cfg);
274 int slpm_val = PIN_SLPM_VAL(cfg);
276 af = NMK_GPIO_ALT_GPIO;
279 * The SLPM_* values are normal values + 1 to allow zero to
280 * mean "same as normal".
283 pull = slpm_pull - 1;
285 output = slpm_output - 1;
289 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
291 slpm_pull ? pullnames[pull] : "same",
292 slpm_output ? (output ? "output" : "input") : "same",
293 slpm_val ? (val ? "high" : "low") : "same");
297 __nmk_gpio_make_output(nmk_chip, offset, val);
299 __nmk_gpio_make_input(nmk_chip, offset);
300 __nmk_gpio_set_pull(nmk_chip, offset, pull);
303 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
306 * If the pin is switching to altfunc, and there was an interrupt
307 * installed on it which has been lazy disabled, actually mask the
308 * interrupt to prevent spurious interrupts that would occur while the
309 * pin is under control of the peripheral. Only SKE does this.
311 if (af != NMK_GPIO_ALT_GPIO)
312 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
315 * If we've backed up the SLPM registers (glitch workaround), modify
316 * the backups since they will be restored.
319 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
320 slpmregs[nmk_chip->bank] |= BIT(offset);
322 slpmregs[nmk_chip->bank] &= ~BIT(offset);
324 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
326 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
330 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
331 * - Save SLPM registers
332 * - Set SLPM=0 for the IOs you want to switch and others to 1
333 * - Configure the GPIO registers for the IOs that are being switched
335 * - Modify the AFLSA/B registers for the IOs that are being switched
337 * - Restore SLPM registers
338 * - Any spurious wake up event during switch sequence to be ignored and
341 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
345 for (i = 0; i < NUM_BANKS; i++) {
346 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
347 unsigned int temp = slpm[i];
352 clk_enable(chip->clk);
354 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
355 writel(temp, chip->addr + NMK_GPIO_SLPC);
359 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
363 for (i = 0; i < NUM_BANKS; i++) {
364 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
369 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
371 clk_disable(chip->clk);
375 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
377 static unsigned int slpm[NUM_BANKS];
383 for (i = 0; i < num; i++) {
384 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
390 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
393 memset(slpm, 0xff, sizeof(slpm));
395 for (i = 0; i < num; i++) {
396 int pin = PIN_NUM(cfgs[i]);
397 int offset = pin % NMK_GPIO_PER_CHIP;
399 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
400 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
403 nmk_gpio_glitch_slpm_init(slpm);
406 for (i = 0; i < num; i++) {
407 struct nmk_gpio_chip *nmk_chip;
408 int pin = PIN_NUM(cfgs[i]);
410 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
416 clk_enable(nmk_chip->clk);
417 spin_lock(&nmk_chip->lock);
418 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
419 cfgs[i], sleep, glitch ? slpm : NULL);
420 spin_unlock(&nmk_chip->lock);
421 clk_disable(nmk_chip->clk);
425 nmk_gpio_glitch_slpm_restore(slpm);
427 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
433 * nmk_config_pin - configure a pin's mux attributes
434 * @cfg: pin confguration
436 * Configures a pin's mode (alternate function or GPIO), its pull up status,
437 * and its sleep mode based on the specified configuration. The @cfg is
438 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
439 * are constructed using, and can be further enhanced with, the macros in
442 * If a pin's mode is set to GPIO, it is configured as an input to avoid
443 * side-effects. The gpio can be manipulated later using standard GPIO API
446 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
448 return __nmk_config_pins(&cfg, 1, sleep);
450 EXPORT_SYMBOL(nmk_config_pin);
453 * nmk_config_pins - configure several pins at once
454 * @cfgs: array of pin configurations
455 * @num: number of elments in the array
457 * Configures several pins using nmk_config_pin(). Refer to that function for
458 * further information.
460 int nmk_config_pins(pin_cfg_t *cfgs, int num)
462 return __nmk_config_pins(cfgs, num, false);
464 EXPORT_SYMBOL(nmk_config_pins);
466 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
468 return __nmk_config_pins(cfgs, num, true);
470 EXPORT_SYMBOL(nmk_config_pins_sleep);
473 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
475 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
477 * This register is actually in the pinmux layer, not the GPIO block itself.
478 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
479 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
480 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
481 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
482 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
483 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
485 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
486 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
487 * entered) regardless of the altfunction selected. Also wake-up detection is
490 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
491 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
492 * (for altfunction GPIO) or respective on-chip peripherals (for other
493 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
495 * Note that enable_irq_wake() will automatically enable wakeup detection.
497 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
499 struct nmk_gpio_chip *nmk_chip;
502 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
506 clk_enable(nmk_chip->clk);
507 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
508 spin_lock(&nmk_chip->lock);
510 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
512 spin_unlock(&nmk_chip->lock);
513 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
514 clk_disable(nmk_chip->clk);
520 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
522 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
524 * Enables/disables pull up/down on a specified pin. This only takes effect if
525 * the pin is configured as an input (either explicitly or by the alternate
528 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
529 * configured as an input. Otherwise, due to the way the controller registers
530 * work, this function will change the value output on the pin.
532 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
534 struct nmk_gpio_chip *nmk_chip;
537 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
541 clk_enable(nmk_chip->clk);
542 spin_lock_irqsave(&nmk_chip->lock, flags);
543 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
544 spin_unlock_irqrestore(&nmk_chip->lock, flags);
545 clk_disable(nmk_chip->clk);
552 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
554 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
555 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
557 * Sets the mode of the specified pin to one of the alternate functions or
560 int nmk_gpio_set_mode(int gpio, int gpio_mode)
562 struct nmk_gpio_chip *nmk_chip;
565 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
569 clk_enable(nmk_chip->clk);
570 spin_lock_irqsave(&nmk_chip->lock, flags);
571 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
572 spin_unlock_irqrestore(&nmk_chip->lock, flags);
573 clk_disable(nmk_chip->clk);
577 EXPORT_SYMBOL(nmk_gpio_set_mode);
579 int nmk_gpio_get_mode(int gpio)
581 struct nmk_gpio_chip *nmk_chip;
582 u32 afunc, bfunc, bit;
584 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
588 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
590 clk_enable(nmk_chip->clk);
592 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
593 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
595 clk_disable(nmk_chip->clk);
597 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
599 EXPORT_SYMBOL(nmk_gpio_get_mode);
603 static inline int nmk_gpio_get_bitmask(int gpio)
605 return 1 << (gpio % NMK_GPIO_PER_CHIP);
608 static void nmk_gpio_irq_ack(struct irq_data *d)
610 struct nmk_gpio_chip *nmk_chip;
612 nmk_chip = irq_data_get_irq_chip_data(d);
616 clk_enable(nmk_chip->clk);
617 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
618 clk_disable(nmk_chip->clk);
621 enum nmk_gpio_irq_type {
626 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
627 int gpio, enum nmk_gpio_irq_type which,
630 u32 bitmask = nmk_gpio_get_bitmask(gpio);
636 if (which == NORMAL) {
637 rimscreg = NMK_GPIO_RIMSC;
638 fimscreg = NMK_GPIO_FIMSC;
639 rimscval = &nmk_chip->rimsc;
640 fimscval = &nmk_chip->fimsc;
642 rimscreg = NMK_GPIO_RWIMSC;
643 fimscreg = NMK_GPIO_FWIMSC;
644 rimscval = &nmk_chip->rwimsc;
645 fimscval = &nmk_chip->fwimsc;
648 /* we must individually set/clear the two edges */
649 if (nmk_chip->edge_rising & bitmask) {
651 *rimscval |= bitmask;
653 *rimscval &= ~bitmask;
654 writel(*rimscval, nmk_chip->addr + rimscreg);
656 if (nmk_chip->edge_falling & bitmask) {
658 *fimscval |= bitmask;
660 *fimscval &= ~bitmask;
661 writel(*fimscval, nmk_chip->addr + fimscreg);
665 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
669 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
670 * disabled, since setting SLPM to 1 increases power consumption, and
671 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
673 if (nmk_chip->sleepmode && on) {
674 __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base,
675 NMK_GPIO_SLPM_WAKEUP_ENABLE);
678 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
681 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
683 struct nmk_gpio_chip *nmk_chip;
687 nmk_chip = irq_data_get_irq_chip_data(d);
688 bitmask = nmk_gpio_get_bitmask(d->hwirq);
692 clk_enable(nmk_chip->clk);
693 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
694 spin_lock(&nmk_chip->lock);
696 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
698 if (!(nmk_chip->real_wake & bitmask))
699 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
701 spin_unlock(&nmk_chip->lock);
702 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
703 clk_disable(nmk_chip->clk);
708 static void nmk_gpio_irq_mask(struct irq_data *d)
710 nmk_gpio_irq_maskunmask(d, false);
713 static void nmk_gpio_irq_unmask(struct irq_data *d)
715 nmk_gpio_irq_maskunmask(d, true);
718 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
720 struct nmk_gpio_chip *nmk_chip;
724 nmk_chip = irq_data_get_irq_chip_data(d);
727 bitmask = nmk_gpio_get_bitmask(d->hwirq);
729 clk_enable(nmk_chip->clk);
730 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
731 spin_lock(&nmk_chip->lock);
733 if (irqd_irq_disabled(d))
734 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
737 nmk_chip->real_wake |= bitmask;
739 nmk_chip->real_wake &= ~bitmask;
741 spin_unlock(&nmk_chip->lock);
742 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
743 clk_disable(nmk_chip->clk);
748 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
750 bool enabled = !irqd_irq_disabled(d);
751 bool wake = irqd_is_wakeup_set(d);
752 struct nmk_gpio_chip *nmk_chip;
756 nmk_chip = irq_data_get_irq_chip_data(d);
757 bitmask = nmk_gpio_get_bitmask(d->hwirq);
760 if (type & IRQ_TYPE_LEVEL_HIGH)
762 if (type & IRQ_TYPE_LEVEL_LOW)
765 clk_enable(nmk_chip->clk);
766 spin_lock_irqsave(&nmk_chip->lock, flags);
769 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
772 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
774 nmk_chip->edge_rising &= ~bitmask;
775 if (type & IRQ_TYPE_EDGE_RISING)
776 nmk_chip->edge_rising |= bitmask;
778 nmk_chip->edge_falling &= ~bitmask;
779 if (type & IRQ_TYPE_EDGE_FALLING)
780 nmk_chip->edge_falling |= bitmask;
783 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
786 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
788 spin_unlock_irqrestore(&nmk_chip->lock, flags);
789 clk_disable(nmk_chip->clk);
794 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
796 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
798 clk_enable(nmk_chip->clk);
799 nmk_gpio_irq_unmask(d);
803 static void nmk_gpio_irq_shutdown(struct irq_data *d)
805 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
807 nmk_gpio_irq_mask(d);
808 clk_disable(nmk_chip->clk);
811 static struct irq_chip nmk_gpio_irq_chip = {
812 .name = "Nomadik-GPIO",
813 .irq_ack = nmk_gpio_irq_ack,
814 .irq_mask = nmk_gpio_irq_mask,
815 .irq_unmask = nmk_gpio_irq_unmask,
816 .irq_set_type = nmk_gpio_irq_set_type,
817 .irq_set_wake = nmk_gpio_irq_set_wake,
818 .irq_startup = nmk_gpio_irq_startup,
819 .irq_shutdown = nmk_gpio_irq_shutdown,
822 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
825 struct nmk_gpio_chip *nmk_chip;
826 struct irq_chip *host_chip = irq_get_chip(irq);
827 unsigned int first_irq;
829 chained_irq_enter(host_chip, desc);
831 nmk_chip = irq_get_handler_data(irq);
832 first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
834 int bit = __ffs(status);
836 generic_handle_irq(first_irq + bit);
840 chained_irq_exit(host_chip, desc);
843 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
845 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
848 clk_enable(nmk_chip->clk);
849 status = readl(nmk_chip->addr + NMK_GPIO_IS);
850 clk_disable(nmk_chip->clk);
852 __nmk_gpio_irq_handler(irq, desc, status);
855 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
856 struct irq_desc *desc)
858 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
859 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
861 __nmk_gpio_irq_handler(irq, desc, status);
864 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
866 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
867 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
869 if (nmk_chip->secondary_parent_irq >= 0) {
870 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
871 nmk_gpio_secondary_irq_handler);
872 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
880 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
883 * Map back to global GPIO space and request muxing, the direction
884 * parameter does not matter for this controller.
886 int gpio = chip->base + offset;
888 return pinctrl_request_gpio(gpio);
891 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
893 int gpio = chip->base + offset;
895 pinctrl_free_gpio(gpio);
898 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
900 struct nmk_gpio_chip *nmk_chip =
901 container_of(chip, struct nmk_gpio_chip, chip);
903 clk_enable(nmk_chip->clk);
905 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
907 clk_disable(nmk_chip->clk);
912 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
914 struct nmk_gpio_chip *nmk_chip =
915 container_of(chip, struct nmk_gpio_chip, chip);
916 u32 bit = 1 << offset;
919 clk_enable(nmk_chip->clk);
921 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
923 clk_disable(nmk_chip->clk);
928 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
931 struct nmk_gpio_chip *nmk_chip =
932 container_of(chip, struct nmk_gpio_chip, chip);
934 clk_enable(nmk_chip->clk);
936 __nmk_gpio_set_output(nmk_chip, offset, val);
938 clk_disable(nmk_chip->clk);
941 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
944 struct nmk_gpio_chip *nmk_chip =
945 container_of(chip, struct nmk_gpio_chip, chip);
947 clk_enable(nmk_chip->clk);
949 __nmk_gpio_make_output(nmk_chip, offset, val);
951 clk_disable(nmk_chip->clk);
956 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
958 struct nmk_gpio_chip *nmk_chip =
959 container_of(chip, struct nmk_gpio_chip, chip);
961 return irq_find_mapping(nmk_chip->domain, offset);
964 #ifdef CONFIG_DEBUG_FS
966 #include <linux/seq_file.h>
968 static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
969 unsigned offset, unsigned gpio)
971 const char *label = gpiochip_is_requested(chip, offset);
972 struct nmk_gpio_chip *nmk_chip =
973 container_of(chip, struct nmk_gpio_chip, chip);
977 u32 bit = 1 << offset;
978 const char *modes[] = {
979 [NMK_GPIO_ALT_GPIO] = "gpio",
980 [NMK_GPIO_ALT_A] = "altA",
981 [NMK_GPIO_ALT_B] = "altB",
982 [NMK_GPIO_ALT_C] = "altC",
985 clk_enable(nmk_chip->clk);
986 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
987 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
988 mode = nmk_gpio_get_mode(gpio);
990 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
991 gpio, label ?: "(none)",
992 is_out ? "out" : "in ",
994 ? (chip->get(chip, offset) ? "hi" : "lo")
996 (mode < 0) ? "unknown" : modes[mode],
997 pull ? "pull" : "none");
999 if (label && !is_out) {
1000 int irq = gpio_to_irq(gpio);
1001 struct irq_desc *desc = irq_to_desc(irq);
1003 /* This races with request_irq(), set_irq_type(),
1004 * and set_irq_wake() ... but those are "rare".
1006 if (irq >= 0 && desc->action) {
1008 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1010 if (nmk_chip->edge_rising & bitmask)
1011 trigger = "edge-rising";
1012 else if (nmk_chip->edge_falling & bitmask)
1013 trigger = "edge-falling";
1015 trigger = "edge-undefined";
1017 seq_printf(s, " irq-%d %s%s",
1019 irqd_is_wakeup_set(&desc->irq_data)
1023 clk_disable(nmk_chip->clk);
1026 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1029 unsigned gpio = chip->base;
1031 for (i = 0; i < chip->ngpio; i++, gpio++) {
1032 nmk_gpio_dbg_show_one(s, chip, i, gpio);
1033 seq_printf(s, "\n");
1038 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1039 struct gpio_chip *chip,
1040 unsigned offset, unsigned gpio)
1043 #define nmk_gpio_dbg_show NULL
1046 /* This structure is replicated for each GPIO block allocated at probe time */
1047 static struct gpio_chip nmk_gpio_template = {
1048 .request = nmk_gpio_request,
1049 .free = nmk_gpio_free,
1050 .direction_input = nmk_gpio_make_input,
1051 .get = nmk_gpio_get_input,
1052 .direction_output = nmk_gpio_make_output,
1053 .set = nmk_gpio_set_output,
1054 .to_irq = nmk_gpio_to_irq,
1055 .dbg_show = nmk_gpio_dbg_show,
1059 void nmk_gpio_clocks_enable(void)
1063 for (i = 0; i < NUM_BANKS; i++) {
1064 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1069 clk_enable(chip->clk);
1073 void nmk_gpio_clocks_disable(void)
1077 for (i = 0; i < NUM_BANKS; i++) {
1078 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1083 clk_disable(chip->clk);
1088 * Called from the suspend/resume path to only keep the real wakeup interrupts
1089 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1090 * and not the rest of the interrupts which we needed to have as wakeups for
1093 * PM ops are not used since this needs to be done at the end, after all the
1094 * other drivers are done with their suspend callbacks.
1096 void nmk_gpio_wakeups_suspend(void)
1100 for (i = 0; i < NUM_BANKS; i++) {
1101 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1106 clk_enable(chip->clk);
1108 writel(chip->rwimsc & chip->real_wake,
1109 chip->addr + NMK_GPIO_RWIMSC);
1110 writel(chip->fwimsc & chip->real_wake,
1111 chip->addr + NMK_GPIO_FWIMSC);
1113 clk_disable(chip->clk);
1117 void nmk_gpio_wakeups_resume(void)
1121 for (i = 0; i < NUM_BANKS; i++) {
1122 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1127 clk_enable(chip->clk);
1129 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1130 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1132 clk_disable(chip->clk);
1137 * Read the pull up/pull down status.
1138 * A bit set in 'pull_up' means that pull up
1139 * is selected if pull is enabled in PDIS register.
1140 * Note: only pull up/down set via this driver can
1141 * be detected due to HW limitations.
1143 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1145 if (gpio_bank < NUM_BANKS) {
1146 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1151 *pull_up = chip->pull_up;
1155 int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1156 irq_hw_number_t hwirq)
1158 struct nmk_gpio_chip *nmk_chip = d->host_data;
1163 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1164 set_irq_flags(irq, IRQF_VALID);
1165 irq_set_chip_data(irq, nmk_chip);
1166 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1171 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1172 .map = nmk_gpio_irq_map,
1173 .xlate = irq_domain_xlate_twocell,
1176 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1178 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1179 struct device_node *np = dev->dev.of_node;
1180 struct nmk_gpio_chip *nmk_chip;
1181 struct gpio_chip *chip;
1182 struct resource *res;
1189 if (!pdata && !np) {
1190 dev_err(&dev->dev, "No platform data or device tree found\n");
1195 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1199 if (of_get_property(np, "supports-sleepmode", NULL))
1200 pdata->supports_sleepmode = true;
1202 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1203 dev_err(&dev->dev, "gpio-bank property not found\n");
1208 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1209 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1212 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1218 irq = platform_get_irq(dev, 0);
1224 secondary_irq = platform_get_irq(dev, 1);
1225 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1230 if (request_mem_region(res->start, resource_size(res),
1231 dev_name(&dev->dev)) == NULL) {
1236 base = ioremap(res->start, resource_size(res));
1242 clk = clk_get(&dev->dev, NULL);
1248 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1255 * The virt address in nmk_chip->addr is in the nomadik register space,
1256 * so we can simply convert the resource address, without remapping
1258 nmk_chip->bank = dev->id;
1259 nmk_chip->clk = clk;
1260 nmk_chip->addr = base;
1261 nmk_chip->chip = nmk_gpio_template;
1262 nmk_chip->parent_irq = irq;
1263 nmk_chip->secondary_parent_irq = secondary_irq;
1264 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1265 nmk_chip->set_ioforce = pdata->set_ioforce;
1266 nmk_chip->sleepmode = pdata->supports_sleepmode;
1267 spin_lock_init(&nmk_chip->lock);
1269 chip = &nmk_chip->chip;
1270 chip->base = pdata->first_gpio;
1271 chip->ngpio = pdata->num_gpio;
1272 chip->label = pdata->name ?: dev_name(&dev->dev);
1273 chip->dev = &dev->dev;
1274 chip->owner = THIS_MODULE;
1276 clk_enable(nmk_chip->clk);
1277 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1278 clk_disable(nmk_chip->clk);
1280 #ifdef CONFIG_OF_GPIO
1284 ret = gpiochip_add(&nmk_chip->chip);
1288 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1290 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1292 platform_set_drvdata(dev, nmk_chip);
1294 nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
1295 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1296 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1297 if (!nmk_chip->domain) {
1298 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1303 nmk_gpio_init_irq(nmk_chip);
1305 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1317 release_mem_region(res->start, resource_size(res));
1319 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1320 pdata->first_gpio, pdata->first_gpio+31);
1327 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1329 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1331 return npct->soc->ngroups;
1334 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1337 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1339 return npct->soc->groups[selector].name;
1342 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1343 const unsigned **pins,
1346 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1348 *pins = npct->soc->groups[selector].pins;
1349 *num_pins = npct->soc->groups[selector].npins;
1353 static struct pinctrl_gpio_range *
1354 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1356 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1359 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1360 struct pinctrl_gpio_range *range;
1362 range = &npct->soc->gpio_ranges[i];
1363 if (offset >= range->pin_base &&
1364 offset <= (range->pin_base + range->npins - 1))
1370 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1373 struct pinctrl_gpio_range *range;
1374 struct gpio_chip *chip;
1376 range = nmk_match_gpio_range(pctldev, offset);
1377 if (!range || !range->gc) {
1378 seq_printf(s, "invalid pin offset");
1382 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1385 static struct pinctrl_ops nmk_pinctrl_ops = {
1386 .get_groups_count = nmk_get_groups_cnt,
1387 .get_group_name = nmk_get_group_name,
1388 .get_group_pins = nmk_get_group_pins,
1389 .pin_dbg_show = nmk_pin_dbg_show,
1392 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1394 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1396 return npct->soc->nfunctions;
1399 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1402 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1404 return npct->soc->functions[function].name;
1407 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1409 const char * const **groups,
1410 unsigned * const num_groups)
1412 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1414 *groups = npct->soc->functions[function].groups;
1415 *num_groups = npct->soc->functions[function].ngroups;
1420 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1423 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1424 const struct nmk_pingroup *g;
1425 static unsigned int slpm[NUM_BANKS];
1426 unsigned long flags;
1431 g = &npct->soc->groups[group];
1433 if (g->altsetting < 0)
1436 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1438 /* Handle this special glitch on altfunction C */
1439 glitch = (g->altsetting == NMK_GPIO_ALT_C);
1442 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1444 /* Initially don't put any pins to sleep when switching */
1445 memset(slpm, 0xff, sizeof(slpm));
1448 * Then mask the pins that need to be sleeping now when we're
1449 * switching to the ALT C function.
1451 for (i = 0; i < g->npins; i++)
1452 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1453 nmk_gpio_glitch_slpm_init(slpm);
1456 for (i = 0; i < g->npins; i++) {
1457 struct pinctrl_gpio_range *range;
1458 struct nmk_gpio_chip *nmk_chip;
1459 struct gpio_chip *chip;
1462 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1465 "invalid pin offset %d in group %s at index %d\n",
1466 g->pins[i], g->name, i);
1470 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1471 g->pins[i], g->name, i);
1475 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1476 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1478 clk_enable(nmk_chip->clk);
1479 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1481 * If the pin is switching to altfunc, and there was an
1482 * interrupt installed on it which has been lazy disabled,
1483 * actually mask the interrupt to prevent spurious interrupts
1484 * that would occur while the pin is under control of the
1485 * peripheral. Only SKE does this.
1487 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1489 __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
1490 clk_disable(nmk_chip->clk);
1493 /* When all pins are successfully reconfigured we get here */
1498 nmk_gpio_glitch_slpm_restore(slpm);
1499 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1505 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1506 unsigned function, unsigned group)
1508 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1509 const struct nmk_pingroup *g;
1511 g = &npct->soc->groups[group];
1513 if (g->altsetting < 0)
1516 /* Poke out the mux, set the pin to some default state? */
1517 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1520 int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1521 struct pinctrl_gpio_range *range,
1524 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1525 struct nmk_gpio_chip *nmk_chip;
1526 struct gpio_chip *chip;
1530 dev_err(npct->dev, "invalid range\n");
1534 dev_err(npct->dev, "missing GPIO chip in range\n");
1538 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1540 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1542 clk_enable(nmk_chip->clk);
1543 bit = offset % NMK_GPIO_PER_CHIP;
1544 /* There is no glitch when converting any pin to GPIO */
1545 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1546 clk_disable(nmk_chip->clk);
1551 void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1552 struct pinctrl_gpio_range *range,
1555 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1557 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1558 /* Set the pin to some default state, GPIO is usually default */
1561 static struct pinmux_ops nmk_pinmux_ops = {
1562 .get_functions_count = nmk_pmx_get_funcs_cnt,
1563 .get_function_name = nmk_pmx_get_func_name,
1564 .get_function_groups = nmk_pmx_get_func_groups,
1565 .enable = nmk_pmx_enable,
1566 .disable = nmk_pmx_disable,
1567 .gpio_request_enable = nmk_gpio_request_enable,
1568 .gpio_disable_free = nmk_gpio_disable_free,
1571 static struct pinctrl_desc nmk_pinctrl_desc = {
1572 .name = "pinctrl-nomadik",
1573 .pctlops = &nmk_pinctrl_ops,
1574 .pmxops = &nmk_pinmux_ops,
1575 .owner = THIS_MODULE,
1578 static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1580 const struct platform_device_id *platid = platform_get_device_id(pdev);
1581 struct nmk_pinctrl *npct;
1584 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1588 /* Poke in other ASIC variants here */
1589 if (platid->driver_data == PINCTRL_NMK_DB8500)
1590 nmk_pinctrl_db8500_init(&npct->soc);
1593 * We need all the GPIO drivers to probe FIRST, or we will not be able
1594 * to obtain references to the struct gpio_chip * for them, and we
1595 * need this to proceed.
1597 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1598 if (!nmk_gpio_chips[i]) {
1599 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1600 devm_kfree(&pdev->dev, npct);
1601 return -EPROBE_DEFER;
1603 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1606 nmk_pinctrl_desc.pins = npct->soc->pins;
1607 nmk_pinctrl_desc.npins = npct->soc->npins;
1608 npct->dev = &pdev->dev;
1609 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1611 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1615 /* We will handle a range of GPIO pins */
1616 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1617 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1619 platform_set_drvdata(pdev, npct);
1620 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1625 static const struct of_device_id nmk_gpio_match[] = {
1626 { .compatible = "st,nomadik-gpio", },
1630 static struct platform_driver nmk_gpio_driver = {
1632 .owner = THIS_MODULE,
1634 .of_match_table = nmk_gpio_match,
1636 .probe = nmk_gpio_probe,
1639 static const struct platform_device_id nmk_pinctrl_id[] = {
1640 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1641 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1644 static struct platform_driver nmk_pinctrl_driver = {
1646 .owner = THIS_MODULE,
1647 .name = "pinctrl-nomadik",
1649 .probe = nmk_pinctrl_probe,
1650 .id_table = nmk_pinctrl_id,
1653 static int __init nmk_gpio_init(void)
1657 ret = platform_driver_register(&nmk_gpio_driver);
1660 return platform_driver_register(&nmk_pinctrl_driver);
1663 core_initcall(nmk_gpio_init);
1665 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1666 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1667 MODULE_LICENSE("GPL");