2 * r8a7791 processor support - PFC hardware block.
4 * Copyright (C) 2013 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/platform_data/gpio-rcar.h>
17 #define CPU_ALL_PORT(fn, sfx) \
18 PORT_GP_32(0, fn, sfx), \
19 PORT_GP_32(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_32(3, fn, sfx), \
22 PORT_GP_32(4, fn, sfx), \
23 PORT_GP_32(5, fn, sfx), \
24 PORT_GP_32(6, fn, sfx), \
25 PORT_GP_32(7, fn, sfx)
34 PINMUX_FUNCTION_BEGIN,
38 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
39 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
40 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
41 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
42 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
43 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
46 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
47 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
48 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
49 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
50 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
54 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
55 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
56 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
57 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
58 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
59 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
60 FN_IP6_5_3, FN_IP6_7_6,
63 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
64 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
65 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
66 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
67 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
68 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
72 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
73 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
74 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
75 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
76 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
77 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
78 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
79 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
82 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
83 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
84 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
85 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
86 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
87 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
88 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
91 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
92 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
93 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
94 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
95 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
96 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
97 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
98 FN_USB1_OVC, FN_DU0_DOTCLKIN,
101 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
102 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
103 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
104 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
105 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
106 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
109 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
110 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
111 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
112 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
113 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
114 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
117 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
118 FN_A9, FN_MSIOF1_SS2, FN_SDA0,
119 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
120 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
121 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
122 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
123 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
125 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
126 FN_A17, FN_DACK2_B, FN_SDA0_C,
127 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
130 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
132 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
133 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
134 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
135 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
136 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
137 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
138 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
139 FN_EX_CS1_N, FN_MSIOF2_SCK,
140 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
141 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
144 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
145 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
146 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
147 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
148 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
149 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
150 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
151 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
152 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
153 FN_DREQ0, FN_PWM3, FN_TPU_TO3,
154 FN_DACK0, FN_DRACK0, FN_REMOCON,
155 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
156 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
157 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
158 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
161 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
162 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
163 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
164 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
165 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
166 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
167 FN_GLO_Q1_D, FN_HCTS1_N_E,
168 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
169 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
170 FN_SSI_SCK4, FN_GLO_SS_D,
171 FN_SSI_WS4, FN_GLO_RFON_D,
172 FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
173 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
174 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
177 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
178 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
179 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
180 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
181 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
182 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
183 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
184 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
185 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
186 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
187 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
188 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
189 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
190 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
191 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
194 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
195 FN_SCIF_CLK, FN_BPFCLK_E,
196 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
197 FN_SCIFA2_RXD, FN_FMIN_E,
198 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
199 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
200 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
201 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
202 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
203 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
204 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
205 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
206 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
207 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
210 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
211 FN_SCIF_CLK_B, FN_GPS_MAG_D,
212 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
213 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
214 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
215 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
216 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
217 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
218 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
219 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
220 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
221 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
222 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
223 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
224 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
225 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
226 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
227 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
230 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
231 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
232 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
233 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
234 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
235 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
236 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
237 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
238 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
239 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
240 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
241 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
242 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
243 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
244 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
245 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
246 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
249 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
250 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
251 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
252 FN_DU1_DOTCLKOUT0, FN_QCLK,
253 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
254 FN_TX3_B, FN_SCL2_B, FN_PWM4,
255 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
256 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
257 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
258 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
259 FN_DU1_DISP, FN_QPOLA,
260 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
261 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
262 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
263 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
264 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
265 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
266 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
267 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
270 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
271 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
272 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
273 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
274 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
275 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
276 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
277 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
278 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
279 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
280 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
281 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
282 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
283 FN_TS_SDATA0_C, FN_ATACS11_N,
284 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
285 FN_TS_SCK0_C, FN_ATAG1_N,
286 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
287 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
288 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
291 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
292 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
293 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
294 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
295 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
296 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
297 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
298 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
299 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
300 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
301 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
302 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
303 FN_VI1_DATA7, FN_AVB_MDC,
304 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
305 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
308 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
309 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
310 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
311 FN_SCL2_D, FN_MSIOF1_RXD_E,
312 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
313 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
314 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
315 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
316 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
317 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
318 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
319 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
320 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
321 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
322 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
323 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
324 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
327 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
328 FN_ADICLK_B, FN_MSIOF0_SS1_C,
329 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
330 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
331 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
332 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
333 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
334 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
335 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
336 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
337 FN_SCIFA5_TXD_B, FN_TX3_C,
338 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
339 FN_SCIFA5_RXD_B, FN_RX3_C,
340 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
341 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
342 FN_SD1_DATA3, FN_IERX_B,
343 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
346 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
347 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
348 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
349 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
350 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
351 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
352 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
353 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
354 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
355 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
356 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
357 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
358 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
359 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
362 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
363 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
364 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
365 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
366 FN_PWM5_B, FN_SCIFA3_TXD_C,
367 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
368 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
369 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
370 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
371 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
372 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
373 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
374 FN_TCLK2, FN_VI1_DATA3_C,
375 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
376 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
379 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
380 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
381 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
382 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
383 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
386 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
387 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
388 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
389 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
390 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
391 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
392 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
393 FN_SEL_QSP_0, FN_SEL_QSP_1,
394 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
395 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
397 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
398 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
399 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
400 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
401 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
404 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
406 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
407 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
408 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
409 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
410 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
411 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
412 FN_SEL_ADG_0, FN_SEL_ADG_1,
413 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
414 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
415 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
416 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
417 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
418 FN_SEL_SIM_0, FN_SEL_SIM_1,
419 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
422 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
423 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
424 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
425 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
426 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
427 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
428 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
429 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
430 FN_SEL_MMC_0, FN_SEL_MMC_1,
431 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
432 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
433 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
435 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
438 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
440 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
441 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
442 FN_SEL_RAD_0, FN_SEL_RAD_1,
443 FN_SEL_RCN_0, FN_SEL_RCN_1,
444 FN_SEL_RSP_0, FN_SEL_RSP_1,
445 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
447 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
449 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
450 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
451 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
456 EX_CS0_N_MARK, RD_N_MARK,
460 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
461 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
462 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
466 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
470 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
471 D6_MARK, D7_MARK, D8_MARK,
472 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
473 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
474 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
475 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
476 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
479 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
480 A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
481 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
482 A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
483 A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
484 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
485 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
486 A15_MARK, BPFCLK_C_MARK,
487 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
488 A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
489 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
492 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
493 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
494 A20_MARK, SPCLK_MARK,
495 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
496 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
497 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
498 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
499 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
500 RX1_MARK, SCIFA1_RXD_MARK,
501 CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
502 CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
503 EX_CS1_N_MARK, MSIOF2_SCK_MARK,
504 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
505 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
506 ATAG0_N_MARK, EX_WAIT1_MARK,
509 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
510 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
511 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
512 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
513 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
514 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
515 SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
516 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
517 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
518 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
519 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
520 DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
521 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
522 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
523 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
524 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
525 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
526 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
529 SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
530 SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
531 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
532 SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
533 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
534 SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
535 SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
536 SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
537 GLO_Q1_D_MARK, HCTS1_N_E_MARK,
538 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
539 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
540 SSI_SCK4_MARK, GLO_SS_D_MARK,
541 SSI_WS4_MARK, GLO_RFON_D_MARK,
542 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
543 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
544 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
547 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
548 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
549 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
550 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
551 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
552 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
553 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
554 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
555 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
556 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
557 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
558 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
559 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
560 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
561 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
564 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
565 SCIF_CLK_MARK, BPFCLK_E_MARK,
566 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
567 SCIFA2_RXD_MARK, FMIN_E_MARK,
568 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
569 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
570 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
571 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
572 IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
573 IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
574 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
575 IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
576 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
577 SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
578 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
579 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
580 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
581 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
584 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
585 SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
586 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
587 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
588 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
589 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
590 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
591 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
592 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
593 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
594 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
595 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
596 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
597 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
598 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
599 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
600 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
601 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
604 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
605 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
606 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
607 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
608 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
609 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
610 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
611 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
612 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
613 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
614 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
615 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
616 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
617 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
618 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
619 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
620 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
621 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
624 DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
625 DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
626 SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
627 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
628 DU1_DOTCLKOUT0_MARK, QCLK_MARK,
629 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
630 TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
631 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
632 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
633 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
634 CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
635 DU1_DISP_MARK, QPOLA_MARK,
636 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
637 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
638 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
639 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
640 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
641 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
642 VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
643 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
646 VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
647 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
648 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
649 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
650 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
651 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
652 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
653 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
654 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
655 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
656 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
657 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
658 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
659 TS_SDATA0_C_MARK, ATACS11_N_MARK,
660 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
661 TS_SCK0_C_MARK, ATAG1_N_MARK,
662 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
663 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
664 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
667 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
668 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
669 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
670 SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
671 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
672 TX4_B_MARK, SCIFA4_TXD_B_MARK,
673 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
674 RX4_B_MARK, SCIFA4_RXD_B_MARK,
675 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
676 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
677 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
678 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
679 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
680 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
681 VI1_DATA7_MARK, AVB_MDC_MARK,
682 ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
683 ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
686 ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
687 ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
688 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
689 SCL2_D_MARK, MSIOF1_RXD_E_MARK,
690 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
691 SDA2_D_MARK, MSIOF1_SCK_E_MARK,
692 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
693 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
694 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
695 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
696 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
697 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
698 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
699 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
700 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
701 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
702 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
703 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
706 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
707 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
708 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
709 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
710 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
711 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
712 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
713 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
714 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
715 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
716 SCIFA5_TXD_B_MARK, TX3_C_MARK,
717 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
718 SCIFA5_RXD_B_MARK, RX3_C_MARK,
719 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
720 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
721 SD1_DATA3_MARK, IERX_B_MARK,
722 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
725 SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
726 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
727 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
728 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
729 SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
730 SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
731 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
732 VI1_CLK_C_MARK, VI1_G0_B_MARK,
733 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
734 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
735 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
736 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
737 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
738 VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
739 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
740 VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
743 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
744 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
745 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
746 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
747 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
748 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
749 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
750 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
751 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
752 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
753 TCLK1_MARK, VI1_DATA1_C_MARK,
754 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
755 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
756 TCLK2_MARK, VI1_DATA3_C_MARK,
757 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
758 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
759 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
760 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
763 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
764 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
765 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
766 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
767 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
768 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
769 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
773 static const u16 pinmux_data[] = {
774 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
776 PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
777 PINMUX_DATA(RD_N_MARK, FN_RD_N),
778 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
779 PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
780 PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
781 PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
782 PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
783 PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
784 PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
785 PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
786 PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
787 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
788 PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
789 PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
790 PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
791 PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
792 PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
795 PINMUX_IPSR_DATA(IP0_0, D0),
796 PINMUX_IPSR_DATA(IP0_1, D1),
797 PINMUX_IPSR_DATA(IP0_2, D2),
798 PINMUX_IPSR_DATA(IP0_3, D3),
799 PINMUX_IPSR_DATA(IP0_4, D4),
800 PINMUX_IPSR_DATA(IP0_5, D5),
801 PINMUX_IPSR_DATA(IP0_6, D6),
802 PINMUX_IPSR_DATA(IP0_7, D7),
803 PINMUX_IPSR_DATA(IP0_8, D8),
804 PINMUX_IPSR_DATA(IP0_9, D9),
805 PINMUX_IPSR_DATA(IP0_10, D10),
806 PINMUX_IPSR_DATA(IP0_11, D11),
807 PINMUX_IPSR_DATA(IP0_12, D12),
808 PINMUX_IPSR_DATA(IP0_13, D13),
809 PINMUX_IPSR_DATA(IP0_14, D14),
810 PINMUX_IPSR_DATA(IP0_15, D15),
811 PINMUX_IPSR_DATA(IP0_18_16, A0),
812 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
813 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
814 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2),
815 PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
816 PINMUX_IPSR_DATA(IP0_20_19, A1),
817 PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
818 PINMUX_IPSR_DATA(IP0_22_21, A2),
819 PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
820 PINMUX_IPSR_DATA(IP0_24_23, A3),
821 PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
822 PINMUX_IPSR_DATA(IP0_26_25, A4),
823 PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
824 PINMUX_IPSR_DATA(IP0_28_27, A5),
825 PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
826 PINMUX_IPSR_DATA(IP0_30_29, A6),
827 PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
830 PINMUX_IPSR_DATA(IP1_1_0, A7),
831 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
832 PINMUX_IPSR_DATA(IP1_3_2, A8),
833 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
834 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0),
835 PINMUX_IPSR_DATA(IP1_5_4, A9),
836 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
837 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0),
838 PINMUX_IPSR_DATA(IP1_7_6, A10),
839 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
840 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
841 PINMUX_IPSR_DATA(IP1_10_8, A11),
842 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
843 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3),
844 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
845 PINMUX_IPSR_DATA(IP1_13_11, A12),
846 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0),
847 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3),
848 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
849 PINMUX_IPSR_DATA(IP1_16_14, A13),
850 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
851 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0),
852 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
853 PINMUX_IPSR_DATA(IP1_19_17, A14),
854 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
855 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0),
856 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2),
857 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
858 PINMUX_IPSR_DATA(IP1_22_20, A15),
859 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2),
860 PINMUX_IPSR_DATA(IP1_25_23, A16),
861 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1),
862 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2),
863 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
864 PINMUX_IPSR_DATA(IP1_28_26, A17),
865 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1),
866 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2),
867 PINMUX_IPSR_DATA(IP1_31_29, A18),
868 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0),
869 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
870 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
873 PINMUX_IPSR_DATA(IP2_2_0, A19),
874 PINMUX_IPSR_DATA(IP2_2_0, DACK1),
875 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
876 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
877 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0),
878 PINMUX_IPSR_DATA(IP2_2_0, A20),
879 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0),
880 PINMUX_IPSR_DATA(IP2_6_5, A21),
881 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
882 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0),
883 PINMUX_IPSR_DATA(IP2_9_7, A22),
884 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0),
885 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1),
886 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0),
887 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
888 PINMUX_IPSR_DATA(IP2_12_10, A23),
889 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0),
890 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1),
891 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0),
892 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
893 PINMUX_IPSR_DATA(IP2_15_13, A24),
894 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0),
895 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0),
896 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0),
897 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
898 PINMUX_IPSR_DATA(IP2_18_16, A25),
899 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0),
900 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0),
901 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2),
902 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0),
903 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
904 PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
905 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
906 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0),
907 PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
908 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
909 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0),
910 PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
911 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
912 PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
913 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0),
914 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
915 PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
916 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0),
917 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
918 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0),
919 PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
922 PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
923 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0),
924 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
925 PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
926 PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
927 PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
928 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
929 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
930 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
931 PINMUX_IPSR_DATA(IP3_5_3, PWM1),
932 PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
933 PINMUX_IPSR_DATA(IP3_8_6, BS_N),
934 PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
935 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
936 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
937 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
938 PINMUX_IPSR_DATA(IP3_8_6, PWM2),
939 PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
940 PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
941 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
942 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1),
943 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
944 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1),
945 PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
946 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
947 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
948 PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
949 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
950 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
951 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
952 PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
953 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
954 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
955 PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
956 PINMUX_IPSR_DATA(IP3_19_18, PWM3),
957 PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
958 PINMUX_IPSR_DATA(IP3_21_20, DACK0),
959 PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
960 PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0),
961 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0),
962 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
963 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
964 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
965 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
966 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2),
967 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
968 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
969 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
970 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
971 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
972 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
973 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
974 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
975 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
976 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
977 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
980 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
981 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1),
982 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1),
983 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
984 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
985 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1),
986 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1),
987 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
988 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3),
989 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0),
990 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1),
991 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1),
992 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
993 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3),
994 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
995 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1),
996 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1),
997 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
998 PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
999 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0),
1000 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1001 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1002 PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1003 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0),
1004 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1005 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4),
1006 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1007 PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1008 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1009 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4),
1010 PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1011 PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1012 PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1013 PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1014 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1015 PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1016 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1017 PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1018 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1019 PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1022 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0),
1023 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1024 PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1027 PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1028 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1029 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1030 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0),
1031 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1032 PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1033 PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1034 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1035 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1036 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0),
1037 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1038 PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1039 PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1040 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1041 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1042 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0),
1043 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1044 PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1045 PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1046 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1047 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1048 PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1049 PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1050 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1051 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1052 PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1053 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1054 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1055 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0),
1056 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1057 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3),
1058 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1059 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0),
1060 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1061 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3),
1062 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1063 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1064 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3),
1065 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1066 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1067 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3),
1068 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1070 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3),
1071 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1073 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1074 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3),
1075 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1078 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1079 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1080 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1081 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1082 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
1083 PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1084 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1085 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1086 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
1087 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1088 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
1089 PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1090 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1091 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
1092 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1093 PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1094 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1095 PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1096 PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1097 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1098 PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1099 PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1100 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1101 PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1102 PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1103 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
1104 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1105 PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1106 PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1107 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1108 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
1109 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1110 PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1111 PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1112 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1113 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
1114 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1115 PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1116 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1117 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1118 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
1119 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1120 PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1121 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1122 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1123 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1124 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1125 PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1126 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1127 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1128 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1129 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1132 PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1133 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1134 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1135 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1136 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1137 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1138 PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1139 PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1140 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1141 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1),
1142 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1143 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1144 PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1145 PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1146 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1147 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1),
1148 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1149 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1150 PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1151 PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1152 PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1153 PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1154 PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1155 PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1156 PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1157 PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1158 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1159 PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1160 PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1161 PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1162 PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1163 PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1164 PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1165 PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1166 PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1167 PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1168 PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1169 PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1170 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1171 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1),
1172 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1173 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1174 PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1175 PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1176 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1177 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1),
1178 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1179 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1180 PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1181 PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1182 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1183 PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1184 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1185 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1188 PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1189 PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1190 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1191 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1192 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1193 PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1194 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1195 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1196 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1197 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1198 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1199 PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1200 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1201 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1202 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1203 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1204 PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1205 PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1206 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1207 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1208 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1209 PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1210 PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1211 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1212 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1213 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1214 PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1215 PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1216 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1217 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1),
1218 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1219 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1220 PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1221 PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1222 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1223 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1),
1224 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1225 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1226 PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1227 PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1228 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1229 PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1230 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1231 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1232 PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1233 PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1234 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1235 PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1236 PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1237 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1238 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1239 PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1240 PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1241 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0),
1242 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1243 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1246 PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1247 PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1248 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2),
1249 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0),
1250 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1251 PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1252 PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1253 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2),
1254 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1255 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1256 PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1257 PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1258 PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1259 PINMUX_IPSR_DATA(IP9_7, QCLK),
1260 PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1261 PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1262 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1263 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1),
1264 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1),
1265 PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1266 PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1267 PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1268 PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1269 PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1270 PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1271 PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1272 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1273 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1),
1274 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1),
1275 PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1276 PINMUX_IPSR_DATA(IP9_16, QPOLA),
1277 PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1278 PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1279 PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1280 PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1281 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0),
1282 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1283 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1284 PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1285 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0),
1286 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1287 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1288 PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0),
1290 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1291 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1292 PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1293 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0),
1294 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1295 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1296 PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1297 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1299 PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1302 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0),
1303 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1304 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1305 PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1308 PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1309 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0),
1310 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1311 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0),
1312 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1313 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1314 PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1315 PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1316 PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1317 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1318 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1),
1319 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1321 PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1322 PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1323 PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1324 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1325 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1),
1326 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1328 PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1329 PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1330 PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1331 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1332 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1334 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1335 PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1336 PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1337 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1338 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3),
1339 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1340 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1341 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1342 PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1343 PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1344 PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3),
1345 PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1346 PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1347 PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3),
1348 PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1349 PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1350 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1351 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1352 PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1353 PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1354 PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1355 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1357 PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1358 PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1359 PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1360 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1361 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1362 PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1363 PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1364 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1365 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1366 PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1367 PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1368 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1369 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2),
1370 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3),
1373 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1374 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1375 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1376 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
1377 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
1378 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1379 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1380 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1381 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
1382 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
1383 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1384 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1385 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
1386 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1387 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
1388 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1389 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1390 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1391 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1392 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1393 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
1394 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1395 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1396 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1397 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1398 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
1399 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1400 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1401 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1402 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1403 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1404 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1405 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1406 PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
1407 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1408 PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
1409 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1410 PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
1411 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1412 PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
1413 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1414 PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
1415 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1416 PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
1417 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1418 PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
1419 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1420 PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
1421 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1422 PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
1423 PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1424 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1425 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1426 PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
1427 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1428 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1429 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
1432 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1433 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1434 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
1435 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
1436 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1437 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1438 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
1439 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
1440 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1441 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1442 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1443 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
1444 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1445 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1446 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1447 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1448 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
1449 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1450 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1451 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1452 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1453 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1454 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1455 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1456 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1457 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1458 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1459 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1460 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1461 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1462 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1463 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1464 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1465 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1466 PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
1467 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1468 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1469 PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
1470 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1471 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1472 PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
1473 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1474 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1475 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1476 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1477 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1479 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1480 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1481 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1482 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1485 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1486 PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1487 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1488 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
1489 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1490 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1491 PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1492 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1493 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1494 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1495 PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1496 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1497 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1498 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1499 PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1500 PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1501 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1502 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1503 PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1504 PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
1505 PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1506 PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1507 PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1508 PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
1509 PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1510 PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
1511 PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1512 PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
1513 PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1514 PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
1515 PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1516 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1517 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1518 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1519 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1520 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
1521 PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1522 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1523 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1524 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1525 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1526 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
1527 PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1528 PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
1529 PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1530 PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1531 PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1532 PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
1533 PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1534 PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
1535 PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1536 PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
1537 PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1538 PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1539 PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1540 PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
1543 PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1544 PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1545 PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
1546 PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1547 PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1548 PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1549 PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1550 PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1551 PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1552 PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1553 PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1554 PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1555 PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1556 PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1557 PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1558 PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1559 PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1560 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
1561 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
1562 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1563 PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1564 PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1565 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
1566 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
1567 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1568 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1569 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
1570 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
1571 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1572 PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1573 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1574 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
1575 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1576 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1577 PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1578 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1579 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
1580 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1581 PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1582 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1583 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
1584 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1585 PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1586 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1587 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
1588 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
1589 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
1590 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1591 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
1592 PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1593 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1594 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
1595 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
1596 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
1597 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1598 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
1599 PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1602 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
1603 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
1604 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1605 PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1606 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
1607 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1608 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
1609 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
1610 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1611 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
1612 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1613 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1614 PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1615 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1616 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1617 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
1618 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1619 PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1620 PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1621 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1622 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
1623 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
1624 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1625 PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1626 PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1627 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1628 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1629 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1630 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1631 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
1632 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1633 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1634 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1635 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1636 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1637 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1638 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1639 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1640 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1641 PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1642 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1643 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
1644 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1645 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1646 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1647 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1648 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
1649 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1650 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1651 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1652 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1655 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
1656 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1657 PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1658 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1659 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1660 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
1661 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1662 PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1663 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1664 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1665 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1666 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1667 PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
1668 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1669 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1670 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1671 PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1672 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1673 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1674 PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1675 PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1676 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1679 static const struct sh_pfc_pin pinmux_pins[] = {
1680 PINMUX_GPIO_GP_ALL(),
1683 /* - DU --------------------------------------------------------------------- */
1684 static const unsigned int du_rgb666_pins[] = {
1685 /* R[7:2], G[7:2], B[7:2] */
1686 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1687 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1688 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1689 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1690 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1691 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1693 static const unsigned int du_rgb666_mux[] = {
1694 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1695 DU1_DR3_MARK, DU1_DR2_MARK,
1696 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1697 DU1_DG3_MARK, DU1_DG2_MARK,
1698 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1699 DU1_DB3_MARK, DU1_DB2_MARK,
1701 static const unsigned int du_rgb888_pins[] = {
1702 /* R[7:0], G[7:0], B[7:0] */
1703 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1704 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1705 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1706 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1707 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1708 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1709 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1710 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1711 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1713 static const unsigned int du_rgb888_mux[] = {
1714 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1715 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1716 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1717 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1718 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1719 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1721 static const unsigned int du_clk_out_0_pins[] = {
1725 static const unsigned int du_clk_out_0_mux[] = {
1728 static const unsigned int du_clk_out_1_pins[] = {
1732 static const unsigned int du_clk_out_1_mux[] = {
1735 static const unsigned int du_sync_pins[] = {
1736 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */
1737 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1739 static const unsigned int du_sync_mux[] = {
1740 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1741 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1743 static const unsigned int du_cde_disp_pins[] = {
1745 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1747 static const unsigned int du_cde_disp_mux[] = {
1748 DU1_CDE_MARK, DU1_DISP_MARK
1750 static const unsigned int du0_clk_in_pins[] = {
1754 static const unsigned int du0_clk_in_mux[] = {
1757 static const unsigned int du1_clk_in_pins[] = {
1761 static const unsigned int du1_clk_in_mux[] = {
1764 static const unsigned int du1_clk_in_b_pins[] = {
1768 static const unsigned int du1_clk_in_b_mux[] = {
1769 DU1_DOTCLKIN_B_MARK,
1771 static const unsigned int du1_clk_in_c_pins[] = {
1775 static const unsigned int du1_clk_in_c_mux[] = {
1776 DU1_DOTCLKIN_C_MARK,
1778 /* - ETH -------------------------------------------------------------------- */
1779 static const unsigned int eth_link_pins[] = {
1783 static const unsigned int eth_link_mux[] = {
1786 static const unsigned int eth_magic_pins[] = {
1790 static const unsigned int eth_magic_mux[] = {
1793 static const unsigned int eth_mdio_pins[] = {
1795 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1797 static const unsigned int eth_mdio_mux[] = {
1798 ETH_MDC_MARK, ETH_MDIO_MARK,
1800 static const unsigned int eth_rmii_pins[] = {
1801 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1802 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
1803 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
1804 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
1806 static const unsigned int eth_rmii_mux[] = {
1807 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1808 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1810 /* - I2C0 ------------------------------------------------------------------- */
1811 static const unsigned int i2c0_pins[] = {
1813 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
1815 static const unsigned int i2c0_mux[] = {
1816 SCL0_MARK, SDA0_MARK,
1818 static const unsigned int i2c0_b_pins[] = {
1820 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1822 static const unsigned int i2c0_b_mux[] = {
1823 SCL0_B_MARK, SDA0_B_MARK,
1825 static const unsigned int i2c0_c_pins[] = {
1827 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
1829 static const unsigned int i2c0_c_mux[] = {
1830 SCL0_C_MARK, SDA0_C_MARK,
1832 /* - I2C1 ------------------------------------------------------------------- */
1833 static const unsigned int i2c1_pins[] = {
1835 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1837 static const unsigned int i2c1_mux[] = {
1838 SCL1_MARK, SDA1_MARK,
1840 static const unsigned int i2c1_b_pins[] = {
1842 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1844 static const unsigned int i2c1_b_mux[] = {
1845 SCL1_B_MARK, SDA1_B_MARK,
1847 static const unsigned int i2c1_c_pins[] = {
1849 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1851 static const unsigned int i2c1_c_mux[] = {
1852 SCL1_C_MARK, SDA1_C_MARK,
1854 static const unsigned int i2c1_d_pins[] = {
1856 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1858 static const unsigned int i2c1_d_mux[] = {
1859 SCL1_D_MARK, SDA1_D_MARK,
1861 static const unsigned int i2c1_e_pins[] = {
1863 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
1865 static const unsigned int i2c1_e_mux[] = {
1866 SCL1_E_MARK, SDA1_E_MARK,
1868 /* - I2C2 ------------------------------------------------------------------- */
1869 static const unsigned int i2c2_pins[] = {
1871 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1873 static const unsigned int i2c2_mux[] = {
1874 SCL2_MARK, SDA2_MARK,
1876 static const unsigned int i2c2_b_pins[] = {
1878 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1880 static const unsigned int i2c2_b_mux[] = {
1881 SCL2_B_MARK, SDA2_B_MARK,
1883 static const unsigned int i2c2_c_pins[] = {
1885 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1887 static const unsigned int i2c2_c_mux[] = {
1888 SCL2_C_MARK, SDA2_C_MARK,
1890 static const unsigned int i2c2_d_pins[] = {
1892 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1894 static const unsigned int i2c2_d_mux[] = {
1895 SCL2_D_MARK, SDA2_D_MARK,
1897 /* - I2C3 ------------------------------------------------------------------- */
1898 static const unsigned int i2c3_pins[] = {
1900 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1902 static const unsigned int i2c3_mux[] = {
1903 SCL3_MARK, SDA3_MARK,
1905 static const unsigned int i2c3_b_pins[] = {
1907 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1909 static const unsigned int i2c3_b_mux[] = {
1910 SCL3_B_MARK, SDA3_B_MARK,
1912 static const unsigned int i2c3_c_pins[] = {
1914 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
1916 static const unsigned int i2c3_c_mux[] = {
1917 SCL3_C_MARK, SDA3_C_MARK,
1919 static const unsigned int i2c3_d_pins[] = {
1921 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1923 static const unsigned int i2c3_d_mux[] = {
1924 SCL3_D_MARK, SDA3_D_MARK,
1926 /* - I2C4 ------------------------------------------------------------------- */
1927 static const unsigned int i2c4_pins[] = {
1929 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1931 static const unsigned int i2c4_mux[] = {
1932 SCL4_MARK, SDA4_MARK,
1934 static const unsigned int i2c4_b_pins[] = {
1936 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
1938 static const unsigned int i2c4_b_mux[] = {
1939 SCL4_B_MARK, SDA4_B_MARK,
1941 static const unsigned int i2c4_c_pins[] = {
1943 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1945 static const unsigned int i2c4_c_mux[] = {
1946 SCL4_C_MARK, SDA4_C_MARK,
1948 /* - INTC ------------------------------------------------------------------- */
1949 static const unsigned int intc_irq0_pins[] = {
1953 static const unsigned int intc_irq0_mux[] = {
1956 static const unsigned int intc_irq1_pins[] = {
1960 static const unsigned int intc_irq1_mux[] = {
1963 static const unsigned int intc_irq2_pins[] = {
1967 static const unsigned int intc_irq2_mux[] = {
1970 static const unsigned int intc_irq3_pins[] = {
1974 static const unsigned int intc_irq3_mux[] = {
1977 /* - MMCIF ------------------------------------------------------------------ */
1978 static const unsigned int mmc_data1_pins[] = {
1982 static const unsigned int mmc_data1_mux[] = {
1985 static const unsigned int mmc_data4_pins[] = {
1987 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1988 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1990 static const unsigned int mmc_data4_mux[] = {
1991 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1993 static const unsigned int mmc_data8_pins[] = {
1995 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1996 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1997 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1998 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2000 static const unsigned int mmc_data8_mux[] = {
2001 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2002 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2004 static const unsigned int mmc_ctrl_pins[] = {
2006 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2008 static const unsigned int mmc_ctrl_mux[] = {
2009 MMC_CLK_MARK, MMC_CMD_MARK,
2011 /* - MSIOF0 ----------------------------------------------------------------- */
2012 static const unsigned int msiof0_clk_pins[] = {
2016 static const unsigned int msiof0_clk_mux[] = {
2019 static const unsigned int msiof0_sync_pins[] = {
2023 static const unsigned int msiof0_sync_mux[] = {
2026 static const unsigned int msiof0_ss1_pins[] = {
2030 static const unsigned int msiof0_ss1_mux[] = {
2033 static const unsigned int msiof0_ss2_pins[] = {
2037 static const unsigned int msiof0_ss2_mux[] = {
2040 static const unsigned int msiof0_rx_pins[] = {
2044 static const unsigned int msiof0_rx_mux[] = {
2047 static const unsigned int msiof0_tx_pins[] = {
2051 static const unsigned int msiof0_tx_mux[] = {
2054 /* - MSIOF1 ----------------------------------------------------------------- */
2055 static const unsigned int msiof1_clk_pins[] = {
2059 static const unsigned int msiof1_clk_mux[] = {
2062 static const unsigned int msiof1_sync_pins[] = {
2066 static const unsigned int msiof1_sync_mux[] = {
2069 static const unsigned int msiof1_ss1_pins[] = {
2073 static const unsigned int msiof1_ss1_mux[] = {
2076 static const unsigned int msiof1_ss2_pins[] = {
2080 static const unsigned int msiof1_ss2_mux[] = {
2083 static const unsigned int msiof1_rx_pins[] = {
2087 static const unsigned int msiof1_rx_mux[] = {
2090 static const unsigned int msiof1_tx_pins[] = {
2094 static const unsigned int msiof1_tx_mux[] = {
2097 /* - MSIOF2 ----------------------------------------------------------------- */
2098 static const unsigned int msiof2_clk_pins[] = {
2102 static const unsigned int msiof2_clk_mux[] = {
2105 static const unsigned int msiof2_sync_pins[] = {
2109 static const unsigned int msiof2_sync_mux[] = {
2112 static const unsigned int msiof2_ss1_pins[] = {
2116 static const unsigned int msiof2_ss1_mux[] = {
2119 static const unsigned int msiof2_ss2_pins[] = {
2123 static const unsigned int msiof2_ss2_mux[] = {
2126 static const unsigned int msiof2_rx_pins[] = {
2130 static const unsigned int msiof2_rx_mux[] = {
2133 static const unsigned int msiof2_tx_pins[] = {
2137 static const unsigned int msiof2_tx_mux[] = {
2140 /* - SCIF0 ------------------------------------------------------------------ */
2141 static const unsigned int scif0_data_pins[] = {
2143 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2145 static const unsigned int scif0_data_mux[] = {
2148 static const unsigned int scif0_data_b_pins[] = {
2150 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2152 static const unsigned int scif0_data_b_mux[] = {
2153 RX0_B_MARK, TX0_B_MARK,
2155 static const unsigned int scif0_data_c_pins[] = {
2157 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
2159 static const unsigned int scif0_data_c_mux[] = {
2160 RX0_C_MARK, TX0_C_MARK,
2162 static const unsigned int scif0_data_d_pins[] = {
2164 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2166 static const unsigned int scif0_data_d_mux[] = {
2167 RX0_D_MARK, TX0_D_MARK,
2169 static const unsigned int scif0_data_e_pins[] = {
2171 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
2173 static const unsigned int scif0_data_e_mux[] = {
2174 RX0_E_MARK, TX0_E_MARK,
2176 /* - SCIF1 ------------------------------------------------------------------ */
2177 static const unsigned int scif1_data_pins[] = {
2179 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2181 static const unsigned int scif1_data_mux[] = {
2184 static const unsigned int scif1_data_b_pins[] = {
2186 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2188 static const unsigned int scif1_data_b_mux[] = {
2189 RX1_B_MARK, TX1_B_MARK,
2191 static const unsigned int scif1_clk_b_pins[] = {
2195 static const unsigned int scif1_clk_b_mux[] = {
2198 static const unsigned int scif1_data_c_pins[] = {
2200 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
2202 static const unsigned int scif1_data_c_mux[] = {
2203 RX1_C_MARK, TX1_C_MARK,
2205 static const unsigned int scif1_data_d_pins[] = {
2207 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
2209 static const unsigned int scif1_data_d_mux[] = {
2210 RX1_D_MARK, TX1_D_MARK,
2212 /* - SCIF2 ------------------------------------------------------------------ */
2213 static const unsigned int scif2_data_pins[] = {
2215 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2217 static const unsigned int scif2_data_mux[] = {
2220 static const unsigned int scif2_data_b_pins[] = {
2222 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2224 static const unsigned int scif2_data_b_mux[] = {
2225 RX2_B_MARK, TX2_B_MARK,
2227 static const unsigned int scif2_clk_b_pins[] = {
2231 static const unsigned int scif2_clk_b_mux[] = {
2234 static const unsigned int scif2_data_c_pins[] = {
2236 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2238 static const unsigned int scif2_data_c_mux[] = {
2239 RX2_C_MARK, TX2_C_MARK,
2241 static const unsigned int scif2_data_e_pins[] = {
2243 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2245 static const unsigned int scif2_data_e_mux[] = {
2246 RX2_E_MARK, TX2_E_MARK,
2248 /* - SCIF3 ------------------------------------------------------------------ */
2249 static const unsigned int scif3_data_pins[] = {
2251 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2253 static const unsigned int scif3_data_mux[] = {
2256 static const unsigned int scif3_clk_pins[] = {
2260 static const unsigned int scif3_clk_mux[] = {
2263 static const unsigned int scif3_data_b_pins[] = {
2265 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
2267 static const unsigned int scif3_data_b_mux[] = {
2268 RX3_B_MARK, TX3_B_MARK,
2270 static const unsigned int scif3_clk_b_pins[] = {
2274 static const unsigned int scif3_clk_b_mux[] = {
2277 static const unsigned int scif3_data_c_pins[] = {
2279 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2281 static const unsigned int scif3_data_c_mux[] = {
2282 RX3_C_MARK, TX3_C_MARK,
2284 static const unsigned int scif3_data_d_pins[] = {
2286 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
2288 static const unsigned int scif3_data_d_mux[] = {
2289 RX3_D_MARK, TX3_D_MARK,
2291 /* - SCIF4 ------------------------------------------------------------------ */
2292 static const unsigned int scif4_data_pins[] = {
2294 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2296 static const unsigned int scif4_data_mux[] = {
2299 static const unsigned int scif4_data_b_pins[] = {
2301 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2303 static const unsigned int scif4_data_b_mux[] = {
2304 RX4_B_MARK, TX4_B_MARK,
2306 static const unsigned int scif4_data_c_pins[] = {
2308 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2310 static const unsigned int scif4_data_c_mux[] = {
2311 RX4_C_MARK, TX4_C_MARK,
2313 /* - SCIF5 ------------------------------------------------------------------ */
2314 static const unsigned int scif5_data_pins[] = {
2316 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2318 static const unsigned int scif5_data_mux[] = {
2321 static const unsigned int scif5_data_b_pins[] = {
2323 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2325 static const unsigned int scif5_data_b_mux[] = {
2326 RX5_B_MARK, TX5_B_MARK,
2328 /* - SCIFA0 ----------------------------------------------------------------- */
2329 static const unsigned int scifa0_data_pins[] = {
2331 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2333 static const unsigned int scifa0_data_mux[] = {
2334 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2336 static const unsigned int scifa0_data_b_pins[] = {
2338 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2340 static const unsigned int scifa0_data_b_mux[] = {
2341 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2343 /* - SCIFA1 ----------------------------------------------------------------- */
2344 static const unsigned int scifa1_data_pins[] = {
2346 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2348 static const unsigned int scifa1_data_mux[] = {
2349 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2351 static const unsigned int scifa1_clk_pins[] = {
2355 static const unsigned int scifa1_clk_mux[] = {
2358 static const unsigned int scifa1_data_b_pins[] = {
2360 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2362 static const unsigned int scifa1_data_b_mux[] = {
2363 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2365 static const unsigned int scifa1_clk_b_pins[] = {
2369 static const unsigned int scifa1_clk_b_mux[] = {
2372 static const unsigned int scifa1_data_c_pins[] = {
2374 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2376 static const unsigned int scifa1_data_c_mux[] = {
2377 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2379 /* - SCIFA2 ----------------------------------------------------------------- */
2380 static const unsigned int scifa2_data_pins[] = {
2382 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2384 static const unsigned int scifa2_data_mux[] = {
2385 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2387 static const unsigned int scifa2_clk_pins[] = {
2391 static const unsigned int scifa2_clk_mux[] = {
2394 static const unsigned int scifa2_data_b_pins[] = {
2396 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2398 static const unsigned int scifa2_data_b_mux[] = {
2399 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2401 /* - SCIFA3 ----------------------------------------------------------------- */
2402 static const unsigned int scifa3_data_pins[] = {
2404 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2406 static const unsigned int scifa3_data_mux[] = {
2407 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2409 static const unsigned int scifa3_clk_pins[] = {
2413 static const unsigned int scifa3_clk_mux[] = {
2416 static const unsigned int scifa3_data_b_pins[] = {
2418 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
2420 static const unsigned int scifa3_data_b_mux[] = {
2421 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2423 static const unsigned int scifa3_clk_b_pins[] = {
2427 static const unsigned int scifa3_clk_b_mux[] = {
2430 static const unsigned int scifa3_data_c_pins[] = {
2432 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
2434 static const unsigned int scifa3_data_c_mux[] = {
2435 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
2437 static const unsigned int scifa3_clk_c_pins[] = {
2441 static const unsigned int scifa3_clk_c_mux[] = {
2444 /* - SCIFA4 ----------------------------------------------------------------- */
2445 static const unsigned int scifa4_data_pins[] = {
2447 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2449 static const unsigned int scifa4_data_mux[] = {
2450 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2452 static const unsigned int scifa4_data_b_pins[] = {
2454 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2456 static const unsigned int scifa4_data_b_mux[] = {
2457 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2459 static const unsigned int scifa4_data_c_pins[] = {
2461 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2463 static const unsigned int scifa4_data_c_mux[] = {
2464 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2466 /* - SCIFA5 ----------------------------------------------------------------- */
2467 static const unsigned int scifa5_data_pins[] = {
2469 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2471 static const unsigned int scifa5_data_mux[] = {
2472 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2474 static const unsigned int scifa5_data_b_pins[] = {
2476 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2478 static const unsigned int scifa5_data_b_mux[] = {
2479 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2481 static const unsigned int scifa5_data_c_pins[] = {
2483 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2485 static const unsigned int scifa5_data_c_mux[] = {
2486 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2488 /* - SCIFB0 ----------------------------------------------------------------- */
2489 static const unsigned int scifb0_data_pins[] = {
2491 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2493 static const unsigned int scifb0_data_mux[] = {
2494 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2496 static const unsigned int scifb0_clk_pins[] = {
2500 static const unsigned int scifb0_clk_mux[] = {
2503 static const unsigned int scifb0_ctrl_pins[] = {
2505 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2507 static const unsigned int scifb0_ctrl_mux[] = {
2508 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2510 static const unsigned int scifb0_data_b_pins[] = {
2512 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2514 static const unsigned int scifb0_data_b_mux[] = {
2515 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2517 static const unsigned int scifb0_clk_b_pins[] = {
2521 static const unsigned int scifb0_clk_b_mux[] = {
2524 static const unsigned int scifb0_ctrl_b_pins[] = {
2526 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
2528 static const unsigned int scifb0_ctrl_b_mux[] = {
2529 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2531 static const unsigned int scifb0_data_c_pins[] = {
2533 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2535 static const unsigned int scifb0_data_c_mux[] = {
2536 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2538 static const unsigned int scifb0_clk_c_pins[] = {
2542 static const unsigned int scifb0_clk_c_mux[] = {
2545 static const unsigned int scifb0_data_d_pins[] = {
2547 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2549 static const unsigned int scifb0_data_d_mux[] = {
2550 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
2552 static const unsigned int scifb0_clk_d_pins[] = {
2556 static const unsigned int scifb0_clk_d_mux[] = {
2559 /* - SCIFB1 ----------------------------------------------------------------- */
2560 static const unsigned int scifb1_data_pins[] = {
2562 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2564 static const unsigned int scifb1_data_mux[] = {
2565 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2567 static const unsigned int scifb1_clk_pins[] = {
2571 static const unsigned int scifb1_clk_mux[] = {
2574 static const unsigned int scifb1_ctrl_pins[] = {
2576 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2578 static const unsigned int scifb1_ctrl_mux[] = {
2579 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2581 static const unsigned int scifb1_data_b_pins[] = {
2583 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2585 static const unsigned int scifb1_data_b_mux[] = {
2586 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2588 static const unsigned int scifb1_clk_b_pins[] = {
2592 static const unsigned int scifb1_clk_b_mux[] = {
2595 static const unsigned int scifb1_data_c_pins[] = {
2597 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2599 static const unsigned int scifb1_data_c_mux[] = {
2600 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2602 static const unsigned int scifb1_clk_c_pins[] = {
2606 static const unsigned int scifb1_clk_c_mux[] = {
2609 static const unsigned int scifb1_data_d_pins[] = {
2611 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
2613 static const unsigned int scifb1_data_d_mux[] = {
2614 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2616 /* - SCIFB2 ----------------------------------------------------------------- */
2617 static const unsigned int scifb2_data_pins[] = {
2619 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2621 static const unsigned int scifb2_data_mux[] = {
2622 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2624 static const unsigned int scifb2_clk_pins[] = {
2628 static const unsigned int scifb2_clk_mux[] = {
2631 static const unsigned int scifb2_ctrl_pins[] = {
2633 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2635 static const unsigned int scifb2_ctrl_mux[] = {
2636 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2638 static const unsigned int scifb2_data_b_pins[] = {
2640 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2642 static const unsigned int scifb2_data_b_mux[] = {
2643 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
2645 static const unsigned int scifb2_clk_b_pins[] = {
2649 static const unsigned int scifb2_clk_b_mux[] = {
2652 static const unsigned int scifb2_ctrl_b_pins[] = {
2654 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2656 static const unsigned int scifb2_ctrl_b_mux[] = {
2657 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
2659 static const unsigned int scifb2_data_c_pins[] = {
2661 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2663 static const unsigned int scifb2_data_c_mux[] = {
2664 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2666 static const unsigned int scifb2_clk_c_pins[] = {
2670 static const unsigned int scifb2_clk_c_mux[] = {
2673 static const unsigned int scifb2_data_d_pins[] = {
2675 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
2677 static const unsigned int scifb2_data_d_mux[] = {
2678 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
2680 /* - SDHI0 ------------------------------------------------------------------ */
2681 static const unsigned int sdhi0_data1_pins[] = {
2685 static const unsigned int sdhi0_data1_mux[] = {
2688 static const unsigned int sdhi0_data4_pins[] = {
2690 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2691 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
2693 static const unsigned int sdhi0_data4_mux[] = {
2694 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
2696 static const unsigned int sdhi0_ctrl_pins[] = {
2698 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2700 static const unsigned int sdhi0_ctrl_mux[] = {
2701 SD0_CLK_MARK, SD0_CMD_MARK,
2703 static const unsigned int sdhi0_cd_pins[] = {
2707 static const unsigned int sdhi0_cd_mux[] = {
2710 static const unsigned int sdhi0_wp_pins[] = {
2714 static const unsigned int sdhi0_wp_mux[] = {
2717 /* - SDHI1 ------------------------------------------------------------------ */
2718 static const unsigned int sdhi1_data1_pins[] = {
2722 static const unsigned int sdhi1_data1_mux[] = {
2725 static const unsigned int sdhi1_data4_pins[] = {
2727 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
2728 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
2730 static const unsigned int sdhi1_data4_mux[] = {
2731 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
2733 static const unsigned int sdhi1_ctrl_pins[] = {
2735 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2737 static const unsigned int sdhi1_ctrl_mux[] = {
2738 SD1_CLK_MARK, SD1_CMD_MARK,
2740 static const unsigned int sdhi1_cd_pins[] = {
2744 static const unsigned int sdhi1_cd_mux[] = {
2747 static const unsigned int sdhi1_wp_pins[] = {
2751 static const unsigned int sdhi1_wp_mux[] = {
2754 /* - SDHI2 ------------------------------------------------------------------ */
2755 static const unsigned int sdhi2_data1_pins[] = {
2759 static const unsigned int sdhi2_data1_mux[] = {
2762 static const unsigned int sdhi2_data4_pins[] = {
2764 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2765 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2767 static const unsigned int sdhi2_data4_mux[] = {
2768 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
2770 static const unsigned int sdhi2_ctrl_pins[] = {
2772 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2774 static const unsigned int sdhi2_ctrl_mux[] = {
2775 SD2_CLK_MARK, SD2_CMD_MARK,
2777 static const unsigned int sdhi2_cd_pins[] = {
2781 static const unsigned int sdhi2_cd_mux[] = {
2784 static const unsigned int sdhi2_wp_pins[] = {
2788 static const unsigned int sdhi2_wp_mux[] = {
2791 /* - USB0 ------------------------------------------------------------------- */
2792 static const unsigned int usb0_pins[] = {
2793 RCAR_GP_PIN(7, 23), /* PWEN */
2794 RCAR_GP_PIN(7, 24), /* OVC */
2796 static const unsigned int usb0_mux[] = {
2800 /* - USB1 ------------------------------------------------------------------- */
2801 static const unsigned int usb1_pins[] = {
2802 RCAR_GP_PIN(7, 25), /* PWEN */
2803 RCAR_GP_PIN(6, 30), /* OVC */
2805 static const unsigned int usb1_mux[] = {
2811 unsigned int data24[24];
2812 unsigned int data20[20];
2813 unsigned int data16[16];
2814 unsigned int data12[12];
2815 unsigned int data10[10];
2816 unsigned int data8[8];
2819 #define VIN_DATA_PIN_GROUP(n, s) \
2822 .pins = n##_pins.data##s, \
2823 .mux = n##_mux.data##s, \
2824 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
2827 /* - VIN0 ------------------------------------------------------------------- */
2828 static const union vin_data vin0_data_pins = {
2831 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
2832 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
2833 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2834 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2836 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2837 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2838 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
2839 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
2841 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
2842 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
2843 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2844 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2847 static const union vin_data vin0_data_mux = {
2850 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2851 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2852 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2853 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2855 VI0_G0_MARK, VI0_G1_MARK,
2856 VI0_G2_MARK, VI0_G3_MARK,
2857 VI0_G4_MARK, VI0_G5_MARK,
2858 VI0_G6_MARK, VI0_G7_MARK,
2860 VI0_R0_MARK, VI0_R1_MARK,
2861 VI0_R2_MARK, VI0_R3_MARK,
2862 VI0_R4_MARK, VI0_R5_MARK,
2863 VI0_R6_MARK, VI0_R7_MARK,
2866 static const unsigned int vin0_data18_pins[] = {
2868 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
2869 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2870 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2872 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2873 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
2874 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
2876 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
2877 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2878 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2880 static const unsigned int vin0_data18_mux[] = {
2882 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2883 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2884 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2886 VI0_G2_MARK, VI0_G3_MARK,
2887 VI0_G4_MARK, VI0_G5_MARK,
2888 VI0_G6_MARK, VI0_G7_MARK,
2890 VI0_R2_MARK, VI0_R3_MARK,
2891 VI0_R4_MARK, VI0_R5_MARK,
2892 VI0_R6_MARK, VI0_R7_MARK,
2894 static const unsigned int vin0_sync_pins[] = {
2895 RCAR_GP_PIN(4, 3), /* HSYNC */
2896 RCAR_GP_PIN(4, 4), /* VSYNC */
2898 static const unsigned int vin0_sync_mux[] = {
2902 static const unsigned int vin0_field_pins[] = {
2905 static const unsigned int vin0_field_mux[] = {
2908 static const unsigned int vin0_clkenb_pins[] = {
2911 static const unsigned int vin0_clkenb_mux[] = {
2914 static const unsigned int vin0_clk_pins[] = {
2917 static const unsigned int vin0_clk_mux[] = {
2920 /* - VIN1 ----------------------------------------------------------------- */
2921 static const unsigned int vin1_data8_pins[] = {
2922 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2923 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
2924 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
2925 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2927 static const unsigned int vin1_data8_mux[] = {
2928 VI1_DATA0_MARK, VI1_DATA1_MARK,
2929 VI1_DATA2_MARK, VI1_DATA3_MARK,
2930 VI1_DATA4_MARK, VI1_DATA5_MARK,
2931 VI1_DATA6_MARK, VI1_DATA7_MARK,
2933 static const unsigned int vin1_sync_pins[] = {
2934 RCAR_GP_PIN(5, 0), /* HSYNC */
2935 RCAR_GP_PIN(5, 1), /* VSYNC */
2937 static const unsigned int vin1_sync_mux[] = {
2941 static const unsigned int vin1_field_pins[] = {
2944 static const unsigned int vin1_field_mux[] = {
2947 static const unsigned int vin1_clkenb_pins[] = {
2950 static const unsigned int vin1_clkenb_mux[] = {
2953 static const unsigned int vin1_clk_pins[] = {
2956 static const unsigned int vin1_clk_mux[] = {
2959 static const union vin_data vin1_b_data_pins = {
2962 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2963 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2964 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2965 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2967 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2968 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2969 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2970 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
2972 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2973 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
2974 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
2975 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
2978 static const union vin_data vin1_b_data_mux = {
2981 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
2982 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
2983 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
2984 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
2986 VI1_G0_B_MARK, VI1_G1_B_MARK,
2987 VI1_G2_B_MARK, VI1_G3_B_MARK,
2988 VI1_G4_B_MARK, VI1_G5_B_MARK,
2989 VI1_G6_B_MARK, VI1_G7_B_MARK,
2991 VI1_R0_B_MARK, VI1_R1_B_MARK,
2992 VI1_R2_B_MARK, VI1_R3_B_MARK,
2993 VI1_R4_B_MARK, VI1_R5_B_MARK,
2994 VI1_R6_B_MARK, VI1_R7_B_MARK,
2997 static const unsigned int vin1_b_data18_pins[] = {
2999 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3000 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3001 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3003 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3004 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3005 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3007 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3008 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3009 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3011 static const unsigned int vin1_b_data18_mux[] = {
3013 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3014 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3015 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3016 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3018 VI1_G0_B_MARK, VI1_G1_B_MARK,
3019 VI1_G2_B_MARK, VI1_G3_B_MARK,
3020 VI1_G4_B_MARK, VI1_G5_B_MARK,
3021 VI1_G6_B_MARK, VI1_G7_B_MARK,
3023 VI1_R0_B_MARK, VI1_R1_B_MARK,
3024 VI1_R2_B_MARK, VI1_R3_B_MARK,
3025 VI1_R4_B_MARK, VI1_R5_B_MARK,
3026 VI1_R6_B_MARK, VI1_R7_B_MARK,
3028 static const unsigned int vin1_b_sync_pins[] = {
3029 RCAR_GP_PIN(3, 17), /* HSYNC */
3030 RCAR_GP_PIN(3, 18), /* VSYNC */
3032 static const unsigned int vin1_b_sync_mux[] = {
3036 static const unsigned int vin1_b_field_pins[] = {
3039 static const unsigned int vin1_b_field_mux[] = {
3042 static const unsigned int vin1_b_clkenb_pins[] = {
3045 static const unsigned int vin1_b_clkenb_mux[] = {
3048 static const unsigned int vin1_b_clk_pins[] = {
3051 static const unsigned int vin1_b_clk_mux[] = {
3054 /* - VIN2 ----------------------------------------------------------------- */
3055 static const unsigned int vin2_data8_pins[] = {
3056 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3057 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3058 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3059 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
3061 static const unsigned int vin2_data8_mux[] = {
3062 VI2_DATA0_MARK, VI2_DATA1_MARK,
3063 VI2_DATA2_MARK, VI2_DATA3_MARK,
3064 VI2_DATA4_MARK, VI2_DATA5_MARK,
3065 VI2_DATA6_MARK, VI2_DATA7_MARK,
3067 static const unsigned int vin2_sync_pins[] = {
3068 RCAR_GP_PIN(4, 15), /* HSYNC */
3069 RCAR_GP_PIN(4, 16), /* VSYNC */
3071 static const unsigned int vin2_sync_mux[] = {
3075 static const unsigned int vin2_field_pins[] = {
3078 static const unsigned int vin2_field_mux[] = {
3081 static const unsigned int vin2_clkenb_pins[] = {
3084 static const unsigned int vin2_clkenb_mux[] = {
3087 static const unsigned int vin2_clk_pins[] = {
3090 static const unsigned int vin2_clk_mux[] = {
3094 static const struct sh_pfc_pin_group pinmux_groups[] = {
3095 SH_PFC_PIN_GROUP(du_rgb666),
3096 SH_PFC_PIN_GROUP(du_rgb888),
3097 SH_PFC_PIN_GROUP(du_clk_out_0),
3098 SH_PFC_PIN_GROUP(du_clk_out_1),
3099 SH_PFC_PIN_GROUP(du_sync),
3100 SH_PFC_PIN_GROUP(du_cde_disp),
3101 SH_PFC_PIN_GROUP(du0_clk_in),
3102 SH_PFC_PIN_GROUP(du1_clk_in),
3103 SH_PFC_PIN_GROUP(du1_clk_in_b),
3104 SH_PFC_PIN_GROUP(du1_clk_in_c),
3105 SH_PFC_PIN_GROUP(eth_link),
3106 SH_PFC_PIN_GROUP(eth_magic),
3107 SH_PFC_PIN_GROUP(eth_mdio),
3108 SH_PFC_PIN_GROUP(eth_rmii),
3109 SH_PFC_PIN_GROUP(i2c0),
3110 SH_PFC_PIN_GROUP(i2c0_b),
3111 SH_PFC_PIN_GROUP(i2c0_c),
3112 SH_PFC_PIN_GROUP(i2c1),
3113 SH_PFC_PIN_GROUP(i2c1_b),
3114 SH_PFC_PIN_GROUP(i2c1_c),
3115 SH_PFC_PIN_GROUP(i2c1_d),
3116 SH_PFC_PIN_GROUP(i2c1_e),
3117 SH_PFC_PIN_GROUP(i2c2),
3118 SH_PFC_PIN_GROUP(i2c2_b),
3119 SH_PFC_PIN_GROUP(i2c2_c),
3120 SH_PFC_PIN_GROUP(i2c2_d),
3121 SH_PFC_PIN_GROUP(i2c3),
3122 SH_PFC_PIN_GROUP(i2c3_b),
3123 SH_PFC_PIN_GROUP(i2c3_c),
3124 SH_PFC_PIN_GROUP(i2c3_d),
3125 SH_PFC_PIN_GROUP(i2c4),
3126 SH_PFC_PIN_GROUP(i2c4_b),
3127 SH_PFC_PIN_GROUP(i2c4_c),
3128 SH_PFC_PIN_GROUP(intc_irq0),
3129 SH_PFC_PIN_GROUP(intc_irq1),
3130 SH_PFC_PIN_GROUP(intc_irq2),
3131 SH_PFC_PIN_GROUP(intc_irq3),
3132 SH_PFC_PIN_GROUP(mmc_data1),
3133 SH_PFC_PIN_GROUP(mmc_data4),
3134 SH_PFC_PIN_GROUP(mmc_data8),
3135 SH_PFC_PIN_GROUP(mmc_ctrl),
3136 SH_PFC_PIN_GROUP(msiof0_clk),
3137 SH_PFC_PIN_GROUP(msiof0_sync),
3138 SH_PFC_PIN_GROUP(msiof0_ss1),
3139 SH_PFC_PIN_GROUP(msiof0_ss2),
3140 SH_PFC_PIN_GROUP(msiof0_rx),
3141 SH_PFC_PIN_GROUP(msiof0_tx),
3142 SH_PFC_PIN_GROUP(msiof1_clk),
3143 SH_PFC_PIN_GROUP(msiof1_sync),
3144 SH_PFC_PIN_GROUP(msiof1_ss1),
3145 SH_PFC_PIN_GROUP(msiof1_ss2),
3146 SH_PFC_PIN_GROUP(msiof1_rx),
3147 SH_PFC_PIN_GROUP(msiof1_tx),
3148 SH_PFC_PIN_GROUP(msiof2_clk),
3149 SH_PFC_PIN_GROUP(msiof2_sync),
3150 SH_PFC_PIN_GROUP(msiof2_ss1),
3151 SH_PFC_PIN_GROUP(msiof2_ss2),
3152 SH_PFC_PIN_GROUP(msiof2_rx),
3153 SH_PFC_PIN_GROUP(msiof2_tx),
3154 SH_PFC_PIN_GROUP(scif0_data),
3155 SH_PFC_PIN_GROUP(scif0_data_b),
3156 SH_PFC_PIN_GROUP(scif0_data_c),
3157 SH_PFC_PIN_GROUP(scif0_data_d),
3158 SH_PFC_PIN_GROUP(scif0_data_e),
3159 SH_PFC_PIN_GROUP(scif1_data),
3160 SH_PFC_PIN_GROUP(scif1_data_b),
3161 SH_PFC_PIN_GROUP(scif1_clk_b),
3162 SH_PFC_PIN_GROUP(scif1_data_c),
3163 SH_PFC_PIN_GROUP(scif1_data_d),
3164 SH_PFC_PIN_GROUP(scif2_data),
3165 SH_PFC_PIN_GROUP(scif2_data_b),
3166 SH_PFC_PIN_GROUP(scif2_clk_b),
3167 SH_PFC_PIN_GROUP(scif2_data_c),
3168 SH_PFC_PIN_GROUP(scif2_data_e),
3169 SH_PFC_PIN_GROUP(scif3_data),
3170 SH_PFC_PIN_GROUP(scif3_clk),
3171 SH_PFC_PIN_GROUP(scif3_data_b),
3172 SH_PFC_PIN_GROUP(scif3_clk_b),
3173 SH_PFC_PIN_GROUP(scif3_data_c),
3174 SH_PFC_PIN_GROUP(scif3_data_d),
3175 SH_PFC_PIN_GROUP(scif4_data),
3176 SH_PFC_PIN_GROUP(scif4_data_b),
3177 SH_PFC_PIN_GROUP(scif4_data_c),
3178 SH_PFC_PIN_GROUP(scif5_data),
3179 SH_PFC_PIN_GROUP(scif5_data_b),
3180 SH_PFC_PIN_GROUP(scifa0_data),
3181 SH_PFC_PIN_GROUP(scifa0_data_b),
3182 SH_PFC_PIN_GROUP(scifa1_data),
3183 SH_PFC_PIN_GROUP(scifa1_clk),
3184 SH_PFC_PIN_GROUP(scifa1_data_b),
3185 SH_PFC_PIN_GROUP(scifa1_clk_b),
3186 SH_PFC_PIN_GROUP(scifa1_data_c),
3187 SH_PFC_PIN_GROUP(scifa2_data),
3188 SH_PFC_PIN_GROUP(scifa2_clk),
3189 SH_PFC_PIN_GROUP(scifa2_data_b),
3190 SH_PFC_PIN_GROUP(scifa3_data),
3191 SH_PFC_PIN_GROUP(scifa3_clk),
3192 SH_PFC_PIN_GROUP(scifa3_data_b),
3193 SH_PFC_PIN_GROUP(scifa3_clk_b),
3194 SH_PFC_PIN_GROUP(scifa3_data_c),
3195 SH_PFC_PIN_GROUP(scifa3_clk_c),
3196 SH_PFC_PIN_GROUP(scifa4_data),
3197 SH_PFC_PIN_GROUP(scifa4_data_b),
3198 SH_PFC_PIN_GROUP(scifa4_data_c),
3199 SH_PFC_PIN_GROUP(scifa5_data),
3200 SH_PFC_PIN_GROUP(scifa5_data_b),
3201 SH_PFC_PIN_GROUP(scifa5_data_c),
3202 SH_PFC_PIN_GROUP(scifb0_data),
3203 SH_PFC_PIN_GROUP(scifb0_clk),
3204 SH_PFC_PIN_GROUP(scifb0_ctrl),
3205 SH_PFC_PIN_GROUP(scifb0_data_b),
3206 SH_PFC_PIN_GROUP(scifb0_clk_b),
3207 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3208 SH_PFC_PIN_GROUP(scifb0_data_c),
3209 SH_PFC_PIN_GROUP(scifb0_clk_c),
3210 SH_PFC_PIN_GROUP(scifb0_data_d),
3211 SH_PFC_PIN_GROUP(scifb0_clk_d),
3212 SH_PFC_PIN_GROUP(scifb1_data),
3213 SH_PFC_PIN_GROUP(scifb1_clk),
3214 SH_PFC_PIN_GROUP(scifb1_ctrl),
3215 SH_PFC_PIN_GROUP(scifb1_data_b),
3216 SH_PFC_PIN_GROUP(scifb1_clk_b),
3217 SH_PFC_PIN_GROUP(scifb1_data_c),
3218 SH_PFC_PIN_GROUP(scifb1_clk_c),
3219 SH_PFC_PIN_GROUP(scifb1_data_d),
3220 SH_PFC_PIN_GROUP(scifb2_data),
3221 SH_PFC_PIN_GROUP(scifb2_clk),
3222 SH_PFC_PIN_GROUP(scifb2_ctrl),
3223 SH_PFC_PIN_GROUP(scifb2_data_b),
3224 SH_PFC_PIN_GROUP(scifb2_clk_b),
3225 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3226 SH_PFC_PIN_GROUP(scifb2_data_c),
3227 SH_PFC_PIN_GROUP(scifb2_clk_c),
3228 SH_PFC_PIN_GROUP(scifb2_data_d),
3229 SH_PFC_PIN_GROUP(sdhi0_data1),
3230 SH_PFC_PIN_GROUP(sdhi0_data4),
3231 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3232 SH_PFC_PIN_GROUP(sdhi0_cd),
3233 SH_PFC_PIN_GROUP(sdhi0_wp),
3234 SH_PFC_PIN_GROUP(sdhi1_data1),
3235 SH_PFC_PIN_GROUP(sdhi1_data4),
3236 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3237 SH_PFC_PIN_GROUP(sdhi1_cd),
3238 SH_PFC_PIN_GROUP(sdhi1_wp),
3239 SH_PFC_PIN_GROUP(sdhi2_data1),
3240 SH_PFC_PIN_GROUP(sdhi2_data4),
3241 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3242 SH_PFC_PIN_GROUP(sdhi2_cd),
3243 SH_PFC_PIN_GROUP(sdhi2_wp),
3244 SH_PFC_PIN_GROUP(usb0),
3245 SH_PFC_PIN_GROUP(usb1),
3246 VIN_DATA_PIN_GROUP(vin0_data, 24),
3247 VIN_DATA_PIN_GROUP(vin0_data, 20),
3248 SH_PFC_PIN_GROUP(vin0_data18),
3249 VIN_DATA_PIN_GROUP(vin0_data, 16),
3250 VIN_DATA_PIN_GROUP(vin0_data, 12),
3251 VIN_DATA_PIN_GROUP(vin0_data, 10),
3252 VIN_DATA_PIN_GROUP(vin0_data, 8),
3253 SH_PFC_PIN_GROUP(vin0_sync),
3254 SH_PFC_PIN_GROUP(vin0_field),
3255 SH_PFC_PIN_GROUP(vin0_clkenb),
3256 SH_PFC_PIN_GROUP(vin0_clk),
3257 SH_PFC_PIN_GROUP(vin1_data8),
3258 SH_PFC_PIN_GROUP(vin1_sync),
3259 SH_PFC_PIN_GROUP(vin1_field),
3260 SH_PFC_PIN_GROUP(vin1_clkenb),
3261 SH_PFC_PIN_GROUP(vin1_clk),
3262 VIN_DATA_PIN_GROUP(vin1_b_data, 24),
3263 VIN_DATA_PIN_GROUP(vin1_b_data, 20),
3264 SH_PFC_PIN_GROUP(vin1_b_data18),
3265 VIN_DATA_PIN_GROUP(vin1_b_data, 16),
3266 VIN_DATA_PIN_GROUP(vin1_b_data, 12),
3267 VIN_DATA_PIN_GROUP(vin1_b_data, 10),
3268 VIN_DATA_PIN_GROUP(vin1_b_data, 8),
3269 SH_PFC_PIN_GROUP(vin1_b_sync),
3270 SH_PFC_PIN_GROUP(vin1_b_field),
3271 SH_PFC_PIN_GROUP(vin1_b_clkenb),
3272 SH_PFC_PIN_GROUP(vin1_b_clk),
3273 SH_PFC_PIN_GROUP(vin2_data8),
3274 SH_PFC_PIN_GROUP(vin2_sync),
3275 SH_PFC_PIN_GROUP(vin2_field),
3276 SH_PFC_PIN_GROUP(vin2_clkenb),
3277 SH_PFC_PIN_GROUP(vin2_clk),
3280 static const char * const du_groups[] = {
3289 static const char * const du0_groups[] = {
3293 static const char * const du1_groups[] = {
3299 static const char * const eth_groups[] = {
3306 static const char * const i2c0_groups[] = {
3312 static const char * const i2c1_groups[] = {
3320 static const char * const i2c2_groups[] = {
3327 static const char * const i2c3_groups[] = {
3334 static const char * const i2c4_groups[] = {
3340 static const char * const intc_groups[] = {
3347 static const char * const mmc_groups[] = {
3354 static const char * const msiof0_groups[] = {
3363 static const char * const msiof1_groups[] = {
3372 static const char * const msiof2_groups[] = {
3381 static const char * const scif0_groups[] = {
3389 static const char * const scif1_groups[] = {
3397 static const char * const scif2_groups[] = {
3404 static const char * const scif3_groups[] = {
3412 static const char * const scif4_groups[] = {
3417 static const char * const scif5_groups[] = {
3421 static const char * const scifa0_groups[] = {
3425 static const char * const scifa1_groups[] = {
3432 static const char * const scifa2_groups[] = {
3437 static const char * const scifa3_groups[] = {
3445 static const char * const scifa4_groups[] = {
3450 static const char * const scifa5_groups[] = {
3455 static const char * const scifb0_groups[] = {
3467 static const char * const scifb1_groups[] = {
3477 static const char * const scifb2_groups[] = {
3489 static const char * const sdhi0_groups[] = {
3497 static const char * const sdhi1_groups[] = {
3505 static const char * const sdhi2_groups[] = {
3513 static const char * const usb0_groups[] = {
3516 static const char * const usb1_groups[] = {
3520 static const char * const vin0_groups[] = {
3534 static const char * const vin1_groups[] = {
3553 static const char * const vin2_groups[] = {
3561 static const struct sh_pfc_function pinmux_functions[] = {
3562 SH_PFC_FUNCTION(du),
3563 SH_PFC_FUNCTION(du0),
3564 SH_PFC_FUNCTION(du1),
3565 SH_PFC_FUNCTION(eth),
3566 SH_PFC_FUNCTION(i2c0),
3567 SH_PFC_FUNCTION(i2c1),
3568 SH_PFC_FUNCTION(i2c2),
3569 SH_PFC_FUNCTION(i2c3),
3570 SH_PFC_FUNCTION(i2c4),
3571 SH_PFC_FUNCTION(intc),
3572 SH_PFC_FUNCTION(mmc),
3573 SH_PFC_FUNCTION(msiof0),
3574 SH_PFC_FUNCTION(msiof1),
3575 SH_PFC_FUNCTION(msiof2),
3576 SH_PFC_FUNCTION(scif0),
3577 SH_PFC_FUNCTION(scif1),
3578 SH_PFC_FUNCTION(scif2),
3579 SH_PFC_FUNCTION(scif3),
3580 SH_PFC_FUNCTION(scif4),
3581 SH_PFC_FUNCTION(scif5),
3582 SH_PFC_FUNCTION(scifa0),
3583 SH_PFC_FUNCTION(scifa1),
3584 SH_PFC_FUNCTION(scifa2),
3585 SH_PFC_FUNCTION(scifa3),
3586 SH_PFC_FUNCTION(scifa4),
3587 SH_PFC_FUNCTION(scifa5),
3588 SH_PFC_FUNCTION(scifb0),
3589 SH_PFC_FUNCTION(scifb1),
3590 SH_PFC_FUNCTION(scifb2),
3591 SH_PFC_FUNCTION(sdhi0),
3592 SH_PFC_FUNCTION(sdhi1),
3593 SH_PFC_FUNCTION(sdhi2),
3594 SH_PFC_FUNCTION(usb0),
3595 SH_PFC_FUNCTION(usb1),
3596 SH_PFC_FUNCTION(vin0),
3597 SH_PFC_FUNCTION(vin1),
3598 SH_PFC_FUNCTION(vin2),
3601 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3602 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3603 GP_0_31_FN, FN_IP1_22_20,
3604 GP_0_30_FN, FN_IP1_19_17,
3605 GP_0_29_FN, FN_IP1_16_14,
3606 GP_0_28_FN, FN_IP1_13_11,
3607 GP_0_27_FN, FN_IP1_10_8,
3608 GP_0_26_FN, FN_IP1_7_6,
3609 GP_0_25_FN, FN_IP1_5_4,
3610 GP_0_24_FN, FN_IP1_3_2,
3611 GP_0_23_FN, FN_IP1_1_0,
3612 GP_0_22_FN, FN_IP0_30_29,
3613 GP_0_21_FN, FN_IP0_28_27,
3614 GP_0_20_FN, FN_IP0_26_25,
3615 GP_0_19_FN, FN_IP0_24_23,
3616 GP_0_18_FN, FN_IP0_22_21,
3617 GP_0_17_FN, FN_IP0_20_19,
3618 GP_0_16_FN, FN_IP0_18_16,
3619 GP_0_15_FN, FN_IP0_15,
3620 GP_0_14_FN, FN_IP0_14,
3621 GP_0_13_FN, FN_IP0_13,
3622 GP_0_12_FN, FN_IP0_12,
3623 GP_0_11_FN, FN_IP0_11,
3624 GP_0_10_FN, FN_IP0_10,
3625 GP_0_9_FN, FN_IP0_9,
3626 GP_0_8_FN, FN_IP0_8,
3627 GP_0_7_FN, FN_IP0_7,
3628 GP_0_6_FN, FN_IP0_6,
3629 GP_0_5_FN, FN_IP0_5,
3630 GP_0_4_FN, FN_IP0_4,
3631 GP_0_3_FN, FN_IP0_3,
3632 GP_0_2_FN, FN_IP0_2,
3633 GP_0_1_FN, FN_IP0_1,
3634 GP_0_0_FN, FN_IP0_0, }
3636 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3643 GP_1_25_FN, FN_IP3_21_20,
3644 GP_1_24_FN, FN_IP3_19_18,
3645 GP_1_23_FN, FN_IP3_17_16,
3646 GP_1_22_FN, FN_IP3_15_14,
3647 GP_1_21_FN, FN_IP3_13_12,
3648 GP_1_20_FN, FN_IP3_11_9,
3649 GP_1_19_FN, FN_RD_N,
3650 GP_1_18_FN, FN_IP3_8_6,
3651 GP_1_17_FN, FN_IP3_5_3,
3652 GP_1_16_FN, FN_IP3_2_0,
3653 GP_1_15_FN, FN_IP2_29_27,
3654 GP_1_14_FN, FN_IP2_26_25,
3655 GP_1_13_FN, FN_IP2_24_23,
3656 GP_1_12_FN, FN_EX_CS0_N,
3657 GP_1_11_FN, FN_IP2_22_21,
3658 GP_1_10_FN, FN_IP2_20_19,
3659 GP_1_9_FN, FN_IP2_18_16,
3660 GP_1_8_FN, FN_IP2_15_13,
3661 GP_1_7_FN, FN_IP2_12_10,
3662 GP_1_6_FN, FN_IP2_9_7,
3663 GP_1_5_FN, FN_IP2_6_5,
3664 GP_1_4_FN, FN_IP2_4_3,
3665 GP_1_3_FN, FN_IP2_2_0,
3666 GP_1_2_FN, FN_IP1_31_29,
3667 GP_1_1_FN, FN_IP1_28_26,
3668 GP_1_0_FN, FN_IP1_25_23, }
3670 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3671 GP_2_31_FN, FN_IP6_7_6,
3672 GP_2_30_FN, FN_IP6_5_3,
3673 GP_2_29_FN, FN_IP6_2_0,
3674 GP_2_28_FN, FN_AUDIO_CLKA,
3675 GP_2_27_FN, FN_IP5_31_29,
3676 GP_2_26_FN, FN_IP5_28_26,
3677 GP_2_25_FN, FN_IP5_25_24,
3678 GP_2_24_FN, FN_IP5_23_22,
3679 GP_2_23_FN, FN_IP5_21_20,
3680 GP_2_22_FN, FN_IP5_19_17,
3681 GP_2_21_FN, FN_IP5_16_15,
3682 GP_2_20_FN, FN_IP5_14_12,
3683 GP_2_19_FN, FN_IP5_11_9,
3684 GP_2_18_FN, FN_IP5_8_6,
3685 GP_2_17_FN, FN_IP5_5_3,
3686 GP_2_16_FN, FN_IP5_2_0,
3687 GP_2_15_FN, FN_IP4_30_28,
3688 GP_2_14_FN, FN_IP4_27_26,
3689 GP_2_13_FN, FN_IP4_25_24,
3690 GP_2_12_FN, FN_IP4_23_22,
3691 GP_2_11_FN, FN_IP4_21,
3692 GP_2_10_FN, FN_IP4_20,
3693 GP_2_9_FN, FN_IP4_19,
3694 GP_2_8_FN, FN_IP4_18_16,
3695 GP_2_7_FN, FN_IP4_15_13,
3696 GP_2_6_FN, FN_IP4_12_10,
3697 GP_2_5_FN, FN_IP4_9_8,
3698 GP_2_4_FN, FN_IP4_7_5,
3699 GP_2_3_FN, FN_IP4_4_2,
3700 GP_2_2_FN, FN_IP4_1_0,
3701 GP_2_1_FN, FN_IP3_30_28,
3702 GP_2_0_FN, FN_IP3_27_25 }
3704 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3705 GP_3_31_FN, FN_IP9_18_17,
3706 GP_3_30_FN, FN_IP9_16,
3707 GP_3_29_FN, FN_IP9_15_13,
3708 GP_3_28_FN, FN_IP9_12,
3709 GP_3_27_FN, FN_IP9_11,
3710 GP_3_26_FN, FN_IP9_10_8,
3711 GP_3_25_FN, FN_IP9_7,
3712 GP_3_24_FN, FN_IP9_6,
3713 GP_3_23_FN, FN_IP9_5_3,
3714 GP_3_22_FN, FN_IP9_2_0,
3715 GP_3_21_FN, FN_IP8_30_28,
3716 GP_3_20_FN, FN_IP8_27_26,
3717 GP_3_19_FN, FN_IP8_25_24,
3718 GP_3_18_FN, FN_IP8_23_21,
3719 GP_3_17_FN, FN_IP8_20_18,
3720 GP_3_16_FN, FN_IP8_17_15,
3721 GP_3_15_FN, FN_IP8_14_12,
3722 GP_3_14_FN, FN_IP8_11_9,
3723 GP_3_13_FN, FN_IP8_8_6,
3724 GP_3_12_FN, FN_IP8_5_3,
3725 GP_3_11_FN, FN_IP8_2_0,
3726 GP_3_10_FN, FN_IP7_29_27,
3727 GP_3_9_FN, FN_IP7_26_24,
3728 GP_3_8_FN, FN_IP7_23_21,
3729 GP_3_7_FN, FN_IP7_20_19,
3730 GP_3_6_FN, FN_IP7_18_17,
3731 GP_3_5_FN, FN_IP7_16_15,
3732 GP_3_4_FN, FN_IP7_14_13,
3733 GP_3_3_FN, FN_IP7_12_11,
3734 GP_3_2_FN, FN_IP7_10_9,
3735 GP_3_1_FN, FN_IP7_8_6,
3736 GP_3_0_FN, FN_IP7_5_3 }
3738 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3739 GP_4_31_FN, FN_IP15_5_4,
3740 GP_4_30_FN, FN_IP15_3_2,
3741 GP_4_29_FN, FN_IP15_1_0,
3742 GP_4_28_FN, FN_IP11_8_6,
3743 GP_4_27_FN, FN_IP11_5_3,
3744 GP_4_26_FN, FN_IP11_2_0,
3745 GP_4_25_FN, FN_IP10_31_29,
3746 GP_4_24_FN, FN_IP10_28_27,
3747 GP_4_23_FN, FN_IP10_26_25,
3748 GP_4_22_FN, FN_IP10_24_22,
3749 GP_4_21_FN, FN_IP10_21_19,
3750 GP_4_20_FN, FN_IP10_18_17,
3751 GP_4_19_FN, FN_IP10_16_15,
3752 GP_4_18_FN, FN_IP10_14_12,
3753 GP_4_17_FN, FN_IP10_11_9,
3754 GP_4_16_FN, FN_IP10_8_6,
3755 GP_4_15_FN, FN_IP10_5_3,
3756 GP_4_14_FN, FN_IP10_2_0,
3757 GP_4_13_FN, FN_IP9_31_29,
3758 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
3759 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
3760 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
3761 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
3762 GP_4_8_FN, FN_IP9_28_27,
3763 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
3764 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
3765 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
3766 GP_4_4_FN, FN_IP9_26_25,
3767 GP_4_3_FN, FN_IP9_24_23,
3768 GP_4_2_FN, FN_IP9_22_21,
3769 GP_4_1_FN, FN_IP9_20_19,
3770 GP_4_0_FN, FN_VI0_CLK }
3772 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3773 GP_5_31_FN, FN_IP3_24_22,
3774 GP_5_30_FN, FN_IP13_9_7,
3775 GP_5_29_FN, FN_IP13_6_5,
3776 GP_5_28_FN, FN_IP13_4_3,
3777 GP_5_27_FN, FN_IP13_2_0,
3778 GP_5_26_FN, FN_IP12_29_27,
3779 GP_5_25_FN, FN_IP12_26_24,
3780 GP_5_24_FN, FN_IP12_23_22,
3781 GP_5_23_FN, FN_IP12_21_20,
3782 GP_5_22_FN, FN_IP12_19_18,
3783 GP_5_21_FN, FN_IP12_17_16,
3784 GP_5_20_FN, FN_IP12_15_13,
3785 GP_5_19_FN, FN_IP12_12_10,
3786 GP_5_18_FN, FN_IP12_9_7,
3787 GP_5_17_FN, FN_IP12_6_4,
3788 GP_5_16_FN, FN_IP12_3_2,
3789 GP_5_15_FN, FN_IP12_1_0,
3790 GP_5_14_FN, FN_IP11_31_30,
3791 GP_5_13_FN, FN_IP11_29_28,
3792 GP_5_12_FN, FN_IP11_27,
3793 GP_5_11_FN, FN_IP11_26,
3794 GP_5_10_FN, FN_IP11_25,
3795 GP_5_9_FN, FN_IP11_24,
3796 GP_5_8_FN, FN_IP11_23,
3797 GP_5_7_FN, FN_IP11_22,
3798 GP_5_6_FN, FN_IP11_21,
3799 GP_5_5_FN, FN_IP11_20,
3800 GP_5_4_FN, FN_IP11_19,
3801 GP_5_3_FN, FN_IP11_18_17,
3802 GP_5_2_FN, FN_IP11_16_15,
3803 GP_5_1_FN, FN_IP11_14_12,
3804 GP_5_0_FN, FN_IP11_11_9 }
3806 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
3807 GP_6_31_FN, FN_DU0_DOTCLKIN,
3808 GP_6_30_FN, FN_USB1_OVC,
3809 GP_6_29_FN, FN_IP14_31_29,
3810 GP_6_28_FN, FN_IP14_28_26,
3811 GP_6_27_FN, FN_IP14_25_23,
3812 GP_6_26_FN, FN_IP14_22_20,
3813 GP_6_25_FN, FN_IP14_19_17,
3814 GP_6_24_FN, FN_IP14_16_14,
3815 GP_6_23_FN, FN_IP14_13_11,
3816 GP_6_22_FN, FN_IP14_10_8,
3817 GP_6_21_FN, FN_IP14_7,
3818 GP_6_20_FN, FN_IP14_6,
3819 GP_6_19_FN, FN_IP14_5,
3820 GP_6_18_FN, FN_IP14_4,
3821 GP_6_17_FN, FN_IP14_3,
3822 GP_6_16_FN, FN_IP14_2,
3823 GP_6_15_FN, FN_IP14_1_0,
3824 GP_6_14_FN, FN_IP13_30_28,
3825 GP_6_13_FN, FN_IP13_27,
3826 GP_6_12_FN, FN_IP13_26,
3827 GP_6_11_FN, FN_IP13_25,
3828 GP_6_10_FN, FN_IP13_24_23,
3829 GP_6_9_FN, FN_IP13_22,
3830 GP_6_8_FN, FN_SD1_CLK,
3831 GP_6_7_FN, FN_IP13_21_19,
3832 GP_6_6_FN, FN_IP13_18_16,
3833 GP_6_5_FN, FN_IP13_15,
3834 GP_6_4_FN, FN_IP13_14,
3835 GP_6_3_FN, FN_IP13_13,
3836 GP_6_2_FN, FN_IP13_12,
3837 GP_6_1_FN, FN_IP13_11,
3838 GP_6_0_FN, FN_IP13_10 }
3840 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
3847 GP_7_25_FN, FN_USB1_PWEN,
3848 GP_7_24_FN, FN_USB0_OVC,
3849 GP_7_23_FN, FN_USB0_PWEN,
3850 GP_7_22_FN, FN_IP15_14_12,
3851 GP_7_21_FN, FN_IP15_11_9,
3852 GP_7_20_FN, FN_IP15_8_6,
3853 GP_7_19_FN, FN_IP7_2_0,
3854 GP_7_18_FN, FN_IP6_29_27,
3855 GP_7_17_FN, FN_IP6_26_24,
3856 GP_7_16_FN, FN_IP6_23_21,
3857 GP_7_15_FN, FN_IP6_20_19,
3858 GP_7_14_FN, FN_IP6_18_16,
3859 GP_7_13_FN, FN_IP6_15_14,
3860 GP_7_12_FN, FN_IP6_13_12,
3861 GP_7_11_FN, FN_IP6_11_10,
3862 GP_7_10_FN, FN_IP6_9_8,
3863 GP_7_9_FN, FN_IP16_11_10,
3864 GP_7_8_FN, FN_IP16_9_8,
3865 GP_7_7_FN, FN_IP16_7_6,
3866 GP_7_6_FN, FN_IP16_5_3,
3867 GP_7_5_FN, FN_IP16_2_0,
3868 GP_7_4_FN, FN_IP15_29_27,
3869 GP_7_3_FN, FN_IP15_26_24,
3870 GP_7_2_FN, FN_IP15_23_21,
3871 GP_7_1_FN, FN_IP15_20_18,
3872 GP_7_0_FN, FN_IP15_17_15 }
3874 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3875 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
3876 1, 1, 1, 1, 1, 1, 1, 1) {
3880 FN_A6, FN_MSIOF1_SCK,
3883 FN_A5, FN_MSIOF0_RXD_B,
3886 FN_A4, FN_MSIOF0_TXD_B,
3889 FN_A3, FN_MSIOF0_SS2_B,
3892 FN_A2, FN_MSIOF0_SS1_B,
3895 FN_A1, FN_MSIOF0_SYNC_B,
3898 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
3933 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3934 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
3936 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
3939 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
3942 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
3945 FN_A15, FN_BPFCLK_C,
3948 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
3951 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
3954 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
3957 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
3960 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
3962 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
3964 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
3966 FN_A7, FN_MSIOF1_SYNC,
3969 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3970 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
3974 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
3975 FN_ATAG0_N, 0, FN_EX_WAIT1,
3978 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
3980 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
3982 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
3984 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
3986 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
3989 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
3992 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
3995 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
3998 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
4000 FN_A20, FN_SPCLK, 0, 0,
4002 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
4003 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
4005 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4006 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
4010 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
4011 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
4014 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
4015 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
4018 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
4019 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
4021 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
4023 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
4025 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
4027 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
4029 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
4031 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
4034 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
4035 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
4037 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
4038 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
4040 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
4043 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4044 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
4048 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
4049 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
4052 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
4054 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
4056 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
4064 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
4067 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
4068 FN_GLO_Q1_D, FN_HCTS1_N_E,
4071 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
4074 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
4076 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
4079 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
4080 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
4083 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
4085 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4086 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
4088 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
4091 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
4094 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
4096 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
4098 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
4100 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
4103 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
4105 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
4108 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
4111 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
4112 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
4115 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
4116 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
4119 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
4120 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
4123 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4124 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
4128 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
4129 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
4132 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
4133 FN_GPS_CLK_C, FN_GPS_CLK_D,
4136 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
4137 FN_SDA1_E, FN_MSIOF2_SYNC_E,
4140 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
4142 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
4145 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
4147 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
4149 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
4151 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
4153 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
4155 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
4156 FN_SCIFA2_RXD, FN_FMIN_E,
4159 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
4160 FN_SCIF_CLK, 0, FN_BPFCLK_E,
4163 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4164 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
4168 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
4169 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
4172 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
4173 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
4176 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
4177 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
4180 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
4182 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
4184 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
4186 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
4188 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
4190 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
4192 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
4193 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
4196 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
4197 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
4200 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
4201 FN_SCIF_CLK_B, FN_GPS_MAG_D,
4204 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4205 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
4209 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
4212 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
4214 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
4216 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
4217 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
4220 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
4221 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
4224 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
4225 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
4228 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
4229 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
4232 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
4233 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
4236 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
4237 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
4240 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
4241 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
4244 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
4247 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4248 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
4250 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
4251 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
4253 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
4255 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
4257 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
4259 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
4261 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
4263 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
4265 FN_DU1_DISP, FN_QPOLA,
4267 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
4268 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
4271 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
4273 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
4275 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
4276 FN_TX3_B, FN_SCL2_B, FN_PWM4,
4279 FN_DU1_DOTCLKOUT0, FN_QCLK,
4281 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
4283 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
4284 FN_SCIF3_SCK, FN_SCIFA3_SCK,
4287 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
4290 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4291 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
4292 /* IP10_31_29 [3] */
4293 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
4295 /* IP10_28_27 [2] */
4296 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
4297 /* IP10_26_25 [2] */
4298 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
4299 /* IP10_24_22 [3] */
4300 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
4302 /* IP10_21_29 [3] */
4303 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
4304 FN_TS_SDATA0_C, FN_ATACS11_N,
4306 /* IP10_18_17 [2] */
4307 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
4308 /* IP10_16_15 [2] */
4309 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
4310 /* IP10_14_12 [3] */
4311 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
4312 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
4314 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
4315 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
4318 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
4319 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
4321 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
4322 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
4324 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
4325 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
4327 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4328 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4330 /* IP11_31_30 [2] */
4331 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
4332 /* IP11_29_28 [2] */
4333 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
4335 FN_VI1_DATA7, FN_AVB_MDC,
4337 FN_VI1_DATA6, FN_AVB_MAGIC,
4339 FN_VI1_DATA5, FN_AVB_RX_DV,
4341 FN_VI1_DATA4, FN_AVB_MDIO,
4343 FN_VI1_DATA3, FN_AVB_RX_ER,
4345 FN_VI1_DATA2, FN_AVB_RXD7,
4347 FN_VI1_DATA1, FN_AVB_RXD6,
4349 FN_VI1_DATA0, FN_AVB_RXD5,
4351 FN_VI1_CLK, FN_AVB_RXD4,
4352 /* IP11_18_17 [2] */
4353 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
4354 /* IP11_16_15 [2] */
4355 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
4356 /* IP11_14_12 [3] */
4357 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
4358 FN_RX4_B, FN_SCIFA4_RXD_B,
4361 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
4362 FN_TX4_B, FN_SCIFA4_TXD_B,
4365 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
4366 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
4368 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
4371 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
4374 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4375 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
4376 /* IP12_31_30 [2] */
4378 /* IP12_29_27 [3] */
4379 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
4380 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
4382 /* IP12_26_24 [3] */
4383 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
4384 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
4386 /* IP12_23_22 [2] */
4387 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
4388 /* IP12_21_20 [2] */
4389 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
4390 /* IP12_19_18 [2] */
4391 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
4392 /* IP12_17_16 [2] */
4393 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
4394 /* IP12_15_13 [3] */
4395 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
4396 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
4398 /* IP12_12_10 [3] */
4399 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
4400 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
4403 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
4404 FN_SDA2_D, FN_MSIOF1_SCK_E,
4407 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
4408 FN_SCL2_D, FN_MSIOF1_RXD_E,
4411 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
4413 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
4415 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4416 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
4420 /* IP13_30_28 [3] */
4421 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
4424 FN_SD1_DATA3, FN_IERX_B,
4426 FN_SD1_DATA2, FN_IECLK_B,
4428 FN_SD1_DATA1, FN_IETX_B,
4429 /* IP13_24_23 [2] */
4430 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
4432 FN_SD1_CMD, FN_REMOCON_B,
4433 /* IP13_21_19 [3] */
4434 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
4435 FN_SCIFA5_RXD_B, FN_RX3_C,
4437 /* IP13_18_16 [3] */
4438 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
4439 FN_SCIFA5_TXD_B, FN_TX3_C,
4442 FN_SD0_DATA3, FN_SSL_B,
4444 FN_SD0_DATA2, FN_IO3_B,
4446 FN_SD0_DATA1, FN_IO2_B,
4448 FN_SD0_DATA0, FN_MISO_IO1_B,
4450 FN_SD0_CMD, FN_MOSI_IO0_B,
4452 FN_SD0_CLK, FN_SPCLK_B,
4454 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
4455 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
4458 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
4460 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
4462 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
4463 FN_ADICLK_B, FN_MSIOF0_SS1_C,
4466 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
4467 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
4468 /* IP14_31_29 [3] */
4469 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
4470 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
4471 /* IP14_28_26 [3] */
4472 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
4473 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
4474 /* IP14_25_23 [3] */
4475 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
4477 /* IP14_22_20 [3] */
4478 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
4480 /* IP14_19_17 [3] */
4481 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
4482 FN_VI1_CLKENB_C, FN_VI1_G1_B,
4484 /* IP14_16_14 [3] */
4485 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
4486 FN_VI1_CLK_C, FN_VI1_G0_B,
4488 /* IP14_13_11 [3] */
4489 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
4492 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
4495 FN_SD2_DATA3, FN_MMC_D3,
4497 FN_SD2_DATA2, FN_MMC_D2,
4499 FN_SD2_DATA1, FN_MMC_D1,
4501 FN_SD2_DATA0, FN_MMC_D0,
4503 FN_SD2_CMD, FN_MMC_CMD,
4505 FN_SD2_CLK, FN_MMC_CLK,
4507 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
4509 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
4510 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
4511 /* IP15_31_30 [2] */
4513 /* IP15_29_27 [3] */
4514 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
4515 FN_CAN0_TX_B, FN_VI1_DATA5_C,
4517 /* IP15_26_24 [3] */
4518 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
4519 FN_CAN0_RX_B, FN_VI1_DATA4_C,
4521 /* IP15_23_21 [3] */
4522 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
4523 FN_TCLK2, FN_VI1_DATA3_C, 0,
4524 /* IP15_20_18 [3] */
4525 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
4527 /* IP15_17_15 [3] */
4528 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
4529 FN_TCLK1, FN_VI1_DATA1_C,
4531 /* IP15_14_12 [3] */
4532 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
4533 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
4536 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
4537 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
4540 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
4541 FN_PWM5_B, FN_SCIFA3_TXD_C,
4544 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
4546 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
4548 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
4550 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
4551 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
4552 /* IP16_31_28 [4] */
4553 0, 0, 0, 0, 0, 0, 0, 0,
4554 0, 0, 0, 0, 0, 0, 0, 0,
4555 /* IP16_27_24 [4] */
4556 0, 0, 0, 0, 0, 0, 0, 0,
4557 0, 0, 0, 0, 0, 0, 0, 0,
4558 /* IP16_23_20 [4] */
4559 0, 0, 0, 0, 0, 0, 0, 0,
4560 0, 0, 0, 0, 0, 0, 0, 0,
4561 /* IP16_19_16 [4] */
4562 0, 0, 0, 0, 0, 0, 0, 0,
4563 0, 0, 0, 0, 0, 0, 0, 0,
4564 /* IP16_15_12 [4] */
4565 0, 0, 0, 0, 0, 0, 0, 0,
4566 0, 0, 0, 0, 0, 0, 0, 0,
4567 /* IP16_11_10 [2] */
4568 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
4570 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
4572 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
4574 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
4575 FN_GLO_SS_C, FN_VI1_DATA7_C,
4578 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
4579 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
4582 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4583 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
4584 3, 2, 2, 2, 1, 2, 2, 2) {
4588 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
4590 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
4591 /* SEL_SCIFB2 [2] */
4592 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
4593 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
4594 /* SEL_SCIFB1 [3] */
4595 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
4596 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
4598 /* SEL_SCIFA1 [2] */
4599 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
4601 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
4603 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
4605 FN_SEL_QSP_0, FN_SEL_QSP_1,
4607 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
4608 /* SEL_HSCIF1 [3] */
4609 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
4610 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
4615 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
4619 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
4621 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
4623 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4625 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
4627 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4628 3, 1, 1, 3, 2, 1, 1, 2, 2,
4629 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
4631 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
4632 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
4637 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
4639 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4640 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
4643 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
4646 /* SEL_SCIFA2 [1] */
4647 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
4649 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
4653 FN_SEL_ADG_0, FN_SEL_ADG_1,
4655 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
4656 FN_SEL_FM_3, FN_SEL_FM_4,
4658 /* SEL_SCIFA5 [2] */
4659 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
4663 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
4664 /* SEL_SCIFA4 [2] */
4665 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
4666 /* SEL_SCIFA3 [2] */
4667 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
4669 FN_SEL_SIM_0, FN_SEL_SIM_1,
4673 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
4675 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4676 2, 2, 2, 2, 2, 2, 2, 2,
4677 1, 1, 2, 2, 3, 2, 2, 2, 1) {
4678 /* SEL_HSCIF2 [2] */
4679 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
4680 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
4681 /* SEL_CANCLK [2] */
4682 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
4683 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
4685 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
4687 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
4689 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
4691 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
4693 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
4695 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
4697 FN_SEL_MMC_0, FN_SEL_MMC_1,
4699 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
4703 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
4705 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
4709 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
4717 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
4718 3, 2, 2, 1, 1, 1, 1, 3, 2,
4719 2, 3, 1, 1, 1, 2, 2, 2, 2) {
4721 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
4724 /* SEL_HSCIF0 [2] */
4725 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
4727 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
4731 FN_SEL_RAD_0, FN_SEL_RAD_1,
4733 FN_SEL_RCN_0, FN_SEL_RCN_1,
4735 FN_SEL_RSP_0, FN_SEL_RSP_1,
4737 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
4738 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
4745 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
4746 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
4751 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
4753 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
4755 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
4766 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
4767 .name = "r8a77910_pfc",
4768 .unlock_reg = 0xe6060000, /* PMMR */
4770 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4772 .pins = pinmux_pins,
4773 .nr_pins = ARRAY_SIZE(pinmux_pins),
4774 .groups = pinmux_groups,
4775 .nr_groups = ARRAY_SIZE(pinmux_groups),
4776 .functions = pinmux_functions,
4777 .nr_functions = ARRAY_SIZE(pinmux_functions),
4779 .cfg_regs = pinmux_config_regs,
4781 .gpio_data = pinmux_data,
4782 .gpio_data_size = ARRAY_SIZE(pinmux_data),