drivers/qe/uec.h

   1 /*
   2  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on source code of Shlomi Gridish
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __UEC_H__
  24 #define __UEC_H__
  25
  26 #define MAX_TX_THREADS                          8
  27 #define MAX_RX_THREADS                          8
  28 #define MAX_TX_QUEUES                           8
  29 #define MAX_RX_QUEUES                           8
  30 #define MAX_PREFETCHED_BDS                      4
  31 #define MAX_IPH_OFFSET_ENTRY                    8
  32 #define MAX_ENET_INIT_PARAM_ENTRIES_RX          9
  33 #define MAX_ENET_INIT_PARAM_ENTRIES_TX          8
  34
  35 /* UEC UPSMR (Protocol Specific Mode Register)
  36  */
  37 #define UPSMR_ECM       0x04000000 /* Enable CAM Miss               */
  38 #define UPSMR_HSE       0x02000000 /* Hardware Statistics Enable    */
  39 #define UPSMR_PRO       0x00400000 /* Promiscuous                   */
  40 #define UPSMR_CAP       0x00200000 /* CAM polarity                  */
  41 #define UPSMR_RSH       0x00100000 /* Receive Short Frames          */
  42 #define UPSMR_RPM       0x00080000 /* Reduced Pin Mode interfaces   */
  43 #define UPSMR_R10M      0x00040000 /* RGMII/RMII 10 Mode            */
  44 #define UPSMR_RLPB      0x00020000 /* RMII Loopback Mode            */
  45 #define UPSMR_TBIM      0x00010000 /* Ten-bit Interface Mode        */
  46 #define UPSMR_RMM       0x00001000 /* RMII/RGMII Mode               */
  47 #define UPSMR_CAM       0x00000400 /* CAM Address Matching          */
  48 #define UPSMR_BRO       0x00000200 /* Broadcast Address             */
  49 #define UPSMR_RES1      0x00002000 /* Reserved feild - must be 1    */
  50 #define UPSMR_SGMM      0x00000020 /* SGMII mode    */
  51
  52 #define UPSMR_INIT_VALUE        (UPSMR_HSE | UPSMR_RES1)
  53
  54 /* UEC MACCFG1 (MAC Configuration 1 Register)
  55  */
  56 #define MACCFG1_FLOW_RX                 0x00000020 /* Flow Control Rx */
  57 #define MACCFG1_FLOW_TX                 0x00000010 /* Flow Control Tx */
  58 #define MACCFG1_ENABLE_SYNCHED_RX       0x00000008 /* Enable Rx Sync  */
  59 #define MACCFG1_ENABLE_RX               0x00000004 /* Enable Rx       */
  60 #define MACCFG1_ENABLE_SYNCHED_TX       0x00000002 /* Enable Tx Sync  */
  61 #define MACCFG1_ENABLE_TX               0x00000001 /* Enable Tx       */
  62
  63 #define MACCFG1_INIT_VALUE              (0)
  64
  65 /* UEC MACCFG2 (MAC Configuration 2 Register)
  66  */
  67 #define MACCFG2_PREL                            0x00007000
  68 #define MACCFG2_PREL_SHIFT                      (31 - 19)
  69 #define MACCFG2_PREL_MASK                       0x0000f000
  70 #define MACCFG2_SRP                             0x00000080
  71 #define MACCFG2_STP                             0x00000040
  72 #define MACCFG2_RESERVED_1                      0x00000020 /* must be set  */
  73 #define MACCFG2_LC                              0x00000010 /* Length Check */
  74 #define MACCFG2_MPE                             0x00000008
  75 #define MACCFG2_FDX                             0x00000001 /* Full Duplex  */
  76 #define MACCFG2_FDX_MASK                        0x00000001
  77 #define MACCFG2_PAD_CRC                         0x00000004
  78 #define MACCFG2_CRC_EN                          0x00000002
  79 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000
  80 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002
  81 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
  82 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100
  83 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200
  84 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300
  85
  86 #define MACCFG2_INIT_VALUE      (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
  87                                  MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
  88
  89 /* UEC Event Register
  90 */
  91 #define UCCE_MPD                                0x80000000
  92 #define UCCE_SCAR                               0x40000000
  93 #define UCCE_GRA                                0x20000000
  94 #define UCCE_CBPR                               0x10000000
  95 #define UCCE_BSY                                0x08000000
  96 #define UCCE_RXC                                0x04000000
  97 #define UCCE_TXC                                0x02000000
  98 #define UCCE_TXE                                0x01000000
  99 #define UCCE_TXB7                               0x00800000
 100 #define UCCE_TXB6                               0x00400000
 101 #define UCCE_TXB5                               0x00200000
 102 #define UCCE_TXB4                               0x00100000
 103 #define UCCE_TXB3                               0x00080000
 104 #define UCCE_TXB2                               0x00040000
 105 #define UCCE_TXB1                               0x00020000
 106 #define UCCE_TXB0                               0x00010000
 107 #define UCCE_RXB7                               0x00008000
 108 #define UCCE_RXB6                               0x00004000
 109 #define UCCE_RXB5                               0x00002000
 110 #define UCCE_RXB4                               0x00001000
 111 #define UCCE_RXB3                               0x00000800
 112 #define UCCE_RXB2                               0x00000400
 113 #define UCCE_RXB1                               0x00000200
 114 #define UCCE_RXB0                               0x00000100
 115 #define UCCE_RXF7                               0x00000080
 116 #define UCCE_RXF6                               0x00000040
 117 #define UCCE_RXF5                               0x00000020
 118 #define UCCE_RXF4                               0x00000010
 119 #define UCCE_RXF3                               0x00000008
 120 #define UCCE_RXF2                               0x00000004
 121 #define UCCE_RXF1                               0x00000002
 122 #define UCCE_RXF0                               0x00000001
 123
 124 #define UCCE_TXB        (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
 125                          UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
 126 #define UCCE_RXB        (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
 127                          UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
 128 #define UCCE_RXF        (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
 129                          UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
 130 #define UCCE_OTHER      (UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  | \
 131                          UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
 132
 133 /* UEC TEMODR Register
 134 */
 135 #define TEMODER_SCHEDULER_ENABLE                0x2000
 136 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400
 137 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200
 138 #define TEMODER_RMON_STATISTICS                 0x0100
 139 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15)
 140
 141 #define TEMODER_INIT_VALUE                      0xc000
 142
 143 /* UEC REMODR Register
 144 */
 145 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000
 146 #define REMODER_RX_EXTENDED_FEATURES            0x80000000
 147 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 )
 148 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
 149 #define REMODER_RX_QOS_MODE_SHIFT               (31-15)
 150 #define REMODER_RMON_STATISTICS                 0x00001000
 151 #define REMODER_RX_EXTENDED_FILTERING           0x00000800
 152 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23)
 153 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008
 154 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004
 155 #define REMODER_IP_CHECKSUM_CHECK               0x00000002
 156 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001
 157
 158 #define REMODER_INIT_VALUE                      0
 159
 160 /* BMRx - Bus Mode Register */
 161 #define BMR_GLB                                 0x20
 162 #define BMR_BO_BE                               0x10
 163 #define BMR_DTB_SECONDARY_BUS                   0x02
 164 #define BMR_BDB_SECONDARY_BUS                   0x01
 165
 166 #define BMR_SHIFT                               24
 167 #define BMR_INIT_VALUE                          (BMR_GLB | BMR_BO_BE)
 168
 169 /* UEC UCCS (Ethernet Status Register)
 170  */
 171 #define UCCS_BPR                                0x02
 172 #define UCCS_PAU                                0x02
 173 #define UCCS_MPD                                0x01
 174
 175 /* UEC MIIMCFG (MII Management Configuration Register)
 176  */
 177 #define MIIMCFG_RESET_MANAGEMENT                0x80000000
 178 #define MIIMCFG_NO_PREAMBLE                     0x00000010
 179 #define MIIMCFG_CLOCK_DIVIDE_SHIFT              (31 - 31)
 180 #define MIIMCFG_CLOCK_DIVIDE_MASK               0x0000000f
 181 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4    0x00000001
 182 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6    0x00000002
 183 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8    0x00000003
 184 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10   0x00000004
 185 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14   0x00000005
 186 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20   0x00000006
 187 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28   0x00000007
 188
 189 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE       \
 190         MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
 191
 192 /* UEC MIIMCOM (MII Management Command Register)
 193  */
 194 #define MIIMCOM_SCAN_CYCLE                      0x00000002 /* Scan cycle */
 195 #define MIIMCOM_READ_CYCLE                      0x00000001 /* Read cycle */
 196
 197 /* UEC MIIMADD (MII Management Address Register)
 198  */
 199 #define MIIMADD_PHY_ADDRESS_SHIFT               (31 - 23)
 200 #define MIIMADD_PHY_REGISTER_SHIFT              (31 - 31)
 201
 202 /* UEC MIIMCON (MII Management Control Register)
 203  */
 204 #define MIIMCON_PHY_CONTROL_SHIFT               (31 - 31)
 205 #define MIIMCON_PHY_STATUS_SHIFT                (31 - 31)
 206
 207 /* UEC MIIMIND (MII Management Indicator Register)
 208  */
 209 #define MIIMIND_NOT_VALID                       0x00000004
 210 #define MIIMIND_SCAN                            0x00000002
 211 #define MIIMIND_BUSY                            0x00000001
 212
 213 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
 214  */
 215 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)
 216 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f
 217
 218 /* UEC UESCR (Ethernet Statistics Control Register)
 219  */
 220 #define UESCR_AUTOZ                             0x8000
 221 #define UESCR_CLRCNT                            0x4000
 222 #define UESCR_MAXCOV_SHIFT                      (15 -  7)
 223 #define UESCR_SCOV_SHIFT                        (15 - 15)
 224
 225 /****** Tx data struct collection ******/
 226 /* Tx thread data, each Tx thread has one this struct.
 227 */
 228 typedef struct uec_thread_data_tx {
 229         u8   res0[136];
 230 } __attribute__ ((packed)) uec_thread_data_tx_t;
 231
 232 /* Tx thread parameter, each Tx thread has one this struct.
 233 */
 234 typedef struct uec_thread_tx_pram {
 235         u8   res0[64];
 236 } __attribute__ ((packed)) uec_thread_tx_pram_t;
 237
 238 /* Send queue queue-descriptor, each Tx queue has one this QD
 239 */
 240 typedef struct uec_send_queue_qd {
 241         u32    bd_ring_base; /* pointer to BD ring base address */
 242         u8     res0[0x8];
 243         u32    last_bd_completed_address; /* last entry in BD ring */
 244         u8     res1[0x30];
 245 } __attribute__ ((packed)) uec_send_queue_qd_t;
 246
 247 /* Send queue memory region */
 248 typedef struct uec_send_queue_mem_region {
 249         uec_send_queue_qd_t   sqqd[MAX_TX_QUEUES];
 250 } __attribute__ ((packed)) uec_send_queue_mem_region_t;
 251
 252 /* Scheduler struct
 253 */
 254 typedef struct uec_scheduler {
 255         u16  cpucount0;        /* CPU packet counter */
 256         u16  cpucount1;        /* CPU packet counter */
 257         u16  cecount0;         /* QE  packet counter */
 258         u16  cecount1;         /* QE  packet counter */
 259         u16  cpucount2;        /* CPU packet counter */
 260         u16  cpucount3;        /* CPU packet counter */
 261         u16  cecount2;         /* QE  packet counter */
 262         u16  cecount3;         /* QE  packet counter */
 263         u16  cpucount4;        /* CPU packet counter */
 264         u16  cpucount5;        /* CPU packet counter */
 265         u16  cecount4;         /* QE  packet counter */
 266         u16  cecount5;         /* QE  packet counter */
 267         u16  cpucount6;        /* CPU packet counter */
 268         u16  cpucount7;        /* CPU packet counter */
 269         u16  cecount6;         /* QE  packet counter */
 270         u16  cecount7;         /* QE  packet counter */
 271         u32  weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
 272         u32  rtsrshadow;       /* temporary variable handled by QE */
 273         u32  time;             /* temporary variable handled by QE */
 274         u32  ttl;              /* temporary variable handled by QE */
 275         u32  mblinterval;      /* max burst length interval        */
 276         u16  nortsrbytetime;   /* normalized value of byte time in tsr units */
 277         u8   fracsiz;
 278         u8   res0[1];
 279         u8   strictpriorityq;  /* Strict Priority Mask register */
 280         u8   txasap;           /* Transmit ASAP register        */
 281         u8   extrabw;          /* Extra BandWidth register      */
 282         u8   oldwfqmask;       /* temporary variable handled by QE */
 283         u8   weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
 284         u32  minw;             /* temporary variable handled by QE */
 285         u8   res1[0x70-0x64];
 286 } __attribute__ ((packed)) uec_scheduler_t;
 287
 288 /* Tx firmware counters
 289 */
 290 typedef struct uec_tx_firmware_statistics_pram {
 291         u32  sicoltx;            /* single collision */
 292         u32  mulcoltx;           /* multiple collision */
 293         u32  latecoltxfr;        /* late collision */
 294         u32  frabortduecol;      /* frames aborted due to tx collision */
 295         u32  frlostinmactxer;    /* frames lost due to internal MAC error tx */
 296         u32  carriersenseertx;   /* carrier sense error */
 297         u32  frtxok;             /* frames transmitted OK */
 298         u32  txfrexcessivedefer;
 299         u32  txpkts256;          /* total packets(including bad) 256~511 B */
 300         u32  txpkts512;          /* total packets(including bad) 512~1023B */
 301         u32  txpkts1024;         /* total packets(including bad) 1024~1518B */
 302         u32  txpktsjumbo;        /* total packets(including bad)  >1024 */
 303 } __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
 304
 305 /* Tx global parameter table
 306 */
 307 typedef struct uec_tx_global_pram {
 308         u16  temoder;
 309         u8   res0[0x38-0x02];
 310         u32  sqptr;
 311         u32  schedulerbasepointer;
 312         u32  txrmonbaseptr;
 313         u32  tstate;
 314         u8   iphoffset[MAX_IPH_OFFSET_ENTRY];
 315         u32  vtagtable[0x8];
 316         u32  tqptr;
 317         u8   res2[0x80-0x74];
 318 } __attribute__ ((packed)) uec_tx_global_pram_t;
 319
 320
 321 /****** Rx data struct collection ******/
 322 /* Rx thread data, each Rx thread has one this struct.
 323 */
 324 typedef struct uec_thread_data_rx {
 325         u8   res0[40];
 326 } __attribute__ ((packed)) uec_thread_data_rx_t;
 327
 328 /* Rx thread parameter, each Rx thread has one this struct.
 329 */
 330 typedef struct uec_thread_rx_pram {
 331         u8   res0[128];
 332 } __attribute__ ((packed)) uec_thread_rx_pram_t;
 333
 334 /* Rx firmware counters
 335 */
 336 typedef struct uec_rx_firmware_statistics_pram {
 337         u32   frrxfcser;         /* frames with crc error */
 338         u32   fraligner;         /* frames with alignment error */
 339         u32   inrangelenrxer;    /* in range length error */
 340         u32   outrangelenrxer;   /* out of range length error */
 341         u32   frtoolong;         /* frame too long */
 342         u32   runt;              /* runt */
 343         u32   verylongevent;     /* very long event */
 344         u32   symbolerror;       /* symbol error */
 345         u32   dropbsy;           /* drop because of BD not ready */
 346         u8    res0[0x8];
 347         u32   mismatchdrop;      /* drop because of MAC filtering */
 348         u32   underpkts;         /* total frames less than 64 octets */
 349         u32   pkts256;           /* total frames(including bad)256~511 B */
 350         u32   pkts512;           /* total frames(including bad)512~1023 B */
 351         u32   pkts1024;          /* total frames(including bad)1024~1518 B */
 352         u32   pktsjumbo;         /* total frames(including bad) >1024 B */
 353         u32   frlossinmacer;
 354         u32   pausefr;           /* pause frames */
 355         u8    res1[0x4];
 356         u32   removevlan;
 357         u32   replacevlan;
 358         u32   insertvlan;
 359 } __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
 360
 361 /* Rx interrupt coalescing entry, each Rx queue has one this entry.
 362 */
 363 typedef struct uec_rx_interrupt_coalescing_entry {
 364         u32   maxvalue;
 365         u32   counter;
 366 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
 367
 368 typedef struct uec_rx_interrupt_coalescing_table {
 369         uec_rx_interrupt_coalescing_entry_t   entry[MAX_RX_QUEUES];
 370 } __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
 371
 372 /* RxBD queue entry, each Rx queue has one this entry.
 373 */
 374 typedef struct uec_rx_bd_queues_entry {
 375         u32   bdbaseptr;         /* BD base pointer          */
 376         u32   bdptr;             /* BD pointer               */
 377         u32   externalbdbaseptr; /* external BD base pointer */
 378         u32   externalbdptr;     /* external BD pointer      */
 379 } __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
 380
 381 /* Rx global paramter table
 382 */
 383 typedef struct uec_rx_global_pram {
 384         u32  remoder;             /* ethernet mode reg. */
 385         u32  rqptr;               /* base pointer to the Rx Queues */
 386         u32  res0[0x1];
 387         u8   res1[0x20-0xC];
 388         u16  typeorlen;
 389         u8   res2[0x1];
 390         u8   rxgstpack;           /* ack on GRACEFUL STOP RX command */
 391         u32  rxrmonbaseptr;       /* Rx RMON statistics base */
 392         u8   res3[0x30-0x28];
 393         u32  intcoalescingptr;    /* Interrupt coalescing table pointer */
 394         u8   res4[0x36-0x34];
 395         u8   rstate;
 396         u8   res5[0x46-0x37];
 397         u16  mrblr;               /* max receive buffer length reg. */
 398         u32  rbdqptr;             /* RxBD parameter table description */
 399         u16  mflr;                /* max frame length reg. */
 400         u16  minflr;              /* min frame length reg. */
 401         u16  maxd1;               /* max dma1 length reg. */
 402         u16  maxd2;               /* max dma2 length reg. */
 403         u32  ecamptr;             /* external CAM address */
 404         u32  l2qt;                /* VLAN priority mapping table. */
 405         u32  l3qt[0x8];           /* IP   priority mapping table. */
 406         u16  vlantype;            /* vlan type */
 407         u16  vlantci;             /* default vlan tci */
 408         u8   addressfiltering[64];/* address filtering data structure */
 409         u32  exfGlobalParam;      /* extended filtering global parameters */
 410         u8   res6[0x100-0xC4];    /* Initialize to zero */
 411 } __attribute__ ((packed)) uec_rx_global_pram_t;
 412
 413 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 414
 415
 416 /****** UEC common ******/
 417 /* UCC statistics - hardware counters
 418 */
 419 typedef struct uec_hardware_statistics {
 420         u32 tx64;
 421         u32 tx127;
 422         u32 tx255;
 423         u32 rx64;
 424         u32 rx127;
 425         u32 rx255;
 426         u32 txok;
 427         u16 txcf;
 428         u32 tmca;
 429         u32 tbca;
 430         u32 rxfok;
 431         u32 rxbok;
 432         u32 rbyt;
 433         u32 rmca;
 434         u32 rbca;
 435 } __attribute__ ((packed)) uec_hardware_statistics_t;
 436
 437 /* InitEnet command parameter
 438 */
 439 typedef struct uec_init_cmd_pram {
 440         u8   resinit0;
 441         u8   resinit1;
 442         u8   resinit2;
 443         u8   resinit3;
 444         u16  resinit4;
 445         u8   res1[0x1];
 446         u8   largestexternallookupkeysize;
 447         u32  rgftgfrxglobal;
 448         u32  rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
 449         u8   res2[0x38 - 0x30];
 450         u32  txglobal;                             /* tx global  */
 451         u32  txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
 452         u8   res3[0x1];
 453 } __attribute__ ((packed)) uec_init_cmd_pram_t;
 454
 455 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 456 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 457
 458 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 459 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 460 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 461 #define ENET_INIT_PARAM_SNUM_SHIFT              24
 462
 463 #define ENET_INIT_PARAM_MAGIC_RES_INIT0         0x06
 464 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x30
 465 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0xff
 466 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0x00
 467 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x0400
 468
 469 /* structure representing 82xx Address Filtering Enet Address in PRAM
 470 */
 471 typedef struct uec_82xx_enet_address {
 472         u8   res1[0x2];
 473         u16  h;       /* address (MSB) */
 474         u16  m;       /* address       */
 475         u16  l;       /* address (LSB) */
 476 } __attribute__ ((packed)) uec_82xx_enet_address_t;
 477
 478 /* structure representing 82xx Address Filtering PRAM
 479 */
 480 typedef struct uec_82xx_address_filtering_pram {
 481         u32  iaddr_h;        /* individual address filter, high */
 482         u32  iaddr_l;        /* individual address filter, low  */
 483         u32  gaddr_h;        /* group address filter, high      */
 484         u32  gaddr_l;        /* group address filter, low       */
 485         uec_82xx_enet_address_t    taddr;
 486         uec_82xx_enet_address_t    paddr[4];
 487         u8                         res0[0x40-0x38];
 488 } __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
 489
 490 /* Buffer Descriptor
 491 */
 492 typedef struct buffer_descriptor {
 493         u16 status;
 494         u16 len;
 495         u32 data;
 496 } __attribute__ ((packed)) qe_bd_t, *p_bd_t;
 497
 498 #define SIZEOFBD                sizeof(qe_bd_t)
 499
 500 /* Common BD flags
 501 */
 502 #define BD_WRAP                 0x2000
 503 #define BD_INT                  0x1000
 504 #define BD_LAST                 0x0800
 505 #define BD_CLEAN                0x3000
 506
 507 /* TxBD status flags
 508 */
 509 #define TxBD_READY              0x8000
 510 #define TxBD_PADCRC             0x4000
 511 #define TxBD_WRAP               BD_WRAP
 512 #define TxBD_INT                BD_INT
 513 #define TxBD_LAST               BD_LAST
 514 #define TxBD_TXCRC              0x0400
 515 #define TxBD_DEF                0x0200
 516 #define TxBD_PP                 0x0100
 517 #define TxBD_LC                 0x0080
 518 #define TxBD_RL                 0x0040
 519 #define TxBD_RC                 0x003C
 520 #define TxBD_UNDERRUN           0x0002
 521 #define TxBD_TRUNC              0x0001
 522
 523 #define TxBD_ERROR              (TxBD_UNDERRUN | TxBD_TRUNC)
 524
 525 /* RxBD status flags
 526 */
 527 #define RxBD_EMPTY              0x8000
 528 #define RxBD_OWNER              0x4000
 529 #define RxBD_WRAP               BD_WRAP
 530 #define RxBD_INT                BD_INT
 531 #define RxBD_LAST               BD_LAST
 532 #define RxBD_FIRST              0x0400
 533 #define RxBD_CMR                0x0200
 534 #define RxBD_MISS               0x0100
 535 #define RxBD_BCAST              0x0080
 536 #define RxBD_MCAST              0x0040
 537 #define RxBD_LG                 0x0020
 538 #define RxBD_NO                 0x0010
 539 #define RxBD_SHORT              0x0008
 540 #define RxBD_CRCERR             0x0004
 541 #define RxBD_OVERRUN            0x0002
 542 #define RxBD_IPCH               0x0001
 543
 544 #define RxBD_ERROR              (RxBD_LG | RxBD_NO | RxBD_SHORT | \
 545                                  RxBD_CRCERR | RxBD_OVERRUN)
 546
 547 /* BD access macros
 548 */
 549 #define BD_STATUS(_bd)                  (((p_bd_t)(_bd))->status)
 550 #define BD_STATUS_SET(_bd, _val)        (((p_bd_t)(_bd))->status = _val)
 551 #define BD_LENGTH(_bd)                  (((p_bd_t)(_bd))->len)
 552 #define BD_LENGTH_SET(_bd, _val)        (((p_bd_t)(_bd))->len = _val)
 553 #define BD_DATA_CLEAR(_bd)              (((p_bd_t)(_bd))->data = 0)
 554 #define BD_IS_DATA(_bd)                 (((p_bd_t)(_bd))->data)
 555 #define BD_DATA(_bd)                    ((u8 *)(((p_bd_t)(_bd))->data))
 556 #define BD_DATA_SET(_bd, _data)         (((p_bd_t)(_bd))->data = (u32)(_data))
 557 #define BD_ADVANCE(_bd,_status,_base)   \
 558         (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
 559
 560 /* Rx Prefetched BDs
 561 */
 562 typedef struct uec_rx_prefetched_bds {
 563     qe_bd_t   bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
 564 } __attribute__ ((packed)) uec_rx_prefetched_bds_t;
 565
 566 /* Alignments
 567  */
 568 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT                            64
 569 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT                            64
 570 #define UEC_THREAD_RX_PRAM_ALIGNMENT                            128
 571 #define UEC_THREAD_TX_PRAM_ALIGNMENT                            64
 572 #define UEC_THREAD_DATA_ALIGNMENT                               256
 573 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT               32
 574 #define UEC_SCHEDULER_ALIGNMENT                                 4
 575 #define UEC_TX_STATISTICS_ALIGNMENT                             4
 576 #define UEC_RX_STATISTICS_ALIGNMENT                             4
 577 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT                   4
 578 #define UEC_RX_BD_QUEUES_ALIGNMENT                              8
 579 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT                         128
 580 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT   4
 581 #define UEC_RX_BD_RING_ALIGNMENT                                32
 582 #define UEC_TX_BD_RING_ALIGNMENT                                32
 583 #define UEC_MRBLR_ALIGNMENT                                     128
 584 #define UEC_RX_BD_RING_SIZE_ALIGNMENT                           4
 585 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT                    32
 586 #define UEC_RX_DATA_BUF_ALIGNMENT                               64
 587
 588 #define UEC_VLAN_PRIORITY_MAX                                   8
 589 #define UEC_IP_PRIORITY_MAX                                     64
 590 #define UEC_TX_VTAG_TABLE_ENTRY_MAX                             8
 591 #define UEC_RX_BD_RING_SIZE_MIN                                 8
 592 #define UEC_TX_BD_RING_SIZE_MIN                                 2
 593
 594 /* Ethernet speed
 595 */
 596 typedef enum enet_speed {
 597         ENET_SPEED_10BT,   /* 10 Base T */
 598         ENET_SPEED_100BT,  /* 100 Base T */
 599         ENET_SPEED_1000BT  /* 1000 Base T */
 600 } enet_speed_e;
 601
 602 /* Ethernet Address Type.
 603 */
 604 typedef enum enet_addr_type {
 605         ENET_ADDR_TYPE_INDIVIDUAL,
 606         ENET_ADDR_TYPE_GROUP,
 607         ENET_ADDR_TYPE_BROADCAST
 608 } enet_addr_type_e;
 609
 610 /* TBI / MII Set Register
 611 */
 612 typedef enum enet_tbi_mii_reg {
 613         ENET_TBI_MII_CR        = 0x00,
 614         ENET_TBI_MII_SR        = 0x01,
 615         ENET_TBI_MII_ANA       = 0x04,
 616         ENET_TBI_MII_ANLPBPA   = 0x05,
 617         ENET_TBI_MII_ANEX      = 0x06,
 618         ENET_TBI_MII_ANNPT     = 0x07,
 619         ENET_TBI_MII_ANLPANP   = 0x08,
 620         ENET_TBI_MII_EXST      = 0x0F,
 621         ENET_TBI_MII_JD        = 0x10,
 622         ENET_TBI_MII_TBICON    = 0x11
 623 } enet_tbi_mii_reg_e;
 624
 625 /* TBI MDIO register bit fields*/
 626 #define TBICON_CLK_SELECT       0x0020
 627 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
 628 #define TBIANA_SYMMETRIC_PAUSE  0x0080
 629 #define TBIANA_HALF_DUPLEX      0x0040
 630 #define TBIANA_FULL_DUPLEX      0x0020
 631 #define TBICR_PHY_RESET         0x8000
 632 #define TBICR_ANEG_ENABLE       0x1000
 633 #define TBICR_RESTART_ANEG      0x0200
 634 #define TBICR_FULL_DUPLEX       0x0100
 635 #define TBICR_SPEED1_SET        0x0040
 636
 637 #define TBIANA_SETTINGS ( \
 638                 TBIANA_ASYMMETRIC_PAUSE \
 639                 | TBIANA_SYMMETRIC_PAUSE \
 640                 | TBIANA_FULL_DUPLEX \
 641                 )
 642
 643 #define TBICR_SETTINGS ( \
 644                 TBICR_PHY_RESET \
 645                 | TBICR_ANEG_ENABLE \
 646                 | TBICR_FULL_DUPLEX \
 647                 | TBICR_SPEED1_SET \
 648                 )
 649
 650 /* UEC number of threads
 651 */
 652 typedef enum uec_num_of_threads {
 653         UEC_NUM_OF_THREADS_1  = 0x1,  /* 1 */
 654         UEC_NUM_OF_THREADS_2  = 0x2,  /* 2 */
 655         UEC_NUM_OF_THREADS_4  = 0x0,  /* 4 */
 656         UEC_NUM_OF_THREADS_6  = 0x3,  /* 6 */
 657         UEC_NUM_OF_THREADS_8  = 0x4   /* 8 */
 658 } uec_num_of_threads_e;
 659
 660 /* UEC ethernet interface type
 661 */
 662 typedef enum enet_interface {
 663         ENET_10_MII,
 664         ENET_10_RMII,
 665         ENET_10_RGMII,
 666         ENET_100_MII,
 667         ENET_100_RMII,
 668         ENET_100_RGMII,
 669         ENET_1000_GMII,
 670         ENET_1000_RGMII,
 671         ENET_1000_RGMII_ID,
 672         ENET_1000_RGMII_RXID,
 673         ENET_1000_TBI,
 674         ENET_1000_RTBI,
 675         ENET_1000_SGMII
 676 } enet_interface_e;
 677
 678 /* UEC initialization info struct
 679 */
 680 #define STD_UEC_INFO(num) \
 681 {                       \
 682         .uf_info                = {     \
 683                 .ucc_num        = CONFIG_SYS_UEC##num##_UCC_NUM,\
 684                 .rx_clock       = CONFIG_SYS_UEC##num##_RX_CLK, \
 685                 .tx_clock       = CONFIG_SYS_UEC##num##_TX_CLK, \
 686                 .eth_type       = CONFIG_SYS_UEC##num##_ETH_TYPE,\
 687         },      \
 688         .num_threads_tx         = UEC_NUM_OF_THREADS_1, \
 689         .num_threads_rx         = UEC_NUM_OF_THREADS_1, \
 690         .risc_tx                = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
 691         .risc_rx                = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
 692         .tx_bd_ring_len         = 16,   \
 693         .rx_bd_ring_len         = 16,   \
 694         .phy_address            = CONFIG_SYS_UEC##num##_PHY_ADDR, \
 695         .enet_interface         = CONFIG_SYS_UEC##num##_INTERFACE_MODE, \
 696 }
 697
 698 typedef struct uec_info {
 699         ucc_fast_info_t                 uf_info;
 700         uec_num_of_threads_e            num_threads_tx;
 701         uec_num_of_threads_e            num_threads_rx;
 702         unsigned int                    risc_tx;
 703         unsigned int                    risc_rx;
 704         u16                             rx_bd_ring_len;
 705         u16                             tx_bd_ring_len;
 706         u8                              phy_address;
 707         enet_interface_e                enet_interface;
 708 } uec_info_t;
 709
 710 /* UEC driver initialized info
 711 */
 712 #define MAX_RXBUF_LEN                   1536
 713 #define MAX_FRAME_LEN                   1518
 714 #define MIN_FRAME_LEN                   64
 715 #define MAX_DMA1_LEN                    1520
 716 #define MAX_DMA2_LEN                    1520
 717
 718 /* UEC driver private struct
 719 */
 720 typedef struct uec_private {
 721         uec_info_t                      *uec_info;
 722         ucc_fast_private_t              *uccf;
 723         struct eth_device               *dev;
 724         uec_t                           *uec_regs;
 725         uec_mii_t                       *uec_mii_regs;
 726         /* enet init command parameter */
 727         uec_init_cmd_pram_t             *p_init_enet_param;
 728         u32                             init_enet_param_offset;
 729         /* Rx and Tx paramter */
 730         uec_rx_global_pram_t            *p_rx_glbl_pram;
 731         u32                             rx_glbl_pram_offset;
 732         uec_tx_global_pram_t            *p_tx_glbl_pram;
 733         u32                             tx_glbl_pram_offset;
 734         uec_send_queue_mem_region_t     *p_send_q_mem_reg;
 735         u32                             send_q_mem_reg_offset;
 736         uec_thread_data_tx_t            *p_thread_data_tx;
 737         u32                             thread_dat_tx_offset;
 738         uec_thread_data_rx_t            *p_thread_data_rx;
 739         u32                             thread_dat_rx_offset;
 740         uec_rx_bd_queues_entry_t        *p_rx_bd_qs_tbl;
 741         u32                             rx_bd_qs_tbl_offset;
 742         /* BDs specific */
 743         u8                              *p_tx_bd_ring;
 744         u32                             tx_bd_ring_offset;
 745         u8                              *p_rx_bd_ring;
 746         u32                             rx_bd_ring_offset;
 747         u8                              *p_rx_buf;
 748         u32                             rx_buf_offset;
 749         volatile qe_bd_t                *txBd;
 750         volatile qe_bd_t                *rxBd;
 751         /* Status */
 752         int                             mac_tx_enabled;
 753         int                             mac_rx_enabled;
 754         int                             grace_stopped_tx;
 755         int                             grace_stopped_rx;
 756         int                             the_first_run;
 757         /* PHY specific */
 758         struct uec_mii_info             *mii_info;
 759         int                             oldspeed;
 760         int                             oldduplex;
 761         int                             oldlink;
 762 } uec_private_t;
 763
 764 int uec_initialize(bd_t *bis, uec_info_t *uec_info);
 765 int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);
 766 int uec_standard_init(bd_t *bis);
 767 #endif /* __UEC_H__ */