2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2010 Orex Computed Radiography
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
15 /* based on rtc-mc13892.c */
18 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
19 * to implement a Linux RTC. Times and alarms are truncated to seconds.
20 * Since the RTC framework performs API locking via rtc->ops_lock the
21 * only simultaneous accesses we need to deal with is updating DryIce
22 * registers while servicing an alarm.
24 * Note that reading the DSR (DryIce Status Register) automatically clears
25 * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
26 * LP (Low Power) domain and set the WCF upon completion. Writes to the
27 * DIER (DryIce Interrupt Enable Register) are the only exception. These
28 * occur at normal bus speeds and do not set WCF. Periodic interrupts are
29 * not supported by the hardware.
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/module.h>
36 #include <linux/platform_device.h>
37 #include <linux/rtc.h>
38 #include <linux/sched.h>
39 #include <linux/workqueue.h>
42 /* DryIce Register Definitions */
44 #define DTCMR 0x00 /* Time Counter MSB Reg */
45 #define DTCLR 0x04 /* Time Counter LSB Reg */
47 #define DCAMR 0x08 /* Clock Alarm MSB Reg */
48 #define DCALR 0x0c /* Clock Alarm LSB Reg */
49 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
51 #define DCR 0x10 /* Control Reg */
52 #define DCR_TCE (1 << 3) /* Time Counter Enable */
54 #define DSR 0x14 /* Status Reg */
55 #define DSR_WBF (1 << 10) /* Write Busy Flag */
56 #define DSR_WNF (1 << 9) /* Write Next Flag */
57 #define DSR_WCF (1 << 8) /* Write Complete Flag */
58 #define DSR_WEF (1 << 7) /* Write Error Flag */
59 #define DSR_CAF (1 << 4) /* Clock Alarm Flag */
60 #define DSR_NVF (1 << 1) /* Non-Valid Flag */
61 #define DSR_SVF (1 << 0) /* Security Violation Flag */
63 #define DIER 0x18 /* Interrupt Enable Reg */
64 #define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
65 #define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
66 #define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
67 #define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
70 * struct imxdi_dev - private imxdi rtc data
71 * @pdev: pionter to platform dev
72 * @rtc: pointer to rtc struct
73 * @ioaddr: IO registers pointer
74 * @irq: dryice normal interrupt
75 * @clk: input reference clock
76 * @dsr: copy of the DSR register
77 * @irq_lock: interrupt enable register (DIER) lock
78 * @write_wait: registers write complete queue
79 * @write_mutex: serialize registers write
80 * @work: schedule alarm work
83 struct platform_device *pdev;
84 struct rtc_device *rtc;
90 wait_queue_head_t write_wait;
91 struct mutex write_mutex;
92 struct work_struct work;
96 * enable a dryice interrupt
98 static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
102 spin_lock_irqsave(&imxdi->irq_lock, flags);
103 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr,
104 imxdi->ioaddr + DIER);
105 spin_unlock_irqrestore(&imxdi->irq_lock, flags);
109 * disable a dryice interrupt
111 static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
115 spin_lock_irqsave(&imxdi->irq_lock, flags);
116 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
117 imxdi->ioaddr + DIER);
118 spin_unlock_irqrestore(&imxdi->irq_lock, flags);
122 * This function attempts to clear the dryice write-error flag.
124 * A dryice write error is similar to a bus fault and should not occur in
125 * normal operation. Clearing the flag requires another write, so the root
126 * cause of the problem may need to be fixed before the flag can be cleared.
128 static void clear_write_error(struct imxdi_dev *imxdi)
132 dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
134 /* clear the write error flag */
135 __raw_writel(DSR_WEF, imxdi->ioaddr + DSR);
137 /* wait for it to take effect */
138 for (cnt = 0; cnt < 1000; cnt++) {
139 if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
143 dev_err(&imxdi->pdev->dev,
144 "ERROR: Cannot clear write-error flag!\n");
148 * Write a dryice register and wait until it completes.
150 * This function uses interrupts to determine when the
151 * write has completed.
153 static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
158 /* serialize register writes */
159 mutex_lock(&imxdi->write_mutex);
161 /* enable the write-complete interrupt */
162 di_int_enable(imxdi, DIER_WCIE);
166 /* do the register write */
167 __raw_writel(val, imxdi->ioaddr + reg);
169 /* wait for the write to finish */
170 ret = wait_event_interruptible_timeout(imxdi->write_wait,
171 imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
175 } else if (ret == 0) {
176 dev_warn(&imxdi->pdev->dev,
177 "Write-wait timeout "
178 "val = 0x%08x reg = 0x%08x\n", val, reg);
181 /* check for write error */
182 if (imxdi->dsr & DSR_WEF) {
183 clear_write_error(imxdi);
188 mutex_unlock(&imxdi->write_mutex);
194 * read the seconds portion of the current time from the dryice time counter
196 static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
198 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
201 now = __raw_readl(imxdi->ioaddr + DTCMR);
202 rtc_time_to_tm(now, tm);
208 * set the seconds portion of dryice time counter and clear the
211 static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
213 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
216 /* zero the fractional part first */
217 rc = di_write_wait(imxdi, 0, DTCLR);
219 rc = di_write_wait(imxdi, secs, DTCMR);
224 static int dryice_rtc_alarm_irq_enable(struct device *dev,
225 unsigned int enabled)
227 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
230 di_int_enable(imxdi, DIER_CAIE);
232 di_int_disable(imxdi, DIER_CAIE);
238 * read the seconds portion of the alarm register.
239 * the fractional part of the alarm register is always zero.
241 static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
243 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
246 dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
247 rtc_time_to_tm(dcamr, &alarm->time);
249 /* alarm is enabled if the interrupt is enabled */
250 alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
252 /* don't allow the DSR read to mess up DSR_WCF */
253 mutex_lock(&imxdi->write_mutex);
255 /* alarm is pending if the alarm flag is set */
256 alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
258 mutex_unlock(&imxdi->write_mutex);
264 * set the seconds portion of dryice alarm register
266 static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
268 struct imxdi_dev *imxdi = dev_get_drvdata(dev);
270 unsigned long alarm_time;
273 rc = rtc_tm_to_time(&alarm->time, &alarm_time);
277 /* don't allow setting alarm in the past */
278 now = __raw_readl(imxdi->ioaddr + DTCMR);
279 if (alarm_time < now)
282 /* write the new alarm time */
283 rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
288 di_int_enable(imxdi, DIER_CAIE); /* enable alarm intr */
290 di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
295 static struct rtc_class_ops dryice_rtc_ops = {
296 .read_time = dryice_rtc_read_time,
297 .set_mmss = dryice_rtc_set_mmss,
298 .alarm_irq_enable = dryice_rtc_alarm_irq_enable,
299 .read_alarm = dryice_rtc_read_alarm,
300 .set_alarm = dryice_rtc_set_alarm,
304 * dryice "normal" interrupt handler
306 static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
308 struct imxdi_dev *imxdi = dev_id;
310 irqreturn_t rc = IRQ_NONE;
312 dier = __raw_readl(imxdi->ioaddr + DIER);
314 /* handle write complete and write error cases */
315 if ((dier & DIER_WCIE)) {
316 /*If the write wait queue is empty then there is no pending
317 operations. It means the interrupt is for DryIce -Security.
318 IRQ must be returned as none.*/
319 if (list_empty_careful(&imxdi->write_wait.task_list))
322 /* DSR_WCF clears itself on DSR read */
323 dsr = __raw_readl(imxdi->ioaddr + DSR);
324 if ((dsr & (DSR_WCF | DSR_WEF))) {
325 /* mask the interrupt */
326 di_int_disable(imxdi, DIER_WCIE);
328 /* save the dsr value for the wait queue */
331 wake_up_interruptible(&imxdi->write_wait);
336 /* handle the alarm case */
337 if ((dier & DIER_CAIE)) {
338 /* DSR_WCF clears itself on DSR read */
339 dsr = __raw_readl(imxdi->ioaddr + DSR);
341 /* mask the interrupt */
342 di_int_disable(imxdi, DIER_CAIE);
344 /* finish alarm in user context */
345 schedule_work(&imxdi->work);
353 * post the alarm event from user context so it can sleep
354 * on the write completion.
356 static void dryice_work(struct work_struct *work)
358 struct imxdi_dev *imxdi = container_of(work,
359 struct imxdi_dev, work);
361 /* dismiss the interrupt (ignore error) */
362 di_write_wait(imxdi, DSR_CAF, DSR);
364 /* pass the alarm event to the rtc framework. */
365 rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
369 * probe for dryice rtc device
371 static int dryice_rtc_probe(struct platform_device *pdev)
373 struct resource *res;
374 struct imxdi_dev *imxdi;
377 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
381 imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
387 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
391 imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start,
393 if (imxdi->ioaddr == NULL)
396 spin_lock_init(&imxdi->irq_lock);
398 imxdi->irq = platform_get_irq(pdev, 0);
402 init_waitqueue_head(&imxdi->write_wait);
404 INIT_WORK(&imxdi->work, dryice_work);
406 mutex_init(&imxdi->write_mutex);
408 imxdi->clk = clk_get(&pdev->dev, NULL);
409 if (IS_ERR(imxdi->clk))
410 return PTR_ERR(imxdi->clk);
411 clk_prepare_enable(imxdi->clk);
414 * Initialize dryice hardware
417 /* mask all interrupts */
418 __raw_writel(0, imxdi->ioaddr + DIER);
420 rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
421 IRQF_SHARED, pdev->name, imxdi);
423 dev_warn(&pdev->dev, "interrupt not available.\n");
427 /* put dryice into valid state */
428 if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
429 rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR);
434 /* initialize alarm */
435 rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
438 rc = di_write_wait(imxdi, 0, DCALR);
442 /* clear alarm flag */
443 if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
444 rc = di_write_wait(imxdi, DSR_CAF, DSR);
449 /* the timer won't count if it has never been written to */
450 if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
451 rc = di_write_wait(imxdi, 0, DTCMR);
456 /* start keeping time */
457 if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
458 rc = di_write_wait(imxdi,
459 __raw_readl(imxdi->ioaddr + DCR) | DCR_TCE,
465 platform_set_drvdata(pdev, imxdi);
466 imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev,
467 &dryice_rtc_ops, THIS_MODULE);
468 if (IS_ERR(imxdi->rtc)) {
469 rc = PTR_ERR(imxdi->rtc);
476 clk_disable_unprepare(imxdi->clk);
482 static int __devexit dryice_rtc_remove(struct platform_device *pdev)
484 struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
486 flush_work(&imxdi->work);
488 /* mask all interrupts */
489 __raw_writel(0, imxdi->ioaddr + DIER);
491 rtc_device_unregister(imxdi->rtc);
493 clk_disable_unprepare(imxdi->clk);
500 static const struct of_device_id dryice_dt_ids[] = {
501 { .compatible = "fsl,imx25-rtc" },
505 MODULE_DEVICE_TABLE(of, dryice_dt_ids);
508 static struct platform_driver dryice_rtc_driver = {
511 .owner = THIS_MODULE,
512 .of_match_table = of_match_ptr(dryice_dt_ids),
514 .remove = __devexit_p(dryice_rtc_remove),
517 static int __init dryice_rtc_init(void)
519 return platform_driver_probe(&dryice_rtc_driver, dryice_rtc_probe);
522 static void __exit dryice_rtc_exit(void)
524 platform_driver_unregister(&dryice_rtc_driver);
527 module_init(dryice_rtc_init);
528 module_exit(dryice_rtc_exit);
530 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
531 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
532 MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
533 MODULE_LICENSE("GPL");