3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* This code should work for both the S3C2400 and the S3C2410
25 * as they seem to have the same I2C controller inside.
26 * The different address mapping is handled by the s3c24xx.h files below.
31 #ifdef CONFIG_DRIVER_S3C24X0_I2C
33 #if defined(CONFIG_S3C2400)
35 #elif defined(CONFIG_S3C2410)
40 #ifdef CONFIG_HARD_I2C
48 #define I2C_NOK_LA 3 /* Lost arbitration */
49 #define I2C_NOK_TOUT 4 /* time out */
51 #define I2CSTAT_BSY 0x20 /* Busy bit */
52 #define I2CSTAT_NACK 0x01 /* Nack bit */
53 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */
54 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
55 #define I2C_MODE_MR 0x80 /* Master Receive Mode */
56 #define I2C_START_STOP 0x20 /* START / STOP */
57 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
59 #define I2C_TIMEOUT 1 /* 1 seconde */
62 static int GetI2CSDA(void)
64 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
67 return (gpio->GPEDAT & 0x8000) >> 15;
70 return (gpio->PGDAT & 0x0020) >> 5;
75 static void SetI2CSDA(int x)
77 rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
81 static void SetI2CSCL(int x)
83 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
86 gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
89 gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6;
94 static int WaitForXfer(void)
96 S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
99 i = I2C_TIMEOUT * 1000;
100 status = i2c->IICCON;
101 while ((i > 0) && !(status & I2CCON_IRPND)) {
103 status = i2c->IICCON;
107 return(status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
110 static int IsACK(void)
112 S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
114 return(!(i2c->IICSTAT & I2CSTAT_NACK));
117 static void ReadWriteByte(void)
119 S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
121 i2c->IICCON &= ~I2CCON_IRPND;
124 void i2c_init (int speed, int slaveadd)
126 S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
127 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
128 ulong freq, pres = 16, div;
131 /* wait for some time to give previous transfer a chance to finish */
133 i = I2C_TIMEOUT * 1000;
134 status = i2c->IICSTAT;
135 while ((i > 0) && (status & I2CSTAT_BSY)) {
137 status = i2c->IICSTAT;
141 if ((status & I2CSTAT_BSY) || GetI2CSDA() == 0) {
142 #ifdef CONFIG_S3C2410
143 ulong old_gpecon = gpio->GPECON;
145 #ifdef CONFIG_S3C2400
146 ulong old_gpecon = gpio->PGCON;
148 /* bus still busy probably by (most) previously interrupted transfer */
150 #ifdef CONFIG_S3C2410
151 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
152 gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
154 #ifdef CONFIG_S3C2400
155 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
156 gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00;
159 /* toggle I2CSCL until bus idle */
160 SetI2CSCL(0); udelay(1000);
162 while ((i > 0) && (GetI2CSDA() != 1)) {
163 SetI2CSCL(1); udelay(1000);
164 SetI2CSCL(0); udelay(1000);
167 SetI2CSCL(1); udelay(1000);
169 /* restore pin functions */
170 #ifdef CONFIG_S3C2410
171 gpio->GPECON = old_gpecon;
173 #ifdef CONFIG_S3C2400
174 gpio->PGCON = old_gpecon;
178 /* calculate prescaler and divisor values */
180 if ((freq / pres / (16+1)) > speed)
181 /* set prescaler to 512 */
185 while ((freq / pres / (div+1)) > speed)
188 /* set prescaler, divisor according to freq, also set
190 i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
192 /* init to SLAVE REVEIVE and set slaveaddr */
194 i2c->IICADD = slaveadd;
195 /* program Master Transmit (and implicit STOP) */
196 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
201 cmd_type is 0 for write 1 for read.
203 addr_len can take any value from 0-255, it is only limited
204 by the char, we could make it larger if needed. If it is
205 0 we skip the address write cycle.
209 int i2c_transfer(unsigned char cmd_type,
211 unsigned char addr[],
212 unsigned char addr_len,
213 unsigned char data[],
214 unsigned short data_len)
216 S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C();
217 int i, status, result;
219 if (data == 0 || data_len == 0) {
220 /*Don't support data transfer of no length or to address 0*/
221 printf( "i2c_transfer: bad call\n" );
227 /* Check I2C bus idle */
228 i = I2C_TIMEOUT * 1000;
229 status = i2c->IICSTAT;
230 while ((i > 0) && (status & I2CSTAT_BSY)) {
232 status = i2c->IICSTAT;
237 if (status & I2CSTAT_BSY) {
238 result = I2C_NOK_TOUT;
248 if (addr && addr_len) {
251 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
253 while ((i < addr_len) && (result == I2C_OK)) {
254 result = WaitForXfer();
255 i2c->IICDS = addr[i];
260 while ((i < data_len) && (result == I2C_OK)) {
261 result = WaitForXfer();
262 i2c->IICDS = data[i];
269 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
271 while ((i < data_len) && (result = I2C_OK)) {
272 result = WaitForXfer();
273 i2c->IICDS = data[i];
279 if (result == I2C_OK)
280 result = WaitForXfer();
283 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
288 if (addr && addr_len) {
289 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
292 i2c->IICSTAT |= I2C_START_STOP;
293 result = WaitForXfer();
296 while ((i < addr_len) && (result == I2C_OK)) {
297 i2c->IICDS = addr[i];
299 result = WaitForXfer();
305 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP;
307 result = WaitForXfer();
309 while ((i < data_len) && (result == I2C_OK)) {
310 /* disable ACK for final READ */
311 if (i == data_len - 1)
312 i2c->IICCON &= ~0x80;
314 result = WaitForXfer();
315 data[i] = i2c->IICDS;
323 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
326 i2c->IICSTAT |= I2C_START_STOP;
327 result = WaitForXfer();
331 while ((i < data_len) && (result == I2C_OK)) {
332 /* disable ACK for final READ */
333 if (i == data_len - 1)
334 i2c->IICCON &= ~0x80;
336 result = WaitForXfer();
337 data[i] = i2c->IICDS;
346 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
351 printf( "i2c_transfer: bad call\n" );
359 int i2c_probe (uchar chip)
366 * What is needed is to send the chip address and verify that the
367 * address was <ACK>ed (i.e. there was a chip at that address which
368 * drove the data line low).
370 return(i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK);
373 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
379 printf ("I2C read: addr len %d not supported\n", alen);
384 xaddr[0] = (addr >> 24) & 0xFF;
385 xaddr[1] = (addr >> 16) & 0xFF;
386 xaddr[2] = (addr >> 8) & 0xFF;
387 xaddr[3] = addr & 0xFF;
391 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
393 * EEPROM chips that implement "address overflow" are ones
394 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
395 * address and the extra bits end up in the "chip address"
396 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
397 * four 256 byte chips.
399 * Note that we consider the length of the address field to
400 * still be one byte because the extra address bits are
401 * hidden in the chip address.
404 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
406 if( (ret = i2c_transfer(I2C_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
407 printf( "I2c read: failed %d\n", ret);
413 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
418 printf ("I2C write: addr len %d not supported\n", alen);
423 xaddr[0] = (addr >> 24) & 0xFF;
424 xaddr[1] = (addr >> 16) & 0xFF;
425 xaddr[2] = (addr >> 8) & 0xFF;
426 xaddr[3] = addr & 0xFF;
429 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
431 * EEPROM chips that implement "address overflow" are ones
432 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
433 * address and the extra bits end up in the "chip address"
434 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
435 * four 256 byte chips.
437 * Note that we consider the length of the address field to
438 * still be one byte because the extra address bits are
439 * hidden in the chip address.
442 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
444 return (i2c_transfer(I2C_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
447 #endif /* CONFIG_HARD_I2C */
449 #endif /* CONFIG_DRIVER_S3C24X0_I2C */