1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4" /* AdvanSys Driver Version */
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10 * All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/firmware.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
69 * 8. Add module_param to override ISA/VLB ioport array
71 #warning this driver is still not properly converted to the DMA API
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
76 /* Enable driver tracing. */
79 typedef unsigned char uchar;
81 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
83 #define PCI_VENDOR_ID_ASP 0x10cd
84 #define PCI_DEVICE_ID_ASP_1200A 0x1100
85 #define PCI_DEVICE_ID_ASP_ABP940 0x1200
86 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300
87 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
88 #define PCI_DEVICE_ID_38C0800_REV1 0x2500
89 #define PCI_DEVICE_ID_38C1600_REV1 0x2700
92 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
93 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
94 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
97 #define CC_VERY_LONG_SG_LIST 0
98 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
100 #define PortAddr unsigned int /* port address size */
101 #define inp(port) inb(port)
102 #define outp(port, byte) outb((byte), (port))
104 #define inpw(port) inw(port)
105 #define outpw(port, word) outw((word), (port))
107 #define ASC_MAX_SG_QUEUE 7
108 #define ASC_MAX_SG_LIST 255
110 #define ASC_CS_TYPE unsigned short
112 #define ASC_IS_ISA (0x0001)
113 #define ASC_IS_ISAPNP (0x0081)
114 #define ASC_IS_EISA (0x0002)
115 #define ASC_IS_PCI (0x0004)
116 #define ASC_IS_PCI_ULTRA (0x0104)
117 #define ASC_IS_PCMCIA (0x0008)
118 #define ASC_IS_MCA (0x0020)
119 #define ASC_IS_VL (0x0040)
120 #define ASC_IS_WIDESCSI_16 (0x0100)
121 #define ASC_IS_WIDESCSI_32 (0x0200)
122 #define ASC_IS_BIG_ENDIAN (0x8000)
124 #define ASC_CHIP_MIN_VER_VL (0x01)
125 #define ASC_CHIP_MAX_VER_VL (0x07)
126 #define ASC_CHIP_MIN_VER_PCI (0x09)
127 #define ASC_CHIP_MAX_VER_PCI (0x0F)
128 #define ASC_CHIP_VER_PCI_BIT (0x08)
129 #define ASC_CHIP_MIN_VER_ISA (0x11)
130 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
131 #define ASC_CHIP_MAX_VER_ISA (0x27)
132 #define ASC_CHIP_VER_ISA_BIT (0x30)
133 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
134 #define ASC_CHIP_VER_ASYN_BUG (0x21)
135 #define ASC_CHIP_VER_PCI 0x08
136 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
137 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
138 #define ASC_CHIP_MIN_VER_EISA (0x41)
139 #define ASC_CHIP_MAX_VER_EISA (0x47)
140 #define ASC_CHIP_VER_EISA_BIT (0x40)
141 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
142 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
143 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
144 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
146 #define ASC_SCSI_ID_BITS 3
147 #define ASC_SCSI_TIX_TYPE uchar
148 #define ASC_ALL_DEVICE_BIT_SET 0xFF
149 #define ASC_SCSI_BIT_ID_TYPE uchar
150 #define ASC_MAX_TID 7
151 #define ASC_MAX_LUN 7
152 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
153 #define ASC_MAX_SENSE_LEN 32
154 #define ASC_MIN_SENSE_LEN 14
155 #define ASC_SCSI_RESET_HOLD_TIME_US 60
158 * Narrow boards only support 12-byte commands, while wide boards
159 * extend to 16-byte commands.
161 #define ASC_MAX_CDB_LEN 12
162 #define ADV_MAX_CDB_LEN 16
164 #define MS_SDTR_LEN 0x03
165 #define MS_WDTR_LEN 0x02
167 #define ASC_SG_LIST_PER_Q 7
169 #define QS_READY 0x01
170 #define QS_DISC1 0x02
171 #define QS_DISC2 0x04
173 #define QS_ABORTED 0x40
175 #define QC_NO_CALLBACK 0x01
176 #define QC_SG_SWAP_QUEUE 0x02
177 #define QC_SG_HEAD 0x04
178 #define QC_DATA_IN 0x08
179 #define QC_DATA_OUT 0x10
180 #define QC_URGENT 0x20
181 #define QC_MSG_OUT 0x40
182 #define QC_REQ_SENSE 0x80
183 #define QCSG_SG_XFER_LIST 0x02
184 #define QCSG_SG_XFER_MORE 0x04
185 #define QCSG_SG_XFER_END 0x08
186 #define QD_IN_PROGRESS 0x00
187 #define QD_NO_ERROR 0x01
188 #define QD_ABORTED_BY_HOST 0x02
189 #define QD_WITH_ERROR 0x04
190 #define QD_INVALID_REQUEST 0x80
191 #define QD_INVALID_HOST_NUM 0x81
192 #define QD_INVALID_DEVICE 0x82
193 #define QD_ERR_INTERNAL 0xFF
194 #define QHSTA_NO_ERROR 0x00
195 #define QHSTA_M_SEL_TIMEOUT 0x11
196 #define QHSTA_M_DATA_OVER_RUN 0x12
197 #define QHSTA_M_DATA_UNDER_RUN 0x12
198 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
199 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
200 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
201 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
202 #define QHSTA_D_HOST_ABORT_FAILED 0x23
203 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
204 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
205 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
206 #define QHSTA_M_WTM_TIMEOUT 0x41
207 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
208 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
209 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
210 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
211 #define QHSTA_M_BAD_TAG_CODE 0x46
212 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
213 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
214 #define QHSTA_D_LRAM_CMP_ERROR 0x81
215 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
216 #define ASC_FLAG_SCSIQ_REQ 0x01
217 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
218 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
219 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
220 #define ASC_FLAG_WIN16 0x10
221 #define ASC_FLAG_WIN32 0x20
222 #define ASC_FLAG_ISA_OVER_16MB 0x40
223 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
224 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
225 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
226 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
227 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
228 #define ASC_SCSIQ_CPY_BEG 4
229 #define ASC_SCSIQ_SGHD_CPY_BEG 2
230 #define ASC_SCSIQ_B_FWD 0
231 #define ASC_SCSIQ_B_BWD 1
232 #define ASC_SCSIQ_B_STATUS 2
233 #define ASC_SCSIQ_B_QNO 3
234 #define ASC_SCSIQ_B_CNTL 4
235 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
236 #define ASC_SCSIQ_D_DATA_ADDR 8
237 #define ASC_SCSIQ_D_DATA_CNT 12
238 #define ASC_SCSIQ_B_SENSE_LEN 20
239 #define ASC_SCSIQ_DONE_INFO_BEG 22
240 #define ASC_SCSIQ_D_SRBPTR 22
241 #define ASC_SCSIQ_B_TARGET_IX 26
242 #define ASC_SCSIQ_B_CDB_LEN 28
243 #define ASC_SCSIQ_B_TAG_CODE 29
244 #define ASC_SCSIQ_W_VM_ID 30
245 #define ASC_SCSIQ_DONE_STATUS 32
246 #define ASC_SCSIQ_HOST_STATUS 33
247 #define ASC_SCSIQ_SCSI_STATUS 34
248 #define ASC_SCSIQ_CDB_BEG 36
249 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
250 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
251 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
252 #define ASC_SCSIQ_B_SG_WK_QP 49
253 #define ASC_SCSIQ_B_SG_WK_IX 50
254 #define ASC_SCSIQ_W_ALT_DC1 52
255 #define ASC_SCSIQ_B_LIST_CNT 6
256 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
257 #define ASC_SGQ_B_SG_CNTL 4
258 #define ASC_SGQ_B_SG_HEAD_QP 5
259 #define ASC_SGQ_B_SG_LIST_CNT 6
260 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
261 #define ASC_SGQ_LIST_BEG 8
262 #define ASC_DEF_SCSI1_QNG 4
263 #define ASC_MAX_SCSI1_QNG 4
264 #define ASC_DEF_SCSI2_QNG 16
265 #define ASC_MAX_SCSI2_QNG 32
266 #define ASC_TAG_CODE_MASK 0x23
267 #define ASC_STOP_REQ_RISC_STOP 0x01
268 #define ASC_STOP_ACK_RISC_STOP 0x03
269 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
270 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
271 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
272 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
273 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
274 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
275 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
276 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
277 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
278 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
280 typedef struct asc_scsiq_1 {
294 typedef struct asc_scsiq_2 {
303 typedef struct asc_scsiq_3 {
310 typedef struct asc_scsiq_4 {
311 uchar cdb[ASC_MAX_CDB_LEN];
312 uchar y_first_sg_list_qp;
313 uchar y_working_sg_qp;
314 uchar y_working_sg_ix;
317 ushort x_reconnect_rtn;
318 __le32 x_saved_data_addr;
319 __le32 x_saved_data_cnt;
322 typedef struct asc_q_done_info {
334 typedef struct asc_sg_list {
339 typedef struct asc_sg_head {
342 ushort entry_to_copy;
344 ASC_SG_LIST sg_list[0];
347 typedef struct asc_scsi_q {
351 ASC_SG_HEAD *sg_head;
352 ushort remain_sg_entry_cnt;
353 ushort next_sg_index;
356 typedef struct asc_scsi_req_q {
360 ASC_SG_HEAD *sg_head;
363 uchar cdb[ASC_MAX_CDB_LEN];
364 uchar sense[ASC_MIN_SENSE_LEN];
367 typedef struct asc_scsi_bios_req_q {
371 ASC_SG_HEAD *sg_head;
374 uchar cdb[ASC_MAX_CDB_LEN];
375 uchar sense[ASC_MIN_SENSE_LEN];
376 } ASC_SCSI_BIOS_REQ_Q;
378 typedef struct asc_risc_q {
387 typedef struct asc_sg_list_q {
393 uchar sg_cur_list_cnt;
396 typedef struct asc_risc_sg_list_q {
400 ASC_SG_LIST sg_list[7];
401 } ASC_RISC_SG_LIST_Q;
403 #define ASCQ_ERR_Q_STATUS 0x0D
404 #define ASCQ_ERR_CUR_QNG 0x17
405 #define ASCQ_ERR_SG_Q_LINKS 0x18
406 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
407 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
408 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
411 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
413 #define ASC_WARN_NO_ERROR 0x0000
414 #define ASC_WARN_IO_PORT_ROTATE 0x0001
415 #define ASC_WARN_EEPROM_CHKSUM 0x0002
416 #define ASC_WARN_IRQ_MODIFIED 0x0004
417 #define ASC_WARN_AUTO_CONFIG 0x0008
418 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
419 #define ASC_WARN_EEPROM_RECOVER 0x0020
420 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
423 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
425 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
426 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
427 #define ASC_IERR_SET_PC_ADDR 0x0004
428 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
429 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
430 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
431 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
432 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
433 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
434 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
435 #define ASC_IERR_NO_BUS_TYPE 0x0400
436 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
437 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
438 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
440 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
441 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
442 #define ASC_MIN_FREE_Q (0x02)
443 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
444 #define ASC_MAX_TOTAL_QNG 240
445 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
446 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
447 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
448 #define ASC_MAX_INRAM_TAG_QNG 16
449 #define ASC_IOADR_GAP 0x10
450 #define ASC_SYN_MAX_OFFSET 0x0F
451 #define ASC_DEF_SDTR_OFFSET 0x0F
452 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
453 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
455 /* The narrow chip only supports a limited selection of transfer rates.
456 * These are encoded in the range 0..7 or 0..15 depending whether the chip
457 * is Ultra-capable or not. These tables let us convert from one to the other.
459 static const unsigned char asc_syn_xfer_period[8] = {
460 25, 30, 35, 40, 50, 60, 70, 85
463 static const unsigned char asc_syn_ultra_xfer_period[16] = {
464 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
467 typedef struct ext_msg {
473 uchar sdtr_xfer_period;
474 uchar sdtr_req_ack_offset;
489 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
490 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
491 #define wdtr_width u_ext_msg.wdtr.wdtr_width
492 #define mdp_b3 u_ext_msg.mdp_b3
493 #define mdp_b2 u_ext_msg.mdp_b2
494 #define mdp_b1 u_ext_msg.mdp_b1
495 #define mdp_b0 u_ext_msg.mdp_b0
497 typedef struct asc_dvc_cfg {
498 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
499 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
500 ASC_SCSI_BIT_ID_TYPE disc_enable;
501 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
504 uchar isa_dma_channel;
507 ushort mcode_version;
508 uchar max_tag_qng[ASC_MAX_TID + 1];
509 uchar sdtr_period_offset[ASC_MAX_TID + 1];
510 uchar adapter_info[6];
513 #define ASC_DEF_DVC_CNTL 0xFFFF
514 #define ASC_DEF_CHIP_SCSI_ID 7
515 #define ASC_DEF_ISA_DMA_SPEED 4
516 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
517 #define ASC_INIT_STATE_END_GET_CFG 0x0002
518 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
519 #define ASC_INIT_STATE_END_SET_CFG 0x0008
520 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
521 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
522 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
523 #define ASC_INIT_STATE_END_INQUIRY 0x0080
524 #define ASC_INIT_RESET_SCSI_DONE 0x0100
525 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
526 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
527 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
528 #define ASC_MIN_TAGGED_CMD 7
529 #define ASC_MAX_SCSI_RESET_WAIT 30
530 #define ASC_OVERRUN_BSIZE 64
532 struct asc_dvc_var; /* Forward Declaration. */
534 typedef struct asc_dvc_var {
540 ASC_SCSI_BIT_ID_TYPE init_sdtr;
541 ASC_SCSI_BIT_ID_TYPE sdtr_done;
542 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
543 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
544 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
545 ASC_SCSI_BIT_ID_TYPE start_motor;
547 dma_addr_t overrun_dma;
548 uchar scsi_reset_wait;
553 uchar in_critical_cnt;
554 uchar last_q_shortage;
556 uchar cur_dvc_qng[ASC_MAX_TID + 1];
557 uchar max_dvc_qng[ASC_MAX_TID + 1];
558 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
559 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
560 const uchar *sdtr_period_tbl;
562 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
565 uchar dos_int13_table[ASC_MAX_TID + 1];
566 unsigned int max_dma_count;
567 ASC_SCSI_BIT_ID_TYPE no_scam;
568 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
569 uchar min_sdtr_index;
570 uchar max_sdtr_index;
571 struct asc_board *drv_ptr;
572 unsigned int uc_break;
575 typedef struct asc_dvc_inq_info {
576 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
579 typedef struct asc_cap_info {
584 typedef struct asc_cap_info_array {
585 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
586 } ASC_CAP_INFO_ARRAY;
588 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
589 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
590 #define ASC_CNTL_INITIATOR (ushort)0x0001
591 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
592 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
593 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
594 #define ASC_CNTL_NO_SCAM (ushort)0x0010
595 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
596 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
597 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
598 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
599 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
600 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
601 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
602 #define ASC_CNTL_BURST_MODE (ushort)0x2000
603 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
604 #define ASC_EEP_DVC_CFG_BEG_VL 2
605 #define ASC_EEP_MAX_DVC_ADDR_VL 15
606 #define ASC_EEP_DVC_CFG_BEG 32
607 #define ASC_EEP_MAX_DVC_ADDR 45
608 #define ASC_EEP_MAX_RETRY 20
611 * These macros keep the chip SCSI id and ISA DMA speed
612 * bitfields in board order. C bitfields aren't portable
613 * between big and little-endian platforms so they are
617 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
618 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
619 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
620 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
621 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
622 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
624 typedef struct asceep_config {
636 uchar id_speed; /* low order 4 bits is chip scsi id */
637 /* high order 4 bits is isa dma speed */
638 uchar dos_int13_table[ASC_MAX_TID + 1];
639 uchar adapter_info[6];
644 #define ASC_EEP_CMD_READ 0x80
645 #define ASC_EEP_CMD_WRITE 0x40
646 #define ASC_EEP_CMD_WRITE_ABLE 0x30
647 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
648 #define ASCV_MSGOUT_BEG 0x0000
649 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
650 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
651 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
652 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
653 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
654 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
655 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
656 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
657 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
658 #define ASCV_BREAK_ADDR (ushort)0x0028
659 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
660 #define ASCV_BREAK_CONTROL (ushort)0x002C
661 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
663 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
664 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
665 #define ASCV_MCODE_SIZE_W (ushort)0x0034
666 #define ASCV_STOP_CODE_B (ushort)0x0036
667 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
668 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
669 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
670 #define ASCV_HALTCODE_W (ushort)0x0040
671 #define ASCV_CHKSUM_W (ushort)0x0042
672 #define ASCV_MC_DATE_W (ushort)0x0044
673 #define ASCV_MC_VER_W (ushort)0x0046
674 #define ASCV_NEXTRDY_B (ushort)0x0048
675 #define ASCV_DONENEXT_B (ushort)0x0049
676 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
677 #define ASCV_SCSIBUSY_B (ushort)0x004B
678 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
679 #define ASCV_CURCDB_B (ushort)0x004D
680 #define ASCV_RCLUN_B (ushort)0x004E
681 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
682 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
683 #define ASCV_DISC_ENABLE_B (ushort)0x0052
684 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
685 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
686 #define ASCV_MCODE_CNTL_B (ushort)0x0056
687 #define ASCV_NULL_TARGET_B (ushort)0x0057
688 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
689 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
690 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
691 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
692 #define ASCV_HOST_FLAG_B (ushort)0x005D
693 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
694 #define ASCV_VER_SERIAL_B (ushort)0x0065
695 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
696 #define ASCV_WTM_FLAG_B (ushort)0x0068
697 #define ASCV_RISC_FLAG_B (ushort)0x006A
698 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
699 #define ASC_HOST_FLAG_IN_ISR 0x01
700 #define ASC_HOST_FLAG_ACK_INT 0x02
701 #define ASC_RISC_FLAG_GEN_INT 0x01
702 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
703 #define IOP_CTRL (0x0F)
704 #define IOP_STATUS (0x0E)
705 #define IOP_INT_ACK IOP_STATUS
706 #define IOP_REG_IFC (0x0D)
707 #define IOP_SYN_OFFSET (0x0B)
708 #define IOP_EXTRA_CONTROL (0x0D)
709 #define IOP_REG_PC (0x0C)
710 #define IOP_RAM_ADDR (0x0A)
711 #define IOP_RAM_DATA (0x08)
712 #define IOP_EEP_DATA (0x06)
713 #define IOP_EEP_CMD (0x07)
714 #define IOP_VERSION (0x03)
715 #define IOP_CONFIG_HIGH (0x04)
716 #define IOP_CONFIG_LOW (0x02)
717 #define IOP_SIG_BYTE (0x01)
718 #define IOP_SIG_WORD (0x00)
719 #define IOP_REG_DC1 (0x0E)
720 #define IOP_REG_DC0 (0x0C)
721 #define IOP_REG_SB (0x0B)
722 #define IOP_REG_DA1 (0x0A)
723 #define IOP_REG_DA0 (0x08)
724 #define IOP_REG_SC (0x09)
725 #define IOP_DMA_SPEED (0x07)
726 #define IOP_REG_FLAG (0x07)
727 #define IOP_FIFO_H (0x06)
728 #define IOP_FIFO_L (0x04)
729 #define IOP_REG_ID (0x05)
730 #define IOP_REG_QP (0x03)
731 #define IOP_REG_IH (0x02)
732 #define IOP_REG_IX (0x01)
733 #define IOP_REG_AX (0x00)
734 #define IFC_REG_LOCK (0x00)
735 #define IFC_REG_UNLOCK (0x09)
736 #define IFC_WR_EN_FILTER (0x10)
737 #define IFC_RD_NO_EEPROM (0x10)
738 #define IFC_SLEW_RATE (0x20)
739 #define IFC_ACT_NEG (0x40)
740 #define IFC_INP_FILTER (0x80)
741 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
742 #define SC_SEL (uchar)(0x80)
743 #define SC_BSY (uchar)(0x40)
744 #define SC_ACK (uchar)(0x20)
745 #define SC_REQ (uchar)(0x10)
746 #define SC_ATN (uchar)(0x08)
747 #define SC_IO (uchar)(0x04)
748 #define SC_CD (uchar)(0x02)
749 #define SC_MSG (uchar)(0x01)
750 #define SEC_SCSI_CTL (uchar)(0x80)
751 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
752 #define SEC_SLEW_RATE (uchar)(0x20)
753 #define SEC_ENABLE_FILTER (uchar)(0x10)
754 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
755 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
756 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
757 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
758 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
759 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
760 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
761 #define ASC_MAX_QNO 0xF8
762 #define ASC_DATA_SEC_BEG (ushort)0x0080
763 #define ASC_DATA_SEC_END (ushort)0x0080
764 #define ASC_CODE_SEC_BEG (ushort)0x0080
765 #define ASC_CODE_SEC_END (ushort)0x0080
766 #define ASC_QADR_BEG (0x4000)
767 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
768 #define ASC_QADR_END (ushort)0x7FFF
769 #define ASC_QLAST_ADR (ushort)0x7FC0
770 #define ASC_QBLK_SIZE 0x40
771 #define ASC_BIOS_DATA_QBEG 0xF8
772 #define ASC_MIN_ACTIVE_QNO 0x01
773 #define ASC_QLINK_END 0xFF
774 #define ASC_EEPROM_WORDS 0x10
775 #define ASC_MAX_MGS_LEN 0x10
776 #define ASC_BIOS_ADDR_DEF 0xDC00
777 #define ASC_BIOS_SIZE 0x3800
778 #define ASC_BIOS_RAM_OFF 0x3800
779 #define ASC_BIOS_RAM_SIZE 0x800
780 #define ASC_BIOS_MIN_ADDR 0xC000
781 #define ASC_BIOS_MAX_ADDR 0xEC00
782 #define ASC_BIOS_BANK_SIZE 0x0400
783 #define ASC_MCODE_START_ADDR 0x0080
784 #define ASC_CFG0_HOST_INT_ON 0x0020
785 #define ASC_CFG0_BIOS_ON 0x0040
786 #define ASC_CFG0_VERA_BURST_ON 0x0080
787 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
788 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
789 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
790 #define ASC_CFG_MSW_CLR_MASK 0x3080
791 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
792 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
793 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
794 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
795 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
796 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
797 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
798 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
799 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
800 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
801 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
802 #define CSW_HALTED (ASC_CS_TYPE)0x0010
803 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
804 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
805 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
806 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
807 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
808 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
809 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
810 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
811 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
812 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
813 #define CC_CHIP_RESET (uchar)0x80
814 #define CC_SCSI_RESET (uchar)0x40
815 #define CC_HALT (uchar)0x20
816 #define CC_SINGLE_STEP (uchar)0x10
817 #define CC_DMA_ABLE (uchar)0x08
818 #define CC_TEST (uchar)0x04
819 #define CC_BANK_ONE (uchar)0x02
820 #define CC_DIAG (uchar)0x01
821 #define ASC_1000_ID0W 0x04C1
822 #define ASC_1000_ID0W_FIX 0x00C1
823 #define ASC_1000_ID1B 0x25
824 #define ASC_EISA_REV_IOP_MASK (0x0C83)
825 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
826 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
827 #define INS_HALTINT (ushort)0x6281
828 #define INS_HALT (ushort)0x6280
829 #define INS_SINT (ushort)0x6200
830 #define INS_RFLAG_WTM (ushort)0x7380
831 #define ASC_MC_SAVE_CODE_WSIZE 0x500
832 #define ASC_MC_SAVE_DATA_WSIZE 0x40
834 typedef struct asc_mc_saved {
835 ushort data[ASC_MC_SAVE_DATA_WSIZE];
836 ushort code[ASC_MC_SAVE_CODE_WSIZE];
839 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
840 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
841 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
842 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
843 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
844 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
845 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
846 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
847 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
848 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
849 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
850 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
851 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
852 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
853 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
854 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
855 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
856 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
857 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
858 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
859 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
860 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
861 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
862 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
863 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
864 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
865 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
866 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
867 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
868 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
869 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
870 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
871 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
872 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
873 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
874 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
875 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
876 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
877 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
878 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
879 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
880 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
881 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
882 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
883 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
884 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
885 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
886 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
887 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
888 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
889 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
890 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
891 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
892 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
893 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
894 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
895 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
896 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
897 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
898 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
899 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
900 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
901 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
902 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
903 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
904 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
905 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
908 * These macros are used to convert a virtual address to a
909 * 32-bit value. This currently can be used on Linux Alpha
910 * which uses 64-bit virtual address but a 32-bit bus address.
911 * This is likely to break in the future, but doing this now
912 * will give us time to change the HW and FW to handle 64-bit
915 #define ADV_U32_TO_VADDR bus_to_virt
917 #define AdvPortAddr void __iomem * /* Virtual memory address size */
920 * Define Adv Library required memory access macros.
922 #define ADV_MEM_READB(addr) readb(addr)
923 #define ADV_MEM_READW(addr) readw(addr)
924 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
925 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
926 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
929 * Define total number of simultaneous maximum element scatter-gather
930 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
931 * maximum number of outstanding commands per wide host adapter. Each
932 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
933 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
934 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
935 * structures or 255 scatter-gather elements.
937 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
940 * Define maximum number of scatter-gather elements per request.
942 #define ADV_MAX_SG_LIST 255
943 #define NO_OF_SG_PER_BLOCK 15
945 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
946 #define ADV_EEP_DVC_CFG_END (0x15)
947 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
948 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
950 #define ADV_EEP_DELAY_MS 100
952 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
953 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
955 * For the ASC3550 Bit 13 is Termination Polarity control bit.
956 * For later ICs Bit 13 controls whether the CIS (Card Information
957 * Service Section) is loaded from EEPROM.
959 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
960 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
964 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
965 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
966 * Function 0 will specify INT B.
968 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
969 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
970 * Function 1 will specify INT A.
972 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
974 typedef struct adveep_3550_config {
975 /* Word Offset, Description */
977 ushort cfg_lsw; /* 00 power up initialization */
978 /* bit 13 set - Term Polarity Control */
979 /* bit 14 set - BIOS Enable */
980 /* bit 15 set - Big Endian Mode */
981 ushort cfg_msw; /* 01 unused */
982 ushort disc_enable; /* 02 disconnect enable */
983 ushort wdtr_able; /* 03 Wide DTR able */
984 ushort sdtr_able; /* 04 Synchronous DTR able */
985 ushort start_motor; /* 05 send start up motor */
986 ushort tagqng_able; /* 06 tag queuing able */
987 ushort bios_scan; /* 07 BIOS device control */
988 ushort scam_tolerant; /* 08 no scam */
990 uchar adapter_scsi_id; /* 09 Host Adapter ID */
991 uchar bios_boot_delay; /* power up wait */
993 uchar scsi_reset_delay; /* 10 reset delay */
994 uchar bios_id_lun; /* first boot device scsi id & lun */
995 /* high nibble is lun */
996 /* low nibble is scsi id */
998 uchar termination; /* 11 0 - automatic */
999 /* 1 - low off / high off */
1000 /* 2 - low off / high on */
1001 /* 3 - low on / high on */
1002 /* There is no low on / high off */
1004 uchar reserved1; /* reserved byte (not used) */
1006 ushort bios_ctrl; /* 12 BIOS control bits */
1007 /* bit 0 BIOS don't act as initiator. */
1008 /* bit 1 BIOS > 1 GB support */
1009 /* bit 2 BIOS > 2 Disk Support */
1010 /* bit 3 BIOS don't support removables */
1011 /* bit 4 BIOS support bootable CD */
1012 /* bit 5 BIOS scan enabled */
1013 /* bit 6 BIOS support multiple LUNs */
1014 /* bit 7 BIOS display of message */
1015 /* bit 8 SCAM disabled */
1016 /* bit 9 Reset SCSI bus during init. */
1018 /* bit 11 No verbose initialization. */
1019 /* bit 12 SCSI parity enabled */
1023 ushort ultra_able; /* 13 ULTRA speed able */
1024 ushort reserved2; /* 14 reserved */
1025 uchar max_host_qng; /* 15 maximum host queuing */
1026 uchar max_dvc_qng; /* maximum per device queuing */
1027 ushort dvc_cntl; /* 16 control bit for driver */
1028 ushort bug_fix; /* 17 control bit for bug fix */
1029 ushort serial_number_word1; /* 18 Board serial number word 1 */
1030 ushort serial_number_word2; /* 19 Board serial number word 2 */
1031 ushort serial_number_word3; /* 20 Board serial number word 3 */
1032 ushort check_sum; /* 21 EEP check sum */
1033 uchar oem_name[16]; /* 22 OEM name */
1034 ushort dvc_err_code; /* 30 last device driver error code */
1035 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1036 ushort adv_err_addr; /* 32 last uc error address */
1037 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1038 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1039 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1040 ushort num_of_err; /* 36 number of error */
1041 } ADVEEP_3550_CONFIG;
1043 typedef struct adveep_38C0800_config {
1044 /* Word Offset, Description */
1046 ushort cfg_lsw; /* 00 power up initialization */
1047 /* bit 13 set - Load CIS */
1048 /* bit 14 set - BIOS Enable */
1049 /* bit 15 set - Big Endian Mode */
1050 ushort cfg_msw; /* 01 unused */
1051 ushort disc_enable; /* 02 disconnect enable */
1052 ushort wdtr_able; /* 03 Wide DTR able */
1053 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1054 ushort start_motor; /* 05 send start up motor */
1055 ushort tagqng_able; /* 06 tag queuing able */
1056 ushort bios_scan; /* 07 BIOS device control */
1057 ushort scam_tolerant; /* 08 no scam */
1059 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1060 uchar bios_boot_delay; /* power up wait */
1062 uchar scsi_reset_delay; /* 10 reset delay */
1063 uchar bios_id_lun; /* first boot device scsi id & lun */
1064 /* high nibble is lun */
1065 /* low nibble is scsi id */
1067 uchar termination_se; /* 11 0 - automatic */
1068 /* 1 - low off / high off */
1069 /* 2 - low off / high on */
1070 /* 3 - low on / high on */
1071 /* There is no low on / high off */
1073 uchar termination_lvd; /* 11 0 - automatic */
1074 /* 1 - low off / high off */
1075 /* 2 - low off / high on */
1076 /* 3 - low on / high on */
1077 /* There is no low on / high off */
1079 ushort bios_ctrl; /* 12 BIOS control bits */
1080 /* bit 0 BIOS don't act as initiator. */
1081 /* bit 1 BIOS > 1 GB support */
1082 /* bit 2 BIOS > 2 Disk Support */
1083 /* bit 3 BIOS don't support removables */
1084 /* bit 4 BIOS support bootable CD */
1085 /* bit 5 BIOS scan enabled */
1086 /* bit 6 BIOS support multiple LUNs */
1087 /* bit 7 BIOS display of message */
1088 /* bit 8 SCAM disabled */
1089 /* bit 9 Reset SCSI bus during init. */
1091 /* bit 11 No verbose initialization. */
1092 /* bit 12 SCSI parity enabled */
1096 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1097 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1098 uchar max_host_qng; /* 15 maximum host queueing */
1099 uchar max_dvc_qng; /* maximum per device queuing */
1100 ushort dvc_cntl; /* 16 control bit for driver */
1101 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1102 ushort serial_number_word1; /* 18 Board serial number word 1 */
1103 ushort serial_number_word2; /* 19 Board serial number word 2 */
1104 ushort serial_number_word3; /* 20 Board serial number word 3 */
1105 ushort check_sum; /* 21 EEP check sum */
1106 uchar oem_name[16]; /* 22 OEM name */
1107 ushort dvc_err_code; /* 30 last device driver error code */
1108 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1109 ushort adv_err_addr; /* 32 last uc error address */
1110 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1111 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1112 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1113 ushort reserved36; /* 36 reserved */
1114 ushort reserved37; /* 37 reserved */
1115 ushort reserved38; /* 38 reserved */
1116 ushort reserved39; /* 39 reserved */
1117 ushort reserved40; /* 40 reserved */
1118 ushort reserved41; /* 41 reserved */
1119 ushort reserved42; /* 42 reserved */
1120 ushort reserved43; /* 43 reserved */
1121 ushort reserved44; /* 44 reserved */
1122 ushort reserved45; /* 45 reserved */
1123 ushort reserved46; /* 46 reserved */
1124 ushort reserved47; /* 47 reserved */
1125 ushort reserved48; /* 48 reserved */
1126 ushort reserved49; /* 49 reserved */
1127 ushort reserved50; /* 50 reserved */
1128 ushort reserved51; /* 51 reserved */
1129 ushort reserved52; /* 52 reserved */
1130 ushort reserved53; /* 53 reserved */
1131 ushort reserved54; /* 54 reserved */
1132 ushort reserved55; /* 55 reserved */
1133 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1134 ushort cisprt_msw; /* 57 CIS PTR MSW */
1135 ushort subsysvid; /* 58 SubSystem Vendor ID */
1136 ushort subsysid; /* 59 SubSystem ID */
1137 ushort reserved60; /* 60 reserved */
1138 ushort reserved61; /* 61 reserved */
1139 ushort reserved62; /* 62 reserved */
1140 ushort reserved63; /* 63 reserved */
1141 } ADVEEP_38C0800_CONFIG;
1143 typedef struct adveep_38C1600_config {
1144 /* Word Offset, Description */
1146 ushort cfg_lsw; /* 00 power up initialization */
1147 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1148 /* clear - Func. 0 INTA, Func. 1 INTB */
1149 /* bit 13 set - Load CIS */
1150 /* bit 14 set - BIOS Enable */
1151 /* bit 15 set - Big Endian Mode */
1152 ushort cfg_msw; /* 01 unused */
1153 ushort disc_enable; /* 02 disconnect enable */
1154 ushort wdtr_able; /* 03 Wide DTR able */
1155 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1156 ushort start_motor; /* 05 send start up motor */
1157 ushort tagqng_able; /* 06 tag queuing able */
1158 ushort bios_scan; /* 07 BIOS device control */
1159 ushort scam_tolerant; /* 08 no scam */
1161 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1162 uchar bios_boot_delay; /* power up wait */
1164 uchar scsi_reset_delay; /* 10 reset delay */
1165 uchar bios_id_lun; /* first boot device scsi id & lun */
1166 /* high nibble is lun */
1167 /* low nibble is scsi id */
1169 uchar termination_se; /* 11 0 - automatic */
1170 /* 1 - low off / high off */
1171 /* 2 - low off / high on */
1172 /* 3 - low on / high on */
1173 /* There is no low on / high off */
1175 uchar termination_lvd; /* 11 0 - automatic */
1176 /* 1 - low off / high off */
1177 /* 2 - low off / high on */
1178 /* 3 - low on / high on */
1179 /* There is no low on / high off */
1181 ushort bios_ctrl; /* 12 BIOS control bits */
1182 /* bit 0 BIOS don't act as initiator. */
1183 /* bit 1 BIOS > 1 GB support */
1184 /* bit 2 BIOS > 2 Disk Support */
1185 /* bit 3 BIOS don't support removables */
1186 /* bit 4 BIOS support bootable CD */
1187 /* bit 5 BIOS scan enabled */
1188 /* bit 6 BIOS support multiple LUNs */
1189 /* bit 7 BIOS display of message */
1190 /* bit 8 SCAM disabled */
1191 /* bit 9 Reset SCSI bus during init. */
1192 /* bit 10 Basic Integrity Checking disabled */
1193 /* bit 11 No verbose initialization. */
1194 /* bit 12 SCSI parity enabled */
1195 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1198 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1199 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1200 uchar max_host_qng; /* 15 maximum host queueing */
1201 uchar max_dvc_qng; /* maximum per device queuing */
1202 ushort dvc_cntl; /* 16 control bit for driver */
1203 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1204 ushort serial_number_word1; /* 18 Board serial number word 1 */
1205 ushort serial_number_word2; /* 19 Board serial number word 2 */
1206 ushort serial_number_word3; /* 20 Board serial number word 3 */
1207 ushort check_sum; /* 21 EEP check sum */
1208 uchar oem_name[16]; /* 22 OEM name */
1209 ushort dvc_err_code; /* 30 last device driver error code */
1210 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1211 ushort adv_err_addr; /* 32 last uc error address */
1212 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1213 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1214 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1215 ushort reserved36; /* 36 reserved */
1216 ushort reserved37; /* 37 reserved */
1217 ushort reserved38; /* 38 reserved */
1218 ushort reserved39; /* 39 reserved */
1219 ushort reserved40; /* 40 reserved */
1220 ushort reserved41; /* 41 reserved */
1221 ushort reserved42; /* 42 reserved */
1222 ushort reserved43; /* 43 reserved */
1223 ushort reserved44; /* 44 reserved */
1224 ushort reserved45; /* 45 reserved */
1225 ushort reserved46; /* 46 reserved */
1226 ushort reserved47; /* 47 reserved */
1227 ushort reserved48; /* 48 reserved */
1228 ushort reserved49; /* 49 reserved */
1229 ushort reserved50; /* 50 reserved */
1230 ushort reserved51; /* 51 reserved */
1231 ushort reserved52; /* 52 reserved */
1232 ushort reserved53; /* 53 reserved */
1233 ushort reserved54; /* 54 reserved */
1234 ushort reserved55; /* 55 reserved */
1235 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1236 ushort cisprt_msw; /* 57 CIS PTR MSW */
1237 ushort subsysvid; /* 58 SubSystem Vendor ID */
1238 ushort subsysid; /* 59 SubSystem ID */
1239 ushort reserved60; /* 60 reserved */
1240 ushort reserved61; /* 61 reserved */
1241 ushort reserved62; /* 62 reserved */
1242 ushort reserved63; /* 63 reserved */
1243 } ADVEEP_38C1600_CONFIG;
1248 #define ASC_EEP_CMD_DONE 0x0200
1251 #define BIOS_CTRL_BIOS 0x0001
1252 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
1253 #define BIOS_CTRL_GT_2_DISK 0x0004
1254 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1255 #define BIOS_CTRL_BOOTABLE_CD 0x0010
1256 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
1257 #define BIOS_CTRL_DISPLAY_MSG 0x0080
1258 #define BIOS_CTRL_NO_SCAM 0x0100
1259 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1260 #define BIOS_CTRL_INIT_VERBOSE 0x0800
1261 #define BIOS_CTRL_SCSI_PARITY 0x1000
1262 #define BIOS_CTRL_AIPP_DIS 0x2000
1264 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1266 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1269 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1270 * a special 16K Adv Library and Microcode version. After the issue is
1271 * resolved, should restore 32K support.
1273 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1275 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1278 * Byte I/O register address from base of 'iop_base'.
1280 #define IOPB_INTR_STATUS_REG 0x00
1281 #define IOPB_CHIP_ID_1 0x01
1282 #define IOPB_INTR_ENABLES 0x02
1283 #define IOPB_CHIP_TYPE_REV 0x03
1284 #define IOPB_RES_ADDR_4 0x04
1285 #define IOPB_RES_ADDR_5 0x05
1286 #define IOPB_RAM_DATA 0x06
1287 #define IOPB_RES_ADDR_7 0x07
1288 #define IOPB_FLAG_REG 0x08
1289 #define IOPB_RES_ADDR_9 0x09
1290 #define IOPB_RISC_CSR 0x0A
1291 #define IOPB_RES_ADDR_B 0x0B
1292 #define IOPB_RES_ADDR_C 0x0C
1293 #define IOPB_RES_ADDR_D 0x0D
1294 #define IOPB_SOFT_OVER_WR 0x0E
1295 #define IOPB_RES_ADDR_F 0x0F
1296 #define IOPB_MEM_CFG 0x10
1297 #define IOPB_RES_ADDR_11 0x11
1298 #define IOPB_GPIO_DATA 0x12
1299 #define IOPB_RES_ADDR_13 0x13
1300 #define IOPB_FLASH_PAGE 0x14
1301 #define IOPB_RES_ADDR_15 0x15
1302 #define IOPB_GPIO_CNTL 0x16
1303 #define IOPB_RES_ADDR_17 0x17
1304 #define IOPB_FLASH_DATA 0x18
1305 #define IOPB_RES_ADDR_19 0x19
1306 #define IOPB_RES_ADDR_1A 0x1A
1307 #define IOPB_RES_ADDR_1B 0x1B
1308 #define IOPB_RES_ADDR_1C 0x1C
1309 #define IOPB_RES_ADDR_1D 0x1D
1310 #define IOPB_RES_ADDR_1E 0x1E
1311 #define IOPB_RES_ADDR_1F 0x1F
1312 #define IOPB_DMA_CFG0 0x20
1313 #define IOPB_DMA_CFG1 0x21
1314 #define IOPB_TICKLE 0x22
1315 #define IOPB_DMA_REG_WR 0x23
1316 #define IOPB_SDMA_STATUS 0x24
1317 #define IOPB_SCSI_BYTE_CNT 0x25
1318 #define IOPB_HOST_BYTE_CNT 0x26
1319 #define IOPB_BYTE_LEFT_TO_XFER 0x27
1320 #define IOPB_BYTE_TO_XFER_0 0x28
1321 #define IOPB_BYTE_TO_XFER_1 0x29
1322 #define IOPB_BYTE_TO_XFER_2 0x2A
1323 #define IOPB_BYTE_TO_XFER_3 0x2B
1324 #define IOPB_ACC_GRP 0x2C
1325 #define IOPB_RES_ADDR_2D 0x2D
1326 #define IOPB_DEV_ID 0x2E
1327 #define IOPB_RES_ADDR_2F 0x2F
1328 #define IOPB_SCSI_DATA 0x30
1329 #define IOPB_RES_ADDR_31 0x31
1330 #define IOPB_RES_ADDR_32 0x32
1331 #define IOPB_SCSI_DATA_HSHK 0x33
1332 #define IOPB_SCSI_CTRL 0x34
1333 #define IOPB_RES_ADDR_35 0x35
1334 #define IOPB_RES_ADDR_36 0x36
1335 #define IOPB_RES_ADDR_37 0x37
1336 #define IOPB_RAM_BIST 0x38
1337 #define IOPB_PLL_TEST 0x39
1338 #define IOPB_PCI_INT_CFG 0x3A
1339 #define IOPB_RES_ADDR_3B 0x3B
1340 #define IOPB_RFIFO_CNT 0x3C
1341 #define IOPB_RES_ADDR_3D 0x3D
1342 #define IOPB_RES_ADDR_3E 0x3E
1343 #define IOPB_RES_ADDR_3F 0x3F
1346 * Word I/O register address from base of 'iop_base'.
1348 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
1349 #define IOPW_CTRL_REG 0x02 /* CC */
1350 #define IOPW_RAM_ADDR 0x04 /* LA */
1351 #define IOPW_RAM_DATA 0x06 /* LD */
1352 #define IOPW_RES_ADDR_08 0x08
1353 #define IOPW_RISC_CSR 0x0A /* CSR */
1354 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1355 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1356 #define IOPW_RES_ADDR_10 0x10
1357 #define IOPW_SEL_MASK 0x12 /* SM */
1358 #define IOPW_RES_ADDR_14 0x14
1359 #define IOPW_FLASH_ADDR 0x16 /* FA */
1360 #define IOPW_RES_ADDR_18 0x18
1361 #define IOPW_EE_CMD 0x1A /* EC */
1362 #define IOPW_EE_DATA 0x1C /* ED */
1363 #define IOPW_SFIFO_CNT 0x1E /* SFC */
1364 #define IOPW_RES_ADDR_20 0x20
1365 #define IOPW_Q_BASE 0x22 /* QB */
1366 #define IOPW_QP 0x24 /* QP */
1367 #define IOPW_IX 0x26 /* IX */
1368 #define IOPW_SP 0x28 /* SP */
1369 #define IOPW_PC 0x2A /* PC */
1370 #define IOPW_RES_ADDR_2C 0x2C
1371 #define IOPW_RES_ADDR_2E 0x2E
1372 #define IOPW_SCSI_DATA 0x30 /* SD */
1373 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1374 #define IOPW_SCSI_CTRL 0x34 /* SC */
1375 #define IOPW_HSHK_CFG 0x36 /* HCFG */
1376 #define IOPW_SXFR_STATUS 0x36 /* SXS */
1377 #define IOPW_SXFR_CNTL 0x38 /* SXL */
1378 #define IOPW_SXFR_CNTH 0x3A /* SXH */
1379 #define IOPW_RES_ADDR_3C 0x3C
1380 #define IOPW_RFIFO_DATA 0x3E /* RFD */
1383 * Doubleword I/O register address from base of 'iop_base'.
1385 #define IOPDW_RES_ADDR_0 0x00
1386 #define IOPDW_RAM_DATA 0x04
1387 #define IOPDW_RES_ADDR_8 0x08
1388 #define IOPDW_RES_ADDR_C 0x0C
1389 #define IOPDW_RES_ADDR_10 0x10
1390 #define IOPDW_COMMA 0x14
1391 #define IOPDW_COMMB 0x18
1392 #define IOPDW_RES_ADDR_1C 0x1C
1393 #define IOPDW_SDMA_ADDR0 0x20
1394 #define IOPDW_SDMA_ADDR1 0x24
1395 #define IOPDW_SDMA_COUNT 0x28
1396 #define IOPDW_SDMA_ERROR 0x2C
1397 #define IOPDW_RDMA_ADDR0 0x30
1398 #define IOPDW_RDMA_ADDR1 0x34
1399 #define IOPDW_RDMA_COUNT 0x38
1400 #define IOPDW_RDMA_ERROR 0x3C
1402 #define ADV_CHIP_ID_BYTE 0x25
1403 #define ADV_CHIP_ID_WORD 0x04C1
1405 #define ADV_INTR_ENABLE_HOST_INTR 0x01
1406 #define ADV_INTR_ENABLE_SEL_INTR 0x02
1407 #define ADV_INTR_ENABLE_DPR_INTR 0x04
1408 #define ADV_INTR_ENABLE_RTA_INTR 0x08
1409 #define ADV_INTR_ENABLE_RMA_INTR 0x10
1410 #define ADV_INTR_ENABLE_RST_INTR 0x20
1411 #define ADV_INTR_ENABLE_DPE_INTR 0x40
1412 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1414 #define ADV_INTR_STATUS_INTRA 0x01
1415 #define ADV_INTR_STATUS_INTRB 0x02
1416 #define ADV_INTR_STATUS_INTRC 0x04
1418 #define ADV_RISC_CSR_STOP (0x0000)
1419 #define ADV_RISC_TEST_COND (0x2000)
1420 #define ADV_RISC_CSR_RUN (0x4000)
1421 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1423 #define ADV_CTRL_REG_HOST_INTR 0x0100
1424 #define ADV_CTRL_REG_SEL_INTR 0x0200
1425 #define ADV_CTRL_REG_DPR_INTR 0x0400
1426 #define ADV_CTRL_REG_RTA_INTR 0x0800
1427 #define ADV_CTRL_REG_RMA_INTR 0x1000
1428 #define ADV_CTRL_REG_RES_BIT14 0x2000
1429 #define ADV_CTRL_REG_DPE_INTR 0x4000
1430 #define ADV_CTRL_REG_POWER_DONE 0x8000
1431 #define ADV_CTRL_REG_ANY_INTR 0xFF00
1433 #define ADV_CTRL_REG_CMD_RESET 0x00C6
1434 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1435 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1436 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1437 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1439 #define ADV_TICKLE_NOP 0x00
1440 #define ADV_TICKLE_A 0x01
1441 #define ADV_TICKLE_B 0x02
1442 #define ADV_TICKLE_C 0x03
1444 #define AdvIsIntPending(port) \
1445 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1448 * SCSI_CFG0 Register bit definitions
1450 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1451 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1452 #define EVEN_PARITY 0x1000 /* Select Even Parity */
1453 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1454 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1455 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1456 #define SCAM_EN 0x0080 /* Enable SCAM selection */
1457 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1458 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1459 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1460 #define OUR_ID 0x000F /* SCSI ID */
1463 * SCSI_CFG1 Register bit definitions
1465 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1466 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1467 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1468 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
1469 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1470 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1471 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1472 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1473 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1474 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1475 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1476 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1477 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1478 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1479 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1482 * Addendum for ASC-38C0800 Chip
1484 * The ASC-38C1600 Chip uses the same definitions except that the
1485 * bus mode override bits [12:10] have been moved to byte register
1486 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1487 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1488 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1489 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1490 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1492 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1493 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1494 #define HVD 0x1000 /* HVD Device Detect */
1495 #define LVD 0x0800 /* LVD Device Detect */
1496 #define SE 0x0400 /* SE Device Detect */
1497 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
1498 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1499 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1500 #define TERM_SE 0x0030 /* SE Termination Bits */
1501 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1502 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1503 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1504 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1505 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1506 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1507 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1508 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1510 #define CABLE_ILLEGAL_A 0x7
1511 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1513 #define CABLE_ILLEGAL_B 0xB
1514 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1517 * MEM_CFG Register bit definitions
1519 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1520 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1521 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1522 #define RAM_SZ_2KB 0x00 /* 2 KB */
1523 #define RAM_SZ_4KB 0x04 /* 4 KB */
1524 #define RAM_SZ_8KB 0x08 /* 8 KB */
1525 #define RAM_SZ_16KB 0x0C /* 16 KB */
1526 #define RAM_SZ_32KB 0x10 /* 32 KB */
1527 #define RAM_SZ_64KB 0x14 /* 64 KB */
1530 * DMA_CFG0 Register bit definitions
1532 * This register is only accessible to the host.
1534 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1535 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1536 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
1537 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
1538 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
1539 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
1540 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1541 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
1542 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
1543 #define START_CTL 0x0C /* DMA start conditions */
1544 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
1545 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1546 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1547 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1548 #define READ_CMD 0x03 /* Memory Read Method */
1549 #define READ_CMD_MR 0x00 /* Memory Read */
1550 #define READ_CMD_MRL 0x02 /* Memory Read Long */
1551 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1554 * ASC-38C0800 RAM BIST Register bit definitions
1556 #define RAM_TEST_MODE 0x80
1557 #define PRE_TEST_MODE 0x40
1558 #define NORMAL_MODE 0x00
1559 #define RAM_TEST_DONE 0x10
1560 #define RAM_TEST_STATUS 0x0F
1561 #define RAM_TEST_HOST_ERROR 0x08
1562 #define RAM_TEST_INTRAM_ERROR 0x04
1563 #define RAM_TEST_RISC_ERROR 0x02
1564 #define RAM_TEST_SCSI_ERROR 0x01
1565 #define RAM_TEST_SUCCESS 0x00
1566 #define PRE_TEST_VALUE 0x05
1567 #define NORMAL_VALUE 0x00
1570 * ASC38C1600 Definitions
1572 * IOPB_PCI_INT_CFG Bit Field Definitions
1575 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1578 * Bit 1 can be set to change the interrupt for the Function to operate in
1579 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1580 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1581 * mode, otherwise the operating mode is undefined.
1583 #define TOTEMPOLE 0x02
1586 * Bit 0 can be used to change the Int Pin for the Function. The value is
1587 * 0 by default for both Functions with Function 0 using INT A and Function
1588 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1591 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1592 * value specified in the PCI Configuration Space.
1597 * Adv Library Status Definitions
1601 #define ADV_SUCCESS 1
1603 #define ADV_ERROR (-1)
1606 * ADV_DVC_VAR 'warn_code' values
1608 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1609 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1610 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
1611 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1613 #define ADV_MAX_TID 15 /* max. target identifier */
1614 #define ADV_MAX_LUN 7 /* max. logical unit number */
1617 * Fixed locations of microcode operating variables.
1619 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1620 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1621 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1622 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1623 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1624 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1625 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1626 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1627 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1628 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1629 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1630 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1631 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1632 #define ASC_MC_CHIP_TYPE 0x009A
1633 #define ASC_MC_INTRB_CODE 0x009B
1634 #define ASC_MC_WDTR_ABLE 0x009C
1635 #define ASC_MC_SDTR_ABLE 0x009E
1636 #define ASC_MC_TAGQNG_ABLE 0x00A0
1637 #define ASC_MC_DISC_ENABLE 0x00A2
1638 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
1639 #define ASC_MC_IDLE_CMD 0x00A6
1640 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1641 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1642 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1643 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1644 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1645 #define ASC_MC_SDTR_DONE 0x00B6
1646 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1647 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1648 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
1649 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1650 #define ASC_MC_WDTR_DONE 0x0124
1651 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1652 #define ASC_MC_ICQ 0x0160
1653 #define ASC_MC_IRQ 0x0164
1654 #define ASC_MC_PPR_ABLE 0x017A
1657 * BIOS LRAM variable absolute offsets.
1659 #define BIOS_CODESEG 0x54
1660 #define BIOS_CODELEN 0x56
1661 #define BIOS_SIGNATURE 0x58
1662 #define BIOS_VERSION 0x5A
1665 * Microcode Control Flags
1667 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1668 * and handled by the microcode.
1670 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1671 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1674 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1676 #define HSHK_CFG_WIDE_XFR 0x8000
1677 #define HSHK_CFG_RATE 0x0F00
1678 #define HSHK_CFG_OFFSET 0x001F
1680 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1681 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1682 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1683 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1685 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1686 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1687 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1688 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1689 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1691 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1692 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1693 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1694 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1695 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1697 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1698 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1700 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1701 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1704 * All fields here are accessed by the board microcode and need to be
1707 typedef struct adv_carr_t {
1708 __le32 carr_va; /* Carrier Virtual Address */
1709 __le32 carr_pa; /* Carrier Physical Address */
1710 __le32 areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1712 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1714 * next_vpa [3:1] Reserved Bits
1715 * next_vpa [0] Done Flag set in Response Queue.
1721 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1723 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1725 #define ASC_RQ_DONE 0x00000001
1726 #define ASC_RQ_GOOD 0x00000002
1727 #define ASC_CQ_STOPPER 0x00000000
1729 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1732 * Each carrier is 64 bytes, and we need three additional
1733 * carrier for icq, irq, and the termination carrier.
1735 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1737 #define ADV_CARRIER_BUFSIZE \
1738 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1741 * ASC_SCSI_REQ_Q 'a_flag' definitions
1743 * The Adv Library should limit use to the lower nibble (4 bits) of
1744 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1746 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1747 #define ADV_SCSIQ_DONE 0x02 /* request done */
1748 #define ADV_DONT_RETRY 0x08 /* don't do retry */
1750 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1751 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1752 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1755 * Adapter temporary configuration structure
1757 * This structure can be discarded after initialization. Don't add
1758 * fields here needed after initialization.
1760 * Field naming convention:
1762 * *_enable indicates the field enables or disables a feature. The
1763 * value of the field is never reset.
1765 typedef struct adv_dvc_cfg {
1766 ushort disc_enable; /* enable disconnection */
1767 uchar chip_version; /* chip version */
1768 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1769 ushort control_flag; /* Microcode Control Flag */
1770 ushort mcode_date; /* Microcode date */
1771 ushort mcode_version; /* Microcode version */
1772 ushort serial1; /* EEPROM serial number word 1 */
1773 ushort serial2; /* EEPROM serial number word 2 */
1774 ushort serial3; /* EEPROM serial number word 3 */
1778 struct adv_scsi_req_q;
1780 typedef struct adv_sg_block {
1784 uchar sg_cnt; /* Valid entries in block. */
1785 __le32 sg_ptr; /* Pointer to next sg block. */
1787 __le32 sg_addr; /* SG element address. */
1788 __le32 sg_count; /* SG element count. */
1789 } sg_list[NO_OF_SG_PER_BLOCK];
1793 * ADV_SCSI_REQ_Q - microcode request structure
1795 * All fields in this structure up to byte 60 are used by the microcode.
1796 * The microcode makes assumptions about the size and ordering of fields
1797 * in this structure. Do not change the structure definition here without
1798 * coordinating the change with the microcode.
1800 * All fields accessed by microcode must be maintained in little_endian
1803 typedef struct adv_scsi_req_q {
1804 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1806 uchar target_id; /* Device target identifier. */
1807 uchar target_lun; /* Device target logical unit number. */
1808 __le32 data_addr; /* Data buffer physical address. */
1809 __le32 data_cnt; /* Data count. Ucode sets to residual. */
1814 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1816 uchar done_status; /* Completion status. */
1817 uchar scsi_status; /* SCSI status byte. */
1818 uchar host_status; /* Ucode host status. */
1819 uchar sg_working_ix;
1820 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1821 __le32 sg_real_addr; /* SG list physical address. */
1823 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1827 * End of microcode structure - 60 bytes. The rest of the structure
1828 * is used by the Adv Library and ignored by the microcode.
1832 uchar pad[3]; /* Pad out to a word boundary. */
1833 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1837 * The following two structures are used to process Wide Board requests.
1839 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1840 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1841 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1842 * to the Mid-Level SCSI request structure.
1844 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1845 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1846 * up to 255 scatter-gather elements may be used per request or
1849 * Both structures must be 32 byte aligned.
1851 typedef struct adv_sgblk {
1852 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1853 dma_addr_t sg_addr; /* Physical address */
1854 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1857 typedef struct adv_req {
1858 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1859 uchar align[24]; /* Request structure padding. */
1860 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1861 dma_addr_t req_addr;
1862 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1863 } adv_req_t __aligned(32);
1866 * Adapter operation variable structure.
1868 * One structure is required per host adapter.
1870 * Field naming convention:
1872 * *_able indicates both whether a feature should be enabled or disabled
1873 * and whether a device isi capable of the feature. At initialization
1874 * this field may be set, but later if a device is found to be incapable
1875 * of the feature, the field is cleared.
1877 typedef struct adv_dvc_var {
1878 AdvPortAddr iop_base; /* I/O port address */
1879 ushort err_code; /* fatal error code */
1880 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1881 ushort wdtr_able; /* try WDTR for a device */
1882 ushort sdtr_able; /* try SDTR for a device */
1883 ushort ultra_able; /* try SDTR Ultra speed for a device */
1884 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1885 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1886 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1887 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1888 ushort tagqng_able; /* try tagged queuing with a device */
1889 ushort ppr_able; /* PPR message capable per TID bitmask. */
1890 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1891 ushort start_motor; /* start motor command allowed */
1892 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1893 uchar chip_no; /* should be assigned by caller */
1894 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1895 ushort no_scam; /* scam_tolerant of EEPROM */
1896 struct asc_board *drv_ptr; /* driver pointer to private structure */
1897 uchar chip_scsi_id; /* chip SCSI target ID */
1899 uchar bist_err_code;
1900 ADV_CARR_T *carrier;
1901 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1902 dma_addr_t carrier_addr;
1903 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1904 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1905 ushort carr_pending_cnt; /* Count of pending carriers. */
1907 * Note: The following fields will not be used after initialization. The
1908 * driver may discard the buffer after initialization is done.
1910 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1914 * Microcode idle loop commands
1916 #define IDLE_CMD_COMPLETED 0
1917 #define IDLE_CMD_STOP_CHIP 0x0001
1918 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1919 #define IDLE_CMD_SEND_INT 0x0004
1920 #define IDLE_CMD_ABORT 0x0008
1921 #define IDLE_CMD_DEVICE_RESET 0x0010
1922 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1923 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1924 #define IDLE_CMD_SCSIREQ 0x0080
1926 #define IDLE_CMD_STATUS_SUCCESS 0x0001
1927 #define IDLE_CMD_STATUS_FAILURE 0x0002
1930 * AdvSendIdleCmd() flag definitions.
1932 #define ADV_NOWAIT 0x01
1935 * Wait loop time out values.
1937 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1938 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
1939 #define SCSI_MAX_RETRY 10 /* retry count */
1941 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1942 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1943 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1944 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1946 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1948 /* Read byte from a register. */
1949 #define AdvReadByteRegister(iop_base, reg_off) \
1950 (ADV_MEM_READB((iop_base) + (reg_off)))
1952 /* Write byte to a register. */
1953 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1954 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1956 /* Read word (2 bytes) from a register. */
1957 #define AdvReadWordRegister(iop_base, reg_off) \
1958 (ADV_MEM_READW((iop_base) + (reg_off)))
1960 /* Write word (2 bytes) to a register. */
1961 #define AdvWriteWordRegister(iop_base, reg_off, word) \
1962 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1964 /* Write dword (4 bytes) to a register. */
1965 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1966 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1968 /* Read byte from LRAM. */
1969 #define AdvReadByteLram(iop_base, addr, byte) \
1971 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1972 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1975 /* Write byte to LRAM. */
1976 #define AdvWriteByteLram(iop_base, addr, byte) \
1977 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1978 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1980 /* Read word (2 bytes) from LRAM. */
1981 #define AdvReadWordLram(iop_base, addr, word) \
1983 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1984 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1987 /* Write word (2 bytes) to LRAM. */
1988 #define AdvWriteWordLram(iop_base, addr, word) \
1989 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1990 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1992 /* Write little-endian double word (4 bytes) to LRAM */
1993 /* Because of unspecified C language ordering don't use auto-increment. */
1994 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1995 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1996 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1997 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1998 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
1999 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2000 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2002 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2003 #define AdvReadWordAutoIncLram(iop_base) \
2004 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2006 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2007 #define AdvWriteWordAutoIncLram(iop_base, word) \
2008 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2011 * Define macro to check for Condor signature.
2013 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2014 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2016 #define AdvFindSignature(iop_base) \
2017 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2018 ADV_CHIP_ID_BYTE) && \
2019 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2020 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2023 * Define macro to Return the version number of the chip at 'iop_base'.
2025 * The second parameter 'bus_type' is currently unused.
2027 #define AdvGetChipVersion(iop_base, bus_type) \
2028 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2031 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
2032 * match the ASC_SCSI_REQ_Q 'srb_tag' field.
2034 * If the request has not yet been sent to the device it will simply be
2035 * aborted from RISC memory. If the request is disconnected it will be
2036 * aborted on reselection by sending an Abort Message to the target ID.
2039 * ADV_TRUE(1) - Queue was successfully aborted.
2040 * ADV_FALSE(0) - Queue was not found on the active queue list.
2042 #define AdvAbortQueue(asc_dvc, srb_tag) \
2043 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2044 (ADV_DCNT) (srb_tag))
2047 * Send a Bus Device Reset Message to the specified target ID.
2049 * All outstanding commands will be purged if sending the
2050 * Bus Device Reset Message is successful.
2053 * ADV_TRUE(1) - All requests on the target are purged.
2054 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2057 #define AdvResetDevice(asc_dvc, target_id) \
2058 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2059 (ADV_DCNT) (target_id))
2062 * SCSI Wide Type definition.
2064 #define ADV_SCSI_BIT_ID_TYPE ushort
2067 * AdvInitScsiTarget() 'cntl_flag' options.
2069 #define ADV_SCAN_LUN 0x01
2070 #define ADV_CAPINFO_NOLUN 0x02
2073 * Convert target id to target id bit mask.
2075 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2078 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2081 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
2082 #define QD_NO_ERROR 0x01
2083 #define QD_ABORTED_BY_HOST 0x02
2084 #define QD_WITH_ERROR 0x04
2086 #define QHSTA_NO_ERROR 0x00
2087 #define QHSTA_M_SEL_TIMEOUT 0x11
2088 #define QHSTA_M_DATA_OVER_RUN 0x12
2089 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2090 #define QHSTA_M_QUEUE_ABORTED 0x15
2091 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2092 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2093 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2094 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2095 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2096 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2097 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
2098 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2099 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2100 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2101 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2102 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2103 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2104 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2105 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2106 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
2107 #define QHSTA_M_WTM_TIMEOUT 0x41
2108 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2109 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2110 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2111 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2112 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2113 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
2115 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2116 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2119 * Total contiguous memory needed for driver SG blocks.
2121 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2122 * number of scatter-gather elements the driver supports in a
2126 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2127 (sizeof(ADV_SG_BLOCK) * \
2128 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2130 /* struct asc_board flags */
2131 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
2133 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2135 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
2137 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
2139 /* Asc Library return codes */
2142 #define ASC_NOERROR 1
2144 #define ASC_ERROR (-1)
2146 /* struct scsi_cmnd function return codes */
2147 #define STATUS_BYTE(byte) (byte)
2148 #define MSG_BYTE(byte) ((byte) << 8)
2149 #define HOST_BYTE(byte) ((byte) << 16)
2150 #define DRIVER_BYTE(byte) ((byte) << 24)
2152 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2153 #ifndef ADVANSYS_STATS
2154 #define ASC_STATS_ADD(shost, counter, count)
2155 #else /* ADVANSYS_STATS */
2156 #define ASC_STATS_ADD(shost, counter, count) \
2157 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2158 #endif /* ADVANSYS_STATS */
2160 /* If the result wraps when calculating tenths, return 0. */
2161 #define ASC_TENTHS(num, den) \
2162 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2163 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2166 * Display a message to the console.
2168 #define ASC_PRINT(s) \
2170 printk("advansys: "); \
2174 #define ASC_PRINT1(s, a1) \
2176 printk("advansys: "); \
2177 printk((s), (a1)); \
2180 #define ASC_PRINT2(s, a1, a2) \
2182 printk("advansys: "); \
2183 printk((s), (a1), (a2)); \
2186 #define ASC_PRINT3(s, a1, a2, a3) \
2188 printk("advansys: "); \
2189 printk((s), (a1), (a2), (a3)); \
2192 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2194 printk("advansys: "); \
2195 printk((s), (a1), (a2), (a3), (a4)); \
2198 #ifndef ADVANSYS_DEBUG
2200 #define ASC_DBG(lvl, s...)
2201 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2202 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2203 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2204 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2205 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2206 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2207 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2208 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2209 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2211 #else /* ADVANSYS_DEBUG */
2214 * Debugging Message Levels:
2216 * 1: High-Level Tracing
2217 * 2-N: Verbose Tracing
2220 #define ASC_DBG(lvl, format, arg...) { \
2221 if (asc_dbglvl >= (lvl)) \
2222 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
2223 __func__ , ## arg); \
2226 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2228 if (asc_dbglvl >= (lvl)) { \
2229 asc_prt_scsi_host(s); \
2233 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2235 if (asc_dbglvl >= (lvl)) { \
2236 asc_prt_asc_scsi_q(scsiqp); \
2240 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2242 if (asc_dbglvl >= (lvl)) { \
2243 asc_prt_asc_qdone_info(qdone); \
2247 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2249 if (asc_dbglvl >= (lvl)) { \
2250 asc_prt_adv_scsi_req_q(scsiqp); \
2254 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2256 if (asc_dbglvl >= (lvl)) { \
2257 asc_prt_hex((name), (start), (length)); \
2261 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2262 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2264 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2265 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2267 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2268 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2269 #endif /* ADVANSYS_DEBUG */
2271 #ifdef ADVANSYS_STATS
2273 /* Per board statistics structure */
2275 /* Driver Entrypoint Statistics */
2276 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2277 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2278 unsigned int biosparam; /* # calls to advansys_biosparam() */
2279 unsigned int interrupt; /* # advansys_interrupt() calls */
2280 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2281 unsigned int done; /* # calls to request's scsi_done function */
2282 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2283 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2284 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2285 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2286 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2287 unsigned int exe_busy; /* # ASC_BUSY returns. */
2288 unsigned int exe_error; /* # ASC_ERROR returns. */
2289 unsigned int exe_unknown; /* # unknown returns. */
2290 /* Data Transfer Statistics */
2291 unsigned int xfer_cnt; /* # I/O requests received */
2292 unsigned int xfer_elem; /* # scatter-gather elements */
2293 unsigned int xfer_sect; /* # 512-byte blocks */
2295 #endif /* ADVANSYS_STATS */
2298 * Structure allocated for each board.
2300 * This structure is allocated by scsi_host_alloc() at the end
2301 * of the 'Scsi_Host' structure starting at the 'hostdata'
2302 * field. It is guaranteed to be allocated from DMA-able memory.
2306 struct Scsi_Host *shost;
2307 uint flags; /* Board flags */
2310 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2311 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2314 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2315 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2317 ushort asc_n_io_port; /* Number I/O ports. */
2318 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
2319 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2320 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2321 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2323 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2324 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2325 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2326 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2328 /* /proc/scsi/advansys/[0...] */
2329 #ifdef ADVANSYS_STATS
2330 struct asc_stats asc_stats; /* Board statistics */
2331 #endif /* ADVANSYS_STATS */
2333 * The following fields are used only for Narrow Boards.
2335 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2337 * The following fields are used only for Wide Boards.
2339 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2340 ushort ioport; /* I/O Port address. */
2341 adv_req_t *adv_reqp; /* Request structures. */
2342 dma_addr_t adv_reqp_addr;
2343 size_t adv_reqp_size;
2344 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
2345 ushort bios_signature; /* BIOS Signature. */
2346 ushort bios_version; /* BIOS Version. */
2347 ushort bios_codeseg; /* BIOS Code Segment. */
2348 ushort bios_codelen; /* BIOS Code Segment Length. */
2351 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2352 dvc_var.asc_dvc_var)
2353 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2354 dvc_var.adv_dvc_var)
2355 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2357 #ifdef ADVANSYS_DEBUG
2358 static int asc_dbglvl = 3;
2361 * asc_prt_asc_dvc_var()
2363 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2365 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2367 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2368 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2370 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2371 (unsigned)h->init_sdtr);
2373 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2374 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2375 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2376 (unsigned)h->chip_no);
2378 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2379 "%u,\n", (unsigned)h->queue_full_or_busy,
2380 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2382 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2383 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2384 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2385 (unsigned)h->in_critical_cnt);
2387 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2388 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2389 (unsigned)h->init_state, (unsigned)h->no_scam,
2390 (unsigned)h->pci_fix_asyn_xfer);
2392 printk(" cfg 0x%lx\n", (ulong)h->cfg);
2396 * asc_prt_asc_dvc_cfg()
2398 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2400 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2402 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2403 h->can_tagged_qng, h->cmd_qng_enabled);
2404 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2405 h->disc_enable, h->sdtr_enable);
2407 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2408 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2409 h->isa_dma_channel, h->chip_version);
2411 printk(" mcode_date 0x%x, mcode_version %d\n",
2412 h->mcode_date, h->mcode_version);
2416 * asc_prt_adv_dvc_var()
2418 * Display an ADV_DVC_VAR structure.
2420 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2422 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2424 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2425 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2427 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2428 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2430 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2431 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2433 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2434 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2437 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2439 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2440 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2442 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2443 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2447 * asc_prt_adv_dvc_cfg()
2449 * Display an ADV_DVC_CFG structure.
2451 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2453 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2455 printk(" disc_enable 0x%x, termination 0x%x\n",
2456 h->disc_enable, h->termination);
2458 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2459 h->chip_version, h->mcode_date);
2461 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2462 h->mcode_version, h->control_flag);
2466 * asc_prt_scsi_host()
2468 static void asc_prt_scsi_host(struct Scsi_Host *s)
2470 struct asc_board *boardp = shost_priv(s);
2472 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2473 printk(" host_busy %u, host_no %d,\n",
2474 atomic_read(&s->host_busy), s->host_no);
2476 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2477 (ulong)s->base, (ulong)s->io_port, boardp->irq);
2479 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2480 s->dma_channel, s->this_id, s->can_queue);
2482 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2483 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2485 if (ASC_NARROW_BOARD(boardp)) {
2486 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2487 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2489 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2490 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2497 * Print hexadecimal output in 4 byte groupings 32 bytes
2498 * or 8 double-words per line.
2500 static void asc_prt_hex(char *f, uchar *s, int l)
2507 printk("%s: (%d bytes)\n", f, l);
2509 for (i = 0; i < l; i += 32) {
2511 /* Display a maximum of 8 double-words per line. */
2512 if ((k = (l - i) / 4) >= 8) {
2519 for (j = 0; j < k; j++) {
2520 printk(" %2.2X%2.2X%2.2X%2.2X",
2521 (unsigned)s[i + (j * 4)],
2522 (unsigned)s[i + (j * 4) + 1],
2523 (unsigned)s[i + (j * 4) + 2],
2524 (unsigned)s[i + (j * 4) + 3]);
2532 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2535 printk(" %2.2X%2.2X",
2536 (unsigned)s[i + (j * 4)],
2537 (unsigned)s[i + (j * 4) + 1]);
2540 printk(" %2.2X%2.2X%2.2X",
2541 (unsigned)s[i + (j * 4) + 1],
2542 (unsigned)s[i + (j * 4) + 2],
2543 (unsigned)s[i + (j * 4) + 3]);
2552 * asc_prt_asc_scsi_q()
2554 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2559 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2562 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2563 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2567 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2568 (ulong)le32_to_cpu(q->q1.data_addr),
2569 (ulong)le32_to_cpu(q->q1.data_cnt),
2570 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2572 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2573 (ulong)q->cdbptr, q->q2.cdb_len,
2574 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2578 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2579 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2581 for (i = 0; i < sgp->entry_cnt; i++) {
2582 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2583 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2584 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2591 * asc_prt_asc_qdone_info()
2593 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2595 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2596 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2597 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2600 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2601 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2605 * asc_prt_adv_sgblock()
2607 * Display an ADV_SG_BLOCK structure.
2609 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2613 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2614 (ulong)b, sgblockno);
2615 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2616 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2617 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2619 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2620 for (i = 0; i < b->sg_cnt; i++) {
2621 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2622 i, (ulong)b->sg_list[i].sg_addr,
2623 (ulong)b->sg_list[i].sg_count);
2628 * asc_prt_adv_scsi_req_q()
2630 * Display an ADV_SCSI_REQ_Q structure.
2632 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2635 struct adv_sg_block *sg_ptr;
2636 adv_sgblk_t *sgblkp;
2638 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2640 printk(" target_id %u, target_lun %u, srb_tag 0x%x, a_flag 0x%x\n",
2641 q->target_id, q->target_lun, q->srb_tag, q->a_flag);
2643 printk(" cntl 0x%x, data_addr 0x%lx\n",
2644 q->cntl, (ulong)le32_to_cpu(q->data_addr));
2646 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2647 (ulong)le32_to_cpu(q->data_cnt),
2648 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2651 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2652 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2654 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2655 q->sg_working_ix, q->target_cmd);
2657 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2658 (ulong)le32_to_cpu(q->scsiq_rptr),
2659 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2661 /* Display the request's ADV_SG_BLOCK structures. */
2662 if (q->sg_list_ptr != NULL) {
2663 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2666 sg_ptr = &sgblkp->sg_block;
2667 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2668 if (sg_ptr->sg_ptr == 0) {
2671 sgblkp = sgblkp->next_sgblkp;
2676 #endif /* ADVANSYS_DEBUG */
2681 * Return suitable for printing on the console with the argument
2682 * adapter's configuration information.
2684 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2685 * otherwise the static 'info' array will be overrun.
2687 static const char *advansys_info(struct Scsi_Host *shost)
2689 static char info[ASC_INFO_SIZE];
2690 struct asc_board *boardp = shost_priv(shost);
2691 ASC_DVC_VAR *asc_dvc_varp;
2692 ADV_DVC_VAR *adv_dvc_varp;
2694 char *widename = NULL;
2696 if (ASC_NARROW_BOARD(boardp)) {
2697 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2698 ASC_DBG(1, "begin\n");
2699 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2700 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2702 busname = "ISA PnP";
2707 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2708 ASC_VERSION, busname,
2709 (ulong)shost->io_port,
2710 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2711 boardp->irq, shost->dma_channel);
2713 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2715 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2717 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2718 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2719 == ASC_IS_PCI_ULTRA) {
2720 busname = "PCI Ultra";
2726 shost_printk(KERN_ERR, shost, "unknown bus "
2727 "type %d\n", asc_dvc_varp->bus_type);
2730 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2731 ASC_VERSION, busname, (ulong)shost->io_port,
2732 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2737 * Wide Adapter Information
2739 * Memory-mapped I/O is used instead of I/O space to access
2740 * the adapter, but display the I/O Port range. The Memory
2741 * I/O address is displayed through the driver /proc file.
2743 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2744 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2745 widename = "Ultra-Wide";
2746 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2747 widename = "Ultra2-Wide";
2749 widename = "Ultra3-Wide";
2752 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2753 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2754 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2756 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2757 ASC_DBG(1, "end\n");
2761 #ifdef CONFIG_PROC_FS
2764 * asc_prt_board_devices()
2766 * Print driver information for devices attached to the board.
2768 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2770 struct asc_board *boardp = shost_priv(shost);
2775 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2778 if (ASC_NARROW_BOARD(boardp)) {
2779 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2781 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2784 seq_puts(m, "Target IDs Detected:");
2785 for (i = 0; i <= ADV_MAX_TID; i++) {
2786 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2787 seq_printf(m, " %X,", i);
2789 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2793 * Display Wide Board BIOS Information.
2795 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2797 struct asc_board *boardp = shost_priv(shost);
2798 ushort major, minor, letter;
2800 seq_puts(m, "\nROM BIOS Version: ");
2803 * If the BIOS saved a valid signature, then fill in
2804 * the BIOS code segment base address.
2806 if (boardp->bios_signature != 0x55AA) {
2807 seq_puts(m, "Disabled or Pre-3.1\n"
2808 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2809 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2811 major = (boardp->bios_version >> 12) & 0xF;
2812 minor = (boardp->bios_version >> 8) & 0xF;
2813 letter = (boardp->bios_version & 0xFF);
2815 seq_printf(m, "%d.%d%c\n",
2817 letter >= 26 ? '?' : letter + 'A');
2819 * Current available ROM BIOS release is 3.1I for UW
2820 * and 3.2I for U2W. This code doesn't differentiate
2821 * UW and U2W boards.
2823 if (major < 3 || (major <= 3 && minor < 1) ||
2824 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2825 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2826 "ftp://ftp.connectcom.net/pub\n");
2832 * Add serial number to information bar if signature AAh
2833 * is found in at bit 15-9 (7 bits) of word 1.
2835 * Serial Number consists fo 12 alpha-numeric digits.
2837 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2838 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2839 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2840 * 5 - Product revision (A-J) Word0: " "
2842 * Signature Word1: 15-9 (7 bits)
2843 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2844 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
2846 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2848 * Note 1: Only production cards will have a serial number.
2850 * Note 2: Signature is most significant 7 bits (0xFE).
2852 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2854 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2858 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2862 * First word - 6 digits.
2866 /* Product type - 1st digit. */
2867 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2868 /* Product type is P=Prototype */
2873 /* Manufacturing location - 2nd digit. */
2874 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2876 /* Product ID - 3rd, 4th digits. */
2878 *cp++ = '0' + (num / 100);
2880 *cp++ = '0' + (num / 10);
2882 /* Product revision - 5th digit. */
2883 *cp++ = 'A' + (num % 10);
2893 * If bit 15 of third word is set, then the
2894 * last digit of the year is greater than 7.
2896 if (serialnum[2] & 0x8000) {
2897 *cp++ = '8' + ((w & 0x1C0) >> 6);
2899 *cp++ = '0' + ((w & 0x1C0) >> 6);
2902 /* Week of year - 7th, 8th digits. */
2904 *cp++ = '0' + num / 10;
2911 w = serialnum[2] & 0x7FFF;
2913 /* Serial number - 9th digit. */
2914 *cp++ = 'A' + (w / 1000);
2916 /* 10th, 11th, 12th digits. */
2918 *cp++ = '0' + num / 100;
2920 *cp++ = '0' + num / 10;
2924 *cp = '\0'; /* Null Terminate the string. */
2930 * asc_prt_asc_board_eeprom()
2932 * Print board EEPROM configuration.
2934 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2936 struct asc_board *boardp = shost_priv(shost);
2937 ASC_DVC_VAR *asc_dvc_varp;
2941 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2942 #endif /* CONFIG_ISA */
2943 uchar serialstr[13];
2945 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2946 ep = &boardp->eep_config.asc_eep;
2949 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2952 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2954 seq_printf(m, " Serial Number: %s\n", serialstr);
2955 else if (ep->adapter_info[5] == 0xBB)
2957 " Default Settings Used for EEPROM-less Adapter.\n");
2959 seq_puts(m, " Serial Number Signature Not Present.\n");
2962 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2963 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2967 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2969 seq_puts(m, " Target ID: ");
2970 for (i = 0; i <= ASC_MAX_TID; i++)
2971 seq_printf(m, " %d", i);
2973 seq_puts(m, "\n Disconnects: ");
2974 for (i = 0; i <= ASC_MAX_TID; i++)
2975 seq_printf(m, " %c",
2976 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2978 seq_puts(m, "\n Command Queuing: ");
2979 for (i = 0; i <= ASC_MAX_TID; i++)
2980 seq_printf(m, " %c",
2981 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2983 seq_puts(m, "\n Start Motor: ");
2984 for (i = 0; i <= ASC_MAX_TID; i++)
2985 seq_printf(m, " %c",
2986 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2988 seq_puts(m, "\n Synchronous Transfer:");
2989 for (i = 0; i <= ASC_MAX_TID; i++)
2990 seq_printf(m, " %c",
2991 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2995 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2997 " Host ISA DMA speed: %d MB/S\n",
2998 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3000 #endif /* CONFIG_ISA */
3004 * asc_prt_adv_board_eeprom()
3006 * Print board EEPROM configuration.
3008 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3010 struct asc_board *boardp = shost_priv(shost);
3011 ADV_DVC_VAR *adv_dvc_varp;
3014 uchar serialstr[13];
3015 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3016 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3017 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3020 ushort sdtr_speed = 0;
3022 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3023 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3024 ep_3550 = &boardp->eep_config.adv_3550_eep;
3025 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3026 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3028 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3032 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3035 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3036 wordp = &ep_3550->serial_number_word1;
3037 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3038 wordp = &ep_38C0800->serial_number_word1;
3040 wordp = &ep_38C1600->serial_number_word1;
3043 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3044 seq_printf(m, " Serial Number: %s\n", serialstr);
3046 seq_puts(m, " Serial Number Signature Not Present.\n");
3048 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3050 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3051 ep_3550->adapter_scsi_id,
3052 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3053 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3055 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3056 ep_38C0800->adapter_scsi_id,
3057 ep_38C0800->max_host_qng,
3058 ep_38C0800->max_dvc_qng);
3061 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3062 ep_38C1600->adapter_scsi_id,
3063 ep_38C1600->max_host_qng,
3064 ep_38C1600->max_dvc_qng);
3065 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3066 word = ep_3550->termination;
3067 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3068 word = ep_38C0800->termination_lvd;
3070 word = ep_38C1600->termination_lvd;
3074 termstr = "Low Off/High Off";
3077 termstr = "Low Off/High On";
3080 termstr = "Low On/High On";
3084 termstr = "Automatic";
3088 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3090 " termination: %u (%s), bios_ctrl: 0x%x\n",
3091 ep_3550->termination, termstr,
3092 ep_3550->bios_ctrl);
3093 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3095 " termination: %u (%s), bios_ctrl: 0x%x\n",
3096 ep_38C0800->termination_lvd, termstr,
3097 ep_38C0800->bios_ctrl);
3100 " termination: %u (%s), bios_ctrl: 0x%x\n",
3101 ep_38C1600->termination_lvd, termstr,
3102 ep_38C1600->bios_ctrl);
3104 seq_puts(m, " Target ID: ");
3105 for (i = 0; i <= ADV_MAX_TID; i++)
3106 seq_printf(m, " %X", i);
3109 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3110 word = ep_3550->disc_enable;
3111 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3112 word = ep_38C0800->disc_enable;
3114 word = ep_38C1600->disc_enable;
3116 seq_puts(m, " Disconnects: ");
3117 for (i = 0; i <= ADV_MAX_TID; i++)
3118 seq_printf(m, " %c",
3119 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3122 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3123 word = ep_3550->tagqng_able;
3124 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3125 word = ep_38C0800->tagqng_able;
3127 word = ep_38C1600->tagqng_able;
3129 seq_puts(m, " Command Queuing: ");
3130 for (i = 0; i <= ADV_MAX_TID; i++)
3131 seq_printf(m, " %c",
3132 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3135 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3136 word = ep_3550->start_motor;
3137 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3138 word = ep_38C0800->start_motor;
3140 word = ep_38C1600->start_motor;
3142 seq_puts(m, " Start Motor: ");
3143 for (i = 0; i <= ADV_MAX_TID; i++)
3144 seq_printf(m, " %c",
3145 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3148 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3149 seq_puts(m, " Synchronous Transfer:");
3150 for (i = 0; i <= ADV_MAX_TID; i++)
3151 seq_printf(m, " %c",
3152 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3157 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3158 seq_puts(m, " Ultra Transfer: ");
3159 for (i = 0; i <= ADV_MAX_TID; i++)
3160 seq_printf(m, " %c",
3161 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3166 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3167 word = ep_3550->wdtr_able;
3168 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3169 word = ep_38C0800->wdtr_able;
3171 word = ep_38C1600->wdtr_able;
3173 seq_puts(m, " Wide Transfer: ");
3174 for (i = 0; i <= ADV_MAX_TID; i++)
3175 seq_printf(m, " %c",
3176 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3179 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3180 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3181 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
3182 for (i = 0; i <= ADV_MAX_TID; i++) {
3186 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3187 } else if (i == 4) {
3188 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3189 } else if (i == 8) {
3190 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3191 } else if (i == 12) {
3192 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3194 switch (sdtr_speed & ADV_MAX_TID) {
3217 seq_printf(m, "%X:%s ", i, speed_str);
3227 * asc_prt_driver_conf()
3229 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3231 struct asc_board *boardp = shost_priv(shost);
3235 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3239 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
3240 atomic_read(&shost->host_busy), shost->max_id,
3241 shost->max_lun, shost->max_channel);
3244 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3245 shost->unique_id, shost->can_queue, shost->this_id,
3246 shost->sg_tablesize, shost->cmd_per_lun);
3249 " unchecked_isa_dma %d, use_clustering %d\n",
3250 shost->unchecked_isa_dma, shost->use_clustering);
3253 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3254 boardp->flags, shost->last_reset, jiffies,
3255 boardp->asc_n_io_port);
3257 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3259 if (ASC_NARROW_BOARD(boardp)) {
3260 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3262 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3267 * asc_prt_asc_board_info()
3269 * Print dynamic board configuration information.
3271 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3273 struct asc_board *boardp = shost_priv(shost);
3278 int renegotiate = 0;
3280 v = &boardp->dvc_var.asc_dvc_var;
3281 c = &boardp->dvc_cfg.asc_dvc_cfg;
3282 chip_scsi_id = c->chip_scsi_id;
3285 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3288 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3289 "mcode_version 0x%x, err_code %u\n",
3290 c->chip_version, c->mcode_date, c->mcode_version,
3293 /* Current number of commands waiting for the host. */
3295 " Total Command Pending: %d\n", v->cur_total_qng);
3297 seq_puts(m, " Command Queuing:");
3298 for (i = 0; i <= ASC_MAX_TID; i++) {
3299 if ((chip_scsi_id == i) ||
3300 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3303 seq_printf(m, " %X:%c",
3305 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3308 /* Current number of commands waiting for a device. */
3309 seq_puts(m, "\n Command Queue Pending:");
3310 for (i = 0; i <= ASC_MAX_TID; i++) {
3311 if ((chip_scsi_id == i) ||
3312 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3315 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3318 /* Current limit on number of commands that can be sent to a device. */
3319 seq_puts(m, "\n Command Queue Limit:");
3320 for (i = 0; i <= ASC_MAX_TID; i++) {
3321 if ((chip_scsi_id == i) ||
3322 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3325 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3328 /* Indicate whether the device has returned queue full status. */
3329 seq_puts(m, "\n Command Queue Full:");
3330 for (i = 0; i <= ASC_MAX_TID; i++) {
3331 if ((chip_scsi_id == i) ||
3332 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3335 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3336 seq_printf(m, " %X:Y-%d",
3337 i, boardp->queue_full_cnt[i]);
3339 seq_printf(m, " %X:N", i);
3342 seq_puts(m, "\n Synchronous Transfer:");
3343 for (i = 0; i <= ASC_MAX_TID; i++) {
3344 if ((chip_scsi_id == i) ||
3345 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3348 seq_printf(m, " %X:%c",
3350 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3354 for (i = 0; i <= ASC_MAX_TID; i++) {
3355 uchar syn_period_ix;
3357 if ((chip_scsi_id == i) ||
3358 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3359 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3363 seq_printf(m, " %X:", i);
3365 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3366 seq_puts(m, " Asynchronous");
3369 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3373 " Transfer Period Factor: %d (%d.%d Mhz),",
3374 v->sdtr_period_tbl[syn_period_ix],
3375 250 / v->sdtr_period_tbl[syn_period_ix],
3377 v->sdtr_period_tbl[syn_period_ix]));
3379 seq_printf(m, " REQ/ACK Offset: %d",
3380 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3383 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3392 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3397 * asc_prt_adv_board_info()
3399 * Print dynamic board configuration information.
3401 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3403 struct asc_board *boardp = shost_priv(shost);
3407 AdvPortAddr iop_base;
3408 ushort chip_scsi_id;
3412 ushort sdtr_able, wdtr_able;
3413 ushort wdtr_done, sdtr_done;
3415 int renegotiate = 0;
3417 v = &boardp->dvc_var.adv_dvc_var;
3418 c = &boardp->dvc_cfg.adv_dvc_cfg;
3419 iop_base = v->iop_base;
3420 chip_scsi_id = v->chip_scsi_id;
3423 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3427 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3428 (unsigned long)v->iop_base,
3429 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3432 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3433 "mcode_version 0x%x\n", c->chip_version,
3434 c->mcode_date, c->mcode_version);
3436 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3437 seq_puts(m, " Queuing Enabled:");
3438 for (i = 0; i <= ADV_MAX_TID; i++) {
3439 if ((chip_scsi_id == i) ||
3440 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3444 seq_printf(m, " %X:%c",
3446 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3449 seq_puts(m, "\n Queue Limit:");
3450 for (i = 0; i <= ADV_MAX_TID; i++) {
3451 if ((chip_scsi_id == i) ||
3452 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3456 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3459 seq_printf(m, " %X:%d", i, lrambyte);
3462 seq_puts(m, "\n Command Pending:");
3463 for (i = 0; i <= ADV_MAX_TID; i++) {
3464 if ((chip_scsi_id == i) ||
3465 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3469 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3472 seq_printf(m, " %X:%d", i, lrambyte);
3476 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3477 seq_puts(m, " Wide Enabled:");
3478 for (i = 0; i <= ADV_MAX_TID; i++) {
3479 if ((chip_scsi_id == i) ||
3480 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3484 seq_printf(m, " %X:%c",
3486 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3490 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3491 seq_puts(m, " Transfer Bit Width:");
3492 for (i = 0; i <= ADV_MAX_TID; i++) {
3493 if ((chip_scsi_id == i) ||
3494 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3498 AdvReadWordLram(iop_base,
3499 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3502 seq_printf(m, " %X:%d",
3503 i, (lramword & 0x8000) ? 16 : 8);
3505 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3506 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3513 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3514 seq_puts(m, " Synchronous Enabled:");
3515 for (i = 0; i <= ADV_MAX_TID; i++) {
3516 if ((chip_scsi_id == i) ||
3517 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3521 seq_printf(m, " %X:%c",
3523 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3527 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3528 for (i = 0; i <= ADV_MAX_TID; i++) {
3530 AdvReadWordLram(iop_base,
3531 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3533 lramword &= ~0x8000;
3535 if ((chip_scsi_id == i) ||
3536 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3537 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3541 seq_printf(m, " %X:", i);
3543 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
3544 seq_puts(m, " Asynchronous");
3546 seq_puts(m, " Transfer Period Factor: ");
3548 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
3549 seq_puts(m, "9 (80.0 Mhz),");
3550 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
3551 seq_puts(m, "10 (40.0 Mhz),");
3552 } else { /* 20 Mhz or below. */
3554 period = (((lramword >> 8) * 25) + 50) / 4;
3556 if (period == 0) { /* Should never happen. */
3557 seq_printf(m, "%d (? Mhz), ", period);
3561 period, 250 / period,
3562 ASC_TENTHS(250, period));
3566 seq_printf(m, " REQ/ACK Offset: %d",
3570 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3579 seq_puts(m, " * = Re-negotiation pending before next command.\n");
3583 #ifdef ADVANSYS_STATS
3585 * asc_prt_board_stats()
3587 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3589 struct asc_board *boardp = shost_priv(shost);
3590 struct asc_stats *s = &boardp->asc_stats;
3593 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3597 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3598 s->queuecommand, s->reset, s->biosparam,
3602 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3603 s->callback, s->done, s->build_error,
3604 s->adv_build_noreq, s->adv_build_nosg);
3607 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3608 s->exe_noerror, s->exe_busy, s->exe_error,
3612 * Display data transfer statistics.
3614 if (s->xfer_cnt > 0) {
3615 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3616 s->xfer_cnt, s->xfer_elem);
3618 seq_printf(m, "xfer_bytes %u.%01u kb\n",
3619 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3621 /* Scatter gather transfer statistics */
3622 seq_printf(m, " avg_num_elem %u.%01u, ",
3623 s->xfer_elem / s->xfer_cnt,
3624 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3626 seq_printf(m, "avg_elem_size %u.%01u kb, ",
3627 (s->xfer_sect / 2) / s->xfer_elem,
3628 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3630 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3631 (s->xfer_sect / 2) / s->xfer_cnt,
3632 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3635 #endif /* ADVANSYS_STATS */
3638 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3640 * m: seq_file to print into
3643 * Return the number of bytes read from or written to a
3644 * /proc/scsi/advansys/[0...] file.
3647 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3649 struct asc_board *boardp = shost_priv(shost);
3651 ASC_DBG(1, "begin\n");
3654 * User read of /proc/scsi/advansys/[0...] file.
3658 * Get board configuration information.
3660 * advansys_info() returns the board string from its own static buffer.
3662 /* Copy board information. */
3663 seq_printf(m, "%s\n", (char *)advansys_info(shost));
3665 * Display Wide Board BIOS Information.
3667 if (!ASC_NARROW_BOARD(boardp))
3668 asc_prt_adv_bios(m, shost);
3671 * Display driver information for each device attached to the board.
3673 asc_prt_board_devices(m, shost);
3676 * Display EEPROM configuration for the board.
3678 if (ASC_NARROW_BOARD(boardp))
3679 asc_prt_asc_board_eeprom(m, shost);
3681 asc_prt_adv_board_eeprom(m, shost);
3684 * Display driver configuration and information for the board.
3686 asc_prt_driver_conf(m, shost);
3688 #ifdef ADVANSYS_STATS
3690 * Display driver statistics for the board.
3692 asc_prt_board_stats(m, shost);
3693 #endif /* ADVANSYS_STATS */
3696 * Display Asc Library dynamic configuration information
3699 if (ASC_NARROW_BOARD(boardp))
3700 asc_prt_asc_board_info(m, shost);
3702 asc_prt_adv_board_info(m, shost);
3705 #endif /* CONFIG_PROC_FS */
3707 static void asc_scsi_done(struct scsi_cmnd *scp)
3709 scsi_dma_unmap(scp);
3710 ASC_STATS(scp->device->host, done);
3711 scp->scsi_done(scp);
3714 static void AscSetBank(PortAddr iop_base, uchar bank)
3718 val = AscGetChipControl(iop_base) &
3720 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3724 } else if (bank == 2) {
3725 val |= CC_DIAG | CC_BANK_ONE;
3727 val &= ~CC_BANK_ONE;
3729 AscSetChipControl(iop_base, val);
3732 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3734 AscSetBank(iop_base, 1);
3735 AscWriteChipIH(iop_base, ins_code);
3736 AscSetBank(iop_base, 0);
3739 static int AscStartChip(PortAddr iop_base)
3741 AscSetChipControl(iop_base, 0);
3742 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3748 static bool AscStopChip(PortAddr iop_base)
3753 AscGetChipControl(iop_base) &
3754 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3755 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3756 AscSetChipIH(iop_base, INS_HALT);
3757 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3758 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3764 static bool AscIsChipHalted(PortAddr iop_base)
3766 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3767 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3774 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3779 iop_base = asc_dvc->iop_base;
3780 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3784 AscStopChip(iop_base);
3785 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3787 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3788 AscSetChipIH(iop_base, INS_HALT);
3789 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3790 AscSetChipControl(iop_base, CC_HALT);
3792 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3793 AscSetChipStatus(iop_base, 0);
3794 return (AscIsChipHalted(iop_base));
3797 static int AscFindSignature(PortAddr iop_base)
3801 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3802 iop_base, AscGetChipSignatureByte(iop_base));
3803 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3804 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3805 iop_base, AscGetChipSignatureWord(iop_base));
3806 sig_word = AscGetChipSignatureWord(iop_base);
3807 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3808 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3815 static void AscEnableInterrupt(PortAddr iop_base)
3819 cfg = AscGetChipCfgLsw(iop_base);
3820 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3823 static void AscDisableInterrupt(PortAddr iop_base)
3827 cfg = AscGetChipCfgLsw(iop_base);
3828 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3831 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3833 unsigned char byte_data;
3834 unsigned short word_data;
3836 if (isodd_word(addr)) {
3837 AscSetChipLramAddr(iop_base, addr - 1);
3838 word_data = AscGetChipLramData(iop_base);
3839 byte_data = (word_data >> 8) & 0xFF;
3841 AscSetChipLramAddr(iop_base, addr);
3842 word_data = AscGetChipLramData(iop_base);
3843 byte_data = word_data & 0xFF;
3848 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3852 AscSetChipLramAddr(iop_base, addr);
3853 word_data = AscGetChipLramData(iop_base);
3857 #if CC_VERY_LONG_SG_LIST
3858 static u32 AscReadLramDWord(PortAddr iop_base, ushort addr)
3860 ushort val_low, val_high;
3863 AscSetChipLramAddr(iop_base, addr);
3864 val_low = AscGetChipLramData(iop_base);
3865 val_high = AscGetChipLramData(iop_base);
3866 dword_data = ((u32) val_high << 16) | (u32) val_low;
3867 return (dword_data);
3869 #endif /* CC_VERY_LONG_SG_LIST */
3872 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3876 AscSetChipLramAddr(iop_base, s_addr);
3877 for (i = 0; i < words; i++) {
3878 AscSetChipLramData(iop_base, set_wval);
3882 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3884 AscSetChipLramAddr(iop_base, addr);
3885 AscSetChipLramData(iop_base, word_val);
3888 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3892 if (isodd_word(addr)) {
3894 word_data = AscReadLramWord(iop_base, addr);
3895 word_data &= 0x00FF;
3896 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3898 word_data = AscReadLramWord(iop_base, addr);
3899 word_data &= 0xFF00;
3900 word_data |= ((ushort)byte_val & 0x00FF);
3902 AscWriteLramWord(iop_base, addr, word_data);
3906 * Copy 2 bytes to LRAM.
3908 * The source data is assumed to be in little-endian order in memory
3909 * and is maintained in little-endian order when written to LRAM.
3912 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3913 const uchar *s_buffer, int words)
3917 AscSetChipLramAddr(iop_base, s_addr);
3918 for (i = 0; i < 2 * words; i += 2) {
3920 * On a little-endian system the second argument below
3921 * produces a little-endian ushort which is written to
3922 * LRAM in little-endian order. On a big-endian system
3923 * the second argument produces a big-endian ushort which
3924 * is "transparently" byte-swapped by outpw() and written
3925 * in little-endian order to LRAM.
3927 outpw(iop_base + IOP_RAM_DATA,
3928 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3933 * Copy 4 bytes to LRAM.
3935 * The source data is assumed to be in little-endian order in memory
3936 * and is maintained in little-endian order when written to LRAM.
3939 AscMemDWordCopyPtrToLram(PortAddr iop_base,
3940 ushort s_addr, uchar *s_buffer, int dwords)
3944 AscSetChipLramAddr(iop_base, s_addr);
3945 for (i = 0; i < 4 * dwords; i += 4) {
3946 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3947 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3952 * Copy 2 bytes from LRAM.
3954 * The source data is assumed to be in little-endian order in LRAM
3955 * and is maintained in little-endian order when written to memory.
3958 AscMemWordCopyPtrFromLram(PortAddr iop_base,
3959 ushort s_addr, uchar *d_buffer, int words)
3964 AscSetChipLramAddr(iop_base, s_addr);
3965 for (i = 0; i < 2 * words; i += 2) {
3966 word = inpw(iop_base + IOP_RAM_DATA);
3967 d_buffer[i] = word & 0xff;
3968 d_buffer[i + 1] = (word >> 8) & 0xff;
3972 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3977 for (i = 0; i < words; i++, s_addr += 2) {
3978 sum += AscReadLramWord(iop_base, s_addr);
3983 static void AscInitLram(ASC_DVC_VAR *asc_dvc)
3989 iop_base = asc_dvc->iop_base;
3990 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3991 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3993 i = ASC_MIN_ACTIVE_QNO;
3994 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3995 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3997 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3998 (uchar)(asc_dvc->max_total_qng));
3999 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4002 s_addr += ASC_QBLK_SIZE;
4003 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4004 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4006 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4008 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4011 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4012 (uchar)ASC_QLINK_END);
4013 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4014 (uchar)(asc_dvc->max_total_qng - 1));
4015 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4016 (uchar)asc_dvc->max_total_qng);
4018 s_addr += ASC_QBLK_SIZE;
4019 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4020 i++, s_addr += ASC_QBLK_SIZE) {
4021 AscWriteLramByte(iop_base,
4022 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4023 AscWriteLramByte(iop_base,
4024 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4025 AscWriteLramByte(iop_base,
4026 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4031 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4032 const uchar *mcode_buf, ushort mcode_size)
4035 ushort mcode_word_size;
4036 ushort mcode_chksum;
4038 /* Write the microcode buffer starting at LRAM address 0. */
4039 mcode_word_size = (ushort)(mcode_size >> 1);
4040 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4041 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4043 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4044 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4045 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4046 (ushort)ASC_CODE_SEC_BEG,
4047 (ushort)((mcode_size -
4051 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4052 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4053 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4057 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4063 iop_base = asc_dvc->iop_base;
4064 AscPutRiscVarFreeQHead(iop_base, 1);
4065 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4066 AscPutVarFreeQHead(iop_base, 1);
4067 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4068 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4069 (uchar)((int)asc_dvc->max_total_qng + 1));
4070 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4071 (uchar)((int)asc_dvc->max_total_qng + 2));
4072 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4073 asc_dvc->max_total_qng);
4074 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4075 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4076 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4077 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4078 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4079 AscPutQDoneInProgress(iop_base, 0);
4080 lram_addr = ASC_QADR_BEG;
4081 for (i = 0; i < 32; i++, lram_addr += 2) {
4082 AscWriteLramWord(iop_base, lram_addr, 0);
4086 static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4093 struct asc_board *board = asc_dvc_to_board(asc_dvc);
4095 iop_base = asc_dvc->iop_base;
4097 for (i = 0; i <= ASC_MAX_TID; i++) {
4098 AscPutMCodeInitSDTRAtID(iop_base, i,
4099 asc_dvc->cfg->sdtr_period_offset[i]);
4102 AscInitQLinkVar(asc_dvc);
4103 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4104 asc_dvc->cfg->disc_enable);
4105 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4106 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4108 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4109 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4110 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4111 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4112 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4113 warn_code = -ENOMEM;
4116 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4117 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4118 (uchar *)&phy_addr, 1);
4119 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4120 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4121 (uchar *)&phy_size, 1);
4123 asc_dvc->cfg->mcode_date =
4124 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4125 asc_dvc->cfg->mcode_version =
4126 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4128 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4129 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4130 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4131 warn_code = -EINVAL;
4132 goto err_mcode_start;
4134 if (AscStartChip(iop_base) != 1) {
4135 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4137 goto err_mcode_start;
4143 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4144 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4146 asc_dvc->overrun_dma = 0;
4150 static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4152 const struct firmware *fw;
4153 const char fwname[] = "advansys/mcode.bin";
4155 unsigned long chksum;
4159 iop_base = asc_dvc->iop_base;
4161 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4162 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4163 AscResetChipAndScsiBus(asc_dvc);
4164 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4166 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4167 if (asc_dvc->err_code != 0)
4169 if (!AscFindSignature(asc_dvc->iop_base)) {
4170 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4173 AscDisableInterrupt(iop_base);
4174 AscInitLram(asc_dvc);
4176 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4178 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4180 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4184 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4186 release_firmware(fw);
4187 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4190 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4191 (fw->data[1] << 8) | fw->data[0];
4192 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4193 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4194 fw->size - 4) != chksum) {
4195 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4196 release_firmware(fw);
4199 release_firmware(fw);
4200 warn_code |= AscInitMicroCodeVar(asc_dvc);
4201 if (!asc_dvc->overrun_dma)
4203 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4204 AscEnableInterrupt(iop_base);
4209 * Load the Microcode
4211 * Write the microcode image to RISC memory starting at address 0.
4213 * The microcode is stored compressed in the following format:
4215 * 254 word (508 byte) table indexed by byte code followed
4216 * by the following byte codes:
4219 * 00: Emit word 0 in table.
4220 * 01: Emit word 1 in table.
4222 * FD: Emit word 253 in table.
4225 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4226 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4228 * Returns 0 or an error if the checksum doesn't match
4230 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4231 int size, int memsize, int chksum)
4233 int i, j, end, len = 0;
4236 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4238 for (i = 253 * 2; i < size; i++) {
4239 if (buf[i] == 0xff) {
4240 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4241 for (j = 0; j < buf[i + 1]; j++) {
4242 AdvWriteWordAutoIncLram(iop_base, word);
4246 } else if (buf[i] == 0xfe) {
4247 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4248 AdvWriteWordAutoIncLram(iop_base, word);
4252 unsigned int off = buf[i] * 2;
4253 unsigned short word = (buf[off + 1] << 8) | buf[off];
4254 AdvWriteWordAutoIncLram(iop_base, word);
4261 while (len < memsize) {
4262 AdvWriteWordAutoIncLram(iop_base, 0);
4266 /* Verify the microcode checksum. */
4268 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4270 for (len = 0; len < end; len += 2) {
4271 sum += AdvReadWordAutoIncLram(iop_base);
4275 return ASC_IERR_MCODE_CHKSUM;
4280 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4282 off_t carr_offset = 0, next_offset;
4283 dma_addr_t carr_paddr;
4284 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4286 for (i = 0; i < carr_num; i++) {
4287 carr_offset = i * sizeof(ADV_CARR_T);
4288 /* Get physical address of the carrier 'carrp'. */
4289 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4291 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4292 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4293 adv_dvc->carrier[i].areq_vpa = 0;
4294 next_offset = carr_offset + sizeof(ADV_CARR_T);
4297 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4300 * We cannot have a carrier with 'carr_va' of '0', as
4301 * a reference to this carrier would be interpreted as
4303 * So start at carrier 1 with the freelist.
4305 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4308 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4312 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4314 index = offset / sizeof(ADV_CARR_T);
4315 return &adv_dvc->carrier[index];
4318 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4320 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4321 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4323 if (next_vpa == 0 || next_vpa == ~0) {
4324 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4328 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4330 * insert stopper carrier to terminate list
4332 carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4338 * 'offset' is the index in the request pointer array
4340 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4342 struct asc_board *boardp = adv_dvc->drv_ptr;
4344 BUG_ON(offset > adv_dvc->max_host_qng);
4345 return &boardp->adv_reqp[offset];
4349 * Send an idle command to the chip and wait for completion.
4351 * Command completion is polled for once per microsecond.
4353 * The function can be called from anywhere including an interrupt handler.
4354 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4355 * functions to prevent reentrancy.
4358 * ADV_TRUE - command completed successfully
4359 * ADV_FALSE - command failed
4360 * ADV_ERROR - command timed out
4363 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4364 ushort idle_cmd, u32 idle_cmd_parameter)
4367 AdvPortAddr iop_base;
4369 iop_base = asc_dvc->iop_base;
4372 * Clear the idle command status which is set by the microcode
4373 * to a non-zero value to indicate when the command is completed.
4374 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4376 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4379 * Write the idle command value after the idle command parameter
4380 * has been written to avoid a race condition. If the order is not
4381 * followed, the microcode may process the idle command before the
4382 * parameters have been written to LRAM.
4384 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4385 cpu_to_le32(idle_cmd_parameter));
4386 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4389 * Tickle the RISC to tell it to process the idle command.
4391 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4392 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4394 * Clear the tickle value. In the ASC-3550 the RISC flag
4395 * command 'clr_tickle_b' does not work unless the host
4398 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4401 /* Wait for up to 100 millisecond for the idle command to timeout. */
4402 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4403 /* Poll once each microsecond for command completion. */
4404 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4405 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4413 BUG(); /* The idle command should never timeout. */
4418 * Reset SCSI Bus and purge all outstanding requests.
4421 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4422 * ADV_FALSE(0) - Microcode command failed.
4423 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4424 * may be hung which requires driver recovery.
4426 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4431 * Send the SCSI Bus Reset idle start idle command which asserts
4432 * the SCSI Bus Reset signal.
4434 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4435 if (status != ADV_TRUE) {
4440 * Delay for the specified SCSI Bus Reset hold time.
4442 * The hold time delay is done on the host because the RISC has no
4443 * microsecond accurate timer.
4445 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4448 * Send the SCSI Bus Reset end idle command which de-asserts
4449 * the SCSI Bus Reset signal and purges any pending requests.
4451 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4452 if (status != ADV_TRUE) {
4456 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4462 * Initialize the ASC-3550.
4464 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4466 * For a non-fatal error return a warning code. If there are no warnings
4467 * then 0 is returned.
4469 * Needed after initialization for error recovery.
4471 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4473 const struct firmware *fw;
4474 const char fwname[] = "advansys/3550.bin";
4475 AdvPortAddr iop_base;
4483 unsigned long chksum;
4486 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4487 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4488 uchar max_cmd[ADV_MAX_TID + 1];
4490 /* If there is already an error, don't continue. */
4491 if (asc_dvc->err_code != 0)
4495 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4497 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4498 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4503 iop_base = asc_dvc->iop_base;
4506 * Save the RISC memory BIOS region before writing the microcode.
4507 * The BIOS may already be loaded and using its RISC LRAM region
4508 * so its region must be saved and restored.
4510 * Note: This code makes the assumption, which is currently true,
4511 * that a chip reset does not clear RISC LRAM.
4513 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4514 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4519 * Save current per TID negotiated values.
4521 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4522 ushort bios_version, major, minor;
4525 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4526 major = (bios_version >> 12) & 0xF;
4527 minor = (bios_version >> 8) & 0xF;
4528 if (major < 3 || (major == 3 && minor == 1)) {
4529 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4530 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4532 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4535 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4536 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4537 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4538 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4542 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4544 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4546 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4550 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4552 release_firmware(fw);
4553 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4556 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4557 (fw->data[1] << 8) | fw->data[0];
4558 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4559 fw->size - 4, ADV_3550_MEMSIZE,
4561 release_firmware(fw);
4562 if (asc_dvc->err_code)
4566 * Restore the RISC memory BIOS region.
4568 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4569 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4574 * Calculate and write the microcode code checksum to the microcode
4575 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4577 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4578 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4580 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4581 for (word = begin_addr; word < end_addr; word += 2) {
4582 code_sum += AdvReadWordAutoIncLram(iop_base);
4584 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4587 * Read and save microcode version and date.
4589 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4590 asc_dvc->cfg->mcode_date);
4591 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4592 asc_dvc->cfg->mcode_version);
4595 * Set the chip type to indicate the ASC3550.
4597 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4600 * If the PCI Configuration Command Register "Parity Error Response
4601 * Control" Bit was clear (0), then set the microcode variable
4602 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4603 * to ignore DMA parity errors.
4605 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4606 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4607 word |= CONTROL_FLAG_IGNORE_PERR;
4608 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4612 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4613 * threshold of 128 bytes. This register is only accessible to the host.
4615 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4616 START_CTL_EMFU | READ_CMD_MRM);
4619 * Microcode operating variables for WDTR, SDTR, and command tag
4620 * queuing will be set in slave_configure() based on what a
4621 * device reports it is capable of in Inquiry byte 7.
4623 * If SCSI Bus Resets have been disabled, then directly set
4624 * SDTR and WDTR from the EEPROM configuration. This will allow
4625 * the BIOS and warm boot to work without a SCSI bus hang on
4626 * the Inquiry caused by host and target mismatched DTR values.
4627 * Without the SCSI Bus Reset, before an Inquiry a device can't
4628 * be assumed to be in Asynchronous, Narrow mode.
4630 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4631 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4632 asc_dvc->wdtr_able);
4633 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4634 asc_dvc->sdtr_able);
4638 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4639 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4640 * bitmask. These values determine the maximum SDTR speed negotiated
4643 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4644 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4645 * without determining here whether the device supports SDTR.
4647 * 4-bit speed SDTR speed name
4648 * =========== ===============
4649 * 0000b (0x0) SDTR disabled
4651 * 0010b (0x2) 10 Mhz
4652 * 0011b (0x3) 20 Mhz (Ultra)
4653 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4654 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4655 * 0110b (0x6) Undefined
4657 * 1111b (0xF) Undefined
4660 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4661 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4662 /* Set Ultra speed for TID 'tid'. */
4663 word |= (0x3 << (4 * (tid % 4)));
4665 /* Set Fast speed for TID 'tid'. */
4666 word |= (0x2 << (4 * (tid % 4)));
4668 if (tid == 3) { /* Check if done with sdtr_speed1. */
4669 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4671 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4672 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4674 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4675 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4677 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4678 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4684 * Set microcode operating variable for the disconnect per TID bitmask.
4686 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4687 asc_dvc->cfg->disc_enable);
4690 * Set SCSI_CFG0 Microcode Default Value.
4692 * The microcode will set the SCSI_CFG0 register using this value
4693 * after it is started below.
4695 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4696 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4697 asc_dvc->chip_scsi_id);
4700 * Determine SCSI_CFG1 Microcode Default Value.
4702 * The microcode will set the SCSI_CFG1 register using this value
4703 * after it is started below.
4706 /* Read current SCSI_CFG1 Register value. */
4707 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4710 * If all three connectors are in use, return an error.
4712 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4713 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4714 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4719 * If the internal narrow cable is reversed all of the SCSI_CTRL
4720 * register signals will be set. Check for and return an error if
4721 * this condition is found.
4723 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4724 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4729 * If this is a differential board and a single-ended device
4730 * is attached to one of the connectors, return an error.
4732 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4733 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4738 * If automatic termination control is enabled, then set the
4739 * termination value based on a table listed in a_condor.h.
4741 * If manual termination was specified with an EEPROM setting
4742 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4743 * is ready to be 'ored' into SCSI_CFG1.
4745 if (asc_dvc->cfg->termination == 0) {
4747 * The software always controls termination by setting TERM_CTL_SEL.
4748 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4750 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4752 switch (scsi_cfg1 & CABLE_DETECT) {
4753 /* TERM_CTL_H: on, TERM_CTL_L: on */
4760 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4763 /* TERM_CTL_H: on, TERM_CTL_L: off */
4769 asc_dvc->cfg->termination |= TERM_CTL_H;
4772 /* TERM_CTL_H: off, TERM_CTL_L: off */
4780 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4782 scsi_cfg1 &= ~TERM_CTL;
4785 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4786 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4787 * referenced, because the hardware internally inverts
4788 * the Termination High and Low bits if TERM_POL is set.
4790 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4793 * Set SCSI_CFG1 Microcode Default Value
4795 * Set filter value and possibly modified termination control
4796 * bits in the Microcode SCSI_CFG1 Register Value.
4798 * The microcode will set the SCSI_CFG1 register using this value
4799 * after it is started below.
4801 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4802 FLTR_DISABLE | scsi_cfg1);
4805 * Set MEM_CFG Microcode Default Value
4807 * The microcode will set the MEM_CFG register using this value
4808 * after it is started below.
4810 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4813 * ASC-3550 has 8KB internal memory.
4815 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4816 BIOS_EN | RAM_SZ_8KB);
4819 * Set SEL_MASK Microcode Default Value
4821 * The microcode will set the SEL_MASK register using this value
4822 * after it is started below.
4824 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4825 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4827 AdvBuildCarrierFreelist(asc_dvc);
4830 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4833 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4834 if (!asc_dvc->icq_sp) {
4835 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4840 * Set RISC ICQ physical address start value.
4842 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4845 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4847 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4848 if (!asc_dvc->irq_sp) {
4849 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4854 * Set RISC IRQ physical address start value.
4856 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4857 asc_dvc->carr_pending_cnt = 0;
4859 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4860 (ADV_INTR_ENABLE_HOST_INTR |
4861 ADV_INTR_ENABLE_GLOBAL_INTR));
4863 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4864 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4866 /* finally, finally, gentlemen, start your engine */
4867 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4870 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4871 * Resets should be performed. The RISC has to be running
4872 * to issue a SCSI Bus Reset.
4874 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4876 * If the BIOS Signature is present in memory, restore the
4877 * BIOS Handshake Configuration Table and do not perform
4880 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4883 * Restore per TID negotiated values.
4885 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4886 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4887 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4889 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4890 AdvWriteByteLram(iop_base,
4891 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4895 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4896 warn_code = ASC_WARN_BUSRESET_ERROR;
4905 * Initialize the ASC-38C0800.
4907 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4909 * For a non-fatal error return a warning code. If there are no warnings
4910 * then 0 is returned.
4912 * Needed after initialization for error recovery.
4914 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4916 const struct firmware *fw;
4917 const char fwname[] = "advansys/38C0800.bin";
4918 AdvPortAddr iop_base;
4926 unsigned long chksum;
4930 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4931 ushort wdtr_able, sdtr_able, tagqng_able;
4932 uchar max_cmd[ADV_MAX_TID + 1];
4934 /* If there is already an error, don't continue. */
4935 if (asc_dvc->err_code != 0)
4939 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4941 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4942 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4947 iop_base = asc_dvc->iop_base;
4950 * Save the RISC memory BIOS region before writing the microcode.
4951 * The BIOS may already be loaded and using its RISC LRAM region
4952 * so its region must be saved and restored.
4954 * Note: This code makes the assumption, which is currently true,
4955 * that a chip reset does not clear RISC LRAM.
4957 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4958 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4963 * Save current per TID negotiated values.
4965 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4966 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4967 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4968 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4969 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4974 * RAM BIST (RAM Built-In Self Test)
4976 * Address : I/O base + offset 0x38h register (byte).
4977 * Function: Bit 7-6(RW) : RAM mode
4978 * Normal Mode : 0x00
4979 * Pre-test Mode : 0x40
4980 * RAM Test Mode : 0x80
4982 * Bit 4(RO) : Done bit
4983 * Bit 3-0(RO) : Status
4985 * Int_RAM Error : 0x04
4990 * Note: RAM BIST code should be put right here, before loading the
4991 * microcode and after saving the RISC memory BIOS region.
4997 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
4998 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
4999 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5000 * to NORMAL_MODE, return an error too.
5002 for (i = 0; i < 2; i++) {
5003 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5004 mdelay(10); /* Wait for 10ms before reading back. */
5005 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5006 if ((byte & RAM_TEST_DONE) == 0
5007 || (byte & 0x0F) != PRE_TEST_VALUE) {
5008 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5012 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5013 mdelay(10); /* Wait for 10ms before reading back. */
5014 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5016 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5022 * LRAM Test - It takes about 1.5 ms to run through the test.
5024 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5025 * If Done bit not set or Status not 0, save register byte, set the
5026 * err_code, and return an error.
5028 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5029 mdelay(10); /* Wait for 10ms before checking status. */
5031 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5032 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5033 /* Get here if Done bit not set or Status not 0. */
5034 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5035 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5039 /* We need to reset back to normal mode after LRAM test passes. */
5040 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5042 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5044 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5046 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5050 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5052 release_firmware(fw);
5053 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5056 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5057 (fw->data[1] << 8) | fw->data[0];
5058 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5059 fw->size - 4, ADV_38C0800_MEMSIZE,
5061 release_firmware(fw);
5062 if (asc_dvc->err_code)
5066 * Restore the RISC memory BIOS region.
5068 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5069 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5074 * Calculate and write the microcode code checksum to the microcode
5075 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5077 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5078 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5080 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5081 for (word = begin_addr; word < end_addr; word += 2) {
5082 code_sum += AdvReadWordAutoIncLram(iop_base);
5084 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5087 * Read microcode version and date.
5089 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5090 asc_dvc->cfg->mcode_date);
5091 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5092 asc_dvc->cfg->mcode_version);
5095 * Set the chip type to indicate the ASC38C0800.
5097 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5100 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5101 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5102 * cable detection and then we are able to read C_DET[3:0].
5104 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5105 * Microcode Default Value' section below.
5107 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5108 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5109 scsi_cfg1 | DIS_TERM_DRV);
5112 * If the PCI Configuration Command Register "Parity Error Response
5113 * Control" Bit was clear (0), then set the microcode variable
5114 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5115 * to ignore DMA parity errors.
5117 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5118 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5119 word |= CONTROL_FLAG_IGNORE_PERR;
5120 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5124 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5125 * bits for the default FIFO threshold.
5127 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5129 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5131 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5132 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5136 * Microcode operating variables for WDTR, SDTR, and command tag
5137 * queuing will be set in slave_configure() based on what a
5138 * device reports it is capable of in Inquiry byte 7.
5140 * If SCSI Bus Resets have been disabled, then directly set
5141 * SDTR and WDTR from the EEPROM configuration. This will allow
5142 * the BIOS and warm boot to work without a SCSI bus hang on
5143 * the Inquiry caused by host and target mismatched DTR values.
5144 * Without the SCSI Bus Reset, before an Inquiry a device can't
5145 * be assumed to be in Asynchronous, Narrow mode.
5147 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5148 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5149 asc_dvc->wdtr_able);
5150 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5151 asc_dvc->sdtr_able);
5155 * Set microcode operating variables for DISC and SDTR_SPEED1,
5156 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5157 * configuration values.
5159 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5160 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5161 * without determining here whether the device supports SDTR.
5163 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5164 asc_dvc->cfg->disc_enable);
5165 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5166 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5167 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5168 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5171 * Set SCSI_CFG0 Microcode Default Value.
5173 * The microcode will set the SCSI_CFG0 register using this value
5174 * after it is started below.
5176 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5177 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5178 asc_dvc->chip_scsi_id);
5181 * Determine SCSI_CFG1 Microcode Default Value.
5183 * The microcode will set the SCSI_CFG1 register using this value
5184 * after it is started below.
5187 /* Read current SCSI_CFG1 Register value. */
5188 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5191 * If the internal narrow cable is reversed all of the SCSI_CTRL
5192 * register signals will be set. Check for and return an error if
5193 * this condition is found.
5195 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5196 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5201 * All kind of combinations of devices attached to one of four
5202 * connectors are acceptable except HVD device attached. For example,
5203 * LVD device can be attached to SE connector while SE device attached
5204 * to LVD connector. If LVD device attached to SE connector, it only
5205 * runs up to Ultra speed.
5207 * If an HVD device is attached to one of LVD connectors, return an
5208 * error. However, there is no way to detect HVD device attached to
5211 if (scsi_cfg1 & HVD) {
5212 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5217 * If either SE or LVD automatic termination control is enabled, then
5218 * set the termination value based on a table listed in a_condor.h.
5220 * If manual termination was specified with an EEPROM setting then
5221 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5222 * to be 'ored' into SCSI_CFG1.
5224 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5225 /* SE automatic termination control is enabled. */
5226 switch (scsi_cfg1 & C_DET_SE) {
5227 /* TERM_SE_HI: on, TERM_SE_LO: on */
5231 asc_dvc->cfg->termination |= TERM_SE;
5234 /* TERM_SE_HI: on, TERM_SE_LO: off */
5236 asc_dvc->cfg->termination |= TERM_SE_HI;
5241 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5242 /* LVD automatic termination control is enabled. */
5243 switch (scsi_cfg1 & C_DET_LVD) {
5244 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5248 asc_dvc->cfg->termination |= TERM_LVD;
5251 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5258 * Clear any set TERM_SE and TERM_LVD bits.
5260 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5263 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5265 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5268 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5269 * bits and set possibly modified termination control bits in the
5270 * Microcode SCSI_CFG1 Register Value.
5272 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5275 * Set SCSI_CFG1 Microcode Default Value
5277 * Set possibly modified termination control and reset DIS_TERM_DRV
5278 * bits in the Microcode SCSI_CFG1 Register Value.
5280 * The microcode will set the SCSI_CFG1 register using this value
5281 * after it is started below.
5283 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5286 * Set MEM_CFG Microcode Default Value
5288 * The microcode will set the MEM_CFG register using this value
5289 * after it is started below.
5291 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5294 * ASC-38C0800 has 16KB internal memory.
5296 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5297 BIOS_EN | RAM_SZ_16KB);
5300 * Set SEL_MASK Microcode Default Value
5302 * The microcode will set the SEL_MASK register using this value
5303 * after it is started below.
5305 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5306 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5308 AdvBuildCarrierFreelist(asc_dvc);
5311 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5314 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5315 if (!asc_dvc->icq_sp) {
5316 ASC_DBG(0, "Failed to get ICQ carrier\n");
5317 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5322 * Set RISC ICQ physical address start value.
5323 * carr_pa is LE, must be native before write
5325 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5328 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5330 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5331 if (!asc_dvc->irq_sp) {
5332 ASC_DBG(0, "Failed to get IRQ carrier\n");
5333 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5338 * Set RISC IRQ physical address start value.
5340 * carr_pa is LE, must be native before write *
5342 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5343 asc_dvc->carr_pending_cnt = 0;
5345 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5346 (ADV_INTR_ENABLE_HOST_INTR |
5347 ADV_INTR_ENABLE_GLOBAL_INTR));
5349 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5350 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5352 /* finally, finally, gentlemen, start your engine */
5353 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5356 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5357 * Resets should be performed. The RISC has to be running
5358 * to issue a SCSI Bus Reset.
5360 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5362 * If the BIOS Signature is present in memory, restore the
5363 * BIOS Handshake Configuration Table and do not perform
5366 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5369 * Restore per TID negotiated values.
5371 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5372 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5373 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5375 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5376 AdvWriteByteLram(iop_base,
5377 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5381 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5382 warn_code = ASC_WARN_BUSRESET_ERROR;
5391 * Initialize the ASC-38C1600.
5393 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5395 * For a non-fatal error return a warning code. If there are no warnings
5396 * then 0 is returned.
5398 * Needed after initialization for error recovery.
5400 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5402 const struct firmware *fw;
5403 const char fwname[] = "advansys/38C1600.bin";
5404 AdvPortAddr iop_base;
5412 unsigned long chksum;
5416 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5417 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5418 uchar max_cmd[ASC_MAX_TID + 1];
5420 /* If there is already an error, don't continue. */
5421 if (asc_dvc->err_code != 0) {
5426 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5428 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5429 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5434 iop_base = asc_dvc->iop_base;
5437 * Save the RISC memory BIOS region before writing the microcode.
5438 * The BIOS may already be loaded and using its RISC LRAM region
5439 * so its region must be saved and restored.
5441 * Note: This code makes the assumption, which is currently true,
5442 * that a chip reset does not clear RISC LRAM.
5444 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5445 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5450 * Save current per TID negotiated values.
5452 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5453 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5454 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5455 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5456 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5457 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5462 * RAM BIST (Built-In Self Test)
5464 * Address : I/O base + offset 0x38h register (byte).
5465 * Function: Bit 7-6(RW) : RAM mode
5466 * Normal Mode : 0x00
5467 * Pre-test Mode : 0x40
5468 * RAM Test Mode : 0x80
5470 * Bit 4(RO) : Done bit
5471 * Bit 3-0(RO) : Status
5473 * Int_RAM Error : 0x04
5478 * Note: RAM BIST code should be put right here, before loading the
5479 * microcode and after saving the RISC memory BIOS region.
5485 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5486 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5487 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5488 * to NORMAL_MODE, return an error too.
5490 for (i = 0; i < 2; i++) {
5491 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5492 mdelay(10); /* Wait for 10ms before reading back. */
5493 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5494 if ((byte & RAM_TEST_DONE) == 0
5495 || (byte & 0x0F) != PRE_TEST_VALUE) {
5496 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5500 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5501 mdelay(10); /* Wait for 10ms before reading back. */
5502 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5504 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5510 * LRAM Test - It takes about 1.5 ms to run through the test.
5512 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5513 * If Done bit not set or Status not 0, save register byte, set the
5514 * err_code, and return an error.
5516 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5517 mdelay(10); /* Wait for 10ms before checking status. */
5519 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5520 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5521 /* Get here if Done bit not set or Status not 0. */
5522 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5523 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5527 /* We need to reset back to normal mode after LRAM test passes. */
5528 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5530 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5532 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5534 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5538 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5540 release_firmware(fw);
5541 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5544 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5545 (fw->data[1] << 8) | fw->data[0];
5546 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5547 fw->size - 4, ADV_38C1600_MEMSIZE,
5549 release_firmware(fw);
5550 if (asc_dvc->err_code)
5554 * Restore the RISC memory BIOS region.
5556 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5557 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5562 * Calculate and write the microcode code checksum to the microcode
5563 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5565 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5566 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5568 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5569 for (word = begin_addr; word < end_addr; word += 2) {
5570 code_sum += AdvReadWordAutoIncLram(iop_base);
5572 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5575 * Read microcode version and date.
5577 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5578 asc_dvc->cfg->mcode_date);
5579 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5580 asc_dvc->cfg->mcode_version);
5583 * Set the chip type to indicate the ASC38C1600.
5585 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5588 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5589 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5590 * cable detection and then we are able to read C_DET[3:0].
5592 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5593 * Microcode Default Value' section below.
5595 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5596 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5597 scsi_cfg1 | DIS_TERM_DRV);
5600 * If the PCI Configuration Command Register "Parity Error Response
5601 * Control" Bit was clear (0), then set the microcode variable
5602 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5603 * to ignore DMA parity errors.
5605 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5606 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5607 word |= CONTROL_FLAG_IGNORE_PERR;
5608 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5612 * If the BIOS control flag AIPP (Asynchronous Information
5613 * Phase Protection) disable bit is not set, then set the firmware
5614 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5615 * AIPP checking and encoding.
5617 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5618 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5619 word |= CONTROL_FLAG_ENABLE_AIPP;
5620 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5624 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5625 * and START_CTL_TH [3:2].
5627 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5628 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5631 * Microcode operating variables for WDTR, SDTR, and command tag
5632 * queuing will be set in slave_configure() based on what a
5633 * device reports it is capable of in Inquiry byte 7.
5635 * If SCSI Bus Resets have been disabled, then directly set
5636 * SDTR and WDTR from the EEPROM configuration. This will allow
5637 * the BIOS and warm boot to work without a SCSI bus hang on
5638 * the Inquiry caused by host and target mismatched DTR values.
5639 * Without the SCSI Bus Reset, before an Inquiry a device can't
5640 * be assumed to be in Asynchronous, Narrow mode.
5642 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5643 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5644 asc_dvc->wdtr_able);
5645 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5646 asc_dvc->sdtr_able);
5650 * Set microcode operating variables for DISC and SDTR_SPEED1,
5651 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5652 * configuration values.
5654 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5655 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5656 * without determining here whether the device supports SDTR.
5658 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5659 asc_dvc->cfg->disc_enable);
5660 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5661 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5662 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5663 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5666 * Set SCSI_CFG0 Microcode Default Value.
5668 * The microcode will set the SCSI_CFG0 register using this value
5669 * after it is started below.
5671 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5672 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5673 asc_dvc->chip_scsi_id);
5676 * Calculate SCSI_CFG1 Microcode Default Value.
5678 * The microcode will set the SCSI_CFG1 register using this value
5679 * after it is started below.
5681 * Each ASC-38C1600 function has only two cable detect bits.
5682 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5684 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5687 * If the cable is reversed all of the SCSI_CTRL register signals
5688 * will be set. Check for and return an error if this condition is
5691 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5692 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5697 * Each ASC-38C1600 function has two connectors. Only an HVD device
5698 * can not be connected to either connector. An LVD device or SE device
5699 * may be connected to either connecor. If an SE device is connected,
5700 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5702 * If an HVD device is attached, return an error.
5704 if (scsi_cfg1 & HVD) {
5705 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5710 * Each function in the ASC-38C1600 uses only the SE cable detect and
5711 * termination because there are two connectors for each function. Each
5712 * function may use either LVD or SE mode. Corresponding the SE automatic
5713 * termination control EEPROM bits are used for each function. Each
5714 * function has its own EEPROM. If SE automatic control is enabled for
5715 * the function, then set the termination value based on a table listed
5718 * If manual termination is specified in the EEPROM for the function,
5719 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5720 * ready to be 'ored' into SCSI_CFG1.
5722 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5723 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5724 /* SE automatic termination control is enabled. */
5725 switch (scsi_cfg1 & C_DET_SE) {
5726 /* TERM_SE_HI: on, TERM_SE_LO: on */
5730 asc_dvc->cfg->termination |= TERM_SE;
5734 if (PCI_FUNC(pdev->devfn) == 0) {
5735 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5737 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5738 asc_dvc->cfg->termination |= TERM_SE_HI;
5745 * Clear any set TERM_SE bits.
5747 scsi_cfg1 &= ~TERM_SE;
5750 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5752 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5755 * Clear Big Endian and Terminator Polarity bits and set possibly
5756 * modified termination control bits in the Microcode SCSI_CFG1
5759 * Big Endian bit is not used even on big endian machines.
5761 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5764 * Set SCSI_CFG1 Microcode Default Value
5766 * Set possibly modified termination control bits in the Microcode
5767 * SCSI_CFG1 Register Value.
5769 * The microcode will set the SCSI_CFG1 register using this value
5770 * after it is started below.
5772 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5775 * Set MEM_CFG Microcode Default Value
5777 * The microcode will set the MEM_CFG register using this value
5778 * after it is started below.
5780 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5783 * ASC-38C1600 has 32KB internal memory.
5785 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5786 * out a special 16K Adv Library and Microcode version. After the issue
5787 * resolved, we should turn back to the 32K support. Both a_condor.h and
5788 * mcode.sas files also need to be updated.
5790 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5791 * BIOS_EN | RAM_SZ_32KB);
5793 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5794 BIOS_EN | RAM_SZ_16KB);
5797 * Set SEL_MASK Microcode Default Value
5799 * The microcode will set the SEL_MASK register using this value
5800 * after it is started below.
5802 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5803 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5805 AdvBuildCarrierFreelist(asc_dvc);
5808 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5810 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5811 if (!asc_dvc->icq_sp) {
5812 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5817 * Set RISC ICQ physical address start value. Initialize the
5818 * COMMA register to the same value otherwise the RISC will
5819 * prematurely detect a command is available.
5821 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5822 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5823 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5826 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5828 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5829 if (!asc_dvc->irq_sp) {
5830 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5835 * Set RISC IRQ physical address start value.
5837 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5838 asc_dvc->carr_pending_cnt = 0;
5840 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5841 (ADV_INTR_ENABLE_HOST_INTR |
5842 ADV_INTR_ENABLE_GLOBAL_INTR));
5843 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5844 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5846 /* finally, finally, gentlemen, start your engine */
5847 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5850 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5851 * Resets should be performed. The RISC has to be running
5852 * to issue a SCSI Bus Reset.
5854 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5856 * If the BIOS Signature is present in memory, restore the
5857 * per TID microcode operating variables.
5859 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5862 * Restore per TID negotiated values.
5864 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5865 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5866 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5867 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5869 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5870 AdvWriteByteLram(iop_base,
5871 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5875 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5876 warn_code = ASC_WARN_BUSRESET_ERROR;
5885 * Reset chip and SCSI Bus.
5888 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5889 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5891 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5894 ushort wdtr_able, sdtr_able, tagqng_able;
5895 ushort ppr_able = 0;
5896 uchar tid, max_cmd[ADV_MAX_TID + 1];
5897 AdvPortAddr iop_base;
5900 iop_base = asc_dvc->iop_base;
5903 * Save current per TID negotiated values.
5905 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5906 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5907 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5908 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5910 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5911 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5912 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5917 * Force the AdvInitAsc3550/38C0800Driver() function to
5918 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5919 * The initialization functions assumes a SCSI Bus Reset is not
5920 * needed if the BIOS signature word is present.
5922 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5923 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5926 * Stop chip and reset it.
5928 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5929 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5931 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5932 ADV_CTRL_REG_CMD_WR_IO_REG);
5935 * Reset Adv Library error code, if any, and try
5936 * re-initializing the chip.
5938 asc_dvc->err_code = 0;
5939 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5940 status = AdvInitAsc38C1600Driver(asc_dvc);
5941 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5942 status = AdvInitAsc38C0800Driver(asc_dvc);
5944 status = AdvInitAsc3550Driver(asc_dvc);
5947 /* Translate initialization return value to status value. */
5955 * Restore the BIOS signature word.
5957 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5960 * Restore per TID negotiated values.
5962 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5963 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5964 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5965 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5967 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5968 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5969 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5977 * adv_async_callback() - Adv Library asynchronous event callback function.
5979 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5982 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5984 * The firmware detected a SCSI Bus reset.
5986 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
5989 case ADV_ASYNC_RDMA_FAILURE:
5991 * Handle RDMA failure by resetting the SCSI Bus and
5992 * possibly the chip if it is unresponsive. Log the error
5993 * with a unique code.
5995 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
5996 AdvResetChipAndSB(adv_dvc_varp);
5999 case ADV_HOST_SCSI_BUS_RESET:
6001 * Host generated SCSI bus reset occurred.
6003 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6007 ASC_DBG(0, "unknown code 0x%x\n", code);
6013 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6015 * Callback function for the Wide SCSI Adv Library.
6017 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6019 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
6022 adv_sgblk_t *sgblkp;
6023 struct scsi_cmnd *scp;
6025 dma_addr_t sense_addr;
6027 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
6028 adv_dvc_varp, scsiqp);
6029 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6032 * Get the adv_req_t structure for the command that has been
6033 * completed. The adv_req_t structure actually contains the
6034 * completed ADV_SCSI_REQ_Q structure.
6036 srb_tag = le32_to_cpu(scsiqp->srb_tag);
6037 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
6039 ASC_DBG(1, "scp 0x%p\n", scp);
6042 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6045 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6047 reqp = (adv_req_t *)scp->host_scribble;
6048 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6050 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6054 * Remove backreferences to avoid duplicate
6055 * command completions.
6057 scp->host_scribble = NULL;
6060 ASC_STATS(boardp->shost, callback);
6061 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
6063 sense_addr = le32_to_cpu(scsiqp->sense_addr);
6064 dma_unmap_single(boardp->dev, sense_addr,
6065 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6068 * 'done_status' contains the command's ending status.
6070 switch (scsiqp->done_status) {
6072 ASC_DBG(2, "QD_NO_ERROR\n");
6076 * Check for an underrun condition.
6078 * If there was no error and an underrun condition, then
6079 * then return the number of underrun bytes.
6081 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6082 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6083 resid_cnt <= scsi_bufflen(scp)) {
6084 ASC_DBG(1, "underrun condition %lu bytes\n",
6086 scsi_set_resid(scp, resid_cnt);
6091 ASC_DBG(2, "QD_WITH_ERROR\n");
6092 switch (scsiqp->host_status) {
6093 case QHSTA_NO_ERROR:
6094 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6095 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6096 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6097 SCSI_SENSE_BUFFERSIZE);
6099 * Note: The 'status_byte()' macro used by
6100 * target drivers defined in scsi.h shifts the
6101 * status byte returned by host drivers right
6102 * by 1 bit. This is why target drivers also
6103 * use right shifted status byte definitions.
6104 * For instance target drivers use
6105 * CHECK_CONDITION, defined to 0x1, instead of
6106 * the SCSI defined check condition value of
6107 * 0x2. Host drivers are supposed to return
6108 * the status byte as it is defined by SCSI.
6110 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6111 STATUS_BYTE(scsiqp->scsi_status);
6113 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6118 /* Some other QHSTA error occurred. */
6119 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6120 scp->result = HOST_BYTE(DID_BAD_TARGET);
6125 case QD_ABORTED_BY_HOST:
6126 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6128 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6132 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6134 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6139 * If the 'init_tidmask' bit isn't already set for the target and the
6140 * current request finished normally, then set the bit for the target
6141 * to indicate that a device is present.
6143 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6144 scsiqp->done_status == QD_NO_ERROR &&
6145 scsiqp->host_status == QHSTA_NO_ERROR) {
6146 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6152 * Free all 'adv_sgblk_t' structures allocated for the request.
6154 while ((sgblkp = reqp->sgblkp) != NULL) {
6155 /* Remove 'sgblkp' from the request list. */
6156 reqp->sgblkp = sgblkp->next_sgblkp;
6158 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6162 ASC_DBG(1, "done\n");
6166 * Adv Library Interrupt Service Routine
6168 * This function is called by a driver's interrupt service routine.
6169 * The function disables and re-enables interrupts.
6171 * When a microcode idle command is completed, the ADV_DVC_VAR
6172 * 'idle_cmd_done' field is set to ADV_TRUE.
6174 * Note: AdvISR() can be called when interrupts are disabled or even
6175 * when there is no hardware interrupt condition present. It will
6176 * always check for completed idle commands and microcode requests.
6177 * This is an important feature that shouldn't be changed because it
6178 * allows commands to be completed from polling mode loops.
6181 * ADV_TRUE(1) - interrupt was pending
6182 * ADV_FALSE(0) - no interrupt was pending
6184 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6186 AdvPortAddr iop_base;
6189 ADV_CARR_T *free_carrp;
6190 __le32 irq_next_vpa;
6191 ADV_SCSI_REQ_Q *scsiq;
6194 iop_base = asc_dvc->iop_base;
6196 /* Reading the register clears the interrupt. */
6197 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6199 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6200 ADV_INTR_STATUS_INTRC)) == 0) {
6205 * Notify the driver of an asynchronous microcode condition by
6206 * calling the adv_async_callback function. The function
6207 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6209 if (int_stat & ADV_INTR_STATUS_INTRB) {
6212 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6214 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6215 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6216 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6217 asc_dvc->carr_pending_cnt != 0) {
6218 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6220 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6221 AdvWriteByteRegister(iop_base,
6228 adv_async_callback(asc_dvc, intrb_code);
6232 * Check if the IRQ stopper carrier contains a completed request.
6234 while (((irq_next_vpa =
6235 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6237 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6238 * The RISC will have set 'areq_vpa' to a virtual address.
6240 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6241 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6242 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6243 * in AdvExeScsiQueue().
6245 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6246 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6247 asc_dvc->irq_sp, pa_offset);
6248 reqp = adv_get_reqp(asc_dvc, pa_offset);
6249 scsiq = &reqp->scsi_req_q;
6252 * Request finished with good status and the queue was not
6253 * DMAed to host memory by the firmware. Set all status fields
6254 * to indicate good status.
6256 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6257 scsiq->done_status = QD_NO_ERROR;
6258 scsiq->host_status = scsiq->scsi_status = 0;
6259 scsiq->data_cnt = 0L;
6263 * Advance the stopper pointer to the next carrier
6264 * ignoring the lower four bits. Free the previous
6267 free_carrp = asc_dvc->irq_sp;
6268 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6269 ASC_GET_CARRP(irq_next_vpa));
6271 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
6272 asc_dvc->carr_freelist = free_carrp;
6273 asc_dvc->carr_pending_cnt--;
6275 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6278 * Clear request microcode control flag.
6283 * Notify the driver of the completed request by passing
6284 * the ADV_SCSI_REQ_Q pointer to its callback function.
6286 scsiq->a_flag |= ADV_SCSIQ_DONE;
6287 adv_isr_callback(asc_dvc, scsiq);
6289 * Note: After the driver callback function is called, 'scsiq'
6290 * can no longer be referenced.
6292 * Fall through and continue processing other completed
6299 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6301 if (asc_dvc->err_code == 0) {
6302 asc_dvc->err_code = err_code;
6303 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6309 static void AscAckInterrupt(PortAddr iop_base)
6317 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6318 if (loop++ > 0x7FFF) {
6321 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6323 AscReadLramByte(iop_base,
6324 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6325 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6326 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6327 AscSetChipStatus(iop_base, CIW_INT_ACK);
6329 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6330 AscSetChipStatus(iop_base, CIW_INT_ACK);
6335 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6338 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6340 const uchar *period_table;
6345 period_table = asc_dvc->sdtr_period_tbl;
6346 max_index = (int)asc_dvc->max_sdtr_index;
6347 min_index = (int)asc_dvc->min_sdtr_index;
6348 if ((syn_time <= period_table[max_index])) {
6349 for (i = min_index; i < (max_index - 1); i++) {
6350 if (syn_time <= period_table[i]) {
6354 return (uchar)max_index;
6356 return (uchar)(max_index + 1);
6361 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6364 uchar sdtr_period_index;
6367 iop_base = asc_dvc->iop_base;
6368 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6369 sdtr_buf.msg_len = MS_SDTR_LEN;
6370 sdtr_buf.msg_req = EXTENDED_SDTR;
6371 sdtr_buf.xfer_period = sdtr_period;
6372 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6373 sdtr_buf.req_ack_offset = sdtr_offset;
6374 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6375 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6376 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6378 sizeof(EXT_MSG) >> 1);
6379 return ((sdtr_period_index << 4) | sdtr_offset);
6381 sdtr_buf.req_ack_offset = 0;
6382 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6384 sizeof(EXT_MSG) >> 1);
6390 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6393 uchar sdtr_period_ix;
6395 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6396 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6398 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6402 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6404 ASC_SCSI_BIT_ID_TYPE org_id;
6408 AscSetBank(iop_base, 1);
6409 org_id = AscReadChipDvcID(iop_base);
6410 for (i = 0; i <= ASC_MAX_TID; i++) {
6411 if (org_id == (0x01 << i))
6414 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6415 AscWriteChipDvcID(iop_base, id);
6416 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6417 AscSetBank(iop_base, 0);
6418 AscSetChipSyn(iop_base, sdtr_data);
6419 if (AscGetChipSyn(iop_base) != sdtr_data) {
6425 AscSetBank(iop_base, 1);
6426 AscWriteChipDvcID(iop_base, org_id);
6427 AscSetBank(iop_base, 0);
6431 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6433 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6434 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6437 static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6443 ushort int_halt_code;
6444 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6445 ASC_SCSI_BIT_ID_TYPE target_id;
6452 uchar q_cntl, tid_no;
6456 struct asc_board *boardp;
6458 BUG_ON(!asc_dvc->drv_ptr);
6459 boardp = asc_dvc->drv_ptr;
6461 iop_base = asc_dvc->iop_base;
6462 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6464 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6465 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6466 target_ix = AscReadLramByte(iop_base,
6467 (ushort)(halt_q_addr +
6468 (ushort)ASC_SCSIQ_B_TARGET_IX));
6469 q_cntl = AscReadLramByte(iop_base,
6470 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6471 tid_no = ASC_TIX_TO_TID(target_ix);
6472 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6473 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6474 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6478 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6479 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6480 AscSetChipSDTR(iop_base, 0, tid_no);
6481 boardp->sdtr_data[tid_no] = 0;
6483 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6485 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6486 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6487 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6488 boardp->sdtr_data[tid_no] = asyn_sdtr;
6490 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6492 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6493 AscMemWordCopyPtrFromLram(iop_base,
6496 sizeof(EXT_MSG) >> 1);
6498 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6499 ext_msg.msg_req == EXTENDED_SDTR &&
6500 ext_msg.msg_len == MS_SDTR_LEN) {
6502 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6504 sdtr_accept = false;
6505 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6507 if ((ext_msg.xfer_period <
6508 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6509 || (ext_msg.xfer_period >
6510 asc_dvc->sdtr_period_tbl[asc_dvc->
6512 sdtr_accept = false;
6513 ext_msg.xfer_period =
6514 asc_dvc->sdtr_period_tbl[asc_dvc->
6519 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6520 ext_msg.req_ack_offset);
6521 if ((sdtr_data == 0xFF)) {
6523 q_cntl |= QC_MSG_OUT;
6524 asc_dvc->init_sdtr &= ~target_id;
6525 asc_dvc->sdtr_done &= ~target_id;
6526 AscSetChipSDTR(iop_base, asyn_sdtr,
6528 boardp->sdtr_data[tid_no] = asyn_sdtr;
6531 if (ext_msg.req_ack_offset == 0) {
6533 q_cntl &= ~QC_MSG_OUT;
6534 asc_dvc->init_sdtr &= ~target_id;
6535 asc_dvc->sdtr_done &= ~target_id;
6536 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6538 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6539 q_cntl &= ~QC_MSG_OUT;
6540 asc_dvc->sdtr_done |= target_id;
6541 asc_dvc->init_sdtr |= target_id;
6542 asc_dvc->pci_fix_asyn_xfer &=
6545 AscCalSDTRData(asc_dvc,
6546 ext_msg.xfer_period,
6549 AscSetChipSDTR(iop_base, sdtr_data,
6551 boardp->sdtr_data[tid_no] = sdtr_data;
6553 q_cntl |= QC_MSG_OUT;
6554 AscMsgOutSDTR(asc_dvc,
6555 ext_msg.xfer_period,
6556 ext_msg.req_ack_offset);
6557 asc_dvc->pci_fix_asyn_xfer &=
6560 AscCalSDTRData(asc_dvc,
6561 ext_msg.xfer_period,
6564 AscSetChipSDTR(iop_base, sdtr_data,
6566 boardp->sdtr_data[tid_no] = sdtr_data;
6567 asc_dvc->sdtr_done |= target_id;
6568 asc_dvc->init_sdtr |= target_id;
6572 AscWriteLramByte(iop_base,
6573 (ushort)(halt_q_addr +
6574 (ushort)ASC_SCSIQ_B_CNTL),
6576 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6578 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6579 ext_msg.msg_req == EXTENDED_WDTR &&
6580 ext_msg.msg_len == MS_WDTR_LEN) {
6582 ext_msg.wdtr_width = 0;
6583 AscMemWordCopyPtrToLram(iop_base,
6586 sizeof(EXT_MSG) >> 1);
6587 q_cntl |= QC_MSG_OUT;
6588 AscWriteLramByte(iop_base,
6589 (ushort)(halt_q_addr +
6590 (ushort)ASC_SCSIQ_B_CNTL),
6592 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6596 ext_msg.msg_type = MESSAGE_REJECT;
6597 AscMemWordCopyPtrToLram(iop_base,
6600 sizeof(EXT_MSG) >> 1);
6601 q_cntl |= QC_MSG_OUT;
6602 AscWriteLramByte(iop_base,
6603 (ushort)(halt_q_addr +
6604 (ushort)ASC_SCSIQ_B_CNTL),
6606 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6609 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6611 q_cntl |= QC_REQ_SENSE;
6613 if ((asc_dvc->init_sdtr & target_id) != 0) {
6615 asc_dvc->sdtr_done &= ~target_id;
6617 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6618 q_cntl |= QC_MSG_OUT;
6619 AscMsgOutSDTR(asc_dvc,
6621 sdtr_period_tbl[(sdtr_data >> 4) &
6625 (uchar)(sdtr_data & (uchar)
6626 ASC_SYN_MAX_OFFSET));
6629 AscWriteLramByte(iop_base,
6630 (ushort)(halt_q_addr +
6631 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6633 tag_code = AscReadLramByte(iop_base,
6634 (ushort)(halt_q_addr + (ushort)
6635 ASC_SCSIQ_B_TAG_CODE));
6637 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6638 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6641 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6642 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6645 AscWriteLramByte(iop_base,
6646 (ushort)(halt_q_addr +
6647 (ushort)ASC_SCSIQ_B_TAG_CODE),
6650 q_status = AscReadLramByte(iop_base,
6651 (ushort)(halt_q_addr + (ushort)
6652 ASC_SCSIQ_B_STATUS));
6653 q_status |= (QS_READY | QS_BUSY);
6654 AscWriteLramByte(iop_base,
6655 (ushort)(halt_q_addr +
6656 (ushort)ASC_SCSIQ_B_STATUS),
6659 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6660 scsi_busy &= ~target_id;
6661 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6663 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6665 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6667 AscMemWordCopyPtrFromLram(iop_base,
6670 sizeof(EXT_MSG) >> 1);
6672 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6673 (out_msg.msg_len == MS_SDTR_LEN) &&
6674 (out_msg.msg_req == EXTENDED_SDTR)) {
6676 asc_dvc->init_sdtr &= ~target_id;
6677 asc_dvc->sdtr_done &= ~target_id;
6678 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6679 boardp->sdtr_data[tid_no] = asyn_sdtr;
6681 q_cntl &= ~QC_MSG_OUT;
6682 AscWriteLramByte(iop_base,
6683 (ushort)(halt_q_addr +
6684 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6685 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6687 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6689 scsi_status = AscReadLramByte(iop_base,
6690 (ushort)((ushort)halt_q_addr +
6692 ASC_SCSIQ_SCSI_STATUS));
6694 AscReadLramByte(iop_base,
6695 (ushort)((ushort)ASC_QADR_BEG +
6696 (ushort)target_ix));
6697 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6699 scsi_busy = AscReadLramByte(iop_base,
6700 (ushort)ASCV_SCSIBUSY_B);
6701 scsi_busy |= target_id;
6702 AscWriteLramByte(iop_base,
6703 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6704 asc_dvc->queue_full_or_busy |= target_id;
6706 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6707 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6709 asc_dvc->max_dvc_qng[tid_no] =
6712 AscWriteLramByte(iop_base,
6714 ASCV_MAX_DVC_QNG_BEG
6720 * Set the device queue depth to the
6721 * number of active requests when the
6722 * QUEUE FULL condition was encountered.
6724 boardp->queue_full |= target_id;
6725 boardp->queue_full_cnt[tid_no] =
6730 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6733 #if CC_VERY_LONG_SG_LIST
6734 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6738 uchar first_sg_wk_q_no;
6739 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6740 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6741 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6742 ushort sg_list_dwords;
6743 ushort sg_entry_cnt;
6747 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6748 if (q_no == ASC_QLINK_END)
6751 q_addr = ASC_QNO_TO_QADDR(q_no);
6754 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6755 * structure pointer using a macro provided by the driver.
6756 * The ASC_SCSI_REQ pointer provides a pointer to the
6757 * host ASC_SG_HEAD structure.
6759 /* Read request's SRB pointer. */
6760 scsiq = (ASC_SCSI_Q *)
6761 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6764 ASC_SCSIQ_D_SRBPTR))));
6767 * Get request's first and working SG queue.
6769 sg_wk_q_no = AscReadLramByte(iop_base,
6771 ASC_SCSIQ_B_SG_WK_QP));
6773 first_sg_wk_q_no = AscReadLramByte(iop_base,
6775 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6778 * Reset request's working SG queue back to the
6781 AscWriteLramByte(iop_base,
6783 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6786 sg_head = scsiq->sg_head;
6789 * Set sg_entry_cnt to the number of SG elements
6790 * that will be completed on this interrupt.
6792 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6793 * SG elements. The data_cnt and data_addr fields which
6794 * add 1 to the SG element capacity are not used when
6795 * restarting SG handling after a halt.
6797 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6798 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6801 * Keep track of remaining number of SG elements that
6802 * will need to be handled on the next interrupt.
6804 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6806 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6807 scsiq->remain_sg_entry_cnt = 0;
6811 * Copy SG elements into the list of allocated SG queues.
6813 * Last index completed is saved in scsiq->next_sg_index.
6815 next_qp = first_sg_wk_q_no;
6816 q_addr = ASC_QNO_TO_QADDR(next_qp);
6817 scsi_sg_q.sg_head_qp = q_no;
6818 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6819 for (i = 0; i < sg_head->queue_cnt; i++) {
6820 scsi_sg_q.seq_no = i + 1;
6821 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6822 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6823 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6825 * After very first SG queue RISC FW uses next
6826 * SG queue first element then checks sg_list_cnt
6827 * against zero and then decrements, so set
6828 * sg_list_cnt 1 less than number of SG elements
6831 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6832 scsi_sg_q.sg_cur_list_cnt =
6833 ASC_SG_LIST_PER_Q - 1;
6836 * This is the last SG queue in the list of
6837 * allocated SG queues. If there are more
6838 * SG elements than will fit in the allocated
6839 * queues, then set the QCSG_SG_XFER_MORE flag.
6841 if (scsiq->remain_sg_entry_cnt != 0) {
6842 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6844 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6846 /* equals sg_entry_cnt * 2 */
6847 sg_list_dwords = sg_entry_cnt << 1;
6848 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6849 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6853 scsi_sg_q.q_no = next_qp;
6854 AscMemWordCopyPtrToLram(iop_base,
6855 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6856 (uchar *)&scsi_sg_q,
6857 sizeof(ASC_SG_LIST_Q) >> 1);
6859 AscMemDWordCopyPtrToLram(iop_base,
6860 q_addr + ASC_SGQ_LIST_BEG,
6862 sg_list[scsiq->next_sg_index],
6865 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6868 * If the just completed SG queue contained the
6869 * last SG element, then no more SG queues need
6872 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6876 next_qp = AscReadLramByte(iop_base,
6879 q_addr = ASC_QNO_TO_QADDR(next_qp);
6883 * Clear the halt condition so the RISC will be restarted
6886 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6889 #endif /* CC_VERY_LONG_SG_LIST */
6895 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6897 * Calling/Exit State:
6901 * Input an ASC_QDONE_INFO structure from the chip
6904 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6909 AscSetChipLramAddr(iop_base, s_addr);
6910 for (i = 0; i < 2 * words; i += 2) {
6914 word = inpw(iop_base + IOP_RAM_DATA);
6915 inbuf[i] = word & 0xff;
6916 inbuf[i + 1] = (word >> 8) & 0xff;
6918 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6922 _AscCopyLramScsiDoneQ(PortAddr iop_base,
6924 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
6929 DvcGetQinfo(iop_base,
6930 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6932 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6934 _val = AscReadLramWord(iop_base,
6935 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6936 scsiq->q_status = (uchar)_val;
6937 scsiq->q_no = (uchar)(_val >> 8);
6938 _val = AscReadLramWord(iop_base,
6939 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6940 scsiq->cntl = (uchar)_val;
6941 sg_queue_cnt = (uchar)(_val >> 8);
6942 _val = AscReadLramWord(iop_base,
6944 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6945 scsiq->sense_len = (uchar)_val;
6946 scsiq->extra_bytes = (uchar)(_val >> 8);
6949 * Read high word of remain bytes from alternate location.
6951 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6954 ASC_SCSIQ_W_ALT_DC1)))
6957 * Read low word of remain bytes from original location.
6959 scsiq->remain_bytes += AscReadLramWord(iop_base,
6960 (ushort)(q_addr + (ushort)
6961 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6963 scsiq->remain_bytes &= max_dma_count;
6964 return sg_queue_cnt;
6968 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6970 * Interrupt callback function for the Narrow SCSI Asc Library.
6972 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6974 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6976 struct scsi_cmnd *scp;
6978 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
6979 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6982 * Decrease the srb_tag by 1 to find the SCSI command
6984 srb_tag = qdonep->d2.srb_tag - 1;
6985 scp = scsi_host_find_tag(boardp->shost, srb_tag);
6989 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6991 ASC_STATS(boardp->shost, callback);
6993 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
6994 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6996 * 'qdonep' contains the command's ending status.
6998 switch (qdonep->d3.done_stat) {
7000 ASC_DBG(2, "QD_NO_ERROR\n");
7004 * Check for an underrun condition.
7006 * If there was no error and an underrun condition, then
7007 * return the number of underrun bytes.
7009 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7010 qdonep->remain_bytes <= scsi_bufflen(scp)) {
7011 ASC_DBG(1, "underrun condition %u bytes\n",
7012 (unsigned)qdonep->remain_bytes);
7013 scsi_set_resid(scp, qdonep->remain_bytes);
7018 ASC_DBG(2, "QD_WITH_ERROR\n");
7019 switch (qdonep->d3.host_stat) {
7020 case QHSTA_NO_ERROR:
7021 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7022 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7023 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7024 SCSI_SENSE_BUFFERSIZE);
7026 * Note: The 'status_byte()' macro used by
7027 * target drivers defined in scsi.h shifts the
7028 * status byte returned by host drivers right
7029 * by 1 bit. This is why target drivers also
7030 * use right shifted status byte definitions.
7031 * For instance target drivers use
7032 * CHECK_CONDITION, defined to 0x1, instead of
7033 * the SCSI defined check condition value of
7034 * 0x2. Host drivers are supposed to return
7035 * the status byte as it is defined by SCSI.
7037 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7038 STATUS_BYTE(qdonep->d3.scsi_stat);
7040 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7045 /* QHSTA error occurred */
7046 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7047 scp->result = HOST_BYTE(DID_BAD_TARGET);
7052 case QD_ABORTED_BY_HOST:
7053 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7055 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7057 STATUS_BYTE(qdonep->d3.scsi_stat);
7061 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7063 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7065 STATUS_BYTE(qdonep->d3.scsi_stat);
7070 * If the 'init_tidmask' bit isn't already set for the target and the
7071 * current request finished normally, then set the bit for the target
7072 * to indicate that a device is present.
7074 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7075 qdonep->d3.done_stat == QD_NO_ERROR &&
7076 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7077 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7083 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7092 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7093 ASC_SCSI_BIT_ID_TYPE target_id;
7097 uchar cur_target_qng;
7098 ASC_QDONE_INFO scsiq_buf;
7099 ASC_QDONE_INFO *scsiq;
7102 iop_base = asc_dvc->iop_base;
7104 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7105 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7106 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7107 next_qp = AscReadLramByte(iop_base,
7108 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7109 if (next_qp != ASC_QLINK_END) {
7110 AscPutVarDoneQTail(iop_base, next_qp);
7111 q_addr = ASC_QNO_TO_QADDR(next_qp);
7112 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7113 asc_dvc->max_dma_count);
7114 AscWriteLramByte(iop_base,
7116 (ushort)ASC_SCSIQ_B_STATUS),
7118 q_status & (uchar)~(QS_READY |
7120 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7121 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7122 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7124 sg_list_qp = next_qp;
7125 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7126 sg_list_qp = AscReadLramByte(iop_base,
7130 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7131 if (sg_list_qp == ASC_QLINK_END) {
7132 AscSetLibErrorCode(asc_dvc,
7133 ASCQ_ERR_SG_Q_LINKS);
7134 scsiq->d3.done_stat = QD_WITH_ERROR;
7135 scsiq->d3.host_stat =
7136 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7137 goto FATAL_ERR_QDONE;
7139 AscWriteLramByte(iop_base,
7140 (ushort)(sg_q_addr + (ushort)
7141 ASC_SCSIQ_B_STATUS),
7144 n_q_used = sg_queue_cnt + 1;
7145 AscPutVarDoneQTail(iop_base, sg_list_qp);
7147 if (asc_dvc->queue_full_or_busy & target_id) {
7148 cur_target_qng = AscReadLramByte(iop_base,
7154 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7155 scsi_busy = AscReadLramByte(iop_base, (ushort)
7157 scsi_busy &= ~target_id;
7158 AscWriteLramByte(iop_base,
7159 (ushort)ASCV_SCSIBUSY_B,
7161 asc_dvc->queue_full_or_busy &= ~target_id;
7164 if (asc_dvc->cur_total_qng >= n_q_used) {
7165 asc_dvc->cur_total_qng -= n_q_used;
7166 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7167 asc_dvc->cur_dvc_qng[tid_no]--;
7170 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7171 scsiq->d3.done_stat = QD_WITH_ERROR;
7172 goto FATAL_ERR_QDONE;
7174 if ((scsiq->d2.srb_tag == 0UL) ||
7175 ((scsiq->q_status & QS_ABORTED) != 0)) {
7177 } else if (scsiq->q_status == QS_DONE) {
7179 * This is also curious.
7180 * false_overrun will _always_ be set to 'false'
7182 false_overrun = false;
7183 if (scsiq->extra_bytes != 0) {
7184 scsiq->remain_bytes += scsiq->extra_bytes;
7186 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7187 if (scsiq->d3.host_stat ==
7188 QHSTA_M_DATA_OVER_RUN) {
7190 cntl & (QC_DATA_IN | QC_DATA_OUT))
7192 scsiq->d3.done_stat =
7194 scsiq->d3.host_stat =
7196 } else if (false_overrun) {
7197 scsiq->d3.done_stat =
7199 scsiq->d3.host_stat =
7202 } else if (scsiq->d3.host_stat ==
7203 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7204 AscStopChip(iop_base);
7205 AscSetChipControl(iop_base,
7206 (uchar)(CC_SCSI_RESET
7209 AscSetChipControl(iop_base, CC_HALT);
7210 AscSetChipStatus(iop_base,
7211 CIW_CLR_SCSI_RESET_INT);
7212 AscSetChipStatus(iop_base, 0);
7213 AscSetChipControl(iop_base, 0);
7216 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7217 asc_isr_callback(asc_dvc, scsiq);
7219 if ((AscReadLramByte(iop_base,
7220 (ushort)(q_addr + (ushort)
7223 asc_dvc->unit_not_ready &= ~target_id;
7224 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7225 asc_dvc->start_motor &=
7232 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7234 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7235 asc_isr_callback(asc_dvc, scsiq);
7243 static int AscISR(ASC_DVC_VAR *asc_dvc)
7245 ASC_CS_TYPE chipstat;
7247 ushort saved_ram_addr;
7249 uchar saved_ctrl_reg;
7254 iop_base = asc_dvc->iop_base;
7255 int_pending = ASC_FALSE;
7257 if (AscIsIntPending(iop_base) == 0)
7260 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7263 if (asc_dvc->in_critical_cnt != 0) {
7264 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7267 if (asc_dvc->is_in_int) {
7268 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7271 asc_dvc->is_in_int = true;
7272 ctrl_reg = AscGetChipControl(iop_base);
7273 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7274 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7275 chipstat = AscGetChipStatus(iop_base);
7276 if (chipstat & CSW_SCSI_RESET_LATCH) {
7277 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7279 int_pending = ASC_TRUE;
7280 asc_dvc->sdtr_done = 0;
7281 saved_ctrl_reg &= (uchar)(~CC_HALT);
7282 while ((AscGetChipStatus(iop_base) &
7283 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7286 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7287 AscSetChipControl(iop_base, CC_HALT);
7288 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7289 AscSetChipStatus(iop_base, 0);
7290 chipstat = AscGetChipStatus(iop_base);
7293 saved_ram_addr = AscGetChipLramAddr(iop_base);
7294 host_flag = AscReadLramByte(iop_base,
7296 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7297 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7298 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7299 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7300 AscAckInterrupt(iop_base);
7301 int_pending = ASC_TRUE;
7302 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7303 AscIsrChipHalted(asc_dvc);
7304 saved_ctrl_reg &= (uchar)(~CC_HALT);
7306 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7308 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7313 AscIsrQDone(asc_dvc)) == 1) {
7316 } while (status == 0x11);
7318 if ((status & 0x80) != 0)
7319 int_pending = ASC_ERROR;
7322 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7323 AscSetChipLramAddr(iop_base, saved_ram_addr);
7324 AscSetChipControl(iop_base, saved_ctrl_reg);
7325 asc_dvc->is_in_int = false;
7332 * Reset the host associated with the command 'scp'.
7334 * This function runs its own thread. Interrupts must be blocked but
7335 * sleeping is allowed and no locking other than for host structures is
7336 * required. Returns SUCCESS or FAILED.
7338 static int advansys_reset(struct scsi_cmnd *scp)
7340 struct Scsi_Host *shost = scp->device->host;
7341 struct asc_board *boardp = shost_priv(shost);
7342 unsigned long flags;
7346 ASC_DBG(1, "0x%p\n", scp);
7348 ASC_STATS(shost, reset);
7350 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
7352 if (ASC_NARROW_BOARD(boardp)) {
7353 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7355 /* Reset the chip and SCSI bus. */
7356 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7357 status = AscInitAsc1000Driver(asc_dvc);
7359 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7360 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7361 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
7362 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7365 } else if (status) {
7366 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
7369 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7373 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7376 * If the suggest reset bus flags are set, then reset the bus.
7377 * Otherwise only reset the device.
7379 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7382 * Reset the chip and SCSI bus.
7384 ASC_DBG(1, "before AdvResetChipAndSB()\n");
7385 switch (AdvResetChipAndSB(adv_dvc)) {
7387 scmd_printk(KERN_INFO, scp, "SCSI host reset "
7392 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
7396 spin_lock_irqsave(shost->host_lock, flags);
7398 spin_unlock_irqrestore(shost->host_lock, flags);
7401 ASC_DBG(1, "ret %d\n", ret);
7407 * advansys_biosparam()
7409 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7410 * support is enabled for a drive.
7412 * ip (information pointer) is an int array with the following definition:
7418 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7419 sector_t capacity, int ip[])
7421 struct asc_board *boardp = shost_priv(sdev->host);
7423 ASC_DBG(1, "begin\n");
7424 ASC_STATS(sdev->host, biosparam);
7425 if (ASC_NARROW_BOARD(boardp)) {
7426 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7427 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7435 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7436 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7444 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7445 ASC_DBG(1, "end\n");
7450 * First-level interrupt handler.
7452 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7454 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7456 struct Scsi_Host *shost = dev_id;
7457 struct asc_board *boardp = shost_priv(shost);
7458 irqreturn_t result = IRQ_NONE;
7460 ASC_DBG(2, "boardp 0x%p\n", boardp);
7461 spin_lock(shost->host_lock);
7462 if (ASC_NARROW_BOARD(boardp)) {
7463 if (AscIsIntPending(shost->io_port)) {
7464 result = IRQ_HANDLED;
7465 ASC_STATS(shost, interrupt);
7466 ASC_DBG(1, "before AscISR()\n");
7467 AscISR(&boardp->dvc_var.asc_dvc_var);
7470 ASC_DBG(1, "before AdvISR()\n");
7471 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7472 result = IRQ_HANDLED;
7473 ASC_STATS(shost, interrupt);
7476 spin_unlock(shost->host_lock);
7478 ASC_DBG(1, "end\n");
7482 static bool AscHostReqRiscHalt(PortAddr iop_base)
7486 uchar saved_stop_code;
7488 if (AscIsChipHalted(iop_base))
7490 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7491 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7492 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7494 if (AscIsChipHalted(iop_base)) {
7499 } while (count++ < 20);
7500 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7505 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7509 if (AscHostReqRiscHalt(iop_base)) {
7510 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7511 AscStartChip(iop_base);
7516 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7518 char type = sdev->type;
7519 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7521 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7523 if (asc_dvc->init_sdtr & tid_bits)
7526 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7527 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7529 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7530 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7531 (type == TYPE_ROM) || (type == TYPE_TAPE))
7532 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7534 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7535 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7536 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7540 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7542 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7543 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7545 if (sdev->lun == 0) {
7546 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7547 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7548 asc_dvc->init_sdtr |= tid_bit;
7550 asc_dvc->init_sdtr &= ~tid_bit;
7553 if (orig_init_sdtr != asc_dvc->init_sdtr)
7554 AscAsyncFix(asc_dvc, sdev);
7557 if (sdev->tagged_supported) {
7558 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7559 if (sdev->lun == 0) {
7560 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7561 asc_dvc->use_tagged_qng |= tid_bit;
7563 scsi_change_queue_depth(sdev,
7564 asc_dvc->max_dvc_qng[sdev->id]);
7567 if (sdev->lun == 0) {
7568 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7569 asc_dvc->use_tagged_qng &= ~tid_bit;
7573 if ((sdev->lun == 0) &&
7574 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7575 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7576 asc_dvc->cfg->disc_enable);
7577 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7578 asc_dvc->use_tagged_qng);
7579 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7580 asc_dvc->cfg->can_tagged_qng);
7582 asc_dvc->max_dvc_qng[sdev->id] =
7583 asc_dvc->cfg->max_tag_qng[sdev->id];
7584 AscWriteLramByte(asc_dvc->iop_base,
7585 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7586 asc_dvc->max_dvc_qng[sdev->id]);
7593 * If the EEPROM enabled WDTR for the device and the device supports wide
7594 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7595 * write the new value to the microcode.
7598 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7600 unsigned short cfg_word;
7601 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7602 if ((cfg_word & tidmask) != 0)
7605 cfg_word |= tidmask;
7606 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7609 * Clear the microcode SDTR and WDTR negotiation done indicators for
7610 * the target to cause it to negotiate with the new setting set above.
7611 * WDTR when accepted causes the target to enter asynchronous mode, so
7612 * SDTR must be negotiated.
7614 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7615 cfg_word &= ~tidmask;
7616 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7617 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7618 cfg_word &= ~tidmask;
7619 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7623 * Synchronous Transfers
7625 * If the EEPROM enabled SDTR for the device and the device
7626 * supports synchronous transfers, then turn on the device's
7627 * 'sdtr_able' bit. Write the new value to the microcode.
7630 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7632 unsigned short cfg_word;
7633 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7634 if ((cfg_word & tidmask) != 0)
7637 cfg_word |= tidmask;
7638 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7641 * Clear the microcode "SDTR negotiation" done indicator for the
7642 * target to cause it to negotiate with the new setting set above.
7644 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7645 cfg_word &= ~tidmask;
7646 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7650 * PPR (Parallel Protocol Request) Capable
7652 * If the device supports DT mode, then it must be PPR capable.
7653 * The PPR message will be used in place of the SDTR and WDTR
7654 * messages to negotiate synchronous speed and offset, transfer
7655 * width, and protocol options.
7657 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7658 AdvPortAddr iop_base, unsigned short tidmask)
7660 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7661 adv_dvc->ppr_able |= tidmask;
7662 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7666 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7668 AdvPortAddr iop_base = adv_dvc->iop_base;
7669 unsigned short tidmask = 1 << sdev->id;
7671 if (sdev->lun == 0) {
7673 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7674 * is enabled in the EEPROM and the device supports the
7675 * feature, then enable it in the microcode.
7678 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7679 advansys_wide_enable_wdtr(iop_base, tidmask);
7680 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7681 advansys_wide_enable_sdtr(iop_base, tidmask);
7682 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7683 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7686 * Tag Queuing is disabled for the BIOS which runs in polled
7687 * mode and would see no benefit from Tag Queuing. Also by
7688 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7689 * bugs will at least work with the BIOS.
7691 if ((adv_dvc->tagqng_able & tidmask) &&
7692 sdev->tagged_supported) {
7693 unsigned short cfg_word;
7694 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7695 cfg_word |= tidmask;
7696 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7698 AdvWriteByteLram(iop_base,
7699 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7700 adv_dvc->max_dvc_qng);
7704 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7705 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
7709 * Set the number of commands to queue per device for the
7710 * specified host adapter.
7712 static int advansys_slave_configure(struct scsi_device *sdev)
7714 struct asc_board *boardp = shost_priv(sdev->host);
7716 if (ASC_NARROW_BOARD(boardp))
7717 advansys_narrow_slave_configure(sdev,
7718 &boardp->dvc_var.asc_dvc_var);
7720 advansys_wide_slave_configure(sdev,
7721 &boardp->dvc_var.adv_dvc_var);
7726 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7728 struct asc_board *board = shost_priv(scp->device->host);
7729 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7730 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7731 dma_cache_sync(board->dev, scp->sense_buffer,
7732 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7733 return cpu_to_le32(scp->SCp.dma_handle);
7736 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7737 struct asc_scsi_q *asc_scsi_q)
7739 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7743 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7746 * Set the srb_tag to the command tag + 1, as
7747 * srb_tag '0' is used internally by the chip.
7749 srb_tag = scp->request->tag + 1;
7750 asc_scsi_q->q2.srb_tag = srb_tag;
7753 * Build the ASC_SCSI_Q request.
7755 asc_scsi_q->cdbptr = &scp->cmnd[0];
7756 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7757 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7758 asc_scsi_q->q1.target_lun = scp->device->lun;
7759 asc_scsi_q->q2.target_ix =
7760 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7761 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
7762 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7765 * If there are any outstanding requests for the current target,
7766 * then every 255th request send an ORDERED request. This heuristic
7767 * tries to retain the benefit of request sorting while preventing
7768 * request starvation. 255 is the max number of tags or pending commands
7769 * a device may have outstanding.
7771 * The request count is incremented below for every successfully
7775 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7776 (boardp->reqcnt[scp->device->id] % 255) == 0) {
7777 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
7779 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
7782 /* Build ASC_SCSI_Q */
7783 use_sg = scsi_dma_map(scp);
7786 struct scatterlist *slp;
7787 struct asc_sg_head *asc_sg_head;
7789 if (use_sg > scp->device->host->sg_tablesize) {
7790 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7791 "sg_tablesize %d\n", use_sg,
7792 scp->device->host->sg_tablesize);
7793 scsi_dma_unmap(scp);
7794 scp->result = HOST_BYTE(DID_ERROR);
7798 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7799 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7801 scsi_dma_unmap(scp);
7802 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7806 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7807 asc_scsi_q->sg_head = asc_sg_head;
7808 asc_scsi_q->q1.data_cnt = 0;
7809 asc_scsi_q->q1.data_addr = 0;
7810 /* This is a byte value, otherwise it would need to be swapped. */
7811 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7812 ASC_STATS_ADD(scp->device->host, xfer_elem,
7813 asc_sg_head->entry_cnt);
7816 * Convert scatter-gather list into ASC_SG_HEAD list.
7818 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7819 asc_sg_head->sg_list[sgcnt].addr =
7820 cpu_to_le32(sg_dma_address(slp));
7821 asc_sg_head->sg_list[sgcnt].bytes =
7822 cpu_to_le32(sg_dma_len(slp));
7823 ASC_STATS_ADD(scp->device->host, xfer_sect,
7824 DIV_ROUND_UP(sg_dma_len(slp), 512));
7828 ASC_STATS(scp->device->host, xfer_cnt);
7830 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7831 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7837 * Build scatter-gather list for Adv Library (Wide Board).
7839 * Additional ADV_SG_BLOCK structures will need to be allocated
7840 * if the total number of scatter-gather elements exceeds
7841 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7842 * assumed to be physically contiguous.
7845 * ADV_SUCCESS(1) - SG List successfully created
7846 * ADV_ERROR(-1) - SG List creation failed
7849 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7850 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
7852 adv_sgblk_t *sgblkp, *prev_sgblkp;
7853 struct scatterlist *slp;
7855 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7856 dma_addr_t sgblk_paddr;
7859 slp = scsi_sglist(scp);
7860 sg_elem_cnt = use_sg;
7862 prev_sg_block = NULL;
7863 reqp->sgblkp = NULL;
7867 * Allocate a 'adv_sgblk_t' structure from the board free
7868 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7869 * (15) scatter-gather elements.
7871 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7874 ASC_DBG(1, "no free adv_sgblk_t\n");
7875 ASC_STATS(scp->device->host, adv_build_nosg);
7878 * Allocation failed. Free 'adv_sgblk_t' structures
7879 * already allocated for the request.
7881 while ((sgblkp = reqp->sgblkp) != NULL) {
7882 /* Remove 'sgblkp' from the request list. */
7883 reqp->sgblkp = sgblkp->next_sgblkp;
7884 sgblkp->next_sgblkp = NULL;
7885 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7890 /* Complete 'adv_sgblk_t' board allocation. */
7891 sgblkp->sg_addr = sgblk_paddr;
7892 sgblkp->next_sgblkp = NULL;
7893 sg_block = &sgblkp->sg_block;
7896 * Check if this is the first 'adv_sgblk_t' for the
7899 if (reqp->sgblkp == NULL) {
7900 /* Request's first scatter-gather block. */
7901 reqp->sgblkp = sgblkp;
7904 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7907 scsiqp->sg_list_ptr = sg_block;
7908 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
7910 /* Request's second or later scatter-gather block. */
7911 prev_sgblkp->next_sgblkp = sgblkp;
7914 * Point the previous ADV_SG_BLOCK structure to
7915 * the newly allocated ADV_SG_BLOCK structure.
7917 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
7920 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7921 sg_block->sg_list[i].sg_addr =
7922 cpu_to_le32(sg_dma_address(slp));
7923 sg_block->sg_list[i].sg_count =
7924 cpu_to_le32(sg_dma_len(slp));
7925 ASC_STATS_ADD(scp->device->host, xfer_sect,
7926 DIV_ROUND_UP(sg_dma_len(slp), 512));
7928 if (--sg_elem_cnt == 0) {
7930 * Last ADV_SG_BLOCK and scatter-gather entry.
7932 sg_block->sg_cnt = i + 1;
7933 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7938 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7939 prev_sg_block = sg_block;
7940 prev_sgblkp = sgblkp;
7945 * Build a request structure for the Adv Library (Wide Board).
7947 * If an adv_req_t can not be allocated to issue the request,
7948 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7950 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
7951 * microcode for DMA addresses or math operations are byte swapped
7952 * to little-endian order.
7955 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7956 adv_req_t **adv_reqpp)
7958 u32 srb_tag = scp->request->tag;
7960 ADV_SCSI_REQ_Q *scsiqp;
7963 dma_addr_t sense_addr;
7966 * Allocate an adv_req_t structure from the board to execute
7969 reqp = &boardp->adv_reqp[srb_tag];
7970 if (reqp->cmndp && reqp->cmndp != scp ) {
7971 ASC_DBG(1, "no free adv_req_t\n");
7972 ASC_STATS(scp->device->host, adv_build_noreq);
7976 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7978 scsiqp = &reqp->scsi_req_q;
7981 * Initialize the structure.
7983 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
7986 * Set the srb_tag to the command tag.
7988 scsiqp->srb_tag = srb_tag;
7991 * Set 'host_scribble' to point to the adv_req_t structure.
7994 scp->host_scribble = (void *)reqp;
7997 * Build the ADV_SCSI_REQ_Q request.
8000 /* Set CDB length and copy it to the request structure. */
8001 scsiqp->cdb_len = scp->cmd_len;
8002 /* Copy first 12 CDB bytes to cdb[]. */
8003 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
8004 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8005 if (scp->cmd_len > 12) {
8006 int cdb16_len = scp->cmd_len - 12;
8008 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
8011 scsiqp->target_id = scp->device->id;
8012 scsiqp->target_lun = scp->device->lun;
8014 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
8015 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
8016 scsiqp->sense_addr = cpu_to_le32(sense_addr);
8017 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
8019 /* Build ADV_SCSI_REQ_Q */
8021 use_sg = scsi_dma_map(scp);
8023 /* Zero-length transfer */
8024 reqp->sgblkp = NULL;
8025 scsiqp->data_cnt = 0;
8027 scsiqp->data_addr = 0;
8028 scsiqp->sg_list_ptr = NULL;
8029 scsiqp->sg_real_addr = 0;
8031 if (use_sg > ADV_MAX_SG_LIST) {
8032 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8033 "ADV_MAX_SG_LIST %d\n", use_sg,
8034 scp->device->host->sg_tablesize);
8035 scsi_dma_unmap(scp);
8036 scp->result = HOST_BYTE(DID_ERROR);
8038 scp->host_scribble = NULL;
8043 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8045 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
8046 if (ret != ADV_SUCCESS) {
8047 scsi_dma_unmap(scp);
8048 scp->result = HOST_BYTE(DID_ERROR);
8050 scp->host_scribble = NULL;
8055 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
8058 ASC_STATS(scp->device->host, xfer_cnt);
8060 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8061 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8068 static int AscSgListToQueue(int sg_list)
8072 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8073 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8075 return n_sg_list_qs + 1;
8079 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8083 ASC_SCSI_BIT_ID_TYPE target_id;
8086 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8087 tid_no = ASC_TIX_TO_TID(target_ix);
8088 if ((asc_dvc->unit_not_ready & target_id) ||
8089 (asc_dvc->queue_full_or_busy & target_id)) {
8093 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8094 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8096 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8097 (uint) ASC_MIN_FREE_Q;
8099 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8100 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8101 if (asc_dvc->cur_dvc_qng[tid_no] >=
8102 asc_dvc->max_dvc_qng[tid_no]) {
8108 if ((n_qs > asc_dvc->last_q_shortage)
8109 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8110 asc_dvc->last_q_shortage = n_qs;
8116 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8122 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8123 q_status = (uchar)AscReadLramByte(iop_base,
8125 ASC_SCSIQ_B_STATUS));
8126 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8127 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8129 return ASC_QLINK_END;
8133 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8137 for (i = 0; i < n_free_q; i++) {
8138 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8139 if (free_q_head == ASC_QLINK_END)
8147 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8149 * Calling/Exit State:
8153 * Output an ASC_SCSI_Q structure to the chip
8156 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8160 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8161 AscSetChipLramAddr(iop_base, s_addr);
8162 for (i = 0; i < 2 * words; i += 2) {
8163 if (i == 4 || i == 20) {
8166 outpw(iop_base + IOP_RAM_DATA,
8167 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
8171 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8176 uchar syn_period_ix;
8180 iop_base = asc_dvc->iop_base;
8181 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8182 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8183 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8184 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8186 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8187 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8188 AscMsgOutSDTR(asc_dvc,
8189 asc_dvc->sdtr_period_tbl[syn_period_ix],
8191 scsiq->q1.cntl |= QC_MSG_OUT;
8193 q_addr = ASC_QNO_TO_QADDR(q_no);
8194 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
8195 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8197 scsiq->q1.status = QS_FREE;
8198 AscMemWordCopyPtrToLram(iop_base,
8199 q_addr + ASC_SCSIQ_CDB_BEG,
8200 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8202 DvcPutScsiQ(iop_base,
8203 q_addr + ASC_SCSIQ_CPY_BEG,
8204 (uchar *)&scsiq->q1.cntl,
8205 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8206 AscWriteLramWord(iop_base,
8207 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8208 (ushort)(((ushort)scsiq->q1.
8209 q_no << 8) | (ushort)QS_READY));
8214 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8218 ASC_SG_HEAD *sg_head;
8219 ASC_SG_LIST_Q scsi_sg_q;
8220 __le32 saved_data_addr;
8221 __le32 saved_data_cnt;
8223 ushort sg_list_dwords;
8225 ushort sg_entry_cnt;
8229 iop_base = asc_dvc->iop_base;
8230 sg_head = scsiq->sg_head;
8231 saved_data_addr = scsiq->q1.data_addr;
8232 saved_data_cnt = scsiq->q1.data_cnt;
8233 scsiq->q1.data_addr = sg_head->sg_list[0].addr;
8234 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
8235 #if CC_VERY_LONG_SG_LIST
8237 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8238 * then not all SG elements will fit in the allocated queues.
8239 * The rest of the SG elements will be copied when the RISC
8240 * completes the SG elements that fit and halts.
8242 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8244 * Set sg_entry_cnt to be the number of SG elements that
8245 * will fit in the allocated SG queues. It is minus 1, because
8246 * the first SG element is handled above. ASC_MAX_SG_LIST is
8247 * already inflated by 1 to account for this. For example it
8248 * may be 50 which is 1 + 7 queues * 7 SG elements.
8250 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8253 * Keep track of remaining number of SG elements that will
8254 * need to be handled from a_isr.c.
8256 scsiq->remain_sg_entry_cnt =
8257 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8259 #endif /* CC_VERY_LONG_SG_LIST */
8261 * Set sg_entry_cnt to be the number of SG elements that
8262 * will fit in the allocated SG queues. It is minus 1, because
8263 * the first SG element is handled above.
8265 sg_entry_cnt = sg_head->entry_cnt - 1;
8266 #if CC_VERY_LONG_SG_LIST
8268 #endif /* CC_VERY_LONG_SG_LIST */
8269 if (sg_entry_cnt != 0) {
8270 scsiq->q1.cntl |= QC_SG_HEAD;
8271 q_addr = ASC_QNO_TO_QADDR(q_no);
8273 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8274 scsi_sg_q.sg_head_qp = q_no;
8275 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8276 for (i = 0; i < sg_head->queue_cnt; i++) {
8277 scsi_sg_q.seq_no = i + 1;
8278 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8279 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8280 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8282 scsi_sg_q.sg_list_cnt =
8284 scsi_sg_q.sg_cur_list_cnt =
8287 scsi_sg_q.sg_list_cnt =
8288 ASC_SG_LIST_PER_Q - 1;
8289 scsi_sg_q.sg_cur_list_cnt =
8290 ASC_SG_LIST_PER_Q - 1;
8293 #if CC_VERY_LONG_SG_LIST
8295 * This is the last SG queue in the list of
8296 * allocated SG queues. If there are more
8297 * SG elements than will fit in the allocated
8298 * queues, then set the QCSG_SG_XFER_MORE flag.
8300 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8301 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8303 #endif /* CC_VERY_LONG_SG_LIST */
8304 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8305 #if CC_VERY_LONG_SG_LIST
8307 #endif /* CC_VERY_LONG_SG_LIST */
8308 sg_list_dwords = sg_entry_cnt << 1;
8310 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8311 scsi_sg_q.sg_cur_list_cnt =
8314 scsi_sg_q.sg_list_cnt =
8316 scsi_sg_q.sg_cur_list_cnt =
8321 next_qp = AscReadLramByte(iop_base,
8324 scsi_sg_q.q_no = next_qp;
8325 q_addr = ASC_QNO_TO_QADDR(next_qp);
8326 AscMemWordCopyPtrToLram(iop_base,
8327 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8328 (uchar *)&scsi_sg_q,
8329 sizeof(ASC_SG_LIST_Q) >> 1);
8330 AscMemDWordCopyPtrToLram(iop_base,
8331 q_addr + ASC_SGQ_LIST_BEG,
8335 sg_index += ASC_SG_LIST_PER_Q;
8336 scsiq->next_sg_index = sg_index;
8339 scsiq->q1.cntl &= ~QC_SG_HEAD;
8341 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8342 scsiq->q1.data_addr = saved_data_addr;
8343 scsiq->q1.data_cnt = saved_data_cnt;
8348 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8357 iop_base = asc_dvc->iop_base;
8358 target_ix = scsiq->q2.target_ix;
8359 tid_no = ASC_TIX_TO_TID(target_ix);
8361 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8362 if (n_q_required > 1) {
8363 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8364 (uchar)n_q_required);
8365 if (next_qp != ASC_QLINK_END) {
8366 asc_dvc->last_q_shortage = 0;
8367 scsiq->sg_head->queue_cnt = n_q_required - 1;
8368 scsiq->q1.q_no = free_q_head;
8369 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8372 } else if (n_q_required == 1) {
8373 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8374 if (next_qp != ASC_QLINK_END) {
8375 scsiq->q1.q_no = free_q_head;
8376 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8380 AscPutVarFreeQHead(iop_base, next_qp);
8381 asc_dvc->cur_total_qng += n_q_required;
8382 asc_dvc->cur_dvc_qng[tid_no]++;
8387 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8388 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8407 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8412 bool disable_syn_offset_one_fix;
8415 ushort sg_entry_cnt = 0;
8416 ushort sg_entry_cnt_minus_one = 0;
8423 ASC_SG_HEAD *sg_head;
8424 unsigned long data_cnt;
8426 iop_base = asc_dvc->iop_base;
8427 sg_head = scsiq->sg_head;
8428 if (asc_dvc->err_code != 0)
8431 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8432 scsiq->q1.extra_bytes = 0;
8435 target_ix = scsiq->q2.target_ix;
8436 tid_no = ASC_TIX_TO_TID(target_ix);
8438 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8439 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8440 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8441 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8442 AscMsgOutSDTR(asc_dvc,
8444 sdtr_period_tbl[(sdtr_data >> 4) &
8448 (uchar)(sdtr_data & (uchar)
8449 ASC_SYN_MAX_OFFSET));
8450 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8453 if (asc_dvc->in_critical_cnt != 0) {
8454 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8457 asc_dvc->in_critical_cnt++;
8458 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8459 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8460 asc_dvc->in_critical_cnt--;
8463 #if !CC_VERY_LONG_SG_LIST
8464 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8465 asc_dvc->in_critical_cnt--;
8468 #endif /* !CC_VERY_LONG_SG_LIST */
8469 if (sg_entry_cnt == 1) {
8470 scsiq->q1.data_addr = sg_head->sg_list[0].addr;
8471 scsiq->q1.data_cnt = sg_head->sg_list[0].bytes;
8472 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8474 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8476 scsi_cmd = scsiq->cdbptr[0];
8477 disable_syn_offset_one_fix = false;
8478 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8479 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8480 if (scsiq->q1.cntl & QC_SG_HEAD) {
8482 for (i = 0; i < sg_entry_cnt; i++) {
8483 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8487 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8489 if (data_cnt != 0UL) {
8490 if (data_cnt < 512UL) {
8491 disable_syn_offset_one_fix = true;
8493 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8496 _syn_offset_one_disable_cmd[i];
8497 if (disable_cmd == 0xFF) {
8500 if (scsi_cmd == disable_cmd) {
8501 disable_syn_offset_one_fix =
8509 if (disable_syn_offset_one_fix) {
8510 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
8511 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8512 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8514 scsiq->q2.tag_code &= 0x27;
8516 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8517 if (asc_dvc->bug_fix_cntl) {
8518 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8519 if ((scsi_cmd == READ_6) ||
8520 (scsi_cmd == READ_10)) {
8521 addr = le32_to_cpu(sg_head->
8523 [sg_entry_cnt_minus_one].
8525 le32_to_cpu(sg_head->
8527 [sg_entry_cnt_minus_one].
8530 (uchar)((ushort)addr & 0x0003);
8531 if ((extra_bytes != 0)
8535 ASC_TAG_FLAG_EXTRA_BYTES)
8537 scsiq->q2.tag_code |=
8538 ASC_TAG_FLAG_EXTRA_BYTES;
8539 scsiq->q1.extra_bytes =
8542 le32_to_cpu(sg_head->
8544 [sg_entry_cnt_minus_one].
8546 data_cnt -= extra_bytes;
8549 [sg_entry_cnt_minus_one].
8551 cpu_to_le32(data_cnt);
8556 sg_head->entry_to_copy = sg_head->entry_cnt;
8557 #if CC_VERY_LONG_SG_LIST
8559 * Set the sg_entry_cnt to the maximum possible. The rest of
8560 * the SG elements will be copied when the RISC completes the
8561 * SG elements that fit and halts.
8563 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8564 sg_entry_cnt = ASC_MAX_SG_LIST;
8566 #endif /* CC_VERY_LONG_SG_LIST */
8567 n_q_required = AscSgListToQueue(sg_entry_cnt);
8568 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8569 (uint) n_q_required)
8570 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8572 AscSendScsiQueue(asc_dvc, scsiq,
8573 n_q_required)) == 1) {
8574 asc_dvc->in_critical_cnt--;
8579 if (asc_dvc->bug_fix_cntl) {
8580 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8581 if ((scsi_cmd == READ_6) ||
8582 (scsi_cmd == READ_10)) {
8584 le32_to_cpu(scsiq->q1.data_addr) +
8585 le32_to_cpu(scsiq->q1.data_cnt);
8587 (uchar)((ushort)addr & 0x0003);
8588 if ((extra_bytes != 0)
8592 ASC_TAG_FLAG_EXTRA_BYTES)
8595 le32_to_cpu(scsiq->q1.
8597 if (((ushort)data_cnt & 0x01FF)
8599 scsiq->q2.tag_code |=
8600 ASC_TAG_FLAG_EXTRA_BYTES;
8601 data_cnt -= extra_bytes;
8602 scsiq->q1.data_cnt =
8605 scsiq->q1.extra_bytes =
8613 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8614 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8615 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8616 n_q_required)) == 1) {
8617 asc_dvc->in_critical_cnt--;
8622 asc_dvc->in_critical_cnt--;
8627 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8629 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8630 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8631 * RISC to notify it a new command is ready to be executed.
8633 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8634 * set to SCSI_MAX_RETRY.
8636 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8637 * for DMA addresses or math operations are byte swapped to little-endian
8641 * ADV_SUCCESS(1) - The request was successfully queued.
8642 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8643 * request completes.
8644 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8647 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
8649 AdvPortAddr iop_base;
8650 ADV_CARR_T *new_carrp;
8651 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
8654 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8656 if (scsiq->target_id > ADV_MAX_TID) {
8657 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8658 scsiq->done_status = QD_WITH_ERROR;
8662 iop_base = asc_dvc->iop_base;
8665 * Allocate a carrier ensuring at least one carrier always
8666 * remains on the freelist and initialize fields.
8668 new_carrp = adv_get_next_carrier(asc_dvc);
8670 ASC_DBG(1, "No free carriers\n");
8674 asc_dvc->carr_pending_cnt++;
8677 * Clear the ADV_SCSI_REQ_Q done flag.
8679 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
8681 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8682 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8683 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
8685 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
8686 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8689 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8690 * the microcode. The newly allocated stopper will become the new
8693 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
8696 * Set the 'next_vpa' pointer for the old stopper to be the
8697 * physical address of the new stopper. The RISC can only
8698 * follow physical addresses.
8700 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8703 * Set the host adapter stopper pointer to point to the new carrier.
8705 asc_dvc->icq_sp = new_carrp;
8707 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8708 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8710 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8712 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8713 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8715 * Clear the tickle value. In the ASC-3550 the RISC flag
8716 * command 'clr_tickle_a' does not work unless the host
8719 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8722 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8724 * Notify the RISC a carrier is ready by writing the physical
8725 * address of the new carrier stopper to the COMMA register.
8727 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8728 le32_to_cpu(new_carrp->carr_pa));
8735 * Execute a single 'Scsi_Cmnd'.
8737 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8740 struct asc_board *boardp = shost_priv(scp->device->host);
8742 ASC_DBG(1, "scp 0x%p\n", scp);
8744 if (ASC_NARROW_BOARD(boardp)) {
8745 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8746 struct asc_scsi_q asc_scsi_q;
8748 /* asc_build_req() can not return ASC_BUSY. */
8749 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8750 if (ret == ASC_ERROR) {
8751 ASC_STATS(scp->device->host, build_error);
8755 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8756 kfree(asc_scsi_q.sg_head);
8757 err_code = asc_dvc->err_code;
8759 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8760 adv_req_t *adv_reqp;
8762 switch (adv_build_req(boardp, scp, &adv_reqp)) {
8764 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8767 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8769 * The asc_stats fields 'adv_build_noreq' and
8770 * 'adv_build_nosg' count wide board busy conditions.
8771 * They are updated in adv_build_req and
8772 * adv_get_sglist, respectively.
8777 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8778 ASC_STATS(scp->device->host, build_error);
8782 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
8783 err_code = adv_dvc->err_code;
8788 ASC_STATS(scp->device->host, exe_noerror);
8790 * Increment monotonically increasing per device
8791 * successful request counter. Wrapping doesn't matter.
8793 boardp->reqcnt[scp->device->id]++;
8794 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8797 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
8798 ASC_STATS(scp->device->host, exe_busy);
8801 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8802 "err_code 0x%x\n", err_code);
8803 ASC_STATS(scp->device->host, exe_error);
8804 scp->result = HOST_BYTE(DID_ERROR);
8807 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8808 "err_code 0x%x\n", err_code);
8809 ASC_STATS(scp->device->host, exe_unknown);
8810 scp->result = HOST_BYTE(DID_ERROR);
8814 ASC_DBG(1, "end\n");
8819 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8821 * This function always returns 0. Command return status is saved
8822 * in the 'scp' result field.
8825 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
8827 struct Scsi_Host *shost = scp->device->host;
8828 int asc_res, result = 0;
8830 ASC_STATS(shost, queuecommand);
8831 scp->scsi_done = done;
8833 asc_res = asc_execute_scsi_cmnd(scp);
8839 result = SCSI_MLQUEUE_HOST_BUSY;
8850 static DEF_SCSI_QCMD(advansys_queuecommand)
8852 static ushort AscGetEisaChipCfg(PortAddr iop_base)
8854 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8855 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8856 return inpw(eisa_cfg_iop);
8860 * Return the BIOS address of the adapter at the specified
8861 * I/O port and with the specified bus type.
8863 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8864 unsigned short bus_type)
8866 unsigned short cfg_lsw;
8867 unsigned short bios_addr;
8870 * The PCI BIOS is re-located by the motherboard BIOS. Because
8871 * of this the driver can not determine where a PCI BIOS is
8872 * loaded and executes.
8874 if (bus_type & ASC_IS_PCI)
8877 if ((bus_type & ASC_IS_EISA) != 0) {
8878 cfg_lsw = AscGetEisaChipCfg(iop_base);
8880 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8884 cfg_lsw = AscGetChipCfgLsw(iop_base);
8887 * ISA PnP uses the top bit as the 32K BIOS flag
8889 if (bus_type == ASC_IS_ISAPNP)
8891 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8895 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
8899 if (AscGetChipScsiID(iop_base) == new_host_id) {
8900 return (new_host_id);
8902 cfg_lsw = AscGetChipCfgLsw(iop_base);
8904 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8905 AscSetChipCfgLsw(iop_base, cfg_lsw);
8906 return (AscGetChipScsiID(iop_base));
8909 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
8913 AscSetBank(iop_base, 1);
8914 sc = inp(iop_base + IOP_REG_SC);
8915 AscSetBank(iop_base, 0);
8919 static unsigned char AscGetChipVersion(PortAddr iop_base,
8920 unsigned short bus_type)
8922 if (bus_type & ASC_IS_EISA) {
8924 unsigned char revision;
8925 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8926 (PortAddr) ASC_EISA_REV_IOP_MASK;
8927 revision = inp(eisa_iop);
8928 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
8930 return AscGetChipVerNo(iop_base);
8934 static void AscEnableIsaDma(uchar dma_channel)
8936 if (dma_channel < 4) {
8937 outp(0x000B, (ushort)(0xC0 | dma_channel));
8938 outp(0x000A, dma_channel);
8939 } else if (dma_channel < 8) {
8940 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8941 outp(0x00D4, (ushort)(dma_channel - 4));
8944 #endif /* CONFIG_ISA */
8946 static int AscStopQueueExe(PortAddr iop_base)
8950 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8951 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8952 ASC_STOP_REQ_RISC_STOP);
8954 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8955 ASC_STOP_ACK_RISC_STOP) {
8959 } while (count++ < 20);
8964 static unsigned int AscGetMaxDmaCount(ushort bus_type)
8966 if (bus_type & ASC_IS_ISA)
8967 return ASC_MAX_ISA_DMA_COUNT;
8968 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8969 return ASC_MAX_VL_DMA_COUNT;
8970 return ASC_MAX_PCI_DMA_COUNT;
8974 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
8978 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8979 if (channel == 0x03)
8981 else if (channel == 0x00)
8983 return (channel + 4);
8986 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
8991 if ((dma_channel >= 5) && (dma_channel <= 7)) {
8992 if (dma_channel == 7)
8995 value = dma_channel - 4;
8996 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
8998 AscSetChipCfgLsw(iop_base, cfg_lsw);
8999 return (AscGetIsaDmaChannel(iop_base));
9004 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
9008 AscSetBank(iop_base, 1);
9009 speed_value = AscReadChipDmaSpeed(iop_base);
9010 speed_value &= 0x07;
9011 AscSetBank(iop_base, 0);
9015 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
9017 speed_value &= 0x07;
9018 AscSetBank(iop_base, 1);
9019 AscWriteChipDmaSpeed(iop_base, speed_value);
9020 AscSetBank(iop_base, 0);
9021 return AscGetIsaDmaSpeed(iop_base);
9023 #endif /* CONFIG_ISA */
9025 static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
9031 iop_base = asc_dvc->iop_base;
9032 asc_dvc->err_code = 0;
9033 if ((asc_dvc->bus_type &
9034 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9035 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
9037 AscSetChipControl(iop_base, CC_HALT);
9038 AscSetChipStatus(iop_base, 0);
9039 asc_dvc->bug_fix_cntl = 0;
9040 asc_dvc->pci_fix_asyn_xfer = 0;
9041 asc_dvc->pci_fix_asyn_xfer_always = 0;
9042 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
9043 asc_dvc->sdtr_done = 0;
9044 asc_dvc->cur_total_qng = 0;
9045 asc_dvc->is_in_int = false;
9046 asc_dvc->in_critical_cnt = 0;
9047 asc_dvc->last_q_shortage = 0;
9048 asc_dvc->use_tagged_qng = 0;
9049 asc_dvc->no_scam = 0;
9050 asc_dvc->unit_not_ready = 0;
9051 asc_dvc->queue_full_or_busy = 0;
9052 asc_dvc->redo_scam = 0;
9054 asc_dvc->min_sdtr_index = 0;
9055 asc_dvc->cfg->can_tagged_qng = 0;
9056 asc_dvc->cfg->cmd_qng_enabled = 0;
9057 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9058 asc_dvc->init_sdtr = 0;
9059 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9060 asc_dvc->scsi_reset_wait = 3;
9061 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9062 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9063 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9064 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9065 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
9066 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9067 asc_dvc->cfg->chip_version = chip_version;
9068 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
9069 asc_dvc->max_sdtr_index = 7;
9070 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9071 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9072 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
9073 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
9074 asc_dvc->max_sdtr_index = 15;
9075 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9076 AscSetExtraControl(iop_base,
9077 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9078 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9079 AscSetExtraControl(iop_base,
9080 (SEC_ACTIVE_NEGATE |
9081 SEC_ENABLE_FILTER));
9084 if (asc_dvc->bus_type == ASC_IS_PCI) {
9085 AscSetExtraControl(iop_base,
9086 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9089 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9091 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9092 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9093 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9094 asc_dvc->bus_type = ASC_IS_ISAPNP;
9096 asc_dvc->cfg->isa_dma_channel =
9097 (uchar)AscGetIsaDmaChannel(iop_base);
9099 #endif /* CONFIG_ISA */
9100 for (i = 0; i <= ASC_MAX_TID; i++) {
9101 asc_dvc->cur_dvc_qng[i] = 0;
9102 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9103 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9104 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9105 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
9109 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9113 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9114 unsigned char read_back;
9115 AscSetChipEEPCmd(iop_base, cmd_reg);
9117 read_back = AscGetChipEEPCmd(iop_base);
9118 if (read_back == cmd_reg)
9124 static void AscWaitEEPRead(void)
9129 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
9134 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9136 cmd_reg = addr | ASC_EEP_CMD_READ;
9137 AscWriteEEPCmdReg(iop_base, cmd_reg);
9139 read_wval = AscGetChipEEPData(iop_base);
9144 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9152 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9155 wbuf = (ushort *)cfg_buf;
9157 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9158 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9159 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9162 if (bus_type & ASC_IS_VL) {
9163 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9164 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9166 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9167 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9169 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9170 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9171 if (s_addr <= uchar_end_in_config) {
9173 * Swap all char fields - must unswap bytes already swapped
9174 * by AscReadEEPWord().
9176 *wbuf = le16_to_cpu(wval);
9178 /* Don't swap word field at the end - cntl field. */
9181 sum += wval; /* Checksum treats all EEPROM data as words. */
9184 * Read the checksum word which will be compared against 'sum'
9185 * by the caller. Word field already swapped.
9187 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9191 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
9198 iop_base = asc_dvc->iop_base;
9200 q_addr = ASC_QNO_TO_QADDR(241);
9201 saved_word = AscReadLramWord(iop_base, q_addr);
9202 AscSetChipLramAddr(iop_base, q_addr);
9203 AscSetChipLramData(iop_base, 0x55AA);
9205 AscSetChipLramAddr(iop_base, q_addr);
9206 if (AscGetChipLramData(iop_base) == 0x55AA) {
9208 AscWriteLramWord(iop_base, q_addr, saved_word);
9213 static void AscWaitEEPWrite(void)
9218 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9225 AscSetChipEEPData(iop_base, data_reg);
9227 read_back = AscGetChipEEPData(iop_base);
9228 if (read_back == data_reg) {
9231 if (retry++ > ASC_EEP_MAX_RETRY) {
9237 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9241 read_wval = AscReadEEPWord(iop_base, addr);
9242 if (read_wval != word_val) {
9243 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9245 AscWriteEEPDataReg(iop_base, word_val);
9247 AscWriteEEPCmdReg(iop_base,
9248 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9250 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9252 return (AscReadEEPWord(iop_base, addr));
9257 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9267 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9269 wbuf = (ushort *)cfg_buf;
9272 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9273 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9275 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9279 if (bus_type & ASC_IS_VL) {
9280 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9281 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9283 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9284 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9286 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9287 if (s_addr <= uchar_end_in_config) {
9289 * This is a char field. Swap char fields before they are
9290 * swapped again by AscWriteEEPWord().
9292 word = cpu_to_le16(*wbuf);
9294 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9298 /* Don't swap word field at the end - cntl field. */
9300 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9304 sum += *wbuf; /* Checksum calculated from word values. */
9306 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9308 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9312 /* Read EEPROM back again. */
9313 wbuf = (ushort *)cfg_buf;
9315 * Read two config words; Byte-swapping done by AscReadEEPWord().
9317 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9318 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9322 if (bus_type & ASC_IS_VL) {
9323 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9324 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9326 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9327 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9329 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9330 if (s_addr <= uchar_end_in_config) {
9332 * Swap all char fields. Must unswap bytes already swapped
9333 * by AscReadEEPWord().
9336 le16_to_cpu(AscReadEEPWord
9337 (iop_base, (uchar)s_addr));
9339 /* Don't swap word field at the end - cntl field. */
9340 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9342 if (*wbuf != word) {
9346 /* Read checksum; Byte swapping not needed. */
9347 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9353 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9361 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9365 if (++retry > ASC_EEP_MAX_RETRY) {
9372 static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9374 ASCEEP_CONFIG eep_config_buf;
9375 ASCEEP_CONFIG *eep_config;
9379 ushort cfg_msw, cfg_lsw;
9383 iop_base = asc_dvc->iop_base;
9385 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9386 AscStopQueueExe(iop_base);
9387 if ((AscStopChip(iop_base)) ||
9388 (AscGetChipScsiCtrl(iop_base) != 0)) {
9389 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9390 AscResetChipAndScsiBus(asc_dvc);
9391 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9393 if (!AscIsChipHalted(iop_base)) {
9394 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9397 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9398 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9399 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9402 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9403 cfg_msw = AscGetChipCfgMsw(iop_base);
9404 cfg_lsw = AscGetChipCfgLsw(iop_base);
9405 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9406 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9407 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9408 AscSetChipCfgMsw(iop_base, cfg_msw);
9410 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9411 ASC_DBG(1, "chksum 0x%x\n", chksum);
9415 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9416 warn_code |= ASC_WARN_AUTO_CONFIG;
9417 if (asc_dvc->cfg->chip_version == 3) {
9418 if (eep_config->cfg_lsw != cfg_lsw) {
9419 warn_code |= ASC_WARN_EEPROM_RECOVER;
9420 eep_config->cfg_lsw =
9421 AscGetChipCfgLsw(iop_base);
9423 if (eep_config->cfg_msw != cfg_msw) {
9424 warn_code |= ASC_WARN_EEPROM_RECOVER;
9425 eep_config->cfg_msw =
9426 AscGetChipCfgMsw(iop_base);
9430 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9431 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9432 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9433 if (chksum != eep_config->chksum) {
9434 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9435 ASC_CHIP_VER_PCI_ULTRA_3050) {
9436 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9437 eep_config->init_sdtr = 0xFF;
9438 eep_config->disc_enable = 0xFF;
9439 eep_config->start_motor = 0xFF;
9440 eep_config->use_cmd_qng = 0;
9441 eep_config->max_total_qng = 0xF0;
9442 eep_config->max_tag_qng = 0x20;
9443 eep_config->cntl = 0xBFFF;
9444 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9445 eep_config->no_scam = 0;
9446 eep_config->adapter_info[0] = 0;
9447 eep_config->adapter_info[1] = 0;
9448 eep_config->adapter_info[2] = 0;
9449 eep_config->adapter_info[3] = 0;
9450 eep_config->adapter_info[4] = 0;
9451 /* Indicate EEPROM-less board. */
9452 eep_config->adapter_info[5] = 0xBB;
9455 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9457 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9460 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9461 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9462 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9463 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9464 asc_dvc->start_motor = eep_config->start_motor;
9465 asc_dvc->dvc_cntl = eep_config->cntl;
9466 asc_dvc->no_scam = eep_config->no_scam;
9467 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9468 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9469 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9470 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9471 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9472 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9473 if (!AscTestExternalLram(asc_dvc)) {
9474 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9475 ASC_IS_PCI_ULTRA)) {
9476 eep_config->max_total_qng =
9477 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9478 eep_config->max_tag_qng =
9479 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9481 eep_config->cfg_msw |= 0x0800;
9483 AscSetChipCfgMsw(iop_base, cfg_msw);
9484 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9485 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9489 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9490 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9492 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9493 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9495 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9496 eep_config->max_tag_qng = eep_config->max_total_qng;
9498 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9499 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9501 asc_dvc->max_total_qng = eep_config->max_total_qng;
9502 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9503 eep_config->use_cmd_qng) {
9504 eep_config->disc_enable = eep_config->use_cmd_qng;
9505 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9507 ASC_EEP_SET_CHIP_ID(eep_config,
9508 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9509 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9510 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9511 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9512 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9515 for (i = 0; i <= ASC_MAX_TID; i++) {
9516 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9517 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9518 asc_dvc->cfg->sdtr_period_offset[i] =
9519 (uchar)(ASC_DEF_SDTR_OFFSET |
9520 (asc_dvc->min_sdtr_index << 4));
9522 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9524 if ((i = AscSetEEPConfig(iop_base, eep_config,
9525 asc_dvc->bus_type)) != 0) {
9527 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9531 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9537 static int AscInitGetConfig(struct Scsi_Host *shost)
9539 struct asc_board *board = shost_priv(shost);
9540 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9541 unsigned short warn_code = 0;
9543 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9544 if (asc_dvc->err_code != 0)
9545 return asc_dvc->err_code;
9547 if (AscFindSignature(asc_dvc->iop_base)) {
9548 AscInitAscDvcVar(asc_dvc);
9549 warn_code = AscInitFromEEP(asc_dvc);
9550 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9551 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9552 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9554 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9557 switch (warn_code) {
9558 case 0: /* No error */
9560 case ASC_WARN_IO_PORT_ROTATE:
9561 shost_printk(KERN_WARNING, shost, "I/O port address "
9564 case ASC_WARN_AUTO_CONFIG:
9565 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9568 case ASC_WARN_EEPROM_CHKSUM:
9569 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9571 case ASC_WARN_IRQ_MODIFIED:
9572 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9574 case ASC_WARN_CMD_QNG_CONFLICT:
9575 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9579 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9584 if (asc_dvc->err_code != 0)
9585 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9586 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9588 return asc_dvc->err_code;
9591 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9593 struct asc_board *board = shost_priv(shost);
9594 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9595 PortAddr iop_base = asc_dvc->iop_base;
9596 unsigned short cfg_msw;
9597 unsigned short warn_code = 0;
9599 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9600 if (asc_dvc->err_code != 0)
9601 return asc_dvc->err_code;
9602 if (!AscFindSignature(asc_dvc->iop_base)) {
9603 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9604 return asc_dvc->err_code;
9607 cfg_msw = AscGetChipCfgMsw(iop_base);
9608 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9609 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9610 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9611 AscSetChipCfgMsw(iop_base, cfg_msw);
9613 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9614 asc_dvc->cfg->cmd_qng_enabled) {
9615 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9616 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9618 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9619 warn_code |= ASC_WARN_AUTO_CONFIG;
9622 if (asc_dvc->bus_type & ASC_IS_PCI) {
9624 AscSetChipCfgMsw(iop_base, cfg_msw);
9625 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9627 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9628 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9629 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9630 asc_dvc->bug_fix_cntl |=
9631 ASC_BUG_FIX_ASYN_USE_SYN;
9635 #endif /* CONFIG_PCI */
9636 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9637 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9638 == ASC_CHIP_VER_ASYN_BUG) {
9639 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9642 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9643 asc_dvc->cfg->chip_scsi_id) {
9644 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9647 if (asc_dvc->bus_type & ASC_IS_ISA) {
9648 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9649 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9651 #endif /* CONFIG_ISA */
9653 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9655 switch (warn_code) {
9656 case 0: /* No error. */
9658 case ASC_WARN_IO_PORT_ROTATE:
9659 shost_printk(KERN_WARNING, shost, "I/O port address "
9662 case ASC_WARN_AUTO_CONFIG:
9663 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9666 case ASC_WARN_EEPROM_CHKSUM:
9667 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9669 case ASC_WARN_IRQ_MODIFIED:
9670 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9672 case ASC_WARN_CMD_QNG_CONFLICT:
9673 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9677 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9682 if (asc_dvc->err_code != 0)
9683 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9684 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9686 return asc_dvc->err_code;
9690 * EEPROM Configuration.
9692 * All drivers should use this structure to set the default EEPROM
9693 * configuration. The BIOS now uses this structure when it is built.
9694 * Additional structure information can be found in a_condor.h where
9695 * the structure is defined.
9697 * The *_Field_IsChar structs are needed to correct for endianness.
9698 * These values are read from the board 16 bits at a time directly
9699 * into the structs. Because some fields are char, the values will be
9700 * in the wrong order. The *_Field_IsChar tells when to flip the
9701 * bytes. Data read and written to PCI memory is automatically swapped
9702 * on big-endian platforms so char fields read as words are actually being
9703 * unswapped on big-endian platforms.
9705 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9706 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9707 0x0000, /* cfg_msw */
9708 0xFFFF, /* disc_enable */
9709 0xFFFF, /* wdtr_able */
9710 0xFFFF, /* sdtr_able */
9711 0xFFFF, /* start_motor */
9712 0xFFFF, /* tagqng_able */
9713 0xFFFF, /* bios_scan */
9714 0, /* scam_tolerant */
9715 7, /* adapter_scsi_id */
9716 0, /* bios_boot_delay */
9717 3, /* scsi_reset_delay */
9718 0, /* bios_id_lun */
9719 0, /* termination */
9721 0xFFE7, /* bios_ctrl */
9722 0xFFFF, /* ultra_able */
9724 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9725 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9728 0, /* serial_number_word1 */
9729 0, /* serial_number_word2 */
9730 0, /* serial_number_word3 */
9732 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9733 , /* oem_name[16] */
9734 0, /* dvc_err_code */
9735 0, /* adv_err_code */
9736 0, /* adv_err_addr */
9737 0, /* saved_dvc_err_code */
9738 0, /* saved_adv_err_code */
9739 0, /* saved_adv_err_addr */
9743 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9746 0, /* -disc_enable */
9749 0, /* start_motor */
9750 0, /* tagqng_able */
9752 0, /* scam_tolerant */
9753 1, /* adapter_scsi_id */
9754 1, /* bios_boot_delay */
9755 1, /* scsi_reset_delay */
9756 1, /* bios_id_lun */
9757 1, /* termination */
9762 1, /* max_host_qng */
9763 1, /* max_dvc_qng */
9766 0, /* serial_number_word1 */
9767 0, /* serial_number_word2 */
9768 0, /* serial_number_word3 */
9770 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9771 , /* oem_name[16] */
9772 0, /* dvc_err_code */
9773 0, /* adv_err_code */
9774 0, /* adv_err_addr */
9775 0, /* saved_dvc_err_code */
9776 0, /* saved_adv_err_code */
9777 0, /* saved_adv_err_addr */
9781 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9782 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9783 0x0000, /* 01 cfg_msw */
9784 0xFFFF, /* 02 disc_enable */
9785 0xFFFF, /* 03 wdtr_able */
9786 0x4444, /* 04 sdtr_speed1 */
9787 0xFFFF, /* 05 start_motor */
9788 0xFFFF, /* 06 tagqng_able */
9789 0xFFFF, /* 07 bios_scan */
9790 0, /* 08 scam_tolerant */
9791 7, /* 09 adapter_scsi_id */
9792 0, /* bios_boot_delay */
9793 3, /* 10 scsi_reset_delay */
9794 0, /* bios_id_lun */
9795 0, /* 11 termination_se */
9796 0, /* termination_lvd */
9797 0xFFE7, /* 12 bios_ctrl */
9798 0x4444, /* 13 sdtr_speed2 */
9799 0x4444, /* 14 sdtr_speed3 */
9800 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9801 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9802 0, /* 16 dvc_cntl */
9803 0x4444, /* 17 sdtr_speed4 */
9804 0, /* 18 serial_number_word1 */
9805 0, /* 19 serial_number_word2 */
9806 0, /* 20 serial_number_word3 */
9807 0, /* 21 check_sum */
9808 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9809 , /* 22-29 oem_name[16] */
9810 0, /* 30 dvc_err_code */
9811 0, /* 31 adv_err_code */
9812 0, /* 32 adv_err_addr */
9813 0, /* 33 saved_dvc_err_code */
9814 0, /* 34 saved_adv_err_code */
9815 0, /* 35 saved_adv_err_addr */
9816 0, /* 36 reserved */
9817 0, /* 37 reserved */
9818 0, /* 38 reserved */
9819 0, /* 39 reserved */
9820 0, /* 40 reserved */
9821 0, /* 41 reserved */
9822 0, /* 42 reserved */
9823 0, /* 43 reserved */
9824 0, /* 44 reserved */
9825 0, /* 45 reserved */
9826 0, /* 46 reserved */
9827 0, /* 47 reserved */
9828 0, /* 48 reserved */
9829 0, /* 49 reserved */
9830 0, /* 50 reserved */
9831 0, /* 51 reserved */
9832 0, /* 52 reserved */
9833 0, /* 53 reserved */
9834 0, /* 54 reserved */
9835 0, /* 55 reserved */
9836 0, /* 56 cisptr_lsw */
9837 0, /* 57 cisprt_msw */
9838 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9839 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9840 0, /* 60 reserved */
9841 0, /* 61 reserved */
9842 0, /* 62 reserved */
9846 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
9849 0, /* 02 disc_enable */
9850 0, /* 03 wdtr_able */
9851 0, /* 04 sdtr_speed1 */
9852 0, /* 05 start_motor */
9853 0, /* 06 tagqng_able */
9854 0, /* 07 bios_scan */
9855 0, /* 08 scam_tolerant */
9856 1, /* 09 adapter_scsi_id */
9857 1, /* bios_boot_delay */
9858 1, /* 10 scsi_reset_delay */
9859 1, /* bios_id_lun */
9860 1, /* 11 termination_se */
9861 1, /* termination_lvd */
9862 0, /* 12 bios_ctrl */
9863 0, /* 13 sdtr_speed2 */
9864 0, /* 14 sdtr_speed3 */
9865 1, /* 15 max_host_qng */
9866 1, /* max_dvc_qng */
9867 0, /* 16 dvc_cntl */
9868 0, /* 17 sdtr_speed4 */
9869 0, /* 18 serial_number_word1 */
9870 0, /* 19 serial_number_word2 */
9871 0, /* 20 serial_number_word3 */
9872 0, /* 21 check_sum */
9873 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9874 , /* 22-29 oem_name[16] */
9875 0, /* 30 dvc_err_code */
9876 0, /* 31 adv_err_code */
9877 0, /* 32 adv_err_addr */
9878 0, /* 33 saved_dvc_err_code */
9879 0, /* 34 saved_adv_err_code */
9880 0, /* 35 saved_adv_err_addr */
9881 0, /* 36 reserved */
9882 0, /* 37 reserved */
9883 0, /* 38 reserved */
9884 0, /* 39 reserved */
9885 0, /* 40 reserved */
9886 0, /* 41 reserved */
9887 0, /* 42 reserved */
9888 0, /* 43 reserved */
9889 0, /* 44 reserved */
9890 0, /* 45 reserved */
9891 0, /* 46 reserved */
9892 0, /* 47 reserved */
9893 0, /* 48 reserved */
9894 0, /* 49 reserved */
9895 0, /* 50 reserved */
9896 0, /* 51 reserved */
9897 0, /* 52 reserved */
9898 0, /* 53 reserved */
9899 0, /* 54 reserved */
9900 0, /* 55 reserved */
9901 0, /* 56 cisptr_lsw */
9902 0, /* 57 cisprt_msw */
9903 0, /* 58 subsysvid */
9904 0, /* 59 subsysid */
9905 0, /* 60 reserved */
9906 0, /* 61 reserved */
9907 0, /* 62 reserved */
9911 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
9912 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9913 0x0000, /* 01 cfg_msw */
9914 0xFFFF, /* 02 disc_enable */
9915 0xFFFF, /* 03 wdtr_able */
9916 0x5555, /* 04 sdtr_speed1 */
9917 0xFFFF, /* 05 start_motor */
9918 0xFFFF, /* 06 tagqng_able */
9919 0xFFFF, /* 07 bios_scan */
9920 0, /* 08 scam_tolerant */
9921 7, /* 09 adapter_scsi_id */
9922 0, /* bios_boot_delay */
9923 3, /* 10 scsi_reset_delay */
9924 0, /* bios_id_lun */
9925 0, /* 11 termination_se */
9926 0, /* termination_lvd */
9927 0xFFE7, /* 12 bios_ctrl */
9928 0x5555, /* 13 sdtr_speed2 */
9929 0x5555, /* 14 sdtr_speed3 */
9930 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9931 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9932 0, /* 16 dvc_cntl */
9933 0x5555, /* 17 sdtr_speed4 */
9934 0, /* 18 serial_number_word1 */
9935 0, /* 19 serial_number_word2 */
9936 0, /* 20 serial_number_word3 */
9937 0, /* 21 check_sum */
9938 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9939 , /* 22-29 oem_name[16] */
9940 0, /* 30 dvc_err_code */
9941 0, /* 31 adv_err_code */
9942 0, /* 32 adv_err_addr */
9943 0, /* 33 saved_dvc_err_code */
9944 0, /* 34 saved_adv_err_code */
9945 0, /* 35 saved_adv_err_addr */
9946 0, /* 36 reserved */
9947 0, /* 37 reserved */
9948 0, /* 38 reserved */
9949 0, /* 39 reserved */
9950 0, /* 40 reserved */
9951 0, /* 41 reserved */
9952 0, /* 42 reserved */
9953 0, /* 43 reserved */
9954 0, /* 44 reserved */
9955 0, /* 45 reserved */
9956 0, /* 46 reserved */
9957 0, /* 47 reserved */
9958 0, /* 48 reserved */
9959 0, /* 49 reserved */
9960 0, /* 50 reserved */
9961 0, /* 51 reserved */
9962 0, /* 52 reserved */
9963 0, /* 53 reserved */
9964 0, /* 54 reserved */
9965 0, /* 55 reserved */
9966 0, /* 56 cisptr_lsw */
9967 0, /* 57 cisprt_msw */
9968 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9969 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9970 0, /* 60 reserved */
9971 0, /* 61 reserved */
9972 0, /* 62 reserved */
9976 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
9979 0, /* 02 disc_enable */
9980 0, /* 03 wdtr_able */
9981 0, /* 04 sdtr_speed1 */
9982 0, /* 05 start_motor */
9983 0, /* 06 tagqng_able */
9984 0, /* 07 bios_scan */
9985 0, /* 08 scam_tolerant */
9986 1, /* 09 adapter_scsi_id */
9987 1, /* bios_boot_delay */
9988 1, /* 10 scsi_reset_delay */
9989 1, /* bios_id_lun */
9990 1, /* 11 termination_se */
9991 1, /* termination_lvd */
9992 0, /* 12 bios_ctrl */
9993 0, /* 13 sdtr_speed2 */
9994 0, /* 14 sdtr_speed3 */
9995 1, /* 15 max_host_qng */
9996 1, /* max_dvc_qng */
9997 0, /* 16 dvc_cntl */
9998 0, /* 17 sdtr_speed4 */
9999 0, /* 18 serial_number_word1 */
10000 0, /* 19 serial_number_word2 */
10001 0, /* 20 serial_number_word3 */
10002 0, /* 21 check_sum */
10003 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10004 , /* 22-29 oem_name[16] */
10005 0, /* 30 dvc_err_code */
10006 0, /* 31 adv_err_code */
10007 0, /* 32 adv_err_addr */
10008 0, /* 33 saved_dvc_err_code */
10009 0, /* 34 saved_adv_err_code */
10010 0, /* 35 saved_adv_err_addr */
10011 0, /* 36 reserved */
10012 0, /* 37 reserved */
10013 0, /* 38 reserved */
10014 0, /* 39 reserved */
10015 0, /* 40 reserved */
10016 0, /* 41 reserved */
10017 0, /* 42 reserved */
10018 0, /* 43 reserved */
10019 0, /* 44 reserved */
10020 0, /* 45 reserved */
10021 0, /* 46 reserved */
10022 0, /* 47 reserved */
10023 0, /* 48 reserved */
10024 0, /* 49 reserved */
10025 0, /* 50 reserved */
10026 0, /* 51 reserved */
10027 0, /* 52 reserved */
10028 0, /* 53 reserved */
10029 0, /* 54 reserved */
10030 0, /* 55 reserved */
10031 0, /* 56 cisptr_lsw */
10032 0, /* 57 cisprt_msw */
10033 0, /* 58 subsysvid */
10034 0, /* 59 subsysid */
10035 0, /* 60 reserved */
10036 0, /* 61 reserved */
10037 0, /* 62 reserved */
10038 0 /* 63 reserved */
10043 * Wait for EEPROM command to complete
10045 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
10049 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10050 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10051 ASC_EEP_CMD_DONE) {
10056 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10062 * Read the EEPROM from specified location
10064 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
10066 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10067 ASC_EEP_CMD_READ | eep_word_addr);
10068 AdvWaitEEPCmd(iop_base);
10069 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10073 * Write the EEPROM from 'cfg_buf'.
10075 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10076 ADVEEP_3550_CONFIG *cfg_buf)
10079 ushort addr, chksum;
10080 ushort *charfields;
10082 wbuf = (ushort *)cfg_buf;
10083 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10086 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10087 AdvWaitEEPCmd(iop_base);
10090 * Write EEPROM from word 0 to word 20.
10092 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10093 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10096 if (*charfields++) {
10097 word = cpu_to_le16(*wbuf);
10101 chksum += *wbuf; /* Checksum is calculated from word values. */
10102 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10103 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10104 ASC_EEP_CMD_WRITE | addr);
10105 AdvWaitEEPCmd(iop_base);
10106 mdelay(ADV_EEP_DELAY_MS);
10110 * Write EEPROM checksum at word 21.
10112 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10113 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10114 AdvWaitEEPCmd(iop_base);
10119 * Write EEPROM OEM name at words 22 to 29.
10121 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10122 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10125 if (*charfields++) {
10126 word = cpu_to_le16(*wbuf);
10130 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10131 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10132 ASC_EEP_CMD_WRITE | addr);
10133 AdvWaitEEPCmd(iop_base);
10135 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10136 AdvWaitEEPCmd(iop_base);
10140 * Write the EEPROM from 'cfg_buf'.
10142 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10143 ADVEEP_38C0800_CONFIG *cfg_buf)
10146 ushort *charfields;
10147 ushort addr, chksum;
10149 wbuf = (ushort *)cfg_buf;
10150 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10153 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10154 AdvWaitEEPCmd(iop_base);
10157 * Write EEPROM from word 0 to word 20.
10159 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10160 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10163 if (*charfields++) {
10164 word = cpu_to_le16(*wbuf);
10168 chksum += *wbuf; /* Checksum is calculated from word values. */
10169 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10170 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10171 ASC_EEP_CMD_WRITE | addr);
10172 AdvWaitEEPCmd(iop_base);
10173 mdelay(ADV_EEP_DELAY_MS);
10177 * Write EEPROM checksum at word 21.
10179 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10180 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10181 AdvWaitEEPCmd(iop_base);
10186 * Write EEPROM OEM name at words 22 to 29.
10188 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10189 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10192 if (*charfields++) {
10193 word = cpu_to_le16(*wbuf);
10197 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10198 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10199 ASC_EEP_CMD_WRITE | addr);
10200 AdvWaitEEPCmd(iop_base);
10202 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10203 AdvWaitEEPCmd(iop_base);
10207 * Write the EEPROM from 'cfg_buf'.
10209 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10210 ADVEEP_38C1600_CONFIG *cfg_buf)
10213 ushort *charfields;
10214 ushort addr, chksum;
10216 wbuf = (ushort *)cfg_buf;
10217 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10220 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10221 AdvWaitEEPCmd(iop_base);
10224 * Write EEPROM from word 0 to word 20.
10226 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10227 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10230 if (*charfields++) {
10231 word = cpu_to_le16(*wbuf);
10235 chksum += *wbuf; /* Checksum is calculated from word values. */
10236 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10237 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10238 ASC_EEP_CMD_WRITE | addr);
10239 AdvWaitEEPCmd(iop_base);
10240 mdelay(ADV_EEP_DELAY_MS);
10244 * Write EEPROM checksum at word 21.
10246 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10247 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10248 AdvWaitEEPCmd(iop_base);
10253 * Write EEPROM OEM name at words 22 to 29.
10255 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10256 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10259 if (*charfields++) {
10260 word = cpu_to_le16(*wbuf);
10264 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10265 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10266 ASC_EEP_CMD_WRITE | addr);
10267 AdvWaitEEPCmd(iop_base);
10269 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10270 AdvWaitEEPCmd(iop_base);
10274 * Read EEPROM configuration into the specified buffer.
10276 * Return a checksum based on the EEPROM configuration read.
10278 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10279 ADVEEP_3550_CONFIG *cfg_buf)
10281 ushort wval, chksum;
10284 ushort *charfields;
10286 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10287 wbuf = (ushort *)cfg_buf;
10290 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10291 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10292 wval = AdvReadEEPWord(iop_base, eep_addr);
10293 chksum += wval; /* Checksum is calculated from word values. */
10294 if (*charfields++) {
10295 *wbuf = le16_to_cpu(wval);
10300 /* Read checksum word. */
10301 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10305 /* Read rest of EEPROM not covered by the checksum. */
10306 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10307 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10308 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10309 if (*charfields++) {
10310 *wbuf = le16_to_cpu(*wbuf);
10317 * Read EEPROM configuration into the specified buffer.
10319 * Return a checksum based on the EEPROM configuration read.
10321 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10322 ADVEEP_38C0800_CONFIG *cfg_buf)
10324 ushort wval, chksum;
10327 ushort *charfields;
10329 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10330 wbuf = (ushort *)cfg_buf;
10333 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10334 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10335 wval = AdvReadEEPWord(iop_base, eep_addr);
10336 chksum += wval; /* Checksum is calculated from word values. */
10337 if (*charfields++) {
10338 *wbuf = le16_to_cpu(wval);
10343 /* Read checksum word. */
10344 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10348 /* Read rest of EEPROM not covered by the checksum. */
10349 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10350 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10351 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10352 if (*charfields++) {
10353 *wbuf = le16_to_cpu(*wbuf);
10360 * Read EEPROM configuration into the specified buffer.
10362 * Return a checksum based on the EEPROM configuration read.
10364 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10365 ADVEEP_38C1600_CONFIG *cfg_buf)
10367 ushort wval, chksum;
10370 ushort *charfields;
10372 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10373 wbuf = (ushort *)cfg_buf;
10376 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10377 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10378 wval = AdvReadEEPWord(iop_base, eep_addr);
10379 chksum += wval; /* Checksum is calculated from word values. */
10380 if (*charfields++) {
10381 *wbuf = le16_to_cpu(wval);
10386 /* Read checksum word. */
10387 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10391 /* Read rest of EEPROM not covered by the checksum. */
10392 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10393 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10394 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10395 if (*charfields++) {
10396 *wbuf = le16_to_cpu(*wbuf);
10403 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10404 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10405 * all of this is done.
10407 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10409 * For a non-fatal error return a warning code. If there are no warnings
10410 * then 0 is returned.
10412 * Note: Chip is stopped on entry.
10414 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10416 AdvPortAddr iop_base;
10418 ADVEEP_3550_CONFIG eep_config;
10420 iop_base = asc_dvc->iop_base;
10425 * Read the board's EEPROM configuration.
10427 * Set default values if a bad checksum is found.
10429 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10430 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10433 * Set EEPROM default values.
10435 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10436 sizeof(ADVEEP_3550_CONFIG));
10439 * Assume the 6 byte board serial number that was read from
10440 * EEPROM is correct even if the EEPROM checksum failed.
10442 eep_config.serial_number_word3 =
10443 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10445 eep_config.serial_number_word2 =
10446 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10448 eep_config.serial_number_word1 =
10449 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10451 AdvSet3550EEPConfig(iop_base, &eep_config);
10454 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10455 * EEPROM configuration that was read.
10457 * This is the mapping of EEPROM fields to Adv Library fields.
10459 asc_dvc->wdtr_able = eep_config.wdtr_able;
10460 asc_dvc->sdtr_able = eep_config.sdtr_able;
10461 asc_dvc->ultra_able = eep_config.ultra_able;
10462 asc_dvc->tagqng_able = eep_config.tagqng_able;
10463 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10464 asc_dvc->max_host_qng = eep_config.max_host_qng;
10465 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10466 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10467 asc_dvc->start_motor = eep_config.start_motor;
10468 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10469 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10470 asc_dvc->no_scam = eep_config.scam_tolerant;
10471 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10472 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10473 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10476 * Set the host maximum queuing (max. 253, min. 16) and the per device
10477 * maximum queuing (max. 63, min. 4).
10479 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10480 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10481 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10482 /* If the value is zero, assume it is uninitialized. */
10483 if (eep_config.max_host_qng == 0) {
10484 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10486 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10490 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10491 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10492 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10493 /* If the value is zero, assume it is uninitialized. */
10494 if (eep_config.max_dvc_qng == 0) {
10495 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10497 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10502 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10503 * set 'max_dvc_qng' to 'max_host_qng'.
10505 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10506 eep_config.max_dvc_qng = eep_config.max_host_qng;
10510 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10511 * values based on possibly adjusted EEPROM values.
10513 asc_dvc->max_host_qng = eep_config.max_host_qng;
10514 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10517 * If the EEPROM 'termination' field is set to automatic (0), then set
10518 * the ADV_DVC_CFG 'termination' field to automatic also.
10520 * If the termination is specified with a non-zero 'termination'
10521 * value check that a legal value is set and set the ADV_DVC_CFG
10522 * 'termination' field appropriately.
10524 if (eep_config.termination == 0) {
10525 asc_dvc->cfg->termination = 0; /* auto termination */
10527 /* Enable manual control with low off / high off. */
10528 if (eep_config.termination == 1) {
10529 asc_dvc->cfg->termination = TERM_CTL_SEL;
10531 /* Enable manual control with low off / high on. */
10532 } else if (eep_config.termination == 2) {
10533 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10535 /* Enable manual control with low on / high on. */
10536 } else if (eep_config.termination == 3) {
10537 asc_dvc->cfg->termination =
10538 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10541 * The EEPROM 'termination' field contains a bad value. Use
10542 * automatic termination instead.
10544 asc_dvc->cfg->termination = 0;
10545 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10553 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10554 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10555 * all of this is done.
10557 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10559 * For a non-fatal error return a warning code. If there are no warnings
10560 * then 0 is returned.
10562 * Note: Chip is stopped on entry.
10564 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10566 AdvPortAddr iop_base;
10568 ADVEEP_38C0800_CONFIG eep_config;
10569 uchar tid, termination;
10570 ushort sdtr_speed = 0;
10572 iop_base = asc_dvc->iop_base;
10577 * Read the board's EEPROM configuration.
10579 * Set default values if a bad checksum is found.
10581 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10582 eep_config.check_sum) {
10583 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10586 * Set EEPROM default values.
10588 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10589 sizeof(ADVEEP_38C0800_CONFIG));
10592 * Assume the 6 byte board serial number that was read from
10593 * EEPROM is correct even if the EEPROM checksum failed.
10595 eep_config.serial_number_word3 =
10596 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10598 eep_config.serial_number_word2 =
10599 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10601 eep_config.serial_number_word1 =
10602 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10604 AdvSet38C0800EEPConfig(iop_base, &eep_config);
10607 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10608 * EEPROM configuration that was read.
10610 * This is the mapping of EEPROM fields to Adv Library fields.
10612 asc_dvc->wdtr_able = eep_config.wdtr_able;
10613 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10614 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10615 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10616 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10617 asc_dvc->tagqng_able = eep_config.tagqng_able;
10618 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10619 asc_dvc->max_host_qng = eep_config.max_host_qng;
10620 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10621 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10622 asc_dvc->start_motor = eep_config.start_motor;
10623 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10624 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10625 asc_dvc->no_scam = eep_config.scam_tolerant;
10626 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10627 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10628 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10631 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10632 * are set, then set an 'sdtr_able' bit for it.
10634 asc_dvc->sdtr_able = 0;
10635 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10637 sdtr_speed = asc_dvc->sdtr_speed1;
10638 } else if (tid == 4) {
10639 sdtr_speed = asc_dvc->sdtr_speed2;
10640 } else if (tid == 8) {
10641 sdtr_speed = asc_dvc->sdtr_speed3;
10642 } else if (tid == 12) {
10643 sdtr_speed = asc_dvc->sdtr_speed4;
10645 if (sdtr_speed & ADV_MAX_TID) {
10646 asc_dvc->sdtr_able |= (1 << tid);
10652 * Set the host maximum queuing (max. 253, min. 16) and the per device
10653 * maximum queuing (max. 63, min. 4).
10655 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10656 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10657 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10658 /* If the value is zero, assume it is uninitialized. */
10659 if (eep_config.max_host_qng == 0) {
10660 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10662 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10666 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10667 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10668 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10669 /* If the value is zero, assume it is uninitialized. */
10670 if (eep_config.max_dvc_qng == 0) {
10671 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10673 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10678 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10679 * set 'max_dvc_qng' to 'max_host_qng'.
10681 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10682 eep_config.max_dvc_qng = eep_config.max_host_qng;
10686 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10687 * values based on possibly adjusted EEPROM values.
10689 asc_dvc->max_host_qng = eep_config.max_host_qng;
10690 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10693 * If the EEPROM 'termination' field is set to automatic (0), then set
10694 * the ADV_DVC_CFG 'termination' field to automatic also.
10696 * If the termination is specified with a non-zero 'termination'
10697 * value check that a legal value is set and set the ADV_DVC_CFG
10698 * 'termination' field appropriately.
10700 if (eep_config.termination_se == 0) {
10701 termination = 0; /* auto termination for SE */
10703 /* Enable manual control with low off / high off. */
10704 if (eep_config.termination_se == 1) {
10707 /* Enable manual control with low off / high on. */
10708 } else if (eep_config.termination_se == 2) {
10709 termination = TERM_SE_HI;
10711 /* Enable manual control with low on / high on. */
10712 } else if (eep_config.termination_se == 3) {
10713 termination = TERM_SE;
10716 * The EEPROM 'termination_se' field contains a bad value.
10717 * Use automatic termination instead.
10720 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10724 if (eep_config.termination_lvd == 0) {
10725 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10727 /* Enable manual control with low off / high off. */
10728 if (eep_config.termination_lvd == 1) {
10729 asc_dvc->cfg->termination = termination;
10731 /* Enable manual control with low off / high on. */
10732 } else if (eep_config.termination_lvd == 2) {
10733 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10735 /* Enable manual control with low on / high on. */
10736 } else if (eep_config.termination_lvd == 3) {
10737 asc_dvc->cfg->termination = termination | TERM_LVD;
10740 * The EEPROM 'termination_lvd' field contains a bad value.
10741 * Use automatic termination instead.
10743 asc_dvc->cfg->termination = termination;
10744 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10752 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10753 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10754 * all of this is done.
10756 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10758 * For a non-fatal error return a warning code. If there are no warnings
10759 * then 0 is returned.
10761 * Note: Chip is stopped on entry.
10763 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10765 AdvPortAddr iop_base;
10767 ADVEEP_38C1600_CONFIG eep_config;
10768 uchar tid, termination;
10769 ushort sdtr_speed = 0;
10771 iop_base = asc_dvc->iop_base;
10776 * Read the board's EEPROM configuration.
10778 * Set default values if a bad checksum is found.
10780 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10781 eep_config.check_sum) {
10782 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10783 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10786 * Set EEPROM default values.
10788 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10789 sizeof(ADVEEP_38C1600_CONFIG));
10791 if (PCI_FUNC(pdev->devfn) != 0) {
10794 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10795 * and old Mac system booting problem. The Expansion
10796 * ROM must be disabled in Function 1 for these systems
10798 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10800 * Clear the INTAB (bit 11) if the GPIO 0 input
10801 * indicates the Function 1 interrupt line is wired
10804 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10805 * 1 - Function 1 interrupt line wired to INT A.
10806 * 0 - Function 1 interrupt line wired to INT B.
10808 * Note: Function 0 is always wired to INTA.
10809 * Put all 5 GPIO bits in input mode and then read
10810 * their input values.
10812 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10813 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10814 if ((ints & 0x01) == 0)
10815 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10819 * Assume the 6 byte board serial number that was read from
10820 * EEPROM is correct even if the EEPROM checksum failed.
10822 eep_config.serial_number_word3 =
10823 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10824 eep_config.serial_number_word2 =
10825 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10826 eep_config.serial_number_word1 =
10827 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10829 AdvSet38C1600EEPConfig(iop_base, &eep_config);
10833 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10834 * EEPROM configuration that was read.
10836 * This is the mapping of EEPROM fields to Adv Library fields.
10838 asc_dvc->wdtr_able = eep_config.wdtr_able;
10839 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10840 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10841 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10842 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10843 asc_dvc->ppr_able = 0;
10844 asc_dvc->tagqng_able = eep_config.tagqng_able;
10845 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10846 asc_dvc->max_host_qng = eep_config.max_host_qng;
10847 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10848 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10849 asc_dvc->start_motor = eep_config.start_motor;
10850 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10851 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10852 asc_dvc->no_scam = eep_config.scam_tolerant;
10855 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10856 * are set, then set an 'sdtr_able' bit for it.
10858 asc_dvc->sdtr_able = 0;
10859 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10861 sdtr_speed = asc_dvc->sdtr_speed1;
10862 } else if (tid == 4) {
10863 sdtr_speed = asc_dvc->sdtr_speed2;
10864 } else if (tid == 8) {
10865 sdtr_speed = asc_dvc->sdtr_speed3;
10866 } else if (tid == 12) {
10867 sdtr_speed = asc_dvc->sdtr_speed4;
10869 if (sdtr_speed & ASC_MAX_TID) {
10870 asc_dvc->sdtr_able |= (1 << tid);
10876 * Set the host maximum queuing (max. 253, min. 16) and the per device
10877 * maximum queuing (max. 63, min. 4).
10879 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10880 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10881 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10882 /* If the value is zero, assume it is uninitialized. */
10883 if (eep_config.max_host_qng == 0) {
10884 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10886 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10890 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10891 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10892 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10893 /* If the value is zero, assume it is uninitialized. */
10894 if (eep_config.max_dvc_qng == 0) {
10895 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10897 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10902 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10903 * set 'max_dvc_qng' to 'max_host_qng'.
10905 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10906 eep_config.max_dvc_qng = eep_config.max_host_qng;
10910 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10911 * values based on possibly adjusted EEPROM values.
10913 asc_dvc->max_host_qng = eep_config.max_host_qng;
10914 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10917 * If the EEPROM 'termination' field is set to automatic (0), then set
10918 * the ASC_DVC_CFG 'termination' field to automatic also.
10920 * If the termination is specified with a non-zero 'termination'
10921 * value check that a legal value is set and set the ASC_DVC_CFG
10922 * 'termination' field appropriately.
10924 if (eep_config.termination_se == 0) {
10925 termination = 0; /* auto termination for SE */
10927 /* Enable manual control with low off / high off. */
10928 if (eep_config.termination_se == 1) {
10931 /* Enable manual control with low off / high on. */
10932 } else if (eep_config.termination_se == 2) {
10933 termination = TERM_SE_HI;
10935 /* Enable manual control with low on / high on. */
10936 } else if (eep_config.termination_se == 3) {
10937 termination = TERM_SE;
10940 * The EEPROM 'termination_se' field contains a bad value.
10941 * Use automatic termination instead.
10944 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10948 if (eep_config.termination_lvd == 0) {
10949 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10951 /* Enable manual control with low off / high off. */
10952 if (eep_config.termination_lvd == 1) {
10953 asc_dvc->cfg->termination = termination;
10955 /* Enable manual control with low off / high on. */
10956 } else if (eep_config.termination_lvd == 2) {
10957 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10959 /* Enable manual control with low on / high on. */
10960 } else if (eep_config.termination_lvd == 3) {
10961 asc_dvc->cfg->termination = termination | TERM_LVD;
10964 * The EEPROM 'termination_lvd' field contains a bad value.
10965 * Use automatic termination instead.
10967 asc_dvc->cfg->termination = termination;
10968 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10976 * Initialize the ADV_DVC_VAR structure.
10978 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10980 * For a non-fatal error return a warning code. If there are no warnings
10981 * then 0 is returned.
10983 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
10985 struct asc_board *board = shost_priv(shost);
10986 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
10987 unsigned short warn_code = 0;
10988 AdvPortAddr iop_base = asc_dvc->iop_base;
10992 asc_dvc->err_code = 0;
10995 * Save the state of the PCI Configuration Command Register
10996 * "Parity Error Response Control" Bit. If the bit is clear (0),
10997 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
10998 * DMA parity errors.
11000 asc_dvc->cfg->control_flag = 0;
11001 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11002 if ((cmd & PCI_COMMAND_PARITY) == 0)
11003 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11005 asc_dvc->cfg->chip_version =
11006 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11008 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
11009 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11010 (ushort)ADV_CHIP_ID_BYTE);
11012 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
11013 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11014 (ushort)ADV_CHIP_ID_WORD);
11017 * Reset the chip to start and allow register writes.
11019 if (AdvFindSignature(iop_base) == 0) {
11020 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11024 * The caller must set 'chip_type' to a valid setting.
11026 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11027 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11028 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11029 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11036 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11037 ADV_CTRL_REG_CMD_RESET);
11039 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11040 ADV_CTRL_REG_CMD_WR_IO_REG);
11042 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11043 status = AdvInitFrom38C1600EEP(asc_dvc);
11044 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11045 status = AdvInitFrom38C0800EEP(asc_dvc);
11047 status = AdvInitFrom3550EEP(asc_dvc);
11049 warn_code |= status;
11052 if (warn_code != 0)
11053 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
11055 if (asc_dvc->err_code)
11056 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11057 asc_dvc->err_code);
11059 return asc_dvc->err_code;
11063 static struct scsi_host_template advansys_template = {
11064 .proc_name = DRV_NAME,
11065 #ifdef CONFIG_PROC_FS
11066 .show_info = advansys_show_info,
11069 .info = advansys_info,
11070 .queuecommand = advansys_queuecommand,
11071 .eh_host_reset_handler = advansys_reset,
11072 .bios_param = advansys_biosparam,
11073 .slave_configure = advansys_slave_configure,
11075 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11076 * must be set. The flag will be cleared in advansys_board_found
11077 * for non-ISA adapters.
11079 .unchecked_isa_dma = true,
11081 * All adapters controlled by this driver are capable of large
11082 * scatter-gather lists. According to the mid-level SCSI documentation
11083 * this obviates any performance gain provided by setting
11084 * 'use_clustering'. But empirically while CPU utilization is increased
11085 * by enabling clustering, I/O throughput increases as well.
11087 .use_clustering = ENABLE_CLUSTERING,
11091 static int advansys_wide_init_chip(struct Scsi_Host *shost)
11093 struct asc_board *board = shost_priv(shost);
11094 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11095 size_t sgblk_pool_size;
11096 int warn_code, err_code;
11099 * Allocate buffer carrier structures. The total size
11100 * is about 8 KB, so allocate all at once.
11102 adv_dvc->carrier = dma_alloc_coherent(board->dev,
11103 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
11104 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
11106 if (!adv_dvc->carrier)
11107 goto kmalloc_failed;
11110 * Allocate up to 'max_host_qng' request structures for the Wide
11111 * board. The total size is about 16 KB, so allocate all at once.
11112 * If the allocation fails decrement and try again.
11114 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
11115 if (board->adv_reqp_size & 0x1f) {
11116 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
11117 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
11119 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
11120 &board->adv_reqp_addr, GFP_KERNEL);
11122 if (!board->adv_reqp)
11123 goto kmalloc_failed;
11125 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
11126 adv_dvc->max_host_qng, board->adv_reqp_size);
11129 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11130 * the Wide board. Each structure is about 136 bytes.
11132 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
11133 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
11134 sgblk_pool_size, 32, 0);
11136 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
11137 sizeof(adv_sgblk_t), sgblk_pool_size);
11139 if (!board->adv_sgblk_pool)
11140 goto kmalloc_failed;
11142 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
11143 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
11144 warn_code = AdvInitAsc3550Driver(adv_dvc);
11145 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11146 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
11147 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
11149 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
11150 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
11152 err_code = adv_dvc->err_code;
11154 if (warn_code || err_code) {
11155 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11156 "0x%x\n", warn_code, err_code);
11162 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
11163 err_code = ADV_ERROR;
11168 static void advansys_wide_free_mem(struct asc_board *board)
11170 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11172 if (adv_dvc->carrier) {
11173 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
11174 adv_dvc->carrier, adv_dvc->carrier_addr);
11175 adv_dvc->carrier = NULL;
11177 if (board->adv_reqp) {
11178 dma_free_coherent(board->dev, board->adv_reqp_size,
11179 board->adv_reqp, board->adv_reqp_addr);
11180 board->adv_reqp = NULL;
11182 if (board->adv_sgblk_pool) {
11183 dma_pool_destroy(board->adv_sgblk_pool);
11184 board->adv_sgblk_pool = NULL;
11188 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11191 struct pci_dev *pdev;
11192 struct asc_board *boardp = shost_priv(shost);
11193 ASC_DVC_VAR *asc_dvc_varp = NULL;
11194 ADV_DVC_VAR *adv_dvc_varp = NULL;
11195 int share_irq, warn_code, ret;
11197 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
11199 if (ASC_NARROW_BOARD(boardp)) {
11200 ASC_DBG(1, "narrow board\n");
11201 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11202 asc_dvc_varp->bus_type = bus_type;
11203 asc_dvc_varp->drv_ptr = boardp;
11204 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
11205 asc_dvc_varp->iop_base = iop;
11208 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11209 adv_dvc_varp->drv_ptr = boardp;
11210 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
11211 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
11212 ASC_DBG(1, "wide board ASC-3550\n");
11213 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11214 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
11215 ASC_DBG(1, "wide board ASC-38C0800\n");
11216 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11218 ASC_DBG(1, "wide board ASC-38C1600\n");
11219 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11222 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
11223 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
11224 if (!boardp->ioremap_addr) {
11225 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
11227 (long)pci_resource_start(pdev, 1),
11228 boardp->asc_n_io_port);
11232 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11233 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
11236 * Even though it isn't used to access wide boards, other
11237 * than for the debug line below, save I/O Port address so
11238 * that it can be reported.
11240 boardp->ioport = iop;
11242 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11243 (ushort)inp(iop + 1), (ushort)inpw(iop));
11244 #endif /* CONFIG_PCI */
11247 if (ASC_NARROW_BOARD(boardp)) {
11249 * Set the board bus type and PCI IRQ before
11250 * calling AscInitGetConfig().
11252 switch (asc_dvc_varp->bus_type) {
11255 shost->unchecked_isa_dma = true;
11259 shost->unchecked_isa_dma = false;
11263 shost->unchecked_isa_dma = false;
11264 share_irq = IRQF_SHARED;
11266 #endif /* CONFIG_ISA */
11269 shost->unchecked_isa_dma = false;
11270 share_irq = IRQF_SHARED;
11272 #endif /* CONFIG_PCI */
11274 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11275 "%d\n", asc_dvc_varp->bus_type);
11276 shost->unchecked_isa_dma = false;
11282 * NOTE: AscInitGetConfig() may change the board's
11283 * bus_type value. The bus_type value should no
11284 * longer be used. If the bus_type field must be
11285 * referenced only use the bit-wise AND operator "&".
11287 ASC_DBG(2, "AscInitGetConfig()\n");
11288 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11292 * For Wide boards set PCI information before calling
11293 * AdvInitGetConfig().
11295 shost->unchecked_isa_dma = false;
11296 share_irq = IRQF_SHARED;
11297 ASC_DBG(2, "AdvInitGetConfig()\n");
11299 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11300 #endif /* CONFIG_PCI */
11307 * Save the EEPROM configuration so that it can be displayed
11308 * from /proc/scsi/advansys/[0...].
11310 if (ASC_NARROW_BOARD(boardp)) {
11315 * Set the adapter's target id bit in the 'init_tidmask' field.
11317 boardp->init_tidmask |=
11318 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11321 * Save EEPROM settings for the board.
11323 ep = &boardp->eep_config.asc_eep;
11325 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11326 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11327 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11328 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11329 ep->start_motor = asc_dvc_varp->start_motor;
11330 ep->cntl = asc_dvc_varp->dvc_cntl;
11331 ep->no_scam = asc_dvc_varp->no_scam;
11332 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11333 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11334 /* 'max_tag_qng' is set to the same value for every device. */
11335 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11336 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11337 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11338 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11339 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11340 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11341 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11344 * Modify board configuration.
11346 ASC_DBG(2, "AscInitSetConfig()\n");
11347 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11351 ADVEEP_3550_CONFIG *ep_3550;
11352 ADVEEP_38C0800_CONFIG *ep_38C0800;
11353 ADVEEP_38C1600_CONFIG *ep_38C1600;
11356 * Save Wide EEP Configuration Information.
11358 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11359 ep_3550 = &boardp->eep_config.adv_3550_eep;
11361 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11362 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11363 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11364 ep_3550->termination = adv_dvc_varp->cfg->termination;
11365 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11366 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11367 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11368 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11369 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11370 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11371 ep_3550->start_motor = adv_dvc_varp->start_motor;
11372 ep_3550->scsi_reset_delay =
11373 adv_dvc_varp->scsi_reset_wait;
11374 ep_3550->serial_number_word1 =
11375 adv_dvc_varp->cfg->serial1;
11376 ep_3550->serial_number_word2 =
11377 adv_dvc_varp->cfg->serial2;
11378 ep_3550->serial_number_word3 =
11379 adv_dvc_varp->cfg->serial3;
11380 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11381 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11383 ep_38C0800->adapter_scsi_id =
11384 adv_dvc_varp->chip_scsi_id;
11385 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11386 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11387 ep_38C0800->termination_lvd =
11388 adv_dvc_varp->cfg->termination;
11389 ep_38C0800->disc_enable =
11390 adv_dvc_varp->cfg->disc_enable;
11391 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11392 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11393 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11394 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11395 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11396 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11397 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11398 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11399 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11400 ep_38C0800->scsi_reset_delay =
11401 adv_dvc_varp->scsi_reset_wait;
11402 ep_38C0800->serial_number_word1 =
11403 adv_dvc_varp->cfg->serial1;
11404 ep_38C0800->serial_number_word2 =
11405 adv_dvc_varp->cfg->serial2;
11406 ep_38C0800->serial_number_word3 =
11407 adv_dvc_varp->cfg->serial3;
11409 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11411 ep_38C1600->adapter_scsi_id =
11412 adv_dvc_varp->chip_scsi_id;
11413 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11414 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11415 ep_38C1600->termination_lvd =
11416 adv_dvc_varp->cfg->termination;
11417 ep_38C1600->disc_enable =
11418 adv_dvc_varp->cfg->disc_enable;
11419 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11420 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11421 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11422 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11423 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11424 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11425 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11426 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11427 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11428 ep_38C1600->scsi_reset_delay =
11429 adv_dvc_varp->scsi_reset_wait;
11430 ep_38C1600->serial_number_word1 =
11431 adv_dvc_varp->cfg->serial1;
11432 ep_38C1600->serial_number_word2 =
11433 adv_dvc_varp->cfg->serial2;
11434 ep_38C1600->serial_number_word3 =
11435 adv_dvc_varp->cfg->serial3;
11439 * Set the adapter's target id bit in the 'init_tidmask' field.
11441 boardp->init_tidmask |=
11442 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11446 * Channels are numbered beginning with 0. For AdvanSys one host
11447 * structure supports one channel. Multi-channel boards have a
11448 * separate host structure for each channel.
11450 shost->max_channel = 0;
11451 if (ASC_NARROW_BOARD(boardp)) {
11452 shost->max_id = ASC_MAX_TID + 1;
11453 shost->max_lun = ASC_MAX_LUN + 1;
11454 shost->max_cmd_len = ASC_MAX_CDB_LEN;
11456 shost->io_port = asc_dvc_varp->iop_base;
11457 boardp->asc_n_io_port = ASC_IOADR_GAP;
11458 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11460 /* Set maximum number of queues the adapter can handle. */
11461 shost->can_queue = asc_dvc_varp->max_total_qng;
11463 shost->max_id = ADV_MAX_TID + 1;
11464 shost->max_lun = ADV_MAX_LUN + 1;
11465 shost->max_cmd_len = ADV_MAX_CDB_LEN;
11468 * Save the I/O Port address and length even though
11469 * I/O ports are not used to access Wide boards.
11470 * Instead the Wide boards are accessed with
11471 * PCI Memory Mapped I/O.
11473 shost->io_port = iop;
11475 shost->this_id = adv_dvc_varp->chip_scsi_id;
11477 /* Set maximum number of queues the adapter can handle. */
11478 shost->can_queue = adv_dvc_varp->max_host_qng;
11480 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11482 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11487 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11488 * and should be set to zero.
11490 * But because of a bug introduced in v1.3.89 if the driver is
11491 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11492 * SCSI function 'allocate_device' will panic. To allow the driver
11493 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11495 * Note: This is wrong. cmd_per_lun should be set to the depth
11496 * you want on untagged devices always.
11499 shost->cmd_per_lun = 1;
11501 shost->cmd_per_lun = 0;
11505 * Set the maximum number of scatter-gather elements the
11506 * adapter can handle.
11508 if (ASC_NARROW_BOARD(boardp)) {
11510 * Allow two commands with 'sg_tablesize' scatter-gather
11511 * elements to be executed simultaneously. This value is
11512 * the theoretical hardware limit. It may be decreased
11515 shost->sg_tablesize =
11516 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11517 ASC_SG_LIST_PER_Q) + 1;
11519 shost->sg_tablesize = ADV_MAX_SG_LIST;
11523 * The value of 'sg_tablesize' can not exceed the SCSI
11524 * mid-level driver definition of SG_ALL. SG_ALL also
11525 * must not be exceeded, because it is used to define the
11526 * size of the scatter-gather table in 'struct asc_sg_head'.
11528 if (shost->sg_tablesize > SG_ALL) {
11529 shost->sg_tablesize = SG_ALL;
11532 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11534 /* BIOS start address. */
11535 if (ASC_NARROW_BOARD(boardp)) {
11536 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11537 asc_dvc_varp->bus_type);
11540 * Fill-in BIOS board variables. The Wide BIOS saves
11541 * information in LRAM that is used by the driver.
11543 AdvReadWordLram(adv_dvc_varp->iop_base,
11544 BIOS_SIGNATURE, boardp->bios_signature);
11545 AdvReadWordLram(adv_dvc_varp->iop_base,
11546 BIOS_VERSION, boardp->bios_version);
11547 AdvReadWordLram(adv_dvc_varp->iop_base,
11548 BIOS_CODESEG, boardp->bios_codeseg);
11549 AdvReadWordLram(adv_dvc_varp->iop_base,
11550 BIOS_CODELEN, boardp->bios_codelen);
11552 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11553 boardp->bios_signature, boardp->bios_version);
11555 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11556 boardp->bios_codeseg, boardp->bios_codelen);
11559 * If the BIOS saved a valid signature, then fill in
11560 * the BIOS code segment base address.
11562 if (boardp->bios_signature == 0x55AA) {
11564 * Convert x86 realmode code segment to a linear
11565 * address by shifting left 4.
11567 shost->base = ((ulong)boardp->bios_codeseg << 4);
11574 * Register Board Resources - I/O Port, DMA, IRQ
11577 /* Register DMA Channel for Narrow boards. */
11578 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11580 if (ASC_NARROW_BOARD(boardp)) {
11581 /* Register DMA channel for ISA bus. */
11582 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11583 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11584 ret = request_dma(shost->dma_channel, DRV_NAME);
11586 shost_printk(KERN_ERR, shost, "request_dma() "
11588 shost->dma_channel, ret);
11591 AscEnableIsaDma(shost->dma_channel);
11594 #endif /* CONFIG_ISA */
11596 /* Register IRQ Number. */
11597 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11599 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11603 if (ret == -EBUSY) {
11604 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11605 "already in use\n", boardp->irq);
11606 } else if (ret == -EINVAL) {
11607 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11608 "not valid\n", boardp->irq);
11610 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11611 "failed with %d\n", boardp->irq, ret);
11617 * Initialize board RISC chip and enable interrupts.
11619 if (ASC_NARROW_BOARD(boardp)) {
11620 ASC_DBG(2, "AscInitAsc1000Driver()\n");
11622 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11623 if (!asc_dvc_varp->overrun_buf) {
11627 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11629 if (warn_code || asc_dvc_varp->err_code) {
11630 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11631 "warn 0x%x, error 0x%x\n",
11632 asc_dvc_varp->init_state, warn_code,
11633 asc_dvc_varp->err_code);
11634 if (!asc_dvc_varp->overrun_dma) {
11640 if (advansys_wide_init_chip(shost)) {
11646 ASC_DBG_PRT_SCSI_HOST(2, shost);
11648 ret = scsi_add_host(shost, boardp->dev);
11652 scsi_scan_host(shost);
11656 if (ASC_NARROW_BOARD(boardp)) {
11657 if (asc_dvc_varp->overrun_dma)
11658 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11659 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11660 kfree(asc_dvc_varp->overrun_buf);
11662 advansys_wide_free_mem(boardp);
11664 free_irq(boardp->irq, shost);
11667 if (shost->dma_channel != NO_ISA_DMA)
11668 free_dma(shost->dma_channel);
11671 if (boardp->ioremap_addr)
11672 iounmap(boardp->ioremap_addr);
11678 * advansys_release()
11680 * Release resources allocated for a single AdvanSys adapter.
11682 static int advansys_release(struct Scsi_Host *shost)
11684 struct asc_board *board = shost_priv(shost);
11685 ASC_DBG(1, "begin\n");
11686 scsi_remove_host(shost);
11687 free_irq(board->irq, shost);
11689 if (shost->dma_channel != NO_ISA_DMA) {
11690 ASC_DBG(1, "free_dma()\n");
11691 free_dma(shost->dma_channel);
11694 if (ASC_NARROW_BOARD(board)) {
11695 dma_unmap_single(board->dev,
11696 board->dvc_var.asc_dvc_var.overrun_dma,
11697 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11698 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11700 iounmap(board->ioremap_addr);
11701 advansys_wide_free_mem(board);
11703 scsi_host_put(shost);
11704 ASC_DBG(1, "end\n");
11708 #define ASC_IOADR_TABLE_MAX_IX 11
11710 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11711 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11712 0x0210, 0x0230, 0x0250, 0x0330
11716 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11722 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11724 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11725 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11726 if (chip_irq == 13)
11731 static int advansys_isa_probe(struct device *dev, unsigned int id)
11734 PortAddr iop_base = _asc_def_iop_base[id];
11735 struct Scsi_Host *shost;
11736 struct asc_board *board;
11738 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11739 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11742 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11743 if (!AscFindSignature(iop_base))
11744 goto release_region;
11745 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11746 goto release_region;
11749 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11751 goto release_region;
11753 board = shost_priv(shost);
11754 board->irq = advansys_isa_irq_no(iop_base);
11756 board->shost = shost;
11758 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11762 dev_set_drvdata(dev, shost);
11766 scsi_host_put(shost);
11768 release_region(iop_base, ASC_IOADR_GAP);
11772 static int advansys_isa_remove(struct device *dev, unsigned int id)
11774 int ioport = _asc_def_iop_base[id];
11775 advansys_release(dev_get_drvdata(dev));
11776 release_region(ioport, ASC_IOADR_GAP);
11780 static struct isa_driver advansys_isa_driver = {
11781 .probe = advansys_isa_probe,
11782 .remove = advansys_isa_remove,
11784 .owner = THIS_MODULE,
11790 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11800 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11802 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11803 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11804 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11809 static int advansys_vlb_probe(struct device *dev, unsigned int id)
11812 PortAddr iop_base = _asc_def_iop_base[id];
11813 struct Scsi_Host *shost;
11814 struct asc_board *board;
11816 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11817 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11820 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11821 if (!AscFindSignature(iop_base))
11822 goto release_region;
11824 * I don't think this condition can actually happen, but the old
11825 * driver did it, and the chances of finding a VLB setup in 2007
11826 * to do testing with is slight to none.
11828 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
11829 goto release_region;
11832 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11834 goto release_region;
11836 board = shost_priv(shost);
11837 board->irq = advansys_vlb_irq_no(iop_base);
11839 board->shost = shost;
11841 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11845 dev_set_drvdata(dev, shost);
11849 scsi_host_put(shost);
11851 release_region(iop_base, ASC_IOADR_GAP);
11855 static struct isa_driver advansys_vlb_driver = {
11856 .probe = advansys_vlb_probe,
11857 .remove = advansys_isa_remove,
11859 .owner = THIS_MODULE,
11860 .name = "advansys_vlb",
11864 static struct eisa_device_id advansys_eisa_table[] = {
11870 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11873 * EISA is a little more tricky than PCI; each EISA device may have two
11874 * channels, and this driver is written to make each channel its own Scsi_Host
11876 struct eisa_scsi_data {
11877 struct Scsi_Host *host[2];
11881 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11891 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
11893 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11894 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11895 if ((chip_irq == 13) || (chip_irq > 15))
11900 static int advansys_eisa_probe(struct device *dev)
11902 int i, ioport, irq = 0;
11904 struct eisa_device *edev = to_eisa_device(dev);
11905 struct eisa_scsi_data *data;
11908 data = kzalloc(sizeof(*data), GFP_KERNEL);
11911 ioport = edev->base_addr + 0xc30;
11914 for (i = 0; i < 2; i++, ioport += 0x20) {
11915 struct asc_board *board;
11916 struct Scsi_Host *shost;
11917 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
11918 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11919 ioport + ASC_IOADR_GAP - 1);
11922 if (!AscFindSignature(ioport)) {
11923 release_region(ioport, ASC_IOADR_GAP);
11928 * I don't know why we need to do this for EISA chips, but
11929 * not for any others. It looks to be equivalent to
11930 * AscGetChipCfgMsw, but I may have overlooked something,
11931 * so I'm not converting it until I get an EISA board to
11937 irq = advansys_eisa_irq_no(edev);
11940 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11942 goto release_region;
11944 board = shost_priv(shost);
11947 board->shost = shost;
11949 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11951 data->host[i] = shost;
11955 scsi_host_put(shost);
11957 release_region(ioport, ASC_IOADR_GAP);
11963 dev_set_drvdata(dev, data);
11967 kfree(data->host[0]);
11968 kfree(data->host[1]);
11974 static int advansys_eisa_remove(struct device *dev)
11977 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11979 for (i = 0; i < 2; i++) {
11981 struct Scsi_Host *shost = data->host[i];
11984 ioport = shost->io_port;
11985 advansys_release(shost);
11986 release_region(ioport, ASC_IOADR_GAP);
11993 static struct eisa_driver advansys_eisa_driver = {
11994 .id_table = advansys_eisa_table,
11997 .probe = advansys_eisa_probe,
11998 .remove = advansys_eisa_remove,
12002 /* PCI Devices supported by this driver */
12003 static struct pci_device_id advansys_pci_tbl[] = {
12004 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12005 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12006 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12007 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12008 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12009 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12010 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12011 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12012 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12013 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12014 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12015 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12019 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
12021 static void advansys_set_latency(struct pci_dev *pdev)
12023 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12024 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12025 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12028 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12029 if (latency < 0x20)
12030 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12034 static int advansys_pci_probe(struct pci_dev *pdev,
12035 const struct pci_device_id *ent)
12038 struct Scsi_Host *shost;
12039 struct asc_board *board;
12041 err = pci_enable_device(pdev);
12044 err = pci_request_regions(pdev, DRV_NAME);
12046 goto disable_device;
12047 pci_set_master(pdev);
12048 advansys_set_latency(pdev);
12051 if (pci_resource_len(pdev, 0) == 0)
12052 goto release_region;
12054 ioport = pci_resource_start(pdev, 0);
12057 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12059 goto release_region;
12061 board = shost_priv(shost);
12062 board->irq = pdev->irq;
12063 board->dev = &pdev->dev;
12064 board->shost = shost;
12066 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12067 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12068 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12069 board->flags |= ASC_IS_WIDE_BOARD;
12072 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12076 pci_set_drvdata(pdev, shost);
12080 scsi_host_put(shost);
12082 pci_release_regions(pdev);
12084 pci_disable_device(pdev);
12089 static void advansys_pci_remove(struct pci_dev *pdev)
12091 advansys_release(pci_get_drvdata(pdev));
12092 pci_release_regions(pdev);
12093 pci_disable_device(pdev);
12096 static struct pci_driver advansys_pci_driver = {
12098 .id_table = advansys_pci_tbl,
12099 .probe = advansys_pci_probe,
12100 .remove = advansys_pci_remove,
12103 static int __init advansys_init(void)
12107 error = isa_register_driver(&advansys_isa_driver,
12108 ASC_IOADR_TABLE_MAX_IX);
12112 error = isa_register_driver(&advansys_vlb_driver,
12113 ASC_IOADR_TABLE_MAX_IX);
12115 goto unregister_isa;
12117 error = eisa_driver_register(&advansys_eisa_driver);
12119 goto unregister_vlb;
12121 error = pci_register_driver(&advansys_pci_driver);
12123 goto unregister_eisa;
12128 eisa_driver_unregister(&advansys_eisa_driver);
12130 isa_unregister_driver(&advansys_vlb_driver);
12132 isa_unregister_driver(&advansys_isa_driver);
12137 static void __exit advansys_exit(void)
12139 pci_unregister_driver(&advansys_pci_driver);
12140 eisa_driver_unregister(&advansys_eisa_driver);
12141 isa_unregister_driver(&advansys_vlb_driver);
12142 isa_unregister_driver(&advansys_isa_driver);
12145 module_init(advansys_init);
12146 module_exit(advansys_exit);
12148 MODULE_LICENSE("GPL");
12149 MODULE_FIRMWARE("advansys/mcode.bin");
12150 MODULE_FIRMWARE("advansys/3550.bin");
12151 MODULE_FIRMWARE("advansys/38C0800.bin");
12152 MODULE_FIRMWARE("advansys/38C1600.bin");