drivers/scsi/hisi_sas/hisi_sas_v1_hw.c

   1 /*
   2  * Copyright (c) 2015 Linaro Ltd.
   3  * Copyright (c) 2015 Hisilicon Limited.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  */
  11
  12 #include "hisi_sas.h"
  13 #define DRV_NAME "hisi_sas_v1_hw"
  14
  15 /* global registers need init*/
  16 #define DLVRY_QUEUE_ENABLE              0x0
  17 #define IOST_BASE_ADDR_LO               0x8
  18 #define IOST_BASE_ADDR_HI               0xc
  19 #define ITCT_BASE_ADDR_LO               0x10
  20 #define ITCT_BASE_ADDR_HI               0x14
  21 #define BROKEN_MSG_ADDR_LO              0x18
  22 #define BROKEN_MSG_ADDR_HI              0x1c
  23 #define PHY_CONTEXT                     0x20
  24 #define PHY_STATE                       0x24
  25 #define PHY_PORT_NUM_MA                 0x28
  26 #define PORT_STATE                      0x2c
  27 #define PHY_CONN_RATE                   0x30
  28 #define HGC_TRANS_TASK_CNT_LIMIT        0x38
  29 #define AXI_AHB_CLK_CFG                 0x3c
  30 #define HGC_SAS_TXFAIL_RETRY_CTRL       0x84
  31 #define HGC_GET_ITV_TIME                0x90
  32 #define DEVICE_MSG_WORK_MODE            0x94
  33 #define I_T_NEXUS_LOSS_TIME             0xa0
  34 #define BUS_INACTIVE_LIMIT_TIME         0xa8
  35 #define REJECT_TO_OPEN_LIMIT_TIME       0xac
  36 #define CFG_AGING_TIME                  0xbc
  37 #define CFG_AGING_TIME_ITCT_REL_OFF     0
  38 #define CFG_AGING_TIME_ITCT_REL_MSK     (0x1 << CFG_AGING_TIME_ITCT_REL_OFF)
  39 #define HGC_DFX_CFG2                    0xc0
  40 #define FIS_LIST_BADDR_L                0xc4
  41 #define CFG_1US_TIMER_TRSH              0xcc
  42 #define CFG_SAS_CONFIG                  0xd4
  43 #define HGC_IOST_ECC_ADDR               0x140
  44 #define HGC_IOST_ECC_ADDR_BAD_OFF       16
  45 #define HGC_IOST_ECC_ADDR_BAD_MSK       (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF)
  46 #define HGC_DQ_ECC_ADDR                 0x144
  47 #define HGC_DQ_ECC_ADDR_BAD_OFF         16
  48 #define HGC_DQ_ECC_ADDR_BAD_MSK         (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF)
  49 #define HGC_INVLD_DQE_INFO              0x148
  50 #define HGC_INVLD_DQE_INFO_DQ_OFF       0
  51 #define HGC_INVLD_DQE_INFO_DQ_MSK       (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF)
  52 #define HGC_INVLD_DQE_INFO_TYPE_OFF     16
  53 #define HGC_INVLD_DQE_INFO_TYPE_MSK     (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF)
  54 #define HGC_INVLD_DQE_INFO_FORCE_OFF    17
  55 #define HGC_INVLD_DQE_INFO_FORCE_MSK    (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF)
  56 #define HGC_INVLD_DQE_INFO_PHY_OFF      18
  57 #define HGC_INVLD_DQE_INFO_PHY_MSK      (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF)
  58 #define HGC_INVLD_DQE_INFO_ABORT_OFF    19
  59 #define HGC_INVLD_DQE_INFO_ABORT_MSK    (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF)
  60 #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF  20
  61 #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK  (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF)
  62 #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF  21
  63 #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK  (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF)
  64 #define HGC_INVLD_DQE_INFO_OFL_OFF      22
  65 #define HGC_INVLD_DQE_INFO_OFL_MSK      (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF)
  66 #define HGC_ITCT_ECC_ADDR               0x150
  67 #define HGC_ITCT_ECC_ADDR_BAD_OFF       16
  68 #define HGC_ITCT_ECC_ADDR_BAD_MSK       (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF)
  69 #define HGC_AXI_FIFO_ERR_INFO           0x154
  70 #define INT_COAL_EN                     0x1bc
  71 #define OQ_INT_COAL_TIME                0x1c0
  72 #define OQ_INT_COAL_CNT                 0x1c4
  73 #define ENT_INT_COAL_TIME               0x1c8
  74 #define ENT_INT_COAL_CNT                0x1cc
  75 #define OQ_INT_SRC                      0x1d0
  76 #define OQ_INT_SRC_MSK                  0x1d4
  77 #define ENT_INT_SRC1                    0x1d8
  78 #define ENT_INT_SRC2                    0x1dc
  79 #define ENT_INT_SRC2_DQ_CFG_ERR_OFF     25
  80 #define ENT_INT_SRC2_DQ_CFG_ERR_MSK     (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF)
  81 #define ENT_INT_SRC2_CQ_CFG_ERR_OFF     27
  82 #define ENT_INT_SRC2_CQ_CFG_ERR_MSK     (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF)
  83 #define ENT_INT_SRC2_AXI_WRONG_INT_OFF  28
  84 #define ENT_INT_SRC2_AXI_WRONG_INT_MSK  (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF)
  85 #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29
  86 #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF)
  87 #define ENT_INT_SRC_MSK1                0x1e0
  88 #define ENT_INT_SRC_MSK2                0x1e4
  89 #define SAS_ECC_INTR                    0x1e8
  90 #define SAS_ECC_INTR_DQ_ECC1B_OFF       0
  91 #define SAS_ECC_INTR_DQ_ECC1B_MSK       (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF)
  92 #define SAS_ECC_INTR_DQ_ECCBAD_OFF      1
  93 #define SAS_ECC_INTR_DQ_ECCBAD_MSK      (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF)
  94 #define SAS_ECC_INTR_IOST_ECC1B_OFF     2
  95 #define SAS_ECC_INTR_IOST_ECC1B_MSK     (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF)
  96 #define SAS_ECC_INTR_IOST_ECCBAD_OFF    3
  97 #define SAS_ECC_INTR_IOST_ECCBAD_MSK    (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF)
  98 #define SAS_ECC_INTR_ITCT_ECC1B_OFF     4
  99 #define SAS_ECC_INTR_ITCT_ECC1B_MSK     (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF)
 100 #define SAS_ECC_INTR_ITCT_ECCBAD_OFF    5
 101 #define SAS_ECC_INTR_ITCT_ECCBAD_MSK    (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF)
 102 #define SAS_ECC_INTR_MSK                0x1ec
 103 #define HGC_ERR_STAT_EN                 0x238
 104 #define DLVRY_Q_0_BASE_ADDR_LO          0x260
 105 #define DLVRY_Q_0_BASE_ADDR_HI          0x264
 106 #define DLVRY_Q_0_DEPTH                 0x268
 107 #define DLVRY_Q_0_WR_PTR                0x26c
 108 #define DLVRY_Q_0_RD_PTR                0x270
 109 #define COMPL_Q_0_BASE_ADDR_LO          0x4e0
 110 #define COMPL_Q_0_BASE_ADDR_HI          0x4e4
 111 #define COMPL_Q_0_DEPTH                 0x4e8
 112 #define COMPL_Q_0_WR_PTR                0x4ec
 113 #define COMPL_Q_0_RD_PTR                0x4f0
 114 #define HGC_ECC_ERR                     0x7d0
 115
 116 /* phy registers need init */
 117 #define PORT_BASE                       (0x800)
 118
 119 #define PHY_CFG                         (PORT_BASE + 0x0)
 120 #define PHY_CFG_ENA_OFF                 0
 121 #define PHY_CFG_ENA_MSK                 (0x1 << PHY_CFG_ENA_OFF)
 122 #define PHY_CFG_DC_OPT_OFF              2
 123 #define PHY_CFG_DC_OPT_MSK              (0x1 << PHY_CFG_DC_OPT_OFF)
 124 #define PROG_PHY_LINK_RATE              (PORT_BASE + 0xc)
 125 #define PROG_PHY_LINK_RATE_MAX_OFF      0
 126 #define PROG_PHY_LINK_RATE_MAX_MSK      (0xf << PROG_PHY_LINK_RATE_MAX_OFF)
 127 #define PROG_PHY_LINK_RATE_MIN_OFF      4
 128 #define PROG_PHY_LINK_RATE_MIN_MSK      (0xf << PROG_PHY_LINK_RATE_MIN_OFF)
 129 #define PROG_PHY_LINK_RATE_OOB_OFF      8
 130 #define PROG_PHY_LINK_RATE_OOB_MSK      (0xf << PROG_PHY_LINK_RATE_OOB_OFF)
 131 #define PHY_CTRL                        (PORT_BASE + 0x14)
 132 #define PHY_CTRL_RESET_OFF              0
 133 #define PHY_CTRL_RESET_MSK              (0x1 << PHY_CTRL_RESET_OFF)
 134 #define PHY_RATE_NEGO                   (PORT_BASE + 0x30)
 135 #define PHY_PCN                         (PORT_BASE + 0x44)
 136 #define SL_TOUT_CFG                     (PORT_BASE + 0x8c)
 137 #define SL_CONTROL                      (PORT_BASE + 0x94)
 138 #define SL_CONTROL_NOTIFY_EN_OFF        0
 139 #define SL_CONTROL_NOTIFY_EN_MSK        (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
 140 #define TX_ID_DWORD0                    (PORT_BASE + 0x9c)
 141 #define TX_ID_DWORD1                    (PORT_BASE + 0xa0)
 142 #define TX_ID_DWORD2                    (PORT_BASE + 0xa4)
 143 #define TX_ID_DWORD3                    (PORT_BASE + 0xa8)
 144 #define TX_ID_DWORD4                    (PORT_BASE + 0xaC)
 145 #define TX_ID_DWORD5                    (PORT_BASE + 0xb0)
 146 #define TX_ID_DWORD6                    (PORT_BASE + 0xb4)
 147 #define RX_IDAF_DWORD0                  (PORT_BASE + 0xc4)
 148 #define RX_IDAF_DWORD1                  (PORT_BASE + 0xc8)
 149 #define RX_IDAF_DWORD2                  (PORT_BASE + 0xcc)
 150 #define RX_IDAF_DWORD3                  (PORT_BASE + 0xd0)
 151 #define RX_IDAF_DWORD4                  (PORT_BASE + 0xd4)
 152 #define RX_IDAF_DWORD5                  (PORT_BASE + 0xd8)
 153 #define RX_IDAF_DWORD6                  (PORT_BASE + 0xdc)
 154 #define RXOP_CHECK_CFG_H                (PORT_BASE + 0xfc)
 155 #define DONE_RECEIVED_TIME              (PORT_BASE + 0x12c)
 156 #define CON_CFG_DRIVER                  (PORT_BASE + 0x130)
 157 #define PHY_CONFIG2                     (PORT_BASE + 0x1a8)
 158 #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF  3
 159 #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK  (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF)
 160 #define PHY_CONFIG2_TX_TRAIN_COMP_OFF   24
 161 #define PHY_CONFIG2_TX_TRAIN_COMP_MSK   (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF)
 162 #define CHL_INT0                        (PORT_BASE + 0x1b0)
 163 #define CHL_INT0_PHYCTRL_NOTRDY_OFF     0
 164 #define CHL_INT0_PHYCTRL_NOTRDY_MSK     (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF)
 165 #define CHL_INT0_SN_FAIL_NGR_OFF        2
 166 #define CHL_INT0_SN_FAIL_NGR_MSK        (0x1 << CHL_INT0_SN_FAIL_NGR_OFF)
 167 #define CHL_INT0_DWS_LOST_OFF           4
 168 #define CHL_INT0_DWS_LOST_MSK           (0x1 << CHL_INT0_DWS_LOST_OFF)
 169 #define CHL_INT0_SL_IDAF_FAIL_OFF       10
 170 #define CHL_INT0_SL_IDAF_FAIL_MSK       (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF)
 171 #define CHL_INT0_ID_TIMEOUT_OFF         11
 172 #define CHL_INT0_ID_TIMEOUT_MSK         (0x1 << CHL_INT0_ID_TIMEOUT_OFF)
 173 #define CHL_INT0_SL_OPAF_FAIL_OFF       12
 174 #define CHL_INT0_SL_OPAF_FAIL_MSK       (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF)
 175 #define CHL_INT0_SL_PS_FAIL_OFF         21
 176 #define CHL_INT0_SL_PS_FAIL_MSK         (0x1 << CHL_INT0_SL_PS_FAIL_OFF)
 177 #define CHL_INT1                        (PORT_BASE + 0x1b4)
 178 #define CHL_INT2                        (PORT_BASE + 0x1b8)
 179 #define CHL_INT2_SL_RX_BC_ACK_OFF       2
 180 #define CHL_INT2_SL_RX_BC_ACK_MSK       (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF)
 181 #define CHL_INT2_SL_PHY_ENA_OFF         6
 182 #define CHL_INT2_SL_PHY_ENA_MSK         (0x1 << CHL_INT2_SL_PHY_ENA_OFF)
 183 #define CHL_INT0_MSK                    (PORT_BASE + 0x1bc)
 184 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0
 185 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF)
 186 #define CHL_INT1_MSK                    (PORT_BASE + 0x1c0)
 187 #define CHL_INT2_MSK                    (PORT_BASE + 0x1c4)
 188 #define CHL_INT_COAL_EN                 (PORT_BASE + 0x1d0)
 189 #define DMA_TX_STATUS                   (PORT_BASE + 0x2d0)
 190 #define DMA_TX_STATUS_BUSY_OFF          0
 191 #define DMA_TX_STATUS_BUSY_MSK          (0x1 << DMA_TX_STATUS_BUSY_OFF)
 192 #define DMA_RX_STATUS                   (PORT_BASE + 0x2e8)
 193 #define DMA_RX_STATUS_BUSY_OFF          0
 194 #define DMA_RX_STATUS_BUSY_MSK          (0x1 << DMA_RX_STATUS_BUSY_OFF)
 195
 196 #define AXI_CFG                         0x5100
 197 #define RESET_VALUE                     0x7ffff
 198
 199 /* HW dma structures */
 200 /* Delivery queue header */
 201 /* dw0 */
 202 #define CMD_HDR_RESP_REPORT_OFF         5
 203 #define CMD_HDR_RESP_REPORT_MSK         0x20
 204 #define CMD_HDR_TLR_CTRL_OFF            6
 205 #define CMD_HDR_TLR_CTRL_MSK            0xc0
 206 #define CMD_HDR_PORT_OFF                17
 207 #define CMD_HDR_PORT_MSK                0xe0000
 208 #define CMD_HDR_PRIORITY_OFF            27
 209 #define CMD_HDR_PRIORITY_MSK            0x8000000
 210 #define CMD_HDR_MODE_OFF                28
 211 #define CMD_HDR_MODE_MSK                0x10000000
 212 #define CMD_HDR_CMD_OFF                 29
 213 #define CMD_HDR_CMD_MSK                 0xe0000000
 214 /* dw1 */
 215 #define CMD_HDR_VERIFY_DTL_OFF          10
 216 #define CMD_HDR_VERIFY_DTL_MSK          0x400
 217 #define CMD_HDR_SSP_FRAME_TYPE_OFF      13
 218 #define CMD_HDR_SSP_FRAME_TYPE_MSK      0xe000
 219 #define CMD_HDR_DEVICE_ID_OFF           16
 220 #define CMD_HDR_DEVICE_ID_MSK           0xffff0000
 221 /* dw2 */
 222 #define CMD_HDR_CFL_OFF                 0
 223 #define CMD_HDR_CFL_MSK                 0x1ff
 224 #define CMD_HDR_MRFL_OFF                15
 225 #define CMD_HDR_MRFL_MSK                0xff8000
 226 #define CMD_HDR_FIRST_BURST_OFF         25
 227 #define CMD_HDR_FIRST_BURST_MSK         0x2000000
 228 /* dw3 */
 229 #define CMD_HDR_IPTT_OFF                0
 230 #define CMD_HDR_IPTT_MSK                0xffff
 231 /* dw6 */
 232 #define CMD_HDR_DATA_SGL_LEN_OFF        16
 233 #define CMD_HDR_DATA_SGL_LEN_MSK        0xffff0000
 234
 235 /* Completion header */
 236 #define CMPLT_HDR_IPTT_OFF              0
 237 #define CMPLT_HDR_IPTT_MSK              (0xffff << CMPLT_HDR_IPTT_OFF)
 238 #define CMPLT_HDR_CMD_CMPLT_OFF         17
 239 #define CMPLT_HDR_CMD_CMPLT_MSK         (0x1 << CMPLT_HDR_CMD_CMPLT_OFF)
 240 #define CMPLT_HDR_ERR_RCRD_XFRD_OFF     18
 241 #define CMPLT_HDR_ERR_RCRD_XFRD_MSK     (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF)
 242 #define CMPLT_HDR_RSPNS_XFRD_OFF        19
 243 #define CMPLT_HDR_RSPNS_XFRD_MSK        (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
 244 #define CMPLT_HDR_IO_CFG_ERR_OFF        27
 245 #define CMPLT_HDR_IO_CFG_ERR_MSK        (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF)
 246
 247 /* ITCT header */
 248 /* qw0 */
 249 #define ITCT_HDR_DEV_TYPE_OFF           0
 250 #define ITCT_HDR_DEV_TYPE_MSK           (0x3ULL << ITCT_HDR_DEV_TYPE_OFF)
 251 #define ITCT_HDR_VALID_OFF              2
 252 #define ITCT_HDR_VALID_MSK              (0x1ULL << ITCT_HDR_VALID_OFF)
 253 #define ITCT_HDR_AWT_CONTROL_OFF        4
 254 #define ITCT_HDR_AWT_CONTROL_MSK        (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF)
 255 #define ITCT_HDR_MAX_CONN_RATE_OFF      5
 256 #define ITCT_HDR_MAX_CONN_RATE_MSK      (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF)
 257 #define ITCT_HDR_VALID_LINK_NUM_OFF     9
 258 #define ITCT_HDR_VALID_LINK_NUM_MSK     (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF)
 259 #define ITCT_HDR_PORT_ID_OFF            13
 260 #define ITCT_HDR_PORT_ID_MSK            (0x7ULL << ITCT_HDR_PORT_ID_OFF)
 261 #define ITCT_HDR_SMP_TIMEOUT_OFF        16
 262 #define ITCT_HDR_SMP_TIMEOUT_MSK        (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF)
 263 /* qw1 */
 264 #define ITCT_HDR_MAX_SAS_ADDR_OFF       0
 265 #define ITCT_HDR_MAX_SAS_ADDR_MSK       (0xffffffffffffffff << \
 266                                         ITCT_HDR_MAX_SAS_ADDR_OFF)
 267 /* qw2 */
 268 #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF   0
 269 #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK   (0xffffULL << \
 270                                         ITCT_HDR_IT_NEXUS_LOSS_TL_OFF)
 271 #define ITCT_HDR_BUS_INACTIVE_TL_OFF    16
 272 #define ITCT_HDR_BUS_INACTIVE_TL_MSK    (0xffffULL << \
 273                                         ITCT_HDR_BUS_INACTIVE_TL_OFF)
 274 #define ITCT_HDR_MAX_CONN_TL_OFF        32
 275 #define ITCT_HDR_MAX_CONN_TL_MSK        (0xffffULL << \
 276                                         ITCT_HDR_MAX_CONN_TL_OFF)
 277 #define ITCT_HDR_REJ_OPEN_TL_OFF        48
 278 #define ITCT_HDR_REJ_OPEN_TL_MSK        (0xffffULL << \
 279                                         ITCT_HDR_REJ_OPEN_TL_OFF)
 280
 281 /* Err record header */
 282 #define ERR_HDR_DMA_TX_ERR_TYPE_OFF     0
 283 #define ERR_HDR_DMA_TX_ERR_TYPE_MSK     (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF)
 284 #define ERR_HDR_DMA_RX_ERR_TYPE_OFF     16
 285 #define ERR_HDR_DMA_RX_ERR_TYPE_MSK     (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF)
 286
 287 struct hisi_sas_complete_v1_hdr {
 288         __le32 data;
 289 };
 290
 291 enum {
 292         HISI_SAS_PHY_BCAST_ACK = 0,
 293         HISI_SAS_PHY_SL_PHY_ENABLED,
 294         HISI_SAS_PHY_INT_ABNORMAL,
 295         HISI_SAS_PHY_INT_NR
 296 };
 297
 298 enum {
 299         DMA_TX_ERR_BASE = 0x0,
 300         DMA_RX_ERR_BASE = 0x100,
 301         TRANS_TX_FAIL_BASE = 0x200,
 302         TRANS_RX_FAIL_BASE = 0x300,
 303
 304         /* dma tx */
 305         DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */
 306         DMA_TX_DIF_APP_ERR, /* 0x1 */
 307         DMA_TX_DIF_RPP_ERR, /* 0x2 */
 308         DMA_TX_AXI_BUS_ERR, /* 0x3 */
 309         DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */
 310         DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */
 311         DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */
 312         DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */
 313         DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */
 314         DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */
 315
 316         /* dma rx */
 317         DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */
 318         DMA_RX_DIF_CRC_ERR, /* 0x101 */
 319         DMA_RX_DIF_APP_ERR, /* 0x102 */
 320         DMA_RX_DIF_RPP_ERR, /* 0x103 */
 321         DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */
 322         DMA_RX_AXI_BUS_ERR, /* 0x105 */
 323         DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */
 324         DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */
 325         DMA_RX_DATA_OFFSET_ERR, /* 0x108 */
 326         DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */
 327         DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */
 328         DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */
 329         DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */
 330
 331         /* trans tx */
 332         TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */
 333         TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */
 334         TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */
 335         TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */
 336         TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */
 337         TRANS_TX_RSVD1_ERR, /* 0x205 */
 338         TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */
 339         TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */
 340         TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */
 341         TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */
 342         TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */
 343         TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */
 344         TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */
 345         TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */
 346         TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */
 347         TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */
 348         TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */
 349         TRANS_TX_RSVD2_ERR, /* 0x211 */
 350         TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */
 351         TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */
 352         TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */
 353         TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */
 354         TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */
 355         TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */
 356         TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */
 357         TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */
 358         TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */
 359         TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */
 360         TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */
 361         TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */
 362         TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */
 363         TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */
 364
 365         /* trans rx */
 366         TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */
 367         TRANS_RX_FRAME_DONE_ERR, /* 0x301 */
 368         TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */
 369         TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */
 370         TRANS_RX_RSVD0_ERR, /* 0x304 */
 371         TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */
 372         TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */
 373         TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */
 374         TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */
 375         TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */
 376         TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */
 377         TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */
 378         TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */
 379         TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */
 380         TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */
 381         TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */
 382         TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */
 383         TRANS_RX_BAD_HASH_ERR, /* 0x311 */
 384         TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */
 385         TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */
 386         TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */
 387         TRANS_RX_NO_BALANCE_ERR, /* 0x315 */
 388         TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */
 389         TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */
 390         TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */
 391         TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */
 392         TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */
 393 };
 394
 395 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS)
 396 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES)
 397 #define HISI_SAS_FATAL_INT_NR (2)
 398
 399 #define HISI_SAS_MAX_INT_NR \
 400         (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\
 401         HISI_SAS_FATAL_INT_NR)
 402
 403 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
 404 {
 405         void __iomem *regs = hisi_hba->regs + off;
 406
 407         return readl(regs);
 408 }
 409
 410 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
 411 {
 412         void __iomem *regs = hisi_hba->regs + off;
 413
 414         return readl_relaxed(regs);
 415 }
 416
 417 static void hisi_sas_write32(struct hisi_hba *hisi_hba,
 418                                     u32 off, u32 val)
 419 {
 420         void __iomem *regs = hisi_hba->regs + off;
 421
 422         writel(val, regs);
 423 }
 424
 425 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba,
 426                                         int phy_no, u32 off, u32 val)
 427 {
 428         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 429
 430         writel(val, regs);
 431 }
 432
 433 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
 434                                       int phy_no, u32 off)
 435 {
 436         void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
 437
 438         return readl(regs);
 439 }
 440
 441 static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 442 {
 443         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 444
 445         cfg &= ~PHY_CFG_DC_OPT_MSK;
 446         cfg |= 1 << PHY_CFG_DC_OPT_OFF;
 447         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 448 }
 449
 450 static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 451 {
 452         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2);
 453
 454         cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK;
 455         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg);
 456 }
 457
 458 static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 459 {
 460         struct sas_identify_frame identify_frame;
 461         u32 *identify_buffer;
 462
 463         memset(&identify_frame, 0, sizeof(identify_frame));
 464         identify_frame.dev_type = SAS_END_DEVICE;
 465         identify_frame.frame_type = 0;
 466         identify_frame._un1 = 1;
 467         identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
 468         identify_frame.target_bits = SAS_PROTOCOL_NONE;
 469         memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 470         memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
 471         identify_frame.phy_id = phy_no;
 472         identify_buffer = (u32 *)(&identify_frame);
 473
 474         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
 475                         __swab32(identify_buffer[0]));
 476         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
 477                         identify_buffer[2]);
 478         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
 479                         identify_buffer[1]);
 480         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
 481                         identify_buffer[4]);
 482         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
 483                         identify_buffer[3]);
 484         hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
 485                         __swab32(identify_buffer[5]));
 486 }
 487
 488 static void init_id_frame_v1_hw(struct hisi_hba *hisi_hba)
 489 {
 490         int i;
 491
 492         for (i = 0; i < hisi_hba->n_phy; i++)
 493                 config_id_frame_v1_hw(hisi_hba, i);
 494 }
 495
 496 static void setup_itct_v1_hw(struct hisi_hba *hisi_hba,
 497                              struct hisi_sas_device *sas_dev)
 498 {
 499         struct domain_device *device = sas_dev->sas_device;
 500         struct device *dev = &hisi_hba->pdev->dev;
 501         u64 qw0, device_id = sas_dev->device_id;
 502         struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
 503
 504         memset(itct, 0, sizeof(*itct));
 505
 506         /* qw0 */
 507         qw0 = 0;
 508         switch (sas_dev->dev_type) {
 509         case SAS_END_DEVICE:
 510         case SAS_EDGE_EXPANDER_DEVICE:
 511         case SAS_FANOUT_EXPANDER_DEVICE:
 512                 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
 513                 break;
 514         default:
 515                 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
 516                          sas_dev->dev_type);
 517         }
 518
 519         qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
 520                 (1 << ITCT_HDR_AWT_CONTROL_OFF) |
 521                 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) |
 522                 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) |
 523                 (device->port->id << ITCT_HDR_PORT_ID_OFF));
 524         itct->qw0 = cpu_to_le64(qw0);
 525
 526         /* qw1 */
 527         memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
 528         itct->sas_addr = __swab64(itct->sas_addr);
 529
 530         /* qw2 */
 531         itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) |
 532                                 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) |
 533                                 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) |
 534                                 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF));
 535 }
 536
 537 static void free_device_v1_hw(struct hisi_hba *hisi_hba,
 538                               struct hisi_sas_device *sas_dev)
 539 {
 540         u64 dev_id = sas_dev->device_id;
 541         struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
 542         u64 qw0;
 543         u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
 544
 545         reg_val |= CFG_AGING_TIME_ITCT_REL_MSK;
 546         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
 547
 548         /* free itct */
 549         udelay(1);
 550         reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME);
 551         reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK;
 552         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val);
 553
 554         qw0 = cpu_to_le64(itct->qw0);
 555         qw0 &= ~ITCT_HDR_VALID_MSK;
 556         itct->qw0 = cpu_to_le64(qw0);
 557 }
 558
 559 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba)
 560 {
 561         int i;
 562         unsigned long end_time;
 563         u32 val;
 564         struct device *dev = &hisi_hba->pdev->dev;
 565
 566         for (i = 0; i < hisi_hba->n_phy; i++) {
 567                 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL);
 568
 569                 phy_ctrl |= PHY_CTRL_RESET_MSK;
 570                 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl);
 571         }
 572         msleep(1); /* It is safe to wait for 50us */
 573
 574         /* Ensure DMA tx & rx idle */
 575         for (i = 0; i < hisi_hba->n_phy; i++) {
 576                 u32 dma_tx_status, dma_rx_status;
 577
 578                 end_time = jiffies + msecs_to_jiffies(1000);
 579
 580                 while (1) {
 581                         dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
 582                                                             DMA_TX_STATUS);
 583                         dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
 584                                                             DMA_RX_STATUS);
 585
 586                         if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
 587                                 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
 588                                 break;
 589
 590                         msleep(20);
 591                         if (time_after(jiffies, end_time))
 592                                 return -EIO;
 593                 }
 594         }
 595
 596         /* Ensure axi bus idle */
 597         end_time = jiffies + msecs_to_jiffies(1000);
 598         while (1) {
 599                 u32 axi_status =
 600                         hisi_sas_read32(hisi_hba, AXI_CFG);
 601
 602                 if (axi_status == 0)
 603                         break;
 604
 605                 msleep(20);
 606                 if (time_after(jiffies, end_time))
 607                         return -EIO;
 608         }
 609
 610         /* Apply reset and disable clock */
 611         /* clk disable reg is offset by +4 bytes from clk enable reg */
 612         regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
 613                      RESET_VALUE);
 614         regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
 615                      RESET_VALUE);
 616         msleep(1);
 617         regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 618         if (RESET_VALUE != (val & RESET_VALUE)) {
 619                 dev_err(dev, "Reset failed\n");
 620                 return -EIO;
 621         }
 622
 623         /* De-reset and enable clock */
 624         /* deassert rst reg is offset by +4 bytes from assert reg */
 625         regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
 626                      RESET_VALUE);
 627         regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
 628                      RESET_VALUE);
 629         msleep(1);
 630         regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
 631         if (val & RESET_VALUE) {
 632                 dev_err(dev, "De-reset failed\n");
 633                 return -EIO;
 634         }
 635
 636         return 0;
 637 }
 638
 639 static void init_reg_v1_hw(struct hisi_hba *hisi_hba)
 640 {
 641         int i;
 642
 643         /* Global registers init*/
 644         hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
 645                          (u32)((1ULL << hisi_hba->queue_count) - 1));
 646         hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11);
 647         hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1);
 648         hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff);
 649         hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401);
 650         hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64);
 651         hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
 652         hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64);
 653         hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710);
 654         hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1);
 655         hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12);
 656         hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40);
 657         hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2);
 658         hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
 659         hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0);
 660         hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1);
 661         hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
 662         hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
 663         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff);
 664         hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0);
 665         hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
 666         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0);
 667         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
 668         hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0);
 669         hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0);
 670         hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2);
 671         hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000);
 672
 673         for (i = 0; i < hisi_hba->n_phy; i++) {
 674                 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a);
 675                 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080);
 676                 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00);
 677                 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000);
 678                 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
 679                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0);
 680                 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
 681                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0);
 682                 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a);
 683                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3);
 684                 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8);
 685         }
 686
 687         for (i = 0; i < hisi_hba->queue_count; i++) {
 688                 /* Delivery queue */
 689                 hisi_sas_write32(hisi_hba,
 690                                  DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
 691                                  upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
 692
 693                 hisi_sas_write32(hisi_hba,
 694                                  DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
 695                                  lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
 696
 697                 hisi_sas_write32(hisi_hba,
 698                                  DLVRY_Q_0_DEPTH + (i * 0x14),
 699                                  HISI_SAS_QUEUE_SLOTS);
 700
 701                 /* Completion queue */
 702                 hisi_sas_write32(hisi_hba,
 703                                  COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
 704                                  upper_32_bits(hisi_hba->complete_hdr_dma[i]));
 705
 706                 hisi_sas_write32(hisi_hba,
 707                                  COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
 708                                  lower_32_bits(hisi_hba->complete_hdr_dma[i]));
 709
 710                 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
 711                                  HISI_SAS_QUEUE_SLOTS);
 712         }
 713
 714         /* itct */
 715         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
 716                          lower_32_bits(hisi_hba->itct_dma));
 717
 718         hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
 719                          upper_32_bits(hisi_hba->itct_dma));
 720
 721         /* iost */
 722         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
 723                          lower_32_bits(hisi_hba->iost_dma));
 724
 725         hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
 726                          upper_32_bits(hisi_hba->iost_dma));
 727
 728         /* breakpoint */
 729         hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO,
 730                          lower_32_bits(hisi_hba->breakpoint_dma));
 731
 732         hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI,
 733                          upper_32_bits(hisi_hba->breakpoint_dma));
 734 }
 735
 736 static int hw_init_v1_hw(struct hisi_hba *hisi_hba)
 737 {
 738         struct device *dev = &hisi_hba->pdev->dev;
 739         int rc;
 740
 741         rc = reset_hw_v1_hw(hisi_hba);
 742         if (rc) {
 743                 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
 744                 return rc;
 745         }
 746
 747         msleep(100);
 748         init_reg_v1_hw(hisi_hba);
 749
 750         init_id_frame_v1_hw(hisi_hba);
 751
 752         return 0;
 753 }
 754
 755 static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 756 {
 757         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 758
 759         cfg |= PHY_CFG_ENA_MSK;
 760         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 761 }
 762
 763 static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 764 {
 765         u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
 766
 767         cfg &= ~PHY_CFG_ENA_MSK;
 768         hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
 769 }
 770
 771 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 772 {
 773         config_id_frame_v1_hw(hisi_hba, phy_no);
 774         config_phy_opt_mode_v1_hw(hisi_hba, phy_no);
 775         config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no);
 776         enable_phy_v1_hw(hisi_hba, phy_no);
 777 }
 778
 779 static void stop_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 780 {
 781         disable_phy_v1_hw(hisi_hba, phy_no);
 782 }
 783
 784 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 785 {
 786         stop_phy_v1_hw(hisi_hba, phy_no);
 787         msleep(100);
 788         start_phy_v1_hw(hisi_hba, phy_no);
 789 }
 790
 791 static void start_phys_v1_hw(unsigned long data)
 792 {
 793         struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
 794         int i;
 795
 796         for (i = 0; i < hisi_hba->n_phy; i++) {
 797                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a);
 798                 start_phy_v1_hw(hisi_hba, i);
 799         }
 800 }
 801
 802 static void phys_init_v1_hw(struct hisi_hba *hisi_hba)
 803 {
 804         int i;
 805         struct timer_list *timer = &hisi_hba->timer;
 806
 807         for (i = 0; i < hisi_hba->n_phy; i++) {
 808                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
 809                 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
 810         }
 811
 812         setup_timer(timer, start_phys_v1_hw, (unsigned long)hisi_hba);
 813         mod_timer(timer, jiffies + HZ);
 814 }
 815
 816 static void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no)
 817 {
 818         u32 sl_control;
 819
 820         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 821         sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
 822         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 823         msleep(1);
 824         sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
 825         sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
 826         hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
 827 }
 828
 829 static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id)
 830 {
 831         int i, bitmap = 0;
 832         u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
 833
 834         for (i = 0; i < hisi_hba->n_phy; i++)
 835                 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
 836                         bitmap |= 1 << i;
 837
 838         return bitmap;
 839 }
 840
 841 /**
 842  * This function allocates across all queues to load balance.
 843  * Slots are allocated from queues in a round-robin fashion.
 844  *
 845  * The callpath to this function and upto writing the write
 846  * queue pointer should be safe from interruption.
 847  */
 848 static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, int *q, int *s)
 849 {
 850         struct device *dev = &hisi_hba->pdev->dev;
 851         u32 r, w;
 852         int queue = hisi_hba->queue;
 853
 854         while (1) {
 855                 w = hisi_sas_read32_relaxed(hisi_hba,
 856                                     DLVRY_Q_0_WR_PTR + (queue * 0x14));
 857                 r = hisi_sas_read32_relaxed(hisi_hba,
 858                                     DLVRY_Q_0_RD_PTR + (queue * 0x14));
 859                 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
 860                         queue = (queue + 1) % hisi_hba->queue_count;
 861                         if (queue == hisi_hba->queue) {
 862                                 dev_warn(dev, "could not find free slot\n");
 863                                 return -EAGAIN;
 864                         }
 865                         continue;
 866                 }
 867                 break;
 868         }
 869         hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
 870         *q = queue;
 871         *s = w;
 872         return 0;
 873 }
 874
 875 static void start_delivery_v1_hw(struct hisi_hba *hisi_hba)
 876 {
 877         int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
 878         int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
 879
 880         hisi_sas_write32(hisi_hba,
 881                          DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
 882                          ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS);
 883 }
 884
 885 static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba,
 886                               struct hisi_sas_slot *slot,
 887                               struct hisi_sas_cmd_hdr *hdr,
 888                               struct scatterlist *scatter,
 889                               int n_elem)
 890 {
 891         struct device *dev = &hisi_hba->pdev->dev;
 892         struct scatterlist *sg;
 893         int i;
 894
 895         if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
 896                 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
 897                         n_elem);
 898                 return -EINVAL;
 899         }
 900
 901         slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
 902                                         &slot->sge_page_dma);
 903         if (!slot->sge_page)
 904                 return -ENOMEM;
 905
 906         for_each_sg(scatter, sg, n_elem, i) {
 907                 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
 908
 909                 entry->addr = cpu_to_le64(sg_dma_address(sg));
 910                 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
 911                 entry->data_len = cpu_to_le32(sg_dma_len(sg));
 912                 entry->data_off = 0;
 913         }
 914
 915         hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
 916
 917         hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
 918
 919         return 0;
 920 }
 921
 922 static int prep_smp_v1_hw(struct hisi_hba *hisi_hba,
 923                           struct hisi_sas_slot *slot)
 924 {
 925         struct sas_task *task = slot->task;
 926         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 927         struct domain_device *device = task->dev;
 928         struct device *dev = &hisi_hba->pdev->dev;
 929         struct hisi_sas_port *port = slot->port;
 930         struct scatterlist *sg_req, *sg_resp;
 931         struct hisi_sas_device *sas_dev = device->lldd_dev;
 932         dma_addr_t req_dma_addr;
 933         unsigned int req_len, resp_len;
 934         int elem, rc;
 935
 936         /*
 937         * DMA-map SMP request, response buffers
 938         */
 939         /* req */
 940         sg_req = &task->smp_task.smp_req;
 941         elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
 942         if (!elem)
 943                 return -ENOMEM;
 944         req_len = sg_dma_len(sg_req);
 945         req_dma_addr = sg_dma_address(sg_req);
 946
 947         /* resp */
 948         sg_resp = &task->smp_task.smp_resp;
 949         elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
 950         if (!elem) {
 951                 rc = -ENOMEM;
 952                 goto err_out_req;
 953         }
 954         resp_len = sg_dma_len(sg_resp);
 955         if ((req_len & 0x3) || (resp_len & 0x3)) {
 956                 rc = -EINVAL;
 957                 goto err_out_resp;
 958         }
 959
 960         /* create header */
 961         /* dw0 */
 962         hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
 963                                (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
 964                                (1 << CMD_HDR_MODE_OFF) | /* ini mode */
 965                                (2 << CMD_HDR_CMD_OFF)); /* smp */
 966
 967         /* map itct entry */
 968         hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF);
 969
 970         /* dw2 */
 971         hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) |
 972                                (HISI_SAS_MAX_SMP_RESP_SZ/4 <<
 973                                CMD_HDR_MRFL_OFF));
 974
 975         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
 976
 977         hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
 978         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
 979
 980         return 0;
 981
 982 err_out_resp:
 983         dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
 984                      DMA_FROM_DEVICE);
 985 err_out_req:
 986         dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
 987                      DMA_TO_DEVICE);
 988         return rc;
 989 }
 990
 991 static int prep_ssp_v1_hw(struct hisi_hba *hisi_hba,
 992                           struct hisi_sas_slot *slot, int is_tmf,
 993                           struct hisi_sas_tmf_task *tmf)
 994 {
 995         struct sas_task *task = slot->task;
 996         struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
 997         struct domain_device *device = task->dev;
 998         struct hisi_sas_device *sas_dev = device->lldd_dev;
 999         struct hisi_sas_port *port = slot->port;
1000         struct sas_ssp_task *ssp_task = &task->ssp_task;
1001         struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1002         int has_data = 0, rc, priority = is_tmf;
1003         u8 *buf_cmd, fburst = 0;
1004         u32 dw1, dw2;
1005
1006         /* create header */
1007         hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1008                                (0x2 << CMD_HDR_TLR_CTRL_OFF) |
1009                                (port->id << CMD_HDR_PORT_OFF) |
1010                                (priority << CMD_HDR_PRIORITY_OFF) |
1011                                (1 << CMD_HDR_MODE_OFF) | /* ini mode */
1012                                (1 << CMD_HDR_CMD_OFF)); /* ssp */
1013
1014         dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF;
1015
1016         if (is_tmf) {
1017                 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1018         } else {
1019                 switch (scsi_cmnd->sc_data_direction) {
1020                 case DMA_TO_DEVICE:
1021                         dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1022                         has_data = 1;
1023                         break;
1024                 case DMA_FROM_DEVICE:
1025                         dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1026                         has_data = 1;
1027                         break;
1028                 default:
1029                         dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF;
1030                 }
1031         }
1032
1033         /* map itct entry */
1034         dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF;
1035         hdr->dw1 = cpu_to_le32(dw1);
1036
1037         if (is_tmf) {
1038                 dw2 = ((sizeof(struct ssp_tmf_iu) +
1039                         sizeof(struct ssp_frame_hdr)+3)/4) <<
1040                         CMD_HDR_CFL_OFF;
1041         } else {
1042                 dw2 = ((sizeof(struct ssp_command_iu) +
1043                         sizeof(struct ssp_frame_hdr)+3)/4) <<
1044                         CMD_HDR_CFL_OFF;
1045         }
1046
1047         dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF;
1048
1049         hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1050
1051         if (has_data) {
1052                 rc = prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter,
1053                                         slot->n_elem);
1054                 if (rc)
1055                         return rc;
1056         }
1057
1058         hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1059         hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
1060         hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
1061
1062         buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
1063         if (task->ssp_task.enable_first_burst) {
1064                 fburst = (1 << 7);
1065                 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF;
1066         }
1067         hdr->dw2 = cpu_to_le32(dw2);
1068
1069         memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1070         if (!is_tmf) {
1071                 buf_cmd[9] = fburst | task->ssp_task.task_attr |
1072                                 (task->ssp_task.task_prio << 3);
1073                 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1074                                 task->ssp_task.cmd->cmd_len);
1075         } else {
1076                 buf_cmd[10] = tmf->tmf;
1077                 switch (tmf->tmf) {
1078                 case TMF_ABORT_TASK:
1079                 case TMF_QUERY_TASK:
1080                         buf_cmd[12] =
1081                                 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1082                         buf_cmd[13] =
1083                                 tmf->tag_of_task_to_be_managed & 0xff;
1084                         break;
1085                 default:
1086                         break;
1087                 }
1088         }
1089
1090         return 0;
1091 }
1092
1093 /* by default, task resp is complete */
1094 static void slot_err_v1_hw(struct hisi_hba *hisi_hba,
1095                            struct sas_task *task,
1096                            struct hisi_sas_slot *slot)
1097 {
1098         struct task_status_struct *ts = &task->task_status;
1099         struct hisi_sas_err_record *err_record = slot->status_buffer;
1100         struct device *dev = &hisi_hba->pdev->dev;
1101
1102         switch (task->task_proto) {
1103         case SAS_PROTOCOL_SSP:
1104         {
1105                 int error = -1;
1106                 u32 dma_err_type = cpu_to_le32(err_record->dma_err_type);
1107                 u32 dma_tx_err_type = ((dma_err_type &
1108                                         ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >>
1109                                         ERR_HDR_DMA_TX_ERR_TYPE_OFF;
1110                 u32 dma_rx_err_type = ((dma_err_type &
1111                                         ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >>
1112                                         ERR_HDR_DMA_RX_ERR_TYPE_OFF;
1113                 u32 trans_tx_fail_type =
1114                                 cpu_to_le32(err_record->trans_tx_fail_type);
1115                 u32 trans_rx_fail_type =
1116                                 cpu_to_le32(err_record->trans_rx_fail_type);
1117
1118                 if (dma_tx_err_type) {
1119                         /* dma tx err */
1120                         error = ffs(dma_tx_err_type)
1121                                 - 1 + DMA_TX_ERR_BASE;
1122                 } else if (dma_rx_err_type) {
1123                         /* dma rx err */
1124                         error = ffs(dma_rx_err_type)
1125                                 - 1 + DMA_RX_ERR_BASE;
1126                 } else if (trans_tx_fail_type) {
1127                         /* trans tx err */
1128                         error = ffs(trans_tx_fail_type)
1129                                 - 1 + TRANS_TX_FAIL_BASE;
1130                 } else if (trans_rx_fail_type) {
1131                         /* trans rx err */
1132                         error = ffs(trans_rx_fail_type)
1133                                 - 1 + TRANS_RX_FAIL_BASE;
1134                 }
1135
1136                 switch (error) {
1137                 case DMA_TX_DATA_UNDERFLOW_ERR:
1138                 case DMA_RX_DATA_UNDERFLOW_ERR:
1139                 {
1140                         ts->residual = 0;
1141                         ts->stat = SAS_DATA_UNDERRUN;
1142                         break;
1143                 }
1144                 case DMA_TX_DATA_SGL_OVERFLOW_ERR:
1145                 case DMA_TX_DIF_SGL_OVERFLOW_ERR:
1146                 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR:
1147                 case DMA_RX_DATA_OVERFLOW_ERR:
1148                 case TRANS_RX_FRAME_OVERRUN_ERR:
1149                 case TRANS_RX_LINK_BUF_OVERRUN_ERR:
1150                 {
1151                         ts->stat = SAS_DATA_OVERRUN;
1152                         ts->residual = 0;
1153                         break;
1154                 }
1155                 case TRANS_TX_PHY_NOT_ENABLE_ERR:
1156                 {
1157                         ts->stat = SAS_PHY_DOWN;
1158                         break;
1159                 }
1160                 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR:
1161                 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR:
1162                 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR:
1163                 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR:
1164                 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR:
1165                 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR:
1166                 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR:
1167                 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR:
1168                 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR:
1169                 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR:
1170                 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR:
1171                 case TRANS_TX_OPEN_RETRY_ERR:
1172                 {
1173                         ts->stat = SAS_OPEN_REJECT;
1174                         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1175                         break;
1176                 }
1177                 case TRANS_TX_OPEN_TIMEOUT_ERR:
1178                 {
1179                         ts->stat = SAS_OPEN_TO;
1180                         break;
1181                 }
1182                 case TRANS_TX_NAK_RECEIVE_ERR:
1183                 case TRANS_TX_ACK_NAK_TIMEOUT_ERR:
1184                 {
1185                         ts->stat = SAS_NAK_R_ERR;
1186                         break;
1187                 }
1188                 default:
1189                 {
1190                         ts->stat = SAM_STAT_CHECK_CONDITION;
1191                         break;
1192                 }
1193                 }
1194         }
1195                 break;
1196         case SAS_PROTOCOL_SMP:
1197                 ts->stat = SAM_STAT_CHECK_CONDITION;
1198                 break;
1199
1200         case SAS_PROTOCOL_SATA:
1201         case SAS_PROTOCOL_STP:
1202         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1203         {
1204                 dev_err(dev, "slot err: SATA/STP not supported");
1205         }
1206                 break;
1207         default:
1208                 break;
1209         }
1210
1211 }
1212
1213 static int slot_complete_v1_hw(struct hisi_hba *hisi_hba,
1214                                struct hisi_sas_slot *slot, int abort)
1215 {
1216         struct sas_task *task = slot->task;
1217         struct hisi_sas_device *sas_dev;
1218         struct device *dev = &hisi_hba->pdev->dev;
1219         struct task_status_struct *ts;
1220         struct domain_device *device;
1221         enum exec_status sts;
1222         struct hisi_sas_complete_v1_hdr *complete_queue =
1223                         (struct hisi_sas_complete_v1_hdr *)
1224                         hisi_hba->complete_hdr[slot->cmplt_queue];
1225         struct hisi_sas_complete_v1_hdr *complete_hdr;
1226         u32 cmplt_hdr_data;
1227
1228         complete_hdr = &complete_queue[slot->cmplt_queue_slot];
1229         cmplt_hdr_data = le32_to_cpu(complete_hdr->data);
1230
1231         if (unlikely(!task || !task->lldd_task || !task->dev))
1232                 return -EINVAL;
1233
1234         ts = &task->task_status;
1235         device = task->dev;
1236         sas_dev = device->lldd_dev;
1237
1238         task->task_state_flags &=
1239                 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1240         task->task_state_flags |= SAS_TASK_STATE_DONE;
1241
1242         memset(ts, 0, sizeof(*ts));
1243         ts->resp = SAS_TASK_COMPLETE;
1244
1245         if (unlikely(!sas_dev || abort)) {
1246                 if (!sas_dev)
1247                         dev_dbg(dev, "slot complete: port has not device\n");
1248                 ts->stat = SAS_PHY_DOWN;
1249                 goto out;
1250         }
1251
1252         if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) {
1253                 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO);
1254
1255                 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK)
1256                         dev_err(dev, "slot complete: [%d:%d] has dq IPTT err",
1257                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1258
1259                 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK)
1260                         dev_err(dev, "slot complete: [%d:%d] has dq type err",
1261                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1262
1263                 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK)
1264                         dev_err(dev, "slot complete: [%d:%d] has dq force phy err",
1265                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1266
1267                 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK)
1268                         dev_err(dev, "slot complete: [%d:%d] has dq phy id err",
1269                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1270
1271                 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK)
1272                         dev_err(dev, "slot complete: [%d:%d] has dq abort flag err",
1273                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1274
1275                 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK)
1276                         dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err",
1277                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1278
1279                 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK)
1280                         dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err",
1281                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1282
1283                 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK)
1284                         dev_err(dev, "slot complete: [%d:%d] has dq order frame len err",
1285                                 slot->cmplt_queue, slot->cmplt_queue_slot);
1286
1287                 ts->stat = SAS_OPEN_REJECT;
1288                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1289                 goto out;
1290         }
1291
1292         if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK) {
1293                 if (!(cmplt_hdr_data & CMPLT_HDR_CMD_CMPLT_MSK) ||
1294                     !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK))
1295                         ts->stat = SAS_DATA_OVERRUN;
1296                 else
1297                         slot_err_v1_hw(hisi_hba, task, slot);
1298
1299                 goto out;
1300         }
1301
1302         switch (task->task_proto) {
1303         case SAS_PROTOCOL_SSP:
1304         {
1305                 struct ssp_response_iu *iu = slot->status_buffer +
1306                         sizeof(struct hisi_sas_err_record);
1307                 sas_ssp_task_response(dev, task, iu);
1308                 break;
1309         }
1310         case SAS_PROTOCOL_SMP:
1311         {
1312                 void *to;
1313                 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1314
1315                 ts->stat = SAM_STAT_GOOD;
1316                 to = kmap_atomic(sg_page(sg_resp));
1317
1318                 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1319                              DMA_FROM_DEVICE);
1320                 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1321                              DMA_TO_DEVICE);
1322                 memcpy(to + sg_resp->offset,
1323                        slot->status_buffer +
1324                        sizeof(struct hisi_sas_err_record),
1325                        sg_dma_len(sg_resp));
1326                 kunmap_atomic(to);
1327                 break;
1328         }
1329         case SAS_PROTOCOL_SATA:
1330         case SAS_PROTOCOL_STP:
1331         case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1332                 dev_err(dev, "slot complete: SATA/STP not supported");
1333                 break;
1334
1335         default:
1336                 ts->stat = SAM_STAT_CHECK_CONDITION;
1337                 break;
1338         }
1339
1340         if (!slot->port->port_attached) {
1341                 dev_err(dev, "slot complete: port %d has removed\n",
1342                         slot->port->sas_port.id);
1343                 ts->stat = SAS_PHY_DOWN;
1344         }
1345
1346 out:
1347         if (sas_dev && sas_dev->running_req)
1348                 sas_dev->running_req--;
1349
1350         hisi_sas_slot_task_free(hisi_hba, task, slot);
1351         sts = ts->stat;
1352
1353         if (task->task_done)
1354                 task->task_done(task);
1355
1356         return sts;
1357 }
1358
1359 /* Interrupts */
1360 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p)
1361 {
1362         struct hisi_sas_phy *phy = p;
1363         struct hisi_hba *hisi_hba = phy->hisi_hba;
1364         struct device *dev = &hisi_hba->pdev->dev;
1365         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1366         int i, phy_no = sas_phy->id;
1367         u32 irq_value, context, port_id, link_rate;
1368         u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1369         struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1370         irqreturn_t res = IRQ_HANDLED;
1371
1372         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1373         if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) {
1374                 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n",
1375                         irq_value);
1376                 res = IRQ_NONE;
1377                 goto end;
1378         }
1379
1380         context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1381         if (context & 1 << phy_no) {
1382                 dev_err(dev, "phyup: phy%d SATA attached equipment\n",
1383                         phy_no);
1384                 goto end;
1385         }
1386
1387         port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no))
1388                   & 0xf;
1389         if (port_id == 0xf) {
1390                 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1391                 res = IRQ_NONE;
1392                 goto end;
1393         }
1394
1395         for (i = 0; i < 6; i++) {
1396                 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1397                                         RX_IDAF_DWORD0 + (i * 4));
1398                 frame_rcvd[i] = __swab32(idaf);
1399         }
1400
1401         /* Get the linkrate */
1402         link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1403         link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1404         sas_phy->linkrate = link_rate;
1405         sas_phy->oob_mode = SAS_OOB_MODE;
1406         memcpy(sas_phy->attached_sas_addr,
1407                 &id->sas_addr, SAS_ADDR_SIZE);
1408         dev_info(dev, "phyup: phy%d link_rate=%d\n",
1409                  phy_no, link_rate);
1410         phy->port_id = port_id;
1411         phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1412         phy->phy_type |= PORT_TYPE_SAS;
1413         phy->phy_attached = 1;
1414         phy->identify.device_type = id->dev_type;
1415         phy->frame_rcvd_size =  sizeof(struct sas_identify_frame);
1416         if (phy->identify.device_type == SAS_END_DEVICE)
1417                 phy->identify.target_port_protocols =
1418                         SAS_PROTOCOL_SSP;
1419         else if (phy->identify.device_type != SAS_PHY_UNUSED)
1420                 phy->identify.target_port_protocols =
1421                         SAS_PROTOCOL_SMP;
1422         queue_work(hisi_hba->wq, &phy->phyup_ws);
1423
1424 end:
1425         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1426                              CHL_INT2_SL_PHY_ENA_MSK);
1427
1428         if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) {
1429                 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1430
1431                 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK;
1432                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0);
1433                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee);
1434         }
1435
1436         return res;
1437 }
1438
1439 static irqreturn_t int_bcast_v1_hw(int irq, void *p)
1440 {
1441         struct hisi_sas_phy *phy = p;
1442         struct hisi_hba *hisi_hba = phy->hisi_hba;
1443         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1444         struct sas_ha_struct *sha = &hisi_hba->sha;
1445         struct device *dev = &hisi_hba->pdev->dev;
1446         int phy_no = sas_phy->id;
1447         u32 irq_value;
1448         irqreturn_t res = IRQ_HANDLED;
1449
1450         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1451
1452         if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) {
1453                 dev_err(dev, "bcast: irq_value = %x not set enable bit",
1454                         irq_value);
1455                 res = IRQ_NONE;
1456                 goto end;
1457         }
1458
1459         sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1460
1461 end:
1462         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2,
1463                              CHL_INT2_SL_RX_BC_ACK_MSK);
1464
1465         return res;
1466 }
1467
1468 static irqreturn_t int_abnormal_v1_hw(int irq, void *p)
1469 {
1470         struct hisi_sas_phy *phy = p;
1471         struct hisi_hba *hisi_hba = phy->hisi_hba;
1472         struct device *dev = &hisi_hba->pdev->dev;
1473         struct asd_sas_phy *sas_phy = &phy->sas_phy;
1474         u32 irq_value, irq_mask_old;
1475         int phy_no = sas_phy->id;
1476
1477         /* mask_int0 */
1478         irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK);
1479         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff);
1480
1481         /* read int0 */
1482         irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1483
1484         if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) {
1485                 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1486
1487                 hisi_sas_phy_down(hisi_hba, phy_no,
1488                                   (phy_state & 1 << phy_no) ? 1 : 0);
1489         }
1490
1491         if (irq_value & CHL_INT0_ID_TIMEOUT_MSK)
1492                 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n",
1493                         phy_no);
1494
1495         if (irq_value & CHL_INT0_DWS_LOST_MSK)
1496                 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no);
1497
1498         if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK)
1499                 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n",
1500                         phy_no);
1501
1502         if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK ||
1503                 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK)
1504                 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n",
1505                         phy_no);
1506
1507         if (irq_value & CHL_INT0_SL_PS_FAIL_OFF)
1508                 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no);
1509
1510         /* write to zero */
1511         hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value);
1512
1513         if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK)
1514                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1515                                 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1516         else
1517                 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK,
1518                                 irq_mask_old);
1519
1520         return IRQ_HANDLED;
1521 }
1522
1523 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
1524 {
1525         struct hisi_sas_cq *cq = p;
1526         struct hisi_hba *hisi_hba = cq->hisi_hba;
1527         struct hisi_sas_slot *slot;
1528         int queue = cq->id;
1529         struct hisi_sas_complete_v1_hdr *complete_queue =
1530                         (struct hisi_sas_complete_v1_hdr *)
1531                         hisi_hba->complete_hdr[queue];
1532         u32 irq_value, rd_point, wr_point;
1533
1534         irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1535
1536         hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1537
1538         rd_point = hisi_sas_read32(hisi_hba,
1539                         COMPL_Q_0_RD_PTR + (0x14 * queue));
1540         wr_point = hisi_sas_read32(hisi_hba,
1541                         COMPL_Q_0_WR_PTR + (0x14 * queue));
1542
1543         while (rd_point != wr_point) {
1544                 struct hisi_sas_complete_v1_hdr *complete_hdr;
1545                 int idx;
1546                 u32 cmplt_hdr_data;
1547
1548                 complete_hdr = &complete_queue[rd_point];
1549                 cmplt_hdr_data = cpu_to_le32(complete_hdr->data);
1550                 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >>
1551                       CMPLT_HDR_IPTT_OFF;
1552                 slot = &hisi_hba->slot_info[idx];
1553
1554                 /* The completion queue and queue slot index are not
1555                  * necessarily the same as the delivery queue and
1556                  * queue slot index.
1557                  */
1558                 slot->cmplt_queue_slot = rd_point;
1559                 slot->cmplt_queue = queue;
1560                 slot_complete_v1_hw(hisi_hba, slot, 0);
1561
1562                 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1563                         rd_point = 0;
1564         }
1565
1566         /* update rd_point */
1567         hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1568
1569         return IRQ_HANDLED;
1570 }
1571
1572 static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
1573 {
1574         struct hisi_hba *hisi_hba = p;
1575         struct device *dev = &hisi_hba->pdev->dev;
1576         u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1577
1578         if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
1579                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1580
1581                 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n",
1582                       dev_name(dev), ecc_err);
1583         }
1584
1585         if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) {
1586                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) &
1587                                 HGC_DQ_ECC_ADDR_BAD_MSK) >>
1588                                 HGC_DQ_ECC_ADDR_BAD_OFF;
1589
1590                 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n",
1591                       dev_name(dev), addr);
1592         }
1593
1594         if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) {
1595                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1596
1597                 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n",
1598                       dev_name(dev), ecc_err);
1599         }
1600
1601         if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) {
1602                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) &
1603                                 HGC_IOST_ECC_ADDR_BAD_MSK) >>
1604                                 HGC_IOST_ECC_ADDR_BAD_OFF;
1605
1606                 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n",
1607                       dev_name(dev), addr);
1608         }
1609
1610         if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) {
1611                 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) &
1612                                 HGC_ITCT_ECC_ADDR_BAD_MSK) >>
1613                                 HGC_ITCT_ECC_ADDR_BAD_OFF;
1614
1615                 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n",
1616                       dev_name(dev), addr);
1617         }
1618
1619         if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) {
1620                 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
1621
1622                 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n",
1623                       dev_name(dev), ecc_err);
1624         }
1625
1626         hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f);
1627
1628         return IRQ_HANDLED;
1629 }
1630
1631 static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
1632 {
1633         struct hisi_hba *hisi_hba = p;
1634         struct device *dev = &hisi_hba->pdev->dev;
1635         u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
1636         u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
1637
1638         if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK)
1639                 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n",
1640                       dev_name(dev), axi_info);
1641
1642         if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK)
1643                 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n",
1644                       dev_name(dev), axi_info);
1645
1646         if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK)
1647                 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n",
1648                       dev_name(dev), axi_info);
1649
1650         if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK)
1651                 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n",
1652                       dev_name(dev), axi_info);
1653
1654         hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000);
1655
1656         return IRQ_HANDLED;
1657 }
1658
1659 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1660         int_bcast_v1_hw,
1661         int_phyup_v1_hw,
1662         int_abnormal_v1_hw
1663 };
1664
1665 static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = {
1666         fatal_ecc_int_v1_hw,
1667         fatal_axi_int_v1_hw
1668 };
1669
1670 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
1671 {
1672         struct platform_device *pdev = hisi_hba->pdev;
1673         struct device *dev = &pdev->dev;
1674         int i, j, irq, rc, idx;
1675
1676         for (i = 0; i < hisi_hba->n_phy; i++) {
1677                 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1678
1679                 idx = i * HISI_SAS_PHY_INT_NR;
1680                 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) {
1681                         irq = platform_get_irq(pdev, idx);
1682                         if (!irq) {
1683                                 dev_err(dev,
1684                                         "irq init: fail map phy interrupt %d\n",
1685                                         idx);
1686                                 return -ENOENT;
1687                         }
1688
1689                         rc = devm_request_irq(dev, irq, phy_interrupts[j], 0,
1690                                               DRV_NAME " phy", phy);
1691                         if (rc) {
1692                                 dev_err(dev, "irq init: could not request "
1693                                         "phy interrupt %d, rc=%d\n",
1694                                         irq, rc);
1695                                 return -ENOENT;
1696                         }
1697                 }
1698         }
1699
1700         idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR;
1701         for (i = 0; i < hisi_hba->queue_count; i++, idx++) {
1702                 irq = platform_get_irq(pdev, idx);
1703                 if (!irq) {
1704                         dev_err(dev, "irq init: could not map cq interrupt %d\n",
1705                                 idx);
1706                         return -ENOENT;
1707                 }
1708
1709                 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0,
1710                                       DRV_NAME " cq", &hisi_hba->cq[i]);
1711                 if (rc) {
1712                         dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
1713                                 irq, rc);
1714                         return -ENOENT;
1715                 }
1716         }
1717
1718         idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count;
1719         for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) {
1720                 irq = platform_get_irq(pdev, idx);
1721                 if (!irq) {
1722                         dev_err(dev, "irq init: could not map fatal interrupt %d\n",
1723                                 idx);
1724                         return -ENOENT;
1725                 }
1726
1727                 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
1728                                       DRV_NAME " fatal", hisi_hba);
1729                 if (rc) {
1730                         dev_err(dev,
1731                                 "irq init: could not request fatal interrupt %d, rc=%d\n",
1732                                 irq, rc);
1733                         return -ENOENT;
1734                 }
1735         }
1736
1737         return 0;
1738 }
1739
1740 static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba)
1741 {
1742         int i;
1743         u32 val;
1744
1745         for (i = 0; i < hisi_hba->n_phy; i++) {
1746                 /* Clear interrupt status */
1747                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0);
1748                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val);
1749                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1);
1750                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val);
1751                 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2);
1752                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val);
1753
1754                 /* Unmask interrupt */
1755                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee);
1756                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff);
1757                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a);
1758
1759                 /* bypass chip bug mask abnormal intr */
1760                 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK,
1761                                 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK);
1762         }
1763
1764         return 0;
1765 }
1766
1767 static int hisi_sas_v1_init(struct hisi_hba *hisi_hba)
1768 {
1769         int rc;
1770
1771         rc = hw_init_v1_hw(hisi_hba);
1772         if (rc)
1773                 return rc;
1774
1775         rc = interrupt_init_v1_hw(hisi_hba);
1776         if (rc)
1777                 return rc;
1778
1779         rc = interrupt_openall_v1_hw(hisi_hba);
1780         if (rc)
1781                 return rc;
1782
1783         phys_init_v1_hw(hisi_hba);
1784
1785         return 0;
1786 }
1787
1788 static const struct hisi_sas_hw hisi_sas_v1_hw = {
1789         .hw_init = hisi_sas_v1_init,
1790         .setup_itct = setup_itct_v1_hw,
1791         .sl_notify = sl_notify_v1_hw,
1792         .free_device = free_device_v1_hw,
1793         .prep_smp = prep_smp_v1_hw,
1794         .prep_ssp = prep_ssp_v1_hw,
1795         .get_free_slot = get_free_slot_v1_hw,
1796         .start_delivery = start_delivery_v1_hw,
1797         .slot_complete = slot_complete_v1_hw,
1798         .phy_enable = enable_phy_v1_hw,
1799         .phy_disable = disable_phy_v1_hw,
1800         .phy_hard_reset = phy_hard_reset_v1_hw,
1801         .get_wideport_bitmap = get_wideport_bitmap_v1_hw,
1802         .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr),
1803 };
1804
1805 static int hisi_sas_v1_probe(struct platform_device *pdev)
1806 {
1807         return hisi_sas_probe(pdev, &hisi_sas_v1_hw);
1808 }
1809
1810 static int hisi_sas_v1_remove(struct platform_device *pdev)
1811 {
1812         return hisi_sas_remove(pdev);
1813 }
1814
1815 static const struct of_device_id sas_v1_of_match[] = {
1816         { .compatible = "hisilicon,hip05-sas-v1",},
1817         {},
1818 };
1819 MODULE_DEVICE_TABLE(of, sas_v1_of_match);
1820
1821 static struct platform_driver hisi_sas_v1_driver = {
1822         .probe = hisi_sas_v1_probe,
1823         .remove = hisi_sas_v1_remove,
1824         .driver = {
1825                 .name = DRV_NAME,
1826                 .of_match_table = sas_v1_of_match,
1827         },
1828 };
1829
1830 module_platform_driver(hisi_sas_v1_driver);
1831
1832 MODULE_LICENSE("GPL");
1833 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1834 MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver");
1835 MODULE_ALIAS("platform:" DRV_NAME);