2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/blk-iopoll.h>
36 #include <scsi/scsi.h>
37 #include <scsi/scsi_cmnd.h>
42 #define IPR_DRIVER_VERSION "2.6.0"
43 #define IPR_DRIVER_DATE "(November 16, 2012)"
46 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
47 * ops per device for devices not running tagged command queuing.
48 * This can be adjusted at runtime through sysfs device attributes.
50 #define IPR_MAX_CMD_PER_LUN 6
51 #define IPR_MAX_CMD_PER_ATA_LUN 1
54 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
55 * ops the mid-layer can send to the adapter.
57 #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
59 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
61 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
62 #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
64 #define IPR_SUBS_DEV_ID_2780 0x0264
65 #define IPR_SUBS_DEV_ID_5702 0x0266
66 #define IPR_SUBS_DEV_ID_5703 0x0278
67 #define IPR_SUBS_DEV_ID_572E 0x028D
68 #define IPR_SUBS_DEV_ID_573E 0x02D3
69 #define IPR_SUBS_DEV_ID_573D 0x02D4
70 #define IPR_SUBS_DEV_ID_571A 0x02C0
71 #define IPR_SUBS_DEV_ID_571B 0x02BE
72 #define IPR_SUBS_DEV_ID_571E 0x02BF
73 #define IPR_SUBS_DEV_ID_571F 0x02D5
74 #define IPR_SUBS_DEV_ID_572A 0x02C1
75 #define IPR_SUBS_DEV_ID_572B 0x02C2
76 #define IPR_SUBS_DEV_ID_572F 0x02C3
77 #define IPR_SUBS_DEV_ID_574E 0x030A
78 #define IPR_SUBS_DEV_ID_575B 0x030D
79 #define IPR_SUBS_DEV_ID_575C 0x0338
80 #define IPR_SUBS_DEV_ID_57B3 0x033A
81 #define IPR_SUBS_DEV_ID_57B7 0x0360
82 #define IPR_SUBS_DEV_ID_57B8 0x02C2
84 #define IPR_SUBS_DEV_ID_57B4 0x033B
85 #define IPR_SUBS_DEV_ID_57B2 0x035F
86 #define IPR_SUBS_DEV_ID_57C0 0x0352
87 #define IPR_SUBS_DEV_ID_57C3 0x0353
88 #define IPR_SUBS_DEV_ID_57C4 0x0354
89 #define IPR_SUBS_DEV_ID_57C6 0x0357
90 #define IPR_SUBS_DEV_ID_57CC 0x035C
92 #define IPR_SUBS_DEV_ID_57B5 0x033C
93 #define IPR_SUBS_DEV_ID_57CE 0x035E
94 #define IPR_SUBS_DEV_ID_57B1 0x0355
96 #define IPR_SUBS_DEV_ID_574D 0x0356
97 #define IPR_SUBS_DEV_ID_57C8 0x035D
99 #define IPR_SUBS_DEV_ID_57D5 0x03FB
100 #define IPR_SUBS_DEV_ID_57D6 0x03FC
101 #define IPR_SUBS_DEV_ID_57D7 0x03FF
102 #define IPR_SUBS_DEV_ID_57D8 0x03FE
103 #define IPR_SUBS_DEV_ID_57D9 0x046D
104 #define IPR_SUBS_DEV_ID_57DA 0x04CA
105 #define IPR_SUBS_DEV_ID_57EB 0x0474
106 #define IPR_SUBS_DEV_ID_57EC 0x0475
107 #define IPR_SUBS_DEV_ID_57ED 0x0499
108 #define IPR_SUBS_DEV_ID_57EE 0x049A
109 #define IPR_SUBS_DEV_ID_57EF 0x049B
110 #define IPR_SUBS_DEV_ID_57F0 0x049C
111 #define IPR_NAME "ipr"
116 #define IPR_RC_JOB_CONTINUE 1
117 #define IPR_RC_JOB_RETURN 2
122 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
123 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
124 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
125 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
126 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
127 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
128 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
129 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
130 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
131 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
132 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
133 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
134 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
135 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
136 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
138 #define IPR_FIRST_DRIVER_IOASC 0x10000000
139 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
140 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
142 /* Driver data flags */
143 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
144 #define IPR_USE_PCI_WARM_RESET 0x00000002
146 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
147 #define IPR_NUM_LOG_HCAMS 2
148 #define IPR_NUM_CFG_CHG_HCAMS 2
149 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
151 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
152 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
154 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
155 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
156 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
157 #define IPR_VSET_BUS 0xff
158 #define IPR_IOA_BUS 0xff
159 #define IPR_IOA_TARGET 0xff
160 #define IPR_IOA_LUN 0xff
161 #define IPR_MAX_NUM_BUSES 16
162 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
164 #define IPR_NUM_RESET_RELOAD_RETRIES 3
166 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
167 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
168 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
170 #define IPR_MAX_COMMANDS 100
171 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
172 IPR_NUM_INTERNAL_CMD_BLKS)
174 #define IPR_MAX_PHYSICAL_DEVS 192
175 #define IPR_DEFAULT_SIS64_DEVS 1024
176 #define IPR_MAX_SIS64_DEVS 4096
178 #define IPR_MAX_SGLIST 64
179 #define IPR_IOA_MAX_SECTORS 32767
180 #define IPR_VSET_MAX_SECTORS 512
181 #define IPR_MAX_CDB_LEN 16
182 #define IPR_MAX_HRRQ_RETRIES 3
184 #define IPR_DEFAULT_BUS_WIDTH 16
185 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
186 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
187 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
188 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
190 #define IPR_IOA_RES_HANDLE 0xffffffff
191 #define IPR_INVALID_RES_HANDLE 0
192 #define IPR_IOA_RES_ADDR 0x00ffffff
197 #define IPR_QUERY_RSRC_STATE 0xC2
198 #define IPR_RESET_DEVICE 0xC3
199 #define IPR_RESET_TYPE_SELECT 0x80
200 #define IPR_LUN_RESET 0x40
201 #define IPR_TARGET_RESET 0x20
202 #define IPR_BUS_RESET 0x10
203 #define IPR_ATA_PHY_RESET 0x80
204 #define IPR_ID_HOST_RR_Q 0xC4
205 #define IPR_QUERY_IOA_CONFIG 0xC5
206 #define IPR_CANCEL_ALL_REQUESTS 0xCE
207 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
208 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
209 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
210 #define IPR_SET_SUPPORTED_DEVICES 0xFB
211 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
212 #define IPR_IOA_SHUTDOWN 0xF7
213 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
218 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
219 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
220 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
221 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
222 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
223 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
224 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
225 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
226 #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
227 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
228 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
229 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
230 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
231 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
232 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
233 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
234 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
235 #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
236 #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
237 #define IPR_DUMP_DELAY_SECONDS 4
238 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
243 #define IPR_VENDOR_ID_LEN 8
244 #define IPR_PROD_ID_LEN 16
245 #define IPR_SERIAL_NUM_LEN 8
250 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
251 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
252 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
253 #define IPR_GET_FMT2_BAR_SEL(mbx) \
254 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
255 #define IPR_SDT_FMT2_BAR0_SEL 0x0
256 #define IPR_SDT_FMT2_BAR1_SEL 0x1
257 #define IPR_SDT_FMT2_BAR2_SEL 0x2
258 #define IPR_SDT_FMT2_BAR3_SEL 0x3
259 #define IPR_SDT_FMT2_BAR4_SEL 0x4
260 #define IPR_SDT_FMT2_BAR5_SEL 0x5
261 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
262 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
263 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
264 #define IPR_DOORBELL 0x82800000
265 #define IPR_RUNTIME_RESET 0x40000000
267 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
268 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
269 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
270 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
271 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
272 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
273 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
275 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
276 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
277 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
278 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
279 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
280 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
281 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
282 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
283 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
284 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
285 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
287 #define IPR_PCII_ERROR_INTERRUPTS \
288 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
289 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
291 #define IPR_PCII_OPER_INTERRUPTS \
292 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
294 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
295 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
296 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
298 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
299 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
304 #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
305 #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024)
306 #define IPR_FMT2_NUM_SDT_ENTRIES 511
307 #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
308 #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
309 #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
314 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
315 #define IPR_MAX_MSIX_VECTORS 0x10
316 #define IPR_MAX_HRRQ_NUM 0x10
317 #define IPR_INIT_HRRQ 0x0
320 * Adapter interface types
323 struct ipr_res_addr {
328 #define IPR_GET_PHYS_LOC(res_addr) \
329 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
330 }__attribute__((packed, aligned (4)));
332 struct ipr_std_inq_vpids {
333 u8 vendor_id[IPR_VENDOR_ID_LEN];
334 u8 product_id[IPR_PROD_ID_LEN];
335 }__attribute__((packed));
338 struct ipr_std_inq_vpids vpids;
339 u8 sn[IPR_SERIAL_NUM_LEN];
340 }__attribute__((packed));
345 }__attribute__((packed));
347 struct ipr_ext_vpd64 {
350 }__attribute__((packed));
352 struct ipr_std_inq_data {
353 u8 peri_qual_dev_type;
354 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
355 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
357 u8 removeable_medium_rsvd;
358 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
360 #define IPR_IS_DASD_DEVICE(std_inq) \
361 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
362 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
364 #define IPR_IS_SES_DEVICE(std_inq) \
365 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
374 struct ipr_std_inq_vpids vpids;
376 u8 ros_rsvd_ram_rsvd[4];
378 u8 serial_num[IPR_SERIAL_NUM_LEN];
379 }__attribute__ ((packed));
381 #define IPR_RES_TYPE_AF_DASD 0x00
382 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
383 #define IPR_RES_TYPE_VOLUME_SET 0x02
384 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
385 #define IPR_RES_TYPE_GENERIC_ATA 0x04
386 #define IPR_RES_TYPE_ARRAY 0x05
387 #define IPR_RES_TYPE_IOAFP 0xff
389 struct ipr_config_table_entry {
391 #define IPR_PROTO_SATA 0x02
392 #define IPR_PROTO_SATA_ATAPI 0x03
393 #define IPR_PROTO_SAS_STP 0x06
394 #define IPR_PROTO_SAS_STP_ATAPI 0x07
397 #define IPR_IS_IOA_RESOURCE 0x80
400 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
401 #define IPR_QUEUE_FROZEN_MODEL 0
402 #define IPR_QUEUE_NACA_MODEL 1
404 struct ipr_res_addr res_addr;
407 struct ipr_std_inq_data std_inq_data;
408 }__attribute__ ((packed, aligned (4)));
410 struct ipr_config_table_entry64 {
417 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
424 #define IPR_MAX_RES_PATH_LENGTH 48
426 struct ipr_std_inq_data std_inq_data;
430 }__attribute__ ((packed, aligned (8)));
432 struct ipr_config_table_hdr {
435 #define IPR_UCODE_DOWNLOAD_REQ 0x10
437 }__attribute__((packed, aligned (4)));
439 struct ipr_config_table_hdr64 {
444 }__attribute__((packed, aligned (4)));
446 struct ipr_config_table {
447 struct ipr_config_table_hdr hdr;
448 struct ipr_config_table_entry dev[0];
449 }__attribute__((packed, aligned (4)));
451 struct ipr_config_table64 {
452 struct ipr_config_table_hdr64 hdr64;
453 struct ipr_config_table_entry64 dev[0];
454 }__attribute__((packed, aligned (8)));
456 struct ipr_config_table_entry_wrapper {
458 struct ipr_config_table_entry *cfgte;
459 struct ipr_config_table_entry64 *cfgte64;
463 struct ipr_hostrcb_cfg_ch_not {
465 struct ipr_config_table_entry cfgte;
466 struct ipr_config_table_entry64 cfgte64;
469 }__attribute__((packed, aligned (4)));
471 struct ipr_supported_device {
475 struct ipr_std_inq_vpids vpids;
477 }__attribute__((packed, aligned (4)));
479 struct ipr_hrr_queue {
480 struct ipr_ioa_cfg *ioa_cfg;
482 dma_addr_t host_rrq_dma;
483 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
484 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
485 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
486 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
487 #define IPR_ID_HRRQ_SELE_ENABLE 0x02
488 volatile __be32 *hrrq_start;
489 volatile __be32 *hrrq_end;
490 volatile __be32 *hrrq_curr;
492 struct list_head hrrq_free_q;
493 struct list_head hrrq_pending_q;
497 volatile u32 toggle_bit;
501 u8 allow_interrupts:1;
506 struct blk_iopoll iopoll;
509 /* Command packet structure */
511 u8 reserved; /* Reserved by IOA */
514 #define IPR_RQTYPE_SCSICDB 0x00
515 #define IPR_RQTYPE_IOACMD 0x01
516 #define IPR_RQTYPE_HCAM 0x02
517 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
522 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
523 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
524 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
525 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
526 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
529 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
530 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
531 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
532 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
533 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
534 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
535 #define IPR_FLAGS_LO_ACA_TASK 0x08
539 }__attribute__ ((packed, aligned(4)));
541 struct ipr_ioarcb_ata_regs { /* 22 bytes */
543 #define IPR_ATA_FLAG_PACKET_CMD 0x80
544 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
545 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
563 }__attribute__ ((packed, aligned(2)));
565 struct ipr_ioadl_desc {
566 __be32 flags_and_data_len;
567 #define IPR_IOADL_FLAGS_MASK 0xff000000
568 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
569 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
570 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
571 #define IPR_IOADL_FLAGS_READ 0x48000000
572 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
573 #define IPR_IOADL_FLAGS_WRITE 0x68000000
574 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
575 #define IPR_IOADL_FLAGS_LAST 0x01000000
578 }__attribute__((packed, aligned (8)));
580 struct ipr_ioadl64_desc {
584 }__attribute__((packed, aligned (16)));
586 struct ipr_ata64_ioadl {
587 struct ipr_ioarcb_ata_regs regs;
589 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
590 }__attribute__((packed, aligned (16)));
592 struct ipr_ioarcb_add_data {
594 struct ipr_ioarcb_ata_regs regs;
595 struct ipr_ioadl_desc ioadl[5];
596 __be32 add_cmd_parms[10];
598 }__attribute__ ((packed, aligned (4)));
600 struct ipr_ioarcb_sis64_add_addr_ecb {
601 __be64 ioasa_host_pci_addr;
602 __be64 data_ioadl_addr;
604 __be32 ext_control_buf[4];
605 }__attribute__((packed, aligned (8)));
607 /* IOA Request Control Block 128 bytes */
610 __be32 ioarcb_host_pci_addr;
611 __be64 ioarcb_host_pci_addr64;
614 __be32 host_response_handle;
619 __be32 data_transfer_length;
620 __be32 read_data_transfer_length;
621 __be32 write_ioadl_addr;
623 __be32 read_ioadl_addr;
624 __be32 read_ioadl_len;
626 __be32 ioasa_host_pci_addr;
630 struct ipr_cmd_pkt cmd_pkt;
632 __be16 add_cmd_parms_offset;
633 __be16 add_cmd_parms_len;
636 struct ipr_ioarcb_add_data add_data;
637 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
640 }__attribute__((packed, aligned (4)));
642 struct ipr_ioasa_vset {
643 __be32 failing_lba_hi;
644 __be32 failing_lba_lo;
646 }__attribute__((packed, aligned (4)));
648 struct ipr_ioasa_af_dasd {
651 }__attribute__((packed, aligned (4)));
653 struct ipr_ioasa_gpdd {
658 }__attribute__((packed, aligned (4)));
660 struct ipr_ioasa_gata {
662 u8 nsect; /* Interrupt reason */
668 u8 alt_status; /* ATA CTL */
673 }__attribute__((packed, aligned (4)));
675 struct ipr_auto_sense {
676 __be16 auto_sense_len;
678 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
681 struct ipr_ioasa_hdr {
683 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
684 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
685 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
686 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
688 __be16 ret_stat_len; /* Length of the returned IOASA */
690 __be16 avail_stat_len; /* Total Length of status available. */
692 __be32 residual_data_len; /* number of bytes in the host data */
693 /* buffers that were not used by the IOARCB command. */
696 #define IPR_NO_ILID 0
697 #define IPR_DRIVER_ILID 0xffffffff
701 __be32 fd_phys_locator;
703 __be32 fd_res_handle;
705 __be32 ioasc_specific; /* status code specific field */
706 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
707 #define IPR_AUTOSENSE_VALID 0x40000000
708 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
709 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
710 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
711 #define IPR_FIELD_POINTER_MASK 0x0000ffff
713 }__attribute__((packed, aligned (4)));
716 struct ipr_ioasa_hdr hdr;
719 struct ipr_ioasa_vset vset;
720 struct ipr_ioasa_af_dasd dasd;
721 struct ipr_ioasa_gpdd gpdd;
722 struct ipr_ioasa_gata gata;
725 struct ipr_auto_sense auto_sense;
726 }__attribute__((packed, aligned (4)));
729 struct ipr_ioasa_hdr hdr;
733 struct ipr_ioasa_vset vset;
734 struct ipr_ioasa_af_dasd dasd;
735 struct ipr_ioasa_gpdd gpdd;
736 struct ipr_ioasa_gata gata;
739 struct ipr_auto_sense auto_sense;
740 }__attribute__((packed, aligned (4)));
742 struct ipr_mode_parm_hdr {
745 u8 device_spec_parms;
747 }__attribute__((packed));
749 struct ipr_mode_pages {
750 struct ipr_mode_parm_hdr hdr;
751 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
752 }__attribute__((packed));
754 struct ipr_mode_page_hdr {
756 #define IPR_MODE_PAGE_PS 0x80
757 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
759 }__attribute__ ((packed));
761 struct ipr_dev_bus_entry {
762 struct ipr_res_addr res_addr;
764 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
765 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
766 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
767 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
768 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
769 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
770 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
774 u8 extended_reset_delay;
775 #define IPR_EXTENDED_RESET_DELAY 7
777 __be32 max_xfer_rate;
782 }__attribute__((packed, aligned (4)));
784 struct ipr_mode_page28 {
785 struct ipr_mode_page_hdr hdr;
788 struct ipr_dev_bus_entry bus[0];
789 }__attribute__((packed));
791 struct ipr_mode_page24 {
792 struct ipr_mode_page_hdr hdr;
794 #define IPR_ENABLE_DUAL_IOA_AF 0x80
795 }__attribute__((packed));
798 struct ipr_std_inq_data std_inq_data;
799 u8 ascii_part_num[12];
801 u8 ascii_plant_code[4];
802 }__attribute__((packed));
804 struct ipr_inquiry_page3 {
805 u8 peri_qual_dev_type;
817 }__attribute__((packed));
819 struct ipr_inquiry_cap {
820 u8 peri_qual_dev_type;
828 #define IPR_CAP_DUAL_IOA_RAID 0x80
830 }__attribute__((packed));
832 #define IPR_INQUIRY_PAGE0_ENTRIES 20
833 struct ipr_inquiry_page0 {
834 u8 peri_qual_dev_type;
838 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
839 }__attribute__((packed));
841 struct ipr_hostrcb_device_data_entry {
843 struct ipr_res_addr dev_res_addr;
844 struct ipr_vpd new_vpd;
845 struct ipr_vpd ioa_last_with_dev_vpd;
846 struct ipr_vpd cfc_last_with_dev_vpd;
848 }__attribute__((packed, aligned (4)));
850 struct ipr_hostrcb_device_data_entry_enhanced {
851 struct ipr_ext_vpd vpd;
853 struct ipr_res_addr dev_res_addr;
854 struct ipr_ext_vpd new_vpd;
856 struct ipr_ext_vpd ioa_last_with_dev_vpd;
857 struct ipr_ext_vpd cfc_last_with_dev_vpd;
858 }__attribute__((packed, aligned (4)));
860 struct ipr_hostrcb64_device_data_entry_enhanced {
861 struct ipr_ext_vpd vpd;
864 struct ipr_ext_vpd new_vpd;
866 struct ipr_ext_vpd ioa_last_with_dev_vpd;
867 struct ipr_ext_vpd cfc_last_with_dev_vpd;
868 }__attribute__((packed, aligned (4)));
870 struct ipr_hostrcb_array_data_entry {
872 struct ipr_res_addr expected_dev_res_addr;
873 struct ipr_res_addr dev_res_addr;
874 }__attribute__((packed, aligned (4)));
876 struct ipr_hostrcb64_array_data_entry {
877 struct ipr_ext_vpd vpd;
879 u8 expected_res_path[8];
881 }__attribute__((packed, aligned (4)));
883 struct ipr_hostrcb_array_data_entry_enhanced {
884 struct ipr_ext_vpd vpd;
886 struct ipr_res_addr expected_dev_res_addr;
887 struct ipr_res_addr dev_res_addr;
888 }__attribute__((packed, aligned (4)));
890 struct ipr_hostrcb_type_ff_error {
891 __be32 ioa_data[758];
892 }__attribute__((packed, aligned (4)));
894 struct ipr_hostrcb_type_01_error {
898 __be32 ioa_data[236];
899 }__attribute__((packed, aligned (4)));
901 struct ipr_hostrcb_type_02_error {
902 struct ipr_vpd ioa_vpd;
903 struct ipr_vpd cfc_vpd;
904 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
905 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
907 }__attribute__((packed, aligned (4)));
909 struct ipr_hostrcb_type_12_error {
910 struct ipr_ext_vpd ioa_vpd;
911 struct ipr_ext_vpd cfc_vpd;
912 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
913 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
915 }__attribute__((packed, aligned (4)));
917 struct ipr_hostrcb_type_03_error {
918 struct ipr_vpd ioa_vpd;
919 struct ipr_vpd cfc_vpd;
920 __be32 errors_detected;
921 __be32 errors_logged;
923 struct ipr_hostrcb_device_data_entry dev[3];
924 }__attribute__((packed, aligned (4)));
926 struct ipr_hostrcb_type_13_error {
927 struct ipr_ext_vpd ioa_vpd;
928 struct ipr_ext_vpd cfc_vpd;
929 __be32 errors_detected;
930 __be32 errors_logged;
931 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
932 }__attribute__((packed, aligned (4)));
934 struct ipr_hostrcb_type_23_error {
935 struct ipr_ext_vpd ioa_vpd;
936 struct ipr_ext_vpd cfc_vpd;
937 __be32 errors_detected;
938 __be32 errors_logged;
939 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
940 }__attribute__((packed, aligned (4)));
942 struct ipr_hostrcb_type_04_error {
943 struct ipr_vpd ioa_vpd;
944 struct ipr_vpd cfc_vpd;
946 struct ipr_hostrcb_array_data_entry array_member[10];
947 __be32 exposed_mode_adn;
949 struct ipr_vpd incomp_dev_vpd;
951 struct ipr_hostrcb_array_data_entry array_member2[8];
952 struct ipr_res_addr last_func_vset_res_addr;
953 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
954 u8 protection_level[8];
955 }__attribute__((packed, aligned (4)));
957 struct ipr_hostrcb_type_14_error {
958 struct ipr_ext_vpd ioa_vpd;
959 struct ipr_ext_vpd cfc_vpd;
960 __be32 exposed_mode_adn;
962 struct ipr_res_addr last_func_vset_res_addr;
963 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
964 u8 protection_level[8];
966 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
967 }__attribute__((packed, aligned (4)));
969 struct ipr_hostrcb_type_24_error {
970 struct ipr_ext_vpd ioa_vpd;
971 struct ipr_ext_vpd cfc_vpd;
974 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
977 u8 protection_level[8];
978 struct ipr_ext_vpd64 array_vpd;
982 struct ipr_hostrcb64_array_data_entry array_member[32];
983 }__attribute__((packed, aligned (4)));
985 struct ipr_hostrcb_type_07_error {
986 u8 failure_reason[64];
989 }__attribute__((packed, aligned (4)));
991 struct ipr_hostrcb_type_17_error {
992 u8 failure_reason[64];
993 struct ipr_ext_vpd vpd;
995 }__attribute__((packed, aligned (4)));
997 struct ipr_hostrcb_config_element {
999 #define IPR_PATH_CFG_TYPE_MASK 0xF0
1000 #define IPR_PATH_CFG_NOT_EXIST 0x00
1001 #define IPR_PATH_CFG_IOA_PORT 0x10
1002 #define IPR_PATH_CFG_EXP_PORT 0x20
1003 #define IPR_PATH_CFG_DEVICE_PORT 0x30
1004 #define IPR_PATH_CFG_DEVICE_LUN 0x40
1006 #define IPR_PATH_CFG_STATUS_MASK 0x0F
1007 #define IPR_PATH_CFG_NO_PROB 0x00
1008 #define IPR_PATH_CFG_DEGRADED 0x01
1009 #define IPR_PATH_CFG_FAILED 0x02
1010 #define IPR_PATH_CFG_SUSPECT 0x03
1011 #define IPR_PATH_NOT_DETECTED 0x04
1012 #define IPR_PATH_INCORRECT_CONN 0x05
1014 u8 cascaded_expander;
1017 #define IPR_PHY_LINK_RATE_MASK 0x0F
1020 }__attribute__((packed, aligned (4)));
1022 struct ipr_hostrcb64_config_element {
1025 #define IPR_DESCRIPTOR_MASK 0xC0
1026 #define IPR_DESCRIPTOR_SIS64 0x00
1036 }__attribute__((packed, aligned (8)));
1038 struct ipr_hostrcb_fabric_desc {
1041 u8 cascaded_expander;
1044 #define IPR_PATH_ACTIVE_MASK 0xC0
1045 #define IPR_PATH_NO_INFO 0x00
1046 #define IPR_PATH_ACTIVE 0x40
1047 #define IPR_PATH_NOT_ACTIVE 0x80
1049 #define IPR_PATH_STATE_MASK 0x0F
1050 #define IPR_PATH_STATE_NO_INFO 0x00
1051 #define IPR_PATH_HEALTHY 0x01
1052 #define IPR_PATH_DEGRADED 0x02
1053 #define IPR_PATH_FAILED 0x03
1056 struct ipr_hostrcb_config_element elem[1];
1057 }__attribute__((packed, aligned (4)));
1059 struct ipr_hostrcb64_fabric_desc {
1070 struct ipr_hostrcb64_config_element elem[1];
1071 }__attribute__((packed, aligned (8)));
1073 #define for_each_hrrq(hrrq, ioa_cfg) \
1074 for (hrrq = (ioa_cfg)->hrrq; \
1075 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1077 #define for_each_fabric_cfg(fabric, cfg) \
1078 for (cfg = (fabric)->elem; \
1079 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1082 struct ipr_hostrcb_type_20_error {
1083 u8 failure_reason[64];
1086 struct ipr_hostrcb_fabric_desc desc[1];
1087 }__attribute__((packed, aligned (4)));
1089 struct ipr_hostrcb_type_30_error {
1090 u8 failure_reason[64];
1093 struct ipr_hostrcb64_fabric_desc desc[1];
1094 }__attribute__((packed, aligned (4)));
1096 struct ipr_hostrcb_error {
1098 struct ipr_res_addr fd_res_addr;
1099 __be32 fd_res_handle;
1102 struct ipr_hostrcb_type_ff_error type_ff_error;
1103 struct ipr_hostrcb_type_01_error type_01_error;
1104 struct ipr_hostrcb_type_02_error type_02_error;
1105 struct ipr_hostrcb_type_03_error type_03_error;
1106 struct ipr_hostrcb_type_04_error type_04_error;
1107 struct ipr_hostrcb_type_07_error type_07_error;
1108 struct ipr_hostrcb_type_12_error type_12_error;
1109 struct ipr_hostrcb_type_13_error type_13_error;
1110 struct ipr_hostrcb_type_14_error type_14_error;
1111 struct ipr_hostrcb_type_17_error type_17_error;
1112 struct ipr_hostrcb_type_20_error type_20_error;
1114 }__attribute__((packed, aligned (4)));
1116 struct ipr_hostrcb64_error {
1118 __be32 ioa_fw_level;
1119 __be32 fd_res_handle;
1127 struct ipr_hostrcb_type_ff_error type_ff_error;
1128 struct ipr_hostrcb_type_12_error type_12_error;
1129 struct ipr_hostrcb_type_17_error type_17_error;
1130 struct ipr_hostrcb_type_23_error type_23_error;
1131 struct ipr_hostrcb_type_24_error type_24_error;
1132 struct ipr_hostrcb_type_30_error type_30_error;
1134 }__attribute__((packed, aligned (8)));
1136 struct ipr_hostrcb_raw {
1137 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1138 }__attribute__((packed, aligned (4)));
1142 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1143 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1146 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1147 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1148 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1149 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1150 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1152 u8 notifications_lost;
1153 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1154 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1157 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1158 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1161 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1162 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1163 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1164 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1165 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1166 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1167 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1168 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1169 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1170 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1171 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1172 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1173 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1174 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1175 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1176 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1177 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1181 __be32 time_since_last_ioa_reset;
1186 struct ipr_hostrcb_error error;
1187 struct ipr_hostrcb64_error error64;
1188 struct ipr_hostrcb_cfg_ch_not ccn;
1189 struct ipr_hostrcb_raw raw;
1191 }__attribute__((packed, aligned (4)));
1193 struct ipr_hostrcb {
1194 struct ipr_hcam hcam;
1195 dma_addr_t hostrcb_dma;
1196 struct list_head queue;
1197 struct ipr_ioa_cfg *ioa_cfg;
1198 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1201 /* IPR smart dump table structures */
1202 struct ipr_sdt_entry {
1208 #define IPR_SDT_ENDIAN 0x80
1209 #define IPR_SDT_VALID_ENTRY 0x20
1213 }__attribute__((packed, aligned (4)));
1215 struct ipr_sdt_header {
1218 __be32 num_entries_used;
1220 }__attribute__((packed, aligned (4)));
1223 struct ipr_sdt_header hdr;
1224 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1225 }__attribute__((packed, aligned (4)));
1228 struct ipr_sdt_header hdr;
1229 struct ipr_sdt_entry entry[1];
1230 }__attribute__((packed, aligned (4)));
1235 struct ipr_bus_attributes {
1243 struct ipr_sata_port {
1244 struct ipr_ioa_cfg *ioa_cfg;
1245 struct ata_port *ap;
1246 struct ipr_resource_entry *res;
1247 struct ipr_ioasa_gata ioasa;
1250 struct ipr_resource_entry {
1251 u8 needs_sync_complete:1;
1255 u8 resetting_device:1;
1256 u8 reset_occurred:1;
1258 u32 bus; /* AKA channel */
1259 u32 target; /* AKA id */
1261 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1262 #define IPR_VSET_VIRTUAL_BUS 0x2
1263 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1265 #define IPR_GET_RES_PHYS_LOC(res) \
1266 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1276 struct ipr_std_inq_data std_inq_data;
1281 struct scsi_lun dev_lun;
1284 struct ipr_ioa_cfg *ioa_cfg;
1285 struct scsi_device *sdev;
1286 struct ipr_sata_port *sata_port;
1287 struct list_head queue;
1288 }; /* struct ipr_resource_entry */
1290 struct ipr_resource_hdr {
1295 struct ipr_misc_cbs {
1296 struct ipr_ioa_vpd ioa_vpd;
1297 struct ipr_inquiry_page0 page0_data;
1298 struct ipr_inquiry_page3 page3_data;
1299 struct ipr_inquiry_cap cap;
1300 struct ipr_mode_pages mode_pages;
1301 struct ipr_supported_device supp_dev;
1304 struct ipr_interrupt_offsets {
1305 unsigned long set_interrupt_mask_reg;
1306 unsigned long clr_interrupt_mask_reg;
1307 unsigned long clr_interrupt_mask_reg32;
1308 unsigned long sense_interrupt_mask_reg;
1309 unsigned long sense_interrupt_mask_reg32;
1310 unsigned long clr_interrupt_reg;
1311 unsigned long clr_interrupt_reg32;
1313 unsigned long sense_interrupt_reg;
1314 unsigned long sense_interrupt_reg32;
1315 unsigned long ioarrin_reg;
1316 unsigned long sense_uproc_interrupt_reg;
1317 unsigned long sense_uproc_interrupt_reg32;
1318 unsigned long set_uproc_interrupt_reg;
1319 unsigned long set_uproc_interrupt_reg32;
1320 unsigned long clr_uproc_interrupt_reg;
1321 unsigned long clr_uproc_interrupt_reg32;
1323 unsigned long init_feedback_reg;
1325 unsigned long dump_addr_reg;
1326 unsigned long dump_data_reg;
1328 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1329 unsigned long endian_swap_reg;
1332 struct ipr_interrupts {
1333 void __iomem *set_interrupt_mask_reg;
1334 void __iomem *clr_interrupt_mask_reg;
1335 void __iomem *clr_interrupt_mask_reg32;
1336 void __iomem *sense_interrupt_mask_reg;
1337 void __iomem *sense_interrupt_mask_reg32;
1338 void __iomem *clr_interrupt_reg;
1339 void __iomem *clr_interrupt_reg32;
1341 void __iomem *sense_interrupt_reg;
1342 void __iomem *sense_interrupt_reg32;
1343 void __iomem *ioarrin_reg;
1344 void __iomem *sense_uproc_interrupt_reg;
1345 void __iomem *sense_uproc_interrupt_reg32;
1346 void __iomem *set_uproc_interrupt_reg;
1347 void __iomem *set_uproc_interrupt_reg32;
1348 void __iomem *clr_uproc_interrupt_reg;
1349 void __iomem *clr_uproc_interrupt_reg32;
1351 void __iomem *init_feedback_reg;
1353 void __iomem *dump_addr_reg;
1354 void __iomem *dump_data_reg;
1356 void __iomem *endian_swap_reg;
1359 struct ipr_chip_cfg_t {
1365 struct ipr_interrupt_offsets regs;
1372 #define IPR_USE_LSI 0x00
1373 #define IPR_USE_MSI 0x01
1374 #define IPR_USE_MSIX 0x02
1376 #define IPR_SIS32 0x00
1377 #define IPR_SIS64 0x01
1379 #define IPR_PCI_CFG 0x00
1380 #define IPR_MMIO 0x01
1381 const struct ipr_chip_cfg_t *cfg;
1384 enum ipr_shutdown_type {
1385 IPR_SHUTDOWN_NORMAL = 0x00,
1386 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1387 IPR_SHUTDOWN_ABBREV = 0x80,
1388 IPR_SHUTDOWN_NONE = 0x100
1391 struct ipr_trace_entry {
1397 #define IPR_TRACE_START 0x00
1398 #define IPR_TRACE_FINISH 0xff
1414 struct scatterlist scatterlist[1];
1417 enum ipr_sdt_state {
1426 /* Per-controller data */
1427 struct ipr_ioa_cfg {
1428 char eye_catcher[8];
1429 #define IPR_EYECATCHER "iprcfg"
1431 struct list_head queue;
1433 u8 in_reset_reload:1;
1434 u8 in_ioa_bringdown:1;
1435 u8 ioa_unit_checked:1;
1437 u8 allow_ml_add_del:1;
1438 u8 needs_hard_reset:1;
1440 u8 needs_warm_reset:1;
1450 * Bitmaps for SIS64 generated target values
1452 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1453 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1454 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1456 u16 type; /* CCIN of the card */
1459 #define IPR_MAX_LOG_LEVEL 4
1460 #define IPR_DEFAULT_LOG_LEVEL 2
1462 #define IPR_NUM_TRACE_INDEX_BITS 8
1463 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1464 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1465 char trace_start[8];
1466 #define IPR_TRACE_START_LABEL "trace"
1467 struct ipr_trace_entry *trace;
1468 atomic_t trace_index;
1470 char cfg_table_start[8];
1471 #define IPR_CFG_TBL_START "cfg"
1473 struct ipr_config_table *cfg_table;
1474 struct ipr_config_table64 *cfg_table64;
1476 dma_addr_t cfg_table_dma;
1478 u32 max_devs_supported;
1480 char resource_table_label[8];
1481 #define IPR_RES_TABLE_LABEL "res_tbl"
1482 struct ipr_resource_entry *res_entries;
1483 struct list_head free_res_q;
1484 struct list_head used_res_q;
1486 char ipr_hcam_label[8];
1487 #define IPR_HCAM_LABEL "hcams"
1488 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1489 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1490 struct list_head hostrcb_free_q;
1491 struct list_head hostrcb_pending_q;
1493 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1495 atomic_t hrrq_index;
1496 u16 identify_hrrq_index;
1498 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1500 unsigned int transop_timeout;
1501 const struct ipr_chip_cfg_t *chip_cfg;
1502 const struct ipr_chip_t *ipr_chip;
1504 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1505 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1506 void __iomem *ioa_mailbox;
1507 struct ipr_interrupts regs;
1509 u16 saved_pcix_cmd_reg;
1515 struct Scsi_Host *host;
1516 struct pci_dev *pdev;
1517 struct ipr_sglist *ucode_sglist;
1518 u8 saved_mode_page_len;
1520 struct work_struct work_q;
1522 wait_queue_head_t reset_wait_q;
1523 wait_queue_head_t msi_wait_q;
1525 struct ipr_dump *dump;
1526 enum ipr_sdt_state sdt_state;
1528 struct ipr_misc_cbs *vpd_cbs;
1529 dma_addr_t vpd_cbs_dma;
1531 struct pci_pool *ipr_cmd_pool;
1533 struct ipr_cmnd *reset_cmd;
1534 int (*reset) (struct ipr_cmnd *);
1536 struct ata_host ata_host;
1537 char ipr_cmd_label[8];
1538 #define IPR_CMD_LABEL "ipr_cmd"
1540 struct ipr_cmnd **ipr_cmnd_list;
1541 dma_addr_t *ipr_cmnd_list_dma;
1544 unsigned int nvectors;
1549 } vectors_info[IPR_MAX_MSIX_VECTORS];
1553 }; /* struct ipr_ioa_cfg */
1556 struct ipr_ioarcb ioarcb;
1558 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1559 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1560 struct ipr_ata64_ioadl ata_ioadl;
1563 struct ipr_ioasa ioasa;
1564 struct ipr_ioasa64 ioasa64;
1566 struct list_head queue;
1567 struct scsi_cmnd *scsi_cmd;
1568 struct ata_queued_cmd *qc;
1569 struct completion completion;
1570 struct timer_list timer;
1571 void (*fast_done) (struct ipr_cmnd *);
1572 void (*done) (struct ipr_cmnd *);
1573 int (*job_step) (struct ipr_cmnd *);
1574 int (*job_step_failed) (struct ipr_cmnd *);
1576 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1577 dma_addr_t sense_buffer_dma;
1578 unsigned short dma_use_sg;
1579 dma_addr_t dma_addr;
1580 struct ipr_cmnd *sibling;
1582 enum ipr_shutdown_type shutdown_type;
1583 struct ipr_hostrcb *hostrcb;
1584 unsigned long time_left;
1585 unsigned long scratch;
1586 struct ipr_resource_entry *res;
1587 struct scsi_device *sdev;
1590 struct ipr_hrr_queue *hrrq;
1591 struct ipr_ioa_cfg *ioa_cfg;
1594 struct ipr_ses_table_entry {
1595 char product_id[17];
1596 char compare_product_id_byte[17];
1597 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1600 struct ipr_dump_header {
1602 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1605 u32 first_entry_offset;
1607 #define IPR_DUMP_STATUS_SUCCESS 0
1608 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1609 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1611 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1613 #define IPR_DUMP_DRIVER_NAME 0x49505232
1614 }__attribute__((packed, aligned (4)));
1616 struct ipr_dump_entry_header {
1618 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1623 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1624 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1626 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1627 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1628 #define IPR_DUMP_TRACE_ID 0x54524143
1629 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1630 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1631 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1632 #define IPR_DUMP_PEND_OPS 0x414F5053
1634 }__attribute__((packed, aligned (4)));
1636 struct ipr_dump_location_entry {
1637 struct ipr_dump_entry_header hdr;
1639 }__attribute__((packed));
1641 struct ipr_dump_trace_entry {
1642 struct ipr_dump_entry_header hdr;
1643 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1644 }__attribute__((packed, aligned (4)));
1646 struct ipr_dump_version_entry {
1647 struct ipr_dump_entry_header hdr;
1648 u8 version[sizeof(IPR_DRIVER_VERSION)];
1651 struct ipr_dump_ioa_type_entry {
1652 struct ipr_dump_entry_header hdr;
1657 struct ipr_driver_dump {
1658 struct ipr_dump_header hdr;
1659 struct ipr_dump_version_entry version_entry;
1660 struct ipr_dump_location_entry location_entry;
1661 struct ipr_dump_ioa_type_entry ioa_type_entry;
1662 struct ipr_dump_trace_entry trace_entry;
1663 }__attribute__((packed));
1665 struct ipr_ioa_dump {
1666 struct ipr_dump_entry_header hdr;
1670 u32 next_page_index;
1673 }__attribute__((packed, aligned (4)));
1677 struct ipr_ioa_cfg *ioa_cfg;
1678 struct ipr_driver_dump driver_dump;
1679 struct ipr_ioa_dump ioa_dump;
1682 struct ipr_error_table_t {
1689 struct ipr_software_inq_lid_info {
1691 __be32 timestamp[3];
1692 }__attribute__((packed, aligned (4)));
1694 struct ipr_ucode_image_header {
1695 __be32 header_length;
1696 __be32 lid_table_offset;
1699 u8 minor_release[2];
1701 char eyecatcher[16];
1703 struct ipr_software_inq_lid_info lid[1];
1704 }__attribute__((packed, aligned (4)));
1709 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1711 #ifdef CONFIG_SCSI_IPR_TRACE
1712 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1713 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1715 #define ipr_create_trace_file(kobj, attr) 0
1716 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1719 #ifdef CONFIG_SCSI_IPR_DUMP
1720 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1721 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1723 #define ipr_create_dump_file(kobj, attr) 0
1724 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1728 * Error logging macros
1730 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1731 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1732 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1734 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1735 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1736 bus, target, lun, ##__VA_ARGS__)
1738 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1739 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1741 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1742 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1743 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1745 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1746 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1748 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1750 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1751 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1753 ipr_err(fmt": %d:%d:%d:%d\n", \
1754 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1755 (res).bus, (res).target, (res).lun); \
1759 #define ipr_hcam_err(hostrcb, fmt, ...) \
1761 if (ipr_is_device(hostrcb)) { \
1762 if ((hostrcb)->ioa_cfg->sis64) { \
1763 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1764 ipr_format_res_path(hostrcb->ioa_cfg, \
1765 hostrcb->hcam.u.error64.fd_res_path, \
1766 hostrcb->rp_buffer, \
1767 sizeof(hostrcb->rp_buffer)), \
1770 ipr_ra_err((hostrcb)->ioa_cfg, \
1771 (hostrcb)->hcam.u.error.fd_res_addr, \
1772 fmt, __VA_ARGS__); \
1775 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1779 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1780 __FILE__, __func__, __LINE__)
1782 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1783 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1785 #define ipr_err_separator \
1786 ipr_err("----------------------------------------------------------\n")
1794 * ipr_is_ioa_resource - Determine if a resource is the IOA
1795 * @res: resource entry struct
1798 * 1 if IOA / 0 if not IOA
1800 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1802 return res->type == IPR_RES_TYPE_IOAFP;
1806 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1807 * @res: resource entry struct
1810 * 1 if AF DASD / 0 if not AF DASD
1812 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1814 return res->type == IPR_RES_TYPE_AF_DASD ||
1815 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1819 * ipr_is_vset_device - Determine if a resource is a VSET
1820 * @res: resource entry struct
1823 * 1 if VSET / 0 if not VSET
1825 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1827 return res->type == IPR_RES_TYPE_VOLUME_SET;
1831 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1832 * @res: resource entry struct
1835 * 1 if GSCSI / 0 if not GSCSI
1837 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1839 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1843 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1844 * @res: resource entry struct
1847 * 1 if SCSI disk / 0 if not SCSI disk
1849 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1851 if (ipr_is_af_dasd_device(res) ||
1852 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1859 * ipr_is_gata - Determine if a resource is a generic ATA resource
1860 * @res: resource entry struct
1863 * 1 if GATA / 0 if not GATA
1865 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1867 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1871 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1872 * @res: resource entry struct
1875 * 1 if NACA queueing model / 0 if not NACA queueing model
1877 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1879 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1885 * ipr_is_device - Determine if the hostrcb structure is related to a device
1886 * @hostrcb: host resource control blocks struct
1889 * 1 if AF / 0 if not AF
1891 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1893 struct ipr_res_addr *res_addr;
1896 if (hostrcb->ioa_cfg->sis64) {
1897 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1898 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1899 res_path[0] == 0x81) && res_path[2] != 0xFF)
1902 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1904 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1905 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1912 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1913 * @sdt_word: SDT address
1916 * 1 if format 2 / 0 if not
1918 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1920 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1923 case IPR_SDT_FMT2_BAR0_SEL:
1924 case IPR_SDT_FMT2_BAR1_SEL:
1925 case IPR_SDT_FMT2_BAR2_SEL:
1926 case IPR_SDT_FMT2_BAR3_SEL:
1927 case IPR_SDT_FMT2_BAR4_SEL:
1928 case IPR_SDT_FMT2_BAR5_SEL:
1929 case IPR_SDT_FMT2_EXP_ROM_SEL:
1937 static inline void writeq(u64 val, void __iomem *addr)
1939 writel(((u32) (val >> 32)), addr);
1940 writel(((u32) (val)), (addr + 4));