2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
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30 * modification, are permitted provided that the following conditions
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53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 #include <linux/circ_buf.h>
56 #include <linux/device.h>
61 #include "probe_roms.h"
62 #include "remote_device.h"
64 #include "scu_completion_codes.h"
65 #include "scu_event_codes.h"
66 #include "registers.h"
67 #include "scu_remote_node_context.h"
68 #include "scu_task_context.h"
70 #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
72 #define smu_max_ports(dcc_value) \
74 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
75 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
78 #define smu_max_task_contexts(dcc_value) \
80 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
81 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
84 #define smu_max_rncs(dcc_value) \
86 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
87 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
90 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
95 * The number of milliseconds to wait while a given phy is consuming power
96 * before allowing another set of phys to consume power. Ultimately, this will
97 * be specified by OEM parameter.
99 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
102 * NORMALIZE_PUT_POINTER() -
104 * This macro will normalize the completion queue put pointer so its value can
105 * be used as an array inde
107 #define NORMALIZE_PUT_POINTER(x) \
108 ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
112 * NORMALIZE_EVENT_POINTER() -
114 * This macro will normalize the completion queue event entry so its value can
115 * be used as an index.
117 #define NORMALIZE_EVENT_POINTER(x) \
119 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
120 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
124 * NORMALIZE_GET_POINTER() -
126 * This macro will normalize the completion queue get pointer so its value can
127 * be used as an index into an array
129 #define NORMALIZE_GET_POINTER(x) \
130 ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
133 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
135 * This macro will normalize the completion queue cycle pointer so it matches
136 * the completion queue cycle bit
138 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
139 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
142 * COMPLETION_QUEUE_CYCLE_BIT() -
144 * This macro will return the cycle bit of the completion queue entry
146 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
148 /* Init the state machine and call the state entry function (if any) */
149 void sci_init_sm(struct sci_base_state_machine *sm,
150 const struct sci_base_state *state_table, u32 initial_state)
152 sci_state_transition_t handler;
154 sm->initial_state_id = initial_state;
155 sm->previous_state_id = initial_state;
156 sm->current_state_id = initial_state;
157 sm->state_table = state_table;
159 handler = sm->state_table[initial_state].enter_state;
164 /* Call the state exit fn, update the current state, call the state entry fn */
165 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
167 sci_state_transition_t handler;
169 handler = sm->state_table[sm->current_state_id].exit_state;
173 sm->previous_state_id = sm->current_state_id;
174 sm->current_state_id = next_state;
176 handler = sm->state_table[sm->current_state_id].enter_state;
181 static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
183 u32 get_value = ihost->completion_queue_get;
184 u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
186 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
187 COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
193 static bool sci_controller_isr(struct isci_host *ihost)
195 if (sci_controller_completion_queue_has_entries(ihost)) {
199 * we have a spurious interrupt it could be that we have already
200 * emptied the completion queue from a previous interrupt */
201 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
204 * There is a race in the hardware that could cause us not to be notified
205 * of an interrupt completion if we do not take this step. We will mask
206 * then unmask the interrupts so if there is another interrupt pending
207 * the clearing of the interrupt source we get the next interrupt message. */
208 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
209 writel(0, &ihost->smu_registers->interrupt_mask);
215 irqreturn_t isci_msix_isr(int vec, void *data)
217 struct isci_host *ihost = data;
219 if (sci_controller_isr(ihost))
220 tasklet_schedule(&ihost->completion_tasklet);
225 static bool sci_controller_error_isr(struct isci_host *ihost)
227 u32 interrupt_status;
230 readl(&ihost->smu_registers->interrupt_status);
231 interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
233 if (interrupt_status != 0) {
235 * There is an error interrupt pending so let it through and handle
241 * There is a race in the hardware that could cause us not to be notified
242 * of an interrupt completion if we do not take this step. We will mask
243 * then unmask the error interrupts so if there was another interrupt
244 * pending we will be notified.
245 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
246 writel(0xff, &ihost->smu_registers->interrupt_mask);
247 writel(0, &ihost->smu_registers->interrupt_mask);
252 static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
254 u32 index = SCU_GET_COMPLETION_INDEX(ent);
255 struct isci_request *ireq = ihost->reqs[index];
257 /* Make sure that we really want to process this IO request */
258 if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
259 ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
260 ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
261 /* Yep this is a valid io request pass it along to the
264 sci_io_request_tc_completion(ireq, ent);
267 static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
270 struct isci_request *ireq;
271 struct isci_remote_device *idev;
273 index = SCU_GET_COMPLETION_INDEX(ent);
275 switch (scu_get_command_request_type(ent)) {
276 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
277 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
278 ireq = ihost->reqs[index];
279 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
280 __func__, ent, ireq);
281 /* @todo For a post TC operation we need to fail the IO
285 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
286 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
287 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
288 idev = ihost->device_table[index];
289 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
290 __func__, ent, idev);
291 /* @todo For a port RNC operation we need to fail the
296 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
302 static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
307 struct scu_unsolicited_frame_header *frame_header;
308 struct isci_phy *iphy;
309 struct isci_remote_device *idev;
311 enum sci_status result = SCI_FAILURE;
313 frame_index = SCU_GET_FRAME_INDEX(ent);
315 frame_header = ihost->uf_control.buffers.array[frame_index].header;
316 ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
318 if (SCU_GET_FRAME_ERROR(ent)) {
320 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
321 * / this cause a problem? We expect the phy initialization will
322 * / fail if there is an error in the frame. */
323 sci_controller_release_frame(ihost, frame_index);
327 if (frame_header->is_address_frame) {
328 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
329 iphy = &ihost->phys[index];
330 result = sci_phy_frame_handler(iphy, frame_index);
333 index = SCU_GET_COMPLETION_INDEX(ent);
335 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
337 * This is a signature fis or a frame from a direct attached SATA
338 * device that has not yet been created. In either case forwared
339 * the frame to the PE and let it take care of the frame data. */
340 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
341 iphy = &ihost->phys[index];
342 result = sci_phy_frame_handler(iphy, frame_index);
344 if (index < ihost->remote_node_entries)
345 idev = ihost->device_table[index];
350 result = sci_remote_device_frame_handler(idev, frame_index);
352 sci_controller_release_frame(ihost, frame_index);
356 if (result != SCI_SUCCESS) {
358 * / @todo Is there any reason to report some additional error message
359 * / when we get this failure notifiction? */
363 static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
365 struct isci_remote_device *idev;
366 struct isci_request *ireq;
367 struct isci_phy *iphy;
370 index = SCU_GET_COMPLETION_INDEX(ent);
372 switch (scu_get_event_type(ent)) {
373 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
374 /* / @todo The driver did something wrong and we need to fix the condtion. */
375 dev_err(&ihost->pdev->dev,
376 "%s: SCIC Controller 0x%p received SMU command error "
383 case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
384 case SCU_EVENT_TYPE_SMU_ERROR:
385 case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
387 * / @todo This is a hardware failure and its likely that we want to
388 * / reset the controller. */
389 dev_err(&ihost->pdev->dev,
390 "%s: SCIC Controller 0x%p received fatal controller "
397 case SCU_EVENT_TYPE_TRANSPORT_ERROR:
398 ireq = ihost->reqs[index];
399 sci_io_request_event_handler(ireq, ent);
402 case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
403 switch (scu_get_event_specifier(ent)) {
404 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
405 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
406 ireq = ihost->reqs[index];
408 sci_io_request_event_handler(ireq, ent);
410 dev_warn(&ihost->pdev->dev,
411 "%s: SCIC Controller 0x%p received "
412 "event 0x%x for io request object "
413 "that doesnt exist.\n",
420 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
421 idev = ihost->device_table[index];
423 sci_remote_device_event_handler(idev, ent);
425 dev_warn(&ihost->pdev->dev,
426 "%s: SCIC Controller 0x%p received "
427 "event 0x%x for remote device object "
428 "that doesnt exist.\n",
437 case SCU_EVENT_TYPE_BROADCAST_CHANGE:
439 * direct the broadcast change event to the phy first and then let
440 * the phy redirect the broadcast change to the port object */
441 case SCU_EVENT_TYPE_ERR_CNT_EVENT:
443 * direct error counter event to the phy object since that is where
444 * we get the event notification. This is a type 4 event. */
445 case SCU_EVENT_TYPE_OSSP_EVENT:
446 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
447 iphy = &ihost->phys[index];
448 sci_phy_event_handler(iphy, ent);
451 case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
452 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
453 case SCU_EVENT_TYPE_RNC_OPS_MISC:
454 if (index < ihost->remote_node_entries) {
455 idev = ihost->device_table[index];
458 sci_remote_device_event_handler(idev, ent);
460 dev_err(&ihost->pdev->dev,
461 "%s: SCIC Controller 0x%p received event 0x%x "
462 "for remote device object 0x%0x that doesnt "
472 dev_warn(&ihost->pdev->dev,
473 "%s: SCIC Controller received unknown event code %x\n",
480 static void sci_controller_process_completions(struct isci_host *ihost)
482 u32 completion_count = 0;
489 dev_dbg(&ihost->pdev->dev,
490 "%s: completion queue begining get:0x%08x\n",
492 ihost->completion_queue_get);
494 /* Get the component parts of the completion queue */
495 get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
496 get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
498 event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
499 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
502 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
503 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
507 ent = ihost->completion_queue[get_index];
509 /* increment the get pointer and check for rollover to toggle the cycle bit */
510 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
511 (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
512 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
514 dev_dbg(&ihost->pdev->dev,
515 "%s: completion queue entry:0x%08x\n",
519 switch (SCU_GET_COMPLETION_TYPE(ent)) {
520 case SCU_COMPLETION_TYPE_TASK:
521 sci_controller_task_completion(ihost, ent);
524 case SCU_COMPLETION_TYPE_SDMA:
525 sci_controller_sdma_completion(ihost, ent);
528 case SCU_COMPLETION_TYPE_UFI:
529 sci_controller_unsolicited_frame(ihost, ent);
532 case SCU_COMPLETION_TYPE_EVENT:
533 sci_controller_event_completion(ihost, ent);
536 case SCU_COMPLETION_TYPE_NOTIFY: {
537 event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
538 (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
539 event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
541 sci_controller_event_completion(ihost, ent);
545 dev_warn(&ihost->pdev->dev,
546 "%s: SCIC Controller received unknown "
547 "completion type %x\n",
554 /* Update the get register if we completed one or more entries */
555 if (completion_count > 0) {
556 ihost->completion_queue_get =
557 SMU_CQGR_GEN_BIT(ENABLE) |
558 SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
560 SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
562 SMU_CQGR_GEN_VAL(POINTER, get_index);
564 writel(ihost->completion_queue_get,
565 &ihost->smu_registers->completion_queue_get);
569 dev_dbg(&ihost->pdev->dev,
570 "%s: completion queue ending get:0x%08x\n",
572 ihost->completion_queue_get);
576 static void sci_controller_error_handler(struct isci_host *ihost)
578 u32 interrupt_status;
581 readl(&ihost->smu_registers->interrupt_status);
583 if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
584 sci_controller_completion_queue_has_entries(ihost)) {
586 sci_controller_process_completions(ihost);
587 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
589 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
592 sci_change_state(&ihost->sm, SCIC_FAILED);
597 /* If we dont process any completions I am not sure that we want to do this.
598 * We are in the middle of a hardware fault and should probably be reset.
600 writel(0, &ihost->smu_registers->interrupt_mask);
603 irqreturn_t isci_intx_isr(int vec, void *data)
605 irqreturn_t ret = IRQ_NONE;
606 struct isci_host *ihost = data;
608 if (sci_controller_isr(ihost)) {
609 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
610 tasklet_schedule(&ihost->completion_tasklet);
612 } else if (sci_controller_error_isr(ihost)) {
613 spin_lock(&ihost->scic_lock);
614 sci_controller_error_handler(ihost);
615 spin_unlock(&ihost->scic_lock);
622 irqreturn_t isci_error_isr(int vec, void *data)
624 struct isci_host *ihost = data;
626 if (sci_controller_error_isr(ihost))
627 sci_controller_error_handler(ihost);
633 * isci_host_start_complete() - This function is called by the core library,
634 * through the ISCI Module, to indicate controller start status.
635 * @isci_host: This parameter specifies the ISCI host object
636 * @completion_status: This parameter specifies the completion status from the
640 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
642 if (completion_status != SCI_SUCCESS)
643 dev_info(&ihost->pdev->dev,
644 "controller start timed out, continuing...\n");
645 clear_bit(IHOST_START_PENDING, &ihost->flags);
646 wake_up(&ihost->eventq);
649 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
651 struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost);
652 struct isci_host *ihost = ha->lldd_ha;
654 if (test_bit(IHOST_START_PENDING, &ihost->flags))
663 * sci_controller_get_suggested_start_timeout() - This method returns the
664 * suggested sci_controller_start() timeout amount. The user is free to
665 * use any timeout value, but this method provides the suggested minimum
666 * start timeout value. The returned value is based upon empirical
667 * information determined as a result of interoperability testing.
668 * @controller: the handle to the controller object for which to return the
669 * suggested start timeout.
671 * This method returns the number of milliseconds for the suggested start
674 static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
676 /* Validate the user supplied parameters. */
681 * The suggested minimum timeout value for a controller start operation:
683 * Signature FIS Timeout
684 * + Phy Start Timeout
685 * + Number of Phy Spin Up Intervals
686 * ---------------------------------
687 * Number of milliseconds for the controller start operation.
689 * NOTE: The number of phy spin up intervals will be equivalent
690 * to the number of phys divided by the number phys allowed
691 * per interval - 1 (once OEM parameters are supported).
692 * Currently we assume only 1 phy per interval. */
694 return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
695 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
696 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
699 static void sci_controller_enable_interrupts(struct isci_host *ihost)
701 BUG_ON(ihost->smu_registers == NULL);
702 writel(0, &ihost->smu_registers->interrupt_mask);
705 void sci_controller_disable_interrupts(struct isci_host *ihost)
707 BUG_ON(ihost->smu_registers == NULL);
708 writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
711 static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
713 u32 port_task_scheduler_value;
715 port_task_scheduler_value =
716 readl(&ihost->scu_registers->peg0.ptsg.control);
717 port_task_scheduler_value |=
718 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
719 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
720 writel(port_task_scheduler_value,
721 &ihost->scu_registers->peg0.ptsg.control);
724 static void sci_controller_assign_task_entries(struct isci_host *ihost)
729 * Assign all the TCs to function 0
730 * TODO: Do we actually need to read this register to write it back?
734 readl(&ihost->smu_registers->task_context_assignment[0]);
736 task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
737 (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) |
738 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
740 writel(task_assignment,
741 &ihost->smu_registers->task_context_assignment[0]);
745 static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
748 u32 completion_queue_control_value;
749 u32 completion_queue_get_value;
750 u32 completion_queue_put_value;
752 ihost->completion_queue_get = 0;
754 completion_queue_control_value =
755 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
756 SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
758 writel(completion_queue_control_value,
759 &ihost->smu_registers->completion_queue_control);
762 /* Set the completion queue get pointer and enable the queue */
763 completion_queue_get_value = (
764 (SMU_CQGR_GEN_VAL(POINTER, 0))
765 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
766 | (SMU_CQGR_GEN_BIT(ENABLE))
767 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
770 writel(completion_queue_get_value,
771 &ihost->smu_registers->completion_queue_get);
773 /* Set the completion queue put pointer */
774 completion_queue_put_value = (
775 (SMU_CQPR_GEN_VAL(POINTER, 0))
776 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
779 writel(completion_queue_put_value,
780 &ihost->smu_registers->completion_queue_put);
782 /* Initialize the cycle bit of the completion queue entries */
783 for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
785 * If get.cycle_bit != completion_queue.cycle_bit
786 * its not a valid completion queue entry
787 * so at system start all entries are invalid */
788 ihost->completion_queue[index] = 0x80000000;
792 static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
794 u32 frame_queue_control_value;
795 u32 frame_queue_get_value;
796 u32 frame_queue_put_value;
798 /* Write the queue size */
799 frame_queue_control_value =
800 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
802 writel(frame_queue_control_value,
803 &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
805 /* Setup the get pointer for the unsolicited frame queue */
806 frame_queue_get_value = (
807 SCU_UFQGP_GEN_VAL(POINTER, 0)
808 | SCU_UFQGP_GEN_BIT(ENABLE_BIT)
811 writel(frame_queue_get_value,
812 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
813 /* Setup the put pointer for the unsolicited frame queue */
814 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
815 writel(frame_queue_put_value,
816 &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
819 static void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
821 if (ihost->sm.current_state_id == SCIC_STARTING) {
823 * We move into the ready state, because some of the phys/ports
824 * may be up and operational.
826 sci_change_state(&ihost->sm, SCIC_READY);
828 isci_host_start_complete(ihost, status);
832 static bool is_phy_starting(struct isci_phy *iphy)
834 enum sci_phy_states state;
836 state = iphy->sm.current_state_id;
838 case SCI_PHY_STARTING:
839 case SCI_PHY_SUB_INITIAL:
840 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
841 case SCI_PHY_SUB_AWAIT_IAF_UF:
842 case SCI_PHY_SUB_AWAIT_SAS_POWER:
843 case SCI_PHY_SUB_AWAIT_SATA_POWER:
844 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
845 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
846 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
847 case SCI_PHY_SUB_FINAL:
855 * sci_controller_start_next_phy - start phy
858 * If all the phys have been started, then attempt to transition the
859 * controller to the READY state and inform the user
860 * (sci_cb_controller_start_complete()).
862 static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
864 struct sci_oem_params *oem = &ihost->oem_parameters;
865 struct isci_phy *iphy;
866 enum sci_status status;
868 status = SCI_SUCCESS;
870 if (ihost->phy_startup_timer_pending)
873 if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
874 bool is_controller_start_complete = true;
878 for (index = 0; index < SCI_MAX_PHYS; index++) {
879 iphy = &ihost->phys[index];
880 state = iphy->sm.current_state_id;
882 if (!phy_get_non_dummy_port(iphy))
885 /* The controller start operation is complete iff:
886 * - all links have been given an opportunity to start
887 * - have no indication of a connected device
888 * - have an indication of a connected device and it has
889 * finished the link training process.
891 if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
892 (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
893 (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
894 (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask)) {
895 is_controller_start_complete = false;
901 * The controller has successfully finished the start process.
902 * Inform the SCI Core user and transition to the READY state. */
903 if (is_controller_start_complete == true) {
904 sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
905 sci_del_timer(&ihost->phy_timer);
906 ihost->phy_startup_timer_pending = false;
909 iphy = &ihost->phys[ihost->next_phy_to_start];
911 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
912 if (phy_get_non_dummy_port(iphy) == NULL) {
913 ihost->next_phy_to_start++;
915 /* Caution recursion ahead be forwarned
917 * The PHY was never added to a PORT in MPC mode
918 * so start the next phy in sequence This phy
919 * will never go link up and will not draw power
920 * the OEM parameters either configured the phy
921 * incorrectly for the PORT or it was never
924 return sci_controller_start_next_phy(ihost);
928 status = sci_phy_start(iphy);
930 if (status == SCI_SUCCESS) {
931 sci_mod_timer(&ihost->phy_timer,
932 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
933 ihost->phy_startup_timer_pending = true;
935 dev_warn(&ihost->pdev->dev,
936 "%s: Controller stop operation failed "
937 "to stop phy %d because of status "
940 ihost->phys[ihost->next_phy_to_start].phy_index,
944 ihost->next_phy_to_start++;
950 static void phy_startup_timeout(unsigned long data)
952 struct sci_timer *tmr = (struct sci_timer *)data;
953 struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
955 enum sci_status status;
957 spin_lock_irqsave(&ihost->scic_lock, flags);
962 ihost->phy_startup_timer_pending = false;
965 status = sci_controller_start_next_phy(ihost);
966 } while (status != SCI_SUCCESS);
969 spin_unlock_irqrestore(&ihost->scic_lock, flags);
972 static u16 isci_tci_active(struct isci_host *ihost)
974 return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
977 static enum sci_status sci_controller_start(struct isci_host *ihost,
980 enum sci_status result;
983 if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
984 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
985 __func__, ihost->sm.current_state_id);
986 return SCI_FAILURE_INVALID_STATE;
989 /* Build the TCi free pool */
990 BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
993 for (index = 0; index < ihost->task_context_entries; index++)
994 isci_tci_free(ihost, index);
996 /* Build the RNi free pool */
997 sci_remote_node_table_initialize(&ihost->available_remote_nodes,
998 ihost->remote_node_entries);
1001 * Before anything else lets make sure we will not be
1002 * interrupted by the hardware.
1004 sci_controller_disable_interrupts(ihost);
1006 /* Enable the port task scheduler */
1007 sci_controller_enable_port_task_scheduler(ihost);
1009 /* Assign all the task entries to ihost physical function */
1010 sci_controller_assign_task_entries(ihost);
1012 /* Now initialize the completion queue */
1013 sci_controller_initialize_completion_queue(ihost);
1015 /* Initialize the unsolicited frame queue for use */
1016 sci_controller_initialize_unsolicited_frame_queue(ihost);
1018 /* Start all of the ports on this controller */
1019 for (index = 0; index < ihost->logical_port_entries; index++) {
1020 struct isci_port *iport = &ihost->ports[index];
1022 result = sci_port_start(iport);
1027 sci_controller_start_next_phy(ihost);
1029 sci_mod_timer(&ihost->timer, timeout);
1031 sci_change_state(&ihost->sm, SCIC_STARTING);
1036 void isci_host_scan_start(struct Scsi_Host *shost)
1038 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1039 unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
1041 set_bit(IHOST_START_PENDING, &ihost->flags);
1043 spin_lock_irq(&ihost->scic_lock);
1044 sci_controller_start(ihost, tmo);
1045 sci_controller_enable_interrupts(ihost);
1046 spin_unlock_irq(&ihost->scic_lock);
1049 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1051 sci_controller_disable_interrupts(ihost);
1052 clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1053 wake_up(&ihost->eventq);
1056 static void sci_controller_completion_handler(struct isci_host *ihost)
1058 /* Empty out the completion queue */
1059 if (sci_controller_completion_queue_has_entries(ihost))
1060 sci_controller_process_completions(ihost);
1062 /* Clear the interrupt and enable all interrupts again */
1063 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
1064 /* Could we write the value of SMU_ISR_COMPLETION? */
1065 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
1066 writel(0, &ihost->smu_registers->interrupt_mask);
1070 * isci_host_completion_routine() - This function is the delayed service
1071 * routine that calls the sci core library's completion handler. It's
1072 * scheduled as a tasklet from the interrupt service routine when interrupts
1073 * in use, or set as the timeout function in polled mode.
1074 * @data: This parameter specifies the ISCI host object
1077 static void isci_host_completion_routine(unsigned long data)
1079 struct isci_host *ihost = (struct isci_host *)data;
1080 struct list_head completed_request_list;
1081 struct list_head errored_request_list;
1082 struct list_head *current_position;
1083 struct list_head *next_position;
1084 struct isci_request *request;
1085 struct isci_request *next_request;
1086 struct sas_task *task;
1089 INIT_LIST_HEAD(&completed_request_list);
1090 INIT_LIST_HEAD(&errored_request_list);
1092 spin_lock_irq(&ihost->scic_lock);
1094 sci_controller_completion_handler(ihost);
1096 /* Take the lists of completed I/Os from the host. */
1098 list_splice_init(&ihost->requests_to_complete,
1099 &completed_request_list);
1101 /* Take the list of errored I/Os from the host. */
1102 list_splice_init(&ihost->requests_to_errorback,
1103 &errored_request_list);
1105 spin_unlock_irq(&ihost->scic_lock);
1107 /* Process any completions in the lists. */
1108 list_for_each_safe(current_position, next_position,
1109 &completed_request_list) {
1111 request = list_entry(current_position, struct isci_request,
1113 task = isci_request_access_task(request);
1115 /* Normal notification (task_done) */
1116 dev_dbg(&ihost->pdev->dev,
1117 "%s: Normal - request/task = %p/%p\n",
1122 /* Return the task to libsas */
1125 task->lldd_task = NULL;
1126 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1128 /* If the task is already in the abort path,
1129 * the task_done callback cannot be called.
1131 task->task_done(task);
1135 spin_lock_irq(&ihost->scic_lock);
1136 isci_free_tag(ihost, request->io_tag);
1137 spin_unlock_irq(&ihost->scic_lock);
1139 list_for_each_entry_safe(request, next_request, &errored_request_list,
1142 task = isci_request_access_task(request);
1144 /* Use sas_task_abort */
1145 dev_warn(&ihost->pdev->dev,
1146 "%s: Error - request/task = %p/%p\n",
1153 /* Put the task into the abort path if it's not there
1156 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1157 sas_task_abort(task);
1160 /* This is a case where the request has completed with a
1161 * status such that it needed further target servicing,
1162 * but the sas_task reference has already been removed
1163 * from the request. Since it was errored, it was not
1164 * being aborted, so there is nothing to do except free
1168 spin_lock_irq(&ihost->scic_lock);
1169 /* Remove the request from the remote device's list
1170 * of pending requests.
1172 list_del_init(&request->dev_node);
1173 isci_free_tag(ihost, request->io_tag);
1174 spin_unlock_irq(&ihost->scic_lock);
1178 /* the coalesence timeout doubles at each encoding step, so
1179 * update it based on the ilog2 value of the outstanding requests
1181 active = isci_tci_active(ihost);
1182 writel(SMU_ICC_GEN_VAL(NUMBER, active) |
1183 SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
1184 &ihost->smu_registers->interrupt_coalesce_control);
1188 * sci_controller_stop() - This method will stop an individual controller
1189 * object.This method will invoke the associated user callback upon
1190 * completion. The completion callback is called when the following
1191 * conditions are met: -# the method return status is SCI_SUCCESS. -# the
1192 * controller has been quiesced. This method will ensure that all IO
1193 * requests are quiesced, phys are stopped, and all additional operation by
1194 * the hardware is halted.
1195 * @controller: the handle to the controller object to stop.
1196 * @timeout: This parameter specifies the number of milliseconds in which the
1197 * stop operation should complete.
1199 * The controller must be in the STARTED or STOPPED state. Indicate if the
1200 * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1201 * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1202 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1203 * controller is not either in the STARTED or STOPPED states.
1205 static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
1207 if (ihost->sm.current_state_id != SCIC_READY) {
1208 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
1209 __func__, ihost->sm.current_state_id);
1210 return SCI_FAILURE_INVALID_STATE;
1213 sci_mod_timer(&ihost->timer, timeout);
1214 sci_change_state(&ihost->sm, SCIC_STOPPING);
1219 * sci_controller_reset() - This method will reset the supplied core
1220 * controller regardless of the state of said controller. This operation is
1221 * considered destructive. In other words, all current operations are wiped
1222 * out. No IO completions for outstanding devices occur. Outstanding IO
1223 * requests are not aborted or completed at the actual remote device.
1224 * @controller: the handle to the controller object to reset.
1226 * Indicate if the controller reset method succeeded or failed in some way.
1227 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1228 * the controller reset operation is unable to complete.
1230 static enum sci_status sci_controller_reset(struct isci_host *ihost)
1232 switch (ihost->sm.current_state_id) {
1238 * The reset operation is not a graceful cleanup, just
1239 * perform the state transition.
1241 sci_change_state(&ihost->sm, SCIC_RESETTING);
1244 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
1245 __func__, ihost->sm.current_state_id);
1246 return SCI_FAILURE_INVALID_STATE;
1250 void isci_host_deinit(struct isci_host *ihost)
1254 /* disable output data selects */
1255 for (i = 0; i < isci_gpio_count(ihost); i++)
1256 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
1258 for (i = 0; i < SCI_MAX_PORTS; i++) {
1259 struct isci_port *iport = &ihost->ports[i];
1260 struct isci_remote_device *idev, *d;
1262 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
1263 if (test_bit(IDEV_ALLOCATED, &idev->flags))
1264 isci_remote_device_stop(ihost, idev);
1268 set_bit(IHOST_STOP_PENDING, &ihost->flags);
1270 spin_lock_irq(&ihost->scic_lock);
1271 sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
1272 spin_unlock_irq(&ihost->scic_lock);
1274 wait_for_stop(ihost);
1276 /* disable sgpio: where the above wait should give time for the
1277 * enclosure to sample the gpios going inactive
1279 writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
1281 sci_controller_reset(ihost);
1283 /* Cancel any/all outstanding port timers */
1284 for (i = 0; i < ihost->logical_port_entries; i++) {
1285 struct isci_port *iport = &ihost->ports[i];
1286 del_timer_sync(&iport->timer.timer);
1289 /* Cancel any/all outstanding phy timers */
1290 for (i = 0; i < SCI_MAX_PHYS; i++) {
1291 struct isci_phy *iphy = &ihost->phys[i];
1292 del_timer_sync(&iphy->sata_timer.timer);
1295 del_timer_sync(&ihost->port_agent.timer.timer);
1297 del_timer_sync(&ihost->power_control.timer.timer);
1299 del_timer_sync(&ihost->timer.timer);
1301 del_timer_sync(&ihost->phy_timer.timer);
1304 static void __iomem *scu_base(struct isci_host *isci_host)
1306 struct pci_dev *pdev = isci_host->pdev;
1307 int id = isci_host->id;
1309 return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1312 static void __iomem *smu_base(struct isci_host *isci_host)
1314 struct pci_dev *pdev = isci_host->pdev;
1315 int id = isci_host->id;
1317 return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1320 static void isci_user_parameters_get(struct sci_user_parameters *u)
1324 for (i = 0; i < SCI_MAX_PHYS; i++) {
1325 struct sci_phy_user_params *u_phy = &u->phys[i];
1327 u_phy->max_speed_generation = phy_gen;
1329 /* we are not exporting these for now */
1330 u_phy->align_insertion_frequency = 0x7f;
1331 u_phy->in_connection_align_insertion_frequency = 0xff;
1332 u_phy->notify_enable_spin_up_insertion_frequency = 0x33;
1335 u->stp_inactivity_timeout = stp_inactive_to;
1336 u->ssp_inactivity_timeout = ssp_inactive_to;
1337 u->stp_max_occupancy_timeout = stp_max_occ_to;
1338 u->ssp_max_occupancy_timeout = ssp_max_occ_to;
1339 u->no_outbound_task_timeout = no_outbound_task_to;
1340 u->max_concurr_spinup = max_concurr_spinup;
1343 static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
1345 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1347 sci_change_state(&ihost->sm, SCIC_RESET);
1350 static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
1352 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1354 sci_del_timer(&ihost->timer);
1357 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1358 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1359 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
1360 #define INTERRUPT_COALESCE_NUMBER_MAX 256
1361 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
1362 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
1365 * sci_controller_set_interrupt_coalescence() - This method allows the user to
1366 * configure the interrupt coalescence.
1367 * @controller: This parameter represents the handle to the controller object
1368 * for which its interrupt coalesce register is overridden.
1369 * @coalesce_number: Used to control the number of entries in the Completion
1370 * Queue before an interrupt is generated. If the number of entries exceed
1371 * this number, an interrupt will be generated. The valid range of the input
1372 * is [0, 256]. A setting of 0 results in coalescing being disabled.
1373 * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1374 * input is [0, 2700000] . A setting of 0 is allowed and results in no
1375 * interrupt coalescing timeout.
1377 * Indicate if the user successfully set the interrupt coalesce parameters.
1378 * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1379 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1381 static enum sci_status
1382 sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
1383 u32 coalesce_number,
1384 u32 coalesce_timeout)
1386 u8 timeout_encode = 0;
1390 /* Check if the input parameters fall in the range. */
1391 if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1392 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1395 * Defined encoding for interrupt coalescing timeout:
1396 * Value Min Max Units
1397 * ----- --- --- -----
1427 * Others Undefined */
1430 * Use the table above to decide the encode of interrupt coalescing timeout
1431 * value for register writing. */
1432 if (coalesce_timeout == 0)
1435 /* make the timeout value in unit of (10 ns). */
1436 coalesce_timeout = coalesce_timeout * 100;
1437 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1438 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1440 /* get the encode of timeout for register writing. */
1441 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1442 timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1444 if (min <= coalesce_timeout && max > coalesce_timeout)
1446 else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1447 && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1448 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1460 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1461 /* the value is out of range. */
1462 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1465 writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1466 SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1467 &ihost->smu_registers->interrupt_coalesce_control);
1470 ihost->interrupt_coalesce_number = (u16)coalesce_number;
1471 ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
1477 static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
1479 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1482 /* enable clock gating for power control of the scu unit */
1483 val = readl(&ihost->smu_registers->clock_gating_control);
1484 val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) |
1485 SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) |
1486 SMU_CGUCR_GEN_BIT(XCLK_ENABLE));
1487 val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE);
1488 writel(val, &ihost->smu_registers->clock_gating_control);
1490 /* set the default interrupt coalescence number and timeout value. */
1491 sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1494 static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
1496 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1498 /* disable interrupt coalescence. */
1499 sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1502 static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
1505 enum sci_status status;
1506 enum sci_status phy_status;
1508 status = SCI_SUCCESS;
1510 for (index = 0; index < SCI_MAX_PHYS; index++) {
1511 phy_status = sci_phy_stop(&ihost->phys[index]);
1513 if (phy_status != SCI_SUCCESS &&
1514 phy_status != SCI_FAILURE_INVALID_STATE) {
1515 status = SCI_FAILURE;
1517 dev_warn(&ihost->pdev->dev,
1518 "%s: Controller stop operation failed to stop "
1519 "phy %d because of status %d.\n",
1521 ihost->phys[index].phy_index, phy_status);
1528 static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
1531 enum sci_status port_status;
1532 enum sci_status status = SCI_SUCCESS;
1534 for (index = 0; index < ihost->logical_port_entries; index++) {
1535 struct isci_port *iport = &ihost->ports[index];
1537 port_status = sci_port_stop(iport);
1539 if ((port_status != SCI_SUCCESS) &&
1540 (port_status != SCI_FAILURE_INVALID_STATE)) {
1541 status = SCI_FAILURE;
1543 dev_warn(&ihost->pdev->dev,
1544 "%s: Controller stop operation failed to "
1545 "stop port %d because of status %d.\n",
1547 iport->logical_port_index,
1555 static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
1558 enum sci_status status;
1559 enum sci_status device_status;
1561 status = SCI_SUCCESS;
1563 for (index = 0; index < ihost->remote_node_entries; index++) {
1564 if (ihost->device_table[index] != NULL) {
1565 /* / @todo What timeout value do we want to provide to this request? */
1566 device_status = sci_remote_device_stop(ihost->device_table[index], 0);
1568 if ((device_status != SCI_SUCCESS) &&
1569 (device_status != SCI_FAILURE_INVALID_STATE)) {
1570 dev_warn(&ihost->pdev->dev,
1571 "%s: Controller stop operation failed "
1572 "to stop device 0x%p because of "
1575 ihost->device_table[index], device_status);
1583 static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1585 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1587 /* Stop all of the components for this controller */
1588 sci_controller_stop_phys(ihost);
1589 sci_controller_stop_ports(ihost);
1590 sci_controller_stop_devices(ihost);
1593 static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1595 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1597 sci_del_timer(&ihost->timer);
1600 static void sci_controller_reset_hardware(struct isci_host *ihost)
1602 /* Disable interrupts so we dont take any spurious interrupts */
1603 sci_controller_disable_interrupts(ihost);
1606 writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
1608 /* Delay for 1ms to before clearing the CQP and UFQPR. */
1611 /* The write to the CQGR clears the CQP */
1612 writel(0x00000000, &ihost->smu_registers->completion_queue_get);
1614 /* The write to the UFQGP clears the UFQPR */
1615 writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
1618 static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1620 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1622 sci_controller_reset_hardware(ihost);
1623 sci_change_state(&ihost->sm, SCIC_RESET);
1626 static const struct sci_base_state sci_controller_state_table[] = {
1628 .enter_state = sci_controller_initial_state_enter,
1631 [SCIC_INITIALIZING] = {},
1632 [SCIC_INITIALIZED] = {},
1634 .exit_state = sci_controller_starting_state_exit,
1637 .enter_state = sci_controller_ready_state_enter,
1638 .exit_state = sci_controller_ready_state_exit,
1640 [SCIC_RESETTING] = {
1641 .enter_state = sci_controller_resetting_state_enter,
1644 .enter_state = sci_controller_stopping_state_enter,
1645 .exit_state = sci_controller_stopping_state_exit,
1647 [SCIC_STOPPED] = {},
1651 static void sci_controller_set_default_config_parameters(struct isci_host *ihost)
1653 /* these defaults are overridden by the platform / firmware */
1656 /* Default to APC mode. */
1657 ihost->oem_parameters.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
1659 /* Default to APC mode. */
1660 ihost->oem_parameters.controller.max_concurr_spin_up = 1;
1662 /* Default to no SSC operation. */
1663 ihost->oem_parameters.controller.do_enable_ssc = false;
1665 /* Default to short cables on all phys. */
1666 ihost->oem_parameters.controller.cable_selection_mask = 0;
1668 /* Initialize all of the port parameter information to narrow ports. */
1669 for (index = 0; index < SCI_MAX_PORTS; index++) {
1670 ihost->oem_parameters.ports[index].phy_mask = 0;
1673 /* Initialize all of the phy parameter information. */
1674 for (index = 0; index < SCI_MAX_PHYS; index++) {
1675 /* Default to 3G (i.e. Gen 2). */
1676 ihost->user_parameters.phys[index].max_speed_generation =
1677 SCIC_SDS_PARM_GEN2_SPEED;
1679 /* the frequencies cannot be 0 */
1680 ihost->user_parameters.phys[index].align_insertion_frequency = 0x7f;
1681 ihost->user_parameters.phys[index].in_connection_align_insertion_frequency = 0xff;
1682 ihost->user_parameters.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
1685 * Previous Vitesse based expanders had a arbitration issue that
1686 * is worked around by having the upper 32-bits of SAS address
1687 * with a value greater then the Vitesse company identifier.
1688 * Hence, usage of 0x5FCFFFFF. */
1689 ihost->oem_parameters.phys[index].sas_address.low = 0x1 + ihost->id;
1690 ihost->oem_parameters.phys[index].sas_address.high = 0x5FCFFFFF;
1693 ihost->user_parameters.stp_inactivity_timeout = 5;
1694 ihost->user_parameters.ssp_inactivity_timeout = 5;
1695 ihost->user_parameters.stp_max_occupancy_timeout = 5;
1696 ihost->user_parameters.ssp_max_occupancy_timeout = 20;
1697 ihost->user_parameters.no_outbound_task_timeout = 2;
1700 static void controller_timeout(unsigned long data)
1702 struct sci_timer *tmr = (struct sci_timer *)data;
1703 struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
1704 struct sci_base_state_machine *sm = &ihost->sm;
1705 unsigned long flags;
1707 spin_lock_irqsave(&ihost->scic_lock, flags);
1712 if (sm->current_state_id == SCIC_STARTING)
1713 sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
1714 else if (sm->current_state_id == SCIC_STOPPING) {
1715 sci_change_state(sm, SCIC_FAILED);
1716 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1717 } else /* / @todo Now what do we want to do in this case? */
1718 dev_err(&ihost->pdev->dev,
1719 "%s: Controller timer fired when controller was not "
1720 "in a state being timed.\n",
1724 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1727 static enum sci_status sci_controller_construct(struct isci_host *ihost,
1728 void __iomem *scu_base,
1729 void __iomem *smu_base)
1733 sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
1735 ihost->scu_registers = scu_base;
1736 ihost->smu_registers = smu_base;
1738 sci_port_configuration_agent_construct(&ihost->port_agent);
1740 /* Construct the ports for this controller */
1741 for (i = 0; i < SCI_MAX_PORTS; i++)
1742 sci_port_construct(&ihost->ports[i], i, ihost);
1743 sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
1745 /* Construct the phys for this controller */
1746 for (i = 0; i < SCI_MAX_PHYS; i++) {
1747 /* Add all the PHYs to the dummy port */
1748 sci_phy_construct(&ihost->phys[i],
1749 &ihost->ports[SCI_MAX_PORTS], i);
1752 ihost->invalid_phy_mask = 0;
1754 sci_init_timer(&ihost->timer, controller_timeout);
1756 /* Initialize the User and OEM parameters to default values. */
1757 sci_controller_set_default_config_parameters(ihost);
1759 return sci_controller_reset(ihost);
1762 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
1766 for (i = 0; i < SCI_MAX_PORTS; i++)
1767 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1770 for (i = 0; i < SCI_MAX_PHYS; i++)
1771 if (oem->phys[i].sas_address.high == 0 &&
1772 oem->phys[i].sas_address.low == 0)
1775 if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1776 for (i = 0; i < SCI_MAX_PHYS; i++)
1777 if (oem->ports[i].phy_mask != 0)
1779 } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1782 for (i = 0; i < SCI_MAX_PHYS; i++)
1783 phy_mask |= oem->ports[i].phy_mask;
1790 if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
1791 oem->controller.max_concurr_spin_up < 1)
1794 if (oem->controller.do_enable_ssc) {
1795 if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
1798 if (version >= ISCI_ROM_VER_1_1) {
1799 u8 test = oem->controller.ssc_sata_tx_spread_level;
1812 test = oem->controller.ssc_sas_tx_spread_level;
1813 if (oem->controller.ssc_sas_tx_type == 0) {
1822 } else if (oem->controller.ssc_sas_tx_type == 1) {
1838 static enum sci_status sci_oem_parameters_set(struct isci_host *ihost)
1840 u32 state = ihost->sm.current_state_id;
1841 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
1843 if (state == SCIC_RESET ||
1844 state == SCIC_INITIALIZING ||
1845 state == SCIC_INITIALIZED) {
1846 u8 oem_version = pci_info->orom ? pci_info->orom->hdr.version :
1849 if (sci_oem_parameters_validate(&ihost->oem_parameters,
1851 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1856 return SCI_FAILURE_INVALID_STATE;
1859 static u8 max_spin_up(struct isci_host *ihost)
1861 if (ihost->user_parameters.max_concurr_spinup)
1862 return min_t(u8, ihost->user_parameters.max_concurr_spinup,
1863 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1865 return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
1866 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1869 static void power_control_timeout(unsigned long data)
1871 struct sci_timer *tmr = (struct sci_timer *)data;
1872 struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
1873 struct isci_phy *iphy;
1874 unsigned long flags;
1877 spin_lock_irqsave(&ihost->scic_lock, flags);
1882 ihost->power_control.phys_granted_power = 0;
1884 if (ihost->power_control.phys_waiting == 0) {
1885 ihost->power_control.timer_started = false;
1889 for (i = 0; i < SCI_MAX_PHYS; i++) {
1891 if (ihost->power_control.phys_waiting == 0)
1894 iphy = ihost->power_control.requesters[i];
1898 if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
1901 ihost->power_control.requesters[i] = NULL;
1902 ihost->power_control.phys_waiting--;
1903 ihost->power_control.phys_granted_power++;
1904 sci_phy_consume_power_handler(iphy);
1906 if (iphy->protocol == SAS_PROTOCOL_SSP) {
1909 for (j = 0; j < SCI_MAX_PHYS; j++) {
1910 struct isci_phy *requester = ihost->power_control.requesters[j];
1913 * Search the power_control queue to see if there are other phys
1914 * attached to the same remote device. If found, take all of
1915 * them out of await_sas_power state.
1917 if (requester != NULL && requester != iphy) {
1918 u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
1919 iphy->frame_rcvd.iaf.sas_addr,
1920 sizeof(requester->frame_rcvd.iaf.sas_addr));
1923 ihost->power_control.requesters[j] = NULL;
1924 ihost->power_control.phys_waiting--;
1925 sci_phy_consume_power_handler(requester);
1933 * It doesn't matter if the power list is empty, we need to start the
1934 * timer in case another phy becomes ready.
1936 sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1937 ihost->power_control.timer_started = true;
1940 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1943 void sci_controller_power_control_queue_insert(struct isci_host *ihost,
1944 struct isci_phy *iphy)
1946 BUG_ON(iphy == NULL);
1948 if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
1949 ihost->power_control.phys_granted_power++;
1950 sci_phy_consume_power_handler(iphy);
1953 * stop and start the power_control timer. When the timer fires, the
1954 * no_of_phys_granted_power will be set to 0
1956 if (ihost->power_control.timer_started)
1957 sci_del_timer(&ihost->power_control.timer);
1959 sci_mod_timer(&ihost->power_control.timer,
1960 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1961 ihost->power_control.timer_started = true;
1965 * There are phys, attached to the same sas address as this phy, are
1966 * already in READY state, this phy don't need wait.
1969 struct isci_phy *current_phy;
1971 for (i = 0; i < SCI_MAX_PHYS; i++) {
1973 current_phy = &ihost->phys[i];
1975 other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
1976 iphy->frame_rcvd.iaf.sas_addr,
1977 sizeof(current_phy->frame_rcvd.iaf.sas_addr));
1979 if (current_phy->sm.current_state_id == SCI_PHY_READY &&
1980 current_phy->protocol == SAS_PROTOCOL_SSP &&
1982 sci_phy_consume_power_handler(iphy);
1987 if (i == SCI_MAX_PHYS) {
1988 /* Add the phy in the waiting list */
1989 ihost->power_control.requesters[iphy->phy_index] = iphy;
1990 ihost->power_control.phys_waiting++;
1995 void sci_controller_power_control_queue_remove(struct isci_host *ihost,
1996 struct isci_phy *iphy)
1998 BUG_ON(iphy == NULL);
2000 if (ihost->power_control.requesters[iphy->phy_index])
2001 ihost->power_control.phys_waiting--;
2003 ihost->power_control.requesters[iphy->phy_index] = NULL;
2006 static int is_long_cable(int phy, unsigned char selection_byte)
2008 return !!(selection_byte & (1 << phy));
2011 static int is_medium_cable(int phy, unsigned char selection_byte)
2013 return !!(selection_byte & (1 << (phy + 4)));
2016 static enum cable_selections decode_selection_byte(
2018 unsigned char selection_byte)
2020 return ((selection_byte & (1 << phy)) ? 1 : 0)
2021 + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
2024 static unsigned char *to_cable_select(struct isci_host *ihost)
2026 if (is_cable_select_overridden())
2027 return ((unsigned char *)&cable_selection_override)
2030 return &ihost->oem_parameters.controller.cable_selection_mask;
2033 enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
2035 return decode_selection_byte(phy, *to_cable_select(ihost));
2038 char *lookup_cable_names(enum cable_selections selection)
2040 static char *cable_names[] = {
2041 [short_cable] = "short",
2042 [long_cable] = "long",
2043 [medium_cable] = "medium",
2044 [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
2046 return (selection <= undefined_cable) ? cable_names[selection]
2047 : cable_names[undefined_cable];
2050 #define AFE_REGISTER_WRITE_DELAY 10
2052 static void sci_controller_afe_initialization(struct isci_host *ihost)
2054 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
2055 const struct sci_oem_params *oem = &ihost->oem_parameters;
2056 struct pci_dev *pdev = ihost->pdev;
2059 unsigned char cable_selection_mask = *to_cable_select(ihost);
2061 /* Clear DFX Status registers */
2062 writel(0x0081000f, &afe->afe_dfx_master_control0);
2063 udelay(AFE_REGISTER_WRITE_DELAY);
2065 if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
2066 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
2067 * Timer, PM Stagger Timer
2069 writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
2070 udelay(AFE_REGISTER_WRITE_DELAY);
2073 /* Configure bias currents to normal */
2075 writel(0x00005A00, &afe->afe_bias_control);
2076 else if (is_b0(pdev) || is_c0(pdev))
2077 writel(0x00005F00, &afe->afe_bias_control);
2078 else if (is_c1(pdev))
2079 writel(0x00005500, &afe->afe_bias_control);
2081 udelay(AFE_REGISTER_WRITE_DELAY);
2085 writel(0x80040908, &afe->afe_pll_control0);
2086 else if (is_b0(pdev) || is_c0(pdev))
2087 writel(0x80040A08, &afe->afe_pll_control0);
2088 else if (is_c1(pdev)) {
2089 writel(0x80000B08, &afe->afe_pll_control0);
2090 udelay(AFE_REGISTER_WRITE_DELAY);
2091 writel(0x00000B08, &afe->afe_pll_control0);
2092 udelay(AFE_REGISTER_WRITE_DELAY);
2093 writel(0x80000B08, &afe->afe_pll_control0);
2096 udelay(AFE_REGISTER_WRITE_DELAY);
2098 /* Wait for the PLL to lock */
2100 afe_status = readl(&afe->afe_common_block_status);
2101 udelay(AFE_REGISTER_WRITE_DELAY);
2102 } while ((afe_status & 0x00001000) == 0);
2105 /* Shorten SAS SNW lock time (RxLock timer value from 76
2108 writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
2109 udelay(AFE_REGISTER_WRITE_DELAY);
2112 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
2113 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id];
2114 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
2115 int cable_length_long =
2116 is_long_cable(phy_id, cable_selection_mask);
2117 int cable_length_medium =
2118 is_medium_cable(phy_id, cable_selection_mask);
2121 /* All defaults, except the Receive Word
2122 * Alignament/Comma Detect Enable....(0xe800)
2124 writel(0x00004512, &xcvr->afe_xcvr_control0);
2125 udelay(AFE_REGISTER_WRITE_DELAY);
2127 writel(0x0050100F, &xcvr->afe_xcvr_control1);
2128 udelay(AFE_REGISTER_WRITE_DELAY);
2129 } else if (is_b0(pdev)) {
2130 /* Configure transmitter SSC parameters */
2131 writel(0x00030000, &xcvr->afe_tx_ssc_control);
2132 udelay(AFE_REGISTER_WRITE_DELAY);
2133 } else if (is_c0(pdev)) {
2134 /* Configure transmitter SSC parameters */
2135 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2136 udelay(AFE_REGISTER_WRITE_DELAY);
2138 /* All defaults, except the Receive Word
2139 * Alignament/Comma Detect Enable....(0xe800)
2141 writel(0x00014500, &xcvr->afe_xcvr_control0);
2142 udelay(AFE_REGISTER_WRITE_DELAY);
2143 } else if (is_c1(pdev)) {
2144 /* Configure transmitter SSC parameters */
2145 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2146 udelay(AFE_REGISTER_WRITE_DELAY);
2148 /* All defaults, except the Receive Word
2149 * Alignament/Comma Detect Enable....(0xe800)
2151 writel(0x0001C500, &xcvr->afe_xcvr_control0);
2152 udelay(AFE_REGISTER_WRITE_DELAY);
2155 /* Power up TX and RX out from power down (PWRDNTX and
2156 * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
2159 writel(0x000003F0, &xcvr->afe_channel_control);
2160 else if (is_b0(pdev)) {
2161 writel(0x000003D7, &xcvr->afe_channel_control);
2162 udelay(AFE_REGISTER_WRITE_DELAY);
2164 writel(0x000003D4, &xcvr->afe_channel_control);
2165 } else if (is_c0(pdev)) {
2166 writel(0x000001E7, &xcvr->afe_channel_control);
2167 udelay(AFE_REGISTER_WRITE_DELAY);
2169 writel(0x000001E4, &xcvr->afe_channel_control);
2170 } else if (is_c1(pdev)) {
2171 writel(cable_length_long ? 0x000002F7 : 0x000001F7,
2172 &xcvr->afe_channel_control);
2173 udelay(AFE_REGISTER_WRITE_DELAY);
2175 writel(cable_length_long ? 0x000002F4 : 0x000001F4,
2176 &xcvr->afe_channel_control);
2178 udelay(AFE_REGISTER_WRITE_DELAY);
2181 /* Enable TX equalization (0xe824) */
2182 writel(0x00040000, &xcvr->afe_tx_control);
2183 udelay(AFE_REGISTER_WRITE_DELAY);
2186 if (is_a2(pdev) || is_b0(pdev))
2187 /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2188 * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2189 * Enabled) ....(0xe800)
2191 writel(0x00004100, &xcvr->afe_xcvr_control0);
2192 else if (is_c0(pdev))
2193 writel(0x00014100, &xcvr->afe_xcvr_control0);
2194 else if (is_c1(pdev))
2195 writel(0x0001C100, &xcvr->afe_xcvr_control0);
2196 udelay(AFE_REGISTER_WRITE_DELAY);
2198 /* Leave DFE/FFE on */
2200 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2201 else if (is_b0(pdev)) {
2202 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2203 udelay(AFE_REGISTER_WRITE_DELAY);
2204 /* Enable TX equalization (0xe824) */
2205 writel(0x00040000, &xcvr->afe_tx_control);
2206 } else if (is_c0(pdev)) {
2207 writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
2208 udelay(AFE_REGISTER_WRITE_DELAY);
2210 writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
2211 udelay(AFE_REGISTER_WRITE_DELAY);
2213 /* Enable TX equalization (0xe824) */
2214 writel(0x00040000, &xcvr->afe_tx_control);
2215 } else if (is_c1(pdev)) {
2216 writel(cable_length_long ? 0x01500C0C :
2217 cable_length_medium ? 0x01400C0D : 0x02400C0D,
2218 &xcvr->afe_xcvr_control1);
2219 udelay(AFE_REGISTER_WRITE_DELAY);
2221 writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
2222 udelay(AFE_REGISTER_WRITE_DELAY);
2224 writel(cable_length_long ? 0x33091C1F :
2225 cable_length_medium ? 0x3315181F : 0x2B17161F,
2226 &xcvr->afe_rx_ssc_control0);
2227 udelay(AFE_REGISTER_WRITE_DELAY);
2229 /* Enable TX equalization (0xe824) */
2230 writel(0x00040000, &xcvr->afe_tx_control);
2233 udelay(AFE_REGISTER_WRITE_DELAY);
2235 writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
2236 udelay(AFE_REGISTER_WRITE_DELAY);
2238 writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
2239 udelay(AFE_REGISTER_WRITE_DELAY);
2241 writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
2242 udelay(AFE_REGISTER_WRITE_DELAY);
2244 writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
2245 udelay(AFE_REGISTER_WRITE_DELAY);
2248 /* Transfer control to the PEs */
2249 writel(0x00010f00, &afe->afe_dfx_master_control0);
2250 udelay(AFE_REGISTER_WRITE_DELAY);
2253 static void sci_controller_initialize_power_control(struct isci_host *ihost)
2255 sci_init_timer(&ihost->power_control.timer, power_control_timeout);
2257 memset(ihost->power_control.requesters, 0,
2258 sizeof(ihost->power_control.requesters));
2260 ihost->power_control.phys_waiting = 0;
2261 ihost->power_control.phys_granted_power = 0;
2264 static enum sci_status sci_controller_initialize(struct isci_host *ihost)
2266 struct sci_base_state_machine *sm = &ihost->sm;
2267 enum sci_status result = SCI_FAILURE;
2268 unsigned long i, state, val;
2270 if (ihost->sm.current_state_id != SCIC_RESET) {
2271 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2272 __func__, ihost->sm.current_state_id);
2273 return SCI_FAILURE_INVALID_STATE;
2276 sci_change_state(sm, SCIC_INITIALIZING);
2278 sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
2280 ihost->next_phy_to_start = 0;
2281 ihost->phy_startup_timer_pending = false;
2283 sci_controller_initialize_power_control(ihost);
2286 * There is nothing to do here for B0 since we do not have to
2287 * program the AFE registers.
2288 * / @todo The AFE settings are supposed to be correct for the B0 but
2289 * / presently they seem to be wrong. */
2290 sci_controller_afe_initialization(ihost);
2293 /* Take the hardware out of reset */
2294 writel(0, &ihost->smu_registers->soft_reset_control);
2297 * / @todo Provide meaningfull error code for hardware failure
2298 * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2299 for (i = 100; i >= 1; i--) {
2302 /* Loop until the hardware reports success */
2303 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2304 status = readl(&ihost->smu_registers->control_status);
2306 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2313 * Determine what are the actaul device capacities that the
2314 * hardware will support */
2315 val = readl(&ihost->smu_registers->device_context_capacity);
2317 /* Record the smaller of the two capacity values */
2318 ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2319 ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2320 ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2323 * Make all PEs that are unassigned match up with the
2326 for (i = 0; i < ihost->logical_port_entries; i++) {
2327 struct scu_port_task_scheduler_group_registers __iomem
2328 *ptsg = &ihost->scu_registers->peg0.ptsg;
2330 writel(i, &ptsg->protocol_engine[i]);
2333 /* Initialize hardware PCI Relaxed ordering in DMA engines */
2334 val = readl(&ihost->scu_registers->sdma.pdma_configuration);
2335 val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2336 writel(val, &ihost->scu_registers->sdma.pdma_configuration);
2338 val = readl(&ihost->scu_registers->sdma.cdma_configuration);
2339 val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2340 writel(val, &ihost->scu_registers->sdma.cdma_configuration);
2343 * Initialize the PHYs before the PORTs because the PHY registers
2344 * are accessed during the port initialization.
2346 for (i = 0; i < SCI_MAX_PHYS; i++) {
2347 result = sci_phy_initialize(&ihost->phys[i],
2348 &ihost->scu_registers->peg0.pe[i].tl,
2349 &ihost->scu_registers->peg0.pe[i].ll);
2350 if (result != SCI_SUCCESS)
2354 for (i = 0; i < ihost->logical_port_entries; i++) {
2355 struct isci_port *iport = &ihost->ports[i];
2357 iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
2358 iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
2359 iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
2362 result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
2365 /* Advance the controller state machine */
2366 if (result == SCI_SUCCESS)
2367 state = SCIC_INITIALIZED;
2369 state = SCIC_FAILED;
2370 sci_change_state(sm, state);
2375 static enum sci_status sci_user_parameters_set(struct isci_host *ihost,
2376 struct sci_user_parameters *sci_parms)
2378 u32 state = ihost->sm.current_state_id;
2380 if (state == SCIC_RESET ||
2381 state == SCIC_INITIALIZING ||
2382 state == SCIC_INITIALIZED) {
2386 * Validate the user parameters. If they are not legal, then
2389 for (index = 0; index < SCI_MAX_PHYS; index++) {
2390 struct sci_phy_user_params *user_phy;
2392 user_phy = &sci_parms->phys[index];
2394 if (!((user_phy->max_speed_generation <=
2395 SCIC_SDS_PARM_MAX_SPEED) &&
2396 (user_phy->max_speed_generation >
2397 SCIC_SDS_PARM_NO_SPEED)))
2398 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2400 if (user_phy->in_connection_align_insertion_frequency <
2402 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2404 if ((user_phy->in_connection_align_insertion_frequency <
2406 (user_phy->align_insertion_frequency == 0) ||
2408 notify_enable_spin_up_insertion_frequency ==
2410 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2413 if ((sci_parms->stp_inactivity_timeout == 0) ||
2414 (sci_parms->ssp_inactivity_timeout == 0) ||
2415 (sci_parms->stp_max_occupancy_timeout == 0) ||
2416 (sci_parms->ssp_max_occupancy_timeout == 0) ||
2417 (sci_parms->no_outbound_task_timeout == 0))
2418 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2420 memcpy(&ihost->user_parameters, sci_parms, sizeof(*sci_parms));
2425 return SCI_FAILURE_INVALID_STATE;
2428 static int sci_controller_mem_init(struct isci_host *ihost)
2430 struct device *dev = &ihost->pdev->dev;
2435 size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2436 ihost->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2437 if (!ihost->completion_queue)
2440 writel(lower_32_bits(dma), &ihost->smu_registers->completion_queue_lower);
2441 writel(upper_32_bits(dma), &ihost->smu_registers->completion_queue_upper);
2443 size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
2444 ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma,
2446 if (!ihost->remote_node_context_table)
2449 writel(lower_32_bits(dma), &ihost->smu_registers->remote_node_context_lower);
2450 writel(upper_32_bits(dma), &ihost->smu_registers->remote_node_context_upper);
2452 size = ihost->task_context_entries * sizeof(struct scu_task_context),
2453 ihost->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2454 if (!ihost->task_context_table)
2457 ihost->task_context_dma = dma;
2458 writel(lower_32_bits(dma), &ihost->smu_registers->host_task_table_lower);
2459 writel(upper_32_bits(dma), &ihost->smu_registers->host_task_table_upper);
2461 err = sci_unsolicited_frame_control_construct(ihost);
2466 * Inform the silicon as to the location of the UF headers and
2469 writel(lower_32_bits(ihost->uf_control.headers.physical_address),
2470 &ihost->scu_registers->sdma.uf_header_base_address_lower);
2471 writel(upper_32_bits(ihost->uf_control.headers.physical_address),
2472 &ihost->scu_registers->sdma.uf_header_base_address_upper);
2474 writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
2475 &ihost->scu_registers->sdma.uf_address_table_lower);
2476 writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
2477 &ihost->scu_registers->sdma.uf_address_table_upper);
2482 int isci_host_init(struct isci_host *ihost)
2485 enum sci_status status;
2486 struct sci_user_parameters sci_user_params;
2487 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
2489 spin_lock_init(&ihost->scic_lock);
2490 init_waitqueue_head(&ihost->eventq);
2492 status = sci_controller_construct(ihost, scu_base(ihost),
2495 if (status != SCI_SUCCESS) {
2496 dev_err(&ihost->pdev->dev,
2497 "%s: sci_controller_construct failed - status = %x\n",
2503 ihost->sas_ha.dev = &ihost->pdev->dev;
2504 ihost->sas_ha.lldd_ha = ihost;
2507 * grab initial values stored in the controller object for OEM and USER
2510 isci_user_parameters_get(&sci_user_params);
2511 status = sci_user_parameters_set(ihost, &sci_user_params);
2512 if (status != SCI_SUCCESS) {
2513 dev_warn(&ihost->pdev->dev,
2514 "%s: sci_user_parameters_set failed\n",
2519 /* grab any OEM parameters specified in orom */
2520 if (pci_info->orom) {
2521 status = isci_parse_oem_parameters(&ihost->oem_parameters,
2524 if (status != SCI_SUCCESS) {
2525 dev_warn(&ihost->pdev->dev,
2526 "parsing firmware oem parameters failed\n");
2531 status = sci_oem_parameters_set(ihost);
2532 if (status != SCI_SUCCESS) {
2533 dev_warn(&ihost->pdev->dev,
2534 "%s: sci_oem_parameters_set failed\n",
2539 tasklet_init(&ihost->completion_tasklet,
2540 isci_host_completion_routine, (unsigned long)ihost);
2542 INIT_LIST_HEAD(&ihost->requests_to_complete);
2543 INIT_LIST_HEAD(&ihost->requests_to_errorback);
2545 spin_lock_irq(&ihost->scic_lock);
2546 status = sci_controller_initialize(ihost);
2547 spin_unlock_irq(&ihost->scic_lock);
2548 if (status != SCI_SUCCESS) {
2549 dev_warn(&ihost->pdev->dev,
2550 "%s: sci_controller_initialize failed -"
2556 err = sci_controller_mem_init(ihost);
2560 for (i = 0; i < SCI_MAX_PORTS; i++)
2561 isci_port_init(&ihost->ports[i], ihost, i);
2563 for (i = 0; i < SCI_MAX_PHYS; i++)
2564 isci_phy_init(&ihost->phys[i], ihost, i);
2567 writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
2568 for (i = 0; i < isci_gpio_count(ihost); i++)
2569 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
2570 writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
2572 for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
2573 struct isci_remote_device *idev = &ihost->devices[i];
2575 INIT_LIST_HEAD(&idev->reqs_in_process);
2576 INIT_LIST_HEAD(&idev->node);
2579 for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
2580 struct isci_request *ireq;
2583 ireq = dmam_alloc_coherent(&ihost->pdev->dev,
2584 sizeof(struct isci_request), &dma,
2589 ireq->tc = &ihost->task_context_table[i];
2590 ireq->owning_controller = ihost;
2591 spin_lock_init(&ireq->state_lock);
2592 ireq->request_daddr = dma;
2593 ireq->isci_host = ihost;
2594 ihost->reqs[i] = ireq;
2600 void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
2601 struct isci_phy *iphy)
2603 switch (ihost->sm.current_state_id) {
2605 sci_del_timer(&ihost->phy_timer);
2606 ihost->phy_startup_timer_pending = false;
2607 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2609 sci_controller_start_next_phy(ihost);
2612 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2616 dev_dbg(&ihost->pdev->dev,
2617 "%s: SCIC Controller linkup event from phy %d in "
2618 "unexpected state %d\n", __func__, iphy->phy_index,
2619 ihost->sm.current_state_id);
2623 void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
2624 struct isci_phy *iphy)
2626 switch (ihost->sm.current_state_id) {
2629 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
2633 dev_dbg(&ihost->pdev->dev,
2634 "%s: SCIC Controller linkdown event from phy %d in "
2635 "unexpected state %d\n",
2638 ihost->sm.current_state_id);
2642 static bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
2646 for (index = 0; index < ihost->remote_node_entries; index++) {
2647 if ((ihost->device_table[index] != NULL) &&
2648 (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2655 void sci_controller_remote_device_stopped(struct isci_host *ihost,
2656 struct isci_remote_device *idev)
2658 if (ihost->sm.current_state_id != SCIC_STOPPING) {
2659 dev_dbg(&ihost->pdev->dev,
2660 "SCIC Controller 0x%p remote device stopped event "
2661 "from device 0x%p in unexpected state %d\n",
2663 ihost->sm.current_state_id);
2667 if (!sci_controller_has_remote_devices_stopping(ihost))
2668 sci_change_state(&ihost->sm, SCIC_STOPPED);
2671 void sci_controller_post_request(struct isci_host *ihost, u32 request)
2673 dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
2674 __func__, ihost->id, request);
2676 writel(request, &ihost->smu_registers->post_context_port);
2679 struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
2684 task_index = ISCI_TAG_TCI(io_tag);
2686 if (task_index < ihost->task_context_entries) {
2687 struct isci_request *ireq = ihost->reqs[task_index];
2689 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
2690 task_sequence = ISCI_TAG_SEQ(io_tag);
2692 if (task_sequence == ihost->io_request_sequence[task_index])
2701 * This method allocates remote node index and the reserves the remote node
2702 * context space for use. This method can fail if there are no more remote
2703 * node index available.
2704 * @scic: This is the controller object which contains the set of
2705 * free remote node ids
2706 * @sci_dev: This is the device object which is requesting the a remote node
2708 * @node_id: This is the remote node id that is assinged to the device if one
2711 * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2712 * node index available.
2714 enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
2715 struct isci_remote_device *idev,
2719 u32 remote_node_count = sci_remote_device_node_count(idev);
2721 node_index = sci_remote_node_table_allocate_remote_node(
2722 &ihost->available_remote_nodes, remote_node_count
2725 if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2726 ihost->device_table[node_index] = idev;
2728 *node_id = node_index;
2733 return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2736 void sci_controller_free_remote_node_context(struct isci_host *ihost,
2737 struct isci_remote_device *idev,
2740 u32 remote_node_count = sci_remote_device_node_count(idev);
2742 if (ihost->device_table[node_id] == idev) {
2743 ihost->device_table[node_id] = NULL;
2745 sci_remote_node_table_release_remote_node_index(
2746 &ihost->available_remote_nodes, remote_node_count, node_id
2751 void sci_controller_copy_sata_response(void *response_buffer,
2755 /* XXX type safety? */
2756 memcpy(response_buffer, frame_header, sizeof(u32));
2758 memcpy(response_buffer + sizeof(u32),
2760 sizeof(struct dev_to_host_fis) - sizeof(u32));
2763 void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
2765 if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
2766 writel(ihost->uf_control.get,
2767 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
2770 void isci_tci_free(struct isci_host *ihost, u16 tci)
2772 u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2774 ihost->tci_pool[tail] = tci;
2775 ihost->tci_tail = tail + 1;
2778 static u16 isci_tci_alloc(struct isci_host *ihost)
2780 u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2781 u16 tci = ihost->tci_pool[head];
2783 ihost->tci_head = head + 1;
2787 static u16 isci_tci_space(struct isci_host *ihost)
2789 return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2792 u16 isci_alloc_tag(struct isci_host *ihost)
2794 if (isci_tci_space(ihost)) {
2795 u16 tci = isci_tci_alloc(ihost);
2796 u8 seq = ihost->io_request_sequence[tci];
2798 return ISCI_TAG(seq, tci);
2801 return SCI_CONTROLLER_INVALID_IO_TAG;
2804 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2806 u16 tci = ISCI_TAG_TCI(io_tag);
2807 u16 seq = ISCI_TAG_SEQ(io_tag);
2809 /* prevent tail from passing head */
2810 if (isci_tci_active(ihost) == 0)
2811 return SCI_FAILURE_INVALID_IO_TAG;
2813 if (seq == ihost->io_request_sequence[tci]) {
2814 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2816 isci_tci_free(ihost, tci);
2820 return SCI_FAILURE_INVALID_IO_TAG;
2823 enum sci_status sci_controller_start_io(struct isci_host *ihost,
2824 struct isci_remote_device *idev,
2825 struct isci_request *ireq)
2827 enum sci_status status;
2829 if (ihost->sm.current_state_id != SCIC_READY) {
2830 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2831 __func__, ihost->sm.current_state_id);
2832 return SCI_FAILURE_INVALID_STATE;
2835 status = sci_remote_device_start_io(ihost, idev, ireq);
2836 if (status != SCI_SUCCESS)
2839 set_bit(IREQ_ACTIVE, &ireq->flags);
2840 sci_controller_post_request(ihost, ireq->post_context);
2844 enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
2845 struct isci_remote_device *idev,
2846 struct isci_request *ireq)
2848 /* terminate an ongoing (i.e. started) core IO request. This does not
2849 * abort the IO request at the target, but rather removes the IO
2850 * request from the host controller.
2852 enum sci_status status;
2854 if (ihost->sm.current_state_id != SCIC_READY) {
2855 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2856 __func__, ihost->sm.current_state_id);
2857 return SCI_FAILURE_INVALID_STATE;
2860 status = sci_io_request_terminate(ireq);
2861 if (status != SCI_SUCCESS)
2865 * Utilize the original post context command and or in the POST_TC_ABORT
2868 sci_controller_post_request(ihost,
2869 ireq->post_context | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2874 * sci_controller_complete_io() - This method will perform core specific
2875 * completion operations for an IO request. After this method is invoked,
2876 * the user should consider the IO request as invalid until it is properly
2877 * reused (i.e. re-constructed).
2878 * @ihost: The handle to the controller object for which to complete the
2880 * @idev: The handle to the remote device object for which to complete
2882 * @ireq: the handle to the io request object to complete.
2884 enum sci_status sci_controller_complete_io(struct isci_host *ihost,
2885 struct isci_remote_device *idev,
2886 struct isci_request *ireq)
2888 enum sci_status status;
2891 switch (ihost->sm.current_state_id) {
2893 /* XXX: Implement this function */
2896 status = sci_remote_device_complete_io(ihost, idev, ireq);
2897 if (status != SCI_SUCCESS)
2900 index = ISCI_TAG_TCI(ireq->io_tag);
2901 clear_bit(IREQ_ACTIVE, &ireq->flags);
2904 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2905 __func__, ihost->sm.current_state_id);
2906 return SCI_FAILURE_INVALID_STATE;
2911 enum sci_status sci_controller_continue_io(struct isci_request *ireq)
2913 struct isci_host *ihost = ireq->owning_controller;
2915 if (ihost->sm.current_state_id != SCIC_READY) {
2916 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2917 __func__, ihost->sm.current_state_id);
2918 return SCI_FAILURE_INVALID_STATE;
2921 set_bit(IREQ_ACTIVE, &ireq->flags);
2922 sci_controller_post_request(ihost, ireq->post_context);
2927 * sci_controller_start_task() - This method is called by the SCIC user to
2928 * send/start a framework task management request.
2929 * @controller: the handle to the controller object for which to start the task
2930 * management request.
2931 * @remote_device: the handle to the remote device object for which to start
2932 * the task management request.
2933 * @task_request: the handle to the task request object to start.
2935 enum sci_task_status sci_controller_start_task(struct isci_host *ihost,
2936 struct isci_remote_device *idev,
2937 struct isci_request *ireq)
2939 enum sci_status status;
2941 if (ihost->sm.current_state_id != SCIC_READY) {
2942 dev_warn(&ihost->pdev->dev,
2943 "%s: SCIC Controller starting task from invalid "
2946 return SCI_TASK_FAILURE_INVALID_STATE;
2949 status = sci_remote_device_start_task(ihost, idev, ireq);
2951 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2952 set_bit(IREQ_ACTIVE, &ireq->flags);
2955 * We will let framework know this task request started successfully,
2956 * although core is still woring on starting the request (to post tc when
2961 set_bit(IREQ_ACTIVE, &ireq->flags);
2962 sci_controller_post_request(ihost, ireq->post_context);
2971 static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
2975 /* no support for TX_GP_CFG */
2979 for (d = 0; d < isci_gpio_count(ihost); d++) {
2980 u32 val = 0x444; /* all ODx.n clear */
2983 for (i = 0; i < 3; i++) {
2984 int bit = (i << 2) + 2;
2986 bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
2987 write_data, reg_index,
2992 /* if od is set, clear the 'invert' bit */
2993 val &= ~(bit << ((i << 2) + 2));
2998 writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
3001 /* unless reg_index is > 1, we should always be able to write at
3002 * least one register
3007 int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
3008 u8 reg_count, u8 *write_data)
3010 struct isci_host *ihost = sas_ha->lldd_ha;
3014 case SAS_GPIO_REG_TX_GP:
3015 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);