2 * Copyright (c) 2000-2014 LSI Corporation.
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
9 * mpi2_cnfg.h Version: 02.00.28
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
22 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
23 * Added Manufacturing Page 11.
24 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
26 * 06-26-07 02.00.02 Adding generic structure for product-specific
27 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
28 * Rework of BIOS Page 2 configuration page.
29 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
31 * Added configuration pages IOC Page 8 and Driver
32 * Persistent Mapping Page 0.
33 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
34 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
35 * RAID Physical Disk Pages 0 and 1, RAID Configuration
37 * Added new value for AccessStatus field of SAS Device
38 * Page 0 (_SATA_NEEDS_INITIALIZATION).
39 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
40 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
41 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
43 * Modified IOC Page 7 to use masks and added field for
44 * SASBroadcastPrimitiveMasks.
45 * Added MPI2_CONFIG_PAGE_BIOS_4.
46 * Added MPI2_CONFIG_PAGE_LOG_0.
47 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
48 * Added SAS Device IDs.
49 * Updated Integrated RAID configuration pages including
50 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
52 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
53 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
54 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
55 * Added missing MaxNumRoutedSasAddresses field to
56 * MPI2_CONFIG_PAGE_EXPANDER_0.
57 * Added SAS Port Page 0.
58 * Modified structure layout for
59 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
60 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
61 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
62 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
64 * Added two new values for the Physical Disk Coercion Size
65 * bits in the Flags field of Manufacturing Page 4.
66 * Added product-specific Manufacturing pages 16 to 31.
67 * Modified Flags bits for controlling write cache on SATA
68 * drives in IO Unit Page 1.
69 * Added new bit to AdditionalControlFlags of SAS IO Unit
70 * Page 1 to control Invalid Topology Correction.
71 * Added additional defines for RAID Volume Page 0
72 * VolumeStatusFlags field.
73 * Modified meaning of RAID Volume Page 0 VolumeSettings
74 * define for auto-configure of hot-swap drives.
75 * Added SupportedPhysDisks field to RAID Volume Page 1 and
76 * added related defines.
77 * Added PhysDiskAttributes field (and related defines) to
78 * RAID Physical Disk Page 0.
79 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
80 * Added three new DiscoveryStatus bits for SAS IO Unit
81 * Page 0 and SAS Expander Page 0.
82 * Removed multiplexing information from SAS IO Unit pages.
83 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
84 * Removed Zone Address Resolved bit from PhyInfo and from
85 * Expander Page 0 Flags field.
86 * Added two new AccessStatus values to SAS Device Page 0
87 * for indicating routing problems. Added 3 reserved words
89 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
90 * Inserted missing reserved field into structure for IOC
92 * Added more pending task bits to RAID Volume Page 0
93 * VolumeStatusFlags defines.
94 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
95 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
96 * and SAS Expander Page 0 to flag a downstream initiator
97 * when in simplified routing mode.
98 * Removed SATA Init Failure defines for DiscoveryStatus
99 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
100 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
101 * Added PortGroups, DmaGroup, and ControlGroup fields to
103 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
105 * Added expander reduced functionality data to SAS
107 * Added SAS PHY Page 2 and SAS PHY Page 3.
108 * 07-30-09 02.00.12 Added IO Unit Page 7.
109 * Added new device ids.
110 * Added SAS IO Unit Page 5.
111 * Added partial and slumber power management capable flags
112 * to SAS Device Page 0 Flags field.
113 * Added PhyInfo defines for power condition.
114 * Added Ethernet configuration pages.
115 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
116 * Added SAS PHY Page 4 structure and defines.
117 * 02-10-10 02.00.14 Modified the comments for the configuration page
118 * structures that contain an array of data. The host
119 * should use the "count" field in the page data (e.g. the
120 * NumPhys field) to determine the number of valid elements
122 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
123 * Added PowerManagementCapabilities to IO Unit Page 7.
124 * Added PortWidthModGroup field to
125 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
126 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
129 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
131 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
132 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
133 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
135 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
136 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
138 * Added BoardTemperature and BoardTemperatureUnits fields
139 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
140 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
141 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
142 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
143 * Added IO Unit Page 8, IO Unit Page 9,
144 * and IO Unit Page 10.
145 * Added SASNotifyPrimitiveMasks field to
146 * MPI2_CONFIG_PAGE_IOC_7.
147 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
148 * 05-25-11 02.00.20 Cleaned up a few comments.
149 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
150 * for PCIe link as obsolete.
151 * Added SpinupFlags field containing a Disable Spin-up bit
152 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
154 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
155 * Added UEFIVersion field to BIOS Page 1 and defined new
157 * Incorporating additions for MPI v2.5.
158 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
159 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
160 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
161 * obsolete for MPI v2.5 and later.
162 * Added some defines for 12G SAS speeds.
163 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
164 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
165 * match the specification.
166 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
168 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
169 * MPI2_CONFIG_PAGE_MAN_7.
170 * Added EnclosureLevel and ConnectorName fields to
171 * MPI2_CONFIG_PAGE_SAS_DEV_0.
172 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
173 * MPI2_CONFIG_PAGE_SAS_DEV_0.
174 * Added EnclosureLevel field to
175 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
176 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
177 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
178 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of
179 * MPI2_CONFIG_PAGE_BIOS_1.
180 * --------------------------------------------------------------------------
186 /*****************************************************************************
187 * Configuration Page Header and defines
188 *****************************************************************************/
190 /*Config Page Header */
191 typedef struct _MPI2_CONFIG_PAGE_HEADER {
192 U8 PageVersion; /*0x00 */
193 U8 PageLength; /*0x01 */
194 U8 PageNumber; /*0x02 */
195 U8 PageType; /*0x03 */
196 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
197 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
199 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
200 MPI2_CONFIG_PAGE_HEADER Struct;
204 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
205 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
207 /*Extended Config Page Header */
208 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
209 U8 PageVersion; /*0x00 */
210 U8 Reserved1; /*0x01 */
211 U8 PageNumber; /*0x02 */
212 U8 PageType; /*0x03 */
213 U16 ExtPageLength; /*0x04 */
214 U8 ExtPageType; /*0x06 */
215 U8 Reserved2; /*0x07 */
216 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
217 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
218 Mpi2ConfigExtendedPageHeader_t,
219 *pMpi2ConfigExtendedPageHeader_t;
221 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
222 MPI2_CONFIG_PAGE_HEADER Struct;
223 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
227 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
228 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
229 Mpi2ConfigPageExtendedHeaderUnion,
230 *pMpi2ConfigPageExtendedHeaderUnion;
233 /*PageType field values */
234 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
235 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
236 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
237 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
239 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
240 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
241 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
242 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
243 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
244 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
245 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
246 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
248 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
251 /*ExtPageType field values */
252 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
253 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
254 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
255 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
256 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
257 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
258 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
259 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
260 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
261 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
262 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
265 /*****************************************************************************
266 * PageAddress defines
267 *****************************************************************************/
269 /*RAID Volume PageAddress format */
270 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
271 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
272 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
274 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
277 /*RAID Physical Disk PageAddress format */
278 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
279 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
280 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
281 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
283 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
284 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
287 /*SAS Expander PageAddress format */
288 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
289 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
290 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
291 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
293 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
294 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
295 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
298 /*SAS Device PageAddress format */
299 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
300 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
301 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
303 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
306 /*SAS PHY PageAddress format */
307 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
308 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
309 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
311 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
312 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
315 /*SAS Port PageAddress format */
316 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
317 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
318 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
320 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
323 /*SAS Enclosure PageAddress format */
324 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
325 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
326 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
328 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
331 /*RAID Configuration PageAddress format */
332 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
333 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
334 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
335 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
337 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
340 /*Driver Persistent Mapping PageAddress format */
341 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
342 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
344 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
345 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
346 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
349 /*Ethernet PageAddress format */
350 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
351 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
353 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
357 /****************************************************************************
358 * Configuration messages
359 ****************************************************************************/
361 /*Configuration Request Message */
362 typedef struct _MPI2_CONFIG_REQUEST {
364 U8 SGLFlags; /*0x01 */
365 U8 ChainOffset; /*0x02 */
366 U8 Function; /*0x03 */
367 U16 ExtPageLength; /*0x04 */
368 U8 ExtPageType; /*0x06 */
369 U8 MsgFlags; /*0x07 */
372 U16 Reserved1; /*0x0A */
373 U8 Reserved2; /*0x0C */
374 U8 ProxyVF_ID; /*0x0D */
375 U16 Reserved4; /*0x0E */
376 U32 Reserved3; /*0x10 */
377 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
378 U32 PageAddress; /*0x18 */
379 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */
380 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
381 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
383 /*values for the Action field */
384 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
385 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
386 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
387 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
388 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
389 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
390 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
391 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
393 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
396 /*Config Reply Message */
397 typedef struct _MPI2_CONFIG_REPLY {
399 U8 SGLFlags; /*0x01 */
400 U8 MsgLength; /*0x02 */
401 U8 Function; /*0x03 */
402 U16 ExtPageLength; /*0x04 */
403 U8 ExtPageType; /*0x06 */
404 U8 MsgFlags; /*0x07 */
407 U16 Reserved1; /*0x0A */
408 U16 Reserved2; /*0x0C */
409 U16 IOCStatus; /*0x0E */
410 U32 IOCLogInfo; /*0x10 */
411 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
412 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
413 Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
417 /*****************************************************************************
419 * C o n f i g u r a t i o n P a g e s
421 *****************************************************************************/
423 /****************************************************************************
424 * Manufacturing Config pages
425 ****************************************************************************/
427 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
429 /*MPI v2.0 SAS products */
430 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
431 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
432 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
433 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
434 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
435 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
436 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
438 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
440 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
441 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
442 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
443 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
444 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
445 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
446 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
447 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
448 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
450 /*MPI v2.5 SAS products */
451 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
452 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
453 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
454 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
455 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
456 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
461 /*Manufacturing Page 0 */
463 typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
464 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
465 U8 ChipName[16]; /*0x04 */
466 U8 ChipRevision[8]; /*0x14 */
467 U8 BoardName[16]; /*0x1C */
468 U8 BoardAssembly[16]; /*0x2C */
469 U8 BoardTracerNumber[16]; /*0x3C */
470 } MPI2_CONFIG_PAGE_MAN_0,
471 *PTR_MPI2_CONFIG_PAGE_MAN_0,
472 Mpi2ManufacturingPage0_t,
473 *pMpi2ManufacturingPage0_t;
475 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
478 /*Manufacturing Page 1 */
480 typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
481 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
482 U8 VPD[256]; /*0x04 */
483 } MPI2_CONFIG_PAGE_MAN_1,
484 *PTR_MPI2_CONFIG_PAGE_MAN_1,
485 Mpi2ManufacturingPage1_t,
486 *pMpi2ManufacturingPage1_t;
488 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
491 typedef struct _MPI2_CHIP_REVISION_ID {
492 U16 DeviceID; /*0x00 */
493 U8 PCIRevisionID; /*0x02 */
494 U8 Reserved; /*0x03 */
495 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
496 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
499 /*Manufacturing Page 2 */
502 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
503 *one and check Header.PageLength at runtime.
505 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
506 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
509 typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
510 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
511 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
513 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */
514 } MPI2_CONFIG_PAGE_MAN_2,
515 *PTR_MPI2_CONFIG_PAGE_MAN_2,
516 Mpi2ManufacturingPage2_t,
517 *pMpi2ManufacturingPage2_t;
519 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
522 /*Manufacturing Page 3 */
525 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
526 *one and check Header.PageLength at runtime.
528 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
529 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
532 typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
533 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
534 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
536 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */
537 } MPI2_CONFIG_PAGE_MAN_3,
538 *PTR_MPI2_CONFIG_PAGE_MAN_3,
539 Mpi2ManufacturingPage3_t,
540 *pMpi2ManufacturingPage3_t;
542 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
545 /*Manufacturing Page 4 */
547 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
548 U8 PowerSaveFlags; /*0x00 */
549 U8 InternalOperationsSleepTime; /*0x01 */
550 U8 InternalOperationsRunTime; /*0x02 */
551 U8 HostIdleTime; /*0x03 */
552 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
553 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
554 Mpi2ManPage4PwrSaveSettings_t,
555 *pMpi2ManPage4PwrSaveSettings_t;
557 /*defines for the PowerSaveFlags field */
558 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
559 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
560 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
561 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
563 typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
564 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
565 U32 Reserved1; /*0x04 */
567 U8 InquirySize; /*0x0C */
568 U8 Reserved2; /*0x0D */
569 U16 Reserved3; /*0x0E */
570 U8 InquiryData[56]; /*0x10 */
571 U32 RAID0VolumeSettings; /*0x48 */
572 U32 RAID1EVolumeSettings; /*0x4C */
573 U32 RAID1VolumeSettings; /*0x50 */
574 U32 RAID10VolumeSettings; /*0x54 */
575 U32 Reserved4; /*0x58 */
576 U32 Reserved5; /*0x5C */
577 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */
578 U8 MaxOCEDisks; /*0x64 */
579 U8 ResyncRate; /*0x65 */
580 U16 DataScrubDuration; /*0x66 */
581 U8 MaxHotSpares; /*0x68 */
582 U8 MaxPhysDisksPerVol; /*0x69 */
583 U8 MaxPhysDisks; /*0x6A */
584 U8 MaxVolumes; /*0x6B */
585 } MPI2_CONFIG_PAGE_MAN_4,
586 *PTR_MPI2_CONFIG_PAGE_MAN_4,
587 Mpi2ManufacturingPage4_t,
588 *pMpi2ManufacturingPage4_t;
590 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
592 /*Manufacturing Page 4 Flags field */
593 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
594 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
596 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
597 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
598 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
600 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
601 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
602 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
603 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
604 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
606 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
607 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
608 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
609 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
611 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
612 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
613 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
614 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
615 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
616 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
617 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
618 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
621 /*Manufacturing Page 5 */
624 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
625 *one and check the value returned for NumPhys at runtime.
627 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
628 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
631 typedef struct _MPI2_MANUFACTURING5_ENTRY {
633 U64 DeviceName; /*0x08 */
634 } MPI2_MANUFACTURING5_ENTRY,
635 *PTR_MPI2_MANUFACTURING5_ENTRY,
636 Mpi2Manufacturing5Entry_t,
637 *pMpi2Manufacturing5Entry_t;
639 typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
640 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
641 U8 NumPhys; /*0x04 */
642 U8 Reserved1; /*0x05 */
643 U16 Reserved2; /*0x06 */
644 U32 Reserved3; /*0x08 */
645 U32 Reserved4; /*0x0C */
646 MPI2_MANUFACTURING5_ENTRY
647 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */
648 } MPI2_CONFIG_PAGE_MAN_5,
649 *PTR_MPI2_CONFIG_PAGE_MAN_5,
650 Mpi2ManufacturingPage5_t,
651 *pMpi2ManufacturingPage5_t;
653 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
656 /*Manufacturing Page 6 */
658 typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
659 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
660 U32 ProductSpecificInfo;/*0x04 */
661 } MPI2_CONFIG_PAGE_MAN_6,
662 *PTR_MPI2_CONFIG_PAGE_MAN_6,
663 Mpi2ManufacturingPage6_t,
664 *pMpi2ManufacturingPage6_t;
666 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
669 /*Manufacturing Page 7 */
671 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
672 U32 Pinout; /*0x00 */
673 U8 Connector[16]; /*0x04 */
674 U8 Location; /*0x14 */
675 U8 ReceptacleID; /*0x15 */
677 U32 Reserved2; /*0x18 */
678 } MPI2_MANPAGE7_CONNECTOR_INFO,
679 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
680 Mpi2ManPage7ConnectorInfo_t,
681 *pMpi2ManPage7ConnectorInfo_t;
683 /*defines for the Pinout field */
684 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
685 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
687 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
688 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
689 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
690 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
691 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
692 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
693 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
694 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
695 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
696 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
697 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
698 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
699 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
700 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
701 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
703 /*defines for the Location field */
704 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
705 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
706 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
707 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
708 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
709 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
710 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
713 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
714 *one and check the value returned for NumPhys at runtime.
716 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
717 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
720 typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
721 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
722 U32 Reserved1; /*0x04 */
723 U32 Reserved2; /*0x08 */
725 U8 EnclosureName[16]; /*0x10 */
726 U8 NumPhys; /*0x20 */
727 U8 Reserved3; /*0x21 */
728 U16 Reserved4; /*0x22 */
729 MPI2_MANPAGE7_CONNECTOR_INFO
730 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */
731 } MPI2_CONFIG_PAGE_MAN_7,
732 *PTR_MPI2_CONFIG_PAGE_MAN_7,
733 Mpi2ManufacturingPage7_t,
734 *pMpi2ManufacturingPage7_t;
736 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
738 /*defines for the Flags field */
739 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
740 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
741 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
745 *Generic structure to use for product-specific manufacturing pages
746 *(currently Manufacturing Page 8 through Manufacturing Page 31).
749 typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
750 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
751 U32 ProductSpecificInfo;/*0x04 */
752 } MPI2_CONFIG_PAGE_MAN_PS,
753 *PTR_MPI2_CONFIG_PAGE_MAN_PS,
754 Mpi2ManufacturingPagePS_t,
755 *pMpi2ManufacturingPagePS_t;
757 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
758 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
759 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
760 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
761 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
762 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
763 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
764 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
765 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
766 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
767 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
768 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
769 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
770 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
771 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
772 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
773 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
774 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
775 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
776 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
777 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
778 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
779 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
780 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
783 /****************************************************************************
784 * IO Unit Config Pages
785 ****************************************************************************/
789 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
790 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
791 U64 UniqueValue; /*0x04 */
792 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */
793 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */
794 } MPI2_CONFIG_PAGE_IO_UNIT_0,
795 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
796 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
798 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
803 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
804 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
806 } MPI2_CONFIG_PAGE_IO_UNIT_1,
807 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
808 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
810 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
812 /*IO Unit Page 1 Flags defines */
813 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
814 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
815 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
816 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
817 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
818 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
819 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
820 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
821 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
822 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
823 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
824 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
825 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
831 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
832 *one and check the value returned for GPIOCount at runtime.
834 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
835 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
838 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
839 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
840 U8 GPIOCount; /*0x04 */
841 U8 Reserved1; /*0x05 */
842 U16 Reserved2; /*0x06 */
844 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
845 } MPI2_CONFIG_PAGE_IO_UNIT_3,
846 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
847 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
849 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
851 /*defines for IO Unit Page 3 GPIOVal field */
852 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
853 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
854 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
855 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
861 *Upper layer code (drivers, utilities, etc.) should leave this define set to
862 *one and check the value returned for NumDmaEngines at runtime.
864 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
865 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
868 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
869 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
871 RaidAcceleratorBufferBaseAddress; /*0x04 */
873 RaidAcceleratorBufferSize; /*0x0C */
875 RaidAcceleratorControlBaseAddress; /*0x14 */
876 U8 RAControlSize; /*0x1C */
877 U8 NumDmaEngines; /*0x1D */
878 U8 RAMinControlSize; /*0x1E */
879 U8 RAMaxControlSize; /*0x1F */
880 U32 Reserved1; /*0x20 */
881 U32 Reserved2; /*0x24 */
882 U32 Reserved3; /*0x28 */
884 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */
885 } MPI2_CONFIG_PAGE_IO_UNIT_5,
886 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
887 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
889 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
891 /*defines for IO Unit Page 5 DmaEngineCapabilities field */
892 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
893 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
895 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
896 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
897 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
898 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
903 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
904 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
906 U8 RAHostControlSize; /*0x06 */
907 U8 Reserved0; /*0x07 */
909 RaidAcceleratorHostControlBaseAddress; /*0x08 */
910 U32 Reserved1; /*0x10 */
911 U32 Reserved2; /*0x14 */
912 U32 Reserved3; /*0x18 */
913 } MPI2_CONFIG_PAGE_IO_UNIT_6,
914 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
915 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
917 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
919 /*defines for IO Unit Page 6 Flags field */
920 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
925 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
926 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
927 U8 CurrentPowerMode; /*0x04 */
928 U8 PreviousPowerMode; /*0x05 */
929 U8 PCIeWidth; /*0x06 */
930 U8 PCIeSpeed; /*0x07 */
931 U32 ProcessorState; /*0x08 */
933 PowerManagementCapabilities; /*0x0C */
934 U16 IOCTemperature; /*0x10 */
936 IOCTemperatureUnits; /*0x12 */
937 U8 IOCSpeed; /*0x13 */
938 U16 BoardTemperature; /*0x14 */
940 BoardTemperatureUnits; /*0x16 */
941 U8 Reserved3; /*0x17 */
942 U32 Reserved4; /* 0x18 */
943 U32 Reserved5; /* 0x1C */
944 U32 Reserved6; /* 0x20 */
945 U32 Reserved7; /* 0x24 */
946 } MPI2_CONFIG_PAGE_IO_UNIT_7,
947 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
948 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
950 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x04)
952 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
953 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0)
954 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00)
955 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40)
956 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80)
957 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0)
959 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07)
960 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00)
961 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01)
962 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04)
963 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05)
964 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06)
967 /*defines for IO Unit Page 7 PCIeWidth field */
968 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
969 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
970 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
971 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
973 /*defines for IO Unit Page 7 PCIeSpeed field */
974 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
975 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
976 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
978 /*defines for IO Unit Page 7 ProcessorState field */
979 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
980 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
982 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
983 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
984 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
986 /*defines for IO Unit Page 7 PowerManagementCapabilities field */
987 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000)
988 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000)
989 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000)
990 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000)
991 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000)
992 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000)
993 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000)
994 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000)
995 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000)
996 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400)
997 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200)
998 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100)
999 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040)
1000 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020)
1001 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010)
1002 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008)
1003 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004)
1004 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002)
1005 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001)
1007 /*obsolete names for the PowerManagementCapabilities bits (above) */
1008 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
1009 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
1010 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
1011 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */
1012 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */
1015 /*defines for IO Unit Page 7 IOCTemperatureUnits field */
1016 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
1017 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
1018 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
1020 /*defines for IO Unit Page 7 IOCSpeed field */
1021 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
1022 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
1023 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
1024 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
1026 /*defines for IO Unit Page 7 BoardTemperatureUnits field */
1027 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
1028 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
1029 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
1034 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
1036 typedef struct _MPI2_IOUNIT8_SENSOR {
1037 U16 Flags; /*0x00 */
1038 U16 Reserved1; /*0x02 */
1040 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1041 U32 Reserved2; /*0x0C */
1042 U32 Reserved3; /*0x10 */
1043 U32 Reserved4; /*0x14 */
1044 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1045 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1047 /*defines for IO Unit Page 8 Sensor Flags field */
1048 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
1049 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
1050 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
1051 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
1054 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1055 *one and check the value returned for NumSensors at runtime.
1057 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1058 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
1061 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1062 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1063 U32 Reserved1; /*0x04 */
1064 U32 Reserved2; /*0x08 */
1065 U8 NumSensors; /*0x0C */
1066 U8 PollingInterval; /*0x0D */
1067 U16 Reserved3; /*0x0E */
1069 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */
1070 } MPI2_CONFIG_PAGE_IO_UNIT_8,
1071 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1072 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1074 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1079 typedef struct _MPI2_IOUNIT9_SENSOR {
1080 U16 CurrentTemperature; /*0x00 */
1081 U16 Reserved1; /*0x02 */
1083 U8 Reserved2; /*0x05 */
1084 U16 Reserved3; /*0x06 */
1085 U32 Reserved4; /*0x08 */
1086 U32 Reserved5; /*0x0C */
1087 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1088 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1090 /*defines for IO Unit Page 9 Sensor Flags field */
1091 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1094 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1095 *one and check the value returned for NumSensors at runtime.
1097 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1098 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1101 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1102 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1103 U32 Reserved1; /*0x04 */
1104 U32 Reserved2; /*0x08 */
1105 U8 NumSensors; /*0x0C */
1106 U8 Reserved4; /*0x0D */
1107 U16 Reserved3; /*0x0E */
1109 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */
1110 } MPI2_CONFIG_PAGE_IO_UNIT_9,
1111 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1112 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1114 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1117 /*IO Unit Page 10 */
1119 typedef struct _MPI2_IOUNIT10_FUNCTION {
1120 U8 CreditPercent; /*0x00 */
1121 U8 Reserved1; /*0x01 */
1122 U16 Reserved2; /*0x02 */
1123 } MPI2_IOUNIT10_FUNCTION,
1124 *PTR_MPI2_IOUNIT10_FUNCTION,
1125 Mpi2IOUnit10Function_t,
1126 *pMpi2IOUnit10Function_t;
1129 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1130 *one and check the value returned for NumFunctions at runtime.
1132 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1133 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1136 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1137 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1138 U8 NumFunctions; /*0x04 */
1139 U8 Reserved1; /*0x05 */
1140 U16 Reserved2; /*0x06 */
1141 U32 Reserved3; /*0x08 */
1142 U32 Reserved4; /*0x0C */
1143 MPI2_IOUNIT10_FUNCTION
1144 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */
1145 } MPI2_CONFIG_PAGE_IO_UNIT_10,
1146 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1147 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1149 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1153 /****************************************************************************
1155 ****************************************************************************/
1159 typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1160 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1161 U32 Reserved1; /*0x04 */
1162 U32 Reserved2; /*0x08 */
1163 U16 VendorID; /*0x0C */
1164 U16 DeviceID; /*0x0E */
1165 U8 RevisionID; /*0x10 */
1166 U8 Reserved3; /*0x11 */
1167 U16 Reserved4; /*0x12 */
1168 U32 ClassCode; /*0x14 */
1169 U16 SubsystemVendorID; /*0x18 */
1170 U16 SubsystemID; /*0x1A */
1171 } MPI2_CONFIG_PAGE_IOC_0,
1172 *PTR_MPI2_CONFIG_PAGE_IOC_0,
1173 Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1175 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1180 typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1181 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1182 U32 Flags; /*0x04 */
1183 U32 CoalescingTimeout; /*0x08 */
1184 U8 CoalescingDepth; /*0x0C */
1185 U8 PCISlotNum; /*0x0D */
1186 U8 PCIBusNum; /*0x0E */
1187 U8 PCIDomainSegment; /*0x0F */
1188 U32 Reserved1; /*0x10 */
1189 U32 Reserved2; /*0x14 */
1190 } MPI2_CONFIG_PAGE_IOC_1,
1191 *PTR_MPI2_CONFIG_PAGE_IOC_1,
1192 Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1194 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1196 /*defines for IOC Page 1 Flags field */
1197 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1199 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1200 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1201 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1205 typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1206 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1208 CapabilitiesFlags; /*0x04 */
1209 U8 MaxDrivesRAID0; /*0x08 */
1210 U8 MaxDrivesRAID1; /*0x09 */
1212 MaxDrivesRAID1E; /*0x0A */
1214 MaxDrivesRAID10; /*0x0B */
1215 U8 MinDrivesRAID0; /*0x0C */
1216 U8 MinDrivesRAID1; /*0x0D */
1218 MinDrivesRAID1E; /*0x0E */
1220 MinDrivesRAID10; /*0x0F */
1221 U32 Reserved1; /*0x10 */
1223 MaxGlobalHotSpares; /*0x14 */
1224 U8 MaxPhysDisks; /*0x15 */
1225 U8 MaxVolumes; /*0x16 */
1226 U8 MaxConfigs; /*0x17 */
1227 U8 MaxOCEDisks; /*0x18 */
1228 U8 Reserved2; /*0x19 */
1229 U16 Reserved3; /*0x1A */
1231 SupportedStripeSizeMapRAID0; /*0x1C */
1233 SupportedStripeSizeMapRAID1E; /*0x20 */
1235 SupportedStripeSizeMapRAID10; /*0x24 */
1236 U32 Reserved4; /*0x28 */
1237 U32 Reserved5; /*0x2C */
1239 DefaultMetadataSize; /*0x30 */
1240 U16 Reserved6; /*0x32 */
1242 MaxBadBlockTableEntries; /*0x34 */
1243 U16 Reserved7; /*0x36 */
1245 IRNvsramVersion; /*0x38 */
1246 } MPI2_CONFIG_PAGE_IOC_6,
1247 *PTR_MPI2_CONFIG_PAGE_IOC_6,
1248 Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1250 #define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1252 /*defines for IOC Page 6 CapabilitiesFlags */
1253 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1254 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1255 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1256 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1257 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1258 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1263 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1265 typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1266 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1267 U32 Reserved1; /*0x04 */
1269 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1270 U16 SASBroadcastPrimitiveMasks; /*0x18 */
1271 U16 SASNotifyPrimitiveMasks; /*0x1A */
1272 U32 Reserved3; /*0x1C */
1273 } MPI2_CONFIG_PAGE_IOC_7,
1274 *PTR_MPI2_CONFIG_PAGE_IOC_7,
1275 Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1277 #define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1282 typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1283 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1284 U8 NumDevsPerEnclosure; /*0x04 */
1285 U8 Reserved1; /*0x05 */
1286 U16 Reserved2; /*0x06 */
1287 U16 MaxPersistentEntries; /*0x08 */
1288 U16 MaxNumPhysicalMappedIDs; /*0x0A */
1289 U16 Flags; /*0x0C */
1290 U16 Reserved3; /*0x0E */
1291 U16 IRVolumeMappingFlags; /*0x10 */
1292 U16 Reserved4; /*0x12 */
1293 U32 Reserved5; /*0x14 */
1294 } MPI2_CONFIG_PAGE_IOC_8,
1295 *PTR_MPI2_CONFIG_PAGE_IOC_8,
1296 Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1298 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1300 /*defines for IOC Page 8 Flags field */
1301 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1302 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1304 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1305 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1306 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1308 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1309 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1311 /*defines for IOC Page 8 IRVolumeMappingFlags */
1312 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1313 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1314 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1317 /****************************************************************************
1319 ****************************************************************************/
1323 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1324 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1325 U32 BiosOptions; /*0x04 */
1326 U32 IOCSettings; /*0x08 */
1327 U32 Reserved1; /*0x0C */
1328 U32 DeviceSettings; /*0x10 */
1329 U16 NumberOfDevices; /*0x14 */
1330 U16 UEFIVersion; /*0x16 */
1331 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */
1332 U16 IOTimeoutSequential; /*0x1A */
1333 U16 IOTimeoutOther; /*0x1C */
1334 U16 IOTimeoutBlockDevicesRM; /*0x1E */
1335 } MPI2_CONFIG_PAGE_BIOS_1,
1336 *PTR_MPI2_CONFIG_PAGE_BIOS_1,
1337 Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1339 #define MPI2_BIOSPAGE1_PAGEVERSION (0x06)
1341 /*values for BIOS Page 1 BiosOptions field */
1342 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400)
1344 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300)
1345 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000)
1346 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100)
1347 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200)
1348 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300)
1350 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1351 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1353 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1354 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1355 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1356 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1358 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1360 /*values for BIOS Page 1 IOCSettings field */
1361 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1362 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1363 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1365 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1366 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1367 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1368 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1370 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1371 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1372 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1373 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1374 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1376 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1378 /*values for BIOS Page 1 DeviceSettings field */
1379 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1380 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1381 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1382 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1383 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1385 /*defines for BIOS Page 1 UEFIVersion field */
1386 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1387 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1388 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1389 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1395 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1396 U32 Reserved1; /*0x00 */
1397 U32 Reserved2; /*0x04 */
1398 U32 Reserved3; /*0x08 */
1399 U32 Reserved4; /*0x0C */
1400 U32 Reserved5; /*0x10 */
1401 U32 Reserved6; /*0x14 */
1402 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1403 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1404 Mpi2BootDeviceAdapterOrder_t,
1405 *pMpi2BootDeviceAdapterOrder_t;
1407 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1408 U64 SASAddress; /*0x00 */
1409 U8 LUN[8]; /*0x08 */
1410 U32 Reserved1; /*0x10 */
1411 U32 Reserved2; /*0x14 */
1412 } MPI2_BOOT_DEVICE_SAS_WWID,
1413 *PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1414 Mpi2BootDeviceSasWwid_t,
1415 *pMpi2BootDeviceSasWwid_t;
1417 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1418 U64 EnclosureLogicalID; /*0x00 */
1419 U32 Reserved1; /*0x08 */
1420 U32 Reserved2; /*0x0C */
1421 U16 SlotNumber; /*0x10 */
1422 U16 Reserved3; /*0x12 */
1423 U32 Reserved4; /*0x14 */
1424 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1425 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1426 Mpi2BootDeviceEnclosureSlot_t,
1427 *pMpi2BootDeviceEnclosureSlot_t;
1429 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1430 U64 DeviceName; /*0x00 */
1431 U8 LUN[8]; /*0x08 */
1432 U32 Reserved1; /*0x10 */
1433 U32 Reserved2; /*0x14 */
1434 } MPI2_BOOT_DEVICE_DEVICE_NAME,
1435 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1436 Mpi2BootDeviceDeviceName_t,
1437 *pMpi2BootDeviceDeviceName_t;
1439 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1440 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1441 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1442 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1443 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1444 } MPI2_BIOSPAGE2_BOOT_DEVICE,
1445 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1446 Mpi2BiosPage2BootDevice_t,
1447 *pMpi2BiosPage2BootDevice_t;
1449 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1450 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1451 U32 Reserved1; /*0x04 */
1452 U32 Reserved2; /*0x08 */
1453 U32 Reserved3; /*0x0C */
1454 U32 Reserved4; /*0x10 */
1455 U32 Reserved5; /*0x14 */
1456 U32 Reserved6; /*0x18 */
1457 U8 ReqBootDeviceForm; /*0x1C */
1458 U8 Reserved7; /*0x1D */
1459 U16 Reserved8; /*0x1E */
1460 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */
1461 U8 ReqAltBootDeviceForm; /*0x38 */
1462 U8 Reserved9; /*0x39 */
1463 U16 Reserved10; /*0x3A */
1464 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */
1465 U8 CurrentBootDeviceForm; /*0x58 */
1466 U8 Reserved11; /*0x59 */
1467 U16 Reserved12; /*0x5A */
1468 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */
1469 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1470 Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1472 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1474 /*values for BIOS Page 2 BootDeviceForm fields */
1475 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1476 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1477 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1478 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1479 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1484 typedef struct _MPI2_ADAPTER_INFO {
1485 U8 PciBusNumber; /*0x00 */
1486 U8 PciDeviceAndFunctionNumber; /*0x01 */
1487 U16 AdapterFlags; /*0x02 */
1488 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1489 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1491 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1492 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1494 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1495 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1496 U32 GlobalFlags; /*0x04 */
1497 U32 BiosVersion; /*0x08 */
1498 MPI2_ADAPTER_INFO AdapterOrder[4]; /*0x0C */
1499 U32 Reserved1; /*0x1C */
1500 } MPI2_CONFIG_PAGE_BIOS_3,
1501 *PTR_MPI2_CONFIG_PAGE_BIOS_3,
1502 Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1504 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1506 /*values for BIOS Page 3 GlobalFlags */
1507 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1508 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1509 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1511 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1512 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1513 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1514 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1520 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1521 *one and check the value returned for NumPhys at runtime.
1523 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1524 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1527 typedef struct _MPI2_BIOS4_ENTRY {
1528 U64 ReassignmentWWID; /*0x00 */
1529 U64 ReassignmentDeviceName; /*0x08 */
1530 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1531 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1533 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1534 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1535 U8 NumPhys; /*0x04 */
1536 U8 Reserved1; /*0x05 */
1537 U16 Reserved2; /*0x06 */
1539 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */
1540 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1541 Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1543 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1546 /****************************************************************************
1547 * RAID Volume Config Pages
1548 ****************************************************************************/
1550 /*RAID Volume Page 0 */
1552 typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1553 U8 RAIDSetNum; /*0x00 */
1554 U8 PhysDiskMap; /*0x01 */
1555 U8 PhysDiskNum; /*0x02 */
1556 U8 Reserved; /*0x03 */
1557 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1558 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1560 /*defines for the PhysDiskMap field */
1561 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1562 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1564 typedef struct _MPI2_RAIDVOL0_SETTINGS {
1565 U16 Settings; /*0x00 */
1566 U8 HotSparePool; /*0x01 */
1567 U8 Reserved; /*0x02 */
1568 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1569 Mpi2RaidVol0Settings_t,
1570 *pMpi2RaidVol0Settings_t;
1572 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1573 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1574 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1575 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1576 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1577 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1578 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1579 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1580 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1582 /*RAID Volume Page 0 VolumeSettings defines */
1583 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1584 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1586 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1587 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1588 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1589 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1592 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1593 *one and check the value returned for NumPhysDisks at runtime.
1595 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1596 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1599 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1600 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1601 U16 DevHandle; /*0x04 */
1602 U8 VolumeState; /*0x06 */
1603 U8 VolumeType; /*0x07 */
1604 U32 VolumeStatusFlags; /*0x08 */
1605 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */
1606 U64 MaxLBA; /*0x10 */
1607 U32 StripeSize; /*0x18 */
1608 U16 BlockSize; /*0x1C */
1609 U16 Reserved1; /*0x1E */
1610 U8 SupportedPhysDisks;/*0x20 */
1611 U8 ResyncRate; /*0x21 */
1612 U16 DataScrubDuration; /*0x22 */
1613 U8 NumPhysDisks; /*0x24 */
1614 U8 Reserved2; /*0x25 */
1615 U8 Reserved3; /*0x26 */
1616 U8 InactiveStatus; /*0x27 */
1617 MPI2_RAIDVOL0_PHYS_DISK
1618 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */
1619 } MPI2_CONFIG_PAGE_RAID_VOL_0,
1620 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1621 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1623 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1625 /*values for RAID VolumeState */
1626 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1627 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1628 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1629 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1630 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1631 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1633 /*values for RAID VolumeType */
1634 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1635 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1636 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1637 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1638 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1640 /*values for RAID Volume Page 0 VolumeStatusFlags field */
1641 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1642 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1643 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1644 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1645 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1646 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1647 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1648 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1649 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1650 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1651 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1652 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1653 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1654 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1655 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1656 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1657 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1658 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1659 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1661 /*values for RAID Volume Page 0 SupportedPhysDisks field */
1662 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1663 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1664 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1665 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1667 /*values for RAID Volume Page 0 InactiveStatus field */
1668 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1669 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1670 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1671 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1672 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1673 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1674 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1677 /*RAID Volume Page 1 */
1679 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1680 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1681 U16 DevHandle; /*0x04 */
1682 U16 Reserved0; /*0x06 */
1683 U8 GUID[24]; /*0x08 */
1684 U8 Name[16]; /*0x20 */
1686 U32 Reserved1; /*0x38 */
1687 U32 Reserved2; /*0x3C */
1688 } MPI2_CONFIG_PAGE_RAID_VOL_1,
1689 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1690 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1692 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1695 /****************************************************************************
1696 * RAID Physical Disk Config Pages
1697 ****************************************************************************/
1699 /*RAID Physical Disk Page 0 */
1701 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1702 U16 Reserved1; /*0x00 */
1703 U8 HotSparePool; /*0x02 */
1704 U8 Reserved2; /*0x03 */
1705 } MPI2_RAIDPHYSDISK0_SETTINGS,
1706 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1707 Mpi2RaidPhysDisk0Settings_t,
1708 *pMpi2RaidPhysDisk0Settings_t;
1710 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1712 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1713 U8 VendorID[8]; /*0x00 */
1714 U8 ProductID[16]; /*0x08 */
1715 U8 ProductRevLevel[4]; /*0x18 */
1716 U8 SerialNum[32]; /*0x1C */
1717 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1718 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1719 Mpi2RaidPhysDisk0InquiryData_t,
1720 *pMpi2RaidPhysDisk0InquiryData_t;
1722 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1723 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1724 U16 DevHandle; /*0x04 */
1725 U8 Reserved1; /*0x06 */
1726 U8 PhysDiskNum; /*0x07 */
1727 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */
1728 U32 Reserved2; /*0x0C */
1729 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */
1730 U32 Reserved3; /*0x4C */
1731 U8 PhysDiskState; /*0x50 */
1732 U8 OfflineReason; /*0x51 */
1733 U8 IncompatibleReason; /*0x52 */
1734 U8 PhysDiskAttributes; /*0x53 */
1735 U32 PhysDiskStatusFlags;/*0x54 */
1736 U64 DeviceMaxLBA; /*0x58 */
1737 U64 HostMaxLBA; /*0x60 */
1738 U64 CoercedMaxLBA; /*0x68 */
1739 U16 BlockSize; /*0x70 */
1740 U16 Reserved5; /*0x72 */
1741 U32 Reserved6; /*0x74 */
1742 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1743 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1744 Mpi2RaidPhysDiskPage0_t,
1745 *pMpi2RaidPhysDiskPage0_t;
1747 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1749 /*PhysDiskState defines */
1750 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1751 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1752 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1753 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1754 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1755 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1756 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1757 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1759 /*OfflineReason defines */
1760 #define MPI2_PHYSDISK0_ONLINE (0x00)
1761 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1762 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1763 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1764 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1765 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1766 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1768 /*IncompatibleReason defines */
1769 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1770 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1771 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1772 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1773 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1774 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1775 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1776 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1778 /*PhysDiskAttributes defines */
1779 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1780 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1781 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1783 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1784 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1785 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1787 /*PhysDiskStatusFlags defines */
1788 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1789 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1790 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1791 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1792 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1793 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1794 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1795 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1798 /*RAID Physical Disk Page 1 */
1801 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1802 *one and check the value returned for NumPhysDiskPaths at runtime.
1804 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1805 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1808 typedef struct _MPI2_RAIDPHYSDISK1_PATH {
1809 U16 DevHandle; /*0x00 */
1810 U16 Reserved1; /*0x02 */
1812 U64 OwnerWWID; /*0x0C */
1813 U8 OwnerIdentifier; /*0x14 */
1814 U8 Reserved2; /*0x15 */
1815 U16 Flags; /*0x16 */
1816 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
1817 Mpi2RaidPhysDisk1Path_t,
1818 *pMpi2RaidPhysDisk1Path_t;
1820 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1821 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1822 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1823 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1825 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
1826 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1827 U8 NumPhysDiskPaths; /*0x04 */
1828 U8 PhysDiskNum; /*0x05 */
1829 U16 Reserved1; /*0x06 */
1830 U32 Reserved2; /*0x08 */
1831 MPI2_RAIDPHYSDISK1_PATH
1832 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */
1833 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1834 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1835 Mpi2RaidPhysDiskPage1_t,
1836 *pMpi2RaidPhysDiskPage1_t;
1838 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1841 /****************************************************************************
1842 * values for fields used by several types of SAS Config Pages
1843 ****************************************************************************/
1845 /*values for NegotiatedLinkRates fields */
1846 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1847 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1848 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1849 /*link rates used for Negotiated Physical and Logical Link Rate */
1850 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1851 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1852 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1853 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1854 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1855 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1856 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1857 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1858 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1859 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1860 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
1863 /*values for AttachedPhyInfo fields */
1864 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1865 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1866 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1868 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1869 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1870 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1871 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1872 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1873 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1874 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1875 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1876 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1877 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1880 /*values for PhyInfo fields */
1881 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1883 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1884 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1885 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1886 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1887 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1889 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1890 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1891 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1892 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1893 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1894 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1896 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1897 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1898 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1899 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1900 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1901 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1902 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1903 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1904 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1905 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1907 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1908 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1909 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1910 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1912 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1913 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1915 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1916 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1917 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1918 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1921 /*values for SAS ProgrammedLinkRate fields */
1922 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1923 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1924 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1925 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1926 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1927 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
1928 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1929 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1930 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1931 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1932 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1933 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
1936 /*values for SAS HwLinkRate fields */
1937 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1938 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1939 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1940 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1941 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
1942 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1943 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1944 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1945 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1946 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
1950 /****************************************************************************
1951 * SAS IO Unit Config Pages
1952 ****************************************************************************/
1954 /*SAS IO Unit Page 0 */
1956 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
1958 U8 PortFlags; /*0x01 */
1959 U8 PhyFlags; /*0x02 */
1960 U8 NegotiatedLinkRate; /*0x03 */
1961 U32 ControllerPhyDeviceInfo;/*0x04 */
1962 U16 AttachedDevHandle; /*0x08 */
1963 U16 ControllerDevHandle; /*0x0A */
1964 U32 DiscoveryStatus; /*0x0C */
1965 U32 Reserved; /*0x10 */
1966 } MPI2_SAS_IO_UNIT0_PHY_DATA,
1967 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1968 Mpi2SasIOUnit0PhyData_t,
1969 *pMpi2SasIOUnit0PhyData_t;
1972 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1973 *one and check the value returned for NumPhys at runtime.
1975 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1976 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1979 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
1980 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
1981 U32 Reserved1;/*0x08 */
1982 U8 NumPhys; /*0x0C */
1983 U8 Reserved2;/*0x0D */
1984 U16 Reserved3;/*0x0E */
1985 MPI2_SAS_IO_UNIT0_PHY_DATA
1986 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */
1987 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1988 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1989 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
1991 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1993 /*values for SAS IO Unit Page 0 PortFlags */
1994 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1995 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1997 /*values for SAS IO Unit Page 0 PhyFlags */
1998 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1999 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
2001 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2003 /*see mpi2_sas.h for values for
2004 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2006 /*values for SAS IO Unit Page 0 DiscoveryStatus */
2007 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2008 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2009 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
2010 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2011 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2012 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2013 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2014 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2015 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2016 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2017 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
2018 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2019 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2020 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2021 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2022 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2023 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2024 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2025 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2026 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
2029 /*SAS IO Unit Page 1 */
2031 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2033 U8 PortFlags; /*0x01 */
2034 U8 PhyFlags; /*0x02 */
2035 U8 MaxMinLinkRate; /*0x03 */
2036 U32 ControllerPhyDeviceInfo; /*0x04 */
2037 U16 MaxTargetPortConnectTime; /*0x08 */
2038 U16 Reserved1; /*0x0A */
2039 } MPI2_SAS_IO_UNIT1_PHY_DATA,
2040 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2041 Mpi2SasIOUnit1PhyData_t,
2042 *pMpi2SasIOUnit1PhyData_t;
2045 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2046 *one and check the value returned for NumPhys at runtime.
2048 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2049 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
2052 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2053 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2055 ControlFlags; /*0x08 */
2057 SASNarrowMaxQueueDepth; /*0x0A */
2059 AdditionalControlFlags; /*0x0C */
2061 SASWideMaxQueueDepth; /*0x0E */
2065 SATAMaxQDepth; /*0x11 */
2067 ReportDeviceMissingDelay; /*0x12 */
2069 IODeviceMissingDelay; /*0x13 */
2070 MPI2_SAS_IO_UNIT1_PHY_DATA
2071 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */
2072 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2073 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2074 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2076 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
2078 /*values for SAS IO Unit Page 1 ControlFlags */
2079 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2080 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2081 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2082 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2084 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2085 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2086 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
2087 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
2088 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
2090 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2091 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2092 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2093 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2094 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2095 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2096 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2097 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2099 /*values for SAS IO Unit Page 1 AdditionalControlFlags */
2100 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2101 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2102 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2103 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2104 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2105 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2106 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2107 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2109 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2110 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2111 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2113 /*values for SAS IO Unit Page 1 PortFlags */
2114 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2116 /*values for SAS IO Unit Page 1 PhyFlags */
2117 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2118 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2120 /*values for SAS IO Unit Page 1 MaxMinLinkRate */
2121 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2122 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2123 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2124 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2125 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
2126 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2127 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2128 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2129 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2130 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
2132 /*see mpi2_sas.h for values for
2133 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2136 /*SAS IO Unit Page 4 */
2138 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2139 U8 MaxTargetSpinup; /*0x00 */
2140 U8 SpinupDelay; /*0x01 */
2141 U8 SpinupFlags; /*0x02 */
2142 U8 Reserved1; /*0x03 */
2143 } MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2144 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2145 Mpi2SasIOUnit4SpinupGroup_t,
2146 *pMpi2SasIOUnit4SpinupGroup_t;
2147 /*defines for SAS IO Unit Page 4 SpinupFlags */
2148 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2152 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2153 *one and check the value returned for NumPhys at runtime.
2155 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2156 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2159 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2160 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */
2161 MPI2_SAS_IOUNIT4_SPINUP_GROUP
2162 SpinupGroupParameters[4]; /*0x08 */
2164 Reserved1; /*0x18 */
2166 Reserved2; /*0x1C */
2168 Reserved3; /*0x20 */
2170 BootDeviceWaitTime; /*0x24 */
2172 Reserved4; /*0x25 */
2174 Reserved5; /*0x26 */
2178 PEInitialSpinupDelay; /*0x29 */
2180 PEReplyDelay; /*0x2A */
2184 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */
2185 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2186 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2187 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2189 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2191 /*defines for Flags field */
2192 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2194 /*defines for PHY field */
2195 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2198 /*SAS IO Unit Page 5 */
2200 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2201 U8 ControlFlags; /*0x00 */
2202 U8 PortWidthModGroup; /*0x01 */
2203 U16 InactivityTimerExponent; /*0x02 */
2204 U8 SATAPartialTimeout; /*0x04 */
2205 U8 Reserved2; /*0x05 */
2206 U8 SATASlumberTimeout; /*0x06 */
2207 U8 Reserved3; /*0x07 */
2208 U8 SASPartialTimeout; /*0x08 */
2209 U8 Reserved4; /*0x09 */
2210 U8 SASSlumberTimeout; /*0x0A */
2211 U8 Reserved5; /*0x0B */
2212 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2213 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2214 Mpi2SasIOUnit5PhyPmSettings_t,
2215 *pMpi2SasIOUnit5PhyPmSettings_t;
2217 /*defines for ControlFlags field */
2218 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2219 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2220 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2221 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2223 /*defines for PortWidthModeGroup field */
2224 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2226 /*defines for InactivityTimerExponent field */
2227 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2228 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2229 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2230 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2231 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2232 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2233 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2234 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2236 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2237 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2238 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2239 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2240 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2241 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2242 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2243 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2246 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2247 *one and check the value returned for NumPhys at runtime.
2249 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2250 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2253 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2254 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2255 U8 NumPhys; /*0x08 */
2256 U8 Reserved1;/*0x09 */
2257 U16 Reserved2;/*0x0A */
2258 U32 Reserved3;/*0x0C */
2259 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2260 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */
2261 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2262 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2263 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2265 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2268 /*SAS IO Unit Page 6 */
2270 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2271 U8 CurrentStatus; /*0x00 */
2272 U8 CurrentModulation; /*0x01 */
2273 U8 CurrentUtilization; /*0x02 */
2274 U8 Reserved1; /*0x03 */
2275 U32 Reserved2; /*0x04 */
2276 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2277 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2278 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2279 *pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2281 /*defines for CurrentStatus field */
2282 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2283 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2284 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2285 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2286 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2287 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2288 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2289 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2291 /*defines for CurrentModulation field */
2292 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2293 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2294 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2295 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2298 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2299 *one and check the value returned for NumGroups at runtime.
2301 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2302 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2305 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2306 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2307 U32 Reserved1; /*0x08 */
2308 U32 Reserved2; /*0x0C */
2309 U8 NumGroups; /*0x10 */
2310 U8 Reserved3; /*0x11 */
2311 U16 Reserved4; /*0x12 */
2312 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2313 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */
2314 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2315 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2316 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2318 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2321 /*SAS IO Unit Page 7 */
2323 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2325 U8 Reserved1; /*0x01 */
2326 U16 Reserved2; /*0x02 */
2327 U8 Threshold75Pct; /*0x04 */
2328 U8 Threshold50Pct; /*0x05 */
2329 U8 Threshold25Pct; /*0x06 */
2330 U8 Reserved3; /*0x07 */
2331 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2332 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2333 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2334 *pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2336 /*defines for Flags field */
2337 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2341 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2342 *one and check the value returned for NumGroups at runtime.
2344 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2345 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2348 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2349 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2350 U8 SamplingInterval; /*0x08 */
2351 U8 WindowLength; /*0x09 */
2352 U16 Reserved1; /*0x0A */
2353 U32 Reserved2; /*0x0C */
2354 U32 Reserved3; /*0x10 */
2355 U8 NumGroups; /*0x14 */
2356 U8 Reserved4; /*0x15 */
2357 U16 Reserved5; /*0x16 */
2358 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2359 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */
2360 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2361 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2362 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2364 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2367 /*SAS IO Unit Page 8 */
2369 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2370 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2373 Reserved1; /*0x08 */
2375 PowerManagementCapabilities; /*0x0C */
2377 TxRxSleepStatus; /*0x10 */
2379 Reserved2; /*0x11 */
2381 Reserved3; /*0x12 */
2382 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2383 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2384 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2386 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2388 /*defines for PowerManagementCapabilities field */
2389 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2390 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2391 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2392 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2393 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2394 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2395 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2396 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2397 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2398 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2400 /*defines for TxRxSleepStatus field */
2401 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00)
2402 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01)
2403 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02)
2404 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03)
2408 /*SAS IO Unit Page 16 */
2410 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2411 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2414 TimeStamp; /*0x08 */
2416 Reserved1; /*0x10 */
2418 Reserved2; /*0x14 */
2420 FastPathPendedRequests; /*0x18 */
2422 FastPathUnPendedRequests; /*0x1C */
2424 FastPathHostRequestStarts; /*0x20 */
2426 FastPathFirmwareRequestStarts; /*0x24 */
2428 FastPathHostCompletions; /*0x28 */
2430 FastPathFirmwareCompletions; /*0x2C */
2432 NonFastPathRequestStarts; /*0x30 */
2434 NonFastPathHostCompletions; /*0x30 */
2435 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2436 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2437 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2439 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2442 /****************************************************************************
2443 * SAS Expander Config Pages
2444 ****************************************************************************/
2446 /*SAS Expander Page 0 */
2448 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2449 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2452 PhysicalPort; /*0x08 */
2454 ReportGenLength; /*0x09 */
2456 EnclosureHandle; /*0x0A */
2458 SASAddress; /*0x0C */
2460 DiscoveryStatus; /*0x14 */
2462 DevHandle; /*0x18 */
2464 ParentDevHandle; /*0x1A */
2466 ExpanderChangeCount; /*0x1C */
2468 ExpanderRouteIndexes; /*0x1E */
2476 STPBusInactivityTimeLimit; /*0x24 */
2478 STPMaxConnectTimeLimit; /*0x26 */
2480 STP_SMP_NexusLossTime; /*0x28 */
2482 MaxNumRoutedSasAddresses; /*0x2A */
2484 ActiveZoneManagerSASAddress;/*0x2C */
2486 ZoneLockInactivityLimit; /*0x34 */
2488 Reserved1; /*0x36 */
2490 TimeToReducedFunc; /*0x38 */
2492 InitialTimeToReducedFunc; /*0x39 */
2494 MaxReducedFuncTime; /*0x3A */
2496 Reserved2; /*0x3B */
2497 } MPI2_CONFIG_PAGE_EXPANDER_0,
2498 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2499 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2501 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2503 /*values for SAS Expander Page 0 DiscoveryStatus field */
2504 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2505 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2506 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2507 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2508 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2509 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2510 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2511 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2512 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2513 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2514 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2515 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2516 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2517 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2518 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2519 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2520 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2521 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2522 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2523 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2525 /*values for SAS Expander Page 0 Flags field */
2526 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2527 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2528 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2529 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2530 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2531 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2532 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2533 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2534 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2535 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2536 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2539 /*SAS Expander Page 1 */
2541 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2542 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2545 PhysicalPort; /*0x08 */
2547 Reserved1; /*0x09 */
2549 Reserved2; /*0x0A */
2555 NumTableEntriesProgrammed; /*0x0E */
2557 ProgrammedLinkRate; /*0x10 */
2559 HwLinkRate; /*0x11 */
2561 AttachedDevHandle; /*0x12 */
2565 AttachedDeviceInfo; /*0x18 */
2567 ExpanderDevHandle; /*0x1C */
2569 ChangeCount; /*0x1E */
2571 NegotiatedLinkRate; /*0x1F */
2573 PhyIdentifier; /*0x20 */
2575 AttachedPhyIdentifier; /*0x21 */
2577 Reserved3; /*0x22 */
2579 DiscoveryInfo; /*0x23 */
2581 AttachedPhyInfo; /*0x24 */
2583 ZoneGroup; /*0x28 */
2585 SelfConfigStatus; /*0x29 */
2587 Reserved4; /*0x2A */
2588 } MPI2_CONFIG_PAGE_EXPANDER_1,
2589 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2590 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2592 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2594 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2596 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2598 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2600 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2601 *used for the AttachedDeviceInfo field */
2603 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2605 /*values for SAS Expander Page 1 DiscoveryInfo field */
2606 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2607 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2608 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2610 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2613 /****************************************************************************
2614 * SAS Device Config Pages
2615 ****************************************************************************/
2617 /*SAS Device Page 0 */
2619 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2620 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2625 EnclosureHandle; /*0x0A */
2627 SASAddress; /*0x0C */
2629 ParentDevHandle; /*0x14 */
2633 AccessStatus; /*0x17 */
2635 DevHandle; /*0x18 */
2637 AttachedPhyIdentifier; /*0x1A */
2639 ZoneGroup; /*0x1B */
2641 DeviceInfo; /*0x1C */
2645 PhysicalPort; /*0x22 */
2647 MaxPortConnections; /*0x23 */
2649 DeviceName; /*0x24 */
2651 PortGroups; /*0x2C */
2655 ControlGroup; /*0x2E */
2657 EnclosureLevel; /*0x2F */
2659 ConnectorName[4]; /*0x30 */
2661 Reserved3; /*0x34 */
2662 } MPI2_CONFIG_PAGE_SAS_DEV_0,
2663 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2664 Mpi2SasDevicePage0_t,
2665 *pMpi2SasDevicePage0_t;
2667 #define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2669 /*values for SAS Device Page 0 AccessStatus field */
2670 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2671 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2672 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2673 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2674 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2675 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2676 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2677 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2678 /*specific values for SATA Init failures */
2679 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2680 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2681 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2682 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2683 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2684 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2685 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2686 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2687 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2688 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2689 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2691 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2693 /*values for SAS Device Page 0 Flags field */
2694 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2695 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2696 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2697 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2698 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2699 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2700 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2701 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2702 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2703 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2704 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2705 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2706 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2707 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2708 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2711 /*SAS Device Page 1 */
2713 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2714 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2717 Reserved1; /*0x08 */
2719 SASAddress; /*0x0C */
2721 Reserved2; /*0x14 */
2723 DevHandle; /*0x18 */
2725 Reserved3; /*0x1A */
2727 InitialRegDeviceFIS[20];/*0x1C */
2728 } MPI2_CONFIG_PAGE_SAS_DEV_1,
2729 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2730 Mpi2SasDevicePage1_t,
2731 *pMpi2SasDevicePage1_t;
2733 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2736 /****************************************************************************
2737 * SAS PHY Config Pages
2738 ****************************************************************************/
2742 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2743 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2746 OwnerDevHandle; /*0x08 */
2748 Reserved1; /*0x0A */
2750 AttachedDevHandle; /*0x0C */
2752 AttachedPhyIdentifier; /*0x0E */
2754 Reserved2; /*0x0F */
2756 AttachedPhyInfo; /*0x10 */
2758 ProgrammedLinkRate; /*0x14 */
2760 HwLinkRate; /*0x15 */
2762 ChangeCount; /*0x16 */
2768 NegotiatedLinkRate; /*0x1C */
2770 Reserved3; /*0x1D */
2772 Reserved4; /*0x1E */
2773 } MPI2_CONFIG_PAGE_SAS_PHY_0,
2774 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2775 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
2777 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2779 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2781 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2783 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2785 /*values for SAS PHY Page 0 Flags field */
2786 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2788 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2790 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2795 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
2796 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2799 Reserved1; /*0x08 */
2801 InvalidDwordCount; /*0x0C */
2803 RunningDisparityErrorCount; /*0x10 */
2805 LossDwordSynchCount; /*0x14 */
2807 PhyResetProblemCount; /*0x18 */
2808 } MPI2_CONFIG_PAGE_SAS_PHY_1,
2809 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2810 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
2812 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2817 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2818 U8 PhyEventCode; /*0x00 */
2819 U8 Reserved1; /*0x01 */
2820 U16 Reserved2; /*0x02 */
2821 U32 PhyEventInfo; /*0x04 */
2822 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
2823 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
2825 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2829 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2830 *one and check the value returned for NumPhyEvents at runtime.
2832 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2833 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2836 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2837 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2840 Reserved1; /*0x08 */
2842 NumPhyEvents; /*0x0C */
2844 Reserved2; /*0x0D */
2846 Reserved3; /*0x0E */
2847 MPI2_SASPHY2_PHY_EVENT
2848 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */
2849 } MPI2_CONFIG_PAGE_SAS_PHY_2,
2850 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2852 *pMpi2SasPhyPage2_t;
2854 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2859 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2860 U8 PhyEventCode; /*0x00 */
2861 U8 Reserved1; /*0x01 */
2862 U16 Reserved2; /*0x02 */
2863 U8 CounterType; /*0x04 */
2864 U8 ThresholdWindow; /*0x05 */
2865 U8 TimeUnits; /*0x06 */
2866 U8 Reserved3; /*0x07 */
2867 U32 EventThreshold; /*0x08 */
2868 U16 ThresholdFlags; /*0x0C */
2869 U16 Reserved4; /*0x0E */
2870 } MPI2_SASPHY3_PHY_EVENT_CONFIG,
2871 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2872 Mpi2SasPhy3PhyEventConfig_t,
2873 *pMpi2SasPhy3PhyEventConfig_t;
2875 /*values for PhyEventCode field */
2876 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2877 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2878 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2879 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2880 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2881 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2882 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2883 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2884 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2885 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2886 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2887 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2888 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2889 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2890 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2891 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2892 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2893 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2894 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2895 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2896 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2897 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2898 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2899 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2900 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2901 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2902 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2903 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2904 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2905 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2906 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2907 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2908 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2909 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2910 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2911 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2912 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2914 /*values for the CounterType field */
2915 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2916 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2917 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2919 /*values for the TimeUnits field */
2920 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2921 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2922 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2923 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2925 /*values for the ThresholdFlags field */
2926 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2927 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2930 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2931 *one and check the value returned for NumPhyEvents at runtime.
2933 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2934 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2937 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2938 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2941 Reserved1; /*0x08 */
2943 NumPhyEvents; /*0x0C */
2945 Reserved2; /*0x0D */
2947 Reserved3; /*0x0E */
2948 MPI2_SASPHY3_PHY_EVENT_CONFIG
2949 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */
2950 } MPI2_CONFIG_PAGE_SAS_PHY_3,
2951 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2952 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
2954 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2959 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2960 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2963 Reserved1; /*0x08 */
2965 Reserved2; /*0x0A */
2969 InitialFrame[28]; /*0x0C */
2970 } MPI2_CONFIG_PAGE_SAS_PHY_4,
2971 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2972 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
2974 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2976 /*values for the Flags field */
2977 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2978 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2983 /****************************************************************************
2984 * SAS Port Config Pages
2985 ****************************************************************************/
2987 /*SAS Port Page 0 */
2989 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
2990 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2993 PortNumber; /*0x08 */
2995 PhysicalPort; /*0x09 */
2997 PortWidth; /*0x0A */
2999 PhysicalPortWidth; /*0x0B */
3001 ZoneGroup; /*0x0C */
3003 Reserved1; /*0x0D */
3005 Reserved2; /*0x0E */
3007 SASAddress; /*0x10 */
3009 DeviceInfo; /*0x18 */
3011 Reserved3; /*0x1C */
3013 Reserved4; /*0x20 */
3014 } MPI2_CONFIG_PAGE_SAS_PORT_0,
3015 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3016 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
3018 #define MPI2_SASPORT0_PAGEVERSION (0x00)
3020 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3023 /****************************************************************************
3024 * SAS Enclosure Config Pages
3025 ****************************************************************************/
3027 /*SAS Enclosure Page 0 */
3029 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3030 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3033 Reserved1; /*0x08 */
3035 EnclosureLogicalID; /*0x0C */
3039 EnclosureHandle; /*0x16 */
3043 StartSlot; /*0x1A */
3045 Reserved2; /*0x1C */
3047 EnclosureLevel; /*0x1D */
3049 SEPDevHandle; /*0x1E */
3051 Reserved3; /*0x20 */
3053 Reserved4; /*0x24 */
3054 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3055 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3056 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t;
3058 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
3060 /*values for SAS Enclosure Page 0 Flags field */
3061 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3062 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3063 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3064 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3065 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3066 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3067 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3068 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3071 /****************************************************************************
3073 ****************************************************************************/
3078 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3079 *one and check the value returned for NumLogEntries at runtime.
3081 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3082 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
3085 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
3087 typedef struct _MPI2_LOG_0_ENTRY {
3088 U64 TimeStamp; /*0x00 */
3089 U32 Reserved1; /*0x08 */
3090 U16 LogSequence; /*0x0C */
3091 U16 LogEntryQualifier; /*0x0E */
3094 U16 Reserved2; /*0x12 */
3096 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3097 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3098 Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3100 /*values for Log Page 0 LogEntry LogEntryQualifier field */
3101 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3102 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3103 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
3104 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
3105 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
3107 typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3108 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3109 U32 Reserved1; /*0x08 */
3110 U32 Reserved2; /*0x0C */
3111 U16 NumLogEntries;/*0x10 */
3112 U16 Reserved3; /*0x12 */
3114 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */
3115 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3116 Mpi2LogPage0_t, *pMpi2LogPage0_t;
3118 #define MPI2_LOG_0_PAGEVERSION (0x02)
3121 /****************************************************************************
3123 ****************************************************************************/
3128 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3129 *one and check the value returned for NumElements at runtime.
3131 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3132 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
3135 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3136 U16 ElementFlags; /*0x00 */
3137 U16 VolDevHandle; /*0x02 */
3138 U8 HotSparePool; /*0x04 */
3139 U8 PhysDiskNum; /*0x05 */
3140 U16 PhysDiskDevHandle; /*0x06 */
3141 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3142 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3143 Mpi2RaidConfig0ConfigElement_t,
3144 *pMpi2RaidConfig0ConfigElement_t;
3146 /*values for the ElementFlags field */
3147 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
3148 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
3149 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
3150 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
3151 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
3154 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3155 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3156 U8 NumHotSpares; /*0x08 */
3157 U8 NumPhysDisks; /*0x09 */
3158 U8 NumVolumes; /*0x0A */
3159 U8 ConfigNum; /*0x0B */
3160 U32 Flags; /*0x0C */
3161 U8 ConfigGUID[24]; /*0x10 */
3162 U32 Reserved1; /*0x28 */
3163 U8 NumElements; /*0x2C */
3164 U8 Reserved2; /*0x2D */
3165 U16 Reserved3; /*0x2E */
3166 MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3167 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */
3168 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3169 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3170 Mpi2RaidConfigurationPage0_t,
3171 *pMpi2RaidConfigurationPage0_t;
3173 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
3175 /*values for RAID Configuration Page 0 Flags field */
3176 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
3179 /****************************************************************************
3180 * Driver Persistent Mapping Config Pages
3181 ****************************************************************************/
3183 /*Driver Persistent Mapping Page 0 */
3185 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3186 U64 PhysicalIdentifier; /*0x00 */
3187 U16 MappingInformation; /*0x08 */
3188 U16 DeviceIndex; /*0x0A */
3189 U32 PhysicalBitsMapping; /*0x0C */
3190 U32 Reserved1; /*0x10 */
3191 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3192 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3193 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3195 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3196 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3197 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */
3198 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3199 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3200 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3202 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
3204 /*values for Driver Persistent Mapping Page 0 MappingInformation field */
3205 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
3206 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
3207 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
3210 /****************************************************************************
3211 * Ethernet Config Pages
3212 ****************************************************************************/
3214 /*Ethernet Page 0 */
3216 /*IP address (union of IPv4 and IPv6) */
3217 typedef union _MPI2_ETHERNET_IP_ADDR {
3220 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3221 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3223 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
3225 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3226 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3227 U8 NumInterfaces; /*0x08 */
3228 U8 Reserved0; /*0x09 */
3229 U16 Reserved1; /*0x0A */
3230 U32 Status; /*0x0C */
3231 U8 MediaState; /*0x10 */
3232 U8 Reserved2; /*0x11 */
3233 U16 Reserved3; /*0x12 */
3234 U8 MacAddress[6]; /*0x14 */
3235 U8 Reserved4; /*0x1A */
3236 U8 Reserved5; /*0x1B */
3237 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */
3238 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */
3239 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */
3240 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */
3241 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */
3242 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */
3244 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3245 } MPI2_CONFIG_PAGE_ETHERNET_0,
3246 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3247 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3249 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
3251 /*values for Ethernet Page 0 Status field */
3252 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
3253 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
3254 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
3255 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
3256 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
3257 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
3258 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
3259 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
3260 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
3261 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
3262 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
3263 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
3265 /*values for Ethernet Page 0 MediaState field */
3266 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
3267 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
3268 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
3270 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
3271 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
3272 #define MPI2_ETHPG0_MS_10MBIT (0x01)
3273 #define MPI2_ETHPG0_MS_100MBIT (0x02)
3274 #define MPI2_ETHPG0_MS_1GBIT (0x03)
3277 /*Ethernet Page 1 */
3279 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3280 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3283 Reserved0; /*0x08 */
3287 MediaState; /*0x10 */
3289 Reserved1; /*0x11 */
3291 Reserved2; /*0x12 */
3293 MacAddress[6]; /*0x14 */
3295 Reserved3; /*0x1A */
3297 Reserved4; /*0x1B */
3298 MPI2_ETHERNET_IP_ADDR
3299 StaticIpAddress; /*0x1C */
3300 MPI2_ETHERNET_IP_ADDR
3301 StaticSubnetMask; /*0x2C */
3302 MPI2_ETHERNET_IP_ADDR
3303 StaticGatewayIpAddress; /*0x3C */
3304 MPI2_ETHERNET_IP_ADDR
3305 StaticDNS1IpAddress; /*0x4C */
3306 MPI2_ETHERNET_IP_ADDR
3307 StaticDNS2IpAddress; /*0x5C */
3309 Reserved5; /*0x6C */
3311 Reserved6; /*0x70 */
3313 Reserved7; /*0x74 */
3315 Reserved8; /*0x78 */
3317 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3318 } MPI2_CONFIG_PAGE_ETHERNET_1,
3319 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3320 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3322 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3324 /*values for Ethernet Page 1 Flags field */
3325 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3326 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3327 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3328 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3329 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3330 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3331 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3332 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3333 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3335 /*values for Ethernet Page 1 MediaState field */
3336 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3337 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3338 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3340 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3341 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3342 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3343 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3344 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3347 /****************************************************************************
3348 * Extended Manufacturing Config Pages
3349 ****************************************************************************/
3352 *Generic structure to use for product-specific extended manufacturing pages
3353 *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3357 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3358 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3361 ProductSpecificInfo; /*0x08 */
3362 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3363 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3364 Mpi2ExtManufacturingPagePS_t,
3365 *pMpi2ExtManufacturingPagePS_t;
3367 /*PageVersion should be provided by product-specific code */
projects / karo-tx-linux.git / blob